| /external/tensorflow/tensorflow/python/autograph/operators/ |
| D | logical.py | 39 def and_(a, b): function
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| /external/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 473 __ and_(r5, r5, 0x1f); in Generate_3() local
481 __ and_(r0, r0, 0x1f); in Generate_3() local
489 __ and_(r1, r1, 0x1f); in Generate_3() local
890 __ and_(r3, r3, 0x1f); in Generate_6() local
1072 __ and_(r3, r8, 0x1f); in Generate_8() local
2474 __ and_(r3, r6, 0x1f); in Generate_19() local
2667 __ and_(r2, r2, 0x1f); in Generate_21() local
2671 __ and_(r2, r2, 0x1f); in Generate_21() local
2840 __ and_(lr, r3, 0x1f); in Generate_22() local
2848 __ and_(r0, r0, 0x1f); in Generate_22() local
[all …]
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| /external/OpenCL-CTS/test_conformance/subgroups/ |
| D | subhelpers.h | 265 and_, enumerator
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| /external/python/cpython3/Lib/ |
| D | operator.py | 79 def and_(a, b): function
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| /external/XNNPACK/src/jit/ |
| D | aarch32-assembler.cc | 98 void Assembler::and_(CoreRegister rd, CoreRegister rn, uint8_t imm) { in and_() function in xnnpack::aarch32::Assembler
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| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 115 __ and_(z12.VnD(), p5.Merging(), z12.VnD(), z12.VnD()); in TEST() local
686 __ and_(z25.VnB(), p4.Merging(), z25.VnB(), z27.VnB()); in TEST() local
1098 __ and_(z31.VnS(), z31.VnS(), 4); in TEST() local
1350 __ and_(z8.VnS(), p3.Merging(), z8.VnS(), z31.VnS()); in TEST() local
1353 __ and_(z20.VnS(), z20.VnS(), 4); in TEST() local
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| D | test-trace-aarch64.cc | 65 __ and_(w27, w28, w29); in GenerateTestSequenceBase() local
66 __ and_(x2, x3, x4); in GenerateTestSequenceBase() local
651 __ and_(v10.V16B(), v8.V16B(), v27.V16B()); in GenerateTestSequenceNEON() local
652 __ and_(v5.V8B(), v1.V8B(), v16.V8B()); in GenerateTestSequenceNEON() local
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| D | test-assembler-aarch64.cc | 616 TEST(and_) { in TEST() argument
7339 __ and_(xzr, x0, x2); in TEST() local
7340 __ and_(xzr, x2, xzr); in TEST() local
7341 __ and_(xzr, xzr, x2); in TEST() local
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| /external/python/cpython2/Lib/plat-mac/lib-scriptpackages/StdSuites/ |
| D | AppleScript_Suite.py | 282 def and_(self, _object, _attributes={}, **_arguments): member in AppleScript_Suite_Events
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| /external/tensorflow/tensorflow/python/ops/ |
| D | math_ops.py | 1842 def and_(x, y, name=None): function
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 413 void AssemblerMIPS32::and_(const Operand *OpRd, const Operand *OpRs, in and_() function in Ice::MIPS32::AssemblerMIPS32
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| D | IceAssemblerARM32.cpp | 1361 void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn, in and_() function in Ice::ARM32::AssemblerARM32
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| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in and_() function in vixl::aarch64::Assembler
130 void Assembler::and_(const ZRegister& zd, in and_() function in vixl::aarch64::Assembler
2350 void Assembler::and_(const ZRegister& zd, in and_() function in vixl::aarch64::Assembler
6101 void Assembler::and_(const PRegisterWithLaneSize& pd, in and_() function in vixl::aarch64::Assembler
|
| D | assembler-aarch64.cc | 581 void Assembler::and_(const Register& rd, in and_() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 1012 LogicVRegister Simulator::and_(VectorFormat vform, in and_() function in vixl::aarch64::Simulator
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 1979 void and_(Register rd, Register rn, const Operand& operand) { in and_() function
1982 void and_(Condition cond, Register rd, Register rn, const Operand& operand) { in and_() function
1985 void and_(EncodingSize size, in and_() function
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| D | assembler-aarch32.cc | 2697 void Assembler::and_(Condition cond, in and_() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 1217 void Disassembler::and_(Condition cond, in and_() function in vixl::aarch32::Disassembler
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 507 TEST(and_) { in TEST() argument
|