1{ 2 "arch": "common_x86", 3 "insns": [ 4 { 5 "encodings": { 6 "Adcb": { "opcodes": [ "80", "2" ] }, 7 "Rclb": { "opcodes": [ "C0", "2" ] }, 8 "Rcrb": { "opcodes": [ "C0", "3" ] }, 9 "Sbbb": { "opcodes": [ "80", "3" ] } 10 }, 11 "args": [ 12 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 13 { "class": "Imm8" }, 14 { "class": "FLAGS", "usage": "use_def" } 15 ] 16 }, 17 { 18 "encodings": { 19 "Adcb": { "opcodes": [ "12" ] }, 20 "Sbbb": { "opcodes": [ "1A" ] } 21 }, 22 "args": [ 23 { "class": "GeneralReg8", "usage": "use_def" }, 24 { "class": "Mem8", "usage": "use" }, 25 { "class": "FLAGS", "usage": "use_def" } 26 ] 27 }, 28 { 29 "encodings": { 30 "Adcb": { "opcodes": [ "10" ], "reg_to_rm": true }, 31 "Sbbb": { "opcodes": [ "18" ], "reg_to_rm": true } 32 }, 33 "args": [ 34 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 35 { "class": "GeneralReg8", "usage": "use" }, 36 { "class": "FLAGS", "usage": "use_def" } 37 ] 38 }, 39 { 40 "encodings": { 41 "AdcbAccumulator": { "opcodes": [ "14" ] }, 42 "SbbbAccumulator": { "opcodes": [ "1C" ] } 43 }, 44 "args": [ 45 { "class": "AL", "usage": "use_def" }, 46 { "class": "Imm8" }, 47 { "class": "FLAGS", "usage": "use_def" } 48 ] 49 }, 50 { 51 "encodings": { 52 "Adcl": { "opcodes": [ "13" ] }, 53 "Sbbl": { "opcodes": [ "1B" ] } 54 }, 55 "args": [ 56 { "class": "GeneralReg32", "usage": "use_def" }, 57 { "class": "Mem32", "usage": "use" }, 58 { "class": "FLAGS", "usage": "use_def" } 59 ] 60 }, 61 { 62 "encodings": { 63 "Adcl": { "opcodes": [ "81", "2" ] }, 64 "Sbbl": { "opcodes": [ "81", "3" ] } 65 }, 66 "args": [ 67 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 68 { "class": "Imm32" }, 69 { "class": "FLAGS", "usage": "use_def" } 70 ] 71 }, 72 { 73 "encodings": { 74 "Adcl": { "opcodes": [ "11" ], "reg_to_rm": true }, 75 "Sbbl": { "opcodes": [ "19" ], "reg_to_rm": true } 76 }, 77 "args": [ 78 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 79 { "class": "GeneralReg32", "usage": "use" }, 80 { "class": "FLAGS", "usage": "use_def" } 81 ] 82 }, 83 { 84 "encodings": { 85 "AdclAccumulator": { "opcodes": [ "15" ] }, 86 "SbblAccumulator": { "opcodes": [ "1D" ] } 87 }, 88 "args": [ 89 { "class": "EAX", "usage": "use_def" }, 90 { "class": "Imm32" }, 91 { "class": "FLAGS", "usage": "use_def" } 92 ] 93 }, 94 { 95 "encodings": { 96 "AdclImm8": { "opcodes": [ "83", "2" ] }, 97 "Rcll": { "opcodes": [ "C1", "2" ] }, 98 "Rcrl": { "opcodes": [ "C1", "3" ] }, 99 "SbblImm8": { "opcodes": [ "83", "3" ] } 100 }, 101 "args": [ 102 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 103 { "class": "Imm8" }, 104 { "class": "FLAGS", "usage": "use_def" } 105 ] 106 }, 107 { 108 "encodings": { 109 "Adcw": { "opcodes": [ "66", "13" ] }, 110 "Sbbw": { "opcodes": [ "66", "1B" ] } 111 }, 112 "args": [ 113 { "class": "GeneralReg16", "usage": "use_def" }, 114 { "class": "Mem16", "usage": "use" }, 115 { "class": "FLAGS", "usage": "use_def" } 116 ] 117 }, 118 { 119 "encodings": { 120 "Adcw": { "opcodes": [ "66", "81", "2" ] }, 121 "Sbbw": { "opcodes": [ "66", "81", "3" ] } 122 }, 123 "args": [ 124 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 125 { "class": "Imm16" }, 126 { "class": "FLAGS", "usage": "use_def" } 127 ] 128 }, 129 { 130 "encodings": { 131 "Adcw": { "opcodes": [ "66", "11" ], "reg_to_rm": true }, 132 "Sbbw": { "opcodes": [ "66", "19" ], "reg_to_rm": true } 133 }, 134 "args": [ 135 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 136 { "class": "GeneralReg16", "usage": "use" }, 137 { "class": "FLAGS", "usage": "use_def" } 138 ] 139 }, 140 { 141 "encodings": { 142 "AdcwAccumulator": { "opcodes": [ "66", "15" ] }, 143 "SbbwAccumulator": { "opcodes": [ "66", "1D" ] } 144 }, 145 "args": [ 146 { "class": "AX", "usage": "use_def" }, 147 { "class": "Imm16" }, 148 { "class": "FLAGS", "usage": "use_def" } 149 ] 150 }, 151 { 152 "encodings": { 153 "AdcwImm8": { "opcodes": [ "66", "83", "2" ] }, 154 "Rclw": { "opcodes": [ "66", "C1", "2" ] }, 155 "Rcrw": { "opcodes": [ "66", "C1", "3" ] }, 156 "SbbwImm8": { "opcodes": [ "66", "83", "3" ] } 157 }, 158 "args": [ 159 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 160 { "class": "Imm8" }, 161 { "class": "FLAGS", "usage": "use_def" } 162 ] 163 }, 164 { 165 "encodings": { 166 "Addb": { "opcodes": [ "80", "0" ] }, 167 "Andb": { "opcodes": [ "80", "4" ] }, 168 "Orb": { "opcodes": [ "80", "1" ] }, 169 "Rolb": { "opcodes": [ "C0", "0" ] }, 170 "Rorb": { "opcodes": [ "C0", "1" ] }, 171 "Sarb": { "opcodes": [ "C0", "7" ] }, 172 "Shlb": { "opcodes": [ "C0", "4" ] }, 173 "Shrb": { "opcodes": [ "C0", "5" ] }, 174 "Subb": { "opcodes": [ "80", "5" ] }, 175 "Xorb": { "opcodes": [ "80", "6" ] } 176 }, 177 "args": [ 178 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 179 { "class": "Imm8" }, 180 { "class": "FLAGS", "usage": "def" } 181 ] 182 }, 183 { 184 "encodings": { 185 "Addb": { "opcodes": [ "02" ] }, 186 "Andb": { "opcodes": [ "22" ] }, 187 "Orb": { "opcodes": [ "0A" ] }, 188 "Subb": { "opcodes": [ "2A" ] }, 189 "Xorb": { "opcodes": [ "32" ] } 190 }, 191 "args": [ 192 { "class": "GeneralReg8", "usage": "use_def" }, 193 { "class": "Mem8", "usage": "use" }, 194 { "class": "FLAGS", "usage": "def" } 195 ] 196 }, 197 { 198 "encodings": { 199 "Addb": { "opcodes": [ "00" ], "reg_to_rm": true }, 200 "Andb": { "opcodes": [ "20" ], "reg_to_rm": true }, 201 "Orb": { "opcodes": [ "08" ], "reg_to_rm": true }, 202 "Subb": { "opcodes": [ "28" ], "reg_to_rm": true }, 203 "Xorb": { "opcodes": [ "30" ], "reg_to_rm": true } 204 }, 205 "args": [ 206 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 207 { "class": "GeneralReg8", "usage": "use" }, 208 { "class": "FLAGS", "usage": "def" } 209 ] 210 }, 211 { 212 "encodings": { 213 "AddbAccumulator": { "opcodes": [ "04" ] }, 214 "AndbAccumulator": { "opcodes": [ "24" ] }, 215 "OrbAccumulator": { "opcodes": [ "0C" ] }, 216 "SubbAccumulator": { "opcodes": [ "2C" ] }, 217 "XorbAccumulator": { "opcodes": [ "34" ] } 218 }, 219 "args": [ 220 { "class": "AL", "usage": "use_def" }, 221 { "class": "Imm8" }, 222 { "class": "FLAGS", "usage": "def" } 223 ] 224 }, 225 { 226 "encodings": { 227 "Addl": { "opcodes": [ "01" ], "reg_to_rm": true }, 228 "Andl": { "opcodes": [ "21" ], "reg_to_rm": true }, 229 "Btcl": { "opcodes": [ "0F", "BB" ], "reg_to_rm": true }, 230 "Btrl": { "opcodes": [ "0F", "B3" ], "reg_to_rm": true }, 231 "Btsl": { "opcodes": [ "0F", "AB" ], "reg_to_rm": true }, 232 "Orl": { "opcodes": [ "09" ], "reg_to_rm": true }, 233 "Subl": { "opcodes": [ "29" ], "reg_to_rm": true }, 234 "Xorl": { "opcodes": [ "31" ], "reg_to_rm": true } 235 }, 236 "args": [ 237 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 238 { "class": "GeneralReg32", "usage": "use" }, 239 { "class": "FLAGS", "usage": "def" } 240 ] 241 }, 242 { 243 "encodings": { 244 "Addl": { "opcodes": [ "03" ] }, 245 "Andl": { "opcodes": [ "23" ] }, 246 "Orl": { "opcodes": [ "0B" ] }, 247 "Subl": { "opcodes": [ "2B" ] }, 248 "Xorl": { "opcodes": [ "33" ] } 249 }, 250 "args": [ 251 { "class": "GeneralReg32", "usage": "use_def" }, 252 { "class": "Mem32", "usage": "use" }, 253 { "class": "FLAGS", "usage": "def" } 254 ] 255 }, 256 { 257 "encodings": { 258 "Addl": { "opcodes": [ "81", "0" ] }, 259 "Andl": { "opcodes": [ "81", "4" ] }, 260 "Orl": { "opcodes": [ "81", "1" ] }, 261 "Subl": { "opcodes": [ "81", "5" ] }, 262 "Xorl": { "opcodes": [ "81", "6" ] } 263 }, 264 "args": [ 265 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 266 { "class": "Imm32" }, 267 { "class": "FLAGS", "usage": "def" } 268 ] 269 }, 270 { 271 "encodings": { 272 "AddlAccumulator": { "opcodes": [ "05" ] }, 273 "AndlAccumulator": { "opcodes": [ "25" ] }, 274 "OrlAccumulator": { "opcodes": [ "0D" ] }, 275 "SublAccumulator": { "opcodes": [ "2D" ] }, 276 "XorlAccumulator": { "opcodes": [ "35" ] } 277 }, 278 "args": [ 279 { "class": "EAX", "usage": "use_def" }, 280 { "class": "Imm32" }, 281 { "class": "FLAGS", "usage": "def" } 282 ] 283 }, 284 { 285 "encodings": { 286 "AddlImm8": { "opcodes": [ "83", "0" ] }, 287 "AndlImm8": { "opcodes": [ "83", "4" ] }, 288 "Btcl": { "opcodes": [ "0F", "BA", "7" ] }, 289 "Btl": { "opcodes": [ "0F", "BA", "4" ] }, 290 "Btrl": { "opcodes": [ "0F", "BA", "6" ] }, 291 "Btsl": { "opcodes": [ "0F", "BA", "5" ] }, 292 "OrlImm8": { "opcodes": [ "83", "1" ] }, 293 "Roll": { "opcodes": [ "C1", "0" ] }, 294 "Rorl": { "opcodes": [ "C1", "1" ] }, 295 "Sarl": { "opcodes": [ "C1", "7" ] }, 296 "Shll": { "opcodes": [ "C1", "4" ] }, 297 "Shrl": { "opcodes": [ "C1", "5" ] }, 298 "SublImm8": { "opcodes": [ "83", "5" ] }, 299 "XorlImm8": { "opcodes": [ "83", "6" ] } 300 }, 301 "args": [ 302 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 303 { "class": "Imm8" }, 304 { "class": "FLAGS", "usage": "def" } 305 ] 306 }, 307 { 308 "encodings": { 309 "Addpd": { "opcodes": [ "66", "0F", "58" ] }, 310 "Addps": { "opcodes": [ "0F", "58" ] }, 311 "Andpd": { "opcodes": [ "66", "0F", "54" ] }, 312 "Andps": { "opcodes": [ "0F", "54" ] }, 313 "Cmpeqpd": { "opcodes": [ "66", "0F", "C2", "00" ] }, 314 "Cmpeqps": { "opcodes": [ "0F", "C2", "00" ] }, 315 "Cmplepd": { "opcodes": [ "66", "0F", "C2", "02" ] }, 316 "Cmpleps": { "opcodes": [ "0F", "C2", "02" ] }, 317 "Cmpltpd": { "opcodes": [ "66", "0F", "C2", "01" ] }, 318 "Cmpltps": { "opcodes": [ "0F", "C2", "01" ] }, 319 "Cmpneqpd": { "opcodes": [ "66", "0F", "C2", "04" ] }, 320 "Cmpneqps": { "opcodes": [ "0F", "C2", "04" ] }, 321 "Cmpnlepd": { "opcodes": [ "66", "0F", "C2", "06" ] }, 322 "Cmpnleps": { "opcodes": [ "0F", "C2", "06" ] }, 323 "Cmpnltpd": { "opcodes": [ "66", "0F", "C2", "05" ] }, 324 "Cmpnltps": { "opcodes": [ "0F", "C2", "05" ] }, 325 "Cmpordpd": { "opcodes": [ "66", "0F", "C2", "07" ] }, 326 "Cmpordps": { "opcodes": [ "0F", "C2", "07" ] }, 327 "Cmpunordpd": { "opcodes": [ "66", "0F", "C2", "03" ] }, 328 "Cmpunordps": { "opcodes": [ "0F", "C2", "03" ] }, 329 "Divpd": { "opcodes": [ "66", "0F", "5E" ] }, 330 "Divps": { "opcodes": [ "0F", "5E" ] }, 331 "Haddpd": { "feature": "SSE3", "opcodes": [ "66", "0F", "7C" ] }, 332 "Haddps": { "feature": "SSE3", "opcodes": [ "F2", "0F", "7C" ] }, 333 "Maxpd": { "opcodes": [ "66", "0F", "5F" ] }, 334 "Maxps": { "opcodes": [ "0F", "5F" ] }, 335 "Minpd": { "opcodes": [ "66", "0F", "5D" ] }, 336 "Minps": { "opcodes": [ "0F", "5D" ] }, 337 "Mulpd": { "opcodes": [ "66", "0F", "59" ] }, 338 "Mulps": { "opcodes": [ "0F", "59" ] }, 339 "Orpd": { "opcodes": [ "66", "0F", "56" ] }, 340 "Orps": { "opcodes": [ "0F", "56" ] }, 341 "Packssdw": { "opcodes": [ "66", "0F", "6B" ] }, 342 "Packsswb": { "opcodes": [ "66", "0F", "63" ] }, 343 "Packusdw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "2B" ] }, 344 "Packuswb": { "opcodes": [ "66", "0F", "67" ] }, 345 "Paddb": { "opcodes": [ "66", "0F", "FC" ] }, 346 "Paddd": { "opcodes": [ "66", "0F", "FE" ] }, 347 "Paddq": { "opcodes": [ "66", "0F", "D4" ] }, 348 "Paddsb": { "opcodes": [ "66", "0F", "EC" ] }, 349 "Paddsw": { "opcodes": [ "66", "0F", "ED" ] }, 350 "Paddusb": { "opcodes": [ "66", "0F", "DC" ] }, 351 "Paddusw": { "opcodes": [ "66", "0F", "DD" ] }, 352 "Paddw": { "opcodes": [ "66", "0F", "FD" ] }, 353 "Pand": { "opcodes": [ "66", "0F", "DB" ] }, 354 "Pandn": { "opcodes": [ "66", "0F", "DF" ] }, 355 "Pavgb": { "opcodes": [ "66", "0F", "E0" ] }, 356 "Pavgw": { "opcodes": [ "66", "0F", "E3" ] }, 357 "Pcmpeqb": { "opcodes": [ "66", "0F", "74" ] }, 358 "Pcmpeqd": { "opcodes": [ "66", "0F", "76" ] }, 359 "Pcmpeqq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "29" ] }, 360 "Pcmpeqw": { "opcodes": [ "66", "0F", "75" ] }, 361 "Pcmpgtb": { "opcodes": [ "66", "0F", "64" ] }, 362 "Pcmpgtd": { "opcodes": [ "66", "0F", "66" ] }, 363 "Pcmpgtq": { "feature": "SSE4_2", "opcodes": [ "66", "0F", "38", "37" ] }, 364 "Pcmpgtw": { "opcodes": [ "66", "0F", "65" ] }, 365 "Phaddd": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "02" ] }, 366 "Phaddw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "01" ] }, 367 "Pmaxsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3C" ] }, 368 "Pmaxsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3D" ] }, 369 "Pmaxsw": { "opcodes": [ "66", "0F", "EE" ] }, 370 "Pmaxub": { "opcodes": [ "66", "0F", "DE" ] }, 371 "Pmaxud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3F" ] }, 372 "Pmaxuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3E" ] }, 373 "Pminsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "38" ] }, 374 "Pminsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "39" ] }, 375 "Pminsw": { "opcodes": [ "66", "0F", "EA" ] }, 376 "Pminub": { "opcodes": [ "66", "0F", "DA" ] }, 377 "Pminud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3B" ] }, 378 "Pminuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3A" ] }, 379 "Pmulhrsw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "0B" ] }, 380 "Pmulhw": { "opcodes": [ "66", "0F", "E5" ] }, 381 "Pmulld": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "40" ] }, 382 "Pmullw": { "opcodes": [ "66", "0F", "D5" ] }, 383 "Pmuludq": { "opcodes": [ "66", "0F", "F4" ] }, 384 "Por": { "opcodes": [ "66", "0F", "EB" ] }, 385 "Psadbw": { "opcodes": [ "66", "0F", "F6" ] }, 386 "Pshufb": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "00" ] }, 387 "Pslld": { "opcodes": [ "66", "0F", "F2" ] }, 388 "Psllq": { "opcodes": [ "66", "0F", "F3" ] }, 389 "Psllw": { "opcodes": [ "66", "0F", "F1" ] }, 390 "Psrad": { "opcodes": [ "66", "0F", "E2" ] }, 391 "Psraw": { "opcodes": [ "66", "0F", "E1" ] }, 392 "Psrld": { "opcodes": [ "66", "0F", "D2" ] }, 393 "Psrlq": { "opcodes": [ "66", "0F", "D3" ] }, 394 "Psrlw": { "opcodes": [ "66", "0F", "D1" ] }, 395 "Psubb": { "opcodes": [ "66", "0F", "F8" ] }, 396 "Psubd": { "opcodes": [ "66", "0F", "FA" ] }, 397 "Psubq": { "opcodes": [ "66", "0F", "FB" ] }, 398 "Psubsb": { "opcodes": [ "66", "0F", "E8" ] }, 399 "Psubsw": { "opcodes": [ "66", "0F", "E9" ] }, 400 "Psubusb": { "opcodes": [ "66", "0F", "D8" ] }, 401 "Psubusw": { "opcodes": [ "66", "0F", "D9" ] }, 402 "Psubw": { "opcodes": [ "66", "0F", "F9" ] }, 403 "Punpckhbw": { "opcodes": [ "66", "0F", "68" ] }, 404 "Punpckhdq": { "opcodes": [ "66", "0F", "6A" ] }, 405 "Punpckhqdq": { "opcodes": [ "66", "0F", "6D" ] }, 406 "Punpckhwd": { "opcodes": [ "66", "0F", "69" ] }, 407 "Punpcklbw": { "opcodes": [ "66", "0F", "60" ] }, 408 "Punpckldq": { "opcodes": [ "66", "0F", "62" ] }, 409 "Punpcklqdq": { "opcodes": [ "66", "0F", "6C" ] }, 410 "Punpcklwd": { "opcodes": [ "66", "0F", "61" ] }, 411 "Pxor": { "opcodes": [ "66", "0F", "EF" ] }, 412 "Rsqrtps": { "opcodes": [ "0F", "52" ] }, 413 "Subpd": { "opcodes": [ "66", "0F", "5C" ] }, 414 "Subps": { "opcodes": [ "0F", "5C" ] }, 415 "Vrsqrtps": { "opcodes": [ "C4", "01", "00", "52" ] }, 416 "Xorpd": { "opcodes": [ "66", "0F", "57" ] }, 417 "Xorps": { "opcodes": [ "0F", "57" ] } 418 }, 419 "args": [ 420 { "class": "VecReg128", "usage": "use_def" }, 421 { "class": "VecReg128/VecMem128", "usage": "use" } 422 ] 423 }, 424 { 425 "encodings": { 426 "Addsd": { "opcodes": [ "F2", "0F", "58" ] }, 427 "Cmpeqsd": { "opcodes": [ "F2", "0F", "C2", "00" ] }, 428 "Cmplesd": { "opcodes": [ "F2", "0F", "C2", "02" ] }, 429 "Cmpltsd": { "opcodes": [ "F2", "0F", "C2", "01" ] }, 430 "Cmpneqsd": { "opcodes": [ "F2", "0F", "C2", "04" ] }, 431 "Cmpnlesd": { "opcodes": [ "F2", "0F", "C2", "06" ] }, 432 "Cmpnltsd": { "opcodes": [ "F2", "0F", "C2", "05" ] }, 433 "Cmpordsd": { "opcodes": [ "F2", "0F", "C2", "07" ] }, 434 "Cmpunordsd": { "opcodes": [ "F2", "0F", "C2", "03" ] }, 435 "Divsd": { "opcodes": [ "F2", "0F", "5E" ] }, 436 "Mulsd": { "opcodes": [ "F2", "0F", "59" ] }, 437 "Subsd": { "opcodes": [ "F2", "0F", "5C" ] } 438 }, 439 "args": [ 440 { "class": "FpReg64", "usage": "use_def" }, 441 { "class": "FpReg64/VecMem64", "usage": "use" } 442 ] 443 }, 444 { 445 "encodings": { 446 "Addss": { "opcodes": [ "F3", "0F", "58" ] }, 447 "Cmpeqss": { "opcodes": [ "F3", "0F", "C2", "00" ] }, 448 "Cmpless": { "opcodes": [ "F3", "0F", "C2", "02" ] }, 449 "Cmpltss": { "opcodes": [ "F3", "0F", "C2", "01" ] }, 450 "Cmpneqss": { "opcodes": [ "F3", "0F", "C2", "04" ] }, 451 "Cmpnless": { "opcodes": [ "F3", "0F", "C2", "06" ] }, 452 "Cmpnltss": { "opcodes": [ "F3", "0F", "C2", "05" ] }, 453 "Cmpordss": { "opcodes": [ "F3", "0F", "C2", "07" ] }, 454 "Cmpunordss": { "opcodes": [ "F3", "0F", "C2", "03" ] }, 455 "Divss": { "opcodes": [ "F3", "0F", "5E" ] }, 456 "Mulss": { "opcodes": [ "F3", "0F", "59" ] }, 457 "Subss": { "opcodes": [ "F3", "0F", "5C" ] } 458 }, 459 "args": [ 460 { "class": "FpReg32", "usage": "use_def" }, 461 { "class": "FpReg32/VecMem32", "usage": "use" } 462 ] 463 }, 464 { 465 "encodings": { 466 "Addw": { "opcodes": [ "66", "01" ], "reg_to_rm": true }, 467 "Andw": { "opcodes": [ "66", "21" ], "reg_to_rm": true }, 468 "Btcw": { "opcodes": [ "66", "0F", "BB" ], "reg_to_rm": true }, 469 "Btrw": { "opcodes": [ "66", "0F", "B3" ], "reg_to_rm": true }, 470 "Btsw": { "opcodes": [ "66", "0F", "AB" ], "reg_to_rm": true }, 471 "Orw": { "opcodes": [ "66", "09" ], "reg_to_rm": true }, 472 "Subw": { "opcodes": [ "66", "29" ], "reg_to_rm": true }, 473 "Xorw": { "opcodes": [ "66", "31" ], "reg_to_rm": true } 474 }, 475 "args": [ 476 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 477 { "class": "GeneralReg16", "usage": "use" }, 478 { "class": "FLAGS", "usage": "def" } 479 ] 480 }, 481 { 482 "encodings": { 483 "Addw": { "opcodes": [ "66", "03" ] }, 484 "Andw": { "opcodes": [ "66", "23" ] }, 485 "Orw": { "opcodes": [ "66", "0B" ] }, 486 "Subw": { "opcodes": [ "66", "2B" ] }, 487 "Xorw": { "opcodes": [ "66", "33" ] } 488 }, 489 "args": [ 490 { "class": "GeneralReg16", "usage": "use_def" }, 491 { "class": "Mem16", "usage": "use" }, 492 { "class": "FLAGS", "usage": "def" } 493 ] 494 }, 495 { 496 "encodings": { 497 "Addw": { "opcodes": [ "66", "81", "0" ] }, 498 "Andw": { "opcodes": [ "66", "81", "4" ] }, 499 "Orw": { "opcodes": [ "66", "81", "1" ] }, 500 "Subw": { "opcodes": [ "66", "81", "5" ] }, 501 "Xorw": { "opcodes": [ "66", "81", "6" ] } 502 }, 503 "args": [ 504 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 505 { "class": "Imm16" }, 506 { "class": "FLAGS", "usage": "def" } 507 ] 508 }, 509 { 510 "encodings": { 511 "AddwAccumulator": { "opcodes": [ "66", "05" ] }, 512 "AndwAccumulator": { "opcodes": [ "66", "25" ] }, 513 "OrwAccumulator": { "opcodes": [ "66", "0D" ] }, 514 "SubwAccumulator": { "opcodes": [ "66", "2D" ] }, 515 "XorwAccumulator": { "opcodes": [ "66", "35" ] } 516 }, 517 "args": [ 518 { "class": "AX", "usage": "use_def" }, 519 { "class": "Imm16" }, 520 { "class": "FLAGS", "usage": "def" } 521 ] 522 }, 523 { 524 "encodings": { 525 "AddwImm8": { "opcodes": [ "66", "83", "0" ] }, 526 "AndwImm8": { "opcodes": [ "66", "83", "4" ] }, 527 "OrwImm8": { "opcodes": [ "66", "83", "1" ] }, 528 "Rolw": { "opcodes": [ "66", "C1", "0" ] }, 529 "Rorw": { "opcodes": [ "66", "C1", "1" ] }, 530 "Sarw": { "opcodes": [ "66", "C1", "7" ] }, 531 "Shlw": { "opcodes": [ "66", "C1", "4" ] }, 532 "Shrw": { "opcodes": [ "66", "C1", "5" ] }, 533 "SubwImm8": { "opcodes": [ "66", "83", "5" ] }, 534 "XorwImm8": { "opcodes": [ "66", "83", "6" ] } 535 }, 536 "args": [ 537 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 538 { "class": "Imm8" }, 539 { "class": "FLAGS", "usage": "def" } 540 ] 541 }, 542 { 543 "encodings": { 544 "Bsfl": { "opcodes": [ "0F", "BC" ] }, 545 "Bsrl": { "opcodes": [ "0F", "BD" ] } 546 }, 547 "args": [ 548 { "class": "GeneralReg32", "usage": "def" }, 549 { "class": "GeneralReg32/Mem32", "usage": "use" }, 550 { "class": "FLAGS", "usage": "def" } 551 ] 552 }, 553 { 554 "encodings": { 555 "Bsfw": { "opcodes": [ "66", "0F", "BC" ] }, 556 "Bsrw": { "opcodes": [ "66", "0F", "BD" ] } 557 }, 558 "args": [ 559 { "class": "GeneralReg16", "usage": "def" }, 560 { "class": "GeneralReg16/Mem16", "usage": "use" }, 561 { "class": "FLAGS", "usage": "def" } 562 ] 563 }, 564 { 565 "encodings": { 566 "Bswapl": { "opcodes": [ "0F", "C8" ] } 567 }, 568 "args": [ 569 { "class": "GeneralReg32", "usage": "use_def" } 570 ] 571 }, 572 { 573 "encodings": { 574 "Btl": { "opcodes": [ "0F", "A3" ], "reg_to_rm": true }, 575 "Cmpl": { "opcodes": [ "39" ], "reg_to_rm": true }, 576 "Testl": { "opcodes": [ "85" ], "reg_to_rm": true } 577 }, 578 "args": [ 579 { "class": "GeneralReg32/Mem32", "usage": "use" }, 580 { "class": "GeneralReg32", "usage": "use" }, 581 { "class": "FLAGS", "usage": "def" } 582 ] 583 }, 584 { 585 "encodings": { 586 "Btw": { "opcodes": [ "66", "0F", "A3" ], "reg_to_rm": true }, 587 "Cmpw": { "opcodes": [ "66", "39" ], "reg_to_rm": true }, 588 "Testw": { "opcodes": [ "66", "85" ], "reg_to_rm": true } 589 }, 590 "args": [ 591 { "class": "GeneralReg16/Mem16", "usage": "use" }, 592 { "class": "GeneralReg16", "usage": "use" }, 593 { "class": "FLAGS", "usage": "def" } 594 ] 595 }, 596 { 597 "encodings": { 598 "Call": { "opcodes": [ "FF", "02" ] }, 599 "Push": { "opcodes": [ "50" ] } 600 }, 601 "args": [ 602 { "class": "RSP", "usage": "use_def" }, 603 { "class": "GeneralReg", "usage": "use" } 604 ] 605 }, 606 { 607 "stems": [ "Call" ], 608 "args": [ 609 { "class": "RSP", "usage": "use_def" }, 610 { "class": "Label" } 611 ] 612 }, 613 { 614 "encodings": { 615 "Cbtw": { "opcodes": [ "66", "98" ] }, 616 "Cbw": { "opcodes": [ "66", "98" ] } 617 }, 618 "args": [ 619 { "class": "AL", "usage": "use" }, 620 { "class": "AX", "usage": "def" } 621 ] 622 }, 623 { 624 "encodings": { 625 "Cdq": { "opcodes": [ "99" ] }, 626 "Cltd": { "opcodes": [ "99" ] } 627 }, 628 "args": [ 629 { "class": "EAX", "usage": "use" }, 630 { "class": "EDX", "usage": "def" } 631 ] 632 }, 633 { 634 "encodings": { 635 "Clc": { "opcodes": [ "F8" ] }, 636 "Cmc": { "opcodes": [ "F5" ] }, 637 "Stc": { "opcodes": [ "F9" ] } 638 }, 639 "args": [ 640 { "class": "FLAGS", "usage": "use_def" } 641 ] 642 }, 643 { 644 "encodings": { 645 "Cmovl": { "opcodes": [ "0F", "40" ] } 646 }, 647 "args": [ 648 { "class": "Cond" }, 649 { "class": "GeneralReg32", "usage": "use_def" }, 650 { "class": "GeneralReg32", "usage": "use" }, 651 { "class": "FLAGS", "usage": "use" } 652 ] 653 }, 654 { 655 "encodings": { 656 "CmpXchg8b": { "opcodes": [ "0F", "C7", "1" ] }, 657 "LockCmpXchg8b": { "opcodes": [ "F0", "0F", "C7", "1" ] } 658 }, 659 "args": [ 660 { "class": "EAX", "usage": "use_def" }, 661 { "class": "EDX", "usage": "use_def" }, 662 { "class": "EBX", "usage": "use" }, 663 { "class": "ECX", "usage": "use" }, 664 { "class": "VecMem64", "usage": "use_def" }, 665 { "class": "FLAGS", "usage": "def" } 666 ] 667 }, 668 { 669 "encodings": { 670 "CmpXchgl": { "opcodes": [ "0F", "B1" ], "reg_to_rm": true } 671 }, 672 "args": [ 673 { "class": "EAX", "usage": "use_def" }, 674 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 675 { "class": "GeneralReg32", "usage": "use" }, 676 { "class": "FLAGS", "usage": "def" } 677 ] 678 }, 679 { 680 "encodings": { 681 "Cmpb": { "opcodes": [ "80", "7" ] }, 682 "Testb": { "opcodes": [ "F6", "0" ] } 683 }, 684 "args": [ 685 { "class": "GeneralReg8/Mem8", "usage": "use" }, 686 { "class": "Imm8" }, 687 { "class": "FLAGS", "usage": "def" } 688 ] 689 }, 690 { 691 "encodings": { 692 "Cmpb": { "opcodes": [ "38" ], "reg_to_rm": true }, 693 "Testb": { "opcodes": [ "84" ], "reg_to_rm": true } 694 }, 695 "args": [ 696 { "class": "GeneralReg8/Mem8", "usage": "use" }, 697 { "class": "GeneralReg8", "usage": "use" }, 698 { "class": "FLAGS", "usage": "def" } 699 ] 700 }, 701 { 702 "encodings": { 703 "Cmpb": { "opcodes": [ "3A" ] } 704 }, 705 "args": [ 706 { "class": "GeneralReg8", "usage": "use" }, 707 { "class": "Mem8", "usage": "use" }, 708 { "class": "FLAGS", "usage": "def" } 709 ] 710 }, 711 { 712 "encodings": { 713 "CmpbAccumulator": { "opcodes": [ "3C" ] }, 714 "TestbAccumulator": { "opcodes": [ "A8" ] } 715 }, 716 "args": [ 717 { "class": "AL", "usage": "use" }, 718 { "class": "Imm8" }, 719 { "class": "FLAGS", "usage": "def" } 720 ] 721 }, 722 { 723 "encodings": { 724 "Cmpl": { "opcodes": [ "81", "7" ] }, 725 "Testl": { "opcodes": [ "F7", "0" ] } 726 }, 727 "args": [ 728 { "class": "GeneralReg32/Mem32", "usage": "use" }, 729 { "class": "Imm32" }, 730 { "class": "FLAGS", "usage": "def" } 731 ] 732 }, 733 { 734 "encodings": { 735 "Cmpl": { "opcodes": [ "3B" ] } 736 }, 737 "args": [ 738 { "class": "GeneralReg32", "usage": "use" }, 739 { "class": "Mem32", "usage": "use" }, 740 { "class": "FLAGS", "usage": "def" } 741 ] 742 }, 743 { 744 "encodings": { 745 "CmplAccumulator": { "opcodes": [ "3D" ] }, 746 "TestlAccumulator": { "opcodes": [ "A9" ] } 747 }, 748 "args": [ 749 { "class": "EAX", "usage": "use" }, 750 { "class": "Imm32" }, 751 { "class": "FLAGS", "usage": "def" } 752 ] 753 }, 754 { 755 "encodings": { 756 "CmplImm8": { "opcodes": [ "83", "7" ] } 757 }, 758 "args": [ 759 { "class": "GeneralReg32/Mem32", "usage": "use" }, 760 { "class": "Imm8" }, 761 { "class": "FLAGS", "usage": "def" } 762 ] 763 }, 764 { 765 "encodings": { 766 "Cmpw": { "opcodes": [ "66", "81", "7" ] }, 767 "Testw": { "opcodes": [ "66", "F7", "0" ] } 768 }, 769 "args": [ 770 { "class": "GeneralReg16/Mem16", "usage": "use" }, 771 { "class": "Imm16" }, 772 { "class": "FLAGS", "usage": "def" } 773 ] 774 }, 775 { 776 "encodings": { 777 "Cmpw": { "opcodes": [ "66", "3B" ] } 778 }, 779 "args": [ 780 { "class": "GeneralReg16", "usage": "use" }, 781 { "class": "Mem16", "usage": "use" }, 782 { "class": "FLAGS", "usage": "def" } 783 ] 784 }, 785 { 786 "encodings": { 787 "CmpwAccumulator": { "opcodes": [ "66", "3D" ] }, 788 "TestwAccumulator": { "opcodes": [ "66", "A9" ] } 789 }, 790 "args": [ 791 { "class": "AX", "usage": "use" }, 792 { "class": "Imm16" }, 793 { "class": "FLAGS", "usage": "def" } 794 ] 795 }, 796 { 797 "encodings": { 798 "CmpwImm8": { "opcodes": [ "66", "83", "7" ] } 799 }, 800 "args": [ 801 { "class": "GeneralReg16/Mem16", "usage": "use" }, 802 { "class": "Imm8" }, 803 { "class": "FLAGS", "usage": "def" } 804 ] 805 }, 806 { 807 "encodings": { 808 "Cvtdq2pd": { "opcodes": [ "F3", "0F", "E6" ] }, 809 "Cvtdq2ps": { "opcodes": [ "0F", "5B" ] }, 810 "Cvtpd2dq": { "opcodes": [ "F2", "0F", "E6" ] }, 811 "Cvtpd2ps": { "opcodes": [ "66", "0F", "5A" ] }, 812 "Cvtps2dq": { "opcodes": [ "66", "0F", "5B" ] }, 813 "Cvtps2pd": { "opcodes": [ "0F", "5A" ] }, 814 "Cvttpd2dq": { "opcodes": [ "66", "0F", "E6" ] }, 815 "Cvttps2dq": { "opcodes": [ "F3", "0F", "5B" ] }, 816 "Vcvtdq2pd": { "opcodes": [ "C4", "01", "02", "E6" ] }, 817 "Vcvtdq2ps": { "opcodes": [ "C4", "01", "00", "5B" ] }, 818 "Vcvtpd2dq": { "opcodes": [ "C4", "01", "03", "E6" ] }, 819 "Vcvtpd2ps": { "opcodes": [ "C4", "01", "01", "5A" ] }, 820 "Vcvtps2dq": { "opcodes": [ "C4", "01", "01", "5B" ] }, 821 "Vcvtps2pd": { "opcodes": [ "C4", "01", "00", "5A" ] }, 822 "Vcvttpd2dq": { "opcodes": [ "C4", "01", "01", "E6" ] }, 823 "Vcvttps2dq": { "opcodes": [ "C4", "01", "02", "5B" ] } 824 }, 825 "args": [ 826 { "class": "VecReg128", "usage": "def" }, 827 { "class": "VecReg128/VecMem128", "usage": "use" } 828 ] 829 }, 830 { 831 "encodings": { 832 "Cvtsd2sil": { "opcodes": [ "F2", "0F", "2D" ] }, 833 "Cvttsd2sil": { "opcodes": [ "F2", "0F", "2C" ] }, 834 "Vcvtsd2sil": { "opcodes": [ "C4", "01", "03", "2D" ] }, 835 "Vcvttsd2sil": { "opcodes": [ "C4", "01", "03", "2C" ] } 836 }, 837 "args": [ 838 { "class": "GeneralReg32", "usage": "def" }, 839 { "class": "FpReg64/VecMem64", "usage": "use" } 840 ] 841 }, 842 { 843 "encodings": { 844 "Cvtsd2ss": { "opcodes": [ "F2", "0F", "5A" ] } 845 }, 846 "args": [ 847 { "class": "FpReg32", "usage": "def" }, 848 { "class": "FpReg64/VecMem64", "usage": "use" } 849 ] 850 }, 851 { 852 "encodings": { 853 "Cvtsi2sdl": { "opcodes": [ "F2", "0F", "2A" ] } 854 }, 855 "args": [ 856 { "class": "FpReg64", "usage": "def" }, 857 { "class": "GeneralReg32/Mem32", "usage": "use" } 858 ] 859 }, 860 { 861 "encodings": { 862 "Cvtsi2ssl": { "opcodes": [ "F3", "0F", "2A" ] } 863 }, 864 "args": [ 865 { "class": "FpReg32", "usage": "def" }, 866 { "class": "GeneralReg32/Mem32", "usage": "use" } 867 ] 868 }, 869 { 870 "encodings": { 871 "Cvtss2sd": { "opcodes": [ "F3", "0F", "5A" ] } 872 }, 873 "args": [ 874 { "class": "FpReg64", "usage": "def" }, 875 { "class": "FpReg32/VecMem32", "usage": "use" } 876 ] 877 }, 878 { 879 "encodings": { 880 "Cvtss2sil": { "opcodes": [ "F3", "0F", "2D" ] }, 881 "Cvttss2sil": { "opcodes": [ "F3", "0F", "2C" ] }, 882 "Vcvtss2sil": { "opcodes": [ "C4", "01", "02", "2D" ] }, 883 "Vcvttss2sil": { "opcodes": [ "C4", "01", "02", "2C" ] } 884 }, 885 "args": [ 886 { "class": "GeneralReg32", "usage": "def" }, 887 { "class": "FpReg32/VecMem32", "usage": "use" } 888 ] 889 }, 890 { 891 "encodings": { 892 "Cwd": { "opcodes": [ "66", "99" ] }, 893 "Cwtd": { "opcodes": [ "66", "99" ] } 894 }, 895 "args": [ 896 { "class": "AX", "usage": "use" }, 897 { "class": "DX", "usage": "def" } 898 ] 899 }, 900 { 901 "encodings": { 902 "Cwde": { "opcodes": [ "98" ] }, 903 "Cwtl": { "opcodes": [ "98" ] } 904 }, 905 "args": [ 906 { "class": "AX", "usage": "use" }, 907 { "class": "EAX", "usage": "def" } 908 ] 909 }, 910 { 911 "encodings": { 912 "Decb": { "opcodes": [ "FE", "1" ] }, 913 "Incb": { "opcodes": [ "FE", "0" ] }, 914 "Negb": { "opcodes": [ "F6", "3" ] }, 915 "RolbByOne": { "opcodes": [ "D0", "0" ] }, 916 "RorbByOne": { "opcodes": [ "D0", "1" ] }, 917 "SarbByOne": { "opcodes": [ "D0", "7" ] }, 918 "ShlbByOne": { "opcodes": [ "D0", "4" ] }, 919 "ShrbByOne": { "opcodes": [ "D0", "5" ] } 920 }, 921 "args": [ 922 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 923 { "class": "FLAGS", "usage": "def" } 924 ] 925 }, 926 { 927 "encodings": { 928 "Decl": { "opcodes": [ "FF", "1" ] }, 929 "Incl": { "opcodes": [ "FF", "0" ] } 930 }, 931 "args": [ 932 { "class": "Mem32", "usage": "use_def" }, 933 { "class": "FLAGS", "usage": "def" } 934 ] 935 }, 936 { 937 "encodings": { 938 "Decw": { "opcodes": [ "66", "FF", "1" ] }, 939 "Incw": { "opcodes": [ "66", "FF", "0" ] } 940 }, 941 "args": [ 942 { "class": "Mem16", "usage": "use_def" }, 943 { "class": "FLAGS", "usage": "def" } 944 ] 945 }, 946 { 947 "encodings": { 948 "Divl": { "opcodes": [ "F7", "6" ] }, 949 "Idivl": { "opcodes": [ "F7", "7" ] } 950 }, 951 "args": [ 952 { "class": "EAX", "usage": "use_def" }, 953 { "class": "EDX", "usage": "use_def" }, 954 { "class": "GeneralReg32/Mem32", "usage": "use" }, 955 { "class": "FLAGS", "usage": "def" } 956 ] 957 }, 958 { 959 "encodings": { 960 "Fldl": { "opcodes": [ "DD", "0" ] } 961 }, 962 "args": [ 963 { "class": "Mem64", "usage": "use" } 964 ] 965 }, 966 { 967 "encodings": { 968 "Flds": { "opcodes": [ "D9", "0" ] }, 969 "Ldmxcsr": { "opcodes": [ "0F", "AE", "2" ] }, 970 "Vldmxcsr": { "opcodes": [ "C4", "01", "00", "AE", "2" ] } 971 }, 972 "args": [ 973 { "class": "Mem32", "usage": "use" } 974 ] 975 }, 976 { 977 "encodings": { 978 "Fstpl": { "opcodes": [ "DD", "3" ] } 979 }, 980 "args": [ 981 { "class": "Mem64", "usage": "def" } 982 ] 983 }, 984 { 985 "encodings": { 986 "Fstps": { "opcodes": [ "D9", "3" ] }, 987 "Stmxcsr": { "opcodes": [ "0F", "AE", "3" ] }, 988 "Vstmxcsr": { "opcodes": [ "C4", "01", "00", "AE", "3" ] } 989 }, 990 "args": [ 991 { "class": "Mem32", "usage": "def" } 992 ] 993 }, 994 { 995 "encodings": { 996 "Imulb": { "opcodes": [ "F6", "5" ] }, 997 "Mulb": { "opcodes": [ "F6", "4" ] } 998 }, 999 "args": [ 1000 { "class": "AL", "usage": "use" }, 1001 { "class": "AX", "usage": "def" }, 1002 { "class": "GeneralReg8/Mem8", "usage": "use" }, 1003 { "class": "FLAGS", "usage": "def" } 1004 ] 1005 }, 1006 { 1007 "encodings": { 1008 "Imull": { "opcodes": [ "F7", "5" ] }, 1009 "Mull": { "opcodes": [ "F7", "4" ] } 1010 }, 1011 "args": [ 1012 { "class": "EAX", "usage": "use_def" }, 1013 { "class": "EDX", "usage": "def" }, 1014 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1015 { "class": "FLAGS", "usage": "def" } 1016 ] 1017 }, 1018 { 1019 "encodings": { 1020 "Imull": { "opcodes": [ "69" ] } 1021 }, 1022 "args": [ 1023 { "class": "GeneralReg32", "usage": "def" }, 1024 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1025 { "class": "Imm32" }, 1026 { "class": "FLAGS", "usage": "def" } 1027 ] 1028 }, 1029 { 1030 "encodings": { 1031 "Imull": { "opcodes": [ "0F", "AF" ] } 1032 }, 1033 "args": [ 1034 { "class": "GeneralReg32", "usage": "use_def" }, 1035 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1036 { "class": "FLAGS", "usage": "def" } 1037 ] 1038 }, 1039 { 1040 "encodings": { 1041 "ImullImm8": { "opcodes": [ "6B" ] } 1042 }, 1043 "args": [ 1044 { "class": "GeneralReg32", "usage": "def" }, 1045 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1046 { "class": "Imm8" }, 1047 { "class": "FLAGS", "usage": "def" } 1048 ] 1049 }, 1050 { 1051 "encodings": { 1052 "Imulw": { "opcodes": [ "66", "F7", "5" ] }, 1053 "Mulw": { "opcodes": [ "66", "F7", "4" ] } 1054 }, 1055 "args": [ 1056 { "class": "AX", "usage": "use_def" }, 1057 { "class": "DX", "usage": "def" }, 1058 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1059 { "class": "FLAGS", "usage": "def" } 1060 ] 1061 }, 1062 { 1063 "encodings": { 1064 "Imulw": { "opcodes": [ "66", "69" ] } 1065 }, 1066 "args": [ 1067 { "class": "GeneralReg16", "usage": "def" }, 1068 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1069 { "class": "Imm16" }, 1070 { "class": "FLAGS", "usage": "def" } 1071 ] 1072 }, 1073 { 1074 "encodings": { 1075 "Imulw": { "opcodes": [ "66", "0F", "AF" ] } 1076 }, 1077 "args": [ 1078 { "class": "GeneralReg16", "usage": "use_def" }, 1079 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1080 { "class": "FLAGS", "usage": "def" } 1081 ] 1082 }, 1083 { 1084 "encodings": { 1085 "ImulwImm8": { "opcodes": [ "66", "6B" ] } 1086 }, 1087 "args": [ 1088 { "class": "GeneralReg16", "usage": "def" }, 1089 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1090 { "class": "Imm8" }, 1091 { "class": "FLAGS", "usage": "def" } 1092 ] 1093 }, 1094 { 1095 "encodings": { 1096 "Int3": { "opcodes": [ "CC" ] }, 1097 "Mfence": { "opcodes": [ "0F", "AE", "F0" ] }, 1098 "Nop": { "opcodes": [ "90" ] }, 1099 "UD2": { "opcodes": [ "0F", "0B" ] } 1100 }, 1101 "args": [] 1102 }, 1103 { 1104 "stems": [ "Jcc" ], 1105 "args": [ 1106 { "class": "Cond" }, 1107 { "class": "Label" }, 1108 { "class": "FLAGS", "usage": "use" } 1109 ] 1110 }, 1111 { 1112 "stems": [ "Jmp" ], 1113 "args": [ 1114 { "class": "Label" } 1115 ] 1116 }, 1117 { 1118 "encodings": { 1119 "Jmp": { "opcodes": [ "FF", "4" ] } 1120 }, 1121 "args": [ 1122 { "class": "GeneralReg", "usage": "use" } 1123 ] 1124 }, 1125 { 1126 "encodings": { 1127 "Lahf": { "opcodes": [ "9F" ] } 1128 }, 1129 "args": [ 1130 { "class": "EAX", "usage": "use_def" }, 1131 { "class": "FLAGS", "usage": "use" } 1132 ], 1133 "comment": "Use use_def below because LAHF writes to AH while preserving the rest of RAX" 1134 }, 1135 { 1136 "encodings": { 1137 "Leal": { "opcodes": [ "8D" ] }, 1138 "Movl": { "opcodes": [ "8B" ] } 1139 }, 1140 "args": [ 1141 { "class": "GeneralReg32", "usage": "def" }, 1142 { "class": "Mem32", "usage": "use" } 1143 ] 1144 }, 1145 { 1146 "encodings": { 1147 "LockCmpXchgl": { "opcodes": [ "F0", "0F", "B1" ], "reg_to_rm": true } 1148 }, 1149 "args": [ 1150 { "class": "EAX", "usage": "use_def" }, 1151 { "class": "Mem32", "usage": "use_def" }, 1152 { "class": "GeneralReg32", "usage": "use" }, 1153 { "class": "FLAGS", "usage": "def" } 1154 ] 1155 }, 1156 { 1157 "encodings": { 1158 "Movapd": { "opcodes": [ "66", "0F", "29" ] }, 1159 "Movaps": { "opcodes": [ "0F", "29" ] }, 1160 "Vmovapd": { "opcodes": [ "C4", "01", "01", "29" ] }, 1161 "Vmovaps": { "opcodes": [ "C4", "01", "00", "29" ] } 1162 }, 1163 "args": [ 1164 { "class": "VecMem128", "usage": "def" }, 1165 { "class": "XmmReg", "usage": "use" } 1166 ] 1167 }, 1168 { 1169 "encodings": { 1170 "Movapd": { "opcodes": [ "66", "0F", "28" ] }, 1171 "Movaps": { "opcodes": [ "0F", "28" ] } 1172 }, 1173 "args": [ 1174 { "class": "XmmReg", "usage": "def" }, 1175 { "class": "XmmReg/VecMem128", "usage": "use" } 1176 ] 1177 }, 1178 { 1179 "encodings": { 1180 "Movb": { "opcodes": [ "B0" ] } 1181 }, 1182 "args": [ 1183 { "class": "GeneralReg8", "usage": "def" }, 1184 { "class": "Imm8" } 1185 ] 1186 }, 1187 { 1188 "encodings": { 1189 "Movb": { "opcodes": [ "8A" ] } 1190 }, 1191 "args": [ 1192 { "class": "GeneralReg8", "usage": "def" }, 1193 { "class": "Mem8", "usage": "use" } 1194 ] 1195 }, 1196 { 1197 "encodings": { 1198 "Movb": { "opcodes": [ "88" ], "reg_to_rm": true } 1199 }, 1200 "args": [ 1201 { "class": "GeneralReg8/Mem8", "usage": "def" }, 1202 { "class": "GeneralReg8", "usage": "use" } 1203 ] 1204 }, 1205 { 1206 "encodings": { 1207 "Movb": { "opcodes": [ "C6", "0" ] } 1208 }, 1209 "args": [ 1210 { "class": "Mem8", "usage": "def" }, 1211 { "class": "Imm8" } 1212 ] 1213 }, 1214 { 1215 "encodings": { 1216 "Movd": { "opcodes": [ "66", "0F", "7E" ], "reg_to_rm": true }, 1217 "Vmovd": { "opcodes": [ "C4", "01", "01", "7E" ], "reg_to_rm": true } 1218 }, 1219 "args": [ 1220 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1221 { "class": "XmmReg", "usage": "use" } 1222 ] 1223 }, 1224 { 1225 "encodings": { 1226 "Movd": { "opcodes": [ "66", "0F", "6E" ] }, 1227 "Vmovd": { "opcodes": [ "C4", "01", "01", "6E" ] } 1228 }, 1229 "args": [ 1230 { "class": "XmmReg", "usage": "def" }, 1231 { "class": "GeneralReg32/Mem32", "usage": "use" } 1232 ] 1233 }, 1234 { 1235 "name": "MovdqRegReg", 1236 "args": [ 1237 { "class": "XmmReg", "usage": "def" }, 1238 { "class": "XmmReg", "usage": "use" } 1239 ], 1240 "asm": "Pmov", 1241 "mnemo": "MOVDQ" 1242 }, 1243 { 1244 "encodings": { 1245 "Movdqa": { "opcodes": [ "66", "0F", "7F" ] }, 1246 "Movdqu": { "opcodes": [ "F3", "0F", "7F" ] }, 1247 "Vmovdqa": { "opcodes": [ "C4", "01", "01", "7F" ] }, 1248 "Vmovdqu": { "opcodes": [ "C4", "01", "02", "7F" ] } 1249 }, 1250 "args": [ 1251 { "class": "VecMem128", "usage": "def" }, 1252 { "class": "XmmReg", "usage": "use" } 1253 ] 1254 }, 1255 { 1256 "encodings": { 1257 "Movdqa": { "opcodes": [ "66", "0F", "6F" ] }, 1258 "Movdqu": { "opcodes": [ "F3", "0F", "6F" ] } 1259 }, 1260 "args": [ 1261 { "class": "XmmReg", "usage": "def" }, 1262 { "class": "XmmReg/VecMem128", "usage": "use" } 1263 ] 1264 }, 1265 { 1266 "encodings": { 1267 "Movhlps": { "opcodes": [ "0F", "12" ] }, 1268 "Movlhps": { "opcodes": [ "0F", "16" ] }, 1269 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1270 "Movss": { "opcodes": [ "F3", "0F", "10" ] } 1271 }, 1272 "args": [ 1273 { "class": "XmmReg", "usage": "use_def" }, 1274 { "class": "XmmReg", "usage": "use" } 1275 ], 1276 "comment": "Upper bits (lower bits for Movlhps) are unchanged" 1277 }, 1278 { 1279 "encodings": { 1280 "Movhpd": { "opcodes": [ "66", "0F", "17" ] }, 1281 "Movhps": { "opcodes": [ "0F", "17" ] }, 1282 "Movlpd": { "opcodes": [ "66", "0F", "13" ] }, 1283 "Movlps": { "opcodes": [ "0F", "13" ] }, 1284 "Vmovhpd": { "opcodes": [ "C4", "01", "01", "17" ] }, 1285 "Vmovhps": { "opcodes": [ "C4", "01", "00", "17" ] }, 1286 "Vmovlpd": { "opcodes": [ "C4", "01", "01", "13" ] }, 1287 "Vmovlps": { "opcodes": [ "C4", "01", "00", "13" ] } 1288 }, 1289 "args": [ 1290 { "class": "VecMem64", "usage": "use_def" }, 1291 { "class": "XmmReg", "usage": "use" } 1292 ] 1293 }, 1294 { 1295 "encodings": { 1296 "Movhpd": { "opcodes": [ "66", "0F", "16" ] }, 1297 "Movhps": { "opcodes": [ "0F", "16" ] }, 1298 "Movlpd": { "opcodes": [ "66", "0F", "12" ] }, 1299 "Movlps": { "opcodes": [ "0F", "12" ] } 1300 }, 1301 "args": [ 1302 { "class": "XmmReg", "usage": "use_def" }, 1303 { "class": "VecMem64", "usage": "use" } 1304 ] 1305 }, 1306 { 1307 "encodings": { 1308 "Movl": { "opcodes": [ "B8" ] } 1309 }, 1310 "args": [ 1311 { "class": "GeneralReg32", "usage": "def" }, 1312 { "class": "Imm32" } 1313 ] 1314 }, 1315 { 1316 "encodings": { 1317 "Movl": { "opcodes": [ "89" ], "reg_to_rm": true } 1318 }, 1319 "args": [ 1320 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1321 { "class": "GeneralReg32", "usage": "use" } 1322 ] 1323 }, 1324 { 1325 "encodings": { 1326 "Movl": { "opcodes": [ "C7", "0" ] } 1327 }, 1328 "args": [ 1329 { "class": "Mem32", "usage": "def" }, 1330 { "class": "Imm32" } 1331 ] 1332 }, 1333 { 1334 "encodings": { 1335 "Movmskpd": { "opcodes": [ "66", "0F", "50" ] }, 1336 "Movmskps": { "opcodes": [ "0F", "50" ] }, 1337 "Vmovmskpd": { "opcodes": [ "C4", "01", "01", "50" ] }, 1338 "Vmovmskps": { "opcodes": [ "C4", "01", "00", "50" ] } 1339 }, 1340 "args": [ 1341 { "class": "GeneralReg32", "usage": "def" }, 1342 { "class": "XmmReg", "usage": "use" } 1343 ] 1344 }, 1345 { 1346 "encodings": { 1347 "Movq": { "opcodes": [ "66", "0F", "D6" ] }, 1348 "Movsd": { "opcodes": [ "F2", "0F", "11" ] }, 1349 "Vmovq": { "opcodes": [ "C4", "01", "01", "D6" ] }, 1350 "Vmovsd": { "opcodes": [ "C4", "01", "03", "11" ] } 1351 }, 1352 "args": [ 1353 { "class": "VecMem64", "usage": "def" }, 1354 { "class": "XmmReg", "usage": "use" } 1355 ] 1356 }, 1357 { 1358 "encodings": { 1359 "Movq": { "opcodes": [ "F3", "0F", "7E" ] }, 1360 "Pmovsxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "20" ] }, 1361 "Pmovsxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "25" ] }, 1362 "Pmovsxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "23" ] }, 1363 "Pmovzxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "30" ] }, 1364 "Pmovzxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "35" ] }, 1365 "Pmovzxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "33" ] }, 1366 "Vmovq": { "opcodes": [ "C4", "01", "02", "7E" ] } 1367 }, 1368 "args": [ 1369 { "class": "XmmReg", "usage": "def" }, 1370 { "class": "XmmReg/VecMem64", "usage": "use" } 1371 ], 1372 "comment": "Upper bits are zero-filled for Movq/Vmovq" 1373 }, 1374 { 1375 "encodings": { 1376 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1377 "Vmovsd": { "opcodes": [ "C4", "01", "03", "10" ] } 1378 }, 1379 "args": [ 1380 { "class": "XmmReg", "usage": "def" }, 1381 { "class": "VecMem64", "usage": "use" } 1382 ], 1383 "comment": "Upper bits are zero-filled" 1384 }, 1385 { 1386 "encodings": { 1387 "Movss": { "opcodes": [ "F3", "0F", "10" ] }, 1388 "Vmovss": { "opcodes": [ "C4", "01", "02", "10" ] } 1389 }, 1390 "args": [ 1391 { "class": "XmmReg", "usage": "def" }, 1392 { "class": "VecMem32", "usage": "use" } 1393 ], 1394 "comment": "Upper bits are zero-filled" 1395 }, 1396 { 1397 "encodings": { 1398 "Movss": { "opcodes": [ "F3", "0F", "11" ] } 1399 }, 1400 "args": [ 1401 { "class": "Mem32", "usage": "def" }, 1402 { "class": "XmmReg", "usage": "use" } 1403 ] 1404 }, 1405 { 1406 "encodings": { 1407 "Movsxbl": { "opcodes": [ "0F", "BE" ] }, 1408 "Movzxbl": { "opcodes": [ "0F", "B6" ] } 1409 }, 1410 "args": [ 1411 { "class": "GeneralReg32", "usage": "def" }, 1412 { "class": "GeneralReg8/Mem8", "usage": "use" } 1413 ] 1414 }, 1415 { 1416 "encodings": { 1417 "Movsxwl": { "opcodes": [ "0F", "BF" ] }, 1418 "Movzxwl": { "opcodes": [ "0F", "B7" ] } 1419 }, 1420 "args": [ 1421 { "class": "GeneralReg32", "usage": "def" }, 1422 { "class": "GeneralReg16/Mem16", "usage": "use" } 1423 ] 1424 }, 1425 { 1426 "encodings": { 1427 "Movw": { "opcodes": [ "66", "B8" ] } 1428 }, 1429 "args": [ 1430 { "class": "GeneralReg16", "usage": "def" }, 1431 { "class": "Imm16" } 1432 ] 1433 }, 1434 { 1435 "encodings": { 1436 "Movw": { "opcodes": [ "66", "8B" ] } 1437 }, 1438 "args": [ 1439 { "class": "GeneralReg16", "usage": "def" }, 1440 { "class": "Mem16", "usage": "use" } 1441 ] 1442 }, 1443 { 1444 "encodings": { 1445 "Movw": { "opcodes": [ "66", "89" ], "reg_to_rm": true } 1446 }, 1447 "args": [ 1448 { "class": "GeneralReg16/Mem16", "usage": "def" }, 1449 { "class": "GeneralReg16", "usage": "use" } 1450 ] 1451 }, 1452 { 1453 "encodings": { 1454 "Movw": { "opcodes": [ "66", "C7", "0" ] } 1455 }, 1456 "args": [ 1457 { "class": "Mem16", "usage": "def" }, 1458 { "class": "Imm16" } 1459 ] 1460 }, 1461 { 1462 "encodings": { 1463 "Negl": { "opcodes": [ "F7", "3" ] }, 1464 "RollByOne": { "opcodes": [ "D1", "0" ] }, 1465 "RorlByOne": { "opcodes": [ "D1", "1" ] }, 1466 "SarlByOne": { "opcodes": [ "D1", "7" ] }, 1467 "ShllByOne": { "opcodes": [ "D1", "4" ] }, 1468 "ShrlByOne": { "opcodes": [ "D1", "5" ] } 1469 }, 1470 "args": [ 1471 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1472 { "class": "FLAGS", "usage": "def" } 1473 ] 1474 }, 1475 { 1476 "encodings": { 1477 "Negw": { "opcodes": [ "66", "F7", "3" ] }, 1478 "RolwByOne": { "opcodes": [ "66", "D1", "0" ] }, 1479 "RorwByOne": { "opcodes": [ "66", "D1", "1" ] }, 1480 "SarwByOne": { "opcodes": [ "66", "D1", "7" ] }, 1481 "ShlwByOne": { "opcodes": [ "66", "D1", "4" ] }, 1482 "ShrwByOne": { "opcodes": [ "66", "D1", "5" ] } 1483 }, 1484 "args": [ 1485 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 1486 { "class": "FLAGS", "usage": "def" } 1487 ] 1488 }, 1489 { 1490 "encodings": { 1491 "Notb": { "opcodes": [ "F6", "2" ] } 1492 }, 1493 "args": [ 1494 { "class": "GeneralReg8/Mem8", "usage": "use_def" } 1495 ] 1496 }, 1497 { 1498 "encodings": { 1499 "Notl": { "opcodes": [ "F7", "2" ] } 1500 }, 1501 "args": [ 1502 { "class": "GeneralReg32/Mem32", "usage": "use_def" } 1503 ] 1504 }, 1505 { 1506 "encodings": { 1507 "Notw": { "opcodes": [ "66", "F7", "2" ] } 1508 }, 1509 "args": [ 1510 { "class": "GeneralReg16/Mem16", "usage": "use_def" } 1511 ] 1512 }, 1513 { 1514 "encodings": { 1515 "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "reg_to_rm": true }, 1516 "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "reg_to_rm": true }, 1517 "Pextrw": { "opcodes": [ "66", "0F", "C5" ] }, 1518 "Vpextrb": { "opcodes": [ "C4", "03", "01", "14" ], "reg_to_rm": true }, 1519 "Vpextrd": { "opcodes": [ "C4", "03", "01", "16" ], "reg_to_rm": true }, 1520 "Vpextrw": { "opcodes": [ "C4", "01", "01", "C5" ] } 1521 }, 1522 "args": [ 1523 { "class": "GeneralReg32", "usage": "def" }, 1524 { "class": "VecReg128", "usage": "use" }, 1525 { "class": "Imm8" } 1526 ] 1527 }, 1528 { 1529 "encodings": { 1530 "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] }, 1531 "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] }, 1532 "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] } 1533 }, 1534 "args": [ 1535 { "class": "VecReg128", "usage": "use_def" }, 1536 { "class": "GeneralReg32", "usage": "use" }, 1537 { "class": "Imm8" } 1538 ] 1539 }, 1540 { 1541 "encodings": { 1542 "Pmovmskb": { "opcodes": [ "66", "0F", "D7" ] }, 1543 "Vpmovmskb": { "opcodes": [ "C4", "01", "01", "D7" ] } 1544 }, 1545 "args": [ 1546 { "class": "GeneralReg32", "usage": "def" }, 1547 { "class": "VecReg128", "usage": "use" } 1548 ] 1549 }, 1550 { 1551 "encodings": { 1552 "Pmovsxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "21" ] }, 1553 "Pmovsxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "24" ] }, 1554 "Pmovzxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "31" ] }, 1555 "Pmovzxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "34" ] } 1556 }, 1557 "args": [ 1558 { "class": "XmmReg", "usage": "def" }, 1559 { "class": "XmmReg/VecMem32", "usage": "use" } 1560 ] 1561 }, 1562 { 1563 "encodings": { 1564 "Pop": { "opcodes": [ "58" ] } 1565 }, 1566 "args": [ 1567 { "class": "RSP", "usage": "use_def" }, 1568 { "class": "GeneralReg", "usage": "def" } 1569 ] 1570 }, 1571 { 1572 "encodings": { 1573 "Pshufd": { "opcodes": [ "66", "0F", "70" ] }, 1574 "Pshufhw": { "opcodes": [ "F3", "0F", "70" ] }, 1575 "Pshuflw": { "opcodes": [ "F2", "0F", "70" ] }, 1576 "Roundpd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "09" ] }, 1577 "Roundps": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "08" ] }, 1578 "Vpshufd": { "opcodes": [ "C4", "01", "01", "70" ] }, 1579 "Vpshufhw": { "opcodes": [ "C4", "01", "02", "70" ] }, 1580 "Vpshuflw": { "opcodes": [ "C4", "01", "03", "70" ] } 1581 }, 1582 "args": [ 1583 { "class": "VecReg128", "usage": "def" }, 1584 { "class": "VecReg128/VecMem128", "usage": "use" }, 1585 { "class": "Imm8" } 1586 ] 1587 }, 1588 { 1589 "encodings": { 1590 "Pslld": { "opcodes": [ "66", "0F", "72", "6" ] }, 1591 "Pslldq": { "opcodes": [ "66", "0F", "73", "7" ] }, 1592 "Psllq": { "opcodes": [ "66", "0F", "73", "6" ] }, 1593 "Psllw": { "opcodes": [ "66", "0F", "71", "6" ] }, 1594 "Psrad": { "opcodes": [ "66", "0F", "72", "4" ] }, 1595 "Psraw": { "opcodes": [ "66", "0F", "71", "4" ] }, 1596 "Psrld": { "opcodes": [ "66", "0F", "72", "2" ] }, 1597 "Psrldq": { "opcodes": [ "66", "0F", "73", "3" ] }, 1598 "Psrlq": { "opcodes": [ "66", "0F", "73", "2" ] }, 1599 "Psrlw": { "opcodes": [ "66", "0F", "71", "2" ] } 1600 }, 1601 "args": [ 1602 { "class": "VecReg128", "usage": "use_def" }, 1603 { "class": "Imm8" } 1604 ] 1605 }, 1606 { 1607 "encodings": { 1608 "Push": { "opcodes": [ "68" ] } 1609 }, 1610 "args": [ 1611 { "class": "RSP", "usage": "use_def" }, 1612 { "class": "Imm32" } 1613 ] 1614 }, 1615 { 1616 "encodings": { 1617 "PushImm8": { "opcodes": [ "6A" ] } 1618 }, 1619 "args": [ 1620 { "class": "RSP", "usage": "use_def" }, 1621 { "class": "Imm8" } 1622 ] 1623 }, 1624 { 1625 "encodings": { 1626 "RclbByCl": { "opcodes": [ "D2", "2" ] }, 1627 "RcrbByCl": { "opcodes": [ "D2", "3" ] } 1628 }, 1629 "args": [ 1630 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 1631 { "class": "CL", "usage": "use" }, 1632 { "class": "FLAGS", "usage": "use_def" } 1633 ] 1634 }, 1635 { 1636 "encodings": { 1637 "RclbByOne": { "opcodes": [ "D0", "2" ] }, 1638 "RcrbByOne": { "opcodes": [ "D0", "3" ] } 1639 }, 1640 "args": [ 1641 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 1642 { "class": "FLAGS", "usage": "use_def" } 1643 ] 1644 }, 1645 { 1646 "encodings": { 1647 "RcllByCl": { "opcodes": [ "D3", "2" ] }, 1648 "RcrlByCl": { "opcodes": [ "D3", "3" ] } 1649 }, 1650 "args": [ 1651 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1652 { "class": "CL", "usage": "use" }, 1653 { "class": "FLAGS", "usage": "use_def" } 1654 ] 1655 }, 1656 { 1657 "encodings": { 1658 "RcllByOne": { "opcodes": [ "D1", "2" ] }, 1659 "RcrlByOne": { "opcodes": [ "D1", "3" ] } 1660 }, 1661 "args": [ 1662 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1663 { "class": "FLAGS", "usage": "use_def" } 1664 ] 1665 }, 1666 { 1667 "encodings": { 1668 "RclwByCl": { "opcodes": [ "66", "D3", "2" ] }, 1669 "RcrwByCl": { "opcodes": [ "66", "D3", "3" ] } 1670 }, 1671 "args": [ 1672 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 1673 { "class": "CL", "usage": "use" }, 1674 { "class": "FLAGS", "usage": "use_def" } 1675 ] 1676 }, 1677 { 1678 "encodings": { 1679 "RclwByOne": { "opcodes": [ "66", "D1", "2" ] }, 1680 "RcrwByOne": { "opcodes": [ "66", "D1", "3" ] } 1681 }, 1682 "args": [ 1683 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 1684 { "class": "FLAGS", "usage": "use_def" } 1685 ] 1686 }, 1687 { 1688 "encodings": { 1689 "Ret": { "opcodes": [ "C3" ] } 1690 }, 1691 "args": [ 1692 { "class": "RSP", "usage": "use_def" } 1693 ] 1694 }, 1695 { 1696 "encodings": { 1697 "RolbByCl": { "opcodes": [ "D2", "0" ] }, 1698 "RorbByCl": { "opcodes": [ "D2", "1" ] }, 1699 "SarbByCl": { "opcodes": [ "D2", "7" ] }, 1700 "ShlbByCl": { "opcodes": [ "D2", "4" ] }, 1701 "ShrbByCl": { "opcodes": [ "D2", "5" ] } 1702 }, 1703 "args": [ 1704 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 1705 { "class": "CL", "usage": "use" }, 1706 { "class": "FLAGS", "usage": "def" } 1707 ] 1708 }, 1709 { 1710 "encodings": { 1711 "RollByCl": { "opcodes": [ "D3", "0" ] }, 1712 "RorlByCl": { "opcodes": [ "D3", "1" ] }, 1713 "SarlByCl": { "opcodes": [ "D3", "7" ] }, 1714 "ShllByCl": { "opcodes": [ "D3", "4" ] }, 1715 "ShrlByCl": { "opcodes": [ "D3", "5" ] } 1716 }, 1717 "args": [ 1718 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1719 { "class": "CL", "usage": "use" }, 1720 { "class": "FLAGS", "usage": "def" } 1721 ] 1722 }, 1723 { 1724 "encodings": { 1725 "RolwByCl": { "opcodes": [ "66", "D3", "0" ] }, 1726 "RorwByCl": { "opcodes": [ "66", "D3", "1" ] }, 1727 "SarwByCl": { "opcodes": [ "66", "D3", "7" ] }, 1728 "ShlwByCl": { "opcodes": [ "66", "D3", "4" ] }, 1729 "ShrwByCl": { "opcodes": [ "66", "D3", "5" ] } 1730 }, 1731 "args": [ 1732 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 1733 { "class": "CL", "usage": "use" }, 1734 { "class": "FLAGS", "usage": "def" } 1735 ] 1736 }, 1737 { 1738 "encodings": { 1739 "Roundsd": { "opcodes": [ "66", "0F", "3A", "0B" ] } 1740 }, 1741 "args": [ 1742 { "class": "FpReg64", "usage": "def" }, 1743 { "class": "FpReg64/VecMem64", "usage": "use" }, 1744 { "class": "Imm8" } 1745 ] 1746 }, 1747 { 1748 "encodings": { 1749 "Roundss": { "opcodes": [ "66", "0F", "3A", "0A" ] } 1750 }, 1751 "args": [ 1752 { "class": "FpReg32", "usage": "def" }, 1753 { "class": "FpReg32/VecMem32", "usage": "use" }, 1754 { "class": "Imm8" } 1755 ] 1756 }, 1757 { 1758 "encodings": { 1759 "Sahf": { "opcodes": [ "9E" ] } 1760 }, 1761 "args": [ 1762 { "class": "EAX", "usage": "use" }, 1763 { "class": "FLAGS", "usage": "def" } 1764 ] 1765 }, 1766 { 1767 "encodings": { 1768 "Setcc": { "opcodes": [ "0F", "90", "0" ] } 1769 }, 1770 "args": [ 1771 { "class": "Cond" }, 1772 { "class": "GeneralReg8/Mem8", "usage": "def" }, 1773 { "class": "FLAGS", "usage": "use" } 1774 ] 1775 }, 1776 { 1777 "encodings": { 1778 "Shldl": { "opcodes": [ "0F", "A4" ], "reg_to_rm": true }, 1779 "Shrdl": { "opcodes": [ "0F", "AC" ], "reg_to_rm": true } 1780 }, 1781 "args": [ 1782 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1783 { "class": "GeneralReg32", "usage": "use" }, 1784 { "class": "Imm8" }, 1785 { "class": "FLAGS", "usage": "def" } 1786 ] 1787 }, 1788 { 1789 "encodings": { 1790 "ShldlByCl": { "opcodes": [ "0F", "A5" ], "reg_to_rm": true }, 1791 "ShrdlByCl": { "opcodes": [ "0F", "AD" ], "reg_to_rm": true } 1792 }, 1793 "args": [ 1794 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1795 { "class": "GeneralReg32", "usage": "use" }, 1796 { "class": "CL", "usage": "use" }, 1797 { "class": "FLAGS", "usage": "def" } 1798 ] 1799 }, 1800 { 1801 "encodings": { 1802 "Shufpd": { "opcodes": [ "66", "0F", "C6" ] }, 1803 "Shufps": { "opcodes": [ "0F", "C6" ] } 1804 }, 1805 "args": [ 1806 { "class": "VecReg128", "usage": "use_def" }, 1807 { "class": "VecReg128/VecMem128", "usage": "use" }, 1808 { "class": "Imm8" } 1809 ] 1810 }, 1811 { 1812 "encodings": { 1813 "Sqrtsd": { "opcodes": [ "F2", "0F", "51" ] } 1814 }, 1815 "args": [ 1816 { "class": "FpReg64", "usage": "def" }, 1817 { "class": "FpReg64/VecMem64", "usage": "use" } 1818 ] 1819 }, 1820 { 1821 "encodings": { 1822 "Sqrtss": { "opcodes": [ "F3", "0F", "51" ] } 1823 }, 1824 "args": [ 1825 { "class": "FpReg32", "usage": "def" }, 1826 { "class": "FpReg32/VecMem32", "usage": "use" } 1827 ] 1828 }, 1829 { 1830 "encodings": { 1831 "Ucomisd": { "opcodes": [ "66", "0F", "2E" ] } 1832 }, 1833 "args": [ 1834 { "class": "FpReg64", "usage": "use" }, 1835 { "class": "FpReg64/VecMem64", "usage": "use" }, 1836 { "class": "FLAGS", "usage": "def" } 1837 ] 1838 }, 1839 { 1840 "encodings": { 1841 "Ucomiss": { "opcodes": [ "0F", "2E" ] } 1842 }, 1843 "args": [ 1844 { "class": "FpReg32", "usage": "use" }, 1845 { "class": "FpReg32/VecMem32", "usage": "use" }, 1846 { "class": "FLAGS", "usage": "def" } 1847 ] 1848 }, 1849 { 1850 "encodings": { 1851 "Vaddpd": { "opcodes": [ "C4", "01", "01", "58" ], "vex_rm_to_reg": true }, 1852 "Vaddps": { "opcodes": [ "C4", "01", "00", "58" ], "vex_rm_to_reg": true }, 1853 "Vandpd": { "opcodes": [ "C4", "01", "01", "54" ], "vex_rm_to_reg": true }, 1854 "Vandps": { "opcodes": [ "C4", "01", "00", "54" ], "vex_rm_to_reg": true }, 1855 "Vcmpeqpd": { "opcodes": [ "C4", "01", "01", "C2", "00" ], "vex_rm_to_reg": true }, 1856 "Vcmpeqps": { "opcodes": [ "C4", "01", "00", "C2", "00" ], "vex_rm_to_reg": true }, 1857 "Vcmplepd": { "opcodes": [ "C4", "01", "01", "C2", "02" ], "vex_rm_to_reg": true }, 1858 "Vcmpleps": { "opcodes": [ "C4", "01", "00", "C2", "02" ], "vex_rm_to_reg": true }, 1859 "Vcmpltpd": { "opcodes": [ "C4", "01", "01", "C2", "01" ], "vex_rm_to_reg": true }, 1860 "Vcmpltps": { "opcodes": [ "C4", "01", "00", "C2", "01" ], "vex_rm_to_reg": true }, 1861 "Vcmpneqpd": { "opcodes": [ "C4", "01", "01", "C2", "04" ], "vex_rm_to_reg": true }, 1862 "Vcmpneqps": { "opcodes": [ "C4", "01", "00", "C2", "04" ], "vex_rm_to_reg": true }, 1863 "Vcmpnlepd": { "opcodes": [ "C4", "01", "01", "C2", "06" ], "vex_rm_to_reg": true }, 1864 "Vcmpnleps": { "opcodes": [ "C4", "01", "00", "C2", "06" ], "vex_rm_to_reg": true }, 1865 "Vcmpnltpd": { "opcodes": [ "C4", "01", "01", "C2", "05" ], "vex_rm_to_reg": true }, 1866 "Vcmpnltps": { "opcodes": [ "C4", "01", "00", "C2", "05" ], "vex_rm_to_reg": true }, 1867 "Vcmpordpd": { "opcodes": [ "C4", "01", "01", "C2", "07" ], "vex_rm_to_reg": true }, 1868 "Vcmpordps": { "opcodes": [ "C4", "01", "00", "C2", "07" ], "vex_rm_to_reg": true }, 1869 "Vcmpunordpd": { "opcodes": [ "C4", "01", "01", "C2", "03" ], "vex_rm_to_reg": true }, 1870 "Vcmpunordps": { "opcodes": [ "C4", "01", "00", "C2", "03" ], "vex_rm_to_reg": true }, 1871 "Vdivpd": { "opcodes": [ "C4", "01", "01", "5E" ], "vex_rm_to_reg": true }, 1872 "Vdivps": { "opcodes": [ "C4", "01", "00", "5E" ], "vex_rm_to_reg": true }, 1873 "Vhaddpd": { "opcodes": [ "C4", "01", "01", "7C" ], "vex_rm_to_reg": true }, 1874 "Vhaddps": { "opcodes": [ "C4", "01", "03", "7C" ], "vex_rm_to_reg": true }, 1875 "Vmaxpd": { "opcodes": [ "C4", "01", "01", "5F" ], "vex_rm_to_reg": true }, 1876 "Vmaxps": { "opcodes": [ "C4", "01", "00", "5F" ], "vex_rm_to_reg": true }, 1877 "Vminpd": { "opcodes": [ "C4", "01", "01", "5D" ], "vex_rm_to_reg": true }, 1878 "Vminps": { "opcodes": [ "C4", "01", "00", "5D" ], "vex_rm_to_reg": true }, 1879 "Vmulpd": { "opcodes": [ "C4", "01", "01", "59" ], "vex_rm_to_reg": true }, 1880 "Vmulps": { "opcodes": [ "C4", "01", "00", "59" ], "vex_rm_to_reg": true }, 1881 "Vorpd": { "opcodes": [ "C4", "01", "01", "56" ], "vex_rm_to_reg": true }, 1882 "Vorps": { "opcodes": [ "C4", "01", "00", "56" ], "vex_rm_to_reg": true }, 1883 "Vpackssdw": { "opcodes": [ "C4", "01", "01", "6B" ], "vex_rm_to_reg": true }, 1884 "Vpacksswb": { "opcodes": [ "C4", "01", "01", "63" ], "vex_rm_to_reg": true }, 1885 "Vpackusdw": { "opcodes": [ "C4", "02", "01", "2B" ], "vex_rm_to_reg": true }, 1886 "Vpackuswb": { "opcodes": [ "C4", "01", "01", "67" ], "vex_rm_to_reg": true }, 1887 "Vpaddb": { "opcodes": [ "C4", "01", "01", "FC" ], "vex_rm_to_reg": true }, 1888 "Vpaddd": { "opcodes": [ "C4", "01", "01", "FE" ], "vex_rm_to_reg": true }, 1889 "Vpaddq": { "opcodes": [ "C4", "01", "01", "D4" ], "vex_rm_to_reg": true }, 1890 "Vpaddsb": { "opcodes": [ "C4", "01", "01", "EC" ], "vex_rm_to_reg": true }, 1891 "Vpaddsw": { "opcodes": [ "C4", "01", "01", "ED" ], "vex_rm_to_reg": true }, 1892 "Vpaddusb": { "opcodes": [ "C4", "01", "01", "DC" ], "vex_rm_to_reg": true }, 1893 "Vpaddusw": { "opcodes": [ "C4", "01", "01", "DD" ], "vex_rm_to_reg": true }, 1894 "Vpaddw": { "opcodes": [ "C4", "01", "01", "FD" ], "vex_rm_to_reg": true }, 1895 "Vpand": { "opcodes": [ "C4", "01", "01", "DB" ], "vex_rm_to_reg": true }, 1896 "Vpandn": { "opcodes": [ "C4", "01", "01", "DF" ], "vex_rm_to_reg": true }, 1897 "Vpavgb": { "opcodes": [ "C4", "01", "01", "E0" ], "vex_rm_to_reg": true }, 1898 "Vpavgw": { "opcodes": [ "C4", "01", "01", "E3" ], "vex_rm_to_reg": true }, 1899 "Vpcmpeqb": { "opcodes": [ "C4", "01", "01", "74" ], "vex_rm_to_reg": true }, 1900 "Vpcmpeqd": { "opcodes": [ "C4", "01", "01", "76" ], "vex_rm_to_reg": true }, 1901 "Vpcmpeqq": { "opcodes": [ "C4", "02", "01", "29" ], "vex_rm_to_reg": true }, 1902 "Vpcmpeqw": { "opcodes": [ "C4", "01", "01", "75" ], "vex_rm_to_reg": true }, 1903 "Vpcmpgtb": { "opcodes": [ "C4", "01", "01", "64" ], "vex_rm_to_reg": true }, 1904 "Vpcmpgtd": { "opcodes": [ "C4", "01", "01", "66" ], "vex_rm_to_reg": true }, 1905 "Vpcmpgtq": { "opcodes": [ "C4", "02", "01", "37" ], "vex_rm_to_reg": true }, 1906 "Vpcmpgtw": { "opcodes": [ "C4", "01", "01", "65" ], "vex_rm_to_reg": true }, 1907 "Vpmaxsb": { "opcodes": [ "C4", "02", "01", "3C" ], "vex_rm_to_reg": true }, 1908 "Vpmaxsd": { "opcodes": [ "C4", "02", "01", "3D" ], "vex_rm_to_reg": true }, 1909 "Vpmaxsw": { "opcodes": [ "C4", "01", "01", "EE" ], "vex_rm_to_reg": true }, 1910 "Vpmaxub": { "opcodes": [ "C4", "01", "01", "DE" ], "vex_rm_to_reg": true }, 1911 "Vpmaxud": { "opcodes": [ "C4", "02", "01", "3F" ], "vex_rm_to_reg": true }, 1912 "Vpmaxuw": { "opcodes": [ "C4", "02", "01", "3E" ], "vex_rm_to_reg": true }, 1913 "Vpminsb": { "opcodes": [ "C4", "02", "01", "38" ], "vex_rm_to_reg": true }, 1914 "Vpminsd": { "opcodes": [ "C4", "02", "01", "39" ], "vex_rm_to_reg": true }, 1915 "Vpminsw": { "opcodes": [ "C4", "01", "01", "EA" ], "vex_rm_to_reg": true }, 1916 "Vpminub": { "opcodes": [ "C4", "01", "01", "DA" ], "vex_rm_to_reg": true }, 1917 "Vpminud": { "opcodes": [ "C4", "02", "01", "3B" ], "vex_rm_to_reg": true }, 1918 "Vpminuw": { "opcodes": [ "C4", "02", "01", "3A" ], "vex_rm_to_reg": true }, 1919 "Vpmulhrsw": { "opcodes": [ "C4", "02", "01", "0B" ], "vex_rm_to_reg": true }, 1920 "Vpmulhw": { "opcodes": [ "C4", "01", "01", "E5" ], "vex_rm_to_reg": true }, 1921 "Vpmulld": { "opcodes": [ "C4", "02", "01", "40" ], "vex_rm_to_reg": true }, 1922 "Vpmullw": { "opcodes": [ "C4", "01", "01", "D5" ], "vex_rm_to_reg": true }, 1923 "Vpmuludq": { "opcodes": [ "C4", "01", "01", "F4" ], "vex_rm_to_reg": true }, 1924 "Vpor": { "opcodes": [ "C4", "01", "01", "EB" ], "vex_rm_to_reg": true }, 1925 "Vpsadbw": { "opcodes": [ "C4", "01", "01", "F6" ], "vex_rm_to_reg": true }, 1926 "Vpshufb": { "opcodes": [ "C4", "02", "01", "00" ], "vex_rm_to_reg": true }, 1927 "Vpslld": { "opcodes": [ "C4", "01", "01", "F2" ], "vex_rm_to_reg": true }, 1928 "Vpsllq": { "opcodes": [ "C4", "01", "01", "F3" ], "vex_rm_to_reg": true }, 1929 "Vpsllw": { "opcodes": [ "C4", "01", "01", "F1" ], "vex_rm_to_reg": true }, 1930 "Vpsrad": { "opcodes": [ "C4", "01", "01", "E2" ], "vex_rm_to_reg": true }, 1931 "Vpsraw": { "opcodes": [ "C4", "01", "01", "E1" ], "vex_rm_to_reg": true }, 1932 "Vpsrld": { "opcodes": [ "C4", "01", "01", "D2" ], "vex_rm_to_reg": true }, 1933 "Vpsrlq": { "opcodes": [ "C4", "01", "01", "D3" ], "vex_rm_to_reg": true }, 1934 "Vpsrlw": { "opcodes": [ "C4", "01", "01", "D1" ], "vex_rm_to_reg": true }, 1935 "Vpsubb": { "opcodes": [ "C4", "01", "01", "F8" ], "vex_rm_to_reg": true }, 1936 "Vpsubd": { "opcodes": [ "C4", "01", "01", "FA" ], "vex_rm_to_reg": true }, 1937 "Vpsubq": { "opcodes": [ "C4", "01", "01", "FB" ], "vex_rm_to_reg": true }, 1938 "Vpsubsb": { "opcodes": [ "C4", "01", "01", "E8" ], "vex_rm_to_reg": true }, 1939 "Vpsubsw": { "opcodes": [ "C4", "01", "01", "E9" ], "vex_rm_to_reg": true }, 1940 "Vpsubusb": { "opcodes": [ "C4", "01", "01", "D8" ], "vex_rm_to_reg": true }, 1941 "Vpsubusw": { "opcodes": [ "C4", "01", "01", "D9" ], "vex_rm_to_reg": true }, 1942 "Vpsubw": { "opcodes": [ "C4", "01", "01", "F9" ], "vex_rm_to_reg": true }, 1943 "Vpunpckhbw": { "opcodes": [ "C4", "01", "01", "68" ], "vex_rm_to_reg": true }, 1944 "Vpunpckhdq": { "opcodes": [ "C4", "01", "01", "6A" ], "vex_rm_to_reg": true }, 1945 "Vpunpckhqdq": { "opcodes": [ "C4", "01", "01", "6D" ], "vex_rm_to_reg": true }, 1946 "Vpunpckhwd": { "opcodes": [ "C4", "01", "01", "69" ], "vex_rm_to_reg": true }, 1947 "Vpunpcklbw": { "opcodes": [ "C4", "01", "01", "60" ], "vex_rm_to_reg": true }, 1948 "Vpunpckldq": { "opcodes": [ "C4", "01", "01", "62" ], "vex_rm_to_reg": true }, 1949 "Vpunpcklqdq": { "opcodes": [ "C4", "01", "01", "6C" ], "vex_rm_to_reg": true }, 1950 "Vpunpcklwd": { "opcodes": [ "C4", "01", "01", "61" ], "vex_rm_to_reg": true }, 1951 "Vpxor": { "opcodes": [ "C4", "01", "01", "EF" ], "vex_rm_to_reg": true }, 1952 "Vsubpd": { "opcodes": [ "C4", "01", "01", "5C" ], "vex_rm_to_reg": true }, 1953 "Vsubps": { "opcodes": [ "C4", "01", "00", "5C" ], "vex_rm_to_reg": true }, 1954 "Vxorpd": { "opcodes": [ "C4", "01", "01", "57" ], "vex_rm_to_reg": true }, 1955 "Vxorps": { "opcodes": [ "C4", "01", "00", "57" ], "vex_rm_to_reg": true } 1956 }, 1957 "args": [ 1958 { "class": "VecReg128", "usage": "def" }, 1959 { "class": "VecReg128", "usage": "use" }, 1960 { "class": "VecReg128/VecMem128", "usage": "use" } 1961 ] 1962 }, 1963 { 1964 "encodings": { 1965 "Vaddsd": { "opcodes": [ "C4", "01", "03", "58" ], "vex_rm_to_reg": true }, 1966 "Vcmpeqsd": { "opcodes": [ "C4", "01", "03", "C2", "00" ], "vex_rm_to_reg": true }, 1967 "Vcmplesd": { "opcodes": [ "C4", "01", "03", "C2", "02" ], "vex_rm_to_reg": true }, 1968 "Vcmpltsd": { "opcodes": [ "C4", "01", "03", "C2", "01" ], "vex_rm_to_reg": true }, 1969 "Vcmpneqsd": { "opcodes": [ "C4", "01", "03", "C2", "04" ], "vex_rm_to_reg": true }, 1970 "Vcmpnlesd": { "opcodes": [ "C4", "01", "03", "C2", "06" ], "vex_rm_to_reg": true }, 1971 "Vcmpnltsd": { "opcodes": [ "C4", "01", "03", "C2", "05" ], "vex_rm_to_reg": true }, 1972 "Vcmpordsd": { "opcodes": [ "C4", "01", "03", "C2", "07" ], "vex_rm_to_reg": true }, 1973 "Vcmpunordsd": { "opcodes": [ "C4", "01", "03", "C2", "03" ], "vex_rm_to_reg": true }, 1974 "Vdivsd": { "opcodes": [ "C4", "01", "03", "5E" ], "vex_rm_to_reg": true }, 1975 "Vmulsd": { "opcodes": [ "C4", "01", "03", "59" ], "vex_rm_to_reg": true }, 1976 "Vsubsd": { "opcodes": [ "C4", "01", "03", "5C" ], "vex_rm_to_reg": true } 1977 }, 1978 "args": [ 1979 { "class": "FpReg64", "usage": "def" }, 1980 { "class": "FpReg64", "usage": "use" }, 1981 { "class": "FpReg64/VecMem64", "usage": "use" } 1982 ] 1983 }, 1984 { 1985 "encodings": { 1986 "Vaddss": { "opcodes": [ "C4", "01", "02", "58" ], "vex_rm_to_reg": true }, 1987 "Vcmpeqss": { "opcodes": [ "C4", "01", "02", "C2", "00" ], "vex_rm_to_reg": true }, 1988 "Vcmpless": { "opcodes": [ "C4", "01", "02", "C2", "02" ], "vex_rm_to_reg": true }, 1989 "Vcmpltss": { "opcodes": [ "C4", "01", "02", "C2", "01" ], "vex_rm_to_reg": true }, 1990 "Vcmpneqss": { "opcodes": [ "C4", "01", "02", "C2", "04" ], "vex_rm_to_reg": true }, 1991 "Vcmpnless": { "opcodes": [ "C4", "01", "02", "C2", "06" ], "vex_rm_to_reg": true }, 1992 "Vcmpnltss": { "opcodes": [ "C4", "01", "02", "C2", "05" ], "vex_rm_to_reg": true }, 1993 "Vcmpordss": { "opcodes": [ "C4", "01", "02", "C2", "07" ], "vex_rm_to_reg": true }, 1994 "Vcmpunordss": { "opcodes": [ "C4", "01", "02", "C2", "03" ], "vex_rm_to_reg": true }, 1995 "Vdivss": { "opcodes": [ "C4", "01", "02", "5E" ], "vex_rm_to_reg": true }, 1996 "Vmulss": { "opcodes": [ "C4", "01", "02", "59" ], "vex_rm_to_reg": true }, 1997 "Vsubss": { "opcodes": [ "C4", "01", "02", "5C" ], "vex_rm_to_reg": true } 1998 }, 1999 "args": [ 2000 { "class": "FpReg32", "usage": "def" }, 2001 { "class": "FpReg32", "usage": "use" }, 2002 { "class": "FpReg32/VecMem32", "usage": "use" } 2003 ] 2004 }, 2005 { 2006 "encodings": { 2007 "Vcvtsd2ss": { "opcodes": [ "C4", "01", "03", "5A" ], "vex_rm_to_reg": true } 2008 }, 2009 "args": [ 2010 { "class": "FpReg32", "usage": "def" }, 2011 { "class": "XmmReg", "usage": "use" }, 2012 { "class": "FpReg64/VecMem64", "usage": "use" } 2013 ] 2014 }, 2015 { 2016 "encodings": { 2017 "Vcvtsi2sdl": { "opcodes": [ "C4", "01", "03", "2A" ], "vex_rm_to_reg": true } 2018 }, 2019 "args": [ 2020 { "class": "FpReg64", "usage": "def" }, 2021 { "class": "XmmReg", "usage": "use" }, 2022 { "class": "GeneralReg32/Mem32", "usage": "use" } 2023 ] 2024 }, 2025 { 2026 "encodings": { 2027 "Vcvtsi2ssl": { "opcodes": [ "C4", "01", "02", "2A" ], "vex_rm_to_reg": true } 2028 }, 2029 "args": [ 2030 { "class": "FpReg32", "usage": "def" }, 2031 { "class": "XmmReg", "usage": "use" }, 2032 { "class": "GeneralReg32/Mem32", "usage": "use" } 2033 ] 2034 }, 2035 { 2036 "encodings": { 2037 "Vcvtss2sd": { "opcodes": [ "C4", "01", "02", "5A" ], "vex_rm_to_reg": true } 2038 }, 2039 "args": [ 2040 { "class": "FpReg64", "usage": "def" }, 2041 { "class": "XmmReg", "usage": "use" }, 2042 { "class": "FpReg32/VecMem32", "usage": "use" } 2043 ] 2044 }, 2045 { 2046 "encodings": { 2047 "Vfmadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "98" ], "vex_rm_to_reg": true }, 2048 "Vfmadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "98" ], "vex_rm_to_reg": true }, 2049 "Vfmadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A8" ], "vex_rm_to_reg": true }, 2050 "Vfmadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A8" ], "vex_rm_to_reg": true }, 2051 "Vfmadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B8" ], "vex_rm_to_reg": true }, 2052 "Vfmadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B8" ], "vex_rm_to_reg": true }, 2053 "Vfmaddsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "96" ], "vex_rm_to_reg": true }, 2054 "Vfmaddsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "96" ], "vex_rm_to_reg": true }, 2055 "Vfmaddsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A6" ], "vex_rm_to_reg": true }, 2056 "Vfmaddsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A6" ], "vex_rm_to_reg": true }, 2057 "Vfmaddsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B6" ], "vex_rm_to_reg": true }, 2058 "Vfmaddsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B6" ], "vex_rm_to_reg": true }, 2059 "Vfmsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9A" ], "vex_rm_to_reg": true }, 2060 "Vfmsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9A" ], "vex_rm_to_reg": true }, 2061 "Vfmsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AA" ], "vex_rm_to_reg": true }, 2062 "Vfmsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AA" ], "vex_rm_to_reg": true }, 2063 "Vfmsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BA" ], "vex_rm_to_reg": true }, 2064 "Vfmsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BA" ], "vex_rm_to_reg": true }, 2065 "Vfmsubadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "97" ], "vex_rm_to_reg": true }, 2066 "Vfmsubadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "97" ], "vex_rm_to_reg": true }, 2067 "Vfmsubadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A7" ], "vex_rm_to_reg": true }, 2068 "Vfmsubadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A7" ], "vex_rm_to_reg": true }, 2069 "Vfmsubadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B7" ], "vex_rm_to_reg": true }, 2070 "Vfmsubadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B7" ], "vex_rm_to_reg": true }, 2071 "Vfnmadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9C" ], "vex_rm_to_reg": true }, 2072 "Vfnmadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9C" ], "vex_rm_to_reg": true }, 2073 "Vfnmadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AC" ], "vex_rm_to_reg": true }, 2074 "Vfnmadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AC" ], "vex_rm_to_reg": true }, 2075 "Vfnmadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BC" ], "vex_rm_to_reg": true }, 2076 "Vfnmadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BC" ], "vex_rm_to_reg": true }, 2077 "Vfnmsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9E" ], "vex_rm_to_reg": true }, 2078 "Vfnmsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9E" ], "vex_rm_to_reg": true }, 2079 "Vfnmsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AE" ], "vex_rm_to_reg": true }, 2080 "Vfnmsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AE" ], "vex_rm_to_reg": true }, 2081 "Vfnmsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BE" ], "vex_rm_to_reg": true }, 2082 "Vfnmsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BE" ], "vex_rm_to_reg": true } 2083 }, 2084 "args": [ 2085 { "class": "VecReg128", "usage": "use_def" }, 2086 { "class": "VecReg128", "usage": "use" }, 2087 { "class": "VecReg128/VecMem128", "usage": "use" } 2088 ] 2089 }, 2090 { 2091 "encodings": { 2092 "Vfmadd132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "99" ], "vex_rm_to_reg": true }, 2093 "Vfmadd213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A9" ], "vex_rm_to_reg": true }, 2094 "Vfmadd231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B9" ], "vex_rm_to_reg": true }, 2095 "Vfmsub132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9B" ], "vex_rm_to_reg": true }, 2096 "Vfmsub213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AB" ], "vex_rm_to_reg": true }, 2097 "Vfmsub231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BB" ], "vex_rm_to_reg": true }, 2098 "Vfnmadd132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9D" ], "vex_rm_to_reg": true }, 2099 "Vfnmadd213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AD" ], "vex_rm_to_reg": true }, 2100 "Vfnmadd231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BD" ], "vex_rm_to_reg": true }, 2101 "Vfnmsub132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9F" ], "vex_rm_to_reg": true }, 2102 "Vfnmsub213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AF" ], "vex_rm_to_reg": true }, 2103 "Vfnmsub231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BF" ], "vex_rm_to_reg": true } 2104 }, 2105 "args": [ 2106 { "class": "XmmReg", "usage": "use_def" }, 2107 { "class": "XmmReg", "usage": "use" }, 2108 { "class": "XmmReg/VecMem64", "usage": "use" } 2109 ] 2110 }, 2111 { 2112 "encodings": { 2113 "Vfmadd132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "99" ], "vex_rm_to_reg": true }, 2114 "Vfmadd213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A9" ], "vex_rm_to_reg": true }, 2115 "Vfmadd231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B9" ], "vex_rm_to_reg": true }, 2116 "Vfmsub132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9B" ], "vex_rm_to_reg": true }, 2117 "Vfmsub213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AB" ], "vex_rm_to_reg": true }, 2118 "Vfmsub231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BB" ], "vex_rm_to_reg": true }, 2119 "Vfnmadd132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9D" ], "vex_rm_to_reg": true }, 2120 "Vfnmadd213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AD" ], "vex_rm_to_reg": true }, 2121 "Vfnmadd231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BD" ], "vex_rm_to_reg": true }, 2122 "Vfnmsub132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9F" ], "vex_rm_to_reg": true }, 2123 "Vfnmsub213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AF" ], "vex_rm_to_reg": true }, 2124 "Vfnmsub231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BF" ], "vex_rm_to_reg": true } 2125 }, 2126 "args": [ 2127 { "class": "XmmReg", "usage": "use_def" }, 2128 { "class": "XmmReg", "usage": "use" }, 2129 { "class": "XmmReg/VecMem32", "usage": "use" } 2130 ] 2131 }, 2132 { 2133 "encodings": { 2134 "Vfmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "69" ], "vex_rm_imm_to_reg": true }, 2135 "Vfmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "68" ], "vex_rm_imm_to_reg": true }, 2136 "Vfmaddsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5D" ], "vex_rm_imm_to_reg": true }, 2137 "Vfmaddsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5C" ], "vex_rm_imm_to_reg": true }, 2138 "Vfmsubaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5F" ], "vex_rm_imm_to_reg": true }, 2139 "Vfmsubaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5E" ], "vex_rm_imm_to_reg": true }, 2140 "Vfmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6D" ], "vex_rm_imm_to_reg": true }, 2141 "Vfmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6C" ], "vex_rm_imm_to_reg": true }, 2142 "Vfnmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "79" ], "vex_rm_imm_to_reg": true }, 2143 "Vfnmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "78" ], "vex_rm_imm_to_reg": true }, 2144 "Vfnmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7D" ], "vex_rm_imm_to_reg": true }, 2145 "Vfnmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7C" ], "vex_rm_imm_to_reg": true } 2146 }, 2147 "args": [ 2148 { "class": "VecReg128", "usage": "def" }, 2149 { "class": "VecReg128", "usage": "use" }, 2150 { "class": "VecMem128", "usage": "use" }, 2151 { "class": "VecReg128", "usage": "use" } 2152 ] 2153 }, 2154 { 2155 "encodings": { 2156 "Vfmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "69" ], "vex_imm_rm_to_reg": true }, 2157 "Vfmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "68" ], "vex_imm_rm_to_reg": true }, 2158 "Vfmaddsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5D" ], "vex_imm_rm_to_reg": true }, 2159 "Vfmaddsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5C" ], "vex_imm_rm_to_reg": true }, 2160 "Vfmsubaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5F" ], "vex_imm_rm_to_reg": true }, 2161 "Vfmsubaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5E" ], "vex_imm_rm_to_reg": true }, 2162 "Vfmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6D" ], "vex_imm_rm_to_reg": true }, 2163 "Vfmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6C" ], "vex_imm_rm_to_reg": true }, 2164 "Vfnmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "79" ], "vex_imm_rm_to_reg": true }, 2165 "Vfnmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "78" ], "vex_imm_rm_to_reg": true }, 2166 "Vfnmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7D" ], "vex_imm_rm_to_reg": true }, 2167 "Vfnmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7C" ], "vex_imm_rm_to_reg": true } 2168 }, 2169 "args": [ 2170 { "class": "VecReg128", "usage": "def" }, 2171 { "class": "VecReg128", "usage": "use" }, 2172 { "class": "VecReg128", "usage": "use" }, 2173 { "class": "VecReg128/VecMem128", "usage": "use" } 2174 ] 2175 }, 2176 { 2177 "encodings": { 2178 "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6B" ], "vex_rm_imm_to_reg": true }, 2179 "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6F" ], "vex_rm_imm_to_reg": true }, 2180 "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7B" ], "vex_rm_imm_to_reg": true }, 2181 "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7F" ], "vex_rm_imm_to_reg": true } 2182 }, 2183 "args": [ 2184 { "class": "XmmReg", "usage": "def" }, 2185 { "class": "XmmReg", "usage": "use" }, 2186 { "class": "VecMem64", "usage": "use" }, 2187 { "class": "XmmReg", "usage": "use" } 2188 ] 2189 }, 2190 { 2191 "encodings": { 2192 "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6B" ], "vex_imm_rm_to_reg": true }, 2193 "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6F" ], "vex_imm_rm_to_reg": true }, 2194 "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7B" ], "vex_imm_rm_to_reg": true }, 2195 "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7F" ], "vex_imm_rm_to_reg": true } 2196 }, 2197 "args": [ 2198 { "class": "XmmReg", "usage": "def" }, 2199 { "class": "XmmReg", "usage": "use" }, 2200 { "class": "XmmReg", "usage": "use" }, 2201 { "class": "XmmReg/VecMem64", "usage": "use" } 2202 ] 2203 }, 2204 { 2205 "encodings": { 2206 "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6A" ], "vex_rm_imm_to_reg": true }, 2207 "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6E" ], "vex_rm_imm_to_reg": true }, 2208 "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7A" ], "vex_rm_imm_to_reg": true }, 2209 "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7E" ], "vex_rm_imm_to_reg": true } 2210 }, 2211 "args": [ 2212 { "class": "XmmReg", "usage": "def" }, 2213 { "class": "XmmReg", "usage": "use" }, 2214 { "class": "VecMem32", "usage": "use" }, 2215 { "class": "XmmReg", "usage": "use" } 2216 ] 2217 }, 2218 { 2219 "encodings": { 2220 "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6A" ], "vex_imm_rm_to_reg": true }, 2221 "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6E" ], "vex_imm_rm_to_reg": true }, 2222 "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7A" ], "vex_imm_rm_to_reg": true }, 2223 "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7E" ], "vex_imm_rm_to_reg": true } 2224 }, 2225 "args": [ 2226 { "class": "XmmReg", "usage": "def" }, 2227 { "class": "XmmReg", "usage": "use" }, 2228 { "class": "XmmReg", "usage": "use" }, 2229 { "class": "XmmReg/VecMem32", "usage": "use" } 2230 ] 2231 }, 2232 { 2233 "encodings": { 2234 "Vmovapd": { "opcodes": [ "C4", "01", "01", "28" ] }, 2235 "Vmovaps": { "opcodes": [ "C4", "01", "00", "28" ] } 2236 }, 2237 "args": [ 2238 { "class": "XmmReg", "usage": "def" }, 2239 { "class": "VecMem128", "usage": "use" } 2240 ] 2241 }, 2242 { 2243 "encodings": { 2244 "Vmovdqa": { "opcodes": [ "C4", "01", "01", "6F" ] }, 2245 "Vmovdqu": { "opcodes": [ "C4", "01", "02", "6F" ] } 2246 }, 2247 "args": [ 2248 { "class": "XmmReg", "usage": "def" }, 2249 { "class": "VecMem128", "usage": "use" } 2250 ] 2251 }, 2252 { 2253 "encodings": { 2254 "Vmovhlps": { "opcodes": [ "C4", "01", "00", "12" ], "vex_rm_to_reg": true }, 2255 "Vmovlhps": { "opcodes": [ "C4", "01", "00", "16" ], "vex_rm_to_reg": true } 2256 }, 2257 "args": [ 2258 { "class": "XmmReg", "usage": "def" }, 2259 { "class": "XmmReg", "usage": "use" }, 2260 { "class": "XmmReg", "usage": "use" } 2261 ] 2262 }, 2263 { 2264 "encodings": { 2265 "Vmovhpd": { "opcodes": [ "C4", "01", "01", "16" ] }, 2266 "Vmovhps": { "opcodes": [ "C4", "01", "00", "16" ] }, 2267 "Vmovlpd": { "opcodes": [ "C4", "01", "01", "12" ] }, 2268 "Vmovlps": { "opcodes": [ "C4", "01", "00", "12" ] } 2269 }, 2270 "args": [ 2271 { "class": "XmmReg", "usage": "def" }, 2272 { "class": "XmmReg", "usage": "use" }, 2273 { "class": "VecMem64", "usage": "use" } 2274 ] 2275 }, 2276 { 2277 "encodings": { 2278 "Vpermil2pd": { "opcodes": [ "C4", "03", "81", "49" ], "vex_imm_rm_to_reg": true }, 2279 "Vpermil2ps": { "opcodes": [ "C4", "03", "81", "48" ], "vex_imm_rm_to_reg": true } 2280 }, 2281 "args": [ 2282 { "class": "VecReg128", "usage": "def" }, 2283 { "class": "VecReg128", "usage": "use" }, 2284 { "class": "VecReg128", "usage": "use" }, 2285 { "class": "VecMem128", "usage": "use" }, 2286 { "class": "Imm2" } 2287 ] 2288 }, 2289 { 2290 "encodings": { 2291 "Vpermil2pd": { "opcodes": [ "C4", "03", "01", "49" ], "vex_rm_imm_to_reg": true }, 2292 "Vpermil2ps": { "opcodes": [ "C4", "03", "01", "48" ], "vex_rm_imm_to_reg": true } 2293 }, 2294 "args": [ 2295 { "class": "VecReg128", "usage": "def" }, 2296 { "class": "VecReg128", "usage": "use" }, 2297 { "class": "VecReg128/VecMem128", "usage": "use" }, 2298 { "class": "VecReg128", "usage": "use" }, 2299 { "class": "Imm2" } 2300 ] 2301 }, 2302 { 2303 "encodings": { 2304 "Vpinsrb": { "opcodes": [ "C4", "03", "01", "20" ], "vex_rm_to_reg": true }, 2305 "Vpinsrd": { "opcodes": [ "C4", "03", "01", "22" ], "vex_rm_to_reg": true }, 2306 "Vpinsrw": { "opcodes": [ "C4", "01", "01", "C4" ], "vex_rm_to_reg": true } 2307 }, 2308 "args": [ 2309 { "class": "VecReg128", "usage": "use_def" }, 2310 { "class": "VecReg128", "usage": "use" }, 2311 { "class": "GeneralReg32", "usage": "use" }, 2312 { "class": "Imm8" } 2313 ] 2314 }, 2315 { 2316 "encodings": { 2317 "Vpslld": { "opcodes": [ "C4", "01", "01", "72", "6" ], "rm_to_vex": true }, 2318 "Vpslldq": { "opcodes": [ "C4", "01", "01", "73", "7" ], "rm_to_vex": true }, 2319 "Vpsllq": { "opcodes": [ "C4", "01", "01", "73", "6" ], "rm_to_vex": true }, 2320 "Vpsllw": { "opcodes": [ "C4", "01", "01", "71", "6" ], "rm_to_vex": true }, 2321 "Vpsrad": { "opcodes": [ "C4", "01", "01", "72", "4" ], "rm_to_vex": true }, 2322 "Vpsraw": { "opcodes": [ "C4", "01", "01", "71", "4" ], "rm_to_vex": true }, 2323 "Vpsrld": { "opcodes": [ "C4", "01", "01", "72", "2" ], "rm_to_vex": true }, 2324 "Vpsrldq": { "opcodes": [ "C4", "01", "01", "73", "3" ], "rm_to_vex": true }, 2325 "Vpsrlq": { "opcodes": [ "C4", "01", "01", "73", "2" ], "rm_to_vex": true }, 2326 "Vpsrlw": { "opcodes": [ "C4", "01", "01", "71", "2" ], "rm_to_vex": true } 2327 }, 2328 "args": [ 2329 { "class": "VecReg128", "usage": "def" }, 2330 { "class": "VecReg128", "usage": "use" }, 2331 { "class": "Imm8" } 2332 ] 2333 }, 2334 { 2335 "encodings": { 2336 "Vshufpd": { "opcodes": [ "C4", "01", "01", "C6" ], "vex_rm_to_reg": true }, 2337 "Vshufps": { "opcodes": [ "C4", "01", "00", "C6" ], "vex_rm_to_reg": true } 2338 }, 2339 "args": [ 2340 { "class": "VecReg128", "usage": "def" }, 2341 { "class": "VecReg128", "usage": "use" }, 2342 { "class": "VecReg128/VecMem128", "usage": "use" }, 2343 { "class": "Imm8" } 2344 ] 2345 }, 2346 { 2347 "stems": [ "Xchgl" ], 2348 "args": [ 2349 { "class": "GeneralReg32", "usage": "use_def" }, 2350 { "class": "GeneralReg32", "usage": "use_def" } 2351 ] 2352 }, 2353 { 2354 "encodings": { 2355 "Xchgl": { "opcodes": [ "87" ] } 2356 }, 2357 "args": [ 2358 { "class": "GeneralReg32", "usage": "use_def" }, 2359 { "class": "Mem32", "usage": "use_def" } 2360 ] 2361 } 2362 ] 2363} 2364