1 #pragma once
2 #ifndef CPUINFO_H
3 #define CPUINFO_H
4
5 #ifndef __cplusplus
6 #include <stdbool.h>
7 #endif
8
9 #ifdef __APPLE__
10 #include <TargetConditionals.h>
11 #endif
12
13 #include <stdint.h>
14
15 /* Identify architecture and define corresponding macro */
16
17 #if defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(_M_IX86)
18 #define CPUINFO_ARCH_X86 1
19 #endif
20
21 #if defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64)
22 #define CPUINFO_ARCH_X86_64 1
23 #endif
24
25 #if defined(__arm__) || defined(_M_ARM)
26 #define CPUINFO_ARCH_ARM 1
27 #endif
28
29 #if defined(__aarch64__) || defined(_M_ARM64)
30 #define CPUINFO_ARCH_ARM64 1
31 #endif
32
33 #if defined(__PPC64__) || defined(__powerpc64__) || defined(_ARCH_PPC64)
34 #define CPUINFO_ARCH_PPC64 1
35 #endif
36
37 #if defined(__asmjs__)
38 #define CPUINFO_ARCH_ASMJS 1
39 #endif
40
41 #if defined(__wasm__)
42 #if defined(__wasm_simd128__)
43 #define CPUINFO_ARCH_WASMSIMD 1
44 #else
45 #define CPUINFO_ARCH_WASM 1
46 #endif
47 #endif
48
49 /* Define other architecture-specific macros as 0 */
50
51 #ifndef CPUINFO_ARCH_X86
52 #define CPUINFO_ARCH_X86 0
53 #endif
54
55 #ifndef CPUINFO_ARCH_X86_64
56 #define CPUINFO_ARCH_X86_64 0
57 #endif
58
59 #ifndef CPUINFO_ARCH_ARM
60 #define CPUINFO_ARCH_ARM 0
61 #endif
62
63 #ifndef CPUINFO_ARCH_ARM64
64 #define CPUINFO_ARCH_ARM64 0
65 #endif
66
67 #ifndef CPUINFO_ARCH_PPC64
68 #define CPUINFO_ARCH_PPC64 0
69 #endif
70
71 #ifndef CPUINFO_ARCH_ASMJS
72 #define CPUINFO_ARCH_ASMJS 0
73 #endif
74
75 #ifndef CPUINFO_ARCH_WASM
76 #define CPUINFO_ARCH_WASM 0
77 #endif
78
79 #ifndef CPUINFO_ARCH_WASMSIMD
80 #define CPUINFO_ARCH_WASMSIMD 0
81 #endif
82
83 #if CPUINFO_ARCH_X86 && defined(_MSC_VER)
84 #define CPUINFO_ABI __cdecl
85 #elif CPUINFO_ARCH_X86 && defined(__GNUC__)
86 #define CPUINFO_ABI __attribute__((__cdecl__))
87 #else
88 #define CPUINFO_ABI
89 #endif
90
91 #define CPUINFO_CACHE_UNIFIED 0x00000001
92 #define CPUINFO_CACHE_INCLUSIVE 0x00000002
93 #define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004
94
95 struct cpuinfo_cache {
96 /** Cache size in bytes */
97 uint32_t size;
98 /** Number of ways of associativity */
99 uint32_t associativity;
100 /** Number of sets */
101 uint32_t sets;
102 /** Number of partitions */
103 uint32_t partitions;
104 /** Line size in bytes */
105 uint32_t line_size;
106 /**
107 * Binary characteristics of the cache (unified cache, inclusive cache, cache with complex indexing).
108 *
109 * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, CPUINFO_CACHE_COMPLEX_INDEXING
110 */
111 uint32_t flags;
112 /** Index of the first logical processor that shares this cache */
113 uint32_t processor_start;
114 /** Number of logical processors that share this cache */
115 uint32_t processor_count;
116 };
117
118 struct cpuinfo_trace_cache {
119 uint32_t uops;
120 uint32_t associativity;
121 };
122
123 #define CPUINFO_PAGE_SIZE_4KB 0x1000
124 #define CPUINFO_PAGE_SIZE_1MB 0x100000
125 #define CPUINFO_PAGE_SIZE_2MB 0x200000
126 #define CPUINFO_PAGE_SIZE_4MB 0x400000
127 #define CPUINFO_PAGE_SIZE_16MB 0x1000000
128 #define CPUINFO_PAGE_SIZE_1GB 0x40000000
129
130 struct cpuinfo_tlb {
131 uint32_t entries;
132 uint32_t associativity;
133 uint64_t pages;
134 };
135
136 /** Vendor of processor core design */
137 enum cpuinfo_vendor {
138 /** Processor vendor is not known to the library, or the library failed to get vendor information from the OS. */
139 cpuinfo_vendor_unknown = 0,
140
141 /* Active vendors of modern CPUs */
142
143 /**
144 * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor microarchitectures.
145 *
146 * Sold its ARM design subsidiary in 2006. The last ARM processor design was released in 2004.
147 */
148 cpuinfo_vendor_intel = 1,
149 /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor microarchitectures. */
150 cpuinfo_vendor_amd = 2,
151 /** ARM Holdings plc. Vendor of ARM and ARM64 processor microarchitectures. */
152 cpuinfo_vendor_arm = 3,
153 /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor microarchitectures. */
154 cpuinfo_vendor_qualcomm = 4,
155 /** Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. */
156 cpuinfo_vendor_apple = 5,
157 /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor microarchitectures. */
158 cpuinfo_vendor_samsung = 6,
159 /** Nvidia Corporation. Vendor of ARM64-compatible processor microarchitectures. */
160 cpuinfo_vendor_nvidia = 7,
161 /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */
162 cpuinfo_vendor_mips = 8,
163 /** International Business Machines Corporation. Vendor of PowerPC processor microarchitectures. */
164 cpuinfo_vendor_ibm = 9,
165 /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. */
166 cpuinfo_vendor_ingenic = 10,
167 /**
168 * VIA Technologies, Inc. Vendor of x86 and x86-64 processor microarchitectures.
169 *
170 * Processors are designed by Centaur Technology, a subsidiary of VIA Technologies.
171 */
172 cpuinfo_vendor_via = 11,
173 /** Cavium, Inc. Vendor of ARM64 processor microarchitectures. */
174 cpuinfo_vendor_cavium = 12,
175 /** Broadcom, Inc. Vendor of ARM processor microarchitectures. */
176 cpuinfo_vendor_broadcom = 13,
177 /** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor microarchitectures. */
178 cpuinfo_vendor_apm = 14,
179 /**
180 * Huawei Technologies Co., Ltd. Vendor of ARM64 processor microarchitectures.
181 *
182 * Processors are designed by HiSilicon, a subsidiary of Huawei.
183 */
184 cpuinfo_vendor_huawei = 15,
185 /**
186 * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor of x86-64 processor microarchitectures.
187 *
188 * Processors are variants of AMD cores.
189 */
190 cpuinfo_vendor_hygon = 16,
191
192 /* Active vendors of embedded CPUs */
193
194 /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. */
195 cpuinfo_vendor_texas_instruments = 30,
196 /** Marvell Technology Group Ltd. Vendor of ARM processor microarchitectures. */
197 cpuinfo_vendor_marvell = 31,
198 /** RDC Semiconductor Co., Ltd. Vendor of x86 processor microarchitectures. */
199 cpuinfo_vendor_rdc = 32,
200 /** DM&P Electronics Inc. Vendor of x86 processor microarchitectures. */
201 cpuinfo_vendor_dmp = 33,
202 /** Motorola, Inc. Vendor of PowerPC and ARM processor microarchitectures. */
203 cpuinfo_vendor_motorola = 34,
204
205 /* Defunct CPU vendors */
206
207 /**
208 * Transmeta Corporation. Vendor of x86 processor microarchitectures.
209 *
210 * Now defunct. The last processor design was released in 2004.
211 * Transmeta processors implemented VLIW ISA and used binary translation to execute x86 code.
212 */
213 cpuinfo_vendor_transmeta = 50,
214 /**
215 * Cyrix Corporation. Vendor of x86 processor microarchitectures.
216 *
217 * Now defunct. The last processor design was released in 1996.
218 */
219 cpuinfo_vendor_cyrix = 51,
220 /**
221 * Rise Technology. Vendor of x86 processor microarchitectures.
222 *
223 * Now defunct. The last processor design was released in 1999.
224 */
225 cpuinfo_vendor_rise = 52,
226 /**
227 * National Semiconductor. Vendor of x86 processor microarchitectures.
228 *
229 * Sold its x86 design subsidiary in 1999. The last processor design was released in 1998.
230 */
231 cpuinfo_vendor_nsc = 53,
232 /**
233 * Silicon Integrated Systems. Vendor of x86 processor microarchitectures.
234 *
235 * Sold its x86 design subsidiary in 2001. The last processor design was released in 2001.
236 */
237 cpuinfo_vendor_sis = 54,
238 /**
239 * NexGen. Vendor of x86 processor microarchitectures.
240 *
241 * Now defunct. The last processor design was released in 1994.
242 * NexGen designed the first x86 microarchitecture which decomposed x86 instructions into simple microoperations.
243 */
244 cpuinfo_vendor_nexgen = 55,
245 /**
246 * United Microelectronics Corporation. Vendor of x86 processor microarchitectures.
247 *
248 * Ceased x86 in the early 1990s. The last processor design was released in 1991.
249 * Designed U5C and U5D processors. Both are 486 level.
250 */
251 cpuinfo_vendor_umc = 56,
252 /**
253 * Digital Equipment Corporation. Vendor of ARM processor microarchitecture.
254 *
255 * Sold its ARM designs in 1997. The last processor design was released in 1997.
256 */
257 cpuinfo_vendor_dec = 57,
258 };
259
260 /**
261 * Processor microarchitecture
262 *
263 * Processors with different microarchitectures often have different instruction performance characteristics,
264 * and may have dramatically different pipeline organization.
265 */
266 enum cpuinfo_uarch {
267 /** Microarchitecture is unknown, or the library failed to get information about the microarchitecture from OS */
268 cpuinfo_uarch_unknown = 0,
269
270 /** Pentium and Pentium MMX microarchitecture. */
271 cpuinfo_uarch_p5 = 0x00100100,
272 /** Intel Quark microarchitecture. */
273 cpuinfo_uarch_quark = 0x00100101,
274
275 /** Pentium Pro, Pentium II, and Pentium III. */
276 cpuinfo_uarch_p6 = 0x00100200,
277 /** Pentium M. */
278 cpuinfo_uarch_dothan = 0x00100201,
279 /** Intel Core microarchitecture. */
280 cpuinfo_uarch_yonah = 0x00100202,
281 /** Intel Core 2 microarchitecture on 65 nm process. */
282 cpuinfo_uarch_conroe = 0x00100203,
283 /** Intel Core 2 microarchitecture on 45 nm process. */
284 cpuinfo_uarch_penryn = 0x00100204,
285 /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st gen). */
286 cpuinfo_uarch_nehalem = 0x00100205,
287 /** Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). */
288 cpuinfo_uarch_sandy_bridge = 0x00100206,
289 /** Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). */
290 cpuinfo_uarch_ivy_bridge = 0x00100207,
291 /** Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). */
292 cpuinfo_uarch_haswell = 0x00100208,
293 /** Intel Broadwell microarchitecture. */
294 cpuinfo_uarch_broadwell = 0x00100209,
295 /** Intel Sky Lake microarchitecture (14 nm, including Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */
296 cpuinfo_uarch_sky_lake = 0x0010020A,
297 /** DEPRECATED (Intel Kaby Lake microarchitecture). */
298 cpuinfo_uarch_kaby_lake = 0x0010020A,
299 /** Intel Palm Cove microarchitecture (10 nm, Cannon Lake). */
300 cpuinfo_uarch_palm_cove = 0x0010020B,
301 /** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
302 cpuinfo_uarch_sunny_cove = 0x0010020C,
303
304 /** Pentium 4 with Willamette, Northwood, or Foster cores. */
305 cpuinfo_uarch_willamette = 0x00100300,
306 /** Pentium 4 with Prescott and later cores. */
307 cpuinfo_uarch_prescott = 0x00100301,
308
309 /** Intel Atom on 45 nm process. */
310 cpuinfo_uarch_bonnell = 0x00100400,
311 /** Intel Atom on 32 nm process. */
312 cpuinfo_uarch_saltwell = 0x00100401,
313 /** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */
314 cpuinfo_uarch_silvermont = 0x00100402,
315 /** Intel Airmont microarchitecture (14 nm out-of-order Atom). */
316 cpuinfo_uarch_airmont = 0x00100403,
317 /** Intel Goldmont microarchitecture (Denverton, Apollo Lake). */
318 cpuinfo_uarch_goldmont = 0x00100404,
319 /** Intel Goldmont Plus microarchitecture (Gemini Lake). */
320 cpuinfo_uarch_goldmont_plus = 0x00100405,
321
322 /** Intel Knights Ferry HPC boards. */
323 cpuinfo_uarch_knights_ferry = 0x00100500,
324 /** Intel Knights Corner HPC boards (aka Xeon Phi). */
325 cpuinfo_uarch_knights_corner = 0x00100501,
326 /** Intel Knights Landing microarchitecture (second-gen MIC). */
327 cpuinfo_uarch_knights_landing = 0x00100502,
328 /** Intel Knights Hill microarchitecture (third-gen MIC). */
329 cpuinfo_uarch_knights_hill = 0x00100503,
330 /** Intel Knights Mill Xeon Phi. */
331 cpuinfo_uarch_knights_mill = 0x00100504,
332
333 /** Intel/Marvell XScale series. */
334 cpuinfo_uarch_xscale = 0x00100600,
335
336 /** AMD K5. */
337 cpuinfo_uarch_k5 = 0x00200100,
338 /** AMD K6 and alike. */
339 cpuinfo_uarch_k6 = 0x00200101,
340 /** AMD Athlon and Duron. */
341 cpuinfo_uarch_k7 = 0x00200102,
342 /** AMD Athlon 64, Opteron 64. */
343 cpuinfo_uarch_k8 = 0x00200103,
344 /** AMD Family 10h (Barcelona, Istambul, Magny-Cours). */
345 cpuinfo_uarch_k10 = 0x00200104,
346 /**
347 * AMD Bulldozer microarchitecture
348 * Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs.
349 */
350 cpuinfo_uarch_bulldozer = 0x00200105,
351 /**
352 * AMD Piledriver microarchitecture
353 * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu Dhabi Opteron CPUs.
354 */
355 cpuinfo_uarch_piledriver = 0x00200106,
356 /** AMD Steamroller microarchitecture (Kaveri APUs). */
357 cpuinfo_uarch_steamroller = 0x00200107,
358 /** AMD Excavator microarchitecture (Carizzo APUs). */
359 cpuinfo_uarch_excavator = 0x00200108,
360 /** AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). */
361 cpuinfo_uarch_zen = 0x00200109,
362 /** AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). */
363 cpuinfo_uarch_zen2 = 0x0020010A,
364 /** AMD Zen 3 microarchitecture. */
365 cpuinfo_uarch_zen3 = 0x0020010B,
366
367 /** NSC Geode and AMD Geode GX and LX. */
368 cpuinfo_uarch_geode = 0x00200200,
369 /** AMD Bobcat mobile microarchitecture. */
370 cpuinfo_uarch_bobcat = 0x00200201,
371 /** AMD Jaguar mobile microarchitecture. */
372 cpuinfo_uarch_jaguar = 0x00200202,
373 /** AMD Puma mobile microarchitecture. */
374 cpuinfo_uarch_puma = 0x00200203,
375
376 /** ARM7 series. */
377 cpuinfo_uarch_arm7 = 0x00300100,
378 /** ARM9 series. */
379 cpuinfo_uarch_arm9 = 0x00300101,
380 /** ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. */
381 cpuinfo_uarch_arm11 = 0x00300102,
382
383 /** ARM Cortex-A5. */
384 cpuinfo_uarch_cortex_a5 = 0x00300205,
385 /** ARM Cortex-A7. */
386 cpuinfo_uarch_cortex_a7 = 0x00300207,
387 /** ARM Cortex-A8. */
388 cpuinfo_uarch_cortex_a8 = 0x00300208,
389 /** ARM Cortex-A9. */
390 cpuinfo_uarch_cortex_a9 = 0x00300209,
391 /** ARM Cortex-A12. */
392 cpuinfo_uarch_cortex_a12 = 0x00300212,
393 /** ARM Cortex-A15. */
394 cpuinfo_uarch_cortex_a15 = 0x00300215,
395 /** ARM Cortex-A17. */
396 cpuinfo_uarch_cortex_a17 = 0x00300217,
397
398 /** ARM Cortex-A32. */
399 cpuinfo_uarch_cortex_a32 = 0x00300332,
400 /** ARM Cortex-A35. */
401 cpuinfo_uarch_cortex_a35 = 0x00300335,
402 /** ARM Cortex-A53. */
403 cpuinfo_uarch_cortex_a53 = 0x00300353,
404 /** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+). */
405 cpuinfo_uarch_cortex_a55r0 = 0x00300354,
406 /** ARM Cortex-A55. */
407 cpuinfo_uarch_cortex_a55 = 0x00300355,
408 /** ARM Cortex-A57. */
409 cpuinfo_uarch_cortex_a57 = 0x00300357,
410 /** ARM Cortex-A65. */
411 cpuinfo_uarch_cortex_a65 = 0x00300365,
412 /** ARM Cortex-A72. */
413 cpuinfo_uarch_cortex_a72 = 0x00300372,
414 /** ARM Cortex-A73. */
415 cpuinfo_uarch_cortex_a73 = 0x00300373,
416 /** ARM Cortex-A75. */
417 cpuinfo_uarch_cortex_a75 = 0x00300375,
418 /** ARM Cortex-A76. */
419 cpuinfo_uarch_cortex_a76 = 0x00300376,
420 /** ARM Cortex-A77. */
421 cpuinfo_uarch_cortex_a77 = 0x00300377,
422 /** ARM Cortex-A78. */
423 cpuinfo_uarch_cortex_a78 = 0x00300378,
424
425 /** ARM Neoverse N1. */
426 cpuinfo_uarch_neoverse_n1 = 0x00300400,
427 /** ARM Neoverse E1. */
428 cpuinfo_uarch_neoverse_e1 = 0x00300401,
429 /** ARM Neoverse V1. */
430 cpuinfo_uarch_neoverse_v1 = 0x00300402,
431 /** ARM Neoverse N2. */
432 cpuinfo_uarch_neoverse_n2 = 0x00300403,
433
434 /** ARM Cortex-X1. */
435 cpuinfo_uarch_cortex_x1 = 0x00300501,
436 /** ARM Cortex-X2. */
437 cpuinfo_uarch_cortex_x2 = 0x00300502,
438
439 /** ARM Cortex-A510. */
440 cpuinfo_uarch_cortex_a510 = 0x00300551,
441 /** ARM Cortex-A710. */
442 cpuinfo_uarch_cortex_a710 = 0x00300571,
443
444 /** Qualcomm Scorpion. */
445 cpuinfo_uarch_scorpion = 0x00400100,
446 /** Qualcomm Krait. */
447 cpuinfo_uarch_krait = 0x00400101,
448 /** Qualcomm Kryo. */
449 cpuinfo_uarch_kryo = 0x00400102,
450 /** Qualcomm Falkor. */
451 cpuinfo_uarch_falkor = 0x00400103,
452 /** Qualcomm Saphira. */
453 cpuinfo_uarch_saphira = 0x00400104,
454
455 /** Nvidia Denver. */
456 cpuinfo_uarch_denver = 0x00500100,
457 /** Nvidia Denver 2. */
458 cpuinfo_uarch_denver2 = 0x00500101,
459 /** Nvidia Carmel. */
460 cpuinfo_uarch_carmel = 0x00500102,
461
462 /** Samsung Exynos M1 (Exynos 8890 big cores). */
463 cpuinfo_uarch_exynos_m1 = 0x00600100,
464 /** Samsung Exynos M2 (Exynos 8895 big cores). */
465 cpuinfo_uarch_exynos_m2 = 0x00600101,
466 /** Samsung Exynos M3 (Exynos 9810 big cores). */
467 cpuinfo_uarch_exynos_m3 = 0x00600102,
468 /** Samsung Exynos M4 (Exynos 9820 big cores). */
469 cpuinfo_uarch_exynos_m4 = 0x00600103,
470 /** Samsung Exynos M5 (Exynos 9830 big cores). */
471 cpuinfo_uarch_exynos_m5 = 0x00600104,
472
473 /* Deprecated synonym for Cortex-A76 */
474 cpuinfo_uarch_cortex_a76ae = 0x00300376,
475 /* Deprecated names for Exynos. */
476 cpuinfo_uarch_mongoose_m1 = 0x00600100,
477 cpuinfo_uarch_mongoose_m2 = 0x00600101,
478 cpuinfo_uarch_meerkat_m3 = 0x00600102,
479 cpuinfo_uarch_meerkat_m4 = 0x00600103,
480
481 /** Apple A6 and A6X processors. */
482 cpuinfo_uarch_swift = 0x00700100,
483 /** Apple A7 processor. */
484 cpuinfo_uarch_cyclone = 0x00700101,
485 /** Apple A8 and A8X processor. */
486 cpuinfo_uarch_typhoon = 0x00700102,
487 /** Apple A9 and A9X processor. */
488 cpuinfo_uarch_twister = 0x00700103,
489 /** Apple A10 and A10X processor. */
490 cpuinfo_uarch_hurricane = 0x00700104,
491 /** Apple A11 processor (big cores). */
492 cpuinfo_uarch_monsoon = 0x00700105,
493 /** Apple A11 processor (little cores). */
494 cpuinfo_uarch_mistral = 0x00700106,
495 /** Apple A12 processor (big cores). */
496 cpuinfo_uarch_vortex = 0x00700107,
497 /** Apple A12 processor (little cores). */
498 cpuinfo_uarch_tempest = 0x00700108,
499 /** Apple A13 processor (big cores). */
500 cpuinfo_uarch_lightning = 0x00700109,
501 /** Apple A13 processor (little cores). */
502 cpuinfo_uarch_thunder = 0x0070010A,
503 /** Apple A14 / M1 processor (big cores). */
504 cpuinfo_uarch_firestorm = 0x0070010B,
505 /** Apple A14 / M1 processor (little cores). */
506 cpuinfo_uarch_icestorm = 0x0070010C,
507 /** Apple A15 / M2 processor (big cores). */
508 cpuinfo_uarch_avalanche = 0x0070010D,
509 /** Apple A15 / M2 processor (little cores). */
510 cpuinfo_uarch_blizzard = 0x0070010E,
511
512 /** Cavium ThunderX. */
513 cpuinfo_uarch_thunderx = 0x00800100,
514 /** Cavium ThunderX2 (originally Broadcom Vulkan). */
515 cpuinfo_uarch_thunderx2 = 0x00800200,
516
517 /** Marvell PJ4. */
518 cpuinfo_uarch_pj4 = 0x00900100,
519
520 /** Broadcom Brahma B15. */
521 cpuinfo_uarch_brahma_b15 = 0x00A00100,
522 /** Broadcom Brahma B53. */
523 cpuinfo_uarch_brahma_b53 = 0x00A00101,
524
525 /** Applied Micro X-Gene. */
526 cpuinfo_uarch_xgene = 0x00B00100,
527
528 /* Hygon Dhyana (a modification of AMD Zen for Chinese market). */
529 cpuinfo_uarch_dhyana = 0x01000100,
530
531 /** HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors). */
532 cpuinfo_uarch_taishan_v110 = 0x00C00100,
533 };
534
535 struct cpuinfo_processor {
536 /** SMT (hyperthread) ID within a core */
537 uint32_t smt_id;
538 /** Core containing this logical processor */
539 const struct cpuinfo_core* core;
540 /** Cluster of cores containing this logical processor */
541 const struct cpuinfo_cluster* cluster;
542 /** Physical package containing this logical processor */
543 const struct cpuinfo_package* package;
544 #if defined(__linux__)
545 /**
546 * Linux-specific ID for the logical processor:
547 * - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu<linux_id>/
548 * - Bit <linux_id> in the cpu_set_t identifies this logical processor
549 */
550 int linux_id;
551 #endif
552 #if defined(_WIN32) || defined(__CYGWIN__)
553 /** Windows-specific ID for the group containing the logical processor. */
554 uint16_t windows_group_id;
555 /**
556 * Windows-specific ID of the logical processor within its group:
557 * - Bit <windows_processor_id> in the KAFFINITY mask identifies this logical processor within its group.
558 */
559 uint16_t windows_processor_id;
560 #endif
561 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
562 /** APIC ID (unique x86-specific ID of the logical processor) */
563 uint32_t apic_id;
564 #endif
565 struct {
566 /** Level 1 instruction cache */
567 const struct cpuinfo_cache* l1i;
568 /** Level 1 data cache */
569 const struct cpuinfo_cache* l1d;
570 /** Level 2 unified or data cache */
571 const struct cpuinfo_cache* l2;
572 /** Level 3 unified or data cache */
573 const struct cpuinfo_cache* l3;
574 /** Level 4 unified or data cache */
575 const struct cpuinfo_cache* l4;
576 } cache;
577 };
578
579 struct cpuinfo_core {
580 /** Index of the first logical processor on this core. */
581 uint32_t processor_start;
582 /** Number of logical processors on this core */
583 uint32_t processor_count;
584 /** Core ID within a package */
585 uint32_t core_id;
586 /** Cluster containing this core */
587 const struct cpuinfo_cluster* cluster;
588 /** Physical package containing this core. */
589 const struct cpuinfo_package* package;
590 /** Vendor of the CPU microarchitecture for this core */
591 enum cpuinfo_vendor vendor;
592 /** CPU microarchitecture for this core */
593 enum cpuinfo_uarch uarch;
594 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
595 /** Value of CPUID leaf 1 EAX register for this core */
596 uint32_t cpuid;
597 #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
598 /** Value of Main ID Register (MIDR) for this core */
599 uint32_t midr;
600 #endif
601 /** Clock rate (non-Turbo) of the core, in Hz */
602 uint64_t frequency;
603 };
604
605 struct cpuinfo_cluster {
606 /** Index of the first logical processor in the cluster */
607 uint32_t processor_start;
608 /** Number of logical processors in the cluster */
609 uint32_t processor_count;
610 /** Index of the first core in the cluster */
611 uint32_t core_start;
612 /** Number of cores on the cluster */
613 uint32_t core_count;
614 /** Cluster ID within a package */
615 uint32_t cluster_id;
616 /** Physical package containing the cluster */
617 const struct cpuinfo_package* package;
618 /** CPU microarchitecture vendor of the cores in the cluster */
619 enum cpuinfo_vendor vendor;
620 /** CPU microarchitecture of the cores in the cluster */
621 enum cpuinfo_uarch uarch;
622 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
623 /** Value of CPUID leaf 1 EAX register of the cores in the cluster */
624 uint32_t cpuid;
625 #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
626 /** Value of Main ID Register (MIDR) of the cores in the cluster */
627 uint32_t midr;
628 #endif
629 /** Clock rate (non-Turbo) of the cores in the cluster, in Hz */
630 uint64_t frequency;
631 };
632
633 #define CPUINFO_PACKAGE_NAME_MAX 48
634
635 struct cpuinfo_package {
636 /** SoC or processor chip model name */
637 char name[CPUINFO_PACKAGE_NAME_MAX];
638 /** Index of the first logical processor on this physical package */
639 uint32_t processor_start;
640 /** Number of logical processors on this physical package */
641 uint32_t processor_count;
642 /** Index of the first core on this physical package */
643 uint32_t core_start;
644 /** Number of cores on this physical package */
645 uint32_t core_count;
646 /** Index of the first cluster of cores on this physical package */
647 uint32_t cluster_start;
648 /** Number of clusters of cores on this physical package */
649 uint32_t cluster_count;
650 };
651
652 struct cpuinfo_uarch_info {
653 /** Type of CPU microarchitecture */
654 enum cpuinfo_uarch uarch;
655 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
656 /** Value of CPUID leaf 1 EAX register for the microarchitecture */
657 uint32_t cpuid;
658 #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
659 /** Value of Main ID Register (MIDR) for the microarchitecture */
660 uint32_t midr;
661 #endif
662 /** Number of logical processors with the microarchitecture */
663 uint32_t processor_count;
664 /** Number of cores with the microarchitecture */
665 uint32_t core_count;
666 };
667
668 #ifdef __cplusplus
669 extern "C" {
670 #endif
671
672 bool CPUINFO_ABI cpuinfo_initialize(void);
673
674 void CPUINFO_ABI cpuinfo_deinitialize(void);
675
676 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
677 /* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions instead. */
678 struct cpuinfo_x86_isa {
679 #if CPUINFO_ARCH_X86
680 bool rdtsc;
681 #endif
682 bool rdtscp;
683 bool rdpid;
684 bool sysenter;
685 #if CPUINFO_ARCH_X86
686 bool syscall;
687 #endif
688 bool msr;
689 bool clzero;
690 bool clflush;
691 bool clflushopt;
692 bool mwait;
693 bool mwaitx;
694 #if CPUINFO_ARCH_X86
695 bool emmx;
696 #endif
697 bool fxsave;
698 bool xsave;
699 #if CPUINFO_ARCH_X86
700 bool fpu;
701 bool mmx;
702 bool mmx_plus;
703 #endif
704 bool three_d_now;
705 bool three_d_now_plus;
706 #if CPUINFO_ARCH_X86
707 bool three_d_now_geode;
708 #endif
709 bool prefetch;
710 bool prefetchw;
711 bool prefetchwt1;
712 #if CPUINFO_ARCH_X86
713 bool daz;
714 bool sse;
715 bool sse2;
716 #endif
717 bool sse3;
718 bool ssse3;
719 bool sse4_1;
720 bool sse4_2;
721 bool sse4a;
722 bool misaligned_sse;
723 bool avx;
724 bool fma3;
725 bool fma4;
726 bool xop;
727 bool f16c;
728 bool avx2;
729 bool avx512f;
730 bool avx512pf;
731 bool avx512er;
732 bool avx512cd;
733 bool avx512dq;
734 bool avx512bw;
735 bool avx512vl;
736 bool avx512ifma;
737 bool avx512vbmi;
738 bool avx512vbmi2;
739 bool avx512bitalg;
740 bool avx512vpopcntdq;
741 bool avx512vnni;
742 bool avx512bf16;
743 bool avx512vp2intersect;
744 bool avx512_4vnniw;
745 bool avx512_4fmaps;
746 bool hle;
747 bool rtm;
748 bool xtest;
749 bool mpx;
750 #if CPUINFO_ARCH_X86
751 bool cmov;
752 bool cmpxchg8b;
753 #endif
754 bool cmpxchg16b;
755 bool clwb;
756 bool movbe;
757 #if CPUINFO_ARCH_X86_64
758 bool lahf_sahf;
759 #endif
760 bool fs_gs_base;
761 bool lzcnt;
762 bool popcnt;
763 bool tbm;
764 bool bmi;
765 bool bmi2;
766 bool adx;
767 bool aes;
768 bool vaes;
769 bool pclmulqdq;
770 bool vpclmulqdq;
771 bool gfni;
772 bool rdrand;
773 bool rdseed;
774 bool sha;
775 bool rng;
776 bool ace;
777 bool ace2;
778 bool phe;
779 bool pmm;
780 bool lwp;
781 };
782
783 extern struct cpuinfo_x86_isa cpuinfo_isa;
784 #endif
785
cpuinfo_has_x86_rdtsc(void)786 static inline bool cpuinfo_has_x86_rdtsc(void) {
787 #if CPUINFO_ARCH_X86_64
788 return true;
789 #elif CPUINFO_ARCH_X86
790 #if defined(__ANDROID__)
791 return true;
792 #else
793 return cpuinfo_isa.rdtsc;
794 #endif
795 #else
796 return false;
797 #endif
798 }
799
cpuinfo_has_x86_rdtscp(void)800 static inline bool cpuinfo_has_x86_rdtscp(void) {
801 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
802 return cpuinfo_isa.rdtscp;
803 #else
804 return false;
805 #endif
806 }
807
cpuinfo_has_x86_rdpid(void)808 static inline bool cpuinfo_has_x86_rdpid(void) {
809 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
810 return cpuinfo_isa.rdpid;
811 #else
812 return false;
813 #endif
814 }
815
cpuinfo_has_x86_clzero(void)816 static inline bool cpuinfo_has_x86_clzero(void) {
817 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
818 return cpuinfo_isa.clzero;
819 #else
820 return false;
821 #endif
822 }
823
cpuinfo_has_x86_mwait(void)824 static inline bool cpuinfo_has_x86_mwait(void) {
825 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
826 return cpuinfo_isa.mwait;
827 #else
828 return false;
829 #endif
830 }
831
cpuinfo_has_x86_mwaitx(void)832 static inline bool cpuinfo_has_x86_mwaitx(void) {
833 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
834 return cpuinfo_isa.mwaitx;
835 #else
836 return false;
837 #endif
838 }
839
cpuinfo_has_x86_fxsave(void)840 static inline bool cpuinfo_has_x86_fxsave(void) {
841 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
842 return cpuinfo_isa.fxsave;
843 #else
844 return false;
845 #endif
846 }
847
cpuinfo_has_x86_xsave(void)848 static inline bool cpuinfo_has_x86_xsave(void) {
849 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
850 return cpuinfo_isa.xsave;
851 #else
852 return false;
853 #endif
854 }
855
cpuinfo_has_x86_fpu(void)856 static inline bool cpuinfo_has_x86_fpu(void) {
857 #if CPUINFO_ARCH_X86_64
858 return true;
859 #elif CPUINFO_ARCH_X86
860 #if defined(__ANDROID__)
861 return true;
862 #else
863 return cpuinfo_isa.fpu;
864 #endif
865 #else
866 return false;
867 #endif
868 }
869
cpuinfo_has_x86_mmx(void)870 static inline bool cpuinfo_has_x86_mmx(void) {
871 #if CPUINFO_ARCH_X86_64
872 return true;
873 #elif CPUINFO_ARCH_X86
874 #if defined(__ANDROID__)
875 return true;
876 #else
877 return cpuinfo_isa.mmx;
878 #endif
879 #else
880 return false;
881 #endif
882 }
883
cpuinfo_has_x86_mmx_plus(void)884 static inline bool cpuinfo_has_x86_mmx_plus(void) {
885 #if CPUINFO_ARCH_X86_64
886 return true;
887 #elif CPUINFO_ARCH_X86
888 #if defined(__ANDROID__)
889 return true;
890 #else
891 return cpuinfo_isa.mmx_plus;
892 #endif
893 #else
894 return false;
895 #endif
896 }
897
cpuinfo_has_x86_3dnow(void)898 static inline bool cpuinfo_has_x86_3dnow(void) {
899 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
900 return cpuinfo_isa.three_d_now;
901 #else
902 return false;
903 #endif
904 }
905
cpuinfo_has_x86_3dnow_plus(void)906 static inline bool cpuinfo_has_x86_3dnow_plus(void) {
907 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
908 return cpuinfo_isa.three_d_now_plus;
909 #else
910 return false;
911 #endif
912 }
913
cpuinfo_has_x86_3dnow_geode(void)914 static inline bool cpuinfo_has_x86_3dnow_geode(void) {
915 #if CPUINFO_ARCH_X86_64
916 return false;
917 #elif CPUINFO_ARCH_X86
918 #if defined(__ANDROID__)
919 return false;
920 #else
921 return cpuinfo_isa.three_d_now_geode;
922 #endif
923 #else
924 return false;
925 #endif
926 }
927
cpuinfo_has_x86_prefetch(void)928 static inline bool cpuinfo_has_x86_prefetch(void) {
929 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
930 return cpuinfo_isa.prefetch;
931 #else
932 return false;
933 #endif
934 }
935
cpuinfo_has_x86_prefetchw(void)936 static inline bool cpuinfo_has_x86_prefetchw(void) {
937 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
938 return cpuinfo_isa.prefetchw;
939 #else
940 return false;
941 #endif
942 }
943
cpuinfo_has_x86_prefetchwt1(void)944 static inline bool cpuinfo_has_x86_prefetchwt1(void) {
945 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
946 return cpuinfo_isa.prefetchwt1;
947 #else
948 return false;
949 #endif
950 }
951
cpuinfo_has_x86_daz(void)952 static inline bool cpuinfo_has_x86_daz(void) {
953 #if CPUINFO_ARCH_X86_64
954 return true;
955 #elif CPUINFO_ARCH_X86
956 #if defined(__ANDROID__)
957 return true;
958 #else
959 return cpuinfo_isa.daz;
960 #endif
961 #else
962 return false;
963 #endif
964 }
965
cpuinfo_has_x86_sse(void)966 static inline bool cpuinfo_has_x86_sse(void) {
967 #if CPUINFO_ARCH_X86_64
968 return true;
969 #elif CPUINFO_ARCH_X86
970 #if defined(__ANDROID__)
971 return true;
972 #else
973 return cpuinfo_isa.sse;
974 #endif
975 #else
976 return false;
977 #endif
978 }
979
cpuinfo_has_x86_sse2(void)980 static inline bool cpuinfo_has_x86_sse2(void) {
981 #if CPUINFO_ARCH_X86_64
982 return true;
983 #elif CPUINFO_ARCH_X86
984 #if defined(__ANDROID__)
985 return true;
986 #else
987 return cpuinfo_isa.sse2;
988 #endif
989 #else
990 return false;
991 #endif
992 }
993
cpuinfo_has_x86_sse3(void)994 static inline bool cpuinfo_has_x86_sse3(void) {
995 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
996 #if defined(__ANDROID__)
997 return true;
998 #else
999 return cpuinfo_isa.sse3;
1000 #endif
1001 #else
1002 return false;
1003 #endif
1004 }
1005
cpuinfo_has_x86_ssse3(void)1006 static inline bool cpuinfo_has_x86_ssse3(void) {
1007 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1008 #if defined(__ANDROID__)
1009 return true;
1010 #else
1011 return cpuinfo_isa.ssse3;
1012 #endif
1013 #else
1014 return false;
1015 #endif
1016 }
1017
cpuinfo_has_x86_sse4_1(void)1018 static inline bool cpuinfo_has_x86_sse4_1(void) {
1019 #if CPUINFO_ARCH_X86_64
1020 #if defined(__ANDROID__)
1021 return true;
1022 #else
1023 return cpuinfo_isa.sse4_1;
1024 #endif
1025 #elif CPUINFO_ARCH_X86
1026 return cpuinfo_isa.sse4_1;
1027 #else
1028 return false;
1029 #endif
1030 }
1031
cpuinfo_has_x86_sse4_2(void)1032 static inline bool cpuinfo_has_x86_sse4_2(void) {
1033 #if CPUINFO_ARCH_X86_64
1034 #if defined(__ANDROID__)
1035 return true;
1036 #else
1037 return cpuinfo_isa.sse4_2;
1038 #endif
1039 #elif CPUINFO_ARCH_X86
1040 return cpuinfo_isa.sse4_2;
1041 #else
1042 return false;
1043 #endif
1044 }
1045
cpuinfo_has_x86_sse4a(void)1046 static inline bool cpuinfo_has_x86_sse4a(void) {
1047 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1048 return cpuinfo_isa.sse4a;
1049 #else
1050 return false;
1051 #endif
1052 }
1053
cpuinfo_has_x86_misaligned_sse(void)1054 static inline bool cpuinfo_has_x86_misaligned_sse(void) {
1055 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1056 return cpuinfo_isa.misaligned_sse;
1057 #else
1058 return false;
1059 #endif
1060 }
1061
cpuinfo_has_x86_avx(void)1062 static inline bool cpuinfo_has_x86_avx(void) {
1063 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1064 return cpuinfo_isa.avx;
1065 #else
1066 return false;
1067 #endif
1068 }
1069
cpuinfo_has_x86_fma3(void)1070 static inline bool cpuinfo_has_x86_fma3(void) {
1071 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1072 return cpuinfo_isa.fma3;
1073 #else
1074 return false;
1075 #endif
1076 }
1077
cpuinfo_has_x86_fma4(void)1078 static inline bool cpuinfo_has_x86_fma4(void) {
1079 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1080 return cpuinfo_isa.fma4;
1081 #else
1082 return false;
1083 #endif
1084 }
1085
cpuinfo_has_x86_xop(void)1086 static inline bool cpuinfo_has_x86_xop(void) {
1087 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1088 return cpuinfo_isa.xop;
1089 #else
1090 return false;
1091 #endif
1092 }
1093
cpuinfo_has_x86_f16c(void)1094 static inline bool cpuinfo_has_x86_f16c(void) {
1095 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1096 return cpuinfo_isa.f16c;
1097 #else
1098 return false;
1099 #endif
1100 }
1101
cpuinfo_has_x86_avx2(void)1102 static inline bool cpuinfo_has_x86_avx2(void) {
1103 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1104 return cpuinfo_isa.avx2;
1105 #else
1106 return false;
1107 #endif
1108 }
1109
cpuinfo_has_x86_avx512f(void)1110 static inline bool cpuinfo_has_x86_avx512f(void) {
1111 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1112 return cpuinfo_isa.avx512f;
1113 #else
1114 return false;
1115 #endif
1116 }
1117
cpuinfo_has_x86_avx512pf(void)1118 static inline bool cpuinfo_has_x86_avx512pf(void) {
1119 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1120 return cpuinfo_isa.avx512pf;
1121 #else
1122 return false;
1123 #endif
1124 }
1125
cpuinfo_has_x86_avx512er(void)1126 static inline bool cpuinfo_has_x86_avx512er(void) {
1127 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1128 return cpuinfo_isa.avx512er;
1129 #else
1130 return false;
1131 #endif
1132 }
1133
cpuinfo_has_x86_avx512cd(void)1134 static inline bool cpuinfo_has_x86_avx512cd(void) {
1135 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1136 return cpuinfo_isa.avx512cd;
1137 #else
1138 return false;
1139 #endif
1140 }
1141
cpuinfo_has_x86_avx512dq(void)1142 static inline bool cpuinfo_has_x86_avx512dq(void) {
1143 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1144 return cpuinfo_isa.avx512dq;
1145 #else
1146 return false;
1147 #endif
1148 }
1149
cpuinfo_has_x86_avx512bw(void)1150 static inline bool cpuinfo_has_x86_avx512bw(void) {
1151 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1152 return cpuinfo_isa.avx512bw;
1153 #else
1154 return false;
1155 #endif
1156 }
1157
cpuinfo_has_x86_avx512vl(void)1158 static inline bool cpuinfo_has_x86_avx512vl(void) {
1159 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1160 return cpuinfo_isa.avx512vl;
1161 #else
1162 return false;
1163 #endif
1164 }
1165
cpuinfo_has_x86_avx512ifma(void)1166 static inline bool cpuinfo_has_x86_avx512ifma(void) {
1167 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1168 return cpuinfo_isa.avx512ifma;
1169 #else
1170 return false;
1171 #endif
1172 }
1173
cpuinfo_has_x86_avx512vbmi(void)1174 static inline bool cpuinfo_has_x86_avx512vbmi(void) {
1175 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1176 return cpuinfo_isa.avx512vbmi;
1177 #else
1178 return false;
1179 #endif
1180 }
1181
cpuinfo_has_x86_avx512vbmi2(void)1182 static inline bool cpuinfo_has_x86_avx512vbmi2(void) {
1183 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1184 return cpuinfo_isa.avx512vbmi2;
1185 #else
1186 return false;
1187 #endif
1188 }
1189
cpuinfo_has_x86_avx512bitalg(void)1190 static inline bool cpuinfo_has_x86_avx512bitalg(void) {
1191 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1192 return cpuinfo_isa.avx512bitalg;
1193 #else
1194 return false;
1195 #endif
1196 }
1197
cpuinfo_has_x86_avx512vpopcntdq(void)1198 static inline bool cpuinfo_has_x86_avx512vpopcntdq(void) {
1199 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1200 return cpuinfo_isa.avx512vpopcntdq;
1201 #else
1202 return false;
1203 #endif
1204 }
1205
cpuinfo_has_x86_avx512vnni(void)1206 static inline bool cpuinfo_has_x86_avx512vnni(void) {
1207 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1208 return cpuinfo_isa.avx512vnni;
1209 #else
1210 return false;
1211 #endif
1212 }
1213
cpuinfo_has_x86_avx512bf16(void)1214 static inline bool cpuinfo_has_x86_avx512bf16(void) {
1215 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1216 return cpuinfo_isa.avx512bf16;
1217 #else
1218 return false;
1219 #endif
1220 }
1221
cpuinfo_has_x86_avx512vp2intersect(void)1222 static inline bool cpuinfo_has_x86_avx512vp2intersect(void) {
1223 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1224 return cpuinfo_isa.avx512vp2intersect;
1225 #else
1226 return false;
1227 #endif
1228 }
1229
cpuinfo_has_x86_avx512_4vnniw(void)1230 static inline bool cpuinfo_has_x86_avx512_4vnniw(void) {
1231 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1232 return cpuinfo_isa.avx512_4vnniw;
1233 #else
1234 return false;
1235 #endif
1236 }
1237
cpuinfo_has_x86_avx512_4fmaps(void)1238 static inline bool cpuinfo_has_x86_avx512_4fmaps(void) {
1239 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1240 return cpuinfo_isa.avx512_4fmaps;
1241 #else
1242 return false;
1243 #endif
1244 }
1245
cpuinfo_has_x86_hle(void)1246 static inline bool cpuinfo_has_x86_hle(void) {
1247 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1248 return cpuinfo_isa.hle;
1249 #else
1250 return false;
1251 #endif
1252 }
1253
cpuinfo_has_x86_rtm(void)1254 static inline bool cpuinfo_has_x86_rtm(void) {
1255 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1256 return cpuinfo_isa.rtm;
1257 #else
1258 return false;
1259 #endif
1260 }
1261
cpuinfo_has_x86_xtest(void)1262 static inline bool cpuinfo_has_x86_xtest(void) {
1263 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1264 return cpuinfo_isa.xtest;
1265 #else
1266 return false;
1267 #endif
1268 }
1269
cpuinfo_has_x86_mpx(void)1270 static inline bool cpuinfo_has_x86_mpx(void) {
1271 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1272 return cpuinfo_isa.mpx;
1273 #else
1274 return false;
1275 #endif
1276 }
1277
cpuinfo_has_x86_cmov(void)1278 static inline bool cpuinfo_has_x86_cmov(void) {
1279 #if CPUINFO_ARCH_X86_64
1280 return true;
1281 #elif CPUINFO_ARCH_X86
1282 return cpuinfo_isa.cmov;
1283 #else
1284 return false;
1285 #endif
1286 }
1287
cpuinfo_has_x86_cmpxchg8b(void)1288 static inline bool cpuinfo_has_x86_cmpxchg8b(void) {
1289 #if CPUINFO_ARCH_X86_64
1290 return true;
1291 #elif CPUINFO_ARCH_X86
1292 return cpuinfo_isa.cmpxchg8b;
1293 #else
1294 return false;
1295 #endif
1296 }
1297
cpuinfo_has_x86_cmpxchg16b(void)1298 static inline bool cpuinfo_has_x86_cmpxchg16b(void) {
1299 #if CPUINFO_ARCH_X86_64
1300 return cpuinfo_isa.cmpxchg16b;
1301 #else
1302 return false;
1303 #endif
1304 }
1305
cpuinfo_has_x86_clwb(void)1306 static inline bool cpuinfo_has_x86_clwb(void) {
1307 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1308 return cpuinfo_isa.clwb;
1309 #else
1310 return false;
1311 #endif
1312 }
1313
cpuinfo_has_x86_movbe(void)1314 static inline bool cpuinfo_has_x86_movbe(void) {
1315 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1316 return cpuinfo_isa.movbe;
1317 #else
1318 return false;
1319 #endif
1320 }
1321
cpuinfo_has_x86_lahf_sahf(void)1322 static inline bool cpuinfo_has_x86_lahf_sahf(void) {
1323 #if CPUINFO_ARCH_X86
1324 return true;
1325 #elif CPUINFO_ARCH_X86_64
1326 return cpuinfo_isa.lahf_sahf;
1327 #else
1328 return false;
1329 #endif
1330 }
1331
cpuinfo_has_x86_lzcnt(void)1332 static inline bool cpuinfo_has_x86_lzcnt(void) {
1333 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1334 return cpuinfo_isa.lzcnt;
1335 #else
1336 return false;
1337 #endif
1338 }
1339
cpuinfo_has_x86_popcnt(void)1340 static inline bool cpuinfo_has_x86_popcnt(void) {
1341 #if CPUINFO_ARCH_X86_64
1342 #if defined(__ANDROID__)
1343 return true;
1344 #else
1345 return cpuinfo_isa.popcnt;
1346 #endif
1347 #elif CPUINFO_ARCH_X86
1348 return cpuinfo_isa.popcnt;
1349 #else
1350 return false;
1351 #endif
1352 }
1353
cpuinfo_has_x86_tbm(void)1354 static inline bool cpuinfo_has_x86_tbm(void) {
1355 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1356 return cpuinfo_isa.tbm;
1357 #else
1358 return false;
1359 #endif
1360 }
1361
cpuinfo_has_x86_bmi(void)1362 static inline bool cpuinfo_has_x86_bmi(void) {
1363 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1364 return cpuinfo_isa.bmi;
1365 #else
1366 return false;
1367 #endif
1368 }
1369
cpuinfo_has_x86_bmi2(void)1370 static inline bool cpuinfo_has_x86_bmi2(void) {
1371 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1372 return cpuinfo_isa.bmi2;
1373 #else
1374 return false;
1375 #endif
1376 }
1377
cpuinfo_has_x86_adx(void)1378 static inline bool cpuinfo_has_x86_adx(void) {
1379 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1380 return cpuinfo_isa.adx;
1381 #else
1382 return false;
1383 #endif
1384 }
1385
cpuinfo_has_x86_aes(void)1386 static inline bool cpuinfo_has_x86_aes(void) {
1387 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1388 return cpuinfo_isa.aes;
1389 #else
1390 return false;
1391 #endif
1392 }
1393
cpuinfo_has_x86_vaes(void)1394 static inline bool cpuinfo_has_x86_vaes(void) {
1395 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1396 return cpuinfo_isa.vaes;
1397 #else
1398 return false;
1399 #endif
1400 }
1401
cpuinfo_has_x86_pclmulqdq(void)1402 static inline bool cpuinfo_has_x86_pclmulqdq(void) {
1403 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1404 return cpuinfo_isa.pclmulqdq;
1405 #else
1406 return false;
1407 #endif
1408 }
1409
cpuinfo_has_x86_vpclmulqdq(void)1410 static inline bool cpuinfo_has_x86_vpclmulqdq(void) {
1411 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1412 return cpuinfo_isa.vpclmulqdq;
1413 #else
1414 return false;
1415 #endif
1416 }
1417
cpuinfo_has_x86_gfni(void)1418 static inline bool cpuinfo_has_x86_gfni(void) {
1419 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1420 return cpuinfo_isa.gfni;
1421 #else
1422 return false;
1423 #endif
1424 }
1425
cpuinfo_has_x86_rdrand(void)1426 static inline bool cpuinfo_has_x86_rdrand(void) {
1427 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1428 return cpuinfo_isa.rdrand;
1429 #else
1430 return false;
1431 #endif
1432 }
1433
cpuinfo_has_x86_rdseed(void)1434 static inline bool cpuinfo_has_x86_rdseed(void) {
1435 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1436 return cpuinfo_isa.rdseed;
1437 #else
1438 return false;
1439 #endif
1440 }
1441
cpuinfo_has_x86_sha(void)1442 static inline bool cpuinfo_has_x86_sha(void) {
1443 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1444 return cpuinfo_isa.sha;
1445 #else
1446 return false;
1447 #endif
1448 }
1449
1450 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1451 /* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions instead. */
1452 struct cpuinfo_arm_isa {
1453 #if CPUINFO_ARCH_ARM
1454 bool thumb;
1455 bool thumb2;
1456 bool thumbee;
1457 bool jazelle;
1458 bool armv5e;
1459 bool armv6;
1460 bool armv6k;
1461 bool armv7;
1462 bool armv7mp;
1463 bool armv8;
1464 bool idiv;
1465
1466 bool vfpv2;
1467 bool vfpv3;
1468 bool d32;
1469 bool fp16;
1470 bool fma;
1471
1472 bool wmmx;
1473 bool wmmx2;
1474 bool neon;
1475 #endif
1476 #if CPUINFO_ARCH_ARM64
1477 bool atomics;
1478 bool bf16;
1479 bool sve;
1480 bool sve2;
1481 bool i8mm;
1482 #endif
1483 bool rdm;
1484 bool fp16arith;
1485 bool dot;
1486 bool jscvt;
1487 bool fcma;
1488 bool fhm;
1489
1490 bool aes;
1491 bool sha1;
1492 bool sha2;
1493 bool pmull;
1494 bool crc32;
1495 };
1496
1497 extern struct cpuinfo_arm_isa cpuinfo_isa;
1498 #endif
1499
cpuinfo_has_arm_thumb(void)1500 static inline bool cpuinfo_has_arm_thumb(void) {
1501 #if CPUINFO_ARCH_ARM
1502 return cpuinfo_isa.thumb;
1503 #else
1504 return false;
1505 #endif
1506 }
1507
cpuinfo_has_arm_thumb2(void)1508 static inline bool cpuinfo_has_arm_thumb2(void) {
1509 #if CPUINFO_ARCH_ARM
1510 return cpuinfo_isa.thumb2;
1511 #else
1512 return false;
1513 #endif
1514 }
1515
cpuinfo_has_arm_v5e(void)1516 static inline bool cpuinfo_has_arm_v5e(void) {
1517 #if CPUINFO_ARCH_ARM
1518 return cpuinfo_isa.armv5e;
1519 #else
1520 return false;
1521 #endif
1522 }
1523
cpuinfo_has_arm_v6(void)1524 static inline bool cpuinfo_has_arm_v6(void) {
1525 #if CPUINFO_ARCH_ARM
1526 return cpuinfo_isa.armv6;
1527 #else
1528 return false;
1529 #endif
1530 }
1531
cpuinfo_has_arm_v6k(void)1532 static inline bool cpuinfo_has_arm_v6k(void) {
1533 #if CPUINFO_ARCH_ARM
1534 return cpuinfo_isa.armv6k;
1535 #else
1536 return false;
1537 #endif
1538 }
1539
cpuinfo_has_arm_v7(void)1540 static inline bool cpuinfo_has_arm_v7(void) {
1541 #if CPUINFO_ARCH_ARM
1542 return cpuinfo_isa.armv7;
1543 #else
1544 return false;
1545 #endif
1546 }
1547
cpuinfo_has_arm_v7mp(void)1548 static inline bool cpuinfo_has_arm_v7mp(void) {
1549 #if CPUINFO_ARCH_ARM
1550 return cpuinfo_isa.armv7mp;
1551 #else
1552 return false;
1553 #endif
1554 }
1555
cpuinfo_has_arm_v8(void)1556 static inline bool cpuinfo_has_arm_v8(void) {
1557 #if CPUINFO_ARCH_ARM64
1558 return true;
1559 #elif CPUINFO_ARCH_ARM
1560 return cpuinfo_isa.armv8;
1561 #else
1562 return false;
1563 #endif
1564 }
1565
cpuinfo_has_arm_idiv(void)1566 static inline bool cpuinfo_has_arm_idiv(void) {
1567 #if CPUINFO_ARCH_ARM64
1568 return true;
1569 #elif CPUINFO_ARCH_ARM
1570 return cpuinfo_isa.idiv;
1571 #else
1572 return false;
1573 #endif
1574 }
1575
cpuinfo_has_arm_vfpv2(void)1576 static inline bool cpuinfo_has_arm_vfpv2(void) {
1577 #if CPUINFO_ARCH_ARM
1578 return cpuinfo_isa.vfpv2;
1579 #else
1580 return false;
1581 #endif
1582 }
1583
cpuinfo_has_arm_vfpv3(void)1584 static inline bool cpuinfo_has_arm_vfpv3(void) {
1585 #if CPUINFO_ARCH_ARM64
1586 return true;
1587 #elif CPUINFO_ARCH_ARM
1588 return cpuinfo_isa.vfpv3;
1589 #else
1590 return false;
1591 #endif
1592 }
1593
cpuinfo_has_arm_vfpv3_d32(void)1594 static inline bool cpuinfo_has_arm_vfpv3_d32(void) {
1595 #if CPUINFO_ARCH_ARM64
1596 return true;
1597 #elif CPUINFO_ARCH_ARM
1598 return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32;
1599 #else
1600 return false;
1601 #endif
1602 }
1603
cpuinfo_has_arm_vfpv3_fp16(void)1604 static inline bool cpuinfo_has_arm_vfpv3_fp16(void) {
1605 #if CPUINFO_ARCH_ARM64
1606 return true;
1607 #elif CPUINFO_ARCH_ARM
1608 return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16;
1609 #else
1610 return false;
1611 #endif
1612 }
1613
cpuinfo_has_arm_vfpv3_fp16_d32(void)1614 static inline bool cpuinfo_has_arm_vfpv3_fp16_d32(void) {
1615 #if CPUINFO_ARCH_ARM64
1616 return true;
1617 #elif CPUINFO_ARCH_ARM
1618 return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32;
1619 #else
1620 return false;
1621 #endif
1622 }
1623
cpuinfo_has_arm_vfpv4(void)1624 static inline bool cpuinfo_has_arm_vfpv4(void) {
1625 #if CPUINFO_ARCH_ARM64
1626 return true;
1627 #elif CPUINFO_ARCH_ARM
1628 return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma;
1629 #else
1630 return false;
1631 #endif
1632 }
1633
cpuinfo_has_arm_vfpv4_d32(void)1634 static inline bool cpuinfo_has_arm_vfpv4_d32(void) {
1635 #if CPUINFO_ARCH_ARM64
1636 return true;
1637 #elif CPUINFO_ARCH_ARM
1638 return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32;
1639 #else
1640 return false;
1641 #endif
1642 }
1643
cpuinfo_has_arm_fp16_arith(void)1644 static inline bool cpuinfo_has_arm_fp16_arith(void) {
1645 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1646 return cpuinfo_isa.fp16arith;
1647 #else
1648 return false;
1649 #endif
1650 }
1651
cpuinfo_has_arm_bf16(void)1652 static inline bool cpuinfo_has_arm_bf16(void) {
1653 #if CPUINFO_ARCH_ARM64
1654 return cpuinfo_isa.bf16;
1655 #else
1656 return false;
1657 #endif
1658 }
1659
cpuinfo_has_arm_wmmx(void)1660 static inline bool cpuinfo_has_arm_wmmx(void) {
1661 #if CPUINFO_ARCH_ARM
1662 return cpuinfo_isa.wmmx;
1663 #else
1664 return false;
1665 #endif
1666 }
1667
cpuinfo_has_arm_wmmx2(void)1668 static inline bool cpuinfo_has_arm_wmmx2(void) {
1669 #if CPUINFO_ARCH_ARM
1670 return cpuinfo_isa.wmmx2;
1671 #else
1672 return false;
1673 #endif
1674 }
1675
cpuinfo_has_arm_neon(void)1676 static inline bool cpuinfo_has_arm_neon(void) {
1677 #if CPUINFO_ARCH_ARM64
1678 return true;
1679 #elif CPUINFO_ARCH_ARM
1680 return cpuinfo_isa.neon;
1681 #else
1682 return false;
1683 #endif
1684 }
1685
cpuinfo_has_arm_neon_fp16(void)1686 static inline bool cpuinfo_has_arm_neon_fp16(void) {
1687 #if CPUINFO_ARCH_ARM64
1688 return true;
1689 #elif CPUINFO_ARCH_ARM
1690 return cpuinfo_isa.neon && cpuinfo_isa.fp16;
1691 #else
1692 return false;
1693 #endif
1694 }
1695
cpuinfo_has_arm_neon_fma(void)1696 static inline bool cpuinfo_has_arm_neon_fma(void) {
1697 #if CPUINFO_ARCH_ARM64
1698 return true;
1699 #elif CPUINFO_ARCH_ARM
1700 return cpuinfo_isa.neon && cpuinfo_isa.fma;
1701 #else
1702 return false;
1703 #endif
1704 }
1705
cpuinfo_has_arm_neon_v8(void)1706 static inline bool cpuinfo_has_arm_neon_v8(void) {
1707 #if CPUINFO_ARCH_ARM64
1708 return true;
1709 #elif CPUINFO_ARCH_ARM
1710 return cpuinfo_isa.neon && cpuinfo_isa.armv8;
1711 #else
1712 return false;
1713 #endif
1714 }
1715
cpuinfo_has_arm_atomics(void)1716 static inline bool cpuinfo_has_arm_atomics(void) {
1717 #if CPUINFO_ARCH_ARM64
1718 return cpuinfo_isa.atomics;
1719 #else
1720 return false;
1721 #endif
1722 }
1723
cpuinfo_has_arm_neon_rdm(void)1724 static inline bool cpuinfo_has_arm_neon_rdm(void) {
1725 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1726 return cpuinfo_isa.rdm;
1727 #else
1728 return false;
1729 #endif
1730 }
1731
cpuinfo_has_arm_neon_fp16_arith(void)1732 static inline bool cpuinfo_has_arm_neon_fp16_arith(void) {
1733 #if CPUINFO_ARCH_ARM
1734 return cpuinfo_isa.neon && cpuinfo_isa.fp16arith;
1735 #elif CPUINFO_ARCH_ARM64
1736 return cpuinfo_isa.fp16arith;
1737 #else
1738 return false;
1739 #endif
1740 }
1741
cpuinfo_has_arm_fhm(void)1742 static inline bool cpuinfo_has_arm_fhm(void) {
1743 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1744 return cpuinfo_isa.fhm;
1745 #else
1746 return false;
1747 #endif
1748 }
1749
cpuinfo_has_arm_neon_dot(void)1750 static inline bool cpuinfo_has_arm_neon_dot(void) {
1751 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1752 return cpuinfo_isa.dot;
1753 #else
1754 return false;
1755 #endif
1756 }
1757
cpuinfo_has_arm_neon_bf16(void)1758 static inline bool cpuinfo_has_arm_neon_bf16(void) {
1759 #if CPUINFO_ARCH_ARM64
1760 return cpuinfo_isa.bf16;
1761 #else
1762 return false;
1763 #endif
1764 }
1765
cpuinfo_has_arm_jscvt(void)1766 static inline bool cpuinfo_has_arm_jscvt(void) {
1767 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1768 return cpuinfo_isa.jscvt;
1769 #else
1770 return false;
1771 #endif
1772 }
1773
cpuinfo_has_arm_fcma(void)1774 static inline bool cpuinfo_has_arm_fcma(void) {
1775 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1776 return cpuinfo_isa.fcma;
1777 #else
1778 return false;
1779 #endif
1780 }
1781
cpuinfo_has_arm_i8mm(void)1782 static inline bool cpuinfo_has_arm_i8mm(void) {
1783 #if CPUINFO_ARCH_ARM64
1784 return cpuinfo_isa.i8mm;
1785 #else
1786 return false;
1787 #endif
1788 }
1789
cpuinfo_has_arm_aes(void)1790 static inline bool cpuinfo_has_arm_aes(void) {
1791 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1792 return cpuinfo_isa.aes;
1793 #else
1794 return false;
1795 #endif
1796 }
1797
cpuinfo_has_arm_sha1(void)1798 static inline bool cpuinfo_has_arm_sha1(void) {
1799 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1800 return cpuinfo_isa.sha1;
1801 #else
1802 return false;
1803 #endif
1804 }
1805
cpuinfo_has_arm_sha2(void)1806 static inline bool cpuinfo_has_arm_sha2(void) {
1807 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1808 return cpuinfo_isa.sha2;
1809 #else
1810 return false;
1811 #endif
1812 }
1813
cpuinfo_has_arm_pmull(void)1814 static inline bool cpuinfo_has_arm_pmull(void) {
1815 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1816 return cpuinfo_isa.pmull;
1817 #else
1818 return false;
1819 #endif
1820 }
1821
cpuinfo_has_arm_crc32(void)1822 static inline bool cpuinfo_has_arm_crc32(void) {
1823 #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
1824 return cpuinfo_isa.crc32;
1825 #else
1826 return false;
1827 #endif
1828 }
1829
cpuinfo_has_arm_sve(void)1830 static inline bool cpuinfo_has_arm_sve(void) {
1831 #if CPUINFO_ARCH_ARM64
1832 return cpuinfo_isa.sve;
1833 #else
1834 return false;
1835 #endif
1836 }
1837
cpuinfo_has_arm_sve_bf16(void)1838 static inline bool cpuinfo_has_arm_sve_bf16(void) {
1839 #if CPUINFO_ARCH_ARM64
1840 return cpuinfo_isa.sve && cpuinfo_isa.bf16;
1841 #else
1842 return false;
1843 #endif
1844 }
1845
cpuinfo_has_arm_sve2(void)1846 static inline bool cpuinfo_has_arm_sve2(void) {
1847 #if CPUINFO_ARCH_ARM64
1848 return cpuinfo_isa.sve2;
1849 #else
1850 return false;
1851 #endif
1852 }
1853
1854 const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void);
1855 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_cores(void);
1856 const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_clusters(void);
1857 const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_packages(void);
1858 const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarchs(void);
1859 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void);
1860 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void);
1861 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void);
1862 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_caches(void);
1863 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_caches(void);
1864
1865 const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processor(uint32_t index);
1866 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_core(uint32_t index);
1867 const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_cluster(uint32_t index);
1868 const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_package(uint32_t index);
1869 const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarch(uint32_t index);
1870 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index);
1871 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index);
1872 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index);
1873 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_cache(uint32_t index);
1874 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_cache(uint32_t index);
1875
1876 uint32_t CPUINFO_ABI cpuinfo_get_processors_count(void);
1877 uint32_t CPUINFO_ABI cpuinfo_get_cores_count(void);
1878 uint32_t CPUINFO_ABI cpuinfo_get_clusters_count(void);
1879 uint32_t CPUINFO_ABI cpuinfo_get_packages_count(void);
1880 uint32_t CPUINFO_ABI cpuinfo_get_uarchs_count(void);
1881 uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void);
1882 uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void);
1883 uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void);
1884 uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void);
1885 uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void);
1886
1887 /**
1888 * Returns upper bound on cache size.
1889 */
1890 uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void);
1891
1892 /**
1893 * Identify the logical processor that executes the current thread.
1894 *
1895 * There is no guarantee that the thread will stay on the same logical processor for any time.
1896 * Callers should treat the result as only a hint, and be prepared to handle NULL return value.
1897 */
1898 const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void);
1899
1900 /**
1901 * Identify the core that executes the current thread.
1902 *
1903 * There is no guarantee that the thread will stay on the same core for any time.
1904 * Callers should treat the result as only a hint, and be prepared to handle NULL return value.
1905 */
1906 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void);
1907
1908 /**
1909 * Identify the microarchitecture index of the core that executes the current thread.
1910 * If the system does not support such identification, the function returns 0.
1911 *
1912 * There is no guarantee that the thread will stay on the same type of core for any time.
1913 * Callers should treat the result as only a hint.
1914 */
1915 uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void);
1916
1917 /**
1918 * Identify the microarchitecture index of the core that executes the current thread.
1919 * If the system does not support such identification, the function returns the user-specified default value.
1920 *
1921 * There is no guarantee that the thread will stay on the same type of core for any time.
1922 * Callers should treat the result as only a hint.
1923 */
1924 uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index);
1925
1926 #ifdef __cplusplus
1927 } /* extern "C" */
1928 #endif
1929
1930 #endif /* CPUINFO_H */
1931