1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /** 25 * \file amdgpu.h 26 * 27 * Declare public libdrm_amdgpu API 28 * 29 * This file define API exposed by libdrm_amdgpu library. 30 * User wanted to use libdrm_amdgpu functionality must include 31 * this file. 32 * 33 */ 34 #ifndef _AMDGPU_H_ 35 #define _AMDGPU_H_ 36 37 #include <stdint.h> 38 #include <stdbool.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 struct drm_amdgpu_info_hw_ip; 45 struct drm_amdgpu_bo_list_entry; 46 47 /*--------------------------------------------------------------------------*/ 48 /* --------------------------- Defines ------------------------------------ */ 49 /*--------------------------------------------------------------------------*/ 50 51 /** 52 * Define max. number of Command Buffers (IB) which could be sent to the single 53 * hardware IP to accommodate CE/DE requirements 54 * 55 * \sa amdgpu_cs_ib_info 56 */ 57 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 58 59 /** 60 * Special timeout value meaning that the timeout is infinite. 61 */ 62 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 63 64 /** 65 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 66 * is absolute. 67 */ 68 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 69 70 /*--------------------------------------------------------------------------*/ 71 /* ----------------------------- Enums ------------------------------------ */ 72 /*--------------------------------------------------------------------------*/ 73 74 /** 75 * Enum describing possible handle types 76 * 77 * \sa amdgpu_bo_import, amdgpu_bo_export 78 * 79 */ 80 enum amdgpu_bo_handle_type { 81 /** GEM flink name (needs DRM authentication, used by DRI2) */ 82 amdgpu_bo_handle_type_gem_flink_name = 0, 83 84 /** KMS handle which is used by all driver ioctls */ 85 amdgpu_bo_handle_type_kms = 1, 86 87 /** DMA-buf fd handle */ 88 amdgpu_bo_handle_type_dma_buf_fd = 2, 89 90 /** Deprecated in favour of and same behaviour as 91 * amdgpu_bo_handle_type_kms, use that instead of this 92 */ 93 amdgpu_bo_handle_type_kms_noimport = 3, 94 }; 95 96 /** Define known types of GPU VM VA ranges */ 97 enum amdgpu_gpu_va_range 98 { 99 /** Allocate from "normal"/general range */ 100 amdgpu_gpu_va_range_general = 0 101 }; 102 103 enum amdgpu_sw_info { 104 amdgpu_sw_info_address32_hi = 0, 105 }; 106 107 /*--------------------------------------------------------------------------*/ 108 /* -------------------------- Datatypes ----------------------------------- */ 109 /*--------------------------------------------------------------------------*/ 110 111 /** 112 * Define opaque pointer to context associated with fd. 113 * This context will be returned as the result of 114 * "initialize" function and should be pass as the first 115 * parameter to any API call 116 */ 117 typedef struct amdgpu_device *amdgpu_device_handle; 118 119 /** 120 * Define GPU Context type as pointer to opaque structure 121 * Example of GPU Context is the "rendering" context associated 122 * with OpenGL context (glCreateContext) 123 */ 124 typedef struct amdgpu_context *amdgpu_context_handle; 125 126 /** 127 * Define handle for amdgpu resources: buffer, GDS, etc. 128 */ 129 typedef struct amdgpu_bo *amdgpu_bo_handle; 130 131 /** 132 * Define handle for list of BOs 133 */ 134 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 135 136 /** 137 * Define handle to be used to work with VA allocated ranges 138 */ 139 typedef struct amdgpu_va *amdgpu_va_handle; 140 141 /** 142 * Define handle for semaphore 143 */ 144 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 145 146 /*--------------------------------------------------------------------------*/ 147 /* -------------------------- Structures ---------------------------------- */ 148 /*--------------------------------------------------------------------------*/ 149 150 /** 151 * Structure describing memory allocation request 152 * 153 * \sa amdgpu_bo_alloc() 154 * 155 */ 156 struct amdgpu_bo_alloc_request { 157 /** Allocation request. It must be aligned correctly. */ 158 uint64_t alloc_size; 159 160 /** 161 * It may be required to have some specific alignment requirements 162 * for physical back-up storage (e.g. for displayable surface). 163 * If 0 there is no special alignment requirement 164 */ 165 uint64_t phys_alignment; 166 167 /** 168 * UMD should specify where to allocate memory and how it 169 * will be accessed by the CPU. 170 */ 171 uint32_t preferred_heap; 172 173 /** Additional flags passed on allocation */ 174 uint64_t flags; 175 }; 176 177 /** 178 * Special UMD specific information associated with buffer. 179 * 180 * It may be need to pass some buffer charactersitic as part 181 * of buffer sharing. Such information are defined UMD and 182 * opaque for libdrm_amdgpu as well for kernel driver. 183 * 184 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 185 * amdgpu_bo_import(), amdgpu_bo_export 186 * 187 */ 188 struct amdgpu_bo_metadata { 189 /** Special flag associated with surface */ 190 uint64_t flags; 191 192 /** 193 * ASIC-specific tiling information (also used by DCE). 194 * The encoding is defined by the AMDGPU_TILING_* definitions. 195 */ 196 uint64_t tiling_info; 197 198 /** Size of metadata associated with the buffer, in bytes. */ 199 uint32_t size_metadata; 200 201 /** UMD specific metadata. Opaque for kernel */ 202 uint32_t umd_metadata[64]; 203 }; 204 205 /** 206 * Structure describing allocated buffer. Client may need 207 * to query such information as part of 'sharing' buffers mechanism 208 * 209 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 210 * amdgpu_bo_import(), amdgpu_bo_export() 211 */ 212 struct amdgpu_bo_info { 213 /** Allocated memory size */ 214 uint64_t alloc_size; 215 216 /** 217 * It may be required to have some specific alignment requirements 218 * for physical back-up storage. 219 */ 220 uint64_t phys_alignment; 221 222 /** Heap where to allocate memory. */ 223 uint32_t preferred_heap; 224 225 /** Additional allocation flags. */ 226 uint64_t alloc_flags; 227 228 /** Metadata associated with buffer if any. */ 229 struct amdgpu_bo_metadata metadata; 230 }; 231 232 /** 233 * Structure with information about "imported" buffer 234 * 235 * \sa amdgpu_bo_import() 236 * 237 */ 238 struct amdgpu_bo_import_result { 239 /** Handle of memory/buffer to use */ 240 amdgpu_bo_handle buf_handle; 241 242 /** Buffer size */ 243 uint64_t alloc_size; 244 }; 245 246 /** 247 * 248 * Structure to describe GDS partitioning information. 249 * \note OA and GWS resources are asscoiated with GDS partition 250 * 251 * \sa amdgpu_gpu_resource_query_gds_info 252 * 253 */ 254 struct amdgpu_gds_resource_info { 255 uint32_t gds_gfx_partition_size; 256 uint32_t compute_partition_size; 257 uint32_t gds_total_size; 258 uint32_t gws_per_gfx_partition; 259 uint32_t gws_per_compute_partition; 260 uint32_t oa_per_gfx_partition; 261 uint32_t oa_per_compute_partition; 262 }; 263 264 /** 265 * Structure describing CS fence 266 * 267 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 268 * 269 */ 270 struct amdgpu_cs_fence { 271 272 /** In which context IB was sent to execution */ 273 amdgpu_context_handle context; 274 275 /** To which HW IP type the fence belongs */ 276 uint32_t ip_type; 277 278 /** IP instance index if there are several IPs of the same type. */ 279 uint32_t ip_instance; 280 281 /** Ring index of the HW IP */ 282 uint32_t ring; 283 284 /** Specify fence for which we need to check submission status.*/ 285 uint64_t fence; 286 }; 287 288 /** 289 * Structure describing IB 290 * 291 * \sa amdgpu_cs_request, amdgpu_cs_submit() 292 * 293 */ 294 struct amdgpu_cs_ib_info { 295 /** Special flags */ 296 uint64_t flags; 297 298 /** Virtual MC address of the command buffer */ 299 uint64_t ib_mc_address; 300 301 /** 302 * Size of Command Buffer to be submitted. 303 * - The size is in units of dwords (4 bytes). 304 * - Could be 0 305 */ 306 uint32_t size; 307 }; 308 309 /** 310 * Structure describing fence information 311 * 312 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 313 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 314 */ 315 struct amdgpu_cs_fence_info { 316 /** buffer object for the fence */ 317 amdgpu_bo_handle handle; 318 319 /** fence offset in the unit of sizeof(uint64_t) */ 320 uint64_t offset; 321 }; 322 323 /** 324 * Structure describing submission request 325 * 326 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 327 * 328 * \sa amdgpu_cs_submit() 329 */ 330 struct amdgpu_cs_request { 331 /** Specify flags with additional information */ 332 uint64_t flags; 333 334 /** Specify HW IP block type to which to send the IB. */ 335 unsigned ip_type; 336 337 /** IP instance index if there are several IPs of the same type. */ 338 unsigned ip_instance; 339 340 /** 341 * Specify ring index of the IP. We could have several rings 342 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 343 */ 344 uint32_t ring; 345 346 /** 347 * List handle with resources used by this request. 348 */ 349 amdgpu_bo_list_handle resources; 350 351 /** 352 * Number of dependencies this Command submission needs to 353 * wait for before starting execution. 354 */ 355 uint32_t number_of_dependencies; 356 357 /** 358 * Array of dependencies which need to be met before 359 * execution can start. 360 */ 361 struct amdgpu_cs_fence *dependencies; 362 363 /** Number of IBs to submit in the field ibs. */ 364 uint32_t number_of_ibs; 365 366 /** 367 * IBs to submit. Those IBs will be submit together as single entity 368 */ 369 struct amdgpu_cs_ib_info *ibs; 370 371 /** 372 * The returned sequence number for the command submission 373 */ 374 uint64_t seq_no; 375 376 /** 377 * The fence information 378 */ 379 struct amdgpu_cs_fence_info fence_info; 380 }; 381 382 /** 383 * Structure which provide information about GPU VM MC Address space 384 * alignments requirements 385 * 386 * \sa amdgpu_query_buffer_size_alignment 387 */ 388 struct amdgpu_buffer_size_alignments { 389 /** Size alignment requirement for allocation in 390 * local memory */ 391 uint64_t size_local; 392 393 /** 394 * Size alignment requirement for allocation in remote memory 395 */ 396 uint64_t size_remote; 397 }; 398 399 /** 400 * Structure which provide information about heap 401 * 402 * \sa amdgpu_query_heap_info() 403 * 404 */ 405 struct amdgpu_heap_info { 406 /** Theoretical max. available memory in the given heap */ 407 uint64_t heap_size; 408 409 /** 410 * Number of bytes allocated in the heap. This includes all processes 411 * and private allocations in the kernel. It changes when new buffers 412 * are allocated, freed, and moved. It cannot be larger than 413 * heap_size. 414 */ 415 uint64_t heap_usage; 416 417 /** 418 * Theoretical possible max. size of buffer which 419 * could be allocated in the given heap 420 */ 421 uint64_t max_allocation; 422 }; 423 424 /** 425 * Describe GPU h/w info needed for UMD correct initialization 426 * 427 * \sa amdgpu_query_gpu_info() 428 */ 429 struct amdgpu_gpu_info { 430 /** Asic id */ 431 uint32_t asic_id; 432 /** Chip revision */ 433 uint32_t chip_rev; 434 /** Chip external revision */ 435 uint32_t chip_external_rev; 436 /** Family ID */ 437 uint32_t family_id; 438 /** Special flags */ 439 uint64_t ids_flags; 440 /** max engine clock*/ 441 uint64_t max_engine_clk; 442 /** max memory clock */ 443 uint64_t max_memory_clk; 444 /** number of shader engines */ 445 uint32_t num_shader_engines; 446 /** number of shader arrays per engine */ 447 uint32_t num_shader_arrays_per_engine; 448 /** Number of available good shader pipes */ 449 uint32_t avail_quad_shader_pipes; 450 /** Max. number of shader pipes.(including good and bad pipes */ 451 uint32_t max_quad_shader_pipes; 452 /** Number of parameter cache entries per shader quad pipe */ 453 uint32_t cache_entries_per_quad_pipe; 454 /** Number of available graphics context */ 455 uint32_t num_hw_gfx_contexts; 456 /** Number of render backend pipes */ 457 uint32_t rb_pipes; 458 /** Enabled render backend pipe mask */ 459 uint32_t enabled_rb_pipes_mask; 460 /** Frequency of GPU Counter */ 461 uint32_t gpu_counter_freq; 462 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 463 uint32_t backend_disable[4]; 464 /** Value of MC_ARB_RAMCFG register*/ 465 uint32_t mc_arb_ramcfg; 466 /** Value of GB_ADDR_CONFIG */ 467 uint32_t gb_addr_cfg; 468 /** Values of the GB_TILE_MODE0..31 registers */ 469 uint32_t gb_tile_mode[32]; 470 /** Values of GB_MACROTILE_MODE0..15 registers */ 471 uint32_t gb_macro_tile_mode[16]; 472 /** Value of PA_SC_RASTER_CONFIG register per SE */ 473 uint32_t pa_sc_raster_cfg[4]; 474 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 475 uint32_t pa_sc_raster_cfg1[4]; 476 /* CU info */ 477 uint32_t cu_active_number; 478 uint32_t cu_ao_mask; 479 uint32_t cu_bitmap[4][4]; 480 /* video memory type info*/ 481 uint32_t vram_type; 482 /* video memory bit width*/ 483 uint32_t vram_bit_width; 484 /** constant engine ram size*/ 485 uint32_t ce_ram_size; 486 /* vce harvesting instance */ 487 uint32_t vce_harvest_config; 488 /* PCI revision ID */ 489 uint32_t pci_rev_id; 490 }; 491 492 493 /*--------------------------------------------------------------------------*/ 494 /*------------------------- Functions --------------------------------------*/ 495 /*--------------------------------------------------------------------------*/ 496 497 /* 498 * Initialization / Cleanup 499 * 500 */ 501 502 /** 503 * 504 * \param fd - \c [in] File descriptor for AMD GPU device 505 * received previously as the result of 506 * e.g. drmOpen() call. 507 * For legacy fd type, the DRI2/DRI3 508 * authentication should be done before 509 * calling this function. 510 * \param major_version - \c [out] Major version of library. It is assumed 511 * that adding new functionality will cause 512 * increase in major version 513 * \param minor_version - \c [out] Minor version of library 514 * \param device_handle - \c [out] Pointer to opaque context which should 515 * be passed as the first parameter on each 516 * API call 517 * 518 * 519 * \return 0 on success\n 520 * <0 - Negative POSIX Error code 521 * 522 * 523 * \sa amdgpu_device_deinitialize() 524 */ 525 int amdgpu_device_initialize(int fd, 526 uint32_t *major_version, 527 uint32_t *minor_version, 528 amdgpu_device_handle *device_handle); 529 530 /** 531 * 532 * When access to such library does not needed any more the special 533 * function must be call giving opportunity to clean up any 534 * resources if needed. 535 * 536 * \param device_handle - \c [in] Context associated with file 537 * descriptor for AMD GPU device 538 * received previously as the 539 * result e.g. of drmOpen() call. 540 * 541 * \return 0 on success\n 542 * <0 - Negative POSIX Error code 543 * 544 * \sa amdgpu_device_initialize() 545 * 546 */ 547 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 548 549 /** 550 * 551 * /param device_handle - \c [in] Device handle. 552 * See #amdgpu_device_initialize() 553 * 554 * \return Returns the drm fd used for operations on this 555 * device. This is still owned by the library and hence 556 * should not be closed. Guaranteed to be valid until 557 * #amdgpu_device_deinitialize gets called. 558 * 559 */ 560 int amdgpu_device_get_fd(amdgpu_device_handle device_handle); 561 562 /* 563 * Memory Management 564 * 565 */ 566 567 /** 568 * Allocate memory to be used by UMD for GPU related operations 569 * 570 * \param dev - \c [in] Device handle. 571 * See #amdgpu_device_initialize() 572 * \param alloc_buffer - \c [in] Pointer to the structure describing an 573 * allocation request 574 * \param buf_handle - \c [out] Allocated buffer handle 575 * 576 * \return 0 on success\n 577 * <0 - Negative POSIX Error code 578 * 579 * \sa amdgpu_bo_free() 580 */ 581 int amdgpu_bo_alloc(amdgpu_device_handle dev, 582 struct amdgpu_bo_alloc_request *alloc_buffer, 583 amdgpu_bo_handle *buf_handle); 584 585 /** 586 * Associate opaque data with buffer to be queried by another UMD 587 * 588 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 589 * \param buf_handle - \c [in] Buffer handle 590 * \param info - \c [in] Metadata to associated with buffer 591 * 592 * \return 0 on success\n 593 * <0 - Negative POSIX Error code 594 */ 595 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 596 struct amdgpu_bo_metadata *info); 597 598 /** 599 * Query buffer information including metadata previusly associated with 600 * buffer. 601 * 602 * \param dev - \c [in] Device handle. 603 * See #amdgpu_device_initialize() 604 * \param buf_handle - \c [in] Buffer handle 605 * \param info - \c [out] Structure describing buffer 606 * 607 * \return 0 on success\n 608 * <0 - Negative POSIX Error code 609 * 610 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 611 */ 612 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 613 struct amdgpu_bo_info *info); 614 615 /** 616 * Allow others to get access to buffer 617 * 618 * \param dev - \c [in] Device handle. 619 * See #amdgpu_device_initialize() 620 * \param buf_handle - \c [in] Buffer handle 621 * \param type - \c [in] Type of handle requested 622 * \param shared_handle - \c [out] Special "shared" handle 623 * 624 * \return 0 on success\n 625 * <0 - Negative POSIX Error code 626 * 627 * \sa amdgpu_bo_import() 628 * 629 */ 630 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 631 enum amdgpu_bo_handle_type type, 632 uint32_t *shared_handle); 633 634 /** 635 * Request access to "shared" buffer 636 * 637 * \param dev - \c [in] Device handle. 638 * See #amdgpu_device_initialize() 639 * \param type - \c [in] Type of handle requested 640 * \param shared_handle - \c [in] Shared handle received as result "import" 641 * operation 642 * \param output - \c [out] Pointer to structure with information 643 * about imported buffer 644 * 645 * \return 0 on success\n 646 * <0 - Negative POSIX Error code 647 * 648 * \note Buffer must be "imported" only using new "fd" (different from 649 * one used by "exporter"). 650 * 651 * \sa amdgpu_bo_export() 652 * 653 */ 654 int amdgpu_bo_import(amdgpu_device_handle dev, 655 enum amdgpu_bo_handle_type type, 656 uint32_t shared_handle, 657 struct amdgpu_bo_import_result *output); 658 659 /** 660 * Request GPU access to user allocated memory e.g. via "malloc" 661 * 662 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 663 * \param cpu - [in] CPU address of user allocated memory which we 664 * want to map to GPU address space (make GPU accessible) 665 * (This address must be correctly aligned). 666 * \param size - [in] Size of allocation (must be correctly aligned) 667 * \param buf_handle - [out] Buffer handle for the userptr memory 668 * resource on submission and be used in other operations. 669 * 670 * 671 * \return 0 on success\n 672 * <0 - Negative POSIX Error code 673 * 674 * \note 675 * This call doesn't guarantee that such memory will be persistently 676 * "locked" / make non-pageable. The purpose of this call is to provide 677 * opportunity for GPU get access to this resource during submission. 678 * 679 * The maximum amount of memory which could be mapped in this call depends 680 * if overcommit is disabled or not. If overcommit is disabled than the max. 681 * amount of memory to be pinned will be limited by left "free" size in total 682 * amount of memory which could be locked simultaneously ("GART" size). 683 * 684 * Supported (theoretical) max. size of mapping is restricted only by 685 * "GART" size. 686 * 687 * It is responsibility of caller to correctly specify access rights 688 * on VA assignment. 689 */ 690 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 691 void *cpu, uint64_t size, 692 amdgpu_bo_handle *buf_handle); 693 694 /** 695 * Validate if the user memory comes from BO 696 * 697 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 698 * \param cpu - [in] CPU address of user allocated memory which we 699 * want to map to GPU address space (make GPU accessible) 700 * (This address must be correctly aligned). 701 * \param size - [in] Size of allocation (must be correctly aligned) 702 * \param buf_handle - [out] Buffer handle for the userptr memory 703 * if the user memory is not from BO, the buf_handle will be NULL. 704 * \param offset_in_bo - [out] offset in this BO for this user memory 705 * 706 * 707 * \return 0 on success\n 708 * <0 - Negative POSIX Error code 709 * 710 */ 711 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 712 void *cpu, 713 uint64_t size, 714 amdgpu_bo_handle *buf_handle, 715 uint64_t *offset_in_bo); 716 717 /** 718 * Free previously allocated memory 719 * 720 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 721 * \param buf_handle - \c [in] Buffer handle to free 722 * 723 * \return 0 on success\n 724 * <0 - Negative POSIX Error code 725 * 726 * \note In the case of memory shared between different applications all 727 * resources will be “physically” freed only all such applications 728 * will be terminated 729 * \note If is UMD responsibility to ‘free’ buffer only when there is no 730 * more GPU access 731 * 732 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 733 * 734 */ 735 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 736 737 /** 738 * Increase the reference count of a buffer object 739 * 740 * \param bo - \c [in] Buffer object handle to increase the reference count 741 * 742 * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 743 * 744 */ 745 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 746 747 /** 748 * Request CPU access to GPU accessible memory 749 * 750 * \param buf_handle - \c [in] Buffer handle 751 * \param cpu - \c [out] CPU address to be used for access 752 * 753 * \return 0 on success\n 754 * <0 - Negative POSIX Error code 755 * 756 * \sa amdgpu_bo_cpu_unmap() 757 * 758 */ 759 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 760 761 /** 762 * Release CPU access to GPU memory 763 * 764 * \param buf_handle - \c [in] Buffer handle 765 * 766 * \return 0 on success\n 767 * <0 - Negative POSIX Error code 768 * 769 * \sa amdgpu_bo_cpu_map() 770 * 771 */ 772 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 773 774 /** 775 * Wait until a buffer is not used by the device. 776 * 777 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 778 * \param buf_handle - \c [in] Buffer handle. 779 * \param timeout_ns - Timeout in nanoseconds. 780 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 781 * and no GPU access is scheduled. 782 * 1 GPU access is in fly or scheduled 783 * 784 * \return 0 - on success 785 * <0 - Negative POSIX Error code 786 */ 787 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 788 uint64_t timeout_ns, 789 bool *buffer_busy); 790 791 /** 792 * Creates a BO list handle for command submission. 793 * 794 * \param dev - \c [in] Device handle. 795 * See #amdgpu_device_initialize() 796 * \param number_of_buffers - \c [in] Number of BOs in the list 797 * \param buffers - \c [in] List of BO handles 798 * \param result - \c [out] Created BO list handle 799 * 800 * \return 0 on success\n 801 * <0 - Negative POSIX Error code 802 * 803 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() 804 */ 805 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, 806 uint32_t number_of_buffers, 807 struct drm_amdgpu_bo_list_entry *buffers, 808 uint32_t *result); 809 810 /** 811 * Destroys a BO list handle. 812 * 813 * \param bo_list - \c [in] BO list handle. 814 * 815 * \return 0 on success\n 816 * <0 - Negative POSIX Error code 817 * 818 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() 819 */ 820 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); 821 822 /** 823 * Creates a BO list handle for command submission. 824 * 825 * \param dev - \c [in] Device handle. 826 * See #amdgpu_device_initialize() 827 * \param number_of_resources - \c [in] Number of BOs in the list 828 * \param resources - \c [in] List of BO handles 829 * \param resource_prios - \c [in] Optional priority for each handle 830 * \param result - \c [out] Created BO list handle 831 * 832 * \return 0 on success\n 833 * <0 - Negative POSIX Error code 834 * 835 * \sa amdgpu_bo_list_destroy() 836 */ 837 int amdgpu_bo_list_create(amdgpu_device_handle dev, 838 uint32_t number_of_resources, 839 amdgpu_bo_handle *resources, 840 uint8_t *resource_prios, 841 amdgpu_bo_list_handle *result); 842 843 /** 844 * Destroys a BO list handle. 845 * 846 * \param handle - \c [in] BO list handle. 847 * 848 * \return 0 on success\n 849 * <0 - Negative POSIX Error code 850 * 851 * \sa amdgpu_bo_list_create() 852 */ 853 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 854 855 /** 856 * Update resources for existing BO list 857 * 858 * \param handle - \c [in] BO list handle 859 * \param number_of_resources - \c [in] Number of BOs in the list 860 * \param resources - \c [in] List of BO handles 861 * \param resource_prios - \c [in] Optional priority for each handle 862 * 863 * \return 0 on success\n 864 * <0 - Negative POSIX Error code 865 * 866 * \sa amdgpu_bo_list_update() 867 */ 868 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 869 uint32_t number_of_resources, 870 amdgpu_bo_handle *resources, 871 uint8_t *resource_prios); 872 873 /* 874 * GPU Execution context 875 * 876 */ 877 878 /** 879 * Create GPU execution Context 880 * 881 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 882 * necessary to have information/identify rendering/compute contexts. 883 * It also may be needed to associate some specific requirements with such 884 * contexts. Kernel driver will guarantee that submission from the same 885 * context will always be executed in order (first come, first serve). 886 * 887 * 888 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 889 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 890 * \param context - \c [out] GPU Context handle 891 * 892 * \return 0 on success\n 893 * <0 - Negative POSIX Error code 894 * 895 * \sa amdgpu_cs_ctx_free() 896 * 897 */ 898 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 899 uint32_t priority, 900 amdgpu_context_handle *context); 901 /** 902 * Create GPU execution Context 903 * 904 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 905 * is missing the priority parameter. 906 * 907 * \sa amdgpu_cs_ctx_create2() 908 * 909 */ 910 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 911 amdgpu_context_handle *context); 912 913 /** 914 * 915 * Destroy GPU execution context when not needed any more 916 * 917 * \param context - \c [in] GPU Context handle 918 * 919 * \return 0 on success\n 920 * <0 - Negative POSIX Error code 921 * 922 * \sa amdgpu_cs_ctx_create() 923 * 924 */ 925 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 926 927 /** 928 * Override the submission priority for the given context using a master fd. 929 * 930 * \param dev - \c [in] device handle 931 * \param context - \c [in] context handle for context id 932 * \param master_fd - \c [in] The master fd to authorize the override. 933 * \param priority - \c [in] The priority to assign to the context. 934 * 935 * \return 0 on success or a a negative Posix error code on failure. 936 */ 937 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, 938 amdgpu_context_handle context, 939 int master_fd, 940 unsigned priority); 941 942 /** 943 * Query reset state for the specific GPU Context 944 * 945 * \param context - \c [in] GPU Context handle 946 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 947 * \param hangs - \c [out] Number of hangs caused by the context. 948 * 949 * \return 0 on success\n 950 * <0 - Negative POSIX Error code 951 * 952 * \sa amdgpu_cs_ctx_create() 953 * 954 */ 955 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 956 uint32_t *state, uint32_t *hangs); 957 958 /** 959 * Query reset state for the specific GPU Context. 960 * 961 * \param context - \c [in] GPU Context handle 962 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_* 963 * 964 * \return 0 on success\n 965 * <0 - Negative POSIX Error code 966 * 967 * \sa amdgpu_cs_ctx_create() 968 * 969 */ 970 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context, 971 uint64_t *flags); 972 973 /* 974 * Command Buffers Management 975 * 976 */ 977 978 /** 979 * Send request to submit command buffers to hardware. 980 * 981 * Kernel driver could use GPU Scheduler to make decision when physically 982 * sent this request to the hardware. Accordingly this request could be put 983 * in queue and sent for execution later. The only guarantee is that request 984 * from the same GPU context to the same ip:ip_instance:ring will be executed in 985 * order. 986 * 987 * The caller can specify the user fence buffer/location with the fence_info in the 988 * cs_request.The sequence number is returned via the 'seq_no' parameter 989 * in ibs_request structure. 990 * 991 * 992 * \param dev - \c [in] Device handle. 993 * See #amdgpu_device_initialize() 994 * \param context - \c [in] GPU Context 995 * \param flags - \c [in] Global submission flags 996 * \param ibs_request - \c [in/out] Pointer to submission requests. 997 * We could submit to the several 998 * engines/rings simulteniously as 999 * 'atomic' operation 1000 * \param number_of_requests - \c [in] Number of submission requests 1001 * 1002 * \return 0 on success\n 1003 * <0 - Negative POSIX Error code 1004 * 1005 * \note It is required to pass correct resource list with buffer handles 1006 * which will be accessible by command buffers from submission 1007 * This will allow kernel driver to correctly implement "paging". 1008 * Failure to do so will have unpredictable results. 1009 * 1010 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 1011 * amdgpu_cs_query_fence_status() 1012 * 1013 */ 1014 int amdgpu_cs_submit(amdgpu_context_handle context, 1015 uint64_t flags, 1016 struct amdgpu_cs_request *ibs_request, 1017 uint32_t number_of_requests); 1018 1019 /** 1020 * Query status of Command Buffer Submission 1021 * 1022 * \param fence - \c [in] Structure describing fence to query 1023 * \param timeout_ns - \c [in] Timeout value to wait 1024 * \param flags - \c [in] Flags for the query 1025 * \param expired - \c [out] If fence expired or not.\n 1026 * 0 – if fence is not expired\n 1027 * !0 - otherwise 1028 * 1029 * \return 0 on success\n 1030 * <0 - Negative POSIX Error code 1031 * 1032 * \note If UMD wants only to check operation status and returned immediately 1033 * then timeout value as 0 must be passed. In this case success will be 1034 * returned in the case if submission was completed or timeout error 1035 * code. 1036 * 1037 * \sa amdgpu_cs_submit() 1038 */ 1039 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 1040 uint64_t timeout_ns, 1041 uint64_t flags, 1042 uint32_t *expired); 1043 1044 /** 1045 * Wait for multiple fences 1046 * 1047 * \param fences - \c [in] The fence array to wait 1048 * \param fence_count - \c [in] The fence count 1049 * \param wait_all - \c [in] If true, wait all fences to be signaled, 1050 * otherwise, wait at least one fence 1051 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 1052 * \param status - \c [out] '1' for signaled, '0' for timeout 1053 * \param first - \c [out] the index of the first signaled fence from @fences 1054 * 1055 * \return 0 on success 1056 * <0 - Negative POSIX Error code 1057 * 1058 * \note Currently it supports only one amdgpu_device. All fences come from 1059 * the same amdgpu_device with the same fd. 1060 */ 1061 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 1062 uint32_t fence_count, 1063 bool wait_all, 1064 uint64_t timeout_ns, 1065 uint32_t *status, uint32_t *first); 1066 1067 /* 1068 * Query / Info API 1069 * 1070 */ 1071 1072 /** 1073 * Query allocation size alignments 1074 * 1075 * UMD should query information about GPU VM MC size alignments requirements 1076 * to be able correctly choose required allocation size and implement 1077 * internal optimization if needed. 1078 * 1079 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1080 * \param info - \c [out] Pointer to structure to get size alignment 1081 * requirements 1082 * 1083 * \return 0 on success\n 1084 * <0 - Negative POSIX Error code 1085 * 1086 */ 1087 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 1088 struct amdgpu_buffer_size_alignments 1089 *info); 1090 1091 /** 1092 * Query firmware versions 1093 * 1094 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1095 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 1096 * \param ip_instance - \c [in] Index of the IP block of the same type. 1097 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 1098 * \param version - \c [out] Pointer to to the "version" return value 1099 * \param feature - \c [out] Pointer to to the "feature" return value 1100 * 1101 * \return 0 on success\n 1102 * <0 - Negative POSIX Error code 1103 * 1104 */ 1105 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 1106 unsigned ip_instance, unsigned index, 1107 uint32_t *version, uint32_t *feature); 1108 1109 /** 1110 * Query the number of HW IP instances of a certain type. 1111 * 1112 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1113 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1114 * \param count - \c [out] Pointer to structure to get information 1115 * 1116 * \return 0 on success\n 1117 * <0 - Negative POSIX Error code 1118 */ 1119 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1120 uint32_t *count); 1121 1122 /** 1123 * Query engine information 1124 * 1125 * This query allows UMD to query information different engines and their 1126 * capabilities. 1127 * 1128 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1129 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1130 * \param ip_instance - \c [in] Index of the IP block of the same type. 1131 * \param info - \c [out] Pointer to structure to get information 1132 * 1133 * \return 0 on success\n 1134 * <0 - Negative POSIX Error code 1135 */ 1136 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1137 unsigned ip_instance, 1138 struct drm_amdgpu_info_hw_ip *info); 1139 1140 /** 1141 * Query heap information 1142 * 1143 * This query allows UMD to query potentially available memory resources and 1144 * adjust their logic if necessary. 1145 * 1146 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1147 * \param heap - \c [in] Heap type 1148 * \param info - \c [in] Pointer to structure to get needed information 1149 * 1150 * \return 0 on success\n 1151 * <0 - Negative POSIX Error code 1152 * 1153 */ 1154 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1155 uint32_t flags, struct amdgpu_heap_info *info); 1156 1157 /** 1158 * Get the CRTC ID from the mode object ID 1159 * 1160 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1161 * \param id - \c [in] Mode object ID 1162 * \param result - \c [in] Pointer to the CRTC ID 1163 * 1164 * \return 0 on success\n 1165 * <0 - Negative POSIX Error code 1166 * 1167 */ 1168 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1169 int32_t *result); 1170 1171 /** 1172 * Query GPU H/w Info 1173 * 1174 * Query hardware specific information 1175 * 1176 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1177 * \param heap - \c [in] Heap type 1178 * \param info - \c [in] Pointer to structure to get needed information 1179 * 1180 * \return 0 on success\n 1181 * <0 - Negative POSIX Error code 1182 * 1183 */ 1184 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1185 struct amdgpu_gpu_info *info); 1186 1187 /** 1188 * Query hardware or driver information. 1189 * 1190 * The return size is query-specific and depends on the "info_id" parameter. 1191 * No more than "size" bytes is returned. 1192 * 1193 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1194 * \param info_id - \c [in] AMDGPU_INFO_* 1195 * \param size - \c [in] Size of the returned value. 1196 * \param value - \c [out] Pointer to the return value. 1197 * 1198 * \return 0 on success\n 1199 * <0 - Negative POSIX error code 1200 * 1201 */ 1202 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1203 unsigned size, void *value); 1204 1205 /** 1206 * Query hardware or driver information. 1207 * 1208 * The return size is query-specific and depends on the "info_id" parameter. 1209 * No more than "size" bytes is returned. 1210 * 1211 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1212 * \param info - \c [in] amdgpu_sw_info_* 1213 * \param value - \c [out] Pointer to the return value. 1214 * 1215 * \return 0 on success\n 1216 * <0 - Negative POSIX error code 1217 * 1218 */ 1219 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1220 void *value); 1221 1222 /** 1223 * Query information about GDS 1224 * 1225 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1226 * \param gds_info - \c [out] Pointer to structure to get GDS information 1227 * 1228 * \return 0 on success\n 1229 * <0 - Negative POSIX Error code 1230 * 1231 */ 1232 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1233 struct amdgpu_gds_resource_info *gds_info); 1234 1235 /** 1236 * Query information about sensor. 1237 * 1238 * The return size is query-specific and depends on the "sensor_type" 1239 * parameter. No more than "size" bytes is returned. 1240 * 1241 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1242 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1243 * \param size - \c [in] Size of the returned value. 1244 * \param value - \c [out] Pointer to the return value. 1245 * 1246 * \return 0 on success\n 1247 * <0 - Negative POSIX Error code 1248 * 1249 */ 1250 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1251 unsigned size, void *value); 1252 1253 /** 1254 * Query information about video capabilities 1255 * 1256 * The return sizeof(struct drm_amdgpu_info_video_caps) 1257 * 1258 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1259 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) 1260 * \param size - \c [in] Size of the returned value. 1261 * \param value - \c [out] Pointer to the return value. 1262 * 1263 * \return 0 on success\n 1264 * <0 - Negative POSIX Error code 1265 * 1266 */ 1267 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 1268 unsigned size, void *value); 1269 1270 /** 1271 * Read a set of consecutive memory-mapped registers. 1272 * Not all registers are allowed to be read by userspace. 1273 * 1274 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1275 * \param dword_offset - \c [in] Register offset in dwords 1276 * \param count - \c [in] The number of registers to read starting 1277 * from the offset 1278 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1279 * uses. Set it to 0xffffffff if unsure. 1280 * \param flags - \c [in] Flags with additional information. 1281 * \param values - \c [out] The pointer to return values. 1282 * 1283 * \return 0 on success\n 1284 * <0 - Negative POSIX error code 1285 * 1286 */ 1287 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1288 unsigned count, uint32_t instance, uint32_t flags, 1289 uint32_t *values); 1290 1291 /** 1292 * Flag to request VA address range in the 32bit address space 1293 */ 1294 #define AMDGPU_VA_RANGE_32_BIT 0x1 1295 #define AMDGPU_VA_RANGE_HIGH 0x2 1296 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4 1297 1298 /** 1299 * Allocate virtual address range 1300 * 1301 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1302 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1303 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1304 * It is client responsibility to correctly aligned size based on the future 1305 * usage of allocated range. 1306 * \param va_base_alignment - \c [in] Overwrite base address alignment 1307 * requirement for GPU VM MC virtual 1308 * address assignment. Must be multiple of size alignments received as 1309 * 'amdgpu_buffer_size_alignments'. 1310 * If 0 use the default one. 1311 * \param va_base_required - \c [in] Specified required va base address. 1312 * If 0 then library choose available one. 1313 * If !0 value will be passed and those value already "in use" then 1314 * corresponding error status will be returned. 1315 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1316 * by client. 1317 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1318 * \param flags - \c [in] flags for special VA range 1319 * 1320 * \return 0 on success\n 1321 * >0 - AMD specific error code\n 1322 * <0 - Negative POSIX Error code 1323 * 1324 * \notes \n 1325 * It is client responsibility to correctly handle VA assignments and usage. 1326 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1327 * detect wrong va assignment. 1328 * 1329 * It is client responsibility to correctly handle multi-GPU cases and to pass 1330 * the corresponding arrays of all devices handles where corresponding VA will 1331 * be used. 1332 * 1333 */ 1334 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1335 enum amdgpu_gpu_va_range va_range_type, 1336 uint64_t size, 1337 uint64_t va_base_alignment, 1338 uint64_t va_base_required, 1339 uint64_t *va_base_allocated, 1340 amdgpu_va_handle *va_range_handle, 1341 uint64_t flags); 1342 1343 /** 1344 * Free previously allocated virtual address range 1345 * 1346 * 1347 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1348 * 1349 * \return 0 on success\n 1350 * >0 - AMD specific error code\n 1351 * <0 - Negative POSIX Error code 1352 * 1353 */ 1354 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1355 1356 /** 1357 * Query virtual address range 1358 * 1359 * UMD can query GPU VM range supported by each device 1360 * to initialize its own VAM accordingly. 1361 * 1362 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1363 * \param type - \c [in] Type of virtual address range 1364 * \param offset - \c [out] Start offset of virtual address range 1365 * \param size - \c [out] Size of virtual address range 1366 * 1367 * \return 0 on success\n 1368 * <0 - Negative POSIX Error code 1369 * 1370 */ 1371 1372 int amdgpu_va_range_query(amdgpu_device_handle dev, 1373 enum amdgpu_gpu_va_range type, 1374 uint64_t *start, 1375 uint64_t *end); 1376 1377 /** 1378 * VA mapping/unmapping for the buffer object 1379 * 1380 * \param bo - \c [in] BO handle 1381 * \param offset - \c [in] Start offset to map 1382 * \param size - \c [in] Size to map 1383 * \param addr - \c [in] Start virtual address. 1384 * \param flags - \c [in] Supported flags for mapping/unmapping 1385 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1386 * 1387 * \return 0 on success\n 1388 * <0 - Negative POSIX Error code 1389 * 1390 */ 1391 1392 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1393 uint64_t offset, 1394 uint64_t size, 1395 uint64_t addr, 1396 uint64_t flags, 1397 uint32_t ops); 1398 1399 /** 1400 * VA mapping/unmapping for a buffer object or PRT region. 1401 * 1402 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1403 * parameters are treated "raw", i.e. size is not automatically aligned, and 1404 * all flags must be specified explicitly. 1405 * 1406 * \param dev - \c [in] device handle 1407 * \param bo - \c [in] BO handle (may be NULL) 1408 * \param offset - \c [in] Start offset to map 1409 * \param size - \c [in] Size to map 1410 * \param addr - \c [in] Start virtual address. 1411 * \param flags - \c [in] Supported flags for mapping/unmapping 1412 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1413 * 1414 * \return 0 on success\n 1415 * <0 - Negative POSIX Error code 1416 * 1417 */ 1418 1419 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1420 amdgpu_bo_handle bo, 1421 uint64_t offset, 1422 uint64_t size, 1423 uint64_t addr, 1424 uint64_t flags, 1425 uint32_t ops); 1426 1427 /** 1428 * create semaphore 1429 * 1430 * \param sem - \c [out] semaphore handle 1431 * 1432 * \return 0 on success\n 1433 * <0 - Negative POSIX Error code 1434 * 1435 */ 1436 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1437 1438 /** 1439 * signal semaphore 1440 * 1441 * \param context - \c [in] GPU Context 1442 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1443 * \param ip_instance - \c [in] Index of the IP block of the same type 1444 * \param ring - \c [in] Specify ring index of the IP 1445 * \param sem - \c [in] semaphore handle 1446 * 1447 * \return 0 on success\n 1448 * <0 - Negative POSIX Error code 1449 * 1450 */ 1451 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1452 uint32_t ip_type, 1453 uint32_t ip_instance, 1454 uint32_t ring, 1455 amdgpu_semaphore_handle sem); 1456 1457 /** 1458 * wait semaphore 1459 * 1460 * \param context - \c [in] GPU Context 1461 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1462 * \param ip_instance - \c [in] Index of the IP block of the same type 1463 * \param ring - \c [in] Specify ring index of the IP 1464 * \param sem - \c [in] semaphore handle 1465 * 1466 * \return 0 on success\n 1467 * <0 - Negative POSIX Error code 1468 * 1469 */ 1470 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1471 uint32_t ip_type, 1472 uint32_t ip_instance, 1473 uint32_t ring, 1474 amdgpu_semaphore_handle sem); 1475 1476 /** 1477 * destroy semaphore 1478 * 1479 * \param sem - \c [in] semaphore handle 1480 * 1481 * \return 0 on success\n 1482 * <0 - Negative POSIX Error code 1483 * 1484 */ 1485 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1486 1487 /** 1488 * Get the ASIC marketing name 1489 * 1490 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1491 * 1492 * \return the constant string of the marketing name 1493 * "NULL" means the ASIC is not found 1494 */ 1495 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1496 1497 /** 1498 * Create kernel sync object 1499 * 1500 * \param dev - \c [in] device handle 1501 * \param flags - \c [in] flags that affect creation 1502 * \param syncobj - \c [out] sync object handle 1503 * 1504 * \return 0 on success\n 1505 * <0 - Negative POSIX Error code 1506 * 1507 */ 1508 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1509 uint32_t flags, 1510 uint32_t *syncobj); 1511 1512 /** 1513 * Create kernel sync object 1514 * 1515 * \param dev - \c [in] device handle 1516 * \param syncobj - \c [out] sync object handle 1517 * 1518 * \return 0 on success\n 1519 * <0 - Negative POSIX Error code 1520 * 1521 */ 1522 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1523 uint32_t *syncobj); 1524 /** 1525 * Destroy kernel sync object 1526 * 1527 * \param dev - \c [in] device handle 1528 * \param syncobj - \c [in] sync object handle 1529 * 1530 * \return 0 on success\n 1531 * <0 - Negative POSIX Error code 1532 * 1533 */ 1534 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1535 uint32_t syncobj); 1536 1537 /** 1538 * Reset kernel sync objects to unsignalled state. 1539 * 1540 * \param dev - \c [in] device handle 1541 * \param syncobjs - \c [in] array of sync object handles 1542 * \param syncobj_count - \c [in] number of handles in syncobjs 1543 * 1544 * \return 0 on success\n 1545 * <0 - Negative POSIX Error code 1546 * 1547 */ 1548 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1549 const uint32_t *syncobjs, uint32_t syncobj_count); 1550 1551 /** 1552 * Signal kernel sync objects. 1553 * 1554 * \param dev - \c [in] device handle 1555 * \param syncobjs - \c [in] array of sync object handles 1556 * \param syncobj_count - \c [in] number of handles in syncobjs 1557 * 1558 * \return 0 on success\n 1559 * <0 - Negative POSIX Error code 1560 * 1561 */ 1562 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1563 const uint32_t *syncobjs, uint32_t syncobj_count); 1564 1565 /** 1566 * Signal kernel timeline sync objects. 1567 * 1568 * \param dev - \c [in] device handle 1569 * \param syncobjs - \c [in] array of sync object handles 1570 * \param points - \c [in] array of timeline points 1571 * \param syncobj_count - \c [in] number of handles in syncobjs 1572 * 1573 * \return 0 on success\n 1574 * <0 - Negative POSIX Error code 1575 * 1576 */ 1577 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev, 1578 const uint32_t *syncobjs, 1579 uint64_t *points, 1580 uint32_t syncobj_count); 1581 1582 /** 1583 * Wait for one or all sync objects to signal. 1584 * 1585 * \param dev - \c [in] self-explanatory 1586 * \param handles - \c [in] array of sync object handles 1587 * \param num_handles - \c [in] self-explanatory 1588 * \param timeout_nsec - \c [in] self-explanatory 1589 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1590 * \param first_signaled - \c [in] self-explanatory 1591 * 1592 * \return 0 on success\n 1593 * -ETIME - Timeout 1594 * <0 - Negative POSIX Error code 1595 * 1596 */ 1597 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1598 uint32_t *handles, unsigned num_handles, 1599 int64_t timeout_nsec, unsigned flags, 1600 uint32_t *first_signaled); 1601 1602 /** 1603 * Wait for one or all sync objects on their points to signal. 1604 * 1605 * \param dev - \c [in] self-explanatory 1606 * \param handles - \c [in] array of sync object handles 1607 * \param points - \c [in] array of sync points to wait 1608 * \param num_handles - \c [in] self-explanatory 1609 * \param timeout_nsec - \c [in] self-explanatory 1610 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1611 * \param first_signaled - \c [in] self-explanatory 1612 * 1613 * \return 0 on success\n 1614 * -ETIME - Timeout 1615 * <0 - Negative POSIX Error code 1616 * 1617 */ 1618 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev, 1619 uint32_t *handles, uint64_t *points, 1620 unsigned num_handles, 1621 int64_t timeout_nsec, unsigned flags, 1622 uint32_t *first_signaled); 1623 /** 1624 * Query sync objects payloads. 1625 * 1626 * \param dev - \c [in] self-explanatory 1627 * \param handles - \c [in] array of sync object handles 1628 * \param points - \c [out] array of sync points returned, which presents 1629 * syncobj payload. 1630 * \param num_handles - \c [in] self-explanatory 1631 * 1632 * \return 0 on success\n 1633 * -ETIME - Timeout 1634 * <0 - Negative POSIX Error code 1635 * 1636 */ 1637 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev, 1638 uint32_t *handles, uint64_t *points, 1639 unsigned num_handles); 1640 /** 1641 * Query sync objects last signaled or submitted point. 1642 * 1643 * \param dev - \c [in] self-explanatory 1644 * \param handles - \c [in] array of sync object handles 1645 * \param points - \c [out] array of sync points returned, which presents 1646 * syncobj payload. 1647 * \param num_handles - \c [in] self-explanatory 1648 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_* 1649 * 1650 * \return 0 on success\n 1651 * -ETIME - Timeout 1652 * <0 - Negative POSIX Error code 1653 * 1654 */ 1655 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev, 1656 uint32_t *handles, uint64_t *points, 1657 unsigned num_handles, uint32_t flags); 1658 1659 /** 1660 * Export kernel sync object to shareable fd. 1661 * 1662 * \param dev - \c [in] device handle 1663 * \param syncobj - \c [in] sync object handle 1664 * \param shared_fd - \c [out] shared file descriptor. 1665 * 1666 * \return 0 on success\n 1667 * <0 - Negative POSIX Error code 1668 * 1669 */ 1670 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1671 uint32_t syncobj, 1672 int *shared_fd); 1673 /** 1674 * Import kernel sync object from shareable fd. 1675 * 1676 * \param dev - \c [in] device handle 1677 * \param shared_fd - \c [in] shared file descriptor. 1678 * \param syncobj - \c [out] sync object handle 1679 * 1680 * \return 0 on success\n 1681 * <0 - Negative POSIX Error code 1682 * 1683 */ 1684 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1685 int shared_fd, 1686 uint32_t *syncobj); 1687 1688 /** 1689 * Export kernel sync object to a sync_file. 1690 * 1691 * \param dev - \c [in] device handle 1692 * \param syncobj - \c [in] sync object handle 1693 * \param sync_file_fd - \c [out] sync_file file descriptor. 1694 * 1695 * \return 0 on success\n 1696 * <0 - Negative POSIX Error code 1697 * 1698 */ 1699 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1700 uint32_t syncobj, 1701 int *sync_file_fd); 1702 1703 /** 1704 * Import kernel sync object from a sync_file. 1705 * 1706 * \param dev - \c [in] device handle 1707 * \param syncobj - \c [in] sync object handle 1708 * \param sync_file_fd - \c [in] sync_file file descriptor. 1709 * 1710 * \return 0 on success\n 1711 * <0 - Negative POSIX Error code 1712 * 1713 */ 1714 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1715 uint32_t syncobj, 1716 int sync_file_fd); 1717 /** 1718 * Export kernel timeline sync object to a sync_file. 1719 * 1720 * \param dev - \c [in] device handle 1721 * \param syncobj - \c [in] sync object handle 1722 * \param point - \c [in] timeline point 1723 * \param flags - \c [in] flags 1724 * \param sync_file_fd - \c [out] sync_file file descriptor. 1725 * 1726 * \return 0 on success\n 1727 * <0 - Negative POSIX Error code 1728 * 1729 */ 1730 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev, 1731 uint32_t syncobj, 1732 uint64_t point, 1733 uint32_t flags, 1734 int *sync_file_fd); 1735 1736 /** 1737 * Import kernel timeline sync object from a sync_file. 1738 * 1739 * \param dev - \c [in] device handle 1740 * \param syncobj - \c [in] sync object handle 1741 * \param point - \c [in] timeline point 1742 * \param sync_file_fd - \c [in] sync_file file descriptor. 1743 * 1744 * \return 0 on success\n 1745 * <0 - Negative POSIX Error code 1746 * 1747 */ 1748 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev, 1749 uint32_t syncobj, 1750 uint64_t point, 1751 int sync_file_fd); 1752 1753 /** 1754 * transfer between syncbojs. 1755 * 1756 * \param dev - \c [in] device handle 1757 * \param dst_handle - \c [in] sync object handle 1758 * \param dst_point - \c [in] timeline point, 0 presents dst is binary 1759 * \param src_handle - \c [in] sync object handle 1760 * \param src_point - \c [in] timeline point, 0 presents src is binary 1761 * \param flags - \c [in] flags 1762 * 1763 * \return 0 on success\n 1764 * <0 - Negative POSIX Error code 1765 * 1766 */ 1767 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev, 1768 uint32_t dst_handle, 1769 uint64_t dst_point, 1770 uint32_t src_handle, 1771 uint64_t src_point, 1772 uint32_t flags); 1773 1774 /** 1775 * Export an amdgpu fence as a handle (syncobj or fd). 1776 * 1777 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1778 * \param out_handle returned handle 1779 * 1780 * \return 0 on success\n 1781 * <0 - Negative POSIX Error code 1782 */ 1783 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1784 struct amdgpu_cs_fence *fence, 1785 uint32_t what, 1786 uint32_t *out_handle); 1787 1788 /** 1789 * Submit raw command submission to kernel 1790 * 1791 * \param dev - \c [in] device handle 1792 * \param context - \c [in] context handle for context id 1793 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1794 * \param num_chunks - \c [in] number of CS chunks to submit 1795 * \param chunks - \c [in] array of CS chunks 1796 * \param seq_no - \c [out] output sequence number for submission. 1797 * 1798 * \return 0 on success\n 1799 * <0 - Negative POSIX Error code 1800 * 1801 */ 1802 struct drm_amdgpu_cs_chunk; 1803 struct drm_amdgpu_cs_chunk_dep; 1804 struct drm_amdgpu_cs_chunk_data; 1805 1806 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1807 amdgpu_context_handle context, 1808 amdgpu_bo_list_handle bo_list_handle, 1809 int num_chunks, 1810 struct drm_amdgpu_cs_chunk *chunks, 1811 uint64_t *seq_no); 1812 1813 /** 1814 * Submit raw command submission to the kernel with a raw BO list handle. 1815 * 1816 * \param dev - \c [in] device handle 1817 * \param context - \c [in] context handle for context id 1818 * \param bo_list_handle - \c [in] raw bo list handle (0 for none) 1819 * \param num_chunks - \c [in] number of CS chunks to submit 1820 * \param chunks - \c [in] array of CS chunks 1821 * \param seq_no - \c [out] output sequence number for submission. 1822 * 1823 * \return 0 on success\n 1824 * <0 - Negative POSIX Error code 1825 * 1826 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() 1827 */ 1828 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, 1829 amdgpu_context_handle context, 1830 uint32_t bo_list_handle, 1831 int num_chunks, 1832 struct drm_amdgpu_cs_chunk *chunks, 1833 uint64_t *seq_no); 1834 1835 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 1836 struct drm_amdgpu_cs_chunk_dep *dep); 1837 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 1838 struct drm_amdgpu_cs_chunk_data *data); 1839 1840 /** 1841 * Reserve VMID 1842 * \param context - \c [in] GPU Context 1843 * \param flags - \c [in] TBD 1844 * 1845 * \return 0 on success otherwise POSIX Error code 1846 */ 1847 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1848 1849 /** 1850 * Free reserved VMID 1851 * \param context - \c [in] GPU Context 1852 * \param flags - \c [in] TBD 1853 * 1854 * \return 0 on success otherwise POSIX Error code 1855 */ 1856 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1857 1858 #ifdef __cplusplus 1859 } 1860 #endif 1861 #endif /* #ifdef _AMDGPU_H_ */ 1862