1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Parent TargetRegisterInfo class common to all hw codegen targets.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AMDGPURegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "SIMachineFunctionInfo.h"
17 #include "SIRegisterInfo.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19
20 using namespace llvm;
21
AMDGPURegisterInfo()22 AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
23
24 //===----------------------------------------------------------------------===//
25 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
26 // they are not supported at this time.
27 //===----------------------------------------------------------------------===//
28
29 // Table of NumRegs sized pieces at every 32-bit offset.
30 static const uint16_t SubRegFromChannelTable[][32] = {
31 { AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
32 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
33 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
34 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
35 AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
36 AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23,
37 AMDGPU::sub24, AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27,
38 AMDGPU::sub28, AMDGPU::sub29, AMDGPU::sub30, AMDGPU::sub31
39 },
40 {
41 AMDGPU::sub0_sub1, AMDGPU::sub1_sub2, AMDGPU::sub2_sub3, AMDGPU::sub3_sub4,
42 AMDGPU::sub4_sub5, AMDGPU::sub5_sub6, AMDGPU::sub6_sub7, AMDGPU::sub7_sub8,
43 AMDGPU::sub8_sub9, AMDGPU::sub9_sub10, AMDGPU::sub10_sub11, AMDGPU::sub11_sub12,
44 AMDGPU::sub12_sub13, AMDGPU::sub13_sub14, AMDGPU::sub14_sub15, AMDGPU::sub15_sub16,
45 AMDGPU::sub16_sub17, AMDGPU::sub17_sub18, AMDGPU::sub18_sub19, AMDGPU::sub19_sub20,
46 AMDGPU::sub20_sub21, AMDGPU::sub21_sub22, AMDGPU::sub22_sub23, AMDGPU::sub23_sub24,
47 AMDGPU::sub24_sub25, AMDGPU::sub25_sub26, AMDGPU::sub26_sub27, AMDGPU::sub27_sub28,
48 AMDGPU::sub28_sub29, AMDGPU::sub29_sub30, AMDGPU::sub30_sub31, AMDGPU::NoSubRegister
49 },
50 {
51 AMDGPU::sub0_sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub3_sub4_sub5,
52 AMDGPU::sub4_sub5_sub6, AMDGPU::sub5_sub6_sub7, AMDGPU::sub6_sub7_sub8, AMDGPU::sub7_sub8_sub9,
53 AMDGPU::sub8_sub9_sub10, AMDGPU::sub9_sub10_sub11, AMDGPU::sub10_sub11_sub12, AMDGPU::sub11_sub12_sub13,
54 AMDGPU::sub12_sub13_sub14, AMDGPU::sub13_sub14_sub15, AMDGPU::sub14_sub15_sub16, AMDGPU::sub15_sub16_sub17,
55 AMDGPU::sub16_sub17_sub18, AMDGPU::sub17_sub18_sub19, AMDGPU::sub18_sub19_sub20, AMDGPU::sub19_sub20_sub21,
56 AMDGPU::sub20_sub21_sub22, AMDGPU::sub21_sub22_sub23, AMDGPU::sub22_sub23_sub24, AMDGPU::sub23_sub24_sub25,
57 AMDGPU::sub24_sub25_sub26, AMDGPU::sub25_sub26_sub27, AMDGPU::sub26_sub27_sub28, AMDGPU::sub27_sub28_sub29,
58 AMDGPU::sub28_sub29_sub30, AMDGPU::sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
59 },
60 {
61 AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6,
62 AMDGPU::sub4_sub5_sub6_sub7, AMDGPU::sub5_sub6_sub7_sub8, AMDGPU::sub6_sub7_sub8_sub9, AMDGPU::sub7_sub8_sub9_sub10,
63 AMDGPU::sub8_sub9_sub10_sub11, AMDGPU::sub9_sub10_sub11_sub12, AMDGPU::sub10_sub11_sub12_sub13, AMDGPU::sub11_sub12_sub13_sub14,
64 AMDGPU::sub12_sub13_sub14_sub15, AMDGPU::sub13_sub14_sub15_sub16, AMDGPU::sub14_sub15_sub16_sub17, AMDGPU::sub15_sub16_sub17_sub18,
65 AMDGPU::sub16_sub17_sub18_sub19, AMDGPU::sub17_sub18_sub19_sub20, AMDGPU::sub18_sub19_sub20_sub21, AMDGPU::sub19_sub20_sub21_sub22,
66 AMDGPU::sub20_sub21_sub22_sub23, AMDGPU::sub21_sub22_sub23_sub24, AMDGPU::sub22_sub23_sub24_sub25, AMDGPU::sub23_sub24_sub25_sub26,
67 AMDGPU::sub24_sub25_sub26_sub27, AMDGPU::sub25_sub26_sub27_sub28, AMDGPU::sub26_sub27_sub28_sub29, AMDGPU::sub27_sub28_sub29_sub30,
68 AMDGPU::sub28_sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
69 }
70 };
71
72 // FIXME: TableGen should generate something to make this manageable for all
73 // register classes. At a minimum we could use the opposite of
74 // composeSubRegIndices and go up from the base 32-bit subreg.
getSubRegFromChannel(unsigned Channel,unsigned NumRegs)75 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel, unsigned NumRegs) {
76 const unsigned NumRegIndex = NumRegs - 1;
77
78 assert(NumRegIndex < array_lengthof(SubRegFromChannelTable) &&
79 "Not implemented");
80 assert(Channel < array_lengthof(SubRegFromChannelTable[0]));
81 return SubRegFromChannelTable[NumRegIndex][Channel];
82 }
83
reserveRegisterTuples(BitVector & Reserved,unsigned Reg) const84 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
85 MCRegAliasIterator R(Reg, this, true);
86
87 for (; R.isValid(); ++R)
88 Reserved.set(*R);
89 }
90
91 #define GET_REGINFO_TARGET_DESC
92 #include "AMDGPUGenRegisterInfo.inc"
93
94 // Forced to be here by one .inc
getCalleeSavedRegs(const MachineFunction * MF) const95 const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
96 const MachineFunction *MF) const {
97 CallingConv::ID CC = MF->getFunction().getCallingConv();
98 switch (CC) {
99 case CallingConv::C:
100 case CallingConv::Fast:
101 case CallingConv::Cold:
102 return CSR_AMDGPU_HighRegs_SaveList;
103 default: {
104 // Dummy to not crash RegisterClassInfo.
105 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
106 return &NoCalleeSavedReg;
107 }
108 }
109 }
110
111 const MCPhysReg *
getCalleeSavedRegsViaCopy(const MachineFunction * MF) const112 SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
113 return nullptr;
114 }
115
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const116 const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
117 CallingConv::ID CC) const {
118 switch (CC) {
119 case CallingConv::C:
120 case CallingConv::Fast:
121 case CallingConv::Cold:
122 return CSR_AMDGPU_HighRegs_RegMask;
123 default:
124 return nullptr;
125 }
126 }
127
getFrameRegister(const MachineFunction & MF) const128 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
129 const SIFrameLowering *TFI =
130 MF.getSubtarget<GCNSubtarget>().getFrameLowering();
131 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
132 return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
133 : FuncInfo->getStackPtrOffsetReg();
134 }
135
getAllVGPRRegMask() const136 const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const {
137 return CSR_AMDGPU_AllVGPRs_RegMask;
138 }
139
getAllAllocatableSRegMask() const140 const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const {
141 return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
142 }
143