| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_combine_constants.cpp | 109 struct imm { struct
114 * The instruction generating the immediate value, if all uses are contained argument
120 * A list of fs_regs that refer to this immediate. If we promote it, we'll argument
125 /** The immediate value */ argument
146 /** The number of coissuable instructions using this immediate. */ argument
161 struct imm *imm; argument
275 build_imm_reg_for_copy(struct imm *imm) in build_imm_reg_for_copy()
290 get_alignment_for_imm(const struct imm *imm) in get_alignment_for_imm()
299 needs_negate(const fs_reg *reg, const struct imm *imm) in needs_negate()
395 struct imm *imm = find_imm(&table, data, size); in opt_combine_constants() local
[all …]
|
| D | brw_reg.h | 646 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF); in brw_imm_df() local
654 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); in brw_imm_u64() local
662 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); in brw_imm_f() local
671 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_Q); in brw_imm_q() local
680 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); in brw_imm_uq() local
689 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); in brw_imm_d() local
698 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); in brw_imm_ud() local
707 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); in brw_imm_uw() local
716 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); in brw_imm_w() local
729 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); in brw_imm_v() local
[all …]
|
| /external/XNNPACK/src/jit/ |
| D | aarch64-assembler.cc | 52 inline uint32_t imm9(int32_t imm) { in imm9()
209 inline bool imm7_offset_valid(int32_t imm, XRegister) { in imm7_offset_valid()
213 inline bool imm7_offset_valid(int32_t imm, DRegister) { in imm7_offset_valid()
217 inline bool imm7_offset_valid(int32_t imm, QRegister) { in imm7_offset_valid()
272 void Assembler::ldp(XRegister xt1, XRegister xt2, MemOperand xn, int32_t imm) { in ldp()
281 const int32_t imm = xn.offset; in ldr() local
290 void Assembler::ldr(XRegister xt, MemOperand xn, int32_t imm) { in ldr()
370 void Assembler::tst(XRegister xn, uint8_t imm) { in tst()
460 void Assembler::ld1(VRegisterList vs, MemOperand xn, int32_t imm) { in ld1()
516 void Assembler::ldp(DRegister dt1, DRegister dt2, MemOperand xn, int32_t imm) { in ldp()
[all …]
|
| D | aarch32-assembler.cc | 88 void Assembler::add(CoreRegister rd, CoreRegister rn, uint8_t imm) { in add()
93 void Assembler::adds(CoreRegister rd, CoreRegister rn, uint8_t imm) { in adds()
98 void Assembler::and_(CoreRegister rd, CoreRegister rn, uint8_t imm) { in and_()
152 void Assembler::bic(CoreRegister rd, CoreRegister rn, uint8_t imm) { in bic()
160 void Assembler::cmp(CoreRegister rn, uint8_t imm) { in cmp()
239 void Assembler::sub(CoreRegister rd, CoreRegister rn, uint8_t imm) { in sub()
247 void Assembler::subs(CoreRegister rd, CoreRegister rn, uint8_t imm) { in subs()
252 void Assembler::tst(CoreRegister rn, uint8_t imm) { in tst()
465 void Assembler::vmov(QRegister qd, uint8_t imm) { in vmov()
|
| /external/clang/lib/Headers/ |
| D | f16cintrin.h | 75 #define _cvtss_sh(a, imm) \ argument
102 #define _mm_cvtps_ph(a, imm) \ argument
|
| D | avx512dqintrin.h | 1153 #define _mm512_extractf32x8_ps(A, imm) __extension__ ({ \ argument
1158 #define _mm512_mask_extractf32x8_ps(W, U, A, imm) __extension__ ({ \ argument
1163 #define _mm512_maskz_extractf32x8_ps(U, A, imm) __extension__ ({ \ argument
1168 #define _mm512_extractf64x2_pd(A, imm) __extension__ ({ \ argument
1174 #define _mm512_mask_extractf64x2_pd(W, U, A, imm) __extension__ ({ \ argument
1180 #define _mm512_maskz_extractf64x2_pd(U, A, imm) __extension__ ({ \ argument
1186 #define _mm512_extracti32x8_epi32(A, imm) __extension__ ({ \ argument
1191 #define _mm512_mask_extracti32x8_epi32(W, U, A, imm) __extension__ ({ \ argument
1196 #define _mm512_maskz_extracti32x8_epi32(U, A, imm) __extension__ ({ \ argument
1201 #define _mm512_extracti64x2_epi64(A, imm) __extension__ ({ \ argument
[all …]
|
| D | avx512vldqintrin.h | 1153 #define _mm256_extractf64x2_pd(A, imm) __extension__ ({ \ argument
1159 #define _mm256_mask_extractf64x2_pd(W, U, A, imm) __extension__ ({ \ argument
1165 #define _mm256_maskz_extractf64x2_pd(U, A, imm) __extension__ ({ \ argument
1171 #define _mm256_extracti64x2_epi64(A, imm) __extension__ ({ \ argument
1177 #define _mm256_mask_extracti64x2_epi64(W, U, A, imm) __extension__ ({ \ argument
1183 #define _mm256_maskz_extracti64x2_epi64(U, A, imm) __extension__ ({ \ argument
1189 #define _mm256_insertf64x2(A, B, imm) __extension__ ({ \ argument
1196 #define _mm256_mask_insertf64x2(W, U, A, B, imm) __extension__ ({ \ argument
1203 #define _mm256_maskz_insertf64x2(U, A, B, imm) __extension__ ({ \ argument
1210 #define _mm256_inserti64x2(A, B, imm) __extension__ ({ \ argument
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | Sparc.h | 150 inline static unsigned HI22(int64_t imm) { in HI22()
154 inline static unsigned LO10(int64_t imm) { in LO10()
158 inline static unsigned HIX22(int64_t imm) { in HIX22()
162 inline static unsigned LOX10(int64_t imm) { in LOX10()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | Sparc.h | 149 inline static unsigned HI22(int64_t imm) { in HI22()
153 inline static unsigned LO10(int64_t imm) { in LO10()
157 inline static unsigned HIX22(int64_t imm) { in HIX22()
161 inline static unsigned LOX10(int64_t imm) { in LOX10()
|
| /external/vixl/src/aarch32/ |
| D | disasm-aarch32.cc | 1324 void Disassembler::bkpt(Condition cond, uint32_t imm) { in bkpt()
1530 void Disassembler::hlt(Condition cond, uint32_t imm) { in hlt()
1536 void Disassembler::hvc(Condition cond, uint32_t imm) { in hvc()
2900 uint32_t imm, in ssat()
2909 uint32_t imm, in ssat16()
3216 void Disassembler::svc(Condition cond, uint32_t imm) { in svc()
3368 void Disassembler::udf(Condition cond, EncodingSize size, uint32_t imm) { in udf()
3597 uint32_t imm, in usat()
3606 uint32_t imm, in usat16()
7050 uint32_t imm = (instr >> 22) & 0x7; in DecodeT32() local
[all …]
|
| D | instructions-aarch32.cc | 605 ImmediateT32::ImmediateT32(uint32_t imm) { in ImmediateT32()
645 bool ImmediateT32::IsImmediateT32(uint32_t imm) { in IsImmediateT32()
679 ImmediateA32::ImmediateA32(uint32_t imm) { in ImmediateA32()
695 bool ImmediateA32::IsImmediateA32(uint32_t imm) { in IsImmediateA32()
|
| D | macro-assembler-aarch32.cc | 225 uint32_t imm) { in HandleOutOfBoundsImmediate()
736 uint32_t imm = operand.GetImmediate(); in Delegate() local
890 int32_t imm = operand.GetSignedImmediate(); in Delegate() local
940 int32_t imm = operand.GetSignedImmediate(); in Delegate() local
979 uint32_t imm, in GenerateSplitInstruction()
1052 int32_t imm = operand.GetSignedImmediate(); in Delegate() local
1249 static inline bool IsI64BitPattern(T imm) { in IsI64BitPattern()
1258 static inline bool IsI8BitPattern(T imm) { in IsI8BitPattern()
1301 static inline RES replicate(T imm) { in replicate()
1356 uint32_t imm = neon_imm.GetImmediate<uint32_t>(); in Delegate() local
[all …]
|
| /external/pcre/src/sljit/ |
| D | sljitNativePPC_32.c | 29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate()
48 sljit_u32 imm; in emit_single_op() local
|
| D | sljitNativeARM_T2_32.c | 66 #define IMM3(imm) ((sljit_ins)imm << 6) argument
67 #define IMM8(imm) ((sljit_ins)imm) argument
85 #define IMM5(imm) \ argument
87 #define IMM12(imm) \ argument
237 …JIT_INLINE sljit_s32 emit_imm32_const(struct sljit_compiler *compiler, sljit_s32 dst, sljit_uw imm) in emit_imm32_const()
515 static sljit_uw get_imm(sljit_uw imm) in get_imm()
564 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 dst, sljit_uw imm) in load_immediate()
602 sljit_uw imm, imm2; in emit_op_imm() local
940 #define ALIGN_CHECK(argw, imm, shift) (!((argw) & ~((imm) << (shift)))) argument
1015 sljit_uw imm; in emit_set_delta() local
[all …]
|
| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 1174 unsigned imm = fieldFromInstruction_4(Val, 7, 5); in DecodeSORegImmOperand() local
1381 unsigned imm = fieldFromInstruction_4(Insn, 0, 8); in DecodeCopMemInstruction() local
1528 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); in DecodeAddrMode2IdxInstruction() local
1635 unsigned imm = fieldFromInstruction_4(Val, 7, 5); in DecodeSORegMemOperand() local
1679 unsigned imm = fieldFromInstruction_4(Insn, 8, 4); in DecodeAddrMode3Instruction() local
2088 int imm = fieldFromInstruction_4(Insn, 0, 8); in DecodeT2CPSInstruction() local
2104 unsigned imm = 0; in DecodeT2MOVTWInstruction() local
2129 unsigned imm = 0; in DecodeArmMOVTWInstruction() local
2184 unsigned imm = fieldFromInstruction_4(Val, 0, 12); in DecodeAddrModeImm12Operand() local
2206 unsigned imm = fieldFromInstruction_4(Val, 0, 8); in DecodeAddrMode5Operand() local
[all …]
|
| /external/capstone/arch/TMS320C64x/ |
| D | TMS320C64xDisassembler.c | 161 int32_t imm; in DecodeScst5() local
176 int32_t imm; in DecodeScst16() local
191 int32_t imm; in DecodePCRelScst7() local
207 int32_t imm; in DecodePCRelScst10() local
223 int32_t imm; in DecodePCRelScst12() local
239 int32_t imm; in DecodePCRelScst21() local
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 35 IntegerOperand imm) { in AddSubHelper()
72 IntegerOperand imm) { in TrySingleAddSub()
96 IntegerOperand imm, in IntWideImmHelper()
131 IntegerOperand imm) { in Mul()
140 IntegerOperand imm) { in Smin()
150 IntegerOperand imm) { in Smax()
160 IntegerOperand imm) { in Umax()
170 IntegerOperand imm) { in Umin()
365 IntegerOperand imm) { in Cpy()
429 double imm) { in Fcpy()
[all …]
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1142 unsigned imm = fieldFromInstruction(Val, 7, 5); in DecodeSORegImmOperand() local
1328 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeCopMemInstruction() local
1478 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeAddrMode2IdxInstruction() local
1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); in DecodeAddrMode2IdxInstruction() local
1583 unsigned imm = fieldFromInstruction(Val, 7, 5); in DecodeSORegMemOperand() local
1628 unsigned imm = fieldFromInstruction(Insn, 8, 4); in DecodeAddrMode3Instruction() local
2056 int imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2CPSInstruction() local
2071 unsigned imm = 0; in DecodeT2MOVTWInstruction() local
2096 unsigned imm = 0; in DecodeArmMOVTWInstruction() local
2199 unsigned imm = fieldFromInstruction(Val, 0, 12); in DecodeAddrModeImm12Operand() local
[all …]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerX8664.cpp | 261 void AssemblerX8664::mov(Type Ty, GPRRegister dst, const Immediate &imm) { in mov()
317 void AssemblerX8664::mov(Type Ty, const AsmAddress &dst, const Immediate &imm) { in mov()
1046 void AssemblerX8664::psll(Type Ty, XmmRegister dst, const Immediate &imm) { in psll()
1090 void AssemblerX8664::psra(Type Ty, XmmRegister dst, const Immediate &imm) { in psra()
1138 void AssemblerX8664::psrl(Type Ty, XmmRegister dst, const Immediate &imm) { in psrl()
1506 const Immediate &imm) { in set1ps()
1537 const Immediate &imm) { in pshufd()
1549 const AsmAddress &src, const Immediate &imm) { in pshufd()
1692 const Immediate &imm) { in shufps()
1703 const AsmAddress &src, const Immediate &imm) { in shufps()
[all …]
|
| D | IceAssemblerX8632.cpp | 279 void AssemblerX8632::mov(Type Ty, GPRRegister dst, const Immediate &imm) { in mov()
331 void AssemblerX8632::mov(Type Ty, const AsmAddress &dst, const Immediate &imm) { in mov()
980 void AssemblerX8632::psll(Type Ty, XmmRegister dst, const Immediate &imm) { in psll()
1021 void AssemblerX8632::psra(Type Ty, XmmRegister dst, const Immediate &imm) { in psra()
1066 void AssemblerX8632::psrl(Type Ty, XmmRegister dst, const Immediate &imm) { in psrl()
1396 const Immediate &imm) { in set1ps()
1425 const Immediate &imm) { in pshufd()
1436 const AsmAddress &src, const Immediate &imm) { in pshufd()
1570 const Immediate &imm) { in shufps()
1580 const AsmAddress &src, const Immediate &imm) { in shufps()
[all …]
|
| /external/mesa3d/src/gallium/auxiliary/rtasm/ |
| D | rtasm_x86sse.c | 455 void x86_mov_reg_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_mov_reg_imm()
464 void x86_mov_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_mov_imm()
477 void x86_mov16_imm( struct x86_function *p, struct x86_reg dst, uint16_t imm ) in x86_mov16_imm()
494 void x86_mov8_imm( struct x86_function *p, struct x86_reg dst, uint8_t imm ) in x86_mov8_imm()
515 unsigned op, struct x86_reg dst, int imm ) in x86_group1_imm()
531 void x86_add_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_add_imm()
537 void x86_or_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_or_imm()
543 void x86_and_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_and_imm()
549 void x86_sub_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_sub_imm()
555 void x86_xor_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_xor_imm()
[all …]
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_emit_gk110.cpp | 208 const ImmediateValue *imm = ref.get()->asImm(); in isLIMM() local
363 ImmediateValue imm(i->getSrc(s)->asImm(), i->sType); in setImmediate32() local
428 const bool imm = i->srcExists(1) && i->src(1).getFile() == FILE_IMMEDIATE; in emitForm_21() local
786 const ImmediateValue *imm = i->src(1).get()->asImm(); in emitSHLADD() local
1459 ImmediateValue *imm = i->getSrc(0)->asImm(); in emitBAR() local
1469 ImmediateValue *imm = i->getSrc(0)->asImm(); in emitBAR() local
1577 const ImmediateValue *imm; in emitSHFL() local
1628 const ImmediateValue *imm; in emitVOTE() local
1847 ImmediateValue *imm = NULL; in emitSUCalc() local
1931 ImmediateValue *imm = i->getSrc(1)->asImm(); in emitVSHL() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VE.h | 100 inline static int64_t HI32(int64_t imm) { in HI32()
104 inline static int64_t LO32(int64_t imm) { in LO32()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1455 unsigned imm = fieldFromInstruction(Val, 7, 5); in DecodeSORegImmOperand() local
1651 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeCopMemInstruction() local
1830 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeAddrMode2IdxInstruction() local
1913 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); in DecodeAddrMode2IdxInstruction() local
1935 unsigned imm = fieldFromInstruction(Val, 7, 5); in DecodeSORegMemOperand() local
1980 unsigned imm = fieldFromInstruction(Insn, 8, 4); in DecodeAddrMode3Instruction() local
2408 int imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2CPSInstruction() local
2423 unsigned imm = 0; in DecodeT2MOVTWInstruction() local
2448 unsigned imm = 0; in DecodeArmMOVTWInstruction() local
2551 unsigned imm = fieldFromInstruction(Val, 0, 12); in DecodeAddrModeImm12Operand() local
[all …]
|
| /external/mesa3d/src/amd/compiler/ |
| D | aco_insert_waitcnt.cpp | 153 uint16_t imm = 0; in pack() local
198 wait_imm imm; member
441 wait_imm imm; in parse_wait_instr() local
452 wait_imm imm; in perform_barrier() local
478 void force_waitcnt(wait_ctx& ctx, wait_imm& imm) in force_waitcnt()
495 wait_imm imm; in kill() local
705 wait_imm imm; in insert_wait_entry() local
852 void emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wait_imm imm) in emit_waitcnt()
|