1 /*
2 * Copyright (c) 2021-2022 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24 #include "src/common/cpuinfo/CpuIsaInfo.h"
25
26 #include "arm_compute/core/Error.h"
27 #include "src/common/cpuinfo/CpuModel.h"
28
29 /* Arm Feature flags */
30 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_HALF (1 << 1)
31 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_NEON (1 << 12)
32
33 /* Arm64 Feature flags */
34 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD (1 << 1)
35 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP (1 << 9)
36 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP (1 << 10)
37 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP (1 << 20)
38 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE (1 << 22)
39 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2 (1 << 1)
40 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM (1 << 9)
41 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM (1 << 10)
42 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16 (1 << 12)
43 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM (1 << 13)
44 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16 (1 << 14)
45 #define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME (1 << 23)
46
47 namespace arm_compute
48 {
49 namespace cpuinfo
50 {
51 namespace
52 {
is_feature_supported(uint64_t features,uint64_t feature_mask)53 inline bool is_feature_supported(uint64_t features, uint64_t feature_mask)
54 {
55 return (features & feature_mask);
56 }
57
58 #if defined(__arm__)
decode_hwcaps(CpuIsaInfo & isa,const uint32_t hwcaps,const uint32_t hwcaps2)59 void decode_hwcaps(CpuIsaInfo &isa, const uint32_t hwcaps, const uint32_t hwcaps2)
60 {
61 ARM_COMPUTE_UNUSED(hwcaps2);
62 isa.fp16 = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_HALF);
63 isa.neon = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_NEON);
64 }
65 #elif defined(__aarch64__)
decode_hwcaps(CpuIsaInfo & isa,const uint32_t hwcaps,const uint32_t hwcaps2)66 void decode_hwcaps(CpuIsaInfo &isa, const uint32_t hwcaps, const uint32_t hwcaps2)
67 {
68 // High-level SIMD support
69 isa.neon = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD);
70 isa.sve = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE);
71 isa.sve2 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2);
72
73 // Detection of SME from type HWCAP2 in the auxillary vector
74 isa.sme = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME);
75 isa.sme2 = isa.sme; // Needs to be set properly
76
77 // Data-type support
78 isa.fp16 = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP | ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP);
79 isa.bf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16);
80 isa.svebf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16);
81
82 // Instruction extensions
83 isa.dot = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP);
84 isa.i8mm = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM);
85 isa.svei8mm = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM);
86 isa.svef32mm = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM);
87 }
88 #else /* defined(__aarch64__) */
decode_hwcaps(CpuIsaInfo & isa,const uint32_t hwcaps,const uint32_t hwcaps2)89 void decode_hwcaps(CpuIsaInfo &isa, const uint32_t hwcaps, const uint32_t hwcaps2)
90 {
91 ARM_COMPUTE_UNUSED(isa, hwcaps, hwcaps2);
92 }
93 #endif /* defined(__aarch64__) */
94
decode_regs(CpuIsaInfo & isa,const uint64_t isar0,const uint64_t isar1,const uint64_t pfr0,const uint64_t pfr1,const uint64_t svefr0)95 void decode_regs(CpuIsaInfo &isa, const uint64_t isar0, const uint64_t isar1, const uint64_t pfr0, const uint64_t pfr1, const uint64_t svefr0)
96 {
97 auto is_supported = [](uint64_t feature_reg, uint8_t feature_pos) -> bool
98 {
99 return ((feature_reg >> feature_pos) & 0xf);
100 };
101
102 // High-level SIMD support
103 isa.sve = is_supported(pfr0, 32);
104 isa.sve2 = is_supported(svefr0, 0);
105 isa.sme = is_supported(pfr1, 24);
106 isa.sme2 = (((pfr1 >> 24) & 0xf) > 1);
107
108 // Data-type support
109 isa.fp16 = is_supported(pfr0, 16);
110 isa.bf16 = is_supported(isar1, 44);
111 isa.svebf16 = is_supported(svefr0, 20);
112
113 // Instruction extensions
114 isa.dot = is_supported(isar0, 44);
115 isa.i8mm = is_supported(isar1, 48);
116 isa.svei8mm = is_supported(svefr0, 44);
117 isa.svef32mm = is_supported(svefr0, 52);
118 }
119
120 /** Handle features from allow-listed models in case of problematic kernels
121 *
122 * @param[in, out] isa ISA to update
123 * @param[in] model CPU model type
124 */
allowlisted_model_features(CpuIsaInfo & isa,CpuModel model)125 void allowlisted_model_features(CpuIsaInfo &isa, CpuModel model)
126 {
127 if(isa.dot == false)
128 {
129 isa.dot = model_supports_dot(model);
130 }
131 if(isa.fp16 == false)
132 {
133 isa.fp16 = model_supports_fp16(model);
134 }
135 }
136 } // namespace
137
init_cpu_isa_from_hwcaps(uint32_t hwcaps,uint32_t hwcaps2,uint32_t midr)138 CpuIsaInfo init_cpu_isa_from_hwcaps(uint32_t hwcaps, uint32_t hwcaps2, uint32_t midr)
139 {
140 CpuIsaInfo isa;
141
142 decode_hwcaps(isa, hwcaps, hwcaps2);
143
144 const CpuModel model = midr_to_model(midr);
145 allowlisted_model_features(isa, model);
146
147 return isa;
148 }
149
init_cpu_isa_from_regs(uint64_t isar0,uint64_t isar1,uint64_t pfr0,uint64_t pfr1,uint64_t svefr0,uint64_t midr)150 CpuIsaInfo init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr)
151 {
152 CpuIsaInfo isa;
153
154 decode_regs(isa, isar0, isar1, pfr0, pfr1, svefr0);
155
156 const CpuModel model = midr_to_model(midr);
157 allowlisted_model_features(isa, model);
158
159 return isa;
160 }
161 } // namespace cpuinfo
162 } // namespace arm_compute
163