1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <ddr.h> 12 #ifndef NXP_COINED_BB 13 #include <flash_info.h> 14 #include <fspi.h> 15 #include <fspi_api.h> 16 #endif 17 #include <lib/mmio.h> 18 #include <lib/psci/psci.h> 19 #ifdef NXP_COINED_BB 20 #include <snvs.h> 21 #endif 22 23 #include <plat_nv_storage.h> 24 #include "plat_warm_rst.h" 25 #include "platform_def.h" 26 27 #if defined(IMAGE_BL2) 28 is_warm_boot(void)29uint32_t is_warm_boot(void) 30 { 31 uint32_t ret = mmio_read_32(NXP_RESET_ADDR + RST_RSTRQSR1_OFFSET) 32 & ~(RSTRQSR1_SWRR); 33 34 const nv_app_data_t *nv_app_data = get_nv_data(); 35 36 if (ret == 0U) { 37 INFO("Not a SW(Warm) triggered reset.\n"); 38 return 0U; 39 } 40 41 ret = (nv_app_data->warm_rst_flag == WARM_BOOT_SUCCESS) ? 1 : 0; 42 43 if (ret != 0U) { 44 INFO("Warm Reset was triggered..\n"); 45 } else { 46 INFO("Warm Reset was not triggered..\n"); 47 } 48 49 return ret; 50 } 51 52 #endif 53 54 #if defined(IMAGE_BL31) prep_n_execute_warm_reset(void)55int prep_n_execute_warm_reset(void) 56 { 57 #ifdef NXP_COINED_BB 58 #if !TRUSTED_BOARD_BOOT 59 snvs_disable_zeroize_lp_gpr(); 60 #endif 61 #else 62 int ret; 63 uint8_t warm_reset = WARM_BOOT_SUCCESS; 64 65 ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR); 66 67 if (ret != 0) { 68 ERROR("Failed to initialized driver flexspi-nor.\n"); 69 ERROR("exiting warm-reset request.\n"); 70 return PSCI_E_INTERN_FAIL; 71 } 72 73 /* Sector starting from NV_STORAGE_BASE_ADDR is already 74 * erased for writing. 75 */ 76 77 #if (ERLY_WRM_RST_FLG_FLSH_UPDT) 78 ret = xspi_write((uint32_t)NV_STORAGE_BASE_ADDR, 79 &warm_reset, 80 sizeof(warm_reset)); 81 #else 82 /* Preparation for writing the Warm reset flag. */ 83 ret = xspi_wren((uint32_t)NV_STORAGE_BASE_ADDR); 84 85 /* IP Control Register0 - SF Address to be read */ 86 fspi_out32((NXP_FLEXSPI_ADDR + FSPI_IPCR0), 87 (uint32_t) NV_STORAGE_BASE_ADDR); 88 89 while ((fspi_in32(NXP_FLEXSPI_ADDR + FSPI_INTR) & 90 FSPI_INTR_IPTXWE_MASK) == 0) { 91 ; 92 } 93 /* Write TX FIFO Data Register */ 94 fspi_out32(NXP_FLEXSPI_ADDR + FSPI_TFDR, (uint32_t) warm_reset); 95 96 fspi_out32(NXP_FLEXSPI_ADDR + FSPI_INTR, FSPI_INTR_IPTXWE); 97 98 /* IP Control Register1 - SEQID_WRITE operation, Size = 1 Byte */ 99 fspi_out32(NXP_FLEXSPI_ADDR + FSPI_IPCR1, 100 (uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 101 (uint16_t) sizeof(warm_reset)); 102 103 /* Trigger XSPI-IP-Write cmd only if: 104 * - Putting DDR in-self refresh mode is successfully. 105 * to complete the writing of the warm-reset flag 106 * to flash. 107 * 108 * This code is as part of assembly. 109 */ 110 #endif 111 #endif 112 INFO("Doing DDR Self refresh.\n"); 113 _soc_sys_warm_reset(); 114 115 /* Expected behaviour is to do the power cycle */ 116 while (1 != 0) 117 ; 118 119 return -1; 120 } 121 #endif 122