1 /******************************************************************************
2 * *
3 * Copyright (C) 2018 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 #include "ixheaacd_type_def.h"
21 #include "ixheaacd_constants.h"
22 #include "ixheaacd_error_standards.h"
23
24 #include "ixheaacd_bitbuffer.h"
25 #include "ixheaacd_config.h"
26
27 #include <assert.h>
28
29 #ifndef sign
30 #define sign(a) (((a) > 0) ? 1 : ((a) < 0) ? -1 : 0)
31 #endif
32
33 typedef struct {
34 WORD32 num_input_chan;
35 WORD32 num_output_chan;
36 WORD32 num_ott_boxes;
37 WORD32 num_ttt_boxes;
38 WORD32 ott_mode_lfe[MAX_NUM_OTT];
39 } ia_ld_mps_dec_tree_properties_struct;
40
41 static WORD32 ixheaacd_freq_res_table[] = {0, 23, 15, 12, 9, 7, 5, 4};
42
43 static WORD32 ixheaacd_hrtf_freq_res_table[][8] = {{0, 28, 20, 14, 10, 7, 5, 4},
44 {0, 13, 13, 8, 7, 4, 3, 3}};
45
46 static ia_ld_mps_dec_tree_properties_struct ixheaacd_tree_property_table[] = {
47 {1, 6, 5, 0, {0, 0, 0, 0, 1}}, {1, 6, 5, 0, {0, 0, 1, 0, 0}}, {2, 6, 3, 1, {1, 0, 0, 0, 0}},
48 {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {6, 8, 2, 0, {0, 0, 0, 0, 0}},
49 {6, 8, 2, 0, {0, 0, 0, 0, 0}}, {1, 2, 1, 0, {0, 0, 0, 0, 0}}};
50
ixheaacd_ld_spatial_extension_config(ia_bit_buf_struct * it_bit_buff,ia_usac_dec_mps_config_struct * config,WORD32 bits_available)51 static IA_ERRORCODE ixheaacd_ld_spatial_extension_config(
52 ia_bit_buf_struct *it_bit_buff, ia_usac_dec_mps_config_struct *config,
53 WORD32 bits_available) {
54 WORD32 j, ch, idx, tmp, tmp_open, sac_ext_len, bits_read, n_fill_bits;
55 UWORD32 i;
56 WORD32 ba = bits_available;
57
58 config->sac_ext_cnt = 0;
59
60 tmp = it_bit_buff->cnt_bits;
61
62 while (ba >= 8) {
63 if (config->sac_ext_cnt >= MAX_NUM_EXT_TYPES) return IA_FATAL_ERROR;
64
65 config->bs_sac_ext_type[config->sac_ext_cnt] =
66 ixheaacd_read_bits_buf(it_bit_buff, 4);
67 ba -= 4;
68
69 sac_ext_len = ixheaacd_read_bits_buf(it_bit_buff, 4);
70 ba -= 4;
71
72 if ((ba >= 6) && (sac_ext_len > 0)) {
73 if (sac_ext_len == 15) {
74 sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 8);
75 ba -= 8;
76 if (sac_ext_len == 15 + 255) {
77 sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 16);
78 ba -= 16;
79 }
80 }
81
82 switch (config->bs_sac_ext_type[config->sac_ext_cnt]) {
83 case 0:
84 config->bs_residual_coding = 1;
85
86 config->bs_residual_sampling_freq_index =
87 ixheaacd_read_bits_buf(it_bit_buff, 4);
88 config->bs_residual_frames_per_spatial_frame =
89 ixheaacd_read_bits_buf(it_bit_buff, 2);
90
91 if ((config->num_ott_boxes + config->num_ttt_boxes) >
92 MAX_RESIDUAL_CHANNELS)
93 return IA_FATAL_ERROR;
94 for (j = 0; j < config->num_ott_boxes + config->num_ttt_boxes; j++) {
95 config->bs_residual_present[j] =
96 ixheaacd_read_bits_buf(it_bit_buff, 1);
97 if (config->bs_residual_present[j]) {
98 config->bs_residual_bands_ld_mps[j] =
99 ixheaacd_read_bits_buf(it_bit_buff, 5);
100 }
101 }
102 break;
103
104 case 1:
105 config->bs_arbitrary_downmix = 2;
106
107 config->bs_arbitrary_downmix_residual_sampling_freq_index =
108 ixheaacd_read_bits_buf(it_bit_buff, 4);
109 config->bs_arbitrary_downmix_residual_frames_per_spatial_frame =
110 ixheaacd_read_bits_buf(it_bit_buff, 2);
111 config->bs_arbitrary_downmix_residual_bands =
112 ixheaacd_read_bits_buf(it_bit_buff, 5);
113
114 break;
115
116 case 2:
117 config->num_out_chan_AT = 0;
118 config->num_ott_boxes_AT = 0;
119 if (config->num_output_channels > MAX_OUTPUT_CHANNELS)
120 return IA_FATAL_ERROR;
121 for (ch = 0; ch < config->num_output_channels; ch++) {
122 tmp_open = 1;
123 idx = 0;
124 while ((tmp_open > 0) && (idx < MAX_ARBITRARY_TREE_INDEX)) {
125 config->bs_ott_box_present_AT[ch][idx] =
126 ixheaacd_read_bits_buf(it_bit_buff, 1);
127 if (config->bs_ott_box_present_AT[ch][idx]) {
128 config->num_ott_boxes_AT++;
129 tmp_open++;
130 } else {
131 config->num_out_chan_AT++;
132 tmp_open--;
133 }
134 idx++;
135 }
136 }
137
138 for (i = 0; i < config->num_ott_boxes_AT; i++) {
139 config->bs_ott_default_cld_AT[i] =
140 ixheaacd_read_bits_buf(it_bit_buff, 1);
141 config->bs_ott_mode_lfe_AT[i] =
142 ixheaacd_read_bits_buf(it_bit_buff, 1);
143 if (config->bs_ott_mode_lfe_AT[i]) {
144 config->bs_ott_bands_AT[i] =
145 ixheaacd_read_bits_buf(it_bit_buff, 5);
146 } else {
147 config->bs_ott_bands_AT[i] = ixheaacd_freq_res_table[config->bs_freq_res];
148 }
149 }
150
151 for (i = 0; i < config->num_out_chan_AT; i++) {
152 config->bs_output_channel_pos_AT[i] =
153 ixheaacd_read_bits_buf(it_bit_buff, 5);
154 }
155
156 break;
157
158 default:;
159 }
160 }
161
162 bits_read = tmp - it_bit_buff->cnt_bits;
163 n_fill_bits = 8 * sac_ext_len - bits_read;
164
165 while (n_fill_bits > 7) {
166 ixheaacd_read_bits_buf(it_bit_buff, 8);
167 n_fill_bits -= 8;
168 }
169 if (n_fill_bits > 0) {
170 ixheaacd_read_bits_buf(it_bit_buff, n_fill_bits);
171 }
172
173 ba -= 8 * sac_ext_len;
174 config->sac_ext_cnt++;
175 }
176 return IA_NO_ERROR;
177 }
178
ixheaacd_ld_spatial_specific_config(ia_usac_dec_mps_config_struct * config,ia_bit_buf_struct * it_bit_buff)179 IA_ERRORCODE ixheaacd_ld_spatial_specific_config(
180 ia_usac_dec_mps_config_struct *config, ia_bit_buf_struct *it_bit_buff) {
181 WORD32 i, num_header_bits;
182 UWORD32 hc, hb;
183 WORD32 sac_header_len;
184 WORD32 bits_available;
185 WORD32 tmp = it_bit_buff->cnt_bits;
186 WORD32 err = 0;
187
188 sac_header_len = tmp;
189
190 bits_available = sac_header_len;
191 config->bs_sampling_freq_index = ixheaacd_read_bits_buf(it_bit_buff, 4);
192 if (config->bs_sampling_freq_index == 15) {
193 config->bs_fampling_frequency = ixheaacd_read_bits_buf(it_bit_buff, 24);
194 }
195
196 config->bs_frame_length = ixheaacd_read_bits_buf(it_bit_buff, 5);
197 config->bs_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
198 config->bs_tree_config = ixheaacd_read_bits_buf(it_bit_buff, 4);
199
200 if (config->bs_tree_config > 7) return IA_FATAL_ERROR;
201
202 if (config->bs_tree_config != 15) {
203 config->num_ott_boxes =
204 ixheaacd_tree_property_table[config->bs_tree_config].num_ott_boxes;
205 config->num_ttt_boxes =
206 ixheaacd_tree_property_table[config->bs_tree_config].num_ttt_boxes;
207 config->num_input_channels =
208 ixheaacd_tree_property_table[config->bs_tree_config].num_input_chan;
209 config->num_output_channels =
210 ixheaacd_tree_property_table[config->bs_tree_config].num_output_chan;
211 for (i = 0; i < MAX_NUM_OTT; i++) {
212 config->ott_mode_lfe[i] =
213 ixheaacd_tree_property_table[config->bs_tree_config].ott_mode_lfe[i];
214 }
215 }
216 config->bs_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 2);
217 if (config->bs_tree_config != 7) {
218 config->bs_one_icc = ixheaacd_read_bits_buf(it_bit_buff, 1);
219 }
220 config->bs_arbitrary_downmix = ixheaacd_read_bits_buf(it_bit_buff, 1);
221 if (config->bs_tree_config != 7) {
222 config->bs_fixed_gain_sur = ixheaacd_read_bits_buf(it_bit_buff, 3);
223 config->bs_fixed_gain_LFE = ixheaacd_read_bits_buf(it_bit_buff, 3);
224 }
225 config->bs_fixed_gain_dmx = ixheaacd_read_bits_buf(it_bit_buff, 3);
226 if (config->bs_tree_config != 7) {
227 config->bs_matrix_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
228 }
229 config->bs_temp_shape_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
230 config->bs_decorr_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
231 if (config->bs_tree_config != 7) {
232 config->bs_3D_audio_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
233 } else {
234 config->bs_3D_audio_mode = 0;
235 }
236
237 // ott_config
238 for (i = 0; i < config->num_ott_boxes; i++) {
239 if (config->ott_mode_lfe[i]) {
240 config->bs_ott_bands[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
241 } else {
242 config->bs_ott_bands[i] = ixheaacd_freq_res_table[config->bs_freq_res];
243 }
244 }
245
246 // ttt_config
247 for (i = 0; i < config->num_ttt_boxes; i++) {
248 config->bs_ttt_dual_mode[i] = ixheaacd_read_bits_buf(it_bit_buff, 1);
249 config->bs_ttt_mode_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
250 if (config->bs_ttt_dual_mode[i]) {
251 config->bs_ttt_mode_high[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
252 config->bs_ttt_bands_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
253 config->bs_ttt_bands_high[i] = ixheaacd_freq_res_table[config->bs_freq_res];
254 } else {
255 config->bs_ttt_bands_low[i] = ixheaacd_freq_res_table[config->bs_freq_res];
256 }
257 }
258
259 if (config->bs_temp_shape_config == 2) {
260 config->bs_env_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
261 }
262
263 if (config->bs_3D_audio_mode) {
264 config->bs_3D_audio_HRTF_set = ixheaacd_read_bits_buf(it_bit_buff, 2);
265 // param_HRTF_set
266 if (config->bs_3D_audio_HRTF_set == 0) {
267 config->bs_HRTF_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
268 config->bs_HRTF_num_chan = 5;
269 config->bs_HRTF_asymmetric = ixheaacd_read_bits_buf(it_bit_buff, 1);
270
271 config->HRTF_num_band = ixheaacd_hrtf_freq_res_table[0][config->bs_HRTF_freq_res];
272 config->HRTF_num_phase = ixheaacd_hrtf_freq_res_table[1][config->bs_HRTF_freq_res];
273
274 for (hc = 0; hc < config->bs_HRTF_num_chan; hc++) {
275 for (hb = 0; hb < config->HRTF_num_band; hb++) {
276 config->bs_HRTF_level_left[hc][hb] =
277 ixheaacd_read_bits_buf(it_bit_buff, 6);
278 }
279 for (hb = 0; hb < config->HRTF_num_band; hb++) {
280 config->bs_HRTF_level_right[hc][hb] =
281 config->bs_HRTF_asymmetric
282 ? ixheaacd_read_bits_buf(it_bit_buff, 6)
283 : config->bs_HRTF_level_left[hc][hb];
284 }
285 config->bs_HRTF_phase[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
286 for (hb = 0; hb < config->HRTF_num_phase; hb++) {
287 config->bs_HRTF_phase_LR[hc][hb] =
288 config->bs_HRTF_phase[hc] ? ixheaacd_read_bits_buf(it_bit_buff, 6)
289 : 0;
290 }
291 config->bs_HRTF_icc[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
292 if (config->bs_HRTF_icc[hc]) {
293 for (hb = 0; hb < config->HRTF_num_band; hb++)
294 config->bs_HRTF_icc_LR[hc][hb] =
295 ixheaacd_read_bits_buf(it_bit_buff, 3);
296 }
297 }
298 }
299 }
300
301 // byte_align
302 i = (it_bit_buff->cnt_bits & 0x7);
303 ixheaacd_read_bits_buf(it_bit_buff, i);
304
305 num_header_bits = tmp - (it_bit_buff->cnt_bits);
306 bits_available -= num_header_bits;
307
308 err =
309 ixheaacd_ld_spatial_extension_config(it_bit_buff, config, bits_available);
310 return err;
311 }
312