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Searched defs:lane (Results 1 – 25 of 59) sorted by relevance

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/external/vixl/test/aarch64/
Dtest-utils-aarch64.h164 inline T zreg_lane(unsigned code, int lane) const { in zreg_lane()
173 int lane) const { in zreg_lane()
190 int lane) const { in preg_lane()
214 inline bool HasSVELane(T reg, int lane) const { in HasSVELane()
220 inline uint64_t GetSVELane(T reg, int lane) const { in GetSVELane()
414 for (int lane = 0; lane < N; ++lane) { in EqualSVE() local
442 for (int lane = 0; lane < core->GetSVELaneCount(reg.GetLaneSizeInBits()); in EqualSVE() local
467 for (int lane = 0; lane < core->GetSVELaneCount(lane_size); ++lane) { in EqualSVE() local
Dtest-simulator-aarch64.cc1565 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1588 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1608 for (unsigned lane = 0; lane < std::max(vd_lane_count, vn_lane_count); in Test1OpNEON() local
1772 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpAcrossNEON() local
1795 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpAcrossNEON() local
1806 for (unsigned lane = vd_lane_count; lane < vd_lanes_per_q; lane++) { in Test1OpAcrossNEON() local
1832 for (unsigned lane = 0; lane < vn_lane_count; lane++) { in Test1OpAcrossNEON() local
2033 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
2057 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
2079 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
[all …]
Dtest-assembler-aarch64.h323 #define ASSERT_EQUAL_SVE_LANE(expected, result, lane) \ argument
/external/vixl/src/aarch64/
Dsimulator-aarch64.h295 void Insert(int lane, T new_value) { in Insert()
309 T GetLane(int lane) const { in GetLane()
349 void ReadLane(T* dst, int lane) const { in ReadLane()
356 void WriteLane(T src, int lane) { in WriteLane()
366 void ReadLane(vixl::internal::SimFloat16* dst, int lane) const { in ReadLane()
372 void WriteLane(vixl::internal::SimFloat16 src, int lane) { in WriteLane()
437 ChunkType GetChunk(int lane) const { return GetActiveMask<ChunkType>(lane); } in GetChunk()
439 void SetChunk(int lane, ChunkType new_value) { in SetChunk()
446 for (int lane = 0; in SetAllBits() local
454 T GetActiveMask(int lane) const { in GetActiveMask()
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/external/deqp-deps/amber/src/vulkan/
Dengine_vulkan_debugger.cc421 const Variables* GetLane(const Variables& lanes, int lane) { in GetLane()
538 int lane, in Thread()
731 if (auto lane = client_.GetLane(locals, lane_)) { in ExpectLocalT() local
958 int lane, in StartThread()
991 int lane; in OnBreakpointHit() local
1003 int lane; in OnBreakpointHit() local
1014 int lane; in OnBreakpointHit() local
1055 int* lane) { in FindLocal()
1100 int* lane) { in FindGlobalInvocationId()
1108 bool FindVertexIndex(dap::integer thread_id, uint32_t index, int* lane) { in FindVertexIndex()
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/external/libvpx/vp9/common/arm/neon/
Dvp9_highbd_iht16x16_add_neon.c23 #define vmull_lane_s32_dual(in, c, lane, out) \ argument
31 #define vmlal_lane_s32_dual(in, c, lane, out) \ argument
43 #define vmlsl_lane_s32_dual(in, c, lane, out) \ argument
65 #define highbd_iadst_half_butterfly(in, c, lane, out) \ argument
/external/python/cpython3/Modules/_sha3/kcp/
DKeccakP-1600-opt64.c98 UINT64 lane; in KeccakP1600_AddBytesInLane() local
182 UINT64 lane = byte; in KeccakP1600_AddByte() local
306 UINT64 lane = ((UINT64*)state)[lanePosition]; in KeccakP1600_ExtractBytesInLane() local
382 UINT64 lane = ((UINT64*)state)[lanePosition]; in KeccakP1600_ExtractAndAddBytesInLane() local
/external/arm-optimized-routines/math/
Dv_pow.c17 for (int lane = 0; lane < v_lanes64 (); lane++) in V_NAME() local
Dv_powf.c162 for (int lane = 0; lane < v_lanes32 (); lane++) in V_NAME() local
/external/tensorflow/tensorflow/lite/kernels/internal/optimized/
Ddepthwiseconv_3x3_filter_common.h131 int8x16_t rhs, const int lane) { in vdotq_four_lane_s32()
155 int8x16_t rhs, int lane) { in vdotq_four_lane_s32()
Dneon_check.h31 #define vld1q_lane_u64(ptr, vec, lane) _MM_INSERT_EPI64(vec, *(ptr), lane) argument
/external/rust/crates/libz-sys/src/zlib-ng/arch/arm/
Dcompare256_neon.c19 uint64_t lane; in compare256_neon_static() local
/external/flac/src/libFLAC/
Dlpc_intrin_neon.c69 #define MUL_32_BIT_LOOP_UNROOL_3(qlp_coeff_vec, lane) \ argument
75 #define MACC_32BIT_LOOP_UNROOL_3(tmp_vec_ind, qlp_coeff_vec, lane) \ argument
641 #define MUL_64_BIT_LOOP_UNROOL_3(qlp_coeff_vec, lane) \ argument
650 #define MACC_64_BIT_LOOP_UNROOL_3(tmp_vec_ind, qlp_coeff_vec, lane) \ argument
/external/neon_2_sse/
DNEON_2_SSE.h9339 #define vld1q_lane_u8(ptr, vec, lane) _MM_INSERT_EPI8(vec, *(ptr), lane) argument
9342 #define vld1q_lane_u16(ptr, vec, lane) _MM_INSERT_EPI16(vec, *(ptr), lane) argument
9345 #define vld1q_lane_u32(ptr, vec, lane) _MM_INSERT_EPI32(vec, *(ptr), lane) argument
9348 #define vld1q_lane_u64(ptr, vec, lane) _MM_INSERT_EPI64(vec, *(ptr), lane); // _p; argument
9352 #define vld1q_lane_s8(ptr, vec, lane) _MM_INSERT_EPI8(vec, *(ptr), lane) argument
9355 #define vld1q_lane_s16(ptr, vec, lane) _MM_INSERT_EPI16(vec, *(ptr), lane) argument
9358 #define vld1q_lane_s32(ptr, vec, lane) _MM_INSERT_EPI32(vec, *(ptr), lane) argument
9373 #define vld1q_lane_s64(ptr, vec, lane) _MM_INSERT_EPI64(vec, *(ptr), lane) argument
9376 #define vld1q_lane_p8(ptr, vec, lane) _MM_INSERT_EPI8(vec, *(ptr), lane) argument
9379 #define vld1q_lane_p16(ptr, vec, lane) _MM_INSERT_EPI16(vec, *(ptr), lane) argument
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/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dfetch_jit.cpp397 for (uint32_t lane = 0; lane < mVWidth; ++lane) in CreateGatherOddFormats() local
1121 for (int64_t lane = 0; lane < vWidth; lane++) in GetSimdValidIndicesGfx() local
1195 for (int64_t lane = 0; lane < mVWidth; lane++) in GetSimdValidIndicesHelper() local
1413 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; in Shuffle8bpcGatherd16() local
1789 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; in Shuffle16bpcGather16() local
2035 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; in Shuffle16bpcGather() local
Dbuilder_mem.cpp480 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; in Shuffle16bpcGather4() local
580 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; in Shuffle8bpcGather4() local
/external/libaom/aom_dsp/arm/
Dmem_neon.h86 #define load_u8_4x1(s, s0, lane) \ argument
200 #define store_u8_4x1(s, s0, lane) \ argument
476 #define store_unaligned_u8_4x1(dst, src, lane) \ argument
483 #define store_unaligned_u8_2x1(dst, src, lane) \ argument
/external/tensorflow/tensorflow/core/profiler/internal/
Dtfprof_timeline.cc244 for (const auto& lane : process.second) { in GenerateGraphTimeline() local
355 const auto& lane = p->lanes[i]; in AllocateLanes() local
/external/vixl/src/aarch32/
Dinstructions-aarch32.h224 SRegister GetLane(uint32_t lane) const { in GetLane()
327 DRegisterLane(DRegister reg, uint32_t lane) in DRegisterLane()
329 DRegisterLane(uint32_t code, uint32_t lane) : DRegister(code), lane_(lane) {} in DRegisterLane()
345 int* lane) { in ExtractDRegisterAndLane()
369 DRegister GetDLane(uint32_t lane) const { in GetDLane()
376 SRegister GetSLane(uint32_t lane) const { in GetSLane()
711 NeonRegisterList(DRegister reg, int lane) in NeonRegisterList()
736 int lane) in NeonRegisterList()
/external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
Dpa_avx.cpp157 INLINE simd4scalar swizzleLaneN(const simdvector& v, int lane) in swizzleLaneN()
311 INLINE simd4scalar swizzleLaneN(const simd16vector& v, int lane) in swizzleLaneN()
505 for (uint32_t lane = 0; lane < KNOB_SIMD_WIDTH; ++lane) in PaPatchListTerm() local
564 for (uint32_t lane = 0; lane < KNOB_SIMD16_WIDTH; ++lane) in PaPatchListTerm_simd16() local
1820 const int lane = pa.numPrims - pa.numPrimsComplete - 1; in PaLineLoop1() local
1872 const int lane = pa.numPrims - pa.numPrimsComplete - 1; in PaLineLoop1_simd16() local
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_gm107.cpp122 Value *lane = bld.mkImm(l); in handleManualTXD() local
/external/swiftshader/src/Pipeline/
DSpirvShaderDebugger.cpp266 for(int lane = 0; lane < sw::SIMD::Width; lane++) in get() local
1182 int const lane; member
2018 int lane) in LocalVariableValue()
2171 for(size_t lane = 0; lane < sw::SIMD::Width; lane++) in Data() local
2333 for(size_t lane = 0; lane < sw::SIMD::Width; lane++) in updateFrameLocals() local
2345 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2379 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2386 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2404 for(int lane = 0; lane < sw::SIMD::Width; lane++) in buildGlobal() local
2415 for(int lane = 0; lane < sw::SIMD::Width; lane++) in buildGlobals() local
/external/mesa3d/src/compiler/nir/
Dnir_opt_uniform_atomics.c166 emit_read_invocation(nir_builder *b, nir_ssa_def *data, nir_ssa_def *lane) in emit_read_invocation()
/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-3700.h226 #define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28) argument
246 #define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28) argument
/external/mesa3d/src/gallium/drivers/swr/
Dswr_shader.cpp791 for (uint32_t lane = 0; lane < mVWidth; ++lane) { in swr_gs_llvm_emit_vertex() local
842 for (uint32_t lane = 0; lane < mVWidth; ++lane) { in swr_gs_llvm_emit_vertex() local
910 for (uint32_t lane = 0; lane < mVWidth; ++lane) { in swr_gs_llvm_end_primitive() local
936 for (uint32_t lane = 0; lane < mVWidth; ++lane) in swr_gs_llvm_epilogue() local
1092 for (uint32_t lane = 0; lane < mVWidth; lane++) { in swr_tcs_llvm_fetch_output() local
1213 for (uint32_t lane = 0; lane < mVWidth; lane++) { in swr_tcs_llvm_store_output() local
1619 for (uint32_t lane = 0; lane < mVWidth; ++lane) in CompileGS() local

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