1 /* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 18 #define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 19 20 #include "base/enums.h" 21 #include "base/macros.h" 22 #include "class_root.h" 23 #include "code_generator.h" 24 #include "common_arm.h" 25 #include "dex/string_reference.h" 26 #include "dex/type_reference.h" 27 #include "driver/compiler_options.h" 28 #include "nodes.h" 29 #include "parallel_move_resolver.h" 30 #include "utils/arm/assembler_arm_vixl.h" 31 32 // TODO(VIXL): make vixl clean wrt -Wshadow. 33 #pragma GCC diagnostic push 34 #pragma GCC diagnostic ignored "-Wshadow" 35 #include "aarch32/constants-aarch32.h" 36 #include "aarch32/instructions-aarch32.h" 37 #include "aarch32/macro-assembler-aarch32.h" 38 #pragma GCC diagnostic pop 39 40 namespace art HIDDEN { 41 42 namespace linker { 43 class Thumb2RelativePatcherTest; 44 } // namespace linker 45 46 namespace arm { 47 48 // This constant is used as an approximate margin when emission of veneer and literal pools 49 // must be blocked. 50 static constexpr int kMaxMacroInstructionSizeInBytes = 51 15 * vixl::aarch32::kMaxInstructionSizeInBytes; 52 53 static const vixl::aarch32::Register kParameterCoreRegistersVIXL[] = { 54 vixl::aarch32::r1, 55 vixl::aarch32::r2, 56 vixl::aarch32::r3 57 }; 58 static const size_t kParameterCoreRegistersLengthVIXL = arraysize(kParameterCoreRegistersVIXL); 59 static const vixl::aarch32::SRegister kParameterFpuRegistersVIXL[] = { 60 vixl::aarch32::s0, 61 vixl::aarch32::s1, 62 vixl::aarch32::s2, 63 vixl::aarch32::s3, 64 vixl::aarch32::s4, 65 vixl::aarch32::s5, 66 vixl::aarch32::s6, 67 vixl::aarch32::s7, 68 vixl::aarch32::s8, 69 vixl::aarch32::s9, 70 vixl::aarch32::s10, 71 vixl::aarch32::s11, 72 vixl::aarch32::s12, 73 vixl::aarch32::s13, 74 vixl::aarch32::s14, 75 vixl::aarch32::s15 76 }; 77 static const size_t kParameterFpuRegistersLengthVIXL = arraysize(kParameterFpuRegistersVIXL); 78 79 static const vixl::aarch32::Register kMethodRegister = vixl::aarch32::r0; 80 81 // Callee saves core registers r5, r6, r7, r8 (except when emitting Baker 82 // read barriers, where it is used as Marking Register), r10, r11, and lr. 83 static const vixl::aarch32::RegisterList kCoreCalleeSaves = vixl::aarch32::RegisterList::Union( 84 vixl::aarch32::RegisterList(vixl::aarch32::r5, 85 vixl::aarch32::r6, 86 vixl::aarch32::r7), 87 // Do not consider r8 as a callee-save register with Baker read barriers. 88 (kReserveMarkingRegister 89 ? vixl::aarch32::RegisterList() 90 : vixl::aarch32::RegisterList(vixl::aarch32::r8)), 91 vixl::aarch32::RegisterList(vixl::aarch32::r10, 92 vixl::aarch32::r11, 93 vixl::aarch32::lr)); 94 95 // Callee saves FP registers s16 to s31 inclusive. 96 static const vixl::aarch32::SRegisterList kFpuCalleeSaves = 97 vixl::aarch32::SRegisterList(vixl::aarch32::s16, 16); 98 99 static const vixl::aarch32::Register kRuntimeParameterCoreRegistersVIXL[] = { 100 vixl::aarch32::r0, 101 vixl::aarch32::r1, 102 vixl::aarch32::r2, 103 vixl::aarch32::r3 104 }; 105 static const size_t kRuntimeParameterCoreRegistersLengthVIXL = 106 arraysize(kRuntimeParameterCoreRegistersVIXL); 107 static const vixl::aarch32::SRegister kRuntimeParameterFpuRegistersVIXL[] = { 108 vixl::aarch32::s0, 109 vixl::aarch32::s1, 110 vixl::aarch32::s2, 111 vixl::aarch32::s3 112 }; 113 static const size_t kRuntimeParameterFpuRegistersLengthVIXL = 114 arraysize(kRuntimeParameterFpuRegistersVIXL); 115 116 class LoadClassSlowPathARMVIXL; 117 class CodeGeneratorARMVIXL; 118 119 using VIXLInt32Literal = vixl::aarch32::Literal<int32_t>; 120 using VIXLUInt32Literal = vixl::aarch32::Literal<uint32_t>; 121 122 #define UNIMPLEMENTED_INTRINSIC_LIST_ARM(V) \ 123 V(MathRoundDouble) /* Could be done by changing rounding mode, maybe? */ \ 124 V(UnsafeCASLong) /* High register pressure */ \ 125 V(SystemArrayCopyChar) \ 126 V(LongDivideUnsigned) \ 127 V(CRC32Update) \ 128 V(CRC32UpdateBytes) \ 129 V(CRC32UpdateByteBuffer) \ 130 V(FP16ToFloat) \ 131 V(FP16ToHalf) \ 132 V(FP16Floor) \ 133 V(FP16Ceil) \ 134 V(FP16Rint) \ 135 V(FP16Greater) \ 136 V(FP16GreaterEquals) \ 137 V(FP16Less) \ 138 V(FP16LessEquals) \ 139 V(FP16Compare) \ 140 V(FP16Min) \ 141 V(FP16Max) \ 142 V(MathMultiplyHigh) \ 143 V(StringStringIndexOf) \ 144 V(StringStringIndexOfAfter) \ 145 V(StringBufferAppend) \ 146 V(StringBufferLength) \ 147 V(StringBufferToString) \ 148 V(StringBuilderAppendObject) \ 149 V(StringBuilderAppendString) \ 150 V(StringBuilderAppendCharSequence) \ 151 V(StringBuilderAppendCharArray) \ 152 V(StringBuilderAppendBoolean) \ 153 V(StringBuilderAppendChar) \ 154 V(StringBuilderAppendInt) \ 155 V(StringBuilderAppendLong) \ 156 V(StringBuilderAppendFloat) \ 157 V(StringBuilderAppendDouble) \ 158 V(StringBuilderLength) \ 159 V(StringBuilderToString) \ 160 V(SystemArrayCopyByte) \ 161 V(SystemArrayCopyInt) \ 162 /* 1.8 */ \ 163 V(MathFmaDouble) \ 164 V(MathFmaFloat) \ 165 V(UnsafeGetAndAddInt) \ 166 V(UnsafeGetAndAddLong) \ 167 V(UnsafeGetAndSetInt) \ 168 V(UnsafeGetAndSetLong) \ 169 V(UnsafeGetAndSetObject) \ 170 V(MethodHandleInvokeExact) \ 171 V(MethodHandleInvoke) \ 172 /* OpenJDK 11 */ \ 173 V(JdkUnsafeCASLong) /* High register pressure */ \ 174 V(JdkUnsafeGetAndAddInt) \ 175 V(JdkUnsafeGetAndAddLong) \ 176 V(JdkUnsafeGetAndSetInt) \ 177 V(JdkUnsafeGetAndSetLong) \ 178 V(JdkUnsafeGetAndSetObject) \ 179 V(JdkUnsafeCompareAndSetLong) 180 181 class JumpTableARMVIXL : public DeletableArenaObject<kArenaAllocSwitchTable> { 182 public: JumpTableARMVIXL(HPackedSwitch * switch_instr)183 explicit JumpTableARMVIXL(HPackedSwitch* switch_instr) 184 : switch_instr_(switch_instr), 185 table_start_(), 186 bb_addresses_(switch_instr->GetAllocator()->Adapter(kArenaAllocCodeGenerator)) { 187 uint32_t num_entries = switch_instr_->GetNumEntries(); 188 for (uint32_t i = 0; i < num_entries; i++) { 189 VIXLInt32Literal *lit = new VIXLInt32Literal(0, vixl32::RawLiteral::kManuallyPlaced); 190 bb_addresses_.emplace_back(lit); 191 } 192 } 193 GetTableStartLabel()194 vixl::aarch32::Label* GetTableStartLabel() { return &table_start_; } 195 196 void EmitTable(CodeGeneratorARMVIXL* codegen); 197 void FixTable(CodeGeneratorARMVIXL* codegen); 198 199 private: 200 HPackedSwitch* const switch_instr_; 201 vixl::aarch32::Label table_start_; 202 ArenaVector<std::unique_ptr<VIXLInt32Literal>> bb_addresses_; 203 204 DISALLOW_COPY_AND_ASSIGN(JumpTableARMVIXL); 205 }; 206 207 class InvokeRuntimeCallingConventionARMVIXL 208 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { 209 public: InvokeRuntimeCallingConventionARMVIXL()210 InvokeRuntimeCallingConventionARMVIXL() 211 : CallingConvention(kRuntimeParameterCoreRegistersVIXL, 212 kRuntimeParameterCoreRegistersLengthVIXL, 213 kRuntimeParameterFpuRegistersVIXL, 214 kRuntimeParameterFpuRegistersLengthVIXL, 215 kArmPointerSize) {} 216 217 private: 218 DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConventionARMVIXL); 219 }; 220 221 class InvokeDexCallingConventionARMVIXL 222 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { 223 public: InvokeDexCallingConventionARMVIXL()224 InvokeDexCallingConventionARMVIXL() 225 : CallingConvention(kParameterCoreRegistersVIXL, 226 kParameterCoreRegistersLengthVIXL, 227 kParameterFpuRegistersVIXL, 228 kParameterFpuRegistersLengthVIXL, 229 kArmPointerSize) {} 230 231 private: 232 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionARMVIXL); 233 }; 234 235 class InvokeDexCallingConventionVisitorARMVIXL : public InvokeDexCallingConventionVisitor { 236 public: InvokeDexCallingConventionVisitorARMVIXL()237 InvokeDexCallingConventionVisitorARMVIXL() {} ~InvokeDexCallingConventionVisitorARMVIXL()238 virtual ~InvokeDexCallingConventionVisitorARMVIXL() {} 239 240 Location GetNextLocation(DataType::Type type) override; 241 Location GetReturnLocation(DataType::Type type) const override; 242 Location GetMethodLocation() const override; 243 244 private: 245 InvokeDexCallingConventionARMVIXL calling_convention; 246 uint32_t double_index_ = 0; 247 248 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorARMVIXL); 249 }; 250 251 class CriticalNativeCallingConventionVisitorARMVIXL : public InvokeDexCallingConventionVisitor { 252 public: CriticalNativeCallingConventionVisitorARMVIXL(bool for_register_allocation)253 explicit CriticalNativeCallingConventionVisitorARMVIXL(bool for_register_allocation) 254 : for_register_allocation_(for_register_allocation) {} 255 ~CriticalNativeCallingConventionVisitorARMVIXL()256 virtual ~CriticalNativeCallingConventionVisitorARMVIXL() {} 257 258 Location GetNextLocation(DataType::Type type) override; 259 Location GetReturnLocation(DataType::Type type) const override; 260 Location GetMethodLocation() const override; 261 GetStackOffset()262 size_t GetStackOffset() const { return stack_offset_; } 263 264 private: 265 // Register allocator does not support adjusting frame size, so we cannot provide final locations 266 // of stack arguments for register allocation. We ask the register allocator for any location and 267 // move these arguments to the right place after adjusting the SP when generating the call. 268 const bool for_register_allocation_; 269 size_t gpr_index_ = 0u; 270 size_t stack_offset_ = 0u; 271 272 DISALLOW_COPY_AND_ASSIGN(CriticalNativeCallingConventionVisitorARMVIXL); 273 }; 274 275 class FieldAccessCallingConventionARMVIXL : public FieldAccessCallingConvention { 276 public: FieldAccessCallingConventionARMVIXL()277 FieldAccessCallingConventionARMVIXL() {} 278 GetObjectLocation()279 Location GetObjectLocation() const override { 280 return helpers::LocationFrom(vixl::aarch32::r1); 281 } GetFieldIndexLocation()282 Location GetFieldIndexLocation() const override { 283 return helpers::LocationFrom(vixl::aarch32::r0); 284 } GetReturnLocation(DataType::Type type)285 Location GetReturnLocation(DataType::Type type) const override { 286 return DataType::Is64BitType(type) 287 ? helpers::LocationFrom(vixl::aarch32::r0, vixl::aarch32::r1) 288 : helpers::LocationFrom(vixl::aarch32::r0); 289 } GetSetValueLocation(DataType::Type type,bool is_instance)290 Location GetSetValueLocation(DataType::Type type, bool is_instance) const override { 291 return DataType::Is64BitType(type) 292 ? helpers::LocationFrom(vixl::aarch32::r2, vixl::aarch32::r3) 293 : (is_instance 294 ? helpers::LocationFrom(vixl::aarch32::r2) 295 : helpers::LocationFrom(vixl::aarch32::r1)); 296 } GetFpuLocation(DataType::Type type)297 Location GetFpuLocation(DataType::Type type) const override { 298 return DataType::Is64BitType(type) 299 ? helpers::LocationFrom(vixl::aarch32::s0, vixl::aarch32::s1) 300 : helpers::LocationFrom(vixl::aarch32::s0); 301 } 302 303 private: 304 DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionARMVIXL); 305 }; 306 307 class SlowPathCodeARMVIXL : public SlowPathCode { 308 public: SlowPathCodeARMVIXL(HInstruction * instruction)309 explicit SlowPathCodeARMVIXL(HInstruction* instruction) 310 : SlowPathCode(instruction), entry_label_(), exit_label_() {} 311 GetEntryLabel()312 vixl::aarch32::Label* GetEntryLabel() { return &entry_label_; } GetExitLabel()313 vixl::aarch32::Label* GetExitLabel() { return &exit_label_; } 314 315 void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override; 316 void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override; 317 318 private: 319 vixl::aarch32::Label entry_label_; 320 vixl::aarch32::Label exit_label_; 321 322 DISALLOW_COPY_AND_ASSIGN(SlowPathCodeARMVIXL); 323 }; 324 325 class ParallelMoveResolverARMVIXL : public ParallelMoveResolverWithSwap { 326 public: ParallelMoveResolverARMVIXL(ArenaAllocator * allocator,CodeGeneratorARMVIXL * codegen)327 ParallelMoveResolverARMVIXL(ArenaAllocator* allocator, CodeGeneratorARMVIXL* codegen) 328 : ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {} 329 330 void EmitMove(size_t index) override; 331 void EmitSwap(size_t index) override; 332 void SpillScratch(int reg) override; 333 void RestoreScratch(int reg) override; 334 335 ArmVIXLAssembler* GetAssembler() const; 336 337 private: 338 void Exchange(vixl32::Register reg, int mem); 339 void Exchange(int mem1, int mem2); 340 341 CodeGeneratorARMVIXL* const codegen_; 342 343 DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverARMVIXL); 344 }; 345 346 class LocationsBuilderARMVIXL : public HGraphVisitor { 347 public: LocationsBuilderARMVIXL(HGraph * graph,CodeGeneratorARMVIXL * codegen)348 LocationsBuilderARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen) 349 : HGraphVisitor(graph), codegen_(codegen) {} 350 351 #define DECLARE_VISIT_INSTRUCTION(name, super) \ 352 void Visit##name(H##name* instr) override; 353 354 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION)355 FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) 356 FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) 357 358 #undef DECLARE_VISIT_INSTRUCTION 359 360 void VisitInstruction(HInstruction* instruction) override { 361 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 362 << " (id " << instruction->GetId() << ")"; 363 } 364 365 private: 366 void HandleInvoke(HInvoke* invoke); 367 void HandleBitwiseOperation(HBinaryOperation* operation, Opcode opcode); 368 void HandleCondition(HCondition* condition); 369 void HandleIntegerRotate(LocationSummary* locations); 370 void HandleLongRotate(LocationSummary* locations); 371 void HandleShift(HBinaryOperation* operation); 372 void HandleFieldSet(HInstruction* instruction, 373 const FieldInfo& field_info, 374 WriteBarrierKind write_barrier_kind); 375 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); 376 377 Location ArithmeticZeroOrFpuRegister(HInstruction* input); 378 Location ArmEncodableConstantOrRegister(HInstruction* constant, Opcode opcode); 379 bool CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode); 380 381 CodeGeneratorARMVIXL* const codegen_; 382 InvokeDexCallingConventionVisitorARMVIXL parameter_visitor_; 383 384 DISALLOW_COPY_AND_ASSIGN(LocationsBuilderARMVIXL); 385 }; 386 387 class InstructionCodeGeneratorARMVIXL : public InstructionCodeGenerator { 388 public: 389 InstructionCodeGeneratorARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen); 390 391 #define DECLARE_VISIT_INSTRUCTION(name, super) \ 392 void Visit##name(H##name* instr) override; 393 394 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION)395 FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) 396 FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) 397 398 #undef DECLARE_VISIT_INSTRUCTION 399 400 void VisitInstruction(HInstruction* instruction) override { 401 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 402 << " (id " << instruction->GetId() << ")"; 403 } 404 GetAssembler()405 ArmVIXLAssembler* GetAssembler() const { return assembler_; } GetVIXLAssembler()406 ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } 407 408 void GenerateAndConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 409 410 private: 411 // Generate code for the given suspend check. If not null, `successor` 412 // is the block to branch to if the suspend check is not needed, and after 413 // the suspend call. 414 void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor); 415 void GenerateClassInitializationCheck(LoadClassSlowPathARMVIXL* slow_path, 416 vixl32::Register class_reg); 417 void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check, 418 vixl::aarch32::Register temp, 419 vixl::aarch32::FlagsUpdate flags_update); 420 void GenerateOrrConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 421 void GenerateEorConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 422 void GenerateAddLongConst(Location out, Location first, uint64_t value); 423 void HandleBitwiseOperation(HBinaryOperation* operation); 424 void HandleCondition(HCondition* condition); 425 void HandleIntegerRotate(HRor* ror); 426 void HandleLongRotate(HRor* ror); 427 void HandleShift(HBinaryOperation* operation); 428 429 void GenerateWideAtomicStore(vixl::aarch32::Register addr, 430 uint32_t offset, 431 vixl::aarch32::Register value_lo, 432 vixl::aarch32::Register value_hi, 433 vixl::aarch32::Register temp1, 434 vixl::aarch32::Register temp2, 435 HInstruction* instruction); 436 void GenerateWideAtomicLoad(vixl::aarch32::Register addr, 437 uint32_t offset, 438 vixl::aarch32::Register out_lo, 439 vixl::aarch32::Register out_hi); 440 441 void HandleFieldSet(HInstruction* instruction, 442 const FieldInfo& field_info, 443 bool value_can_be_null, 444 WriteBarrierKind write_barrier_kind); 445 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); 446 447 void GenerateMinMaxInt(LocationSummary* locations, bool is_min); 448 void GenerateMinMaxLong(LocationSummary* locations, bool is_min); 449 void GenerateMinMaxFloat(HInstruction* minmax, bool is_min); 450 void GenerateMinMaxDouble(HInstruction* minmax, bool is_min); 451 void GenerateMinMax(HBinaryOperation* minmax, bool is_min); 452 453 // Generate a heap reference load using one register `out`: 454 // 455 // out <- *(out + offset) 456 // 457 // while honoring heap poisoning and/or read barriers (if any). 458 // 459 // Location `maybe_temp` is used when generating a read barrier and 460 // shall be a register in that case; it may be an invalid location 461 // otherwise. 462 void GenerateReferenceLoadOneRegister(HInstruction* instruction, 463 Location out, 464 uint32_t offset, 465 Location maybe_temp, 466 ReadBarrierOption read_barrier_option); 467 // Generate a heap reference load using two different registers 468 // `out` and `obj`: 469 // 470 // out <- *(obj + offset) 471 // 472 // while honoring heap poisoning and/or read barriers (if any). 473 // 474 // Location `maybe_temp` is used when generating a Baker's (fast 475 // path) read barrier and shall be a register in that case; it may 476 // be an invalid location otherwise. 477 void GenerateReferenceLoadTwoRegisters(HInstruction* instruction, 478 Location out, 479 Location obj, 480 uint32_t offset, 481 Location maybe_temp, 482 ReadBarrierOption read_barrier_option); 483 void GenerateTestAndBranch(HInstruction* instruction, 484 size_t condition_input_index, 485 vixl::aarch32::Label* true_target, 486 vixl::aarch32::Label* false_target, 487 bool far_target = true); 488 void GenerateCompareTestAndBranch(HCondition* condition, 489 vixl::aarch32::Label* true_target, 490 vixl::aarch32::Label* false_target, 491 bool is_far_target = true); 492 void DivRemOneOrMinusOne(HBinaryOperation* instruction); 493 void DivRemByPowerOfTwo(HBinaryOperation* instruction); 494 void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction); 495 void GenerateDivRemConstantIntegral(HBinaryOperation* instruction); 496 void HandleGoto(HInstruction* got, HBasicBlock* successor); 497 void GenerateMethodEntryExitHook(HInstruction* instruction); 498 499 vixl::aarch32::MemOperand VecAddress( 500 HVecMemoryOperation* instruction, 501 // This function may acquire a scratch register. 502 vixl::aarch32::UseScratchRegisterScope* temps_scope, 503 /*out*/ vixl32::Register* scratch); 504 vixl::aarch32::AlignedMemOperand VecAddressUnaligned( 505 HVecMemoryOperation* instruction, 506 // This function may acquire a scratch register. 507 vixl::aarch32::UseScratchRegisterScope* temps_scope, 508 /*out*/ vixl32::Register* scratch); 509 510 ArmVIXLAssembler* const assembler_; 511 CodeGeneratorARMVIXL* const codegen_; 512 513 DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorARMVIXL); 514 }; 515 516 class CodeGeneratorARMVIXL : public CodeGenerator { 517 public: 518 CodeGeneratorARMVIXL(HGraph* graph, 519 const CompilerOptions& compiler_options, 520 OptimizingCompilerStats* stats = nullptr); ~CodeGeneratorARMVIXL()521 virtual ~CodeGeneratorARMVIXL() {} 522 523 void GenerateFrameEntry() override; 524 void GenerateFrameExit() override; 525 void Bind(HBasicBlock* block) override; 526 void MoveConstant(Location destination, int32_t value) override; 527 void MoveLocation(Location dst, Location src, DataType::Type dst_type) override; 528 void AddLocationAsTemp(Location location, LocationSummary* locations) override; 529 530 size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) override; 531 size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) override; 532 size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) override; 533 size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) override; 534 GetWordSize()535 size_t GetWordSize() const override { 536 return static_cast<size_t>(kArmPointerSize); 537 } 538 GetCalleePreservedFPWidth()539 size_t GetCalleePreservedFPWidth() const override { 540 return vixl::aarch32::kSRegSizeInBytes; 541 } 542 GetSIMDRegisterWidth()543 size_t GetSIMDRegisterWidth() const override { 544 // ARM 32-bit backend doesn't support Q registers in vectorizer, only D 545 // registers (due to register allocator restrictions: overlapping s/d/q 546 // registers). 547 return vixl::aarch32::kDRegSizeInBytes; 548 } 549 GetLocationBuilder()550 HGraphVisitor* GetLocationBuilder() override { return &location_builder_; } 551 GetInstructionVisitor()552 HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; } 553 GetAssembler()554 ArmVIXLAssembler* GetAssembler() override { return &assembler_; } 555 GetAssembler()556 const ArmVIXLAssembler& GetAssembler() const override { return assembler_; } 557 GetVIXLAssembler()558 ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } 559 GetAddressOf(HBasicBlock * block)560 uintptr_t GetAddressOf(HBasicBlock* block) override { 561 vixl::aarch32::Label* block_entry_label = GetLabelOf(block); 562 DCHECK(block_entry_label->IsBound()); 563 return block_entry_label->GetLocation(); 564 } 565 566 void FixJumpTables(); 567 void SetupBlockedRegisters() const override; 568 569 void DumpCoreRegister(std::ostream& stream, int reg) const override; 570 void DumpFloatingPointRegister(std::ostream& stream, int reg) const override; 571 GetMoveResolver()572 ParallelMoveResolver* GetMoveResolver() override { return &move_resolver_; } GetInstructionSet()573 InstructionSet GetInstructionSet() const override { return InstructionSet::kThumb2; } 574 575 const ArmInstructionSetFeatures& GetInstructionSetFeatures() const; 576 577 // Helper method to move a 32-bit value between two locations. 578 void Move32(Location destination, Location source); 579 580 void LoadFromShiftedRegOffset(DataType::Type type, 581 Location out_loc, 582 vixl::aarch32::Register base, 583 vixl::aarch32::Register reg_index, 584 vixl::aarch32::Condition cond = vixl::aarch32::al); 585 void StoreToShiftedRegOffset(DataType::Type type, 586 Location out_loc, 587 vixl::aarch32::Register base, 588 vixl::aarch32::Register reg_index, 589 vixl::aarch32::Condition cond = vixl::aarch32::al); 590 591 // Generate code to invoke a runtime entry point. 592 void InvokeRuntime(QuickEntrypointEnum entrypoint, 593 HInstruction* instruction, 594 uint32_t dex_pc, 595 SlowPathCode* slow_path = nullptr) override; 596 597 // Generate code to invoke a runtime entry point, but do not record 598 // PC-related information in a stack map. 599 void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset, 600 HInstruction* instruction, 601 SlowPathCode* slow_path); 602 603 // Emit a write barrier. 604 void MarkGCCard(vixl::aarch32::Register temp, 605 vixl::aarch32::Register card, 606 vixl::aarch32::Register object, 607 vixl::aarch32::Register value, 608 bool emit_null_check); 609 610 void GenerateMemoryBarrier(MemBarrierKind kind); 611 GetLabelOf(HBasicBlock * block)612 vixl::aarch32::Label* GetLabelOf(HBasicBlock* block) { 613 block = FirstNonEmptyBlock(block); 614 return &(block_labels_[block->GetBlockId()]); 615 } 616 617 vixl32::Label* GetFinalLabel(HInstruction* instruction, vixl32::Label* final_label); 618 Initialize()619 void Initialize() override { 620 block_labels_.resize(GetGraph()->GetBlocks().size()); 621 } 622 623 void Finalize(CodeAllocator* allocator) override; 624 NeedsTwoRegisters(DataType::Type type)625 bool NeedsTwoRegisters(DataType::Type type) const override { 626 return type == DataType::Type::kFloat64 || type == DataType::Type::kInt64; 627 } 628 629 void ComputeSpillMask() override; 630 GetFrameEntryLabel()631 vixl::aarch32::Label* GetFrameEntryLabel() { return &frame_entry_label_; } 632 633 // Check if the desired_string_load_kind is supported. If it is, return it, 634 // otherwise return a fall-back kind that should be used instead. 635 HLoadString::LoadKind GetSupportedLoadStringKind( 636 HLoadString::LoadKind desired_string_load_kind) override; 637 638 // Check if the desired_class_load_kind is supported. If it is, return it, 639 // otherwise return a fall-back kind that should be used instead. 640 HLoadClass::LoadKind GetSupportedLoadClassKind( 641 HLoadClass::LoadKind desired_class_load_kind) override; 642 643 // Check if the desired_dispatch_info is supported. If it is, return it, 644 // otherwise return a fall-back info that should be used instead. 645 HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch( 646 const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info, 647 ArtMethod* method) override; 648 649 void LoadMethod(MethodLoadKind load_kind, Location temp, HInvoke* invoke); 650 void GenerateStaticOrDirectCall( 651 HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) override; 652 void GenerateVirtualCall( 653 HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) override; 654 655 void MoveFromReturnRegister(Location trg, DataType::Type type) override; 656 657 // The PcRelativePatchInfo is used for PC-relative addressing of methods/strings/types, 658 // whether through .data.bimg.rel.ro, .bss, or directly in the boot image. 659 // 660 // The PC-relative address is loaded with three instructions, 661 // MOVW+MOVT to load the offset to base_reg and then ADD base_reg, PC. The offset 662 // is calculated from the ADD's effective PC, i.e. PC+4 on Thumb2. Though we 663 // currently emit these 3 instructions together, instruction scheduling could 664 // split this sequence apart, so we keep separate labels for each of them. 665 struct PcRelativePatchInfo { PcRelativePatchInfoPcRelativePatchInfo666 PcRelativePatchInfo(const DexFile* dex_file, uint32_t off_or_idx) 667 : target_dex_file(dex_file), offset_or_index(off_or_idx) { } 668 669 // Target dex file or null for .data.bmig.rel.ro patches. 670 const DexFile* target_dex_file; 671 // Either the boot image offset (to write to .data.bmig.rel.ro) or string/type/method index. 672 uint32_t offset_or_index; 673 vixl::aarch32::Label movw_label; 674 vixl::aarch32::Label movt_label; 675 vixl::aarch32::Label add_pc_label; 676 }; 677 678 PcRelativePatchInfo* NewBootImageIntrinsicPatch(uint32_t intrinsic_data); 679 PcRelativePatchInfo* NewBootImageRelRoPatch(uint32_t boot_image_offset); 680 PcRelativePatchInfo* NewBootImageMethodPatch(MethodReference target_method); 681 PcRelativePatchInfo* NewMethodBssEntryPatch(MethodReference target_method); 682 PcRelativePatchInfo* NewBootImageTypePatch(const DexFile& dex_file, dex::TypeIndex type_index); 683 PcRelativePatchInfo* NewTypeBssEntryPatch(HLoadClass* load_class); 684 PcRelativePatchInfo* NewBootImageStringPatch(const DexFile& dex_file, 685 dex::StringIndex string_index); 686 PcRelativePatchInfo* NewStringBssEntryPatch(const DexFile& dex_file, 687 dex::StringIndex string_index); 688 689 // Emit the BL instruction for entrypoint thunk call and record the associated patch for AOT. 690 void EmitEntrypointThunkCall(ThreadOffset32 entrypoint_offset); 691 692 // Emit the BNE instruction for baker read barrier and record 693 // the associated patch for AOT or slow path for JIT. 694 void EmitBakerReadBarrierBne(uint32_t custom_data); 695 696 VIXLUInt32Literal* DeduplicateBootImageAddressLiteral(uint32_t address); 697 VIXLUInt32Literal* DeduplicateJitStringLiteral(const DexFile& dex_file, 698 dex::StringIndex string_index, 699 Handle<mirror::String> handle); 700 VIXLUInt32Literal* DeduplicateJitClassLiteral(const DexFile& dex_file, 701 dex::TypeIndex type_index, 702 Handle<mirror::Class> handle); 703 704 void LoadBootImageRelRoEntry(vixl::aarch32::Register reg, uint32_t boot_image_offset); 705 void LoadBootImageAddress(vixl::aarch32::Register reg, uint32_t boot_image_reference); 706 void LoadTypeForBootImageIntrinsic(vixl::aarch32::Register reg, TypeReference type_reference); 707 void LoadIntrinsicDeclaringClass(vixl::aarch32::Register reg, HInvoke* invoke); 708 void LoadClassRootForIntrinsic(vixl::aarch32::Register reg, ClassRoot class_root); 709 710 void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) override; 711 bool NeedsThunkCode(const linker::LinkerPatch& patch) const override; 712 void EmitThunkCode(const linker::LinkerPatch& patch, 713 /*out*/ ArenaVector<uint8_t>* code, 714 /*out*/ std::string* debug_name) override; 715 716 void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) override; 717 718 // Generate a GC root reference load: 719 // 720 // root <- *(obj + offset) 721 // 722 // while honoring read barriers based on read_barrier_option. 723 void GenerateGcRootFieldLoad(HInstruction* instruction, 724 Location root, 725 vixl::aarch32::Register obj, 726 uint32_t offset, 727 ReadBarrierOption read_barrier_option); 728 // Generate MOV for an intrinsic CAS to mark the old value with Baker read barrier. 729 void GenerateIntrinsicCasMoveWithBakerReadBarrier(vixl::aarch32::Register marked_old_value, 730 vixl::aarch32::Register old_value); 731 // Fast path implementation of ReadBarrier::Barrier for a heap 732 // reference field load when Baker's read barriers are used. 733 // Overload suitable for Unsafe.getObject/-Volatile() intrinsic. 734 void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 735 Location ref, 736 vixl::aarch32::Register obj, 737 const vixl::aarch32::MemOperand& src, 738 bool needs_null_check); 739 // Fast path implementation of ReadBarrier::Barrier for a heap 740 // reference field load when Baker's read barriers are used. 741 void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 742 Location ref, 743 vixl::aarch32::Register obj, 744 uint32_t offset, 745 Location maybe_temp, 746 bool needs_null_check); 747 // Fast path implementation of ReadBarrier::Barrier for a heap 748 // reference array load when Baker's read barriers are used. 749 void GenerateArrayLoadWithBakerReadBarrier(Location ref, 750 vixl::aarch32::Register obj, 751 uint32_t data_offset, 752 Location index, 753 Location temp, 754 bool needs_null_check); 755 756 // Emit code checking the status of the Marking Register, and 757 // aborting the program if MR does not match the value stored in the 758 // art::Thread object. Code is only emitted in debug mode and if 759 // CompilerOptions::EmitRunTimeChecksInDebugMode returns true. 760 // 761 // Argument `code` is used to identify the different occurrences of 762 // MaybeGenerateMarkingRegisterCheck in the code generator, and is 763 // used together with kMarkingRegisterCheckBreakCodeBaseCode to 764 // create the value passed to the BKPT instruction. Note that unlike 765 // in the ARM64 code generator, where `__LINE__` is passed as `code` 766 // argument to 767 // CodeGeneratorARM64::MaybeGenerateMarkingRegisterCheck, we cannot 768 // realistically do that here, as Encoding T1 for the BKPT 769 // instruction only accepts 8-bit immediate values. 770 // 771 // If `temp_loc` is a valid location, it is expected to be a 772 // register and will be used as a temporary to generate code; 773 // otherwise, a temporary will be fetched from the core register 774 // scratch pool. 775 virtual void MaybeGenerateMarkingRegisterCheck(int code, 776 Location temp_loc = Location::NoLocation()); 777 778 // Create slow path for a read barrier for a heap reference within `instruction`. 779 // 780 // This is a helper function for GenerateReadBarrierSlow() that has the same 781 // arguments. The creation and adding of the slow path is exposed for intrinsics 782 // that cannot use GenerateReadBarrierSlow() from their own slow paths. 783 SlowPathCodeARMVIXL* AddReadBarrierSlowPath(HInstruction* instruction, 784 Location out, 785 Location ref, 786 Location obj, 787 uint32_t offset, 788 Location index); 789 790 // Generate a read barrier for a heap reference within `instruction` 791 // using a slow path. 792 // 793 // A read barrier for an object reference read from the heap is 794 // implemented as a call to the artReadBarrierSlow runtime entry 795 // point, which is passed the values in locations `ref`, `obj`, and 796 // `offset`: 797 // 798 // mirror::Object* artReadBarrierSlow(mirror::Object* ref, 799 // mirror::Object* obj, 800 // uint32_t offset); 801 // 802 // The `out` location contains the value returned by 803 // artReadBarrierSlow. 804 // 805 // When `index` is provided (i.e. for array accesses), the offset 806 // value passed to artReadBarrierSlow is adjusted to take `index` 807 // into account. 808 void GenerateReadBarrierSlow(HInstruction* instruction, 809 Location out, 810 Location ref, 811 Location obj, 812 uint32_t offset, 813 Location index = Location::NoLocation()); 814 815 // If read barriers are enabled, generate a read barrier for a heap 816 // reference using a slow path. If heap poisoning is enabled, also 817 // unpoison the reference in `out`. 818 void MaybeGenerateReadBarrierSlow(HInstruction* instruction, 819 Location out, 820 Location ref, 821 Location obj, 822 uint32_t offset, 823 Location index = Location::NoLocation()); 824 825 // Generate a read barrier for a GC root within `instruction` using 826 // a slow path. 827 // 828 // A read barrier for an object reference GC root is implemented as 829 // a call to the artReadBarrierForRootSlow runtime entry point, 830 // which is passed the value in location `root`: 831 // 832 // mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root); 833 // 834 // The `out` location contains the value returned by 835 // artReadBarrierForRootSlow. 836 void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root); 837 838 void IncreaseFrame(size_t adjustment) override; 839 void DecreaseFrame(size_t adjustment) override; 840 841 void GenerateNop() override; 842 843 void GenerateImplicitNullCheck(HNullCheck* instruction) override; 844 void GenerateExplicitNullCheck(HNullCheck* instruction) override; 845 CreateJumpTable(HPackedSwitch * switch_instr)846 JumpTableARMVIXL* CreateJumpTable(HPackedSwitch* switch_instr) { 847 jump_tables_.emplace_back(new (GetGraph()->GetAllocator()) JumpTableARMVIXL(switch_instr)); 848 return jump_tables_.back().get(); 849 } 850 void EmitJumpTables(); 851 852 void EmitMovwMovtPlaceholder(CodeGeneratorARMVIXL::PcRelativePatchInfo* labels, 853 vixl::aarch32::Register out); 854 855 // `temp` is an extra temporary register that is used for some conditions; 856 // callers may not specify it, in which case the method will use a scratch 857 // register instead. 858 void GenerateConditionWithZero(IfCondition condition, 859 vixl::aarch32::Register out, 860 vixl::aarch32::Register in, 861 vixl::aarch32::Register temp = vixl32::Register()); 862 MaybeRecordImplicitNullCheck(HInstruction * instr)863 void MaybeRecordImplicitNullCheck(HInstruction* instr) final { 864 // The function must be only be called within special scopes 865 // (EmissionCheckScope, ExactAssemblyScope) which prevent generation of 866 // veneer/literal pools by VIXL assembler. 867 CHECK_EQ(GetVIXLAssembler()->ArePoolsBlocked(), true) 868 << "The function must only be called within EmissionCheckScope or ExactAssemblyScope"; 869 CodeGenerator::MaybeRecordImplicitNullCheck(instr); 870 } 871 872 void MaybeGenerateInlineCacheCheck(HInstruction* instruction, vixl32::Register klass); 873 void MaybeIncrementHotness(bool is_frame_entry); 874 875 private: 876 // Encoding of thunk type and data for link-time generated thunks for Baker read barriers. 877 878 enum class BakerReadBarrierKind : uint8_t { 879 kField, // Field get or array get with constant offset (i.e. constant index). 880 kArray, // Array get with index in register. 881 kGcRoot, // GC root load. 882 kIntrinsicCas, // Unsafe/VarHandle CAS intrinsic. 883 kLast = kIntrinsicCas 884 }; 885 886 enum class BakerReadBarrierWidth : uint8_t { 887 kWide, // 32-bit LDR (and 32-bit NEG if heap poisoning is enabled). 888 kNarrow, // 16-bit LDR (and 16-bit NEG if heap poisoning is enabled). 889 kLast = kNarrow 890 }; 891 892 static constexpr uint32_t kBakerReadBarrierInvalidEncodedReg = /* pc is invalid */ 15u; 893 894 static constexpr size_t kBitsForBakerReadBarrierKind = 895 MinimumBitsToStore(static_cast<size_t>(BakerReadBarrierKind::kLast)); 896 static constexpr size_t kBakerReadBarrierBitsForRegister = 897 MinimumBitsToStore(kBakerReadBarrierInvalidEncodedReg); 898 using BakerReadBarrierKindField = 899 BitField<BakerReadBarrierKind, 0, kBitsForBakerReadBarrierKind>; 900 using BakerReadBarrierFirstRegField = 901 BitField<uint32_t, kBitsForBakerReadBarrierKind, kBakerReadBarrierBitsForRegister>; 902 using BakerReadBarrierSecondRegField = 903 BitField<uint32_t, 904 kBitsForBakerReadBarrierKind + kBakerReadBarrierBitsForRegister, 905 kBakerReadBarrierBitsForRegister>; 906 static constexpr size_t kBitsForBakerReadBarrierWidth = 907 MinimumBitsToStore(static_cast<size_t>(BakerReadBarrierWidth::kLast)); 908 using BakerReadBarrierWidthField = 909 BitField<BakerReadBarrierWidth, 910 kBitsForBakerReadBarrierKind + 2 * kBakerReadBarrierBitsForRegister, 911 kBitsForBakerReadBarrierWidth>; 912 CheckValidReg(uint32_t reg)913 static void CheckValidReg(uint32_t reg) { 914 DCHECK(reg < vixl::aarch32::ip.GetCode() && reg != mr.GetCode()) << reg; 915 } 916 EncodeBakerReadBarrierFieldData(uint32_t base_reg,uint32_t holder_reg,bool narrow)917 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, 918 uint32_t holder_reg, 919 bool narrow) { 920 CheckValidReg(base_reg); 921 CheckValidReg(holder_reg); 922 DCHECK_IMPLIES(narrow, base_reg < 8u) << base_reg; 923 BakerReadBarrierWidth width = 924 narrow ? BakerReadBarrierWidth::kNarrow : BakerReadBarrierWidth::kWide; 925 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kField) | 926 BakerReadBarrierFirstRegField::Encode(base_reg) | 927 BakerReadBarrierSecondRegField::Encode(holder_reg) | 928 BakerReadBarrierWidthField::Encode(width); 929 } 930 EncodeBakerReadBarrierArrayData(uint32_t base_reg)931 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) { 932 CheckValidReg(base_reg); 933 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kArray) | 934 BakerReadBarrierFirstRegField::Encode(base_reg) | 935 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 936 BakerReadBarrierWidthField::Encode(BakerReadBarrierWidth::kWide); 937 } 938 EncodeBakerReadBarrierGcRootData(uint32_t root_reg,bool narrow)939 static uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg, bool narrow) { 940 CheckValidReg(root_reg); 941 DCHECK_IMPLIES(narrow, root_reg < 8u) << root_reg; 942 BakerReadBarrierWidth width = 943 narrow ? BakerReadBarrierWidth::kNarrow : BakerReadBarrierWidth::kWide; 944 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kGcRoot) | 945 BakerReadBarrierFirstRegField::Encode(root_reg) | 946 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 947 BakerReadBarrierWidthField::Encode(width); 948 } 949 EncodeBakerReadBarrierIntrinsicCasData(uint32_t root_reg)950 static uint32_t EncodeBakerReadBarrierIntrinsicCasData(uint32_t root_reg) { 951 CheckValidReg(root_reg); 952 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kIntrinsicCas) | 953 BakerReadBarrierFirstRegField::Encode(root_reg) | 954 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 955 BakerReadBarrierWidthField::Encode(BakerReadBarrierWidth::kWide); 956 } 957 958 void CompileBakerReadBarrierThunk(ArmVIXLAssembler& assembler, 959 uint32_t encoded_data, 960 /*out*/ std::string* debug_name); 961 962 using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, VIXLUInt32Literal*>; 963 using StringToLiteralMap = ArenaSafeMap<StringReference, 964 VIXLUInt32Literal*, 965 StringReferenceValueComparator>; 966 using TypeToLiteralMap = ArenaSafeMap<TypeReference, 967 VIXLUInt32Literal*, 968 TypeReferenceValueComparator>; 969 970 struct BakerReadBarrierPatchInfo { BakerReadBarrierPatchInfoBakerReadBarrierPatchInfo971 explicit BakerReadBarrierPatchInfo(uint32_t data) : label(), custom_data(data) { } 972 973 vixl::aarch32::Label label; 974 uint32_t custom_data; 975 }; 976 977 VIXLUInt32Literal* DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map); 978 PcRelativePatchInfo* NewPcRelativePatch(const DexFile* dex_file, 979 uint32_t offset_or_index, 980 ArenaDeque<PcRelativePatchInfo>* patches); 981 template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)> 982 static void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos, 983 ArenaVector<linker::LinkerPatch>* linker_patches); 984 985 // Labels for each block that will be compiled. 986 // We use a deque so that the `vixl::aarch32::Label` objects do not move in memory. 987 ArenaDeque<vixl::aarch32::Label> block_labels_; // Indexed by block id. 988 vixl::aarch32::Label frame_entry_label_; 989 990 ArenaVector<std::unique_ptr<JumpTableARMVIXL>> jump_tables_; 991 LocationsBuilderARMVIXL location_builder_; 992 InstructionCodeGeneratorARMVIXL instruction_visitor_; 993 ParallelMoveResolverARMVIXL move_resolver_; 994 995 ArmVIXLAssembler assembler_; 996 997 // PC-relative method patch info for kBootImageLinkTimePcRelative. 998 ArenaDeque<PcRelativePatchInfo> boot_image_method_patches_; 999 // PC-relative method patch info for kBssEntry. 1000 ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_; 1001 // PC-relative type patch info for kBootImageLinkTimePcRelative. 1002 ArenaDeque<PcRelativePatchInfo> boot_image_type_patches_; 1003 // PC-relative type patch info for kBssEntry. 1004 ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_; 1005 // PC-relative public type patch info for kBssEntryPublic. 1006 ArenaDeque<PcRelativePatchInfo> public_type_bss_entry_patches_; 1007 // PC-relative package type patch info for kBssEntryPackage. 1008 ArenaDeque<PcRelativePatchInfo> package_type_bss_entry_patches_; 1009 // PC-relative String patch info for kBootImageLinkTimePcRelative. 1010 ArenaDeque<PcRelativePatchInfo> boot_image_string_patches_; 1011 // PC-relative String patch info for kBssEntry. 1012 ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_; 1013 // PC-relative patch info for IntrinsicObjects for the boot image, 1014 // and for method/type/string patches for kBootImageRelRo otherwise. 1015 ArenaDeque<PcRelativePatchInfo> boot_image_other_patches_; 1016 // Patch info for calls to entrypoint dispatch thunks. Used for slow paths. 1017 ArenaDeque<PatchInfo<vixl::aarch32::Label>> call_entrypoint_patches_; 1018 // Baker read barrier patch info. 1019 ArenaDeque<BakerReadBarrierPatchInfo> baker_read_barrier_patches_; 1020 1021 // Deduplication map for 32-bit literals, used for JIT for boot image addresses. 1022 Uint32ToLiteralMap uint32_literals_; 1023 // Patches for string literals in JIT compiled code. 1024 StringToLiteralMap jit_string_patches_; 1025 // Patches for class literals in JIT compiled code. 1026 TypeToLiteralMap jit_class_patches_; 1027 1028 // Baker read barrier slow paths, mapping custom data (uint32_t) to label. 1029 // Wrap the label to work around vixl::aarch32::Label being non-copyable 1030 // and non-moveable and as such unusable in ArenaSafeMap<>. 1031 struct LabelWrapper { LabelWrapperLabelWrapper1032 LabelWrapper(const LabelWrapper& src) 1033 : label() { 1034 DCHECK(!src.label.IsReferenced() && !src.label.IsBound()); 1035 } 1036 LabelWrapper() = default; 1037 vixl::aarch32::Label label; 1038 }; 1039 ArenaSafeMap<uint32_t, LabelWrapper> jit_baker_read_barrier_slow_paths_; 1040 1041 friend class linker::Thumb2RelativePatcherTest; 1042 DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARMVIXL); 1043 }; 1044 1045 } // namespace arm 1046 } // namespace art 1047 1048 #endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 1049