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Searched defs:operand (Results 1 – 6 of 6) sorted by relevance

/art/disassembler/
Ddisassembler_arm.cc101 DisassemblerStream& operator<<(const MemOperand& operand) override { in operator <<()
115 DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override { in operator <<()
/art/compiler/utils/arm/
Dassembler_arm_vixl.h151 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
/art/compiler/utils/x86_64/
Dassembler_x86_64.cc4699 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { in shll()
4704 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) { in shlq()
4719 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { in shrl()
4724 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) { in shrq()
4734 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { in sarl()
4744 void X86_64Assembler::sarq(CpuRegister operand, CpuRegister shifter) { in sarq()
4754 void X86_64Assembler::roll(CpuRegister operand, CpuRegister shifter) { in roll()
4764 void X86_64Assembler::rorl(CpuRegister operand, CpuRegister shifter) { in rorl()
4774 void X86_64Assembler::rolq(CpuRegister operand, CpuRegister shifter) { in rolq()
4784 void X86_64Assembler::rorq(CpuRegister operand, CpuRegister shifter) { in rorq()
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/art/compiler/utils/x86/
Dassembler_x86.cc3408 void X86Assembler::shll(Register operand, Register shifter) { in shll()
3428 void X86Assembler::shrl(Register operand, Register shifter) { in shrl()
3448 void X86Assembler::sarl(Register operand, Register shifter) { in sarl()
3504 void X86Assembler::roll(Register operand, Register shifter) { in roll()
3514 void X86Assembler::rorl(Register operand, Register shifter) { in rorl()
3900 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { in EmitOperand()
3930 const Operand& operand, in EmitComplex()
3987 const Operand& operand, in EmitGenericShift()
4003 const Operand& operand, in EmitGenericShift()
4110 X86ManagedRegister operand, in EmitVexPrefixByteOne()
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/art/compiler/optimizing/
Dloop_optimization.cc94 /*out*/ HInstruction** operand) { in IsSignExtensionAndGet()
159 /*out*/ HInstruction** operand) { in IsZeroExtensionAndGet()
Dcode_generator_arm_vixl.cc1797 Operand operand(0); in GenerateConditionIntegralOrNonPrimitive() local