1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define MSM_PIPE_NONE 0x00 26 #define MSM_PIPE_2D0 0x01 27 #define MSM_PIPE_2D1 0x02 28 #define MSM_PIPE_3D0 0x10 29 #define MSM_PIPE_ID_MASK 0xffff 30 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 31 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 32 struct drm_msm_timespec { 33 __s64 tv_sec; 34 __s64 tv_nsec; 35 }; 36 #define MSM_PARAM_GPU_ID 0x01 37 #define MSM_PARAM_GMEM_SIZE 0x02 38 #define MSM_PARAM_CHIP_ID 0x03 39 #define MSM_PARAM_MAX_FREQ 0x04 40 #define MSM_PARAM_TIMESTAMP 0x05 41 #define MSM_PARAM_GMEM_BASE 0x06 42 #define MSM_PARAM_PRIORITIES 0x07 43 #define MSM_PARAM_PP_PGTABLE 0x08 44 #define MSM_PARAM_FAULTS 0x09 45 #define MSM_PARAM_SUSPENDS 0x0a 46 #define MSM_PARAM_SYSPROF 0x0b 47 #define MSM_PARAM_COMM 0x0c 48 #define MSM_PARAM_CMDLINE 0x0d 49 #define MSM_PARAM_VA_START 0x0e 50 #define MSM_PARAM_VA_SIZE 0x0f 51 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 52 struct drm_msm_param { 53 __u32 pipe; 54 __u32 param; 55 __u64 value; 56 __u32 len; 57 __u32 pad; 58 }; 59 #define MSM_BO_SCANOUT 0x00000001 60 #define MSM_BO_GPU_READONLY 0x00000002 61 #define MSM_BO_CACHE_MASK 0x000f0000 62 #define MSM_BO_CACHED 0x00010000 63 #define MSM_BO_WC 0x00020000 64 #define MSM_BO_UNCACHED 0x00040000 65 #define MSM_BO_CACHED_COHERENT 0x080000 66 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHE_MASK) 67 struct drm_msm_gem_new { 68 __u64 size; 69 __u32 flags; 70 __u32 handle; 71 }; 72 #define MSM_INFO_GET_OFFSET 0x00 73 #define MSM_INFO_GET_IOVA 0x01 74 #define MSM_INFO_SET_NAME 0x02 75 #define MSM_INFO_GET_NAME 0x03 76 #define MSM_INFO_SET_IOVA 0x04 77 #define MSM_INFO_GET_FLAGS 0x05 78 struct drm_msm_gem_info { 79 __u32 handle; 80 __u32 info; 81 __u64 value; 82 __u32 len; 83 __u32 pad; 84 }; 85 #define MSM_PREP_READ 0x01 86 #define MSM_PREP_WRITE 0x02 87 #define MSM_PREP_NOSYNC 0x04 88 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 89 struct drm_msm_gem_cpu_prep { 90 __u32 handle; 91 __u32 op; 92 struct drm_msm_timespec timeout; 93 }; 94 struct drm_msm_gem_cpu_fini { 95 __u32 handle; 96 }; 97 struct drm_msm_gem_submit_reloc { 98 __u32 submit_offset; 99 __u32 or; 100 __s32 shift; 101 __u32 reloc_idx; 102 __u64 reloc_offset; 103 }; 104 #define MSM_SUBMIT_CMD_BUF 0x0001 105 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 106 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 107 struct drm_msm_gem_submit_cmd { 108 __u32 type; 109 __u32 submit_idx; 110 __u32 submit_offset; 111 __u32 size; 112 __u32 pad; 113 __u32 nr_relocs; 114 __u64 relocs; 115 }; 116 #define MSM_SUBMIT_BO_READ 0x0001 117 #define MSM_SUBMIT_BO_WRITE 0x0002 118 #define MSM_SUBMIT_BO_DUMP 0x0004 119 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP) 120 struct drm_msm_gem_submit_bo { 121 __u32 flags; 122 __u32 handle; 123 __u64 presumed; 124 }; 125 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 126 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 127 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 128 #define MSM_SUBMIT_SUDO 0x10000000 129 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 130 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 131 #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 132 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) 133 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 134 #define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0) 135 struct drm_msm_gem_submit_syncobj { 136 __u32 handle; 137 __u32 flags; 138 __u64 point; 139 }; 140 struct drm_msm_gem_submit { 141 __u32 flags; 142 __u32 fence; 143 __u32 nr_bos; 144 __u32 nr_cmds; 145 __u64 bos; 146 __u64 cmds; 147 __s32 fence_fd; 148 __u32 queueid; 149 __u64 in_syncobjs; 150 __u64 out_syncobjs; 151 __u32 nr_in_syncobjs; 152 __u32 nr_out_syncobjs; 153 __u32 syncobj_stride; 154 __u32 pad; 155 }; 156 struct drm_msm_wait_fence { 157 __u32 fence; 158 __u32 pad; 159 struct drm_msm_timespec timeout; 160 __u32 queueid; 161 }; 162 #define MSM_MADV_WILLNEED 0 163 #define MSM_MADV_DONTNEED 1 164 #define __MSM_MADV_PURGED 2 165 struct drm_msm_gem_madvise { 166 __u32 handle; 167 __u32 madv; 168 __u32 retained; 169 }; 170 #define MSM_SUBMITQUEUE_FLAGS (0) 171 struct drm_msm_submitqueue { 172 __u32 flags; 173 __u32 prio; 174 __u32 id; 175 }; 176 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 177 struct drm_msm_submitqueue_query { 178 __u64 data; 179 __u32 id; 180 __u32 param; 181 __u32 len; 182 __u32 pad; 183 }; 184 #define DRM_MSM_GET_PARAM 0x00 185 #define DRM_MSM_SET_PARAM 0x01 186 #define DRM_MSM_GEM_NEW 0x02 187 #define DRM_MSM_GEM_INFO 0x03 188 #define DRM_MSM_GEM_CPU_PREP 0x04 189 #define DRM_MSM_GEM_CPU_FINI 0x05 190 #define DRM_MSM_GEM_SUBMIT 0x06 191 #define DRM_MSM_WAIT_FENCE 0x07 192 #define DRM_MSM_GEM_MADVISE 0x08 193 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 194 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 195 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 196 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 197 #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) 198 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 199 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 200 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 201 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 202 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 203 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 204 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 205 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 206 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 207 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 208 #ifdef __cplusplus 209 } 210 #endif 211 #endif 212