1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 #include "nir.h"
41 #include "nir/nir_to_tgsi_info.h"
42 #include "tgsi/tgsi_from_mesa.h"
43
r600_init_command_buffer(struct r600_command_buffer * cb,unsigned num_dw)44 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
45 {
46 assert(!cb->buf);
47 cb->buf = CALLOC(1, 4 * num_dw);
48 cb->max_num_dw = num_dw;
49 }
50
r600_release_command_buffer(struct r600_command_buffer * cb)51 void r600_release_command_buffer(struct r600_command_buffer *cb)
52 {
53 FREE(cb->buf);
54 }
55
r600_add_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id)56 void r600_add_atom(struct r600_context *rctx,
57 struct r600_atom *atom,
58 unsigned id)
59 {
60 assert(id < R600_NUM_ATOMS);
61 assert(rctx->atoms[id] == NULL);
62 rctx->atoms[id] = atom;
63 atom->id = id;
64 }
65
r600_init_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id,void (* emit)(struct r600_context * ctx,struct r600_atom * state),unsigned num_dw)66 void r600_init_atom(struct r600_context *rctx,
67 struct r600_atom *atom,
68 unsigned id,
69 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
70 unsigned num_dw)
71 {
72 atom->emit = (void*)emit;
73 atom->num_dw = num_dw;
74 r600_add_atom(rctx, atom, id);
75 }
76
r600_emit_cso_state(struct r600_context * rctx,struct r600_atom * atom)77 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
78 {
79 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
80 }
81
r600_emit_alphatest_state(struct r600_context * rctx,struct r600_atom * atom)82 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
83 {
84 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
85 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
86 unsigned alpha_ref = a->sx_alpha_ref;
87
88 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
89 alpha_ref &= ~0x1FFF;
90 }
91
92 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
93 a->sx_alpha_test_control |
94 S_028410_ALPHA_TEST_BYPASS(a->bypass));
95 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
96 }
97
r600_memory_barrier(struct pipe_context * ctx,unsigned flags)98 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
99 {
100 struct r600_context *rctx = (struct r600_context *)ctx;
101
102 if (!(flags & ~PIPE_BARRIER_UPDATE))
103 return;
104
105 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
106 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
107
108 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
109 PIPE_BARRIER_SHADER_BUFFER |
110 PIPE_BARRIER_TEXTURE |
111 PIPE_BARRIER_IMAGE |
112 PIPE_BARRIER_STREAMOUT_BUFFER |
113 PIPE_BARRIER_GLOBAL_BUFFER)) {
114 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
115 R600_CONTEXT_INV_TEX_CACHE;
116 }
117
118 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
119 PIPE_BARRIER_IMAGE))
120 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
121
122 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
123 }
124
r600_texture_barrier(struct pipe_context * ctx,unsigned flags)125 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
126 {
127 struct r600_context *rctx = (struct r600_context *)ctx;
128
129 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
130 R600_CONTEXT_FLUSH_AND_INV_CB |
131 R600_CONTEXT_FLUSH_AND_INV |
132 R600_CONTEXT_WAIT_3D_IDLE;
133 rctx->framebuffer.do_update_surf_dirtiness = true;
134 }
135
r600_conv_pipe_prim(unsigned prim)136 static unsigned r600_conv_pipe_prim(unsigned prim)
137 {
138 static const unsigned prim_conv[] = {
139 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
140 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
141 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
142 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
143 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
144 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
145 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
146 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
147 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
148 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
149 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
150 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
151 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
152 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
153 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
154 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
155 };
156 assert(prim < ARRAY_SIZE(prim_conv));
157 return prim_conv[prim];
158 }
159
r600_conv_prim_to_gs_out(unsigned mode)160 unsigned r600_conv_prim_to_gs_out(unsigned mode)
161 {
162 static const int prim_conv[] = {
163 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
164 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
165 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
168 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
170 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
171 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
172 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
173 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
174 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
175 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
176 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
177 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
178 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
179 };
180 assert(mode < ARRAY_SIZE(prim_conv));
181
182 return prim_conv[mode];
183 }
184
185 /* common state between evergreen and r600 */
186
r600_bind_blend_state_internal(struct r600_context * rctx,struct r600_blend_state * blend,bool blend_disable)187 static void r600_bind_blend_state_internal(struct r600_context *rctx,
188 struct r600_blend_state *blend, bool blend_disable)
189 {
190 unsigned color_control;
191 bool update_cb = false;
192
193 rctx->alpha_to_one = blend->alpha_to_one;
194 rctx->dual_src_blend = blend->dual_src_blend;
195
196 if (!blend_disable) {
197 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
198 color_control = blend->cb_color_control;
199 } else {
200 /* Blending is disabled. */
201 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
202 color_control = blend->cb_color_control_no_blend;
203 }
204
205 /* Update derived states. */
206 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
207 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
208 update_cb = true;
209 }
210 if (rctx->b.chip_class <= R700 &&
211 rctx->cb_misc_state.cb_color_control != color_control) {
212 rctx->cb_misc_state.cb_color_control = color_control;
213 update_cb = true;
214 }
215 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
216 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
217 update_cb = true;
218 }
219 if (update_cb) {
220 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
221 }
222 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
223 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
224 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
225 }
226 }
227
r600_bind_blend_state(struct pipe_context * ctx,void * state)228 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
229 {
230 struct r600_context *rctx = (struct r600_context *)ctx;
231 struct r600_blend_state *blend = (struct r600_blend_state *)state;
232
233 if (!blend) {
234 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
235 return;
236 }
237
238 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
239 }
240
r600_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)241 static void r600_set_blend_color(struct pipe_context *ctx,
242 const struct pipe_blend_color *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245
246 rctx->blend_color.state = *state;
247 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
248 }
249
r600_emit_blend_color(struct r600_context * rctx,struct r600_atom * atom)250 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
251 {
252 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
253 struct pipe_blend_color *state = &rctx->blend_color.state;
254
255 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
256 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
257 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
258 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
259 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
260 }
261
r600_emit_vgt_state(struct r600_context * rctx,struct r600_atom * atom)262 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
263 {
264 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
265 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
266
267 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
268 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
269 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
270 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
271 if (a->last_draw_was_indirect) {
272 a->last_draw_was_indirect = false;
273 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
274 }
275 }
276
r600_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)277 static void r600_set_clip_state(struct pipe_context *ctx,
278 const struct pipe_clip_state *state)
279 {
280 struct r600_context *rctx = (struct r600_context *)ctx;
281
282 rctx->clip_state.state = *state;
283 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
284 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
285 }
286
r600_set_stencil_ref(struct pipe_context * ctx,const struct r600_stencil_ref * state)287 static void r600_set_stencil_ref(struct pipe_context *ctx,
288 const struct r600_stencil_ref *state)
289 {
290 struct r600_context *rctx = (struct r600_context *)ctx;
291
292 rctx->stencil_ref.state = *state;
293 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
294 }
295
r600_emit_stencil_ref(struct r600_context * rctx,struct r600_atom * atom)296 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
297 {
298 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
299 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
300
301 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
302 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
303 S_028430_STENCILREF(a->state.ref_value[0]) |
304 S_028430_STENCILMASK(a->state.valuemask[0]) |
305 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
306 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
307 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
308 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
309 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
310 }
311
r600_set_pipe_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref * state)312 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
313 const struct pipe_stencil_ref *state)
314 {
315 struct r600_context *rctx = (struct r600_context *)ctx;
316 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
317 struct r600_stencil_ref ref;
318
319 rctx->stencil_ref.pipe_state = *state;
320
321 if (!dsa)
322 return;
323
324 ref.ref_value[0] = state->ref_value[0];
325 ref.ref_value[1] = state->ref_value[1];
326 ref.valuemask[0] = dsa->valuemask[0];
327 ref.valuemask[1] = dsa->valuemask[1];
328 ref.writemask[0] = dsa->writemask[0];
329 ref.writemask[1] = dsa->writemask[1];
330
331 r600_set_stencil_ref(ctx, &ref);
332 }
333
r600_bind_dsa_state(struct pipe_context * ctx,void * state)334 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
335 {
336 struct r600_context *rctx = (struct r600_context *)ctx;
337 struct r600_dsa_state *dsa = state;
338 struct r600_stencil_ref ref;
339
340 if (!state) {
341 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
342 return;
343 }
344
345 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
346
347 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
348 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
349 ref.valuemask[0] = dsa->valuemask[0];
350 ref.valuemask[1] = dsa->valuemask[1];
351 ref.writemask[0] = dsa->writemask[0];
352 ref.writemask[1] = dsa->writemask[1];
353 if (rctx->zwritemask != dsa->zwritemask) {
354 rctx->zwritemask = dsa->zwritemask;
355 if (rctx->b.chip_class >= EVERGREEN) {
356 /* work around some issue when not writing to zbuffer
357 * we are having lockup on evergreen so do not enable
358 * hyperz when not writing zbuffer
359 */
360 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
361 }
362 }
363
364 r600_set_stencil_ref(ctx, &ref);
365
366 /* Update alphatest state. */
367 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
368 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
369 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
370 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
371 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
372 }
373 }
374
r600_bind_rs_state(struct pipe_context * ctx,void * state)375 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
376 {
377 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
378 struct r600_context *rctx = (struct r600_context *)ctx;
379
380 if (!state)
381 return;
382
383 rctx->rasterizer = rs;
384
385 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
386
387 if (rs->offset_enable &&
388 (rs->offset_units != rctx->poly_offset_state.offset_units ||
389 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
390 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
391 rctx->poly_offset_state.offset_units = rs->offset_units;
392 rctx->poly_offset_state.offset_scale = rs->offset_scale;
393 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
394 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
395 }
396
397 /* Update clip_misc_state. */
398 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
399 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
400 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
401 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
402 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
403 }
404
405 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
406
407 /* Re-emit PA_SC_LINE_STIPPLE. */
408 rctx->last_primitive_type = -1;
409 }
410
r600_delete_rs_state(struct pipe_context * ctx,void * state)411 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
412 {
413 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
414
415 r600_release_command_buffer(&rs->buffer);
416 FREE(rs);
417 }
418
r600_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)419 static void r600_sampler_view_destroy(struct pipe_context *ctx,
420 struct pipe_sampler_view *state)
421 {
422 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
423
424 if (view->tex_resource->gpu_address &&
425 view->tex_resource->b.b.target == PIPE_BUFFER)
426 list_delinit(&view->list);
427
428 pipe_resource_reference(&state->texture, NULL);
429 FREE(view);
430 }
431
r600_sampler_states_dirty(struct r600_context * rctx,struct r600_sampler_states * state)432 void r600_sampler_states_dirty(struct r600_context *rctx,
433 struct r600_sampler_states *state)
434 {
435 if (state->dirty_mask) {
436 if (state->dirty_mask & state->has_bordercolor_mask) {
437 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
438 }
439 state->atom.num_dw =
440 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
441 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
442 r600_mark_atom_dirty(rctx, &state->atom);
443 }
444 }
445
r600_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,void ** states)446 static void r600_bind_sampler_states(struct pipe_context *pipe,
447 enum pipe_shader_type shader,
448 unsigned start,
449 unsigned count, void **states)
450 {
451 struct r600_context *rctx = (struct r600_context *)pipe;
452 struct r600_textures_info *dst = &rctx->samplers[shader];
453 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
454 int seamless_cube_map = -1;
455 unsigned i;
456 /* This sets 1-bit for states with index >= count. */
457 uint32_t disable_mask = ~((1ull << count) - 1);
458 /* These are the new states set by this function. */
459 uint32_t new_mask = 0;
460
461 assert(start == 0); /* XXX fix below */
462
463 if (!states) {
464 disable_mask = ~0u;
465 count = 0;
466 }
467
468 for (i = 0; i < count; i++) {
469 struct r600_pipe_sampler_state *rstate = rstates[i];
470
471 if (rstate == dst->states.states[i]) {
472 continue;
473 }
474
475 if (rstate) {
476 if (rstate->border_color_use) {
477 dst->states.has_bordercolor_mask |= 1 << i;
478 } else {
479 dst->states.has_bordercolor_mask &= ~(1 << i);
480 }
481 seamless_cube_map = rstate->seamless_cube_map;
482
483 new_mask |= 1 << i;
484 } else {
485 disable_mask |= 1 << i;
486 }
487 }
488
489 memcpy(dst->states.states, rstates, sizeof(void*) * count);
490 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
491
492 dst->states.enabled_mask &= ~disable_mask;
493 dst->states.dirty_mask &= dst->states.enabled_mask;
494 dst->states.enabled_mask |= new_mask;
495 dst->states.dirty_mask |= new_mask;
496 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
497
498 r600_sampler_states_dirty(rctx, &dst->states);
499
500 /* Seamless cubemap state. */
501 if (rctx->b.chip_class <= R700 &&
502 seamless_cube_map != -1 &&
503 seamless_cube_map != rctx->seamless_cube_map.enabled) {
504 /* change in TA_CNTL_AUX need a pipeline flush */
505 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
506 rctx->seamless_cube_map.enabled = seamless_cube_map;
507 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
508 }
509 }
510
r600_delete_sampler_state(struct pipe_context * ctx,void * state)511 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
512 {
513 free(state);
514 }
515
r600_delete_blend_state(struct pipe_context * ctx,void * state)516 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 struct r600_blend_state *blend = (struct r600_blend_state*)state;
520
521 if (rctx->blend_state.cso == state) {
522 ctx->bind_blend_state(ctx, NULL);
523 }
524
525 r600_release_command_buffer(&blend->buffer);
526 r600_release_command_buffer(&blend->buffer_no_blend);
527 FREE(blend);
528 }
529
r600_delete_dsa_state(struct pipe_context * ctx,void * state)530 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
531 {
532 struct r600_context *rctx = (struct r600_context *)ctx;
533 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
534
535 if (rctx->dsa_state.cso == state) {
536 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
537 }
538
539 r600_release_command_buffer(&dsa->buffer);
540 free(dsa);
541 }
542
r600_bind_vertex_elements(struct pipe_context * ctx,void * state)543 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
544 {
545 struct r600_context *rctx = (struct r600_context *)ctx;
546
547 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
548 }
549
r600_delete_vertex_elements(struct pipe_context * ctx,void * state)550 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
551 {
552 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
553 if (shader)
554 r600_resource_reference(&shader->buffer, NULL);
555 FREE(shader);
556 }
557
r600_vertex_buffers_dirty(struct r600_context * rctx)558 void r600_vertex_buffers_dirty(struct r600_context *rctx)
559 {
560 if (rctx->vertex_buffer_state.dirty_mask) {
561 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
562 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
563 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
564 }
565 }
566
r600_set_vertex_buffers(struct pipe_context * ctx,unsigned start_slot,unsigned count,const struct pipe_vertex_buffer * input)567 static void r600_set_vertex_buffers(struct pipe_context *ctx,
568 unsigned start_slot, unsigned count,
569 const struct pipe_vertex_buffer *input)
570 {
571 struct r600_context *rctx = (struct r600_context *)ctx;
572 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
573 struct pipe_vertex_buffer *vb = state->vb + start_slot;
574 unsigned i;
575 uint32_t disable_mask = 0;
576 /* These are the new buffers set by this function. */
577 uint32_t new_buffer_mask = 0;
578
579 /* Set vertex buffers. */
580 if (input) {
581 for (i = 0; i < count; i++) {
582 if ((input[i].buffer.resource != vb[i].buffer.resource) ||
583 (vb[i].stride != input[i].stride) ||
584 (vb[i].buffer_offset != input[i].buffer_offset) ||
585 (vb[i].is_user_buffer != input[i].is_user_buffer)) {
586 if (input[i].buffer.resource) {
587 vb[i].stride = input[i].stride;
588 vb[i].buffer_offset = input[i].buffer_offset;
589 pipe_resource_reference(&vb[i].buffer.resource, input[i].buffer.resource);
590 new_buffer_mask |= 1 << i;
591 r600_context_add_resource_size(ctx, input[i].buffer.resource);
592 } else {
593 pipe_resource_reference(&vb[i].buffer.resource, NULL);
594 disable_mask |= 1 << i;
595 }
596 }
597 }
598 } else {
599 for (i = 0; i < count; i++) {
600 pipe_resource_reference(&vb[i].buffer.resource, NULL);
601 }
602 disable_mask = ((1ull << count) - 1);
603 }
604
605 disable_mask <<= start_slot;
606 new_buffer_mask <<= start_slot;
607
608 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
609 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
610 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
611 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
612
613 r600_vertex_buffers_dirty(rctx);
614 }
615
r600_sampler_views_dirty(struct r600_context * rctx,struct r600_samplerview_state * state)616 void r600_sampler_views_dirty(struct r600_context *rctx,
617 struct r600_samplerview_state *state)
618 {
619 if (state->dirty_mask) {
620 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
621 util_bitcount(state->dirty_mask);
622 r600_mark_atom_dirty(rctx, &state->atom);
623 }
624 }
625
r600_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,struct pipe_sampler_view ** views)626 static void r600_set_sampler_views(struct pipe_context *pipe,
627 enum pipe_shader_type shader,
628 unsigned start, unsigned count,
629 struct pipe_sampler_view **views)
630 {
631 struct r600_context *rctx = (struct r600_context *) pipe;
632 struct r600_textures_info *dst = &rctx->samplers[shader];
633 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
634 uint32_t dirty_sampler_states_mask = 0;
635 unsigned i;
636 /* This sets 1-bit for textures with index >= count. */
637 uint32_t disable_mask = ~((1ull << count) - 1);
638 /* These are the new textures set by this function. */
639 uint32_t new_mask = 0;
640
641 /* Set textures with index >= count to NULL. */
642 uint32_t remaining_mask;
643
644 assert(start == 0); /* XXX fix below */
645
646 if (!views) {
647 disable_mask = ~0u;
648 count = 0;
649 }
650
651 remaining_mask = dst->views.enabled_mask & disable_mask;
652
653 while (remaining_mask) {
654 i = u_bit_scan(&remaining_mask);
655 assert(dst->views.views[i]);
656
657 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
658 }
659
660 for (i = 0; i < count; i++) {
661 if (rviews[i] == dst->views.views[i]) {
662 continue;
663 }
664
665 if (rviews[i]) {
666 struct r600_texture *rtex =
667 (struct r600_texture*)rviews[i]->base.texture;
668 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
669
670 if (!is_buffer && rtex->db_compatible) {
671 dst->views.compressed_depthtex_mask |= 1 << i;
672 } else {
673 dst->views.compressed_depthtex_mask &= ~(1 << i);
674 }
675
676 /* Track compressed colorbuffers. */
677 if (!is_buffer && rtex->cmask.size) {
678 dst->views.compressed_colortex_mask |= 1 << i;
679 } else {
680 dst->views.compressed_colortex_mask &= ~(1 << i);
681 }
682
683 /* Changing from array to non-arrays textures and vice versa requires
684 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
685 if (rctx->b.chip_class <= R700 &&
686 (dst->states.enabled_mask & (1 << i)) &&
687 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
688 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
689 dirty_sampler_states_mask |= 1 << i;
690 }
691
692 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
693 new_mask |= 1 << i;
694 r600_context_add_resource_size(pipe, views[i]->texture);
695 } else {
696 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
697 disable_mask |= 1 << i;
698 }
699 }
700
701 dst->views.enabled_mask &= ~disable_mask;
702 dst->views.dirty_mask &= dst->views.enabled_mask;
703 dst->views.enabled_mask |= new_mask;
704 dst->views.dirty_mask |= new_mask;
705 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
706 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
707 dst->views.dirty_buffer_constants = TRUE;
708 r600_sampler_views_dirty(rctx, &dst->views);
709
710 if (dirty_sampler_states_mask) {
711 dst->states.dirty_mask |= dirty_sampler_states_mask;
712 r600_sampler_states_dirty(rctx, &dst->states);
713 }
714 }
715
r600_update_compressed_colortex_mask(struct r600_samplerview_state * views)716 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
717 {
718 uint32_t mask = views->enabled_mask;
719
720 while (mask) {
721 unsigned i = u_bit_scan(&mask);
722 struct pipe_resource *res = views->views[i]->base.texture;
723
724 if (res && res->target != PIPE_BUFFER) {
725 struct r600_texture *rtex = (struct r600_texture *)res;
726
727 if (rtex->cmask.size) {
728 views->compressed_colortex_mask |= 1 << i;
729 } else {
730 views->compressed_colortex_mask &= ~(1 << i);
731 }
732 }
733 }
734 }
735
r600_get_hw_atomic_count(const struct pipe_context * ctx,enum pipe_shader_type shader)736 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
737 enum pipe_shader_type shader)
738 {
739 const struct r600_context *rctx = (struct r600_context *)ctx;
740 int value = 0;
741 switch (shader) {
742 case PIPE_SHADER_FRAGMENT:
743 case PIPE_SHADER_COMPUTE:
744 default:
745 break;
746 case PIPE_SHADER_VERTEX:
747 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
748 break;
749 case PIPE_SHADER_GEOMETRY:
750 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
751 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
752 break;
753 case PIPE_SHADER_TESS_EVAL:
754 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
755 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
756 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
757 break;
758 case PIPE_SHADER_TESS_CTRL:
759 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
760 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
761 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
762 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
763 break;
764 }
765 return value;
766 }
767
r600_update_compressed_colortex_mask_images(struct r600_image_state * images)768 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
769 {
770 uint32_t mask = images->enabled_mask;
771
772 while (mask) {
773 unsigned i = u_bit_scan(&mask);
774 struct pipe_resource *res = images->views[i].base.resource;
775
776 if (res && res->target != PIPE_BUFFER) {
777 struct r600_texture *rtex = (struct r600_texture *)res;
778
779 if (rtex->cmask.size) {
780 images->compressed_colortex_mask |= 1 << i;
781 } else {
782 images->compressed_colortex_mask &= ~(1 << i);
783 }
784 }
785 }
786 }
787
788 /* Compute the key for the hw shader variant */
r600_shader_selector_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)789 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
790 const struct r600_pipe_shader_selector *sel,
791 union r600_shader_key *key)
792 {
793 const struct r600_context *rctx = (struct r600_context *)ctx;
794 memset(key, 0, sizeof(*key));
795
796 switch (sel->type) {
797 case PIPE_SHADER_VERTEX: {
798 key->vs.as_ls = (rctx->tes_shader != NULL);
799 if (!key->vs.as_ls)
800 key->vs.as_es = (rctx->gs_shader != NULL);
801
802 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
803 key->vs.as_gs_a = true;
804 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
805 }
806 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
807 break;
808 }
809 case PIPE_SHADER_GEOMETRY:
810 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
811 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
812 break;
813 case PIPE_SHADER_FRAGMENT: {
814 if (rctx->ps_shader->info.images_declared)
815 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
816 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
817 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
818 key->ps.alpha_to_one = rctx->alpha_to_one &&
819 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
820 !rctx->framebuffer.cb0_is_integer;
821 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
822 key->ps.apply_sample_id_mask = (rctx->ps_iter_samples > 1) || !rctx->rasterizer->multisample_enable;
823 /* Dual-source blending only makes sense with nr_cbufs == 1. */
824 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend) {
825 key->ps.nr_cbufs = 2;
826 key->ps.dual_source_blend = 1;
827 }
828 break;
829 }
830 case PIPE_SHADER_TESS_EVAL:
831 key->tes.as_es = (rctx->gs_shader != NULL);
832 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
833 break;
834 case PIPE_SHADER_TESS_CTRL:
835 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
836 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
837 break;
838 case PIPE_SHADER_COMPUTE:
839 break;
840 default:
841 assert(0);
842 }
843 }
844
845 /* Select the hw shader variant depending on the current state.
846 * (*dirty) is set to 1 if current variant was changed */
r600_shader_select(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel,bool * dirty)847 int r600_shader_select(struct pipe_context *ctx,
848 struct r600_pipe_shader_selector* sel,
849 bool *dirty)
850 {
851 union r600_shader_key key;
852 struct r600_pipe_shader * shader = NULL;
853 int r;
854
855 r600_shader_selector_key(ctx, sel, &key);
856
857 /* Check if we don't need to change anything.
858 * This path is also used for most shaders that don't need multiple
859 * variants, it will cost just a computation of the key and this
860 * test. */
861 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
862 return 0;
863 }
864
865 /* lookup if we have other variants in the list */
866 if (sel->num_shaders > 1) {
867 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
868
869 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
870 p = c;
871 c = c->next_variant;
872 }
873
874 if (c) {
875 p->next_variant = c->next_variant;
876 shader = c;
877 }
878 }
879
880 if (unlikely(!shader)) {
881 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
882 shader->selector = sel;
883
884 r = r600_pipe_shader_create(ctx, shader, key);
885 if (unlikely(r)) {
886 R600_ERR("Failed to build shader variant (type=%u) %d\n",
887 sel->type, r);
888 sel->current = NULL;
889 FREE(shader);
890 return r;
891 }
892
893 /* We don't know the value of nr_ps_max_color_exports until we built
894 * at least one variant, so we may need to recompute the key after
895 * building first variant. */
896 if (sel->type == PIPE_SHADER_FRAGMENT &&
897 sel->num_shaders == 0) {
898 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
899 r600_shader_selector_key(ctx, sel, &key);
900 }
901
902 memcpy(&shader->key, &key, sizeof(key));
903 sel->num_shaders++;
904 }
905
906 if (dirty)
907 *dirty = true;
908
909 shader->next_variant = sel->current;
910 sel->current = shader;
911
912 return 0;
913 }
914
r600_create_shader_state_tokens(struct pipe_context * ctx,const void * prog,enum pipe_shader_ir ir,unsigned pipe_shader_type)915 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
916 const void *prog, enum pipe_shader_ir ir,
917 unsigned pipe_shader_type)
918 {
919 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
920
921 sel->type = pipe_shader_type;
922 if (ir == PIPE_SHADER_IR_TGSI) {
923 sel->tokens = tgsi_dup_tokens((const struct tgsi_token *)prog);
924 tgsi_scan_shader(sel->tokens, &sel->info);
925 } else if (ir == PIPE_SHADER_IR_NIR){
926 sel->nir = nir_shader_clone(NULL, (const nir_shader *)prog);
927 nir_tgsi_scan_shader(sel->nir, &sel->info, true);
928 }
929 return sel;
930 }
931
r600_create_shader_state(struct pipe_context * ctx,const struct pipe_shader_state * state,unsigned pipe_shader_type)932 static void *r600_create_shader_state(struct pipe_context *ctx,
933 const struct pipe_shader_state *state,
934 unsigned pipe_shader_type)
935 {
936 int i;
937 struct r600_pipe_shader_selector *sel;
938
939 if (state->type == PIPE_SHADER_IR_TGSI)
940 sel = r600_create_shader_state_tokens(ctx, state->tokens, state->type, pipe_shader_type);
941 else if (state->type == PIPE_SHADER_IR_NIR) {
942 sel = r600_create_shader_state_tokens(ctx, state->ir.nir, state->type, pipe_shader_type);
943 } else
944 assert(0 && "Unknown shader type\n");
945
946 sel->ir_type = state->type;
947 sel->so = state->stream_output;
948
949 switch (pipe_shader_type) {
950 case PIPE_SHADER_GEOMETRY:
951 sel->gs_output_prim =
952 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
953 sel->gs_max_out_vertices =
954 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
955 sel->gs_num_invocations =
956 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
957 break;
958 case PIPE_SHADER_VERTEX:
959 case PIPE_SHADER_TESS_CTRL:
960 sel->lds_patch_outputs_written_mask = 0;
961 sel->lds_outputs_written_mask = 0;
962
963 for (i = 0; i < sel->info.num_outputs; i++) {
964 unsigned name = sel->info.output_semantic_name[i];
965 unsigned index = sel->info.output_semantic_index[i];
966
967 switch (name) {
968 case TGSI_SEMANTIC_TESSINNER:
969 case TGSI_SEMANTIC_TESSOUTER:
970 case TGSI_SEMANTIC_PATCH:
971 sel->lds_patch_outputs_written_mask |=
972 1ull << r600_get_lds_unique_index(name, index);
973 break;
974 default:
975 sel->lds_outputs_written_mask |=
976 1ull << r600_get_lds_unique_index(name, index);
977 }
978 }
979 break;
980 default:
981 break;
982 }
983
984 return sel;
985 }
986
r600_create_ps_state(struct pipe_context * ctx,const struct pipe_shader_state * state)987 static void *r600_create_ps_state(struct pipe_context *ctx,
988 const struct pipe_shader_state *state)
989 {
990 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
991 }
992
r600_create_vs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)993 static void *r600_create_vs_state(struct pipe_context *ctx,
994 const struct pipe_shader_state *state)
995 {
996 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
997 }
998
r600_create_gs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)999 static void *r600_create_gs_state(struct pipe_context *ctx,
1000 const struct pipe_shader_state *state)
1001 {
1002 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
1003 }
1004
r600_create_tcs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1005 static void *r600_create_tcs_state(struct pipe_context *ctx,
1006 const struct pipe_shader_state *state)
1007 {
1008 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
1009 }
1010
r600_create_tes_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1011 static void *r600_create_tes_state(struct pipe_context *ctx,
1012 const struct pipe_shader_state *state)
1013 {
1014 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
1015 }
1016
r600_bind_ps_state(struct pipe_context * ctx,void * state)1017 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
1018 {
1019 struct r600_context *rctx = (struct r600_context *)ctx;
1020
1021 if (!state)
1022 state = rctx->dummy_pixel_shader;
1023
1024 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
1025 }
1026
r600_get_vs_info(struct r600_context * rctx)1027 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1028 {
1029 if (rctx->gs_shader)
1030 return &rctx->gs_shader->info;
1031 else if (rctx->tes_shader)
1032 return &rctx->tes_shader->info;
1033 else if (rctx->vs_shader)
1034 return &rctx->vs_shader->info;
1035 else
1036 return NULL;
1037 }
1038
r600_bind_vs_state(struct pipe_context * ctx,void * state)1039 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1040 {
1041 struct r600_context *rctx = (struct r600_context *)ctx;
1042
1043 if (!state || rctx->vs_shader == state)
1044 return;
1045
1046 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1047 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1048
1049 if (rctx->vs_shader->so.num_outputs)
1050 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1051 }
1052
r600_bind_gs_state(struct pipe_context * ctx,void * state)1053 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1054 {
1055 struct r600_context *rctx = (struct r600_context *)ctx;
1056
1057 if (state == rctx->gs_shader)
1058 return;
1059
1060 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1061 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1062
1063 if (!state)
1064 return;
1065
1066 if (rctx->gs_shader->so.num_outputs)
1067 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1068 }
1069
r600_bind_tcs_state(struct pipe_context * ctx,void * state)1070 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1071 {
1072 struct r600_context *rctx = (struct r600_context *)ctx;
1073
1074 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1075 }
1076
r600_bind_tes_state(struct pipe_context * ctx,void * state)1077 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1078 {
1079 struct r600_context *rctx = (struct r600_context *)ctx;
1080
1081 if (state == rctx->tes_shader)
1082 return;
1083
1084 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1085 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1086
1087 if (!state)
1088 return;
1089
1090 if (rctx->tes_shader->so.num_outputs)
1091 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1092 }
1093
r600_delete_shader_selector(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel)1094 void r600_delete_shader_selector(struct pipe_context *ctx,
1095 struct r600_pipe_shader_selector *sel)
1096 {
1097 struct r600_pipe_shader *p = sel->current, *c;
1098 while (p) {
1099 c = p->next_variant;
1100 r600_pipe_shader_destroy(ctx, p);
1101 free(p);
1102 p = c;
1103 }
1104
1105 if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
1106 free(sel->tokens);
1107 /* We might have converted the TGSI shader to a NIR shader */
1108 if (sel->nir)
1109 ralloc_free(sel->nir);
1110 }
1111 else if (sel->ir_type == PIPE_SHADER_IR_NIR)
1112 ralloc_free(sel->nir);
1113 free(sel);
1114 }
1115
1116
r600_delete_ps_state(struct pipe_context * ctx,void * state)1117 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1118 {
1119 struct r600_context *rctx = (struct r600_context *)ctx;
1120 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1121
1122 if (rctx->ps_shader == sel) {
1123 rctx->ps_shader = NULL;
1124 }
1125
1126 r600_delete_shader_selector(ctx, sel);
1127 }
1128
r600_delete_vs_state(struct pipe_context * ctx,void * state)1129 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1130 {
1131 struct r600_context *rctx = (struct r600_context *)ctx;
1132 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1133
1134 if (rctx->vs_shader == sel) {
1135 rctx->vs_shader = NULL;
1136 }
1137
1138 r600_delete_shader_selector(ctx, sel);
1139 }
1140
1141
r600_delete_gs_state(struct pipe_context * ctx,void * state)1142 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1143 {
1144 struct r600_context *rctx = (struct r600_context *)ctx;
1145 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1146
1147 if (rctx->gs_shader == sel) {
1148 rctx->gs_shader = NULL;
1149 }
1150
1151 r600_delete_shader_selector(ctx, sel);
1152 }
1153
r600_delete_tcs_state(struct pipe_context * ctx,void * state)1154 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1155 {
1156 struct r600_context *rctx = (struct r600_context *)ctx;
1157 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1158
1159 if (rctx->tcs_shader == sel) {
1160 rctx->tcs_shader = NULL;
1161 }
1162
1163 r600_delete_shader_selector(ctx, sel);
1164 }
1165
r600_delete_tes_state(struct pipe_context * ctx,void * state)1166 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1167 {
1168 struct r600_context *rctx = (struct r600_context *)ctx;
1169 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1170
1171 if (rctx->tes_shader == sel) {
1172 rctx->tes_shader = NULL;
1173 }
1174
1175 r600_delete_shader_selector(ctx, sel);
1176 }
1177
r600_constant_buffers_dirty(struct r600_context * rctx,struct r600_constbuf_state * state)1178 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1179 {
1180 if (state->dirty_mask) {
1181 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1182 : util_bitcount(state->dirty_mask)*19;
1183 r600_mark_atom_dirty(rctx, &state->atom);
1184 }
1185 }
1186
r600_set_constant_buffer(struct pipe_context * ctx,enum pipe_shader_type shader,uint index,const struct pipe_constant_buffer * input)1187 static void r600_set_constant_buffer(struct pipe_context *ctx,
1188 enum pipe_shader_type shader, uint index,
1189 const struct pipe_constant_buffer *input)
1190 {
1191 struct r600_context *rctx = (struct r600_context *)ctx;
1192 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1193 struct pipe_constant_buffer *cb;
1194 const uint8_t *ptr;
1195
1196 /* Note that the gallium frontend can unbind constant buffers by
1197 * passing NULL here.
1198 */
1199 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1200 state->enabled_mask &= ~(1 << index);
1201 state->dirty_mask &= ~(1 << index);
1202 pipe_resource_reference(&state->cb[index].buffer, NULL);
1203 return;
1204 }
1205
1206 cb = &state->cb[index];
1207 cb->buffer_size = input->buffer_size;
1208
1209 ptr = input->user_buffer;
1210
1211 if (ptr) {
1212 /* Upload the user buffer. */
1213 if (R600_BIG_ENDIAN) {
1214 uint32_t *tmpPtr;
1215 unsigned i, size = input->buffer_size;
1216
1217 if (!(tmpPtr = malloc(size))) {
1218 R600_ERR("Failed to allocate BE swap buffer.\n");
1219 return;
1220 }
1221
1222 for (i = 0; i < size / 4; ++i) {
1223 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1224 }
1225
1226 u_upload_data(ctx->stream_uploader, 0, size, 256,
1227 tmpPtr, &cb->buffer_offset, &cb->buffer);
1228 free(tmpPtr);
1229 } else {
1230 u_upload_data(ctx->stream_uploader, 0,
1231 input->buffer_size, 256, ptr,
1232 &cb->buffer_offset, &cb->buffer);
1233 }
1234 /* account it in gtt */
1235 rctx->b.gtt += input->buffer_size;
1236 } else {
1237 /* Setup the hw buffer. */
1238 cb->buffer_offset = input->buffer_offset;
1239 pipe_resource_reference(&cb->buffer, input->buffer);
1240 r600_context_add_resource_size(ctx, input->buffer);
1241 }
1242
1243 state->enabled_mask |= 1 << index;
1244 state->dirty_mask |= 1 << index;
1245 r600_constant_buffers_dirty(rctx, state);
1246 }
1247
r600_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)1248 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1249 {
1250 struct r600_context *rctx = (struct r600_context*)pipe;
1251
1252 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1253 return;
1254
1255 rctx->sample_mask.sample_mask = sample_mask;
1256 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1257 }
1258
r600_update_driver_const_buffers(struct r600_context * rctx,bool compute_only)1259 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1260 {
1261 int sh, size;
1262 void *ptr;
1263 struct pipe_constant_buffer cb;
1264 int start, end;
1265
1266 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1267 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1268
1269 for (sh = start; sh < end; sh++) {
1270 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1271 if (!info->vs_ucp_dirty &&
1272 !info->texture_const_dirty &&
1273 !info->ps_sample_pos_dirty &&
1274 !info->tcs_default_levels_dirty &&
1275 !info->cs_block_grid_size_dirty)
1276 continue;
1277
1278 ptr = info->constants;
1279 size = info->alloc_size;
1280 if (info->vs_ucp_dirty) {
1281 assert(sh == PIPE_SHADER_VERTEX);
1282 if (!size) {
1283 ptr = rctx->clip_state.state.ucp;
1284 size = R600_UCP_SIZE;
1285 } else {
1286 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1287 }
1288 info->vs_ucp_dirty = false;
1289 }
1290
1291 else if (info->ps_sample_pos_dirty) {
1292 assert(sh == PIPE_SHADER_FRAGMENT);
1293 if (!size) {
1294 ptr = rctx->sample_positions;
1295 size = R600_UCP_SIZE;
1296 } else {
1297 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1298 }
1299 info->ps_sample_pos_dirty = false;
1300 }
1301
1302 else if (info->cs_block_grid_size_dirty) {
1303 assert(sh == PIPE_SHADER_COMPUTE);
1304 if (!size) {
1305 ptr = rctx->cs_block_grid_sizes;
1306 size = R600_CS_BLOCK_GRID_SIZE;
1307 } else {
1308 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1309 }
1310 info->cs_block_grid_size_dirty = false;
1311 }
1312
1313 else if (info->tcs_default_levels_dirty) {
1314 /*
1315 * We'd only really need this for default tcs shader.
1316 */
1317 assert(sh == PIPE_SHADER_TESS_CTRL);
1318 if (!size) {
1319 ptr = rctx->tess_state;
1320 size = R600_TCS_DEFAULT_LEVELS_SIZE;
1321 } else {
1322 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1323 }
1324 info->tcs_default_levels_dirty = false;
1325 }
1326
1327 if (info->texture_const_dirty) {
1328 assert (ptr);
1329 assert (size);
1330 if (sh == PIPE_SHADER_VERTEX)
1331 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1332 if (sh == PIPE_SHADER_FRAGMENT)
1333 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1334 if (sh == PIPE_SHADER_COMPUTE)
1335 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1336 if (sh == PIPE_SHADER_TESS_CTRL)
1337 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1338 }
1339 info->texture_const_dirty = false;
1340
1341 cb.buffer = NULL;
1342 cb.user_buffer = ptr;
1343 cb.buffer_offset = 0;
1344 cb.buffer_size = size;
1345 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1346 pipe_resource_reference(&cb.buffer, NULL);
1347 }
1348 }
1349
r600_alloc_buf_consts(struct r600_context * rctx,int shader_type,unsigned array_size,uint32_t * base_offset)1350 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1351 unsigned array_size, uint32_t *base_offset)
1352 {
1353 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1354 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1355 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1356 info->alloc_size = array_size + R600_UCP_SIZE;
1357 }
1358 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1359 info->texture_const_dirty = true;
1360 *base_offset = R600_UCP_SIZE;
1361 return info->constants;
1362 }
1363 /*
1364 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1365 * doesn't require full swizzles it does need masking and setting alpha
1366 * to one, so we setup a set of 5 constants with the masks + alpha value
1367 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1368 * then OR the alpha with the value given here.
1369 * We use a 6th constant to store the txq buffer size in
1370 * we use 7th slot for number of cube layers in a cube map array.
1371 */
r600_setup_buffer_constants(struct r600_context * rctx,int shader_type)1372 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1373 {
1374 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1375 int bits;
1376 uint32_t array_size;
1377 int i, j;
1378 uint32_t *constants;
1379 uint32_t base_offset;
1380 if (!samplers->views.dirty_buffer_constants)
1381 return;
1382
1383 samplers->views.dirty_buffer_constants = FALSE;
1384
1385 bits = util_last_bit(samplers->views.enabled_mask);
1386 array_size = bits * 8 * sizeof(uint32_t);
1387
1388 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1389
1390 for (i = 0; i < bits; i++) {
1391 if (samplers->views.enabled_mask & (1 << i)) {
1392 int offset = (base_offset / 4) + i * 8;
1393 const struct util_format_description *desc;
1394 desc = util_format_description(samplers->views.views[i]->base.format);
1395
1396 for (j = 0; j < 4; j++)
1397 if (j < desc->nr_channels)
1398 constants[offset+j] = 0xffffffff;
1399 else
1400 constants[offset+j] = 0x0;
1401 if (desc->nr_channels < 4) {
1402 if (desc->channel[0].pure_integer)
1403 constants[offset+4] = 1;
1404 else
1405 constants[offset+4] = fui(1.0);
1406 } else
1407 constants[offset + 4] = 0;
1408
1409 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1410 util_format_get_blocksize(samplers->views.views[i]->base.format);
1411 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1412 }
1413 }
1414
1415 }
1416
1417 /* On evergreen we store one value
1418 * 1. number of cube layers in a cube map array.
1419 */
eg_setup_buffer_constants(struct r600_context * rctx,int shader_type)1420 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1421 {
1422 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1423 struct r600_image_state *images = NULL;
1424 int bits, sview_bits, img_bits;
1425 uint32_t array_size;
1426 int i;
1427 uint32_t *constants;
1428 uint32_t base_offset;
1429
1430 if (shader_type == PIPE_SHADER_FRAGMENT) {
1431 images = &rctx->fragment_images;
1432 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1433 images = &rctx->compute_images;
1434 }
1435
1436 if (!samplers->views.dirty_buffer_constants &&
1437 !(images && images->dirty_buffer_constants))
1438 return;
1439
1440 if (images)
1441 images->dirty_buffer_constants = FALSE;
1442 samplers->views.dirty_buffer_constants = FALSE;
1443
1444 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1445 if (images)
1446 bits += util_last_bit(images->enabled_mask);
1447 img_bits = bits;
1448
1449 array_size = bits * sizeof(uint32_t);
1450
1451 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1452 &base_offset);
1453
1454 for (i = 0; i < sview_bits; i++) {
1455 if (samplers->views.enabled_mask & (1 << i)) {
1456 uint32_t offset = (base_offset / 4) + i;
1457 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1458 }
1459 }
1460 if (images) {
1461 for (i = sview_bits; i < img_bits; i++) {
1462 int idx = i - sview_bits;
1463 if (images->enabled_mask & (1 << idx)) {
1464 uint32_t offset = (base_offset / 4) + i;
1465 constants[offset] = images->views[idx].base.resource->array_size / 6;
1466 }
1467 }
1468 }
1469 }
1470
1471 /* set sample xy locations as array of fragment shader constants */
r600_set_sample_locations_constant_buffer(struct r600_context * rctx)1472 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1473 {
1474 struct pipe_context *ctx = &rctx->b.b;
1475
1476 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1477 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1478
1479 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1480 for (unsigned i = 0; i < rctx->framebuffer.nr_samples; i++) {
1481 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1482 /* Also fill in center-zeroed positions used for interpolateAtSample */
1483 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1484 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1485 }
1486
1487 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1488 }
1489
update_shader_atom(struct pipe_context * ctx,struct r600_shader_state * state,struct r600_pipe_shader * shader)1490 static void update_shader_atom(struct pipe_context *ctx,
1491 struct r600_shader_state *state,
1492 struct r600_pipe_shader *shader)
1493 {
1494 struct r600_context *rctx = (struct r600_context *)ctx;
1495
1496 state->shader = shader;
1497 if (shader) {
1498 state->atom.num_dw = shader->command_buffer.num_dw;
1499 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1500 } else {
1501 state->atom.num_dw = 0;
1502 }
1503 r600_mark_atom_dirty(rctx, &state->atom);
1504 }
1505
update_gs_block_state(struct r600_context * rctx,unsigned enable)1506 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1507 {
1508 if (rctx->shader_stages.geom_enable != enable) {
1509 rctx->shader_stages.geom_enable = enable;
1510 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1511 }
1512
1513 if (rctx->gs_rings.enable != enable) {
1514 rctx->gs_rings.enable = enable;
1515 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1516
1517 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1518 unsigned size = 0x1C000;
1519 rctx->gs_rings.esgs_ring.buffer =
1520 pipe_buffer_create(rctx->b.b.screen, 0,
1521 PIPE_USAGE_DEFAULT, size);
1522 rctx->gs_rings.esgs_ring.buffer_size = size;
1523
1524 size = 0x4000000;
1525
1526 rctx->gs_rings.gsvs_ring.buffer =
1527 pipe_buffer_create(rctx->b.b.screen, 0,
1528 PIPE_USAGE_DEFAULT, size);
1529 rctx->gs_rings.gsvs_ring.buffer_size = size;
1530 }
1531
1532 if (enable) {
1533 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1534 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1535 if (rctx->tes_shader) {
1536 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1537 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1538 } else {
1539 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1540 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1541 }
1542 } else {
1543 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1544 R600_GS_RING_CONST_BUFFER, NULL);
1545 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1546 R600_GS_RING_CONST_BUFFER, NULL);
1547 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1548 R600_GS_RING_CONST_BUFFER, NULL);
1549 }
1550 }
1551 }
1552
r600_update_clip_state(struct r600_context * rctx,struct r600_pipe_shader * current)1553 static void r600_update_clip_state(struct r600_context *rctx,
1554 struct r600_pipe_shader *current)
1555 {
1556 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1557 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1558 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1559 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1560 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1561 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1562 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1563 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1564 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1565 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1566 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1567 }
1568 }
1569
r600_generate_fixed_func_tcs(struct r600_context * rctx)1570 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1571 {
1572 struct ureg_src const0, const1;
1573 struct ureg_dst tessouter, tessinner;
1574 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1575
1576 if (!ureg)
1577 return; /* if we get here, we're screwed */
1578
1579 assert(!rctx->fixed_func_tcs_shader);
1580
1581 ureg_DECL_constant2D(ureg, 0, 1, R600_BUFFER_INFO_CONST_BUFFER);
1582 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1583 R600_BUFFER_INFO_CONST_BUFFER);
1584 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1585 R600_BUFFER_INFO_CONST_BUFFER);
1586
1587 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1588 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1589
1590 ureg_MOV(ureg, tessouter, const0);
1591 ureg_MOV(ureg, tessinner, const1);
1592 ureg_END(ureg);
1593
1594 rctx->fixed_func_tcs_shader =
1595 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1596 }
1597
r600_update_compressed_resource_state(struct r600_context * rctx,bool compute_only)1598 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1599 {
1600 unsigned i;
1601 unsigned counter;
1602
1603 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1604 if (counter != rctx->b.last_compressed_colortex_counter) {
1605 rctx->b.last_compressed_colortex_counter = counter;
1606
1607 if (compute_only) {
1608 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1609 } else {
1610 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1611 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1612 }
1613 }
1614 if (!compute_only)
1615 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1616 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1617 }
1618
1619 /* Decompress textures if needed. */
1620 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1621 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1622
1623 if (compute_only)
1624 if (i != PIPE_SHADER_COMPUTE)
1625 continue;
1626 if (views->compressed_depthtex_mask) {
1627 r600_decompress_depth_textures(rctx, views);
1628 }
1629 if (views->compressed_colortex_mask) {
1630 r600_decompress_color_textures(rctx, views);
1631 }
1632 }
1633
1634 {
1635 struct r600_image_state *istate;
1636
1637 if (!compute_only) {
1638 istate = &rctx->fragment_images;
1639 if (istate->compressed_depthtex_mask)
1640 r600_decompress_depth_images(rctx, istate);
1641 if (istate->compressed_colortex_mask)
1642 r600_decompress_color_images(rctx, istate);
1643 }
1644
1645 istate = &rctx->compute_images;
1646 if (istate->compressed_depthtex_mask)
1647 r600_decompress_depth_images(rctx, istate);
1648 if (istate->compressed_colortex_mask)
1649 r600_decompress_color_images(rctx, istate);
1650 }
1651 }
1652
1653 /* update MEM_SCRATCH buffers if needed */
r600_setup_scratch_area_for_shader(struct r600_context * rctx,struct r600_pipe_shader * shader,struct r600_scratch_buffer * scratch,unsigned ring_base_reg,unsigned item_size_reg,unsigned ring_size_reg)1654 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
1655 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
1656 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg)
1657 {
1658 unsigned num_ses = rctx->screen->b.info.max_se;
1659 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
1660 unsigned nthreads = 128;
1661
1662 unsigned itemsize = shader->scratch_space_needed * 4;
1663 unsigned size = align(itemsize * nthreads * num_pipes * num_ses * 4, 256);
1664
1665 if (scratch->dirty ||
1666 unlikely(shader->scratch_space_needed != scratch->item_size ||
1667 size > scratch->size)) {
1668 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1669
1670 scratch->dirty = false;
1671
1672 if (size > scratch->size) {
1673 // Release prior one if any
1674 if (scratch->buffer) {
1675 pipe_resource_reference((struct pipe_resource**)&scratch->buffer, NULL);
1676 }
1677
1678 scratch->buffer = (struct r600_resource *)pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1679 PIPE_USAGE_DEFAULT, size);
1680 if (scratch->buffer) {
1681 scratch->size = size;
1682 }
1683 }
1684
1685 scratch->item_size = shader->scratch_space_needed;
1686
1687 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1688 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1689 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1690
1691 // multi-SE chips need programming per SE
1692 for (unsigned se = 0; se < num_ses; se++) {
1693 struct r600_resource *rbuffer = scratch->buffer;
1694 unsigned size_per_se = size / num_ses;
1695
1696 // Direct to particular SE
1697 if (num_ses > 1) {
1698 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1699 S_0802C_INSTANCE_INDEX(0) |
1700 S_0802C_SE_INDEX(se) |
1701 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1702 S_0802C_SE_BROADCAST_WRITES(0));
1703 }
1704
1705 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1706 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1707 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1708 RADEON_USAGE_READWRITE,
1709 RADEON_PRIO_SCRATCH_BUFFER));
1710 radeon_set_context_reg(cs, item_size_reg, itemsize);
1711 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1712 }
1713
1714 // Restore broadcast mode
1715 if (num_ses > 1) {
1716 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1717 S_0802C_INSTANCE_INDEX(0) |
1718 S_0802C_SE_INDEX(0) |
1719 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1720 S_0802C_SE_BROADCAST_WRITES(1));
1721 }
1722
1723 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1724 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1725 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1726 }
1727 }
1728
r600_setup_scratch_buffers(struct r600_context * rctx)1729 void r600_setup_scratch_buffers(struct r600_context *rctx) {
1730 static const struct {
1731 unsigned ring_base;
1732 unsigned item_size;
1733 unsigned ring_size;
1734 } regs[R600_NUM_HW_STAGES] = {
1735 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
1736 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
1737 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
1738 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }
1739 };
1740
1741 for (unsigned i = 0; i < R600_NUM_HW_STAGES; i++) {
1742 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
1743
1744 if (stage && unlikely(stage->scratch_space_needed)) {
1745 r600_setup_scratch_area_for_shader(rctx, stage,
1746 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
1747 }
1748 }
1749 }
1750
1751 #define SELECT_SHADER_OR_FAIL(x) do { \
1752 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1753 if (unlikely(!rctx->x##_shader->current)) \
1754 return false; \
1755 } while(0)
1756
1757 #define UPDATE_SHADER(hw, sw) do { \
1758 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1759 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1760 } while(0)
1761
1762 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1763 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1764 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1765 clip_so_current = rctx->sw##_shader->current; \
1766 } \
1767 } while(0)
1768
1769 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1770 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1771 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1772 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1773 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1774 } \
1775 } while(0)
1776
1777 #define SET_NULL_SHADER(hw) do { \
1778 if (rctx->hw_shader_stages[(hw)].shader) \
1779 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1780 } while (0)
1781
r600_update_derived_state(struct r600_context * rctx)1782 static bool r600_update_derived_state(struct r600_context *rctx)
1783 {
1784 struct pipe_context * ctx = (struct pipe_context*)rctx;
1785 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1786 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1787 bool blend_disable;
1788 bool need_buf_const;
1789 struct r600_pipe_shader *clip_so_current = NULL;
1790
1791 if (!rctx->blitter->running)
1792 r600_update_compressed_resource_state(rctx, false);
1793
1794 SELECT_SHADER_OR_FAIL(ps);
1795
1796 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1797
1798 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1799
1800 if (rctx->gs_shader)
1801 SELECT_SHADER_OR_FAIL(gs);
1802
1803 /* Hull Shader */
1804 if (rctx->tcs_shader) {
1805 SELECT_SHADER_OR_FAIL(tcs);
1806
1807 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1808 } else if (rctx->tes_shader) {
1809 if (!rctx->fixed_func_tcs_shader) {
1810 r600_generate_fixed_func_tcs(rctx);
1811 if (!rctx->fixed_func_tcs_shader)
1812 return false;
1813
1814 }
1815 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1816
1817 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1818 } else
1819 SET_NULL_SHADER(EG_HW_STAGE_HS);
1820
1821 if (rctx->tes_shader) {
1822 SELECT_SHADER_OR_FAIL(tes);
1823 }
1824
1825 SELECT_SHADER_OR_FAIL(vs);
1826
1827 if (rctx->gs_shader) {
1828 if (!rctx->shader_stages.geom_enable) {
1829 rctx->shader_stages.geom_enable = true;
1830 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1831 }
1832
1833 /* gs_shader provides GS and VS (copy shader) */
1834 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1835
1836 /* vs_shader is used as ES */
1837
1838 if (rctx->tes_shader) {
1839 /* VS goes to LS, TES goes to ES */
1840 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1841 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1842 } else {
1843 /* vs_shader is used as ES */
1844 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1845 SET_NULL_SHADER(EG_HW_STAGE_LS);
1846 }
1847 } else {
1848 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1849 SET_NULL_SHADER(R600_HW_STAGE_GS);
1850 SET_NULL_SHADER(R600_HW_STAGE_ES);
1851 rctx->shader_stages.geom_enable = false;
1852 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1853 }
1854
1855 if (rctx->tes_shader) {
1856 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1857 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1858 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1859 } else {
1860 SET_NULL_SHADER(EG_HW_STAGE_LS);
1861 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1862 }
1863 }
1864
1865 /*
1866 * XXX: I believe there's some fatal flaw in the dirty state logic when
1867 * enabling/disabling tes.
1868 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1869 * it will therefore overwrite the VS slots. If it now gets disabled,
1870 * the VS needs to rebind all buffer/resource/sampler slots - not only
1871 * has TES overwritten the corresponding slots, but when the VS was
1872 * operating as LS the things with correpsonding dirty bits got bound
1873 * to LS slots and won't reflect what is dirty as VS stage even if the
1874 * TES didn't overwrite it. The story for re-enabled TES is similar.
1875 * In any case, we're not allowed to submit any TES state when
1876 * TES is disabled (the gallium frontend may not do this but this looks
1877 * like an optimization to me, not something which can be relied on).
1878 */
1879
1880 /* Update clip misc state. */
1881 if (clip_so_current) {
1882 r600_update_clip_state(rctx, clip_so_current);
1883 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1884 }
1885
1886 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1887 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1888 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1889
1890 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
1891 rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
1892 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1893 rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
1894 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1895 }
1896
1897 if (rctx->b.chip_class <= R700) {
1898 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1899
1900 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1901 rctx->cb_misc_state.multiwrite = multiwrite;
1902 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1903 }
1904 }
1905
1906 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1907 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1908 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1909
1910 if (rctx->b.chip_class >= EVERGREEN)
1911 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1912 else
1913 r600_update_ps_state(ctx, rctx->ps_shader->current);
1914 }
1915
1916 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1917 }
1918 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1919
1920 if (rctx->b.chip_class >= EVERGREEN) {
1921 evergreen_update_db_shader_control(rctx);
1922 } else {
1923 r600_update_db_shader_control(rctx);
1924 }
1925
1926 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
1927 if (rctx->b.chip_class >= EVERGREEN) {
1928 evergreen_setup_scratch_buffers(rctx);
1929 } else {
1930 r600_setup_scratch_buffers(rctx);
1931 }
1932
1933 /* on R600 we stuff masks + txq info into one constant buffer */
1934 /* on evergreen we only need a txq info one */
1935 if (rctx->ps_shader) {
1936 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1937 if (need_buf_const) {
1938 if (rctx->b.chip_class < EVERGREEN)
1939 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1940 else
1941 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1942 }
1943 }
1944
1945 if (rctx->vs_shader) {
1946 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1947 if (need_buf_const) {
1948 if (rctx->b.chip_class < EVERGREEN)
1949 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1950 else
1951 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1952 }
1953 }
1954
1955 if (rctx->gs_shader) {
1956 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1957 if (need_buf_const) {
1958 if (rctx->b.chip_class < EVERGREEN)
1959 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1960 else
1961 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1962 }
1963 }
1964
1965 if (rctx->tes_shader) {
1966 assert(rctx->b.chip_class >= EVERGREEN);
1967 need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers ||
1968 rctx->tes_shader->current->shader.has_txq_cube_array_z_comp;
1969 if (need_buf_const) {
1970 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_EVAL);
1971 }
1972 if (rctx->tcs_shader) {
1973 need_buf_const = rctx->tcs_shader->current->shader.uses_tex_buffers ||
1974 rctx->tcs_shader->current->shader.has_txq_cube_array_z_comp;
1975 if (need_buf_const) {
1976 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_CTRL);
1977 }
1978 }
1979 }
1980
1981 r600_update_driver_const_buffers(rctx, false);
1982
1983 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1984 if (!r600_adjust_gprs(rctx)) {
1985 /* discard rendering */
1986 return false;
1987 }
1988 }
1989
1990 if (rctx->b.chip_class == EVERGREEN) {
1991 if (!evergreen_adjust_gprs(rctx)) {
1992 /* discard rendering */
1993 return false;
1994 }
1995 }
1996
1997 blend_disable = (rctx->dual_src_blend &&
1998 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1999
2000 if (blend_disable != rctx->force_blend_disable) {
2001 rctx->force_blend_disable = blend_disable;
2002 r600_bind_blend_state_internal(rctx,
2003 rctx->blend_state.cso,
2004 blend_disable);
2005 }
2006
2007 return true;
2008 }
2009
r600_emit_clip_misc_state(struct r600_context * rctx,struct r600_atom * atom)2010 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2011 {
2012 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2013 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
2014
2015 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2016 state->pa_cl_clip_cntl |
2017 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
2018 S_028810_CLIP_DISABLE(state->clip_disable));
2019 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2020 state->pa_cl_vs_out_cntl |
2021 (state->clip_plane_enable & state->clip_dist_write) |
2022 (state->cull_dist_write << 8));
2023 /* reuse needs to be set off if we write oViewport */
2024 if (rctx->b.chip_class >= EVERGREEN)
2025 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2026 S_028AB4_REUSE_OFF(state->vs_out_viewport));
2027 }
2028
2029 /* rast_prim is the primitive type after GS. */
r600_emit_rasterizer_prim_state(struct r600_context * rctx)2030 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
2031 {
2032 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2033 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
2034
2035 /* Skip this if not rendering lines. */
2036 if (rast_prim != PIPE_PRIM_LINES &&
2037 rast_prim != PIPE_PRIM_LINE_LOOP &&
2038 rast_prim != PIPE_PRIM_LINE_STRIP &&
2039 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
2040 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
2041 return;
2042
2043 if (rast_prim == rctx->last_rast_prim)
2044 return;
2045
2046 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2047 * reset the stipple pattern at each packet (line strips, line loops).
2048 */
2049 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
2050 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
2051 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
2052 rctx->last_rast_prim = rast_prim;
2053 }
2054
r600_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info)2055 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
2056 {
2057 struct r600_context *rctx = (struct r600_context *)ctx;
2058 struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource;
2059 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2060 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
2061 bool has_user_indices = info->has_user_indices;
2062 uint64_t mask;
2063 unsigned num_patches, dirty_tex_counter, index_offset = 0;
2064 unsigned index_size = info->index_size;
2065 int index_bias;
2066 struct r600_shader_atomic combined_atomics[8];
2067 uint8_t atomic_used_mask = 0;
2068
2069 if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
2070 return;
2071 }
2072
2073 if (unlikely(!rctx->vs_shader)) {
2074 assert(0);
2075 return;
2076 }
2077 if (unlikely(!rctx->ps_shader &&
2078 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
2079 assert(0);
2080 return;
2081 }
2082
2083 /* make sure that the gfx ring is only one active */
2084 if (radeon_emitted(rctx->b.dma.cs, 0)) {
2085 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2086 }
2087
2088 if (rctx->cmd_buf_is_compute) {
2089 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2090 rctx->cmd_buf_is_compute = false;
2091 }
2092
2093 /* Re-emit the framebuffer state if needed. */
2094 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
2095 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
2096 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
2097 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
2098 rctx->framebuffer.do_update_surf_dirtiness = true;
2099 }
2100
2101 if (rctx->gs_shader) {
2102 /* Determine whether the GS triangle strip adjacency fix should
2103 * be applied. Rotate every other triangle if
2104 * - triangle strips with adjacency are fed to the GS and
2105 * - primitive restart is disabled (the rotation doesn't help
2106 * when the restart occurs after an odd number of triangles).
2107 */
2108 bool gs_tri_strip_adj_fix =
2109 !rctx->tes_shader &&
2110 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
2111 !info->primitive_restart;
2112 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
2113 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2114 }
2115 if (!r600_update_derived_state(rctx)) {
2116 /* useless to render because current rendering command
2117 * can't be achieved
2118 */
2119 return;
2120 }
2121
2122 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
2123 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
2124 : info->mode;
2125
2126 if (rctx->b.chip_class >= EVERGREEN) {
2127 evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask);
2128 }
2129
2130 if (index_size) {
2131 index_offset += info->start * index_size;
2132
2133 /* Translate 8-bit indices to 16-bit. */
2134 if (unlikely(index_size == 1)) {
2135 struct pipe_resource *out_buffer = NULL;
2136 unsigned out_offset;
2137 void *ptr;
2138 unsigned start, count;
2139
2140 if (likely(!info->indirect)) {
2141 start = 0;
2142 count = info->count;
2143 }
2144 else {
2145 /* Have to get start/count from indirect buffer, slow path ahead... */
2146 struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
2147 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
2148 PIPE_MAP_READ);
2149 if (data) {
2150 data += info->indirect->offset / sizeof(unsigned);
2151 start = data[2] * index_size;
2152 count = data[0];
2153 }
2154 else {
2155 start = 0;
2156 count = 0;
2157 }
2158 }
2159
2160 u_upload_alloc(ctx->stream_uploader, start, count * 2,
2161 256, &out_offset, &out_buffer, &ptr);
2162 if (unlikely(!ptr))
2163 return;
2164
2165 util_shorten_ubyte_elts_to_userptr(
2166 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2167
2168 indexbuf = out_buffer;
2169 index_offset = out_offset;
2170 index_size = 2;
2171 has_user_indices = false;
2172 }
2173
2174 /* Upload the index buffer.
2175 * The upload is skipped for small index counts on little-endian machines
2176 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2177 * Indirect draws never use immediate indices.
2178 * Note: Instanced rendering in combination with immediate indices hangs. */
2179 if (has_user_indices && (R600_BIG_ENDIAN || info->indirect ||
2180 info->instance_count > 1 ||
2181 info->count*index_size > 20)) {
2182 indexbuf = NULL;
2183 u_upload_data(ctx->stream_uploader, 0,
2184 info->count * index_size, 256,
2185 info->index.user, &index_offset, &indexbuf);
2186 has_user_indices = false;
2187 }
2188 index_bias = info->index_bias;
2189 } else {
2190 index_bias = info->start;
2191 }
2192
2193 /* Set the index offset and primitive restart. */
2194 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2195 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index ||
2196 rctx->vgt_state.vgt_indx_offset != index_bias ||
2197 (rctx->vgt_state.last_draw_was_indirect && !info->indirect)) {
2198 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2199 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2200 rctx->vgt_state.vgt_indx_offset = index_bias;
2201 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2202 }
2203
2204 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2205 if (rctx->b.chip_class == R600) {
2206 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2207 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2208 }
2209
2210 if (rctx->b.chip_class >= EVERGREEN)
2211 evergreen_setup_tess_constants(rctx, info, &num_patches);
2212
2213 /* Emit states. */
2214 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE, util_bitcount(atomic_used_mask));
2215 r600_flush_emit(rctx);
2216
2217 mask = rctx->dirty_atoms;
2218 while (mask != 0) {
2219 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2220 }
2221
2222 if (rctx->b.chip_class >= EVERGREEN) {
2223 evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask);
2224 }
2225
2226 if (rctx->b.chip_class == CAYMAN) {
2227 /* Copied from radeonsi. */
2228 unsigned primgroup_size = 128; /* recommended without a GS */
2229 bool ia_switch_on_eop = false;
2230 bool partial_vs_wave = false;
2231
2232 if (rctx->gs_shader)
2233 primgroup_size = 64; /* recommended with a GS */
2234
2235 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2236 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2237 ia_switch_on_eop = true;
2238 }
2239
2240 if (r600_get_strmout_en(&rctx->b))
2241 partial_vs_wave = true;
2242
2243 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2244 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2245 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2246 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2247 }
2248
2249 if (rctx->b.chip_class >= EVERGREEN) {
2250 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2251 num_patches);
2252
2253 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2254 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2255 }
2256
2257 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2258 * even though it should have no effect on those. */
2259 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
2260 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2261 unsigned prim = info->mode;
2262
2263 if (rctx->gs_shader) {
2264 prim = rctx->gs_shader->gs_output_prim;
2265 }
2266 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2267
2268 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2269 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2270 info->mode == R600_PRIM_RECTANGLE_LIST) {
2271 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2272 }
2273 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2274 }
2275
2276 /* Update start instance. */
2277 if (!info->indirect && rctx->last_start_instance != info->start_instance) {
2278 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2279 rctx->last_start_instance = info->start_instance;
2280 }
2281
2282 /* Update the primitive type. */
2283 if (rctx->last_primitive_type != info->mode) {
2284 r600_emit_rasterizer_prim_state(rctx);
2285 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2286 r600_conv_pipe_prim(info->mode));
2287
2288 rctx->last_primitive_type = info->mode;
2289 }
2290
2291 /* Draw packets. */
2292 if (likely(!info->indirect)) {
2293 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2294 radeon_emit(cs, info->instance_count);
2295 } else {
2296 uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
2297 assert(rctx->b.chip_class >= EVERGREEN);
2298
2299 // Invalidate so non-indirect draw calls reset this state
2300 rctx->vgt_state.last_draw_was_indirect = true;
2301 rctx->last_start_instance = -1;
2302
2303 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2304 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2305 radeon_emit(cs, va);
2306 radeon_emit(cs, (va >> 32UL) & 0xFF);
2307
2308 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2309 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2310 (struct r600_resource*)info->indirect->buffer,
2311 RADEON_USAGE_READ,
2312 RADEON_PRIO_DRAW_INDIRECT));
2313 }
2314
2315 if (index_size) {
2316 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2317 radeon_emit(cs, index_size == 4 ?
2318 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2319 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2320
2321 if (has_user_indices) {
2322 unsigned size_bytes = info->count*index_size;
2323 unsigned size_dw = align(size_bytes, 4) / 4;
2324 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2325 radeon_emit(cs, info->count);
2326 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2327 radeon_emit_array(cs, info->index.user, size_dw);
2328 } else {
2329 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2330
2331 if (likely(!info->indirect)) {
2332 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2333 radeon_emit(cs, va);
2334 radeon_emit(cs, (va >> 32UL) & 0xFF);
2335 radeon_emit(cs, info->count);
2336 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2337 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2338 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2339 (struct r600_resource*)indexbuf,
2340 RADEON_USAGE_READ,
2341 RADEON_PRIO_INDEX_BUFFER));
2342 }
2343 else {
2344 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2345
2346 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2347 radeon_emit(cs, va);
2348 radeon_emit(cs, (va >> 32UL) & 0xFF);
2349
2350 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2351 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2352 (struct r600_resource*)indexbuf,
2353 RADEON_USAGE_READ,
2354 RADEON_PRIO_INDEX_BUFFER));
2355
2356 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2357 radeon_emit(cs, max_size);
2358
2359 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2360 radeon_emit(cs, info->indirect->offset);
2361 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2362 }
2363 }
2364 } else {
2365 if (unlikely(info->count_from_stream_output)) {
2366 struct r600_so_target *t = (struct r600_so_target*)info->count_from_stream_output;
2367 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2368
2369 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2370
2371 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2372 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2373 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2374 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2375 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2376 radeon_emit(cs, 0); /* unused */
2377
2378 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2379 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2380 t->buf_filled_size, RADEON_USAGE_READ,
2381 RADEON_PRIO_SO_FILLED_SIZE));
2382 }
2383
2384 if (likely(!info->indirect)) {
2385 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2386 radeon_emit(cs, info->count);
2387 }
2388 else {
2389 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2390 radeon_emit(cs, info->indirect->offset);
2391 }
2392 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2393 (info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
2394 }
2395
2396 /* SMX returns CONTEXT_DONE too early workaround */
2397 if (rctx->b.family == CHIP_R600 ||
2398 rctx->b.family == CHIP_RV610 ||
2399 rctx->b.family == CHIP_RV630 ||
2400 rctx->b.family == CHIP_RV635) {
2401 /* if we have gs shader or streamout
2402 we need to do a wait idle after every draw */
2403 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2404 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2405 }
2406 }
2407
2408 /* ES ring rolling over at EOP - workaround */
2409 if (rctx->b.chip_class == R600) {
2410 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2411 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2412 }
2413
2414
2415 if (rctx->b.chip_class >= EVERGREEN)
2416 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2417
2418 if (rctx->trace_buf)
2419 eg_trace_emit(rctx);
2420
2421 if (rctx->framebuffer.do_update_surf_dirtiness) {
2422 /* Set the depth buffer as dirty. */
2423 if (rctx->framebuffer.state.zsbuf) {
2424 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2425 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2426
2427 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2428
2429 if (rtex->surface.has_stencil)
2430 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2431 }
2432 if (rctx->framebuffer.compressed_cb_mask) {
2433 struct pipe_surface *surf;
2434 struct r600_texture *rtex;
2435 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2436
2437 do {
2438 unsigned i = u_bit_scan(&mask);
2439 surf = rctx->framebuffer.state.cbufs[i];
2440 rtex = (struct r600_texture*)surf->texture;
2441
2442 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2443
2444 } while (mask);
2445 }
2446 rctx->framebuffer.do_update_surf_dirtiness = false;
2447 }
2448
2449 if (index_size && indexbuf != info->index.resource)
2450 pipe_resource_reference(&indexbuf, NULL);
2451 rctx->b.num_draw_calls++;
2452 }
2453
r600_translate_stencil_op(int s_op)2454 uint32_t r600_translate_stencil_op(int s_op)
2455 {
2456 switch (s_op) {
2457 case PIPE_STENCIL_OP_KEEP:
2458 return V_028800_STENCIL_KEEP;
2459 case PIPE_STENCIL_OP_ZERO:
2460 return V_028800_STENCIL_ZERO;
2461 case PIPE_STENCIL_OP_REPLACE:
2462 return V_028800_STENCIL_REPLACE;
2463 case PIPE_STENCIL_OP_INCR:
2464 return V_028800_STENCIL_INCR;
2465 case PIPE_STENCIL_OP_DECR:
2466 return V_028800_STENCIL_DECR;
2467 case PIPE_STENCIL_OP_INCR_WRAP:
2468 return V_028800_STENCIL_INCR_WRAP;
2469 case PIPE_STENCIL_OP_DECR_WRAP:
2470 return V_028800_STENCIL_DECR_WRAP;
2471 case PIPE_STENCIL_OP_INVERT:
2472 return V_028800_STENCIL_INVERT;
2473 default:
2474 R600_ERR("Unknown stencil op %d", s_op);
2475 assert(0);
2476 break;
2477 }
2478 return 0;
2479 }
2480
r600_translate_fill(uint32_t func)2481 uint32_t r600_translate_fill(uint32_t func)
2482 {
2483 switch(func) {
2484 case PIPE_POLYGON_MODE_FILL:
2485 return 2;
2486 case PIPE_POLYGON_MODE_LINE:
2487 return 1;
2488 case PIPE_POLYGON_MODE_POINT:
2489 return 0;
2490 default:
2491 assert(0);
2492 return 0;
2493 }
2494 }
2495
r600_tex_wrap(unsigned wrap)2496 unsigned r600_tex_wrap(unsigned wrap)
2497 {
2498 switch (wrap) {
2499 default:
2500 case PIPE_TEX_WRAP_REPEAT:
2501 return V_03C000_SQ_TEX_WRAP;
2502 case PIPE_TEX_WRAP_CLAMP:
2503 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2504 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2505 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2506 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2507 return V_03C000_SQ_TEX_CLAMP_BORDER;
2508 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2509 return V_03C000_SQ_TEX_MIRROR;
2510 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2511 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2512 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2513 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2514 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2515 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2516 }
2517 }
2518
r600_tex_mipfilter(unsigned filter)2519 unsigned r600_tex_mipfilter(unsigned filter)
2520 {
2521 switch (filter) {
2522 case PIPE_TEX_MIPFILTER_NEAREST:
2523 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2524 case PIPE_TEX_MIPFILTER_LINEAR:
2525 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2526 default:
2527 case PIPE_TEX_MIPFILTER_NONE:
2528 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2529 }
2530 }
2531
r600_tex_compare(unsigned compare)2532 unsigned r600_tex_compare(unsigned compare)
2533 {
2534 switch (compare) {
2535 default:
2536 case PIPE_FUNC_NEVER:
2537 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2538 case PIPE_FUNC_LESS:
2539 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2540 case PIPE_FUNC_EQUAL:
2541 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2542 case PIPE_FUNC_LEQUAL:
2543 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2544 case PIPE_FUNC_GREATER:
2545 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2546 case PIPE_FUNC_NOTEQUAL:
2547 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2548 case PIPE_FUNC_GEQUAL:
2549 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2550 case PIPE_FUNC_ALWAYS:
2551 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2552 }
2553 }
2554
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)2555 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2556 {
2557 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2558 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2559 (linear_filter &&
2560 (wrap == PIPE_TEX_WRAP_CLAMP ||
2561 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2562 }
2563
sampler_state_needs_border_color(const struct pipe_sampler_state * state)2564 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2565 {
2566 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2567 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2568
2569 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2570 state->border_color.ui[2] || state->border_color.ui[3]) &&
2571 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2572 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2573 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2574 }
2575
r600_emit_shader(struct r600_context * rctx,struct r600_atom * a)2576 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2577 {
2578
2579 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2580 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2581
2582 if (!shader)
2583 return;
2584
2585 r600_emit_command_buffer(cs, &shader->command_buffer);
2586 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2587 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2588 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
2589 }
2590
r600_get_swizzle_combined(const unsigned char * swizzle_format,const unsigned char * swizzle_view,boolean vtx)2591 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2592 const unsigned char *swizzle_view,
2593 boolean vtx)
2594 {
2595 unsigned i;
2596 unsigned char swizzle[4];
2597 unsigned result = 0;
2598 const uint32_t tex_swizzle_shift[4] = {
2599 16, 19, 22, 25,
2600 };
2601 const uint32_t vtx_swizzle_shift[4] = {
2602 3, 6, 9, 12,
2603 };
2604 const uint32_t swizzle_bit[4] = {
2605 0, 1, 2, 3,
2606 };
2607 const uint32_t *swizzle_shift = tex_swizzle_shift;
2608
2609 if (vtx)
2610 swizzle_shift = vtx_swizzle_shift;
2611
2612 if (swizzle_view) {
2613 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2614 } else {
2615 memcpy(swizzle, swizzle_format, 4);
2616 }
2617
2618 /* Get swizzle. */
2619 for (i = 0; i < 4; i++) {
2620 switch (swizzle[i]) {
2621 case PIPE_SWIZZLE_Y:
2622 result |= swizzle_bit[1] << swizzle_shift[i];
2623 break;
2624 case PIPE_SWIZZLE_Z:
2625 result |= swizzle_bit[2] << swizzle_shift[i];
2626 break;
2627 case PIPE_SWIZZLE_W:
2628 result |= swizzle_bit[3] << swizzle_shift[i];
2629 break;
2630 case PIPE_SWIZZLE_0:
2631 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2632 break;
2633 case PIPE_SWIZZLE_1:
2634 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2635 break;
2636 default: /* PIPE_SWIZZLE_X */
2637 result |= swizzle_bit[0] << swizzle_shift[i];
2638 }
2639 }
2640 return result;
2641 }
2642
2643 /* texture format translate */
r600_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const unsigned char * swizzle_view,uint32_t * word4_p,uint32_t * yuv_format_p,bool do_endian_swap)2644 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2645 enum pipe_format format,
2646 const unsigned char *swizzle_view,
2647 uint32_t *word4_p, uint32_t *yuv_format_p,
2648 bool do_endian_swap)
2649 {
2650 struct r600_screen *rscreen = (struct r600_screen *)screen;
2651 uint32_t result = 0, word4 = 0, yuv_format = 0;
2652 const struct util_format_description *desc;
2653 boolean uniform = TRUE;
2654 bool is_srgb_valid = FALSE;
2655 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2656 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2657 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2658 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2659 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2660
2661 int i;
2662 const uint32_t sign_bit[4] = {
2663 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2664 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2665 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2666 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2667 };
2668
2669 /* Need to replace the specified texture formats in case of big-endian.
2670 * These formats are formats that have channels with number of bits
2671 * not divisible by 8.
2672 * Mesa conversion functions don't swap bits for those formats, and because
2673 * we transmit this over a serial bus to the GPU (PCIe), the
2674 * bit-endianess is important!!!
2675 * In case we have an "opposite" format, just use that for the swizzling
2676 * information. If we don't have such an "opposite" format, we need
2677 * to use a fixed swizzle info instead (see below)
2678 */
2679 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2680 format = PIPE_FORMAT_A4R4_UNORM;
2681
2682 desc = util_format_description(format);
2683 if (!desc)
2684 goto out_unknown;
2685
2686 /* Depth and stencil swizzling is handled separately. */
2687 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2688 /* Need to check for specific texture formats that don't have
2689 * an "opposite" format we can use. For those formats, we directly
2690 * specify the swizzling, which is the LE swizzling as defined in
2691 * u_format.csv
2692 */
2693 if (do_endian_swap) {
2694 if (format == PIPE_FORMAT_L4A4_UNORM)
2695 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2696 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2697 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2698 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2699 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2700 else
2701 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2702 } else {
2703 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2704 }
2705 }
2706
2707 /* Colorspace (return non-RGB formats directly). */
2708 switch (desc->colorspace) {
2709 /* Depth stencil formats */
2710 case UTIL_FORMAT_COLORSPACE_ZS:
2711 switch (format) {
2712 /* Depth sampler formats. */
2713 case PIPE_FORMAT_Z16_UNORM:
2714 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2715 result = FMT_16;
2716 goto out_word4;
2717 case PIPE_FORMAT_Z24X8_UNORM:
2718 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2719 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2720 result = FMT_8_24;
2721 goto out_word4;
2722 case PIPE_FORMAT_X8Z24_UNORM:
2723 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2724 if (rscreen->b.chip_class < EVERGREEN)
2725 goto out_unknown;
2726 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2727 result = FMT_24_8;
2728 goto out_word4;
2729 case PIPE_FORMAT_Z32_FLOAT:
2730 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2731 result = FMT_32_FLOAT;
2732 goto out_word4;
2733 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2734 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2735 result = FMT_X24_8_32_FLOAT;
2736 goto out_word4;
2737 /* Stencil sampler formats. */
2738 case PIPE_FORMAT_S8_UINT:
2739 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2740 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2741 result = FMT_8;
2742 goto out_word4;
2743 case PIPE_FORMAT_X24S8_UINT:
2744 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2745 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2746 result = FMT_8_24;
2747 goto out_word4;
2748 case PIPE_FORMAT_S8X24_UINT:
2749 if (rscreen->b.chip_class < EVERGREEN)
2750 goto out_unknown;
2751 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2752 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2753 result = FMT_24_8;
2754 goto out_word4;
2755 case PIPE_FORMAT_X32_S8X24_UINT:
2756 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2757 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2758 result = FMT_X24_8_32_FLOAT;
2759 goto out_word4;
2760 default:
2761 goto out_unknown;
2762 }
2763
2764 case UTIL_FORMAT_COLORSPACE_YUV:
2765 yuv_format |= (1 << 30);
2766 switch (format) {
2767 case PIPE_FORMAT_UYVY:
2768 case PIPE_FORMAT_YUYV:
2769 default:
2770 break;
2771 }
2772 goto out_unknown; /* XXX */
2773
2774 case UTIL_FORMAT_COLORSPACE_SRGB:
2775 word4 |= S_038010_FORCE_DEGAMMA(1);
2776 break;
2777
2778 default:
2779 break;
2780 }
2781
2782 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2783 switch (format) {
2784 case PIPE_FORMAT_RGTC1_SNORM:
2785 case PIPE_FORMAT_LATC1_SNORM:
2786 word4 |= sign_bit[0];
2787 /* fallthrough */
2788 case PIPE_FORMAT_RGTC1_UNORM:
2789 case PIPE_FORMAT_LATC1_UNORM:
2790 result = FMT_BC4;
2791 goto out_word4;
2792 case PIPE_FORMAT_RGTC2_SNORM:
2793 case PIPE_FORMAT_LATC2_SNORM:
2794 word4 |= sign_bit[0] | sign_bit[1];
2795 /* fallthrough */
2796 case PIPE_FORMAT_RGTC2_UNORM:
2797 case PIPE_FORMAT_LATC2_UNORM:
2798 result = FMT_BC5;
2799 goto out_word4;
2800 default:
2801 goto out_unknown;
2802 }
2803 }
2804
2805 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2806 switch (format) {
2807 case PIPE_FORMAT_DXT1_RGB:
2808 case PIPE_FORMAT_DXT1_RGBA:
2809 case PIPE_FORMAT_DXT1_SRGB:
2810 case PIPE_FORMAT_DXT1_SRGBA:
2811 result = FMT_BC1;
2812 is_srgb_valid = TRUE;
2813 goto out_word4;
2814 case PIPE_FORMAT_DXT3_RGBA:
2815 case PIPE_FORMAT_DXT3_SRGBA:
2816 result = FMT_BC2;
2817 is_srgb_valid = TRUE;
2818 goto out_word4;
2819 case PIPE_FORMAT_DXT5_RGBA:
2820 case PIPE_FORMAT_DXT5_SRGBA:
2821 result = FMT_BC3;
2822 is_srgb_valid = TRUE;
2823 goto out_word4;
2824 default:
2825 goto out_unknown;
2826 }
2827 }
2828
2829 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2830 if (rscreen->b.chip_class < EVERGREEN)
2831 goto out_unknown;
2832
2833 switch (format) {
2834 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2835 case PIPE_FORMAT_BPTC_SRGBA:
2836 result = FMT_BC7;
2837 is_srgb_valid = TRUE;
2838 goto out_word4;
2839 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2840 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2841 /* fall through */
2842 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2843 result = FMT_BC6;
2844 goto out_word4;
2845 default:
2846 goto out_unknown;
2847 }
2848 }
2849
2850 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2851 switch (format) {
2852 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2853 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2854 result = FMT_GB_GR;
2855 goto out_word4;
2856 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2857 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2858 result = FMT_BG_RG;
2859 goto out_word4;
2860 default:
2861 goto out_unknown;
2862 }
2863 }
2864
2865 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2866 result = FMT_5_9_9_9_SHAREDEXP;
2867 goto out_word4;
2868 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2869 result = FMT_10_11_11_FLOAT;
2870 goto out_word4;
2871 }
2872
2873
2874 for (i = 0; i < desc->nr_channels; i++) {
2875 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2876 word4 |= sign_bit[i];
2877 }
2878 }
2879
2880 /* R8G8Bx_SNORM - XXX CxV8U8 */
2881
2882 /* See whether the components are of the same size. */
2883 for (i = 1; i < desc->nr_channels; i++) {
2884 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2885 }
2886
2887 /* Non-uniform formats. */
2888 if (!uniform) {
2889 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2890 desc->channel[0].pure_integer)
2891 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2892 switch(desc->nr_channels) {
2893 case 3:
2894 if (desc->channel[0].size == 5 &&
2895 desc->channel[1].size == 6 &&
2896 desc->channel[2].size == 5) {
2897 result = FMT_5_6_5;
2898 goto out_word4;
2899 }
2900 goto out_unknown;
2901 case 4:
2902 if (desc->channel[0].size == 5 &&
2903 desc->channel[1].size == 5 &&
2904 desc->channel[2].size == 5 &&
2905 desc->channel[3].size == 1) {
2906 result = FMT_1_5_5_5;
2907 goto out_word4;
2908 }
2909 if (desc->channel[0].size == 10 &&
2910 desc->channel[1].size == 10 &&
2911 desc->channel[2].size == 10 &&
2912 desc->channel[3].size == 2) {
2913 result = FMT_2_10_10_10;
2914 goto out_word4;
2915 }
2916 goto out_unknown;
2917 }
2918 goto out_unknown;
2919 }
2920
2921 /* Find the first non-VOID channel. */
2922 for (i = 0; i < 4; i++) {
2923 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2924 break;
2925 }
2926 }
2927
2928 if (i == 4)
2929 goto out_unknown;
2930
2931 /* uniform formats */
2932 switch (desc->channel[i].type) {
2933 case UTIL_FORMAT_TYPE_UNSIGNED:
2934 case UTIL_FORMAT_TYPE_SIGNED:
2935 #if 0
2936 if (!desc->channel[i].normalized &&
2937 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2938 goto out_unknown;
2939 }
2940 #endif
2941 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2942 desc->channel[i].pure_integer)
2943 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2944
2945 switch (desc->channel[i].size) {
2946 case 4:
2947 switch (desc->nr_channels) {
2948 case 2:
2949 result = FMT_4_4;
2950 goto out_word4;
2951 case 4:
2952 result = FMT_4_4_4_4;
2953 goto out_word4;
2954 }
2955 goto out_unknown;
2956 case 8:
2957 switch (desc->nr_channels) {
2958 case 1:
2959 result = FMT_8;
2960 is_srgb_valid = TRUE;
2961 goto out_word4;
2962 case 2:
2963 result = FMT_8_8;
2964 goto out_word4;
2965 case 4:
2966 result = FMT_8_8_8_8;
2967 is_srgb_valid = TRUE;
2968 goto out_word4;
2969 }
2970 goto out_unknown;
2971 case 16:
2972 switch (desc->nr_channels) {
2973 case 1:
2974 result = FMT_16;
2975 goto out_word4;
2976 case 2:
2977 result = FMT_16_16;
2978 goto out_word4;
2979 case 4:
2980 result = FMT_16_16_16_16;
2981 goto out_word4;
2982 }
2983 goto out_unknown;
2984 case 32:
2985 switch (desc->nr_channels) {
2986 case 1:
2987 result = FMT_32;
2988 goto out_word4;
2989 case 2:
2990 result = FMT_32_32;
2991 goto out_word4;
2992 case 4:
2993 result = FMT_32_32_32_32;
2994 goto out_word4;
2995 }
2996 }
2997 goto out_unknown;
2998
2999 case UTIL_FORMAT_TYPE_FLOAT:
3000 switch (desc->channel[i].size) {
3001 case 16:
3002 switch (desc->nr_channels) {
3003 case 1:
3004 result = FMT_16_FLOAT;
3005 goto out_word4;
3006 case 2:
3007 result = FMT_16_16_FLOAT;
3008 goto out_word4;
3009 case 4:
3010 result = FMT_16_16_16_16_FLOAT;
3011 goto out_word4;
3012 }
3013 goto out_unknown;
3014 case 32:
3015 switch (desc->nr_channels) {
3016 case 1:
3017 result = FMT_32_FLOAT;
3018 goto out_word4;
3019 case 2:
3020 result = FMT_32_32_FLOAT;
3021 goto out_word4;
3022 case 4:
3023 result = FMT_32_32_32_32_FLOAT;
3024 goto out_word4;
3025 }
3026 }
3027 goto out_unknown;
3028 }
3029
3030 out_word4:
3031
3032 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
3033 return ~0;
3034 if (word4_p)
3035 *word4_p = word4;
3036 if (yuv_format_p)
3037 *yuv_format_p = yuv_format;
3038 return result;
3039 out_unknown:
3040 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3041 return ~0;
3042 }
3043
r600_translate_colorformat(enum chip_class chip,enum pipe_format format,bool do_endian_swap)3044 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
3045 bool do_endian_swap)
3046 {
3047 const struct util_format_description *desc = util_format_description(format);
3048 int channel = util_format_get_first_non_void_channel(format);
3049 bool is_float;
3050 if (!desc)
3051 return ~0U;
3052
3053 #define HAS_SIZE(x,y,z,w) \
3054 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3055 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3056
3057 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
3058 return V_0280A0_COLOR_10_11_11_FLOAT;
3059
3060 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
3061 channel == -1)
3062 return ~0U;
3063
3064 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
3065
3066 switch (desc->nr_channels) {
3067 case 1:
3068 switch (desc->channel[0].size) {
3069 case 8:
3070 return V_0280A0_COLOR_8;
3071 case 16:
3072 if (is_float)
3073 return V_0280A0_COLOR_16_FLOAT;
3074 else
3075 return V_0280A0_COLOR_16;
3076 case 32:
3077 if (is_float)
3078 return V_0280A0_COLOR_32_FLOAT;
3079 else
3080 return V_0280A0_COLOR_32;
3081 }
3082 break;
3083 case 2:
3084 if (desc->channel[0].size == desc->channel[1].size) {
3085 switch (desc->channel[0].size) {
3086 case 4:
3087 if (chip <= R700)
3088 return V_0280A0_COLOR_4_4;
3089 else
3090 return ~0U; /* removed on Evergreen */
3091 case 8:
3092 return V_0280A0_COLOR_8_8;
3093 case 16:
3094 if (is_float)
3095 return V_0280A0_COLOR_16_16_FLOAT;
3096 else
3097 return V_0280A0_COLOR_16_16;
3098 case 32:
3099 if (is_float)
3100 return V_0280A0_COLOR_32_32_FLOAT;
3101 else
3102 return V_0280A0_COLOR_32_32;
3103 }
3104 } else if (HAS_SIZE(8,24,0,0)) {
3105 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
3106 } else if (HAS_SIZE(24,8,0,0)) {
3107 return V_0280A0_COLOR_8_24;
3108 }
3109 break;
3110 case 3:
3111 if (HAS_SIZE(5,6,5,0)) {
3112 return V_0280A0_COLOR_5_6_5;
3113 } else if (HAS_SIZE(32,8,24,0)) {
3114 return V_0280A0_COLOR_X24_8_32_FLOAT;
3115 }
3116 break;
3117 case 4:
3118 if (desc->channel[0].size == desc->channel[1].size &&
3119 desc->channel[0].size == desc->channel[2].size &&
3120 desc->channel[0].size == desc->channel[3].size) {
3121 switch (desc->channel[0].size) {
3122 case 4:
3123 return V_0280A0_COLOR_4_4_4_4;
3124 case 8:
3125 return V_0280A0_COLOR_8_8_8_8;
3126 case 16:
3127 if (is_float)
3128 return V_0280A0_COLOR_16_16_16_16_FLOAT;
3129 else
3130 return V_0280A0_COLOR_16_16_16_16;
3131 case 32:
3132 if (is_float)
3133 return V_0280A0_COLOR_32_32_32_32_FLOAT;
3134 else
3135 return V_0280A0_COLOR_32_32_32_32;
3136 }
3137 } else if (HAS_SIZE(5,5,5,1)) {
3138 return V_0280A0_COLOR_1_5_5_5;
3139 } else if (HAS_SIZE(10,10,10,2)) {
3140 return V_0280A0_COLOR_2_10_10_10;
3141 }
3142 break;
3143 }
3144 return ~0U;
3145 }
3146
r600_colorformat_endian_swap(uint32_t colorformat,bool do_endian_swap)3147 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
3148 {
3149 if (R600_BIG_ENDIAN) {
3150 switch(colorformat) {
3151 /* 8-bit buffers. */
3152 case V_0280A0_COLOR_4_4:
3153 case V_0280A0_COLOR_8:
3154 return ENDIAN_NONE;
3155
3156 /* 16-bit buffers. */
3157 case V_0280A0_COLOR_8_8:
3158 /*
3159 * No need to do endian swaps on array formats,
3160 * as mesa<-->pipe formats conversion take into account
3161 * the endianess
3162 */
3163 return ENDIAN_NONE;
3164
3165 case V_0280A0_COLOR_5_6_5:
3166 case V_0280A0_COLOR_1_5_5_5:
3167 case V_0280A0_COLOR_4_4_4_4:
3168 case V_0280A0_COLOR_16:
3169 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
3170
3171 /* 32-bit buffers. */
3172 case V_0280A0_COLOR_8_8_8_8:
3173 /*
3174 * No need to do endian swaps on array formats,
3175 * as mesa<-->pipe formats conversion take into account
3176 * the endianess
3177 */
3178 return ENDIAN_NONE;
3179
3180 case V_0280A0_COLOR_2_10_10_10:
3181 case V_0280A0_COLOR_8_24:
3182 case V_0280A0_COLOR_24_8:
3183 case V_0280A0_COLOR_32_FLOAT:
3184 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3185
3186 case V_0280A0_COLOR_16_16_FLOAT:
3187 case V_0280A0_COLOR_16_16:
3188 return ENDIAN_8IN16;
3189
3190 /* 64-bit buffers. */
3191 case V_0280A0_COLOR_16_16_16_16:
3192 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3193 return ENDIAN_8IN16;
3194
3195 case V_0280A0_COLOR_32_32_FLOAT:
3196 case V_0280A0_COLOR_32_32:
3197 case V_0280A0_COLOR_X24_8_32_FLOAT:
3198 return ENDIAN_8IN32;
3199
3200 /* 128-bit buffers. */
3201 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3202 case V_0280A0_COLOR_32_32_32_32:
3203 return ENDIAN_8IN32;
3204 default:
3205 return ENDIAN_NONE; /* Unsupported. */
3206 }
3207 } else {
3208 return ENDIAN_NONE;
3209 }
3210 }
3211
r600_invalidate_buffer(struct pipe_context * ctx,struct pipe_resource * buf)3212 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3213 {
3214 struct r600_context *rctx = (struct r600_context*)ctx;
3215 struct r600_resource *rbuffer = r600_resource(buf);
3216 unsigned i, shader, mask;
3217 struct r600_pipe_sampler_view *view;
3218
3219 /* Reallocate the buffer in the same pipe_resource. */
3220 r600_alloc_resource(&rctx->screen->b, rbuffer);
3221
3222 /* We changed the buffer, now we need to bind it where the old one was bound. */
3223 /* Vertex buffers. */
3224 mask = rctx->vertex_buffer_state.enabled_mask;
3225 while (mask) {
3226 i = u_bit_scan(&mask);
3227 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3228 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3229 r600_vertex_buffers_dirty(rctx);
3230 }
3231 }
3232 /* Streamout buffers. */
3233 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3234 if (rctx->b.streamout.targets[i] &&
3235 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3236 if (rctx->b.streamout.begin_emitted) {
3237 r600_emit_streamout_end(&rctx->b);
3238 }
3239 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3240 r600_streamout_buffers_dirty(&rctx->b);
3241 }
3242 }
3243
3244 /* Constant buffers. */
3245 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3246 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3247 bool found = false;
3248 uint32_t mask = state->enabled_mask;
3249
3250 while (mask) {
3251 unsigned i = u_bit_scan(&mask);
3252 if (state->cb[i].buffer == &rbuffer->b.b) {
3253 found = true;
3254 state->dirty_mask |= 1 << i;
3255 }
3256 }
3257 if (found) {
3258 r600_constant_buffers_dirty(rctx, state);
3259 }
3260 }
3261
3262 /* Texture buffer objects - update the virtual addresses in descriptors. */
3263 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3264 if (view->base.texture == &rbuffer->b.b) {
3265 uint64_t offset = view->base.u.buf.offset;
3266 uint64_t va = rbuffer->gpu_address + offset;
3267
3268 view->tex_resource_words[0] = va;
3269 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3270 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3271 }
3272 }
3273 /* Texture buffer objects - make bindings dirty if needed. */
3274 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3275 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3276 bool found = false;
3277 uint32_t mask = state->enabled_mask;
3278
3279 while (mask) {
3280 unsigned i = u_bit_scan(&mask);
3281 if (state->views[i]->base.texture == &rbuffer->b.b) {
3282 found = true;
3283 state->dirty_mask |= 1 << i;
3284 }
3285 }
3286 if (found) {
3287 r600_sampler_views_dirty(rctx, state);
3288 }
3289 }
3290
3291 /* SSBOs */
3292 struct r600_image_state *istate = &rctx->fragment_buffers;
3293 {
3294 uint32_t mask = istate->enabled_mask;
3295 bool found = false;
3296 while (mask) {
3297 unsigned i = u_bit_scan(&mask);
3298 if (istate->views[i].base.resource == &rbuffer->b.b) {
3299 found = true;
3300 istate->dirty_mask |= 1 << i;
3301 }
3302 }
3303 if (found) {
3304 r600_mark_atom_dirty(rctx, &istate->atom);
3305 }
3306 }
3307
3308 }
3309
r600_set_active_query_state(struct pipe_context * ctx,bool enable)3310 static void r600_set_active_query_state(struct pipe_context *ctx, bool enable)
3311 {
3312 struct r600_context *rctx = (struct r600_context*)ctx;
3313
3314 /* Pipeline stat & streamout queries. */
3315 if (enable) {
3316 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3317 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3318 } else {
3319 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3320 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3321 }
3322
3323 /* Occlusion queries. */
3324 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3325 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3326 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3327 }
3328 }
3329
r600_need_gfx_cs_space(struct pipe_context * ctx,unsigned num_dw,bool include_draw_vbo)3330 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3331 bool include_draw_vbo)
3332 {
3333 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo, 0);
3334 }
3335
3336 /* keep this at the end of this file, please */
r600_init_common_state_functions(struct r600_context * rctx)3337 void r600_init_common_state_functions(struct r600_context *rctx)
3338 {
3339 rctx->b.b.create_fs_state = r600_create_ps_state;
3340 rctx->b.b.create_vs_state = r600_create_vs_state;
3341 rctx->b.b.create_gs_state = r600_create_gs_state;
3342 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3343 rctx->b.b.create_tes_state = r600_create_tes_state;
3344 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3345 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3346 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3347 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3348 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3349 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3350 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3351 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3352 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3353 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3354 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3355 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3356 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3357 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3358 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3359 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3360 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3361 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3362 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3363 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3364 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3365 rctx->b.b.set_blend_color = r600_set_blend_color;
3366 rctx->b.b.set_clip_state = r600_set_clip_state;
3367 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3368 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3369 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3370 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3371 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3372 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3373 rctx->b.b.memory_barrier = r600_memory_barrier;
3374 rctx->b.b.texture_barrier = r600_texture_barrier;
3375 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3376 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3377
3378 rctx->b.b.draw_vbo = r600_draw_vbo;
3379 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3380 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3381 }
3382