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Searched defs:reg1 (Results 1 – 25 of 61) sorted by relevance

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/external/libvpx/vpx_ports/
Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
24 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
27 #define MMI_ADDI(reg1, reg2, immediate) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
36 #define MMI_SRL(reg1, reg2, shift) \ argument
39 #define MMI_SLL(reg1, reg2, shift) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
53 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
56 #define MMI_ADDI(reg1, reg2, immediate) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
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/external/vixl/src/aarch64/
Dregisters-aarch64.cc173 bool AreAliased(const CPURegister& reg1, in AreAliased()
224 bool AreSameSizeAndType(const CPURegister& reg1, in AreSameSizeAndType()
244 bool AreEven(const CPURegister& reg1, in AreEven()
264 bool AreConsecutive(const CPURegister& reg1, in AreConsecutive()
294 bool AreSameFormat(const CPURegister& reg1, in AreSameFormat()
306 bool AreSameLaneSize(const CPURegister& reg1, in AreSameLaneSize()
/external/arm-trusted-firmware/plat/mediatek/common/drivers/gpio/
Dmtgpio_common.c93 uintptr_t reg1; in mt_gpio_set_spec_pull_pupd() local
118 uintptr_t reg1; in mt_gpio_set_pull_pu_pd() local
157 uintptr_t reg1; in mt_gpio_get_spec_pull_pupd() local
185 uintptr_t reg1; in mt_gpio_get_pull_pu_pd() local
/external/libvpx/vp8/encoder/loongarch/
Dencodeopt_lsx.c18 __m128i reg0, reg1, reg2, reg3, error; in vp8_block_error_lsx() local
43 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, error; in vp8_mbblock_error_lsx() local
/external/libabigail/tests/data/test-abidiff-exit/
Dtest-decl-enum-v0.c4 void reg1(const enum embodied_enum * foo) { (void)foo; } in reg1() function
Dtest-decl-enum-v1.c4 void reg1(const enum embodied_enum * foo) { (void)foo; } in reg1() function
Dtest-decl-struct-v1.c4 void reg1(const struct embodied * foo) { (void)foo; } in reg1() function
Dtest-decl-struct-v0.c4 void reg1(const struct embodied * foo) { (void)foo; } in reg1() function
Dtest-member-size-v0.cc25 void reg1(S*, T*, T*) { } in reg1() function
Dtest-member-size-v1.cc26 void reg1(S*, T*, T*) { } in reg1() function
/external/libprotobuf-mutator/examples/libfuzzer/
Dlibfuzzer_example.cc28 static PostProcessor<libfuzzer_example::Msg> reg1 = { variable
Dlibfuzzer_bin_example.cc28 static PostProcessor<libfuzzer_example::Msg> reg1 = { variable
/external/libvpx/vpx_dsp/loongarch/
Dsubtract_lsx.c20 __m128i reg0, reg1; in sub_blk_4x4_lsx() local
51 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_8x8_lsx() local
102 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_16x16_lsx() local
214 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_32x32_lsx() local
281 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_64x64_lsx() local
Dtxfm_macros_lsx.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
Didct32x32_lsx.c93 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
185 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
319 __m128i reg0, reg1, reg2, reg3; in idct_butterfly_transpose_store() local
450 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
545 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
/external/libvpx/vpx_dsp/mips/
Didct32x32_msa.c45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
129 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
355 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
435 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
/external/libyuv/files/source/
Drow_lsx.cc165 __m128i reg0, reg1, reg2, reg3; in ARGB4444ToARGBRow_LSX() local
201 __m128i reg0, reg1, reg2; in ARGB1555ToARGBRow_LSX() local
249 __m128i reg0, reg1, dst0, dst1, dst2, dst3; in RGB565ToARGBRow_LSX() local
353 __m128i reg0, reg1, reg2, dst0; in ARGB1555ToYRow_LSX() local
404 __m128i reg0, reg1, reg2, reg3, dst0; in ARGB1555ToUVRow_LSX() local
464 __m128i reg0, reg1, dst0; in RGB565ToYRow_LSX() local
513 __m128i reg0, reg1, reg2, reg3, dst0; in RGB565ToUVRow_LSX() local
569 __m128i reg0, reg1, dst0; in RGB24ToYRow_LSX() local
655 __m128i reg0, reg1, dst0; in RAWToYRow_LSX() local
922 __m128i reg0, reg1; in ARGBToYJRow_LSX() local
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Drow_lasx.cc1068 __m256i reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_LASX() local
1181 __m256i reg0, reg1, reg2, reg3, reg4, reg5; in ARGBAttenuateRow_LASX() local
1305 __m256i reg0, reg1, reg2, dst0, dst1; in ARGBGrayRow_LASX() local
1333 __m256i reg0, reg1, spb, spg, spr; in ARGBSepiaRow_LASX() local
1378 __m256i reg0, reg1, reg2, reg3; in ARGB4444ToARGBRow_LASX() local
1410 __m256i reg0, reg1, reg2, reg3; in ARGB1555ToARGBRow_LASX() local
1460 __m256i reg0, reg1, reg2, reg3, dst0, dst1, dst2, dst3; in RGB565ToARGBRow_LASX() local
1507 __m256i reg0, reg1, reg2, reg3; in RGB24ToARGBRow_LASX() local
1545 __m256i tmp0, tmp1, tmp2, reg0, reg1, reg2, reg3; in RAWToARGBRow_LASX() local
1587 __m256i reg0, reg1, reg2, dst0; in ARGB1555ToYRow_LASX() local
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Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
Dscale_lsx.cc83 __m128i reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_LSX() local
141 __m128i reg0, reg1, dst0; in ScaleARGBRowDownEvenBox_LSX() local
279 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, dst0; in ScaleRowDown4Box_LSX() local
347 __m128i reg0, reg1, reg2, reg3; in ScaleRowDown38_2_Box_LSX() local
387 __m128i reg0, reg1, reg2, reg3, dst0; in ScaleRowDown38_3_Box_LSX() local
454 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleFilterCols_LSX() local
545 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_LSX() local
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
567 v8u16 reg0, reg1; in ScaleFilterCols_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
Drow_msa.cc515 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
601 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
640 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
803 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
855 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1125 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1199 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1279 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1347 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local
1415 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
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/external/libvpx/third_party/libyuv/source/
Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
567 v8u16 reg0, reg1; in ScaleFilterCols_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
/external/capstone/arch/X86/
DX86Mapping.c2694 x86_reg reg1, reg2; member
3023 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, e… in X86_insn_reg_intel2()
3044 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enu… in X86_insn_reg_att2()

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