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1 /*
2  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT_SPM_INTERNAL_H
8 #define MT_SPM_INTERNAL_H
9 
10 #include "mt_spm.h"
11 
12 /**************************************
13  * Config and Parameter
14  **************************************/
15 #define POWER_ON_VAL0_DEF	0x0000F100
16 #define POWER_ON_VAL1_DEF	0x80015860
17 #define PCM_WDT_TIMEOUT		(30 * 32768)	/* 30s */
18 #define PCM_TIMER_MAX		(0xffffffff - PCM_WDT_TIMEOUT)
19 
20 /**************************************
21  * Define and Declare
22  **************************************/
23 /* PCM_PWR_IO_EN */
24 #define PCM_PWRIO_EN_R0		(1U << 0)
25 #define PCM_PWRIO_EN_R7		(1U << 7)
26 #define PCM_RF_SYNC_R0		(1U << 16)
27 #define PCM_RF_SYNC_R6		(1U << 22)
28 #define PCM_RF_SYNC_R7		(1U << 23)
29 
30 /* SPM_SWINT */
31 #define PCM_SW_INT0		(1U << 0)
32 #define PCM_SW_INT1		(1U << 1)
33 #define PCM_SW_INT2		(1U << 2)
34 #define PCM_SW_INT3		(1U << 3)
35 #define PCM_SW_INT4		(1U << 4)
36 #define PCM_SW_INT5		(1U << 5)
37 #define PCM_SW_INT6		(1U << 6)
38 #define PCM_SW_INT7		(1U << 7)
39 #define PCM_SW_INT8		(1U << 8)
40 #define PCM_SW_INT9		(1U << 9)
41 #define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
42 				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
43 				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
44 				 PCM_SW_INT0)
45 
46 /* SPM_AP_STANDBY_CON */
47 #define WFI_OP_AND		1
48 #define WFI_OP_OR		0
49 
50 /* SPM_IRQ_MASK */
51 #define ISRM_TWAM		(1U << 2)
52 #define ISRM_PCM_RETURN		(1U << 3)
53 #define ISRM_RET_IRQ0		(1U << 8)
54 #define ISRM_RET_IRQ1		(1U << 9)
55 #define ISRM_RET_IRQ2		(1U << 10)
56 #define ISRM_RET_IRQ3		(1U << 11)
57 #define ISRM_RET_IRQ4		(1U << 12)
58 #define ISRM_RET_IRQ5		(1U << 13)
59 #define ISRM_RET_IRQ6		(1U << 14)
60 #define ISRM_RET_IRQ7		(1U << 15)
61 #define ISRM_RET_IRQ8		(1U << 16)
62 #define ISRM_RET_IRQ9		(1U << 17)
63 #define ISRM_RET_IRQ_AUX	((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
64 				 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
65 				 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
66 				 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
67 				 (ISRM_RET_IRQ1))
68 #define ISRM_ALL_EXC_TWAM	(ISRM_RET_IRQ_AUX)
69 #define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
70 
71 /* SPM_IRQ_STA */
72 #define ISRS_TWAM		(1U << 2)
73 #define ISRS_PCM_RETURN		(1U << 3)
74 #define ISRC_TWAM		ISRS_TWAM
75 #define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
76 #define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
77 
78 /* SPM_WAKEUP_MISC */
79 #define WAKE_MISC_GIC_WAKEUP             0x3FF
80 #define WAKE_MISC_DVFSRC_IRQ	         DVFSRC_IRQ_LSB
81 #define WAKE_MISC_REG_CPU_WAKEUP         SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
82 #define WAKE_MISC_PCM_TIMER_EVENT        PCM_TIMER_EVENT_LSB
83 #define WAKE_MISC_PMIC_OUT_B		 ((1U << 19) | (1U << 20))
84 #define WAKE_MISC_TWAM_IRQ_B             TWAM_IRQ_B_LSB
85 #define WAKE_MISC_PMSR_IRQ_B_SET0        PMSR_IRQ_B_SET0_LSB
86 #define WAKE_MISC_PMSR_IRQ_B_SET1        PMSR_IRQ_B_SET1_LSB
87 #define WAKE_MISC_PMSR_IRQ_B_SET2        PMSR_IRQ_B_SET2_LSB
88 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   SPM_ACK_CHK_WAKEUP_0_LSB
89 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 SPM_ACK_CHK_WAKEUP_1_LSB
90 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 SPM_ACK_CHK_WAKEUP_2_LSB
91 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 SPM_ACK_CHK_WAKEUP_3_LSB
92 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
93 #define WAKE_MISC_PMIC_IRQ_ACK           PMIC_IRQ_ACK_LSB
94 #define WAKE_MISC_PMIC_SCP_IRQ           PMIC_SCP_IRQ_LSB
95 
96 /* ABORT MASK for DEBUG FOORTPRINT */
97 #define DEBUG_ABORT_MASK				\
98 	(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC |	\
99 	 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
100 
101 #define DEBUG_ABORT_MASK_1					\
102 	(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT |			\
103 	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT |		\
104 	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT |	\
105 	 SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT |		\
106 	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT |		\
107 	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT |		\
108 	 SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
109 
110 #define MCUPM_MBOX_WAKEUP_CPU		0x0C55FD10
111 
112 struct pwr_ctrl {
113 	uint32_t pcm_flags;
114 	uint32_t pcm_flags_cust;
115 	uint32_t pcm_flags_cust_set;
116 	uint32_t pcm_flags_cust_clr;
117 	uint32_t pcm_flags1;
118 	uint32_t pcm_flags1_cust;
119 	uint32_t pcm_flags1_cust_set;
120 	uint32_t pcm_flags1_cust_clr;
121 	uint32_t timer_val;
122 	uint32_t timer_val_cust;
123 	uint32_t timer_val_ramp_en;
124 	uint32_t timer_val_ramp_en_sec;
125 	uint32_t wake_src;
126 	uint32_t wake_src_cust;
127 	uint8_t wdt_disable;
128 
129 	/* SPM_AP_STANDBY_CON */
130 	uint8_t reg_wfi_op;
131 	uint8_t reg_wfi_type;
132 	uint8_t reg_mp0_cputop_idle_mask;
133 	uint8_t reg_mp1_cputop_idle_mask;
134 	uint8_t reg_mcusys_idle_mask;
135 	uint8_t reg_md_apsrc_1_sel;
136 	uint8_t reg_md_apsrc_0_sel;
137 	uint8_t reg_conn_apsrc_sel;
138 
139 	/* SPM_SRC_REQ */
140 	uint8_t reg_spm_apsrc_req;
141 	uint8_t reg_spm_f26m_req;
142 	uint8_t reg_spm_infra_req;
143 	uint8_t reg_spm_vrf18_req;
144 	uint8_t reg_spm_ddr_en_req;
145 	uint8_t reg_spm_dvfs_req;
146 	uint8_t reg_spm_sw_mailbox_req;
147 	uint8_t reg_spm_sspm_mailbox_req;
148 	uint8_t reg_spm_adsp_mailbox_req;
149 	uint8_t reg_spm_scp_mailbox_req;
150 
151 	/* SPM_SRC_MASK */
152 	uint8_t reg_sspm_srcclkena_0_mask_b;
153 	uint8_t reg_sspm_infra_req_0_mask_b;
154 	uint8_t reg_sspm_apsrc_req_0_mask_b;
155 	uint8_t reg_sspm_vrf18_req_0_mask_b;
156 	uint8_t reg_sspm_ddr_en_0_mask_b;
157 	uint8_t reg_scp_srcclkena_mask_b;
158 	uint8_t reg_scp_infra_req_mask_b;
159 	uint8_t reg_scp_apsrc_req_mask_b;
160 	uint8_t reg_scp_vrf18_req_mask_b;
161 	uint8_t reg_scp_ddr_en_mask_b;
162 	uint8_t reg_audio_dsp_srcclkena_mask_b;
163 	uint8_t reg_audio_dsp_infra_req_mask_b;
164 	uint8_t reg_audio_dsp_apsrc_req_mask_b;
165 	uint8_t reg_audio_dsp_vrf18_req_mask_b;
166 	uint8_t reg_audio_dsp_ddr_en_mask_b;
167 	uint8_t reg_apu_srcclkena_mask_b;
168 	uint8_t reg_apu_infra_req_mask_b;
169 	uint8_t reg_apu_apsrc_req_mask_b;
170 	uint8_t reg_apu_vrf18_req_mask_b;
171 	uint8_t reg_apu_ddr_en_mask_b;
172 	uint8_t reg_cpueb_srcclkena_mask_b;
173 	uint8_t reg_cpueb_infra_req_mask_b;
174 	uint8_t reg_cpueb_apsrc_req_mask_b;
175 	uint8_t reg_cpueb_vrf18_req_mask_b;
176 	uint8_t reg_cpueb_ddr_en_mask_b;
177 	uint8_t reg_bak_psri_srcclkena_mask_b;
178 	uint8_t reg_bak_psri_infra_req_mask_b;
179 	uint8_t reg_bak_psri_apsrc_req_mask_b;
180 	uint8_t reg_bak_psri_vrf18_req_mask_b;
181 	uint8_t reg_bak_psri_ddr_en_mask_b;
182 
183 	/* SPM_SRC2_MASK */
184 	uint8_t reg_msdc0_srcclkena_mask_b;
185 	uint8_t reg_msdc0_infra_req_mask_b;
186 	uint8_t reg_msdc0_apsrc_req_mask_b;
187 	uint8_t reg_msdc0_vrf18_req_mask_b;
188 	uint8_t reg_msdc0_ddr_en_mask_b;
189 	uint8_t reg_msdc1_srcclkena_mask_b;
190 	uint8_t reg_msdc1_infra_req_mask_b;
191 	uint8_t reg_msdc1_apsrc_req_mask_b;
192 	uint8_t reg_msdc1_vrf18_req_mask_b;
193 	uint8_t reg_msdc1_ddr_en_mask_b;
194 	uint8_t reg_msdc2_srcclkena_mask_b;
195 	uint8_t reg_msdc2_infra_req_mask_b;
196 	uint8_t reg_msdc2_apsrc_req_mask_b;
197 	uint8_t reg_msdc2_vrf18_req_mask_b;
198 	uint8_t reg_msdc2_ddr_en_mask_b;
199 	uint8_t reg_ufs_srcclkena_mask_b;
200 	uint8_t reg_ufs_infra_req_mask_b;
201 	uint8_t reg_ufs_apsrc_req_mask_b;
202 	uint8_t reg_ufs_vrf18_req_mask_b;
203 	uint8_t reg_ufs_ddr_en_mask_b;
204 	uint8_t reg_usb_srcclkena_mask_b;
205 	uint8_t reg_usb_infra_req_mask_b;
206 	uint8_t reg_usb_apsrc_req_mask_b;
207 	uint8_t reg_usb_vrf18_req_mask_b;
208 	uint8_t reg_usb_ddr_en_mask_b;
209 	uint8_t reg_pextp_p0_srcclkena_mask_b;
210 	uint8_t reg_pextp_p0_infra_req_mask_b;
211 	uint8_t reg_pextp_p0_apsrc_req_mask_b;
212 	uint8_t reg_pextp_p0_vrf18_req_mask_b;
213 	uint8_t reg_pextp_p0_ddr_en_mask_b;
214 
215 	/* SPM_SRC3_MASK */
216 	uint8_t reg_pextp_p1_srcclkena_mask_b;
217 	uint8_t reg_pextp_p1_infra_req_mask_b;
218 	uint8_t reg_pextp_p1_apsrc_req_mask_b;
219 	uint8_t reg_pextp_p1_vrf18_req_mask_b;
220 	uint8_t reg_pextp_p1_ddr_en_mask_b;
221 	uint8_t reg_gce0_infra_req_mask_b;
222 	uint8_t reg_gce0_apsrc_req_mask_b;
223 	uint8_t reg_gce0_vrf18_req_mask_b;
224 	uint8_t reg_gce0_ddr_en_mask_b;
225 	uint8_t reg_gce1_infra_req_mask_b;
226 	uint8_t reg_gce1_apsrc_req_mask_b;
227 	uint8_t reg_gce1_vrf18_req_mask_b;
228 	uint8_t reg_gce1_ddr_en_mask_b;
229 	uint8_t reg_spm_srcclkena_reserved_mask_b;
230 	uint8_t reg_spm_infra_req_reserved_mask_b;
231 	uint8_t reg_spm_apsrc_req_reserved_mask_b;
232 	uint8_t reg_spm_vrf18_req_reserved_mask_b;
233 	uint8_t reg_spm_ddr_en_reserved_mask_b;
234 	uint8_t reg_disp0_apsrc_req_mask_b;
235 	uint8_t reg_disp0_ddr_en_mask_b;
236 	uint8_t reg_disp1_apsrc_req_mask_b;
237 	uint8_t reg_disp1_ddr_en_mask_b;
238 	uint8_t reg_disp2_apsrc_req_mask_b;
239 	uint8_t reg_disp2_ddr_en_mask_b;
240 	uint8_t reg_disp3_apsrc_req_mask_b;
241 	uint8_t reg_disp3_ddr_en_mask_b;
242 	uint8_t reg_infrasys_apsrc_req_mask_b;
243 	uint8_t reg_infrasys_ddr_en_mask_b;
244 	uint8_t reg_cg_check_srcclkena_mask_b;
245 	uint8_t reg_cg_check_apsrc_req_mask_b;
246 	uint8_t reg_cg_check_vrf18_req_mask_b;
247 	uint8_t reg_cg_check_ddr_en_mask_b;
248 
249 	/* SPM_SRC4_MASK */
250 	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
251 	uint32_t reg_mcusys_merge_ddr_en_mask_b;
252 	uint8_t reg_dramc_md32_infra_req_mask_b;
253 	uint8_t reg_dramc_md32_vrf18_req_mask_b;
254 	uint8_t reg_dramc_md32_ddr_en_mask_b;
255 	uint8_t reg_dvfsrc_event_trigger_mask_b;
256 
257 	/* SPM_WAKEUP_EVENT_MASK2 */
258 	uint8_t reg_sc_sw2spm_wakeup_mask_b;
259 	uint8_t reg_sc_adsp2spm_wakeup_mask_b;
260 	uint8_t reg_sc_sspm2spm_wakeup_mask_b;
261 	uint8_t reg_sc_scp2spm_wakeup_mask_b;
262 	uint8_t reg_csyspwrup_ack_mask;
263 	uint8_t reg_csyspwrup_req_mask;
264 
265 	/* SPM_WAKEUP_EVENT_MASK */
266 	uint32_t reg_wakeup_event_mask;
267 
268 	/* SPM_WAKEUP_EVENT_EXT_MASK */
269 	uint32_t reg_ext_wakeup_event_mask;
270 };
271 
272 /* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
273 enum pwr_ctrl_enum {
274 	PW_PCM_FLAGS,
275 	PW_PCM_FLAGS_CUST,
276 	PW_PCM_FLAGS_CUST_SET,
277 	PW_PCM_FLAGS_CUST_CLR,
278 	PW_PCM_FLAGS1,
279 	PW_PCM_FLAGS1_CUST,
280 	PW_PCM_FLAGS1_CUST_SET,
281 	PW_PCM_FLAGS1_CUST_CLR,
282 	PW_TIMER_VAL,
283 	PW_TIMER_VAL_CUST,
284 	PW_TIMER_VAL_RAMP_EN,
285 	PW_TIMER_VAL_RAMP_EN_SEC,
286 	PW_WAKE_SRC,
287 	PW_WAKE_SRC_CUST,
288 	PW_WAKELOCK_TIMER_VAL,
289 	PW_WDT_DISABLE,
290 
291 	/* SPM_CLK_CON */
292 	PW_REG_SRCCLKEN0_CTL,
293 	PW_REG_SRCCLKEN1_CTL,
294 	PW_REG_SPM_LOCK_INFRA_DCM,
295 	PW_REG_SRCCLKEN_MASK,
296 	PW_REG_MD1_C32RM_EN,
297 	PW_REG_MD2_C32RM_EN,
298 	PW_REG_CLKSQ0_SEL_CTRL,
299 	PW_REG_CLKSQ1_SEL_CTRL,
300 	PW_REG_SRCCLKEN0_EN,
301 	PW_REG_SRCCLKEN1_EN,
302 	PW_REG_SYSCLK0_SRC_MASK_B,
303 	PW_REG_SYSCLK1_SRC_MASK_B,
304 
305 	/* SPM_AP_STANDBY_CON */
306 	PW_REG_WFI_OP,
307 	PW_REG_WFI_TYPE,
308 	PW_REG_MP0_CPUTOP_IDLE_MASK,
309 	PW_REG_MP1_CPUTOP_IDLE_MASK,
310 	PW_REG_MCUSYS_IDLE_MASK,
311 	PW_REG_MD_APSRC_1_SEL,
312 	PW_REG_MD_APSRC_0_SEL,
313 	PW_REG_CONN_APSRC_SEL,
314 
315 	/* SPM_SRC_REQ */
316 	PW_REG_SPM_APSRC_REQ,
317 	PW_REG_SPM_F26M_REQ,
318 	PW_REG_SPM_INFRA_REQ,
319 	PW_REG_SPM_VRF18_REQ,
320 	PW_REG_SPM_DDR_EN_REQ,
321 	PW_REG_SPM_DVFS_REQ,
322 	PW_REG_SPM_SW_MAILBOX_REQ,
323 	PW_REG_SPM_SSPM_MAILBOX_REQ,
324 	PW_REG_SPM_ADSP_MAILBOX_REQ,
325 	PW_REG_SPM_SCP_MAILBOX_REQ,
326 
327 	/* SPM_SRC_MASK */
328 	PW_REG_MD_SRCCLKENA_0_MASK_B,
329 	PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
330 	PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
331 	PW_REG_MD_APSRC_REQ_0_MASK_B,
332 	PW_REG_MD_VRF18_REQ_0_MASK_B,
333 	PW_REG_MD_DDR_EN_0_MASK_B,
334 	PW_REG_MD_SRCCLKENA_1_MASK_B,
335 	PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
336 	PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
337 	PW_REG_MD_APSRC_REQ_1_MASK_B,
338 	PW_REG_MD_VRF18_REQ_1_MASK_B,
339 	PW_REG_MD_DDR_EN_1_MASK_B,
340 	PW_REG_CONN_SRCCLKENA_MASK_B,
341 	PW_REG_CONN_SRCCLKENB_MASK_B,
342 	PW_REG_CONN_INFRA_REQ_MASK_B,
343 	PW_REG_CONN_APSRC_REQ_MASK_B,
344 	PW_REG_CONN_VRF18_REQ_MASK_B,
345 	PW_REG_CONN_DDR_EN_MASK_B,
346 	PW_REG_CONN_VFE28_MASK_B,
347 	PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
348 	PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
349 	PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
350 	PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
351 	PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
352 	PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
353 	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
354 	PW_REG_INFRASYS_DDR_EN_MASK_B,
355 	PW_REG_MD32_SRCCLKENA_MASK_B,
356 	PW_REG_MD32_INFRA_REQ_MASK_B,
357 	PW_REG_MD32_APSRC_REQ_MASK_B,
358 	PW_REG_MD32_VRF18_REQ_MASK_B,
359 	PW_REG_MD32_DDR_EN_MASK_B,
360 
361 	/* SPM_SRC2_MASK */
362 	PW_REG_SCP_SRCCLKENA_MASK_B,
363 	PW_REG_SCP_INFRA_REQ_MASK_B,
364 	PW_REG_SCP_APSRC_REQ_MASK_B,
365 	PW_REG_SCP_VRF18_REQ_MASK_B,
366 	PW_REG_SCP_DDR_EN_MASK_B,
367 	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
368 	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
369 	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
370 	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
371 	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
372 	PW_REG_UFS_SRCCLKENA_MASK_B,
373 	PW_REG_UFS_INFRA_REQ_MASK_B,
374 	PW_REG_UFS_APSRC_REQ_MASK_B,
375 	PW_REG_UFS_VRF18_REQ_MASK_B,
376 	PW_REG_UFS_DDR_EN_MASK_B,
377 	PW_REG_DISP0_APSRC_REQ_MASK_B,
378 	PW_REG_DISP0_DDR_EN_MASK_B,
379 	PW_REG_DISP1_APSRC_REQ_MASK_B,
380 	PW_REG_DISP1_DDR_EN_MASK_B,
381 	PW_REG_GCE_INFRA_REQ_MASK_B,
382 	PW_REG_GCE_APSRC_REQ_MASK_B,
383 	PW_REG_GCE_VRF18_REQ_MASK_B,
384 	PW_REG_GCE_DDR_EN_MASK_B,
385 	PW_REG_APU_SRCCLKENA_MASK_B,
386 	PW_REG_APU_INFRA_REQ_MASK_B,
387 	PW_REG_APU_APSRC_REQ_MASK_B,
388 	PW_REG_APU_VRF18_REQ_MASK_B,
389 	PW_REG_APU_DDR_EN_MASK_B,
390 	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
391 	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
392 	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
393 	PW_REG_CG_CHECK_DDR_EN_MASK_B,
394 
395 	/* SPM_SRC3_MASK */
396 	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
397 	PW_REG_SW2SPM_INT0_MASK_B,
398 	PW_REG_SW2SPM_INT1_MASK_B,
399 	PW_REG_SW2SPM_INT2_MASK_B,
400 	PW_REG_SW2SPM_INT3_MASK_B,
401 	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
402 	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
403 	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
404 	PW_REG_CSYSPWRREQ_MASK,
405 	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
406 	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
407 	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
408 	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
409 	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
410 	PW_REG_MCUPM_SRCCLKENA_MASK_B,
411 	PW_REG_MCUPM_INFRA_REQ_MASK_B,
412 	PW_REG_MCUPM_APSRC_REQ_MASK_B,
413 	PW_REG_MCUPM_VRF18_REQ_MASK_B,
414 	PW_REG_MCUPM_DDR_EN_MASK_B,
415 	PW_REG_MSDC0_SRCCLKENA_MASK_B,
416 	PW_REG_MSDC0_INFRA_REQ_MASK_B,
417 	PW_REG_MSDC0_APSRC_REQ_MASK_B,
418 	PW_REG_MSDC0_VRF18_REQ_MASK_B,
419 	PW_REG_MSDC0_DDR_EN_MASK_B,
420 	PW_REG_MSDC1_SRCCLKENA_MASK_B,
421 	PW_REG_MSDC1_INFRA_REQ_MASK_B,
422 	PW_REG_MSDC1_APSRC_REQ_MASK_B,
423 	PW_REG_MSDC1_VRF18_REQ_MASK_B,
424 	PW_REG_MSDC1_DDR_EN_MASK_B,
425 
426 	/* SPM_SRC4_MASK */
427 	PW_CCIF_EVENT_MASK_B,
428 	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
429 	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
430 	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
431 	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
432 	PW_REG_BAK_PSRI_DDR_EN_MASK_B,
433 	PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
434 	PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
435 	PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
436 	PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
437 	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
438 	PW_REG_DRAMC0_MD32_WAKEUP_MASK,
439 	PW_REG_DRAMC1_MD32_WAKEUP_MASK,
440 
441 	/* SPM_SRC5_MASK */
442 	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
443 	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
444 
445 	/* SPM_WAKEUP_EVENT_MASK */
446 	PW_REG_WAKEUP_EVENT_MASK,
447 
448 	/* SPM_WAKEUP_EVENT_EXT_MASK */
449 	PW_REG_EXT_WAKEUP_EVENT_MASK,
450 
451 	PW_MAX_COUNT,
452 };
453 
454 #define SPM_INTERNAL_STATUS_HW_S1	(1U << 0)
455 #define SPM_ACK_CHK_3_SEL_HW_S1		0x00350098
456 #define SPM_ACK_CHK_3_HW_S1_CNT		1
457 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG	0x800
458 #define SPM_ACK_CHK_3_CON_EN		0x110
459 #define SPM_ACK_CHK_3_CON_CLR_ALL	0x2
460 #define SPM_ACK_CHK_3_CON_RESULT	0x8000
461 
462 struct wake_status_trace_comm {
463 	uint32_t debug_flag;			/* PCM_WDT_LATCH_SPARE_0 */
464 	uint32_t debug_flag1;			/* PCM_WDT_LATCH_SPARE_1 */
465 	uint32_t timer_out;			/* SPM_BK_PCM_TIMER */
466 	uint32_t b_sw_flag0;			/* SPM_SW_RSV_7 */
467 	uint32_t b_sw_flag1;			/* SPM_SW_RSV_8 */
468 	uint32_t r12;				/* SPM_SW_RSV_0 */
469 	uint32_t r13;				/* PCM_REG13_DATA */
470 	uint32_t req_sta0;			/* SRC_REQ_STA_0 */
471 	uint32_t req_sta1;			/* SRC_REQ_STA_1 */
472 	uint32_t req_sta2;			/* SRC_REQ_STA_2 */
473 	uint32_t req_sta3;			/* SRC_REQ_STA_3 */
474 	uint32_t req_sta4;			/* SRC_REQ_STA_4 */
475 	uint32_t raw_sta;			/* SPM_WAKEUP_STA */
476 	uint32_t times_h;			/* timestamp high bits */
477 	uint32_t times_l;			/* timestamp low bits */
478 	uint32_t resumetime;			/* timestamp low bits */
479 };
480 
481 struct wake_status_trace {
482 	struct wake_status_trace_comm comm;
483 };
484 
485 struct wake_status {
486 	struct wake_status_trace tr;
487 	uint32_t r12;				/* SPM_BK_WAKE_EVENT */
488 	uint32_t r12_ext;			/* SPM_WAKEUP_STA */
489 	uint32_t raw_sta;			/* SPM_WAKEUP_STA */
490 	uint32_t raw_ext_sta;			/* SPM_WAKEUP_EXT_STA */
491 	uint32_t md32pcm_wakeup_sta;		/* MD32PCM_WAKEUP_STA */
492 	uint32_t md32pcm_event_sta;		/* MD32PCM_EVENT_STA */
493 	uint32_t src_req;			/* SPM_SRC_REQ */
494 	uint32_t wake_misc;			/* SPM_BK_WAKE_MISC */
495 	uint32_t timer_out;			/* SPM_BK_PCM_TIMER */
496 	uint32_t r13;				/* PCM_REG13_DATA */
497 	uint32_t idle_sta;			/* SUBSYS_IDLE_STA */
498 	uint32_t req_sta0;			/* SRC_REQ_STA_0 */
499 	uint32_t req_sta1;			/* SRC_REQ_STA_1 */
500 	uint32_t req_sta2;			/* SRC_REQ_STA_2 */
501 	uint32_t req_sta3;			/* SRC_REQ_STA_3 */
502 	uint32_t req_sta4;			/* SRC_REQ_STA_4 */
503 	uint32_t cg_check_sta;			/* SPM_CG_CHECK_STA */
504 	uint32_t debug_flag;			/* PCM_WDT_LATCH_SPARE_0 */
505 	uint32_t debug_flag1;			/* PCM_WDT_LATCH_SPARE_1 */
506 	uint32_t b_sw_flag0;			/* SPM_SW_RSV_7 */
507 	uint32_t b_sw_flag1;			/* SPM_SW_RSV_8 */
508 	uint32_t rt_req_sta0;			/* SPM_SW_RSV_2 */
509 	uint32_t rt_req_sta1;			/* SPM_SW_RSV_3 */
510 	uint32_t rt_req_sta2;			/* SPM_SW_RSV_4 */
511 	uint32_t rt_req_sta3;			/* SPM_SW_RSV_5 */
512 	uint32_t rt_req_sta4;			/* SPM_SW_RSV_6 */
513 	uint32_t isr;				/* SPM_IRQ_STA */
514 	uint32_t sw_flag0;			/* SPM_SW_FLAG_0 */
515 	uint32_t sw_flag1;			/* SPM_SW_FLAG_1 */
516 	uint32_t clk_settle;			/* SPM_CLK_SETTLE */
517 	uint32_t abort;
518 };
519 
520 struct spm_lp_scen {
521 	struct pcm_desc *pcmdesc;
522 	struct pwr_ctrl *pwrctrl;
523 };
524 
525 extern struct spm_lp_scen __spm_vcorefs;
526 extern void __spm_set_cpu_status(unsigned int cpu);
527 extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
528 extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
529 extern void __spm_init_pcm_register(void);
530 extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
531 				 unsigned int resource_usage);
532 extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
533 extern void __spm_disable_pcm_timer(void);
534 extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
535 extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
536 extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
537 extern void __spm_send_cpu_wakeup_event(void);
538 extern void __spm_get_wakeup_status(struct wake_status *wakesta,
539 				    unsigned int ext_status);
540 extern void __spm_clean_after_wakeup(void);
541 extern wake_reason_t
542 __spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
543 extern void
544 __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
545 				    const struct pwr_ctrl *src_pwr_ctrl);
546 extern void __spm_set_pcm_wdt(int en);
547 extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
548 extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
549 extern void __spm_ext_int_wakeup_req_clr(void);
550 extern void __spm_xo_soc_bblpm(int en);
551 
set_pwrctrl_pcm_flags(struct pwr_ctrl * pwrctrl,uint32_t flags)552 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
553 					 uint32_t flags)
554 {
555 	if (pwrctrl->pcm_flags_cust == 0U) {
556 		pwrctrl->pcm_flags = flags;
557 	} else {
558 		pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
559 	}
560 }
561 
set_pwrctrl_pcm_flags1(struct pwr_ctrl * pwrctrl,uint32_t flags)562 static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
563 					  uint32_t flags)
564 {
565 	if (pwrctrl->pcm_flags1_cust == 0U) {
566 		pwrctrl->pcm_flags1 = flags;
567 	} else {
568 		pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
569 	}
570 }
571 
572 extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
573 
spm_hw_s1_state_monitor_resume(void)574 static inline void spm_hw_s1_state_monitor_resume(void)
575 {
576 	__spm_hw_s1_state_monitor(1, NULL);
577 }
578 
spm_hw_s1_state_monitor_pause(unsigned int * status)579 static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
580 {
581 	__spm_hw_s1_state_monitor(0, status);
582 }
583 #endif /* MT_SPM_INTERNAL_H */
584