| /external/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 470 scvtf d1, w2 define
471 scvtf d1, w2, #1 define
476 scvtf d1, x2 define
477 scvtf d1, x2, #1 define
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| D | arm64-advsimd.s | 1381 scvtf d0, d0, #2 define
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| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 583 __ scvtf(d31, d16); in GenerateTestSequenceFP() local
584 __ scvtf(d26, d31, 24); in GenerateTestSequenceFP() local
585 __ scvtf(d6, w16); in GenerateTestSequenceFP() local
586 __ scvtf(d5, w20, 6); in GenerateTestSequenceFP() local
587 __ scvtf(d16, x8); in GenerateTestSequenceFP() local
588 __ scvtf(d15, x8, 10); in GenerateTestSequenceFP() local
589 __ scvtf(s7, s4); in GenerateTestSequenceFP() local
590 __ scvtf(s8, s15, 14); in GenerateTestSequenceFP() local
591 __ scvtf(s29, w10); in GenerateTestSequenceFP() local
592 __ scvtf(s15, w21, 11); in GenerateTestSequenceFP() local
[all …]
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| D | test-api-movprfx-aarch64.cc | 574 __ scvtf(z25.VnD(), p6.Merging(), z25.VnS()); in TEST() local
577 __ scvtf(z0.VnD(), p3.Merging(), z0.VnD()); in TEST() local
580 __ scvtf(z19.VnS(), p7.Merging(), z19.VnD()); in TEST() local
583 __ scvtf(z19.VnH(), p4.Merging(), z19.VnD()); in TEST() local
1055 __ scvtf(z22.VnD(), p3.Merging(), z24.VnS()); in TEST() local
1058 __ scvtf(z20.VnH(), p2.Merging(), z9.VnH()); in TEST() local
1061 __ scvtf(z19.VnS(), p1.Merging(), z6.VnD()); in TEST() local
1064 __ scvtf(z31.VnH(), p3.Merging(), z22.VnD()); in TEST() local
1921 __ scvtf(z2.VnD(), p1.Merging(), z16.VnS()); in TEST() local
1924 __ scvtf(z10.VnD(), p5.Merging(), z20.VnD()); in TEST() local
[all …]
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 3247 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf() function in vixl::aarch64::Assembler
3266 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 6823 LogicVRegister Simulator::scvtf(VectorFormat vform, in scvtf() function in vixl::aarch64::Simulator
6867 LogicVRegister Simulator::scvtf(VectorFormat vform, in scvtf() function in vixl::aarch64::Simulator
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| D | assembler-sve-aarch64.cc | 1904 void Assembler::scvtf(const ZRegister& zd, in scvtf() function in vixl::aarch64::Assembler
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