1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_debug.h"
26 #include "si_build_pm4.h"
27 #include "sid.h"
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_prim.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_upload_mgr.h"
33
34 /* special primitive types */
35 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
36
37 ALWAYS_INLINE
si_conv_pipe_prim(unsigned mode)38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST};
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 /**
62 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
63 * LS.LDS_SIZE is shared by all 3 shader stages.
64 *
65 * The information about LDS and other non-compile-time parameters is then
66 * written to userdata SGPRs.
67 */
si_emit_derived_tess_state(struct si_context * sctx,const struct pipe_draw_info * info,unsigned * num_patches)68 static void si_emit_derived_tess_state(struct si_context *sctx, const struct pipe_draw_info *info,
69 unsigned *num_patches)
70 {
71 struct radeon_cmdbuf *cs = sctx->gfx_cs;
72 struct si_shader *ls_current;
73 struct si_shader_selector *ls;
74 /* The TES pointer will only be used for sctx->last_tcs.
75 * It would be wrong to think that TCS = TES. */
76 struct si_shader_selector *tcs =
77 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
78 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
79 bool has_primid_instancing_bug = sctx->chip_class == GFX6 && sctx->screen->info.max_se == 1;
80 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
81 unsigned num_tcs_input_cp = info->vertices_per_patch;
82 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
83 unsigned num_tcs_patch_outputs;
84 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
85 unsigned input_patch_size, output_patch_size, output_patch0_offset;
86 unsigned perpatch_output_offset, lds_size;
87 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
88 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
89
90 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
91 if (sctx->chip_class >= GFX9) {
92 if (sctx->tcs_shader.cso)
93 ls_current = sctx->tcs_shader.current;
94 else
95 ls_current = sctx->fixed_func_tcs_shader.current;
96
97 ls = ls_current->key.part.tcs.ls;
98 } else {
99 ls_current = sctx->vs_shader.current;
100 ls = sctx->vs_shader.cso;
101 }
102
103 if (sctx->last_ls == ls_current && sctx->last_tcs == tcs &&
104 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
105 (!has_primid_instancing_bug || (sctx->last_tess_uses_primid == tess_uses_primid))) {
106 *num_patches = sctx->last_num_patches;
107 return;
108 }
109
110 sctx->last_ls = ls_current;
111 sctx->last_tcs = tcs;
112 sctx->last_tes_sh_base = tes_sh_base;
113 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
114 sctx->last_tess_uses_primid = tess_uses_primid;
115
116 /* This calculates how shader inputs and outputs among VS, TCS, and TES
117 * are laid out in LDS. */
118 num_tcs_inputs = util_last_bit64(ls->outputs_written);
119
120 if (sctx->tcs_shader.cso) {
121 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
122 num_tcs_output_cp = tcs->info.base.tess.tcs_vertices_out;
123 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
124 } else {
125 /* No TCS. Route varyings from LS to TES. */
126 num_tcs_outputs = num_tcs_inputs;
127 num_tcs_output_cp = num_tcs_input_cp;
128 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
129 }
130
131 input_vertex_size = ls->lshs_vertex_stride;
132 output_vertex_size = num_tcs_outputs * 16;
133
134 input_patch_size = num_tcs_input_cp * input_vertex_size;
135
136 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
137 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
138
139 /* Ensure that we only need one wave per SIMD so we don't need to check
140 * resource usage. Also ensures that the number of tcs in and out
141 * vertices per threadgroup are at most 256.
142 */
143 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
144 *num_patches = 256 / max_verts_per_patch;
145
146 /* Make sure that the data fits in LDS. This assumes the shaders only
147 * use LDS for the inputs and outputs.
148 *
149 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
150 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
151 * uses 32K at most on all GCN chips.
152 */
153 hardware_lds_size = 32768;
154 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
155
156 /* Make sure the output data fits in the offchip buffer */
157 *num_patches =
158 MIN2(*num_patches, (sctx->screen->tess_offchip_block_dw_size * 4) / output_patch_size);
159
160 /* Not necessary for correctness, but improves performance.
161 * The hardware can do more, but the radeonsi shader constant is
162 * limited to 6 bits.
163 */
164 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
165
166 /* When distributed tessellation is unsupported, switch between SEs
167 * at a higher frequency to compensate for it.
168 */
169 if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
170 *num_patches = MIN2(*num_patches, 16); /* recommended */
171
172 /* Make sure that vector lanes are reasonably occupied. It probably
173 * doesn't matter much because this is LS-HS, and TES is likely to
174 * occupy significantly more CUs.
175 */
176 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
177 unsigned wave_size = sctx->screen->ge_wave_size;
178
179 if (temp_verts_per_tg > wave_size && temp_verts_per_tg % wave_size < wave_size * 3 / 4)
180 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch;
181
182 if (sctx->chip_class == GFX6) {
183 /* GFX6 bug workaround, related to power management. Limit LS-HS
184 * threadgroups to only one wave.
185 */
186 unsigned one_wave = wave_size / max_verts_per_patch;
187 *num_patches = MIN2(*num_patches, one_wave);
188 }
189
190 /* The VGT HS block increments the patch ID unconditionally
191 * within a single threadgroup. This results in incorrect
192 * patch IDs when instanced draws are used.
193 *
194 * The intended solution is to restrict threadgroups to
195 * a single instance by setting SWITCH_ON_EOI, which
196 * should cause IA to split instances up. However, this
197 * doesn't work correctly on GFX6 when there is no other
198 * SE to switch to.
199 */
200 if (has_primid_instancing_bug && tess_uses_primid)
201 *num_patches = 1;
202
203 sctx->last_num_patches = *num_patches;
204
205 output_patch0_offset = input_patch_size * *num_patches;
206 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
207
208 /* Compute userdata SGPRs. */
209 assert(((input_vertex_size / 4) & ~0xff) == 0);
210 assert(((output_vertex_size / 4) & ~0xff) == 0);
211 assert(((input_patch_size / 4) & ~0x1fff) == 0);
212 assert(((output_patch_size / 4) & ~0x1fff) == 0);
213 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
214 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
215 assert(num_tcs_input_cp <= 32);
216 assert(num_tcs_output_cp <= 32);
217
218 uint64_t ring_va = (unlikely(sctx->ws->cs_is_secure(sctx->gfx_cs)) ?
219 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address;
220 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
221
222 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
223 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
224 tcs_out_layout = (output_patch_size / 4) | (num_tcs_input_cp << 13) | ring_va;
225 tcs_out_offsets = (output_patch0_offset / 16) | ((perpatch_output_offset / 16) << 16);
226 offchip_layout =
227 *num_patches | (num_tcs_output_cp << 6) | (pervertex_output_patch_size * *num_patches << 12);
228
229 /* Compute the LDS size. */
230 lds_size = output_patch0_offset + output_patch_size * *num_patches;
231
232 if (sctx->chip_class >= GFX7) {
233 assert(lds_size <= 65536);
234 lds_size = align(lds_size, 512) / 512;
235 } else {
236 assert(lds_size <= 32768);
237 lds_size = align(lds_size, 256) / 256;
238 }
239
240 /* Set SI_SGPR_VS_STATE_BITS. */
241 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE & C_VS_STATE_LS_OUT_VERTEX_SIZE;
242 sctx->current_vs_state |= tcs_in_layout;
243
244 /* We should be able to support in-shader LDS use with LLVM >= 9
245 * by just adding the lds_sizes together, but it has never
246 * been tested. */
247 assert(ls_current->config.lds_size == 0);
248
249 if (sctx->chip_class >= GFX9) {
250 unsigned hs_rsrc2 = ls_current->config.rsrc2;
251
252 if (sctx->chip_class >= GFX10)
253 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
254 else
255 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
256
257 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
258
259 /* Set userdata SGPRs for merged LS-HS. */
260 radeon_set_sh_reg_seq(
261 cs, R_00B430_SPI_SHADER_USER_DATA_LS_0 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
262 radeon_emit(cs, offchip_layout);
263 radeon_emit(cs, tcs_out_offsets);
264 radeon_emit(cs, tcs_out_layout);
265 } else {
266 unsigned ls_rsrc2 = ls_current->config.rsrc2;
267
268 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
269 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
270
271 /* Due to a hw bug, RSRC2_LS must be written twice with another
272 * LS register written in between. */
273 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
274 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
275 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
276 radeon_emit(cs, ls_current->config.rsrc1);
277 radeon_emit(cs, ls_rsrc2);
278
279 /* Set userdata SGPRs for TCS. */
280 radeon_set_sh_reg_seq(
281 cs, R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
282 radeon_emit(cs, offchip_layout);
283 radeon_emit(cs, tcs_out_offsets);
284 radeon_emit(cs, tcs_out_layout);
285 radeon_emit(cs, tcs_in_layout);
286 }
287
288 /* Set userdata SGPRs for TES. */
289 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
290 radeon_emit(cs, offchip_layout);
291 radeon_emit(cs, ring_va);
292
293 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
294 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
295
296 if (sctx->last_ls_hs_config != ls_hs_config) {
297 if (sctx->chip_class >= GFX7) {
298 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
299 } else {
300 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
301 }
302 sctx->last_ls_hs_config = ls_hs_config;
303 sctx->context_roll = true;
304 }
305 }
306
si_num_prims_for_vertices(enum pipe_prim_type prim,unsigned count,unsigned vertices_per_patch)307 static unsigned si_num_prims_for_vertices(enum pipe_prim_type prim,
308 unsigned count, unsigned vertices_per_patch)
309 {
310 switch (prim) {
311 case PIPE_PRIM_PATCHES:
312 return count / vertices_per_patch;
313 case PIPE_PRIM_POLYGON:
314 return count >= 3;
315 case SI_PRIM_RECTANGLE_LIST:
316 return count / 3;
317 default:
318 return u_decomposed_prims_for_vertices(prim, count);
319 }
320 }
321
si_get_init_multi_vgt_param(struct si_screen * sscreen,union si_vgt_param_key * key)322 static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_vgt_param_key *key)
323 {
324 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
325 unsigned max_primgroup_in_wave = 2;
326
327 /* SWITCH_ON_EOP(0) is always preferable. */
328 bool wd_switch_on_eop = false;
329 bool ia_switch_on_eop = false;
330 bool ia_switch_on_eoi = false;
331 bool partial_vs_wave = false;
332 bool partial_es_wave = false;
333
334 if (key->u.uses_tess) {
335 /* SWITCH_ON_EOI must be set if PrimID is used. */
336 if (key->u.tess_uses_prim_id)
337 ia_switch_on_eoi = true;
338
339 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
340 if ((sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_PITCAIRN ||
341 sscreen->info.family == CHIP_BONAIRE) &&
342 key->u.uses_gs)
343 partial_vs_wave = true;
344
345 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
346 if (sscreen->info.has_distributed_tess) {
347 if (key->u.uses_gs) {
348 if (sscreen->info.chip_class == GFX8)
349 partial_es_wave = true;
350 } else {
351 partial_vs_wave = true;
352 }
353 }
354 }
355
356 /* This is a hardware requirement. */
357 if (key->u.line_stipple_enabled || (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
358 ia_switch_on_eop = true;
359 wd_switch_on_eop = true;
360 }
361
362 if (sscreen->info.chip_class >= GFX7) {
363 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
364 * 4 shader engines. Set 1 to pass the assertion below.
365 * The other cases are hardware requirements.
366 *
367 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
368 * for points, line strips, and tri strips.
369 */
370 if (sscreen->info.max_se <= 2 || key->u.prim == PIPE_PRIM_POLYGON ||
371 key->u.prim == PIPE_PRIM_LINE_LOOP || key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
372 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
373 (key->u.primitive_restart &&
374 (sscreen->info.family < CHIP_POLARIS10 ||
375 (key->u.prim != PIPE_PRIM_POINTS && key->u.prim != PIPE_PRIM_LINE_STRIP &&
376 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
377 key->u.count_from_stream_output)
378 wd_switch_on_eop = true;
379
380 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
381 * We don't know that for indirect drawing, so treat it as
382 * always problematic. */
383 if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing)
384 wd_switch_on_eop = true;
385
386 /* Performance recommendation for 4 SE Gfx7-8 parts if
387 * instances are smaller than a primgroup.
388 * Assume indirect draws always use small instances.
389 * This is needed for good VS wave utilization.
390 */
391 if (sscreen->info.chip_class <= GFX8 && sscreen->info.max_se == 4 &&
392 key->u.multi_instances_smaller_than_primgroup)
393 wd_switch_on_eop = true;
394
395 /* Required on GFX7 and later. */
396 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
397 ia_switch_on_eoi = true;
398
399 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
400 * to work around a GS hang.
401 */
402 if (key->u.uses_gs &&
403 (sscreen->info.family == CHIP_TONGA || sscreen->info.family == CHIP_FIJI ||
404 sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11 ||
405 sscreen->info.family == CHIP_POLARIS12 || sscreen->info.family == CHIP_VEGAM))
406 partial_vs_wave = true;
407
408 /* Required by Hawaii and, for some special cases, by GFX8. */
409 if (ia_switch_on_eoi &&
410 (sscreen->info.family == CHIP_HAWAII ||
411 (sscreen->info.chip_class == GFX8 && (key->u.uses_gs || max_primgroup_in_wave != 2))))
412 partial_vs_wave = true;
413
414 /* Instancing bug on Bonaire. */
415 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi && key->u.uses_instancing)
416 partial_vs_wave = true;
417
418 /* This only applies to Polaris10 and later 4 SE chips.
419 * wd_switch_on_eop is already true on all other chips.
420 */
421 if (!wd_switch_on_eop && key->u.primitive_restart)
422 partial_vs_wave = true;
423
424 /* If the WD switch is false, the IA switch must be false too. */
425 assert(wd_switch_on_eop || !ia_switch_on_eop);
426 }
427
428 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
429 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
430 partial_es_wave = true;
431
432 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
433 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
434 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
435 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
436 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
437 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ? max_primgroup_in_wave
438 : 0) |
439 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
440 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
441 }
442
si_init_ia_multi_vgt_param_table(struct si_context * sctx)443 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
444 {
445 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
446 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
447 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
448 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
449 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
450 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
451 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
452 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
453 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
454 union si_vgt_param_key key;
455
456 key.index = 0;
457 key.u.prim = prim;
458 key.u.uses_instancing = uses_instancing;
459 key.u.multi_instances_smaller_than_primgroup = multi_instances;
460 key.u.primitive_restart = primitive_restart;
461 key.u.count_from_stream_output = count_from_so;
462 key.u.line_stipple_enabled = line_stipple;
463 key.u.uses_tess = uses_tess;
464 key.u.tess_uses_prim_id = tess_uses_primid;
465 key.u.uses_gs = uses_gs;
466
467 sctx->ia_multi_vgt_param[key.index] =
468 si_get_init_multi_vgt_param(sctx->screen, &key);
469 }
470 }
471
si_is_line_stipple_enabled(struct si_context * sctx)472 static bool si_is_line_stipple_enabled(struct si_context *sctx)
473 {
474 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
475
476 return rs->line_stipple_enable && sctx->current_rast_prim != PIPE_PRIM_POINTS &&
477 (rs->polygon_mode_is_lines || util_prim_is_lines(sctx->current_rast_prim));
478 }
479
480 ALWAYS_INLINE
si_get_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_info * info,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)481 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
482 const struct pipe_draw_info *info,
483 enum pipe_prim_type prim, unsigned num_patches,
484 unsigned instance_count, bool primitive_restart,
485 unsigned min_vertex_count)
486 {
487 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
488 unsigned primgroup_size;
489 unsigned ia_multi_vgt_param;
490
491 if (sctx->tes_shader.cso) {
492 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
493 } else if (sctx->gs_shader.cso) {
494 primgroup_size = 64; /* recommended with a GS */
495 } else {
496 primgroup_size = 128; /* recommended without a GS and tess */
497 }
498
499 key.u.prim = prim;
500 key.u.uses_instancing = info->indirect || instance_count > 1;
501 key.u.multi_instances_smaller_than_primgroup =
502 info->indirect ||
503 (instance_count > 1 &&
504 (info->count_from_stream_output ||
505 si_num_prims_for_vertices(prim, min_vertex_count, info->vertices_per_patch) < primgroup_size));
506 key.u.primitive_restart = primitive_restart;
507 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
508 key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
509
510 ia_multi_vgt_param =
511 sctx->ia_multi_vgt_param[key.index] | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
512
513 if (sctx->gs_shader.cso) {
514 /* GS requirement. */
515 if (sctx->chip_class <= GFX8 &&
516 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
517 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
518
519 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
520 * The hw doc says all multi-SE chips are affected, but Vulkan
521 * only applies it to Hawaii. Do what Vulkan does.
522 */
523 if (sctx->family == CHIP_HAWAII && G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
524 (info->indirect ||
525 (instance_count > 1 &&
526 (info->count_from_stream_output ||
527 si_num_prims_for_vertices(prim, min_vertex_count, info->vertices_per_patch) <= 1))))
528
529 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
530 }
531
532 return ia_multi_vgt_param;
533 }
534
535 ALWAYS_INLINE
si_conv_prim_to_gs_out(unsigned mode)536 static unsigned si_conv_prim_to_gs_out(unsigned mode)
537 {
538 static const int prim_conv[] = {
539 [PIPE_PRIM_POINTS] = V_028A6C_POINTLIST,
540 [PIPE_PRIM_LINES] = V_028A6C_LINESTRIP,
541 [PIPE_PRIM_LINE_LOOP] = V_028A6C_LINESTRIP,
542 [PIPE_PRIM_LINE_STRIP] = V_028A6C_LINESTRIP,
543 [PIPE_PRIM_TRIANGLES] = V_028A6C_TRISTRIP,
544 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_TRISTRIP,
545 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_TRISTRIP,
546 [PIPE_PRIM_QUADS] = V_028A6C_TRISTRIP,
547 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_TRISTRIP,
548 [PIPE_PRIM_POLYGON] = V_028A6C_TRISTRIP,
549 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_LINESTRIP,
550 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_LINESTRIP,
551 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_TRISTRIP,
552 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_TRISTRIP,
553 [PIPE_PRIM_PATCHES] = V_028A6C_POINTLIST,
554 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_RECTLIST,
555 };
556 assert(mode < ARRAY_SIZE(prim_conv));
557
558 return prim_conv[mode];
559 }
560
561 /* rast_prim is the primitive type after GS. */
562 ALWAYS_INLINE
si_emit_rasterizer_prim_state(struct si_context * sctx)563 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
564 {
565 struct radeon_cmdbuf *cs = sctx->gfx_cs;
566 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
567 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
568 unsigned initial_cdw = cs->current.cdw;
569
570 if (unlikely(si_is_line_stipple_enabled(sctx))) {
571 /* For lines, reset the stipple pattern at each primitive. Otherwise,
572 * reset the stipple pattern at each packet (line strips, line loops).
573 */
574 unsigned value =
575 rs->pa_sc_line_stipple | S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2);
576
577 radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE, SI_TRACKED_PA_SC_LINE_STIPPLE,
578 value);
579 }
580
581 unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
582 if (unlikely(gs_out_prim != sctx->last_gs_out_prim && (sctx->ngg || sctx->gs_shader.cso))) {
583 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
584 sctx->last_gs_out_prim = gs_out_prim;
585 }
586
587 if (initial_cdw != cs->current.cdw)
588 sctx->context_roll = true;
589
590 if (sctx->ngg) {
591 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
592
593 sctx->current_vs_state &= C_VS_STATE_OUTPRIM & C_VS_STATE_PROVOKING_VTX_INDEX;
594 sctx->current_vs_state |=
595 S_VS_STATE_OUTPRIM(gs_out_prim) | S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
596 }
597 }
598
599 ALWAYS_INLINE
si_emit_vs_state(struct si_context * sctx,const struct pipe_draw_info * info)600 static void si_emit_vs_state(struct si_context *sctx, const struct pipe_draw_info *info)
601 {
602 sctx->current_vs_state &= C_VS_STATE_INDEXED;
603 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
604
605 if (sctx->num_vs_blit_sgprs) {
606 /* Re-emit the state after we leave u_blitter. */
607 sctx->last_vs_state = ~0;
608 return;
609 }
610
611 if (sctx->current_vs_state != sctx->last_vs_state) {
612 struct radeon_cmdbuf *cs = sctx->gfx_cs;
613
614 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
615 radeon_set_sh_reg(
616 cs, sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_STATE_BITS * 4,
617 sctx->current_vs_state);
618
619 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
620 * before the rasterizer.
621 *
622 * For TES or the GS copy shader without NGG:
623 */
624 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] != R_00B130_SPI_SHADER_USER_DATA_VS_0) {
625 radeon_set_sh_reg(cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4,
626 sctx->current_vs_state);
627 }
628
629 /* For NGG: */
630 if (sctx->screen->use_ngg &&
631 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] != R_00B230_SPI_SHADER_USER_DATA_GS_0) {
632 radeon_set_sh_reg(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + SI_SGPR_VS_STATE_BITS * 4,
633 sctx->current_vs_state);
634 }
635
636 sctx->last_vs_state = sctx->current_vs_state;
637 }
638 }
639
640 ALWAYS_INLINE
si_prim_restart_index_changed(struct si_context * sctx,bool primitive_restart,unsigned restart_index)641 static bool si_prim_restart_index_changed(struct si_context *sctx, bool primitive_restart,
642 unsigned restart_index)
643 {
644 return primitive_restart && (restart_index != sctx->last_restart_index ||
645 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
646 }
647
648 ALWAYS_INLINE
si_emit_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_info * info,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)649 static void si_emit_ia_multi_vgt_param(struct si_context *sctx, const struct pipe_draw_info *info,
650 enum pipe_prim_type prim, unsigned num_patches,
651 unsigned instance_count, bool primitive_restart,
652 unsigned min_vertex_count)
653 {
654 struct radeon_cmdbuf *cs = sctx->gfx_cs;
655 unsigned ia_multi_vgt_param;
656
657 ia_multi_vgt_param =
658 si_get_ia_multi_vgt_param(sctx, info, prim, num_patches, instance_count, primitive_restart,
659 min_vertex_count);
660
661 /* Draw state. */
662 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
663 if (sctx->chip_class == GFX9)
664 radeon_set_uconfig_reg_idx(cs, sctx->screen, R_030960_IA_MULTI_VGT_PARAM, 4,
665 ia_multi_vgt_param);
666 else if (sctx->chip_class >= GFX7)
667 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
668 else
669 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
670
671 sctx->last_multi_vgt_param = ia_multi_vgt_param;
672 }
673 }
674
675 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
676 * We overload last_multi_vgt_param.
677 */
678 ALWAYS_INLINE
gfx10_emit_ge_cntl(struct si_context * sctx,unsigned num_patches)679 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
680 {
681 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
682 unsigned ge_cntl;
683
684 if (sctx->ngg) {
685 if (sctx->tes_shader.cso) {
686 ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
687 S_03096C_VERT_GRP_SIZE(0) |
688 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
689 } else {
690 ge_cntl = si_get_vs_state(sctx)->ge_cntl;
691 }
692 } else {
693 unsigned primgroup_size;
694 unsigned vertgroup_size;
695
696 if (sctx->tes_shader.cso) {
697 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
698 vertgroup_size = 0;
699 } else if (sctx->gs_shader.cso) {
700 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
701 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
702 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
703 } else {
704 primgroup_size = 128; /* recommended without a GS and tess */
705 vertgroup_size = 0;
706 }
707
708 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) | S_03096C_VERT_GRP_SIZE(vertgroup_size) |
709 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
710 }
711
712 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx));
713
714 if (ge_cntl != sctx->last_multi_vgt_param) {
715 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
716 sctx->last_multi_vgt_param = ge_cntl;
717 }
718 }
719
720 ALWAYS_INLINE
si_emit_draw_registers(struct si_context * sctx,const struct pipe_draw_info * info,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)721 static void si_emit_draw_registers(struct si_context *sctx, const struct pipe_draw_info *info,
722 enum pipe_prim_type prim, unsigned num_patches,
723 unsigned instance_count, bool primitive_restart,
724 unsigned min_vertex_count)
725 {
726 struct radeon_cmdbuf *cs = sctx->gfx_cs;
727 unsigned vgt_prim = si_conv_pipe_prim(prim);
728
729 if (sctx->chip_class >= GFX10)
730 gfx10_emit_ge_cntl(sctx, num_patches);
731 else
732 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches, instance_count, primitive_restart,
733 min_vertex_count);
734
735 if (vgt_prim != sctx->last_prim) {
736 if (sctx->chip_class >= GFX10)
737 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
738 else if (sctx->chip_class >= GFX7)
739 radeon_set_uconfig_reg_idx(cs, sctx->screen, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
740 else
741 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
742
743 sctx->last_prim = vgt_prim;
744 }
745
746 /* Primitive restart. */
747 if (primitive_restart != sctx->last_primitive_restart_en) {
748 if (sctx->chip_class >= GFX9)
749 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
750 else
751 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
752
753 sctx->last_primitive_restart_en = primitive_restart;
754 }
755 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
756 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
757 sctx->last_restart_index = info->restart_index;
758 sctx->context_roll = true;
759 }
760 }
761
si_emit_draw_packets(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_start_count * draws,unsigned num_draws,struct pipe_resource * indexbuf,unsigned index_size,unsigned index_offset,unsigned instance_count,bool dispatch_prim_discard_cs,unsigned original_index_size)762 static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info,
763 const struct pipe_draw_start_count *draws,
764 unsigned num_draws,
765 struct pipe_resource *indexbuf, unsigned index_size,
766 unsigned index_offset, unsigned instance_count,
767 bool dispatch_prim_discard_cs, unsigned original_index_size)
768 {
769 struct pipe_draw_indirect_info *indirect = info->indirect;
770 struct radeon_cmdbuf *cs = sctx->gfx_cs;
771 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
772 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
773 uint32_t index_max_size = 0;
774 uint64_t index_va = 0;
775
776 if (info->count_from_stream_output) {
777 struct si_streamout_target *t = (struct si_streamout_target *)info->count_from_stream_output;
778
779 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
780 si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL,
781 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2, COPY_DATA_SRC_MEM,
782 t->buf_filled_size, t->buf_filled_size_offset);
783 }
784
785 /* draw packet */
786 if (index_size) {
787 /* Register shadowing doesn't shadow INDEX_TYPE. */
788 if (index_size != sctx->last_index_size || sctx->shadowed_regs) {
789 unsigned index_type;
790
791 /* index type */
792 switch (index_size) {
793 case 1:
794 index_type = V_028A7C_VGT_INDEX_8;
795 break;
796 case 2:
797 index_type =
798 V_028A7C_VGT_INDEX_16 |
799 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
800 break;
801 case 4:
802 index_type =
803 V_028A7C_VGT_INDEX_32 |
804 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
805 break;
806 default:
807 assert(!"unreachable");
808 return;
809 }
810
811 if (sctx->chip_class >= GFX9) {
812 radeon_set_uconfig_reg_idx(cs, sctx->screen, R_03090C_VGT_INDEX_TYPE, 2, index_type);
813 } else {
814 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
815 radeon_emit(cs, index_type);
816 }
817
818 sctx->last_index_size = index_size;
819 }
820
821 if (original_index_size) {
822 index_max_size = (indexbuf->width0 - index_offset) / original_index_size;
823 /* Skip draw calls with 0-sized index buffers.
824 * They cause a hang on some chips, like Navi10-14.
825 */
826 if (!index_max_size)
827 return;
828
829 index_va = si_resource(indexbuf)->gpu_address + index_offset;
830
831 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(indexbuf), RADEON_USAGE_READ,
832 RADEON_PRIO_INDEX_BUFFER);
833 }
834 } else {
835 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
836 * so the state must be re-emitted before the next indexed draw.
837 */
838 if (sctx->chip_class >= GFX7)
839 sctx->last_index_size = -1;
840 }
841
842 if (indirect) {
843 assert(num_draws == 1);
844 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
845
846 assert(indirect_va % 8 == 0);
847
848 si_invalidate_draw_sh_constants(sctx);
849
850 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
851 radeon_emit(cs, 1);
852 radeon_emit(cs, indirect_va);
853 radeon_emit(cs, indirect_va >> 32);
854
855 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(indirect->buffer),
856 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
857
858 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
859
860 assert(indirect->offset % 4 == 0);
861
862 if (index_size) {
863 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
864 radeon_emit(cs, index_va);
865 radeon_emit(cs, index_va >> 32);
866
867 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
868 radeon_emit(cs, index_max_size);
869 }
870
871 if (!sctx->screen->has_draw_indirect_multi) {
872 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT : PKT3_DRAW_INDIRECT, 3,
873 render_cond_bit));
874 radeon_emit(cs, indirect->offset);
875 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
876 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
877 radeon_emit(cs, di_src_sel);
878 } else {
879 uint64_t count_va = 0;
880
881 if (indirect->indirect_draw_count) {
882 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count);
883
884 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, params_buf, RADEON_USAGE_READ,
885 RADEON_PRIO_DRAW_INDIRECT);
886
887 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
888 }
889
890 radeon_emit(cs,
891 PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : PKT3_DRAW_INDIRECT_MULTI, 8,
892 render_cond_bit));
893 radeon_emit(cs, indirect->offset);
894 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
895 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
896 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
897 S_2C3_DRAW_INDEX_ENABLE(1) |
898 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
899 radeon_emit(cs, indirect->draw_count);
900 radeon_emit(cs, count_va);
901 radeon_emit(cs, count_va >> 32);
902 radeon_emit(cs, indirect->stride);
903 radeon_emit(cs, di_src_sel);
904 }
905 } else {
906 int base_vertex;
907
908 /* Register shadowing requires that we always emit PKT3_NUM_INSTANCES. */
909 if (sctx->shadowed_regs ||
910 sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
911 sctx->last_instance_count != instance_count) {
912 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
913 radeon_emit(cs, instance_count);
914 sctx->last_instance_count = instance_count;
915 }
916
917 /* Base vertex and start instance. */
918 base_vertex = original_index_size ? info->index_bias : draws[0].start;
919
920 if (sctx->num_vs_blit_sgprs) {
921 /* Re-emit draw constants after we leave u_blitter. */
922 si_invalidate_draw_sh_constants(sctx);
923
924 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
925 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
926 radeon_emit_array(cs, sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs);
927 } else if (base_vertex != sctx->last_base_vertex ||
928 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
929 info->start_instance != sctx->last_start_instance ||
930 info->drawid != sctx->last_drawid || sh_base_reg != sctx->last_sh_base_reg) {
931 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
932 radeon_emit(cs, base_vertex);
933 radeon_emit(cs, info->start_instance);
934 radeon_emit(cs, info->drawid);
935
936 sctx->last_base_vertex = base_vertex;
937 sctx->last_start_instance = info->start_instance;
938 sctx->last_drawid = info->drawid;
939 sctx->last_sh_base_reg = sh_base_reg;
940 }
941
942 if (index_size) {
943 if (dispatch_prim_discard_cs) {
944 for (unsigned i = 0; i < num_draws; i++) {
945 uint64_t va = index_va + draws[0].start * original_index_size;
946
947 si_dispatch_prim_discard_cs_and_draw(sctx, info, draws[i].count,
948 original_index_size, base_vertex,
949 va, MIN2(index_max_size, draws[i].count));
950 }
951 return;
952 }
953
954 for (unsigned i = 0; i < num_draws; i++) {
955 uint64_t va = index_va + draws[i].start * index_size;
956
957 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
958 radeon_emit(cs, index_max_size);
959 radeon_emit(cs, va);
960 radeon_emit(cs, va >> 32);
961 radeon_emit(cs, draws[i].count);
962 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA |
963 /* NOT_EOP allows merging multiple draws into 1 wave, but only user VGPRs
964 * can be changed between draws and GS fast launch must be disabled.
965 * NOT_EOP doesn't work on gfx9 and older.
966 */
967 S_0287F0_NOT_EOP(sctx->chip_class >= GFX10 &&
968 i < num_draws - 1 &&
969 !(sctx->ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)));
970 }
971 } else {
972 for (unsigned i = 0; i < num_draws; i++) {
973 if (i > 0)
974 radeon_set_sh_reg(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].start);
975
976 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
977 radeon_emit(cs, draws[i].count);
978 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
979 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
980 }
981 if (num_draws > 1 && !sctx->num_vs_blit_sgprs)
982 sctx->last_base_vertex = draws[num_draws - 1].start;
983 }
984 }
985 }
986
si_emit_surface_sync(struct si_context * sctx,struct radeon_cmdbuf * cs,unsigned cp_coher_cntl)987 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned cp_coher_cntl)
988 {
989 bool compute_ib = !sctx->has_graphics || cs == sctx->prim_discard_compute_cs;
990
991 assert(sctx->chip_class <= GFX9);
992
993 if (sctx->chip_class == GFX9 || compute_ib) {
994 /* Flush caches and wait for the caches to assert idle. */
995 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
996 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
997 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
998 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
999 radeon_emit(cs, 0); /* CP_COHER_BASE */
1000 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1001 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1002 } else {
1003 /* ACQUIRE_MEM is only required on a compute ring. */
1004 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1005 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1006 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1007 radeon_emit(cs, 0); /* CP_COHER_BASE */
1008 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1009 }
1010
1011 /* ACQUIRE_MEM has an implicit context roll if the current context
1012 * is busy. */
1013 if (!compute_ib)
1014 sctx->context_roll = true;
1015 }
1016
si_prim_discard_signal_next_compute_ib_start(struct si_context * sctx)1017 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1018 {
1019 if (!si_compute_prim_discard_enabled(sctx))
1020 return;
1021
1022 if (!sctx->barrier_buf) {
1023 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4, &sctx->barrier_buf_offset,
1024 (struct pipe_resource **)&sctx->barrier_buf);
1025 }
1026
1027 /* Emit a placeholder to signal the next compute IB to start.
1028 * See si_compute_prim_discard.c for explanation.
1029 */
1030 uint32_t signal = 1;
1031 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset, 4, V_370_MEM, V_370_ME,
1032 &signal);
1033
1034 sctx->last_pkt3_write_data = &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1035
1036 /* Only the last occurence of WRITE_DATA will be executed.
1037 * The packet will be enabled in si_flush_gfx_cs.
1038 */
1039 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1040 }
1041
gfx10_emit_cache_flush(struct si_context * ctx)1042 void gfx10_emit_cache_flush(struct si_context *ctx)
1043 {
1044 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1045 uint32_t gcr_cntl = 0;
1046 unsigned cb_db_event = 0;
1047 unsigned flags = ctx->flags;
1048
1049 if (!ctx->has_graphics) {
1050 /* Only process compute flags. */
1051 flags &= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
1052 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA |
1053 SI_CONTEXT_CS_PARTIAL_FLUSH;
1054 }
1055
1056 /* We don't need these. */
1057 assert(!(flags & (SI_CONTEXT_VGT_STREAMOUT_SYNC | SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1058
1059 if (flags & SI_CONTEXT_VGT_FLUSH) {
1060 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1061 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1062 }
1063
1064 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1065 ctx->num_cb_cache_flushes++;
1066 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1067 ctx->num_db_cache_flushes++;
1068
1069 if (flags & SI_CONTEXT_INV_ICACHE)
1070 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1071 if (flags & SI_CONTEXT_INV_SCACHE) {
1072 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1073 * to FORWARD when both L1 and L2 are written out (WB or INV).
1074 */
1075 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1076 }
1077 if (flags & SI_CONTEXT_INV_VCACHE)
1078 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1079
1080 /* The L2 cache ops are:
1081 * - INV: - invalidate lines that reflect memory (were loaded from memory)
1082 * - don't touch lines that were overwritten (were stored by gfx clients)
1083 * - WB: - don't touch lines that reflect memory
1084 * - write back lines that were overwritten
1085 * - WB | INV: - invalidate lines that reflect memory
1086 * - write back lines that were overwritten
1087 *
1088 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1089 */
1090 if (flags & SI_CONTEXT_INV_L2) {
1091 /* Writeback and invalidate everything in L2. */
1092 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) | S_586_GLM_INV(1) | S_586_GLM_WB(1);
1093 ctx->num_L2_invalidates++;
1094 } else if (flags & SI_CONTEXT_WB_L2) {
1095 gcr_cntl |= S_586_GL2_WB(1) | S_586_GLM_WB(1) | S_586_GLM_INV(1);
1096 } else if (flags & SI_CONTEXT_INV_L2_METADATA) {
1097 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1098 }
1099
1100 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1101 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1102 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1103 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1104 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1105 }
1106 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1107 /* Flush HTILE. Will wait for idle later. */
1108 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1109 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1110 }
1111
1112 /* First flush CB/DB, then L1/L2. */
1113 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1114
1115 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1116 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1117 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1118 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1119 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1120 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1121 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1122 } else {
1123 assert(0);
1124 }
1125 } else {
1126 /* Wait for graphics shaders to go idle if requested. */
1127 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1129 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1130 /* Only count explicit shader flushes, not implicit ones. */
1131 ctx->num_vs_flushes++;
1132 ctx->num_ps_flushes++;
1133 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1134 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1135 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1136 ctx->num_vs_flushes++;
1137 }
1138 }
1139
1140 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1141 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1142 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1143 ctx->num_cs_flushes++;
1144 ctx->compute_is_busy = false;
1145 }
1146
1147 if (cb_db_event) {
1148 struct si_resource* wait_mem_scratch = unlikely(ctx->ws->cs_is_secure(cs)) ?
1149 ctx->wait_mem_scratch_tmz : ctx->wait_mem_scratch;
1150 /* CB/DB flush and invalidate (or possibly just a wait for a
1151 * meta flush) via RELEASE_MEM.
1152 *
1153 * Combine this with other cache flushes when possible; this
1154 * requires affected shaders to be idle, so do it after the
1155 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1156 * implied).
1157 */
1158 uint64_t va;
1159
1160 /* Do the flush (enqueue the event and wait for it). */
1161 va = wait_mem_scratch->gpu_address;
1162 ctx->wait_mem_number++;
1163
1164 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1165 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1166 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1167 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1168 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1169 assert(G_586_GL2_US(gcr_cntl) == 0);
1170 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1171 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1172 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1173 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1174 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1175
1176 gcr_cntl &= C_586_GLM_WB & C_586_GLM_INV & C_586_GLV_INV & C_586_GL1_INV & C_586_GL2_INV &
1177 C_586_GL2_WB; /* keep SEQ */
1178
1179 si_cp_release_mem(ctx, cs, cb_db_event,
1180 S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) |
1181 S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) |
1182 S_490_SEQ(gcr_seq),
1183 EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1184 EOP_DATA_SEL_VALUE_32BIT, wait_mem_scratch, va, ctx->wait_mem_number,
1185 SI_NOT_QUERY);
1186 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
1187 }
1188
1189 /* Ignore fields that only modify the behavior of other fields. */
1190 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1191 /* Flush caches and wait for the caches to assert idle.
1192 * The cache flush is executed in the ME, but the PFP waits
1193 * for completion.
1194 */
1195 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1196 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1197 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1198 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1199 radeon_emit(cs, 0); /* CP_COHER_BASE */
1200 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1201 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1202 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1203 } else if (cb_db_event || (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH |
1204 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1205 /* We need to ensure that PFP waits as well. */
1206 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1207 radeon_emit(cs, 0);
1208 }
1209
1210 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1211 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1212 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1213 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1214 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1215 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1216 }
1217
1218 ctx->flags = 0;
1219 }
1220
si_emit_cache_flush(struct si_context * sctx)1221 void si_emit_cache_flush(struct si_context *sctx)
1222 {
1223 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1224 uint32_t flags = sctx->flags;
1225
1226 if (!sctx->has_graphics) {
1227 /* Only process compute flags. */
1228 flags &= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
1229 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA |
1230 SI_CONTEXT_CS_PARTIAL_FLUSH;
1231 }
1232
1233 uint32_t cp_coher_cntl = 0;
1234 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB);
1235 const bool is_barrier =
1236 flush_cb_db ||
1237 /* INV_ICACHE == beginning of gfx IB. Checking
1238 * INV_ICACHE fixes corruption for DeusExMD with
1239 * compute-based culling, but I don't know why.
1240 */
1241 flags & (SI_CONTEXT_INV_ICACHE | SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1242 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && sctx->compute_is_busy);
1243
1244 assert(sctx->chip_class <= GFX9);
1245
1246 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1247 sctx->num_cb_cache_flushes++;
1248 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1249 sctx->num_db_cache_flushes++;
1250
1251 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1252 * bit is set. An alternative way is to write SQC_CACHES, but that
1253 * doesn't seem to work reliably. Since the bug doesn't affect
1254 * correctness (it only does more work than necessary) and
1255 * the performance impact is likely negligible, there is no plan
1256 * to add a workaround for it.
1257 */
1258
1259 if (flags & SI_CONTEXT_INV_ICACHE)
1260 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1261 if (flags & SI_CONTEXT_INV_SCACHE)
1262 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1263
1264 if (sctx->chip_class <= GFX8) {
1265 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1266 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) |
1267 S_0085F0_CB1_DEST_BASE_ENA(1) | S_0085F0_CB2_DEST_BASE_ENA(1) |
1268 S_0085F0_CB3_DEST_BASE_ENA(1) | S_0085F0_CB4_DEST_BASE_ENA(1) |
1269 S_0085F0_CB5_DEST_BASE_ENA(1) | S_0085F0_CB6_DEST_BASE_ENA(1) |
1270 S_0085F0_CB7_DEST_BASE_ENA(1);
1271
1272 /* Necessary for DCC */
1273 if (sctx->chip_class == GFX8)
1274 si_cp_release_mem(sctx, cs, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM,
1275 EOP_INT_SEL_NONE, EOP_DATA_SEL_DISCARD, NULL, 0, 0, SI_NOT_QUERY);
1276 }
1277 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1278 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1);
1279 }
1280
1281 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1282 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1283 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1284 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1285 }
1286 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1287 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1288 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1289 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1290 }
1291
1292 /* Wait for shader engines to go idle.
1293 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1294 * for everything including CB/DB cache flushes.
1295 */
1296 if (!flush_cb_db) {
1297 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1298 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1299 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1300 /* Only count explicit shader flushes, not implicit ones
1301 * done by SURFACE_SYNC.
1302 */
1303 sctx->num_vs_flushes++;
1304 sctx->num_ps_flushes++;
1305 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1306 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1307 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1308 sctx->num_vs_flushes++;
1309 }
1310 }
1311
1312 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && sctx->compute_is_busy) {
1313 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1314 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1315 sctx->num_cs_flushes++;
1316 sctx->compute_is_busy = false;
1317 }
1318
1319 /* VGT state synchronization. */
1320 if (flags & SI_CONTEXT_VGT_FLUSH) {
1321 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1322 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1323 }
1324 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1325 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1326 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1327 }
1328
1329 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1330 * wait for idle on GFX9. We have to use a TS event.
1331 */
1332 if (sctx->chip_class == GFX9 && flush_cb_db) {
1333 uint64_t va;
1334 unsigned tc_flags, cb_db_event;
1335
1336 /* Set the CB/DB flush event. */
1337 switch (flush_cb_db) {
1338 case SI_CONTEXT_FLUSH_AND_INV_CB:
1339 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1340 break;
1341 case SI_CONTEXT_FLUSH_AND_INV_DB:
1342 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1343 break;
1344 default:
1345 /* both CB & DB */
1346 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1347 }
1348
1349 /* These are the only allowed combinations. If you need to
1350 * do multiple operations at once, do them separately.
1351 * All operations that invalidate L2 also seem to invalidate
1352 * metadata. Volatile (VOL) and WC flushes are not listed here.
1353 *
1354 * TC | TC_WB = writeback & invalidate L2 & L1
1355 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1356 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1357 * TC | TC_NC = invalidate L2 for MTYPE == NC
1358 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1359 * TCL1 = invalidate L1
1360 */
1361 tc_flags = 0;
1362
1363 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1364 tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_MD_ACTION_ENA;
1365 }
1366
1367 /* Ideally flush TC together with CB/DB. */
1368 if (flags & SI_CONTEXT_INV_L2) {
1369 /* Writeback and invalidate everything in L2 & L1. */
1370 tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA;
1371
1372 /* Clear the flags. */
1373 flags &= ~(SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_VCACHE);
1374 sctx->num_L2_invalidates++;
1375 }
1376
1377 /* Do the flush (enqueue the event and wait for it). */
1378 struct si_resource* wait_mem_scratch = unlikely(sctx->ws->cs_is_secure(cs)) ?
1379 sctx->wait_mem_scratch_tmz : sctx->wait_mem_scratch;
1380 va = wait_mem_scratch->gpu_address;
1381 sctx->wait_mem_number++;
1382
1383 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
1384 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT,
1385 wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY);
1386 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
1387 }
1388
1389 /* Make sure ME is idle (it executes most packets) before continuing.
1390 * This prevents read-after-write hazards between PFP and ME.
1391 */
1392 if (sctx->has_graphics &&
1393 (cp_coher_cntl || (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_INV_VCACHE |
1394 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2)))) {
1395 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1396 radeon_emit(cs, 0);
1397 }
1398
1399 /* GFX6-GFX8 only:
1400 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1401 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1402 *
1403 * cp_coher_cntl should contain all necessary flags except TC flags
1404 * at this point.
1405 *
1406 * GFX6-GFX7 don't support L2 write-back.
1407 */
1408 if (flags & SI_CONTEXT_INV_L2 || (sctx->chip_class <= GFX7 && (flags & SI_CONTEXT_WB_L2))) {
1409 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1410 * WB must be set on GFX8+ when TC_ACTION is set.
1411 */
1412 si_emit_surface_sync(sctx, sctx->gfx_cs,
1413 cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) |
1414 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1415 cp_coher_cntl = 0;
1416 sctx->num_L2_invalidates++;
1417 } else {
1418 /* L1 invalidation and L2 writeback must be done separately,
1419 * because both operations can't be done together.
1420 */
1421 if (flags & SI_CONTEXT_WB_L2) {
1422 /* WB = write-back
1423 * NC = apply to non-coherent MTYPEs
1424 * (i.e. MTYPE <= 1, which is what we use everywhere)
1425 *
1426 * WB doesn't work without NC.
1427 */
1428 si_emit_surface_sync(
1429 sctx, sctx->gfx_cs,
1430 cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1));
1431 cp_coher_cntl = 0;
1432 sctx->num_L2_writebacks++;
1433 }
1434 if (flags & SI_CONTEXT_INV_VCACHE) {
1435 /* Invalidate per-CU VMEM L1. */
1436 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1));
1437 cp_coher_cntl = 0;
1438 }
1439 }
1440
1441 /* If TC flushes haven't cleared this... */
1442 if (cp_coher_cntl)
1443 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1444
1445 if (is_barrier)
1446 si_prim_discard_signal_next_compute_ib_start(sctx);
1447
1448 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1449 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1450 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1451 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1452 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1453 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1454 }
1455
1456 sctx->flags = 0;
1457 }
1458
1459 ALWAYS_INLINE
si_upload_vertex_buffer_descriptors(struct si_context * sctx)1460 static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1461 {
1462 unsigned i, count = sctx->num_vertex_elements;
1463 uint32_t *ptr;
1464
1465 struct si_vertex_elements *velems = sctx->vertex_elements;
1466 unsigned alloc_size = velems->vb_desc_list_alloc_size;
1467
1468 if (alloc_size) {
1469 /* Vertex buffer descriptors are the only ones which are uploaded
1470 * directly through a staging buffer and don't go through
1471 * the fine-grained upload path.
1472 */
1473 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1474 si_optimal_tcc_alignment(sctx, alloc_size), &sctx->vb_descriptors_offset,
1475 (struct pipe_resource **)&sctx->vb_descriptors_buffer, (void **)&ptr);
1476 if (!sctx->vb_descriptors_buffer) {
1477 sctx->vb_descriptors_offset = 0;
1478 sctx->vb_descriptors_gpu_list = NULL;
1479 return false;
1480 }
1481
1482 sctx->vb_descriptors_gpu_list = ptr;
1483 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1484 RADEON_PRIO_DESCRIPTORS);
1485 sctx->vertex_buffer_pointer_dirty = true;
1486 sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
1487 } else {
1488 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
1489 sctx->vertex_buffer_pointer_dirty = false;
1490 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS;
1491 }
1492
1493 assert(count <= SI_MAX_ATTRIBS);
1494
1495 unsigned first_vb_use_mask = velems->first_vb_use_mask;
1496 unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs;
1497
1498 for (i = 0; i < count; i++) {
1499 struct pipe_vertex_buffer *vb;
1500 struct si_resource *buf;
1501 unsigned vbo_index = velems->vertex_buffer_index[i];
1502 uint32_t *desc = i < num_vbos_in_user_sgprs ? &sctx->vb_descriptor_user_sgprs[i * 4]
1503 : &ptr[(i - num_vbos_in_user_sgprs) * 4];
1504
1505 vb = &sctx->vertex_buffer[vbo_index];
1506 buf = si_resource(vb->buffer.resource);
1507 if (!buf) {
1508 memset(desc, 0, 16);
1509 continue;
1510 }
1511
1512 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->src_offset[i];
1513
1514 if (offset >= buf->b.b.width0) {
1515 assert(offset < buf->b.b.width0);
1516 memset(desc, 0, 16);
1517 continue;
1518 }
1519
1520 uint64_t va = buf->gpu_address + offset;
1521
1522 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1523 if (sctx->chip_class != GFX8 && vb->stride) {
1524 /* Round up by rounding down and adding 1 */
1525 num_records = (num_records - velems->format_size[i]) / vb->stride + 1;
1526 }
1527 assert(num_records >= 0 && num_records <= UINT_MAX);
1528
1529 uint32_t rsrc_word3 = velems->rsrc_word3[i];
1530
1531 /* OOB_SELECT chooses the out-of-bounds check:
1532 * - 1: index >= NUM_RECORDS (Structured)
1533 * - 3: offset >= NUM_RECORDS (Raw)
1534 */
1535 if (sctx->chip_class >= GFX10)
1536 rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED
1537 : V_008F0C_OOB_SELECT_RAW);
1538
1539 desc[0] = va;
1540 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride);
1541 desc[2] = num_records;
1542 desc[3] = rsrc_word3;
1543
1544 if (first_vb_use_mask & (1 << i)) {
1545 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(vb->buffer.resource),
1546 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1547 }
1548 }
1549
1550 /* Don't flush the const cache. It would have a very negative effect
1551 * on performance (confirmed by testing). New descriptors are always
1552 * uploaded to a fresh new buffer, so I don't think flushing the const
1553 * cache is needed. */
1554 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1555 sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0;
1556 sctx->vertex_buffers_dirty = false;
1557 return true;
1558 }
1559
si_get_draw_start_count(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_start_count * draws,unsigned num_draws,unsigned * start,unsigned * count)1560 static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_draw_info *info,
1561 const struct pipe_draw_start_count *draws,
1562 unsigned num_draws, unsigned *start, unsigned *count)
1563 {
1564 struct pipe_draw_indirect_info *indirect = info->indirect;
1565
1566 if (indirect) {
1567 unsigned indirect_count;
1568 struct pipe_transfer *transfer;
1569 unsigned begin, end;
1570 unsigned map_size;
1571 unsigned *data;
1572
1573 if (indirect->indirect_draw_count) {
1574 data = pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count,
1575 indirect->indirect_draw_count_offset, sizeof(unsigned),
1576 PIPE_MAP_READ, &transfer);
1577
1578 indirect_count = *data;
1579
1580 pipe_buffer_unmap(&sctx->b, transfer);
1581 } else {
1582 indirect_count = indirect->draw_count;
1583 }
1584
1585 if (!indirect_count) {
1586 *start = *count = 0;
1587 return;
1588 }
1589
1590 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1591 data = pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size,
1592 PIPE_MAP_READ, &transfer);
1593
1594 begin = UINT_MAX;
1595 end = 0;
1596
1597 for (unsigned i = 0; i < indirect_count; ++i) {
1598 unsigned count = data[0];
1599 unsigned start = data[2];
1600
1601 if (count > 0) {
1602 begin = MIN2(begin, start);
1603 end = MAX2(end, start + count);
1604 }
1605
1606 data += indirect->stride / sizeof(unsigned);
1607 }
1608
1609 pipe_buffer_unmap(&sctx->b, transfer);
1610
1611 if (begin < end) {
1612 *start = begin;
1613 *count = end - begin;
1614 } else {
1615 *start = *count = 0;
1616 }
1617 } else {
1618 unsigned min_element = UINT_MAX;
1619 unsigned max_element = 0;
1620
1621 for (unsigned i = 0; i < num_draws; i++) {
1622 min_element = MIN2(min_element, draws[i].start);
1623 max_element = MAX2(max_element, draws[i].start + draws[i].count);
1624 }
1625
1626 *start = min_element;
1627 *count = max_element - min_element;
1628 }
1629 }
1630
si_emit_all_states(struct si_context * sctx,const struct pipe_draw_info * info,enum pipe_prim_type prim,unsigned instance_count,unsigned min_vertex_count,bool primitive_restart,unsigned skip_atom_mask)1631 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1632 enum pipe_prim_type prim, unsigned instance_count,
1633 unsigned min_vertex_count, bool primitive_restart,
1634 unsigned skip_atom_mask)
1635 {
1636 unsigned num_patches = 0;
1637
1638 si_emit_rasterizer_prim_state(sctx);
1639 if (sctx->tes_shader.cso)
1640 si_emit_derived_tess_state(sctx, info, &num_patches);
1641
1642 /* Emit state atoms. */
1643 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1644 while (mask)
1645 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1646
1647 sctx->dirty_atoms &= skip_atom_mask;
1648
1649 /* Emit states. */
1650 mask = sctx->dirty_states;
1651 while (mask) {
1652 unsigned i = u_bit_scan(&mask);
1653 struct si_pm4_state *state = sctx->queued.array[i];
1654
1655 if (!state || sctx->emitted.array[i] == state)
1656 continue;
1657
1658 si_pm4_emit(sctx, state);
1659 sctx->emitted.array[i] = state;
1660 }
1661 sctx->dirty_states = 0;
1662
1663 /* Emit draw states. */
1664 si_emit_vs_state(sctx, info);
1665 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count, primitive_restart,
1666 min_vertex_count);
1667 }
1668
si_all_vs_resources_read_only(struct si_context * sctx,struct pipe_resource * indexbuf)1669 static bool si_all_vs_resources_read_only(struct si_context *sctx, struct pipe_resource *indexbuf)
1670 {
1671 struct radeon_winsys *ws = sctx->ws;
1672 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1673
1674 /* Index buffer. */
1675 if (indexbuf && ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf, RADEON_USAGE_WRITE))
1676 goto has_write_reference;
1677
1678 /* Vertex buffers. */
1679 struct si_vertex_elements *velems = sctx->vertex_elements;
1680 unsigned num_velems = velems->count;
1681
1682 for (unsigned i = 0; i < num_velems; i++) {
1683 if (!((1 << i) & velems->first_vb_use_mask))
1684 continue;
1685
1686 unsigned vb_index = velems->vertex_buffer_index[i];
1687 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1688 if (!res)
1689 continue;
1690
1691 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf, RADEON_USAGE_WRITE))
1692 goto has_write_reference;
1693 }
1694
1695 /* Constant and shader buffers. */
1696 struct si_descriptors *buffers =
1697 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1698 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1699 unsigned index = buffers->first_active_slot + i;
1700 struct pipe_resource *res = sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1701 if (!res)
1702 continue;
1703
1704 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf, RADEON_USAGE_WRITE))
1705 goto has_write_reference;
1706 }
1707
1708 /* Samplers. */
1709 struct si_shader_selector *vs = sctx->vs_shader.cso;
1710 if (vs->info.base.textures_used) {
1711 unsigned num_samplers = util_last_bit(vs->info.base.textures_used);
1712
1713 for (unsigned i = 0; i < num_samplers; i++) {
1714 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1715 if (!view)
1716 continue;
1717
1718 if (ws->cs_is_buffer_referenced(cs, si_resource(view->texture)->buf, RADEON_USAGE_WRITE))
1719 goto has_write_reference;
1720 }
1721 }
1722
1723 /* Images. */
1724 unsigned num_images = vs->info.base.num_images;
1725 if (num_images) {
1726 for (unsigned i = 0; i < num_images; i++) {
1727 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1728 if (!res)
1729 continue;
1730
1731 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf, RADEON_USAGE_WRITE))
1732 goto has_write_reference;
1733 }
1734 }
1735
1736 return true;
1737
1738 has_write_reference:
1739 /* If the current gfx IB has enough packets, flush it to remove write
1740 * references to buffers.
1741 */
1742 if (cs->prev_dw + cs->current.cdw > 2048) {
1743 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1744 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1745 return true;
1746 }
1747 return false;
1748 }
1749
pd_msg(const char * s)1750 static ALWAYS_INLINE bool pd_msg(const char *s)
1751 {
1752 if (SI_PRIM_DISCARD_DEBUG)
1753 printf("PD failed: %s\n", s);
1754 return false;
1755 }
1756
si_multi_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,const struct pipe_draw_start_count * draws,unsigned num_draws)1757 static void si_multi_draw_vbo(struct pipe_context *ctx,
1758 const struct pipe_draw_info *info,
1759 const struct pipe_draw_start_count *draws,
1760 unsigned num_draws)
1761 {
1762 struct si_context *sctx = (struct si_context *)ctx;
1763 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1764 struct pipe_resource *indexbuf = info->index.resource;
1765 unsigned dirty_tex_counter, dirty_buf_counter;
1766 enum pipe_prim_type rast_prim, prim = info->mode;
1767 unsigned index_size = info->index_size;
1768 unsigned index_offset = info->indirect ? draws[0].start * index_size : 0;
1769 unsigned instance_count = info->instance_count;
1770 bool primitive_restart =
1771 info->primitive_restart &&
1772 (!sctx->screen->options.prim_restart_tri_strips_only ||
1773 (prim != PIPE_PRIM_TRIANGLE_STRIP && prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1774
1775 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1776 * no workaround for indirect draws, but we can at least skip
1777 * direct draws.
1778 */
1779 if (unlikely(!info->indirect && !instance_count))
1780 return;
1781
1782 struct si_shader_selector *vs = sctx->vs_shader.cso;
1783 if (unlikely(!vs || sctx->num_vertex_elements < vs->num_vs_inputs ||
1784 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1785 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1786 assert(0);
1787 return;
1788 }
1789
1790 /* Recompute and re-emit the texture resource states if needed. */
1791 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1792 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1793 sctx->last_dirty_tex_counter = dirty_tex_counter;
1794 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1795 sctx->framebuffer.dirty_zsbuf = true;
1796 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1797 si_update_all_texture_descriptors(sctx);
1798 }
1799
1800 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1801 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1802 sctx->last_dirty_buf_counter = dirty_buf_counter;
1803 /* Rebind all buffers unconditionally. */
1804 si_rebind_buffer(sctx, NULL);
1805 }
1806
1807 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1808
1809 /* Set the rasterization primitive type.
1810 *
1811 * This must be done after si_decompress_textures, which can call
1812 * draw_vbo recursively, and before si_update_shaders, which uses
1813 * current_rast_prim for this draw_vbo call. */
1814 if (sctx->gs_shader.cso) {
1815 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1816 rast_prim = sctx->gs_shader.cso->rast_prim;
1817 } else if (sctx->tes_shader.cso) {
1818 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1819 rast_prim = sctx->tes_shader.cso->rast_prim;
1820 } else if (util_rast_prim_is_triangles(prim)) {
1821 rast_prim = PIPE_PRIM_TRIANGLES;
1822 } else {
1823 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1824 rast_prim = prim;
1825 }
1826
1827 if (rast_prim != sctx->current_rast_prim) {
1828 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1829 util_prim_is_points_or_lines(rast_prim))
1830 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1831
1832 sctx->current_rast_prim = rast_prim;
1833 sctx->do_update_shaders = true;
1834 }
1835
1836 if (sctx->tes_shader.cso && sctx->screen->info.has_ls_vgpr_init_bug) {
1837 /* Determine whether the LS VGPR fix should be applied.
1838 *
1839 * It is only required when num input CPs > num output CPs,
1840 * which cannot happen with the fixed function TCS. We should
1841 * also update this bit when switching from TCS to fixed
1842 * function TCS.
1843 */
1844 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1845 bool ls_vgpr_fix =
1846 tcs && info->vertices_per_patch > tcs->info.base.tess.tcs_vertices_out;
1847
1848 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1849 sctx->ls_vgpr_fix = ls_vgpr_fix;
1850 sctx->do_update_shaders = true;
1851 }
1852 }
1853
1854 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1855 /* Determine whether the GS triangle strip adjacency fix should
1856 * be applied. Rotate every other triangle if
1857 * - triangle strips with adjacency are fed to the GS and
1858 * - primitive restart is disabled (the rotation doesn't help
1859 * when the restart occurs after an odd number of triangles).
1860 */
1861 bool gs_tri_strip_adj_fix =
1862 !sctx->tes_shader.cso && prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY && !primitive_restart;
1863
1864 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1865 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1866 sctx->do_update_shaders = true;
1867 }
1868 }
1869
1870 if (index_size) {
1871 /* Translate or upload, if needed. */
1872 /* 8-bit indices are supported on GFX8. */
1873 if (sctx->chip_class <= GFX7 && index_size == 1) {
1874 unsigned start, count, start_offset, size, offset;
1875 void *ptr;
1876
1877 si_get_draw_start_count(sctx, info, draws, num_draws, &start, &count);
1878 start_offset = start * 2;
1879 size = count * 2;
1880
1881 indexbuf = NULL;
1882 u_upload_alloc(ctx->stream_uploader, start_offset, size,
1883 si_optimal_tcc_alignment(sctx, size), &offset, &indexbuf, &ptr);
1884 if (unlikely(!indexbuf))
1885 return;
1886
1887 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0, index_offset + start, count, ptr);
1888
1889 /* info->start will be added by the drawing code */
1890 index_offset = offset - start_offset;
1891 index_size = 2;
1892 } else if (info->has_user_indices) {
1893 unsigned start_offset;
1894
1895 assert(!info->indirect);
1896 assert(num_draws == 1);
1897 start_offset = draws[0].start * index_size;
1898
1899 indexbuf = NULL;
1900 u_upload_data(ctx->stream_uploader, start_offset, draws[0].count * index_size,
1901 sctx->screen->info.tcc_cache_line_size,
1902 (char *)info->index.user + start_offset, &index_offset, &indexbuf);
1903 if (unlikely(!indexbuf))
1904 return;
1905
1906 /* info->start will be added by the drawing code */
1907 index_offset -= start_offset;
1908 } else if (sctx->chip_class <= GFX7 && si_resource(indexbuf)->TC_L2_dirty) {
1909 /* GFX8 reads index buffers through TC L2, so it doesn't
1910 * need this. */
1911 sctx->flags |= SI_CONTEXT_WB_L2;
1912 si_resource(indexbuf)->TC_L2_dirty = false;
1913 }
1914 }
1915
1916 bool dispatch_prim_discard_cs = false;
1917 bool prim_discard_cs_instancing = false;
1918 unsigned original_index_size = index_size;
1919 unsigned avg_direct_count = 0;
1920 unsigned min_direct_count = 0;
1921 unsigned total_direct_count = 0;
1922
1923 if (info->indirect) {
1924 struct pipe_draw_indirect_info *indirect = info->indirect;
1925
1926 /* Add the buffer size for memory checking in need_cs_space. */
1927 si_context_add_resource_size(sctx, indirect->buffer);
1928
1929 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1930 if (sctx->chip_class <= GFX8) {
1931 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1932 sctx->flags |= SI_CONTEXT_WB_L2;
1933 si_resource(indirect->buffer)->TC_L2_dirty = false;
1934 }
1935
1936 if (indirect->indirect_draw_count &&
1937 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1938 sctx->flags |= SI_CONTEXT_WB_L2;
1939 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1940 }
1941 }
1942 } else {
1943 min_direct_count = num_draws ? UINT_MAX : 0;
1944 for (unsigned i = 0; i < num_draws; i++) {
1945 unsigned count = draws[i].count;
1946
1947 total_direct_count += count;
1948 min_direct_count = MIN2(min_direct_count, count);
1949 }
1950 avg_direct_count = (total_direct_count / num_draws) * instance_count;
1951 }
1952
1953 /* Determine if we can use the primitive discard compute shader. */
1954 if (si_compute_prim_discard_enabled(sctx) &&
1955 (avg_direct_count > sctx->prim_discard_vertex_count_threshold
1956 ? (sctx->compute_num_verts_rejected += total_direct_count, true)
1957 : /* Add, then return true. */
1958 (sctx->compute_num_verts_ineligible += total_direct_count,
1959 false)) && /* Add, then return false. */
1960 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1961 (primitive_restart ?
1962 /* Supported prim types with primitive restart: */
1963 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1964 /* Disallow instancing with primitive restart: */
1965 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart"))
1966 :
1967 /* Supported prim types without primitive restart + allow instancing: */
1968 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1969 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1970 /* Instancing is limited to 16-bit indices, because InstanceID is packed into
1971 VertexID. */
1972 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1973 (instance_count == 1 ||
1974 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1975 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1976 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1977 (!sctx->render_cond || pd_msg("render condition")) &&
1978 /* Forced enablement ignores pipeline statistics queries. */
1979 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1980 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1981 pd_msg("pipestat or primgen query")) &&
1982 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1983 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1984 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1985 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1986 !rs->polygon_mode_enabled &&
1987 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1988 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1989 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1990 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1991 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1992 !sctx->vs_shader.cso->info.base.vs.window_space_position &&
1993 !sctx->vs_shader.cso->so.num_outputs &&
1994 #else
1995 (sctx->vs_shader.cso->prim_discard_cs_allowed ||
1996 pd_msg("VS shader uses unsupported features")) &&
1997 #endif
1998 /* Check that all buffers are used for read only, because compute
1999 * dispatches can run ahead. */
2000 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) ||
2001 pd_msg("write reference"))) {
2002 switch (si_prepare_prim_discard_or_split_draw(sctx, info, draws, num_draws,
2003 primitive_restart, total_direct_count)) {
2004 case SI_PRIM_DISCARD_ENABLED:
2005 original_index_size = index_size;
2006 prim_discard_cs_instancing = instance_count > 1;
2007 dispatch_prim_discard_cs = true;
2008
2009 /* The compute shader changes/lowers the following: */
2010 prim = PIPE_PRIM_TRIANGLES;
2011 index_size = 4;
2012 instance_count = 1;
2013 primitive_restart = false;
2014 sctx->compute_num_verts_rejected -= total_direct_count;
2015 sctx->compute_num_verts_accepted += total_direct_count;
2016 break;
2017 case SI_PRIM_DISCARD_DISABLED:
2018 break;
2019 case SI_PRIM_DISCARD_DRAW_SPLIT:
2020 sctx->compute_num_verts_rejected -= total_direct_count;
2021 goto return_cleanup;
2022 case SI_PRIM_DISCARD_MULTI_DRAW_SPLIT:
2023 goto return_cleanup;
2024 }
2025 }
2026
2027 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
2028 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
2029 sctx->do_update_shaders = true;
2030 }
2031
2032 /* Update NGG culling settings. */
2033 uint8_t old_ngg_culling = sctx->ngg_culling;
2034 struct si_shader_selector *hw_vs;
2035 if (sctx->ngg && !dispatch_prim_discard_cs && rast_prim == PIPE_PRIM_TRIANGLES &&
2036 (hw_vs = si_get_vs(sctx)->cso) &&
2037 (avg_direct_count > hw_vs->ngg_cull_vert_threshold ||
2038 (!index_size &&
2039 avg_direct_count > hw_vs->ngg_cull_nonindexed_fast_launch_vert_threshold &&
2040 prim & ((1 << PIPE_PRIM_TRIANGLES) |
2041 (1 << PIPE_PRIM_TRIANGLE_STRIP))))) {
2042 uint8_t ngg_culling = 0;
2043
2044 if (rs->rasterizer_discard) {
2045 ngg_culling |= SI_NGG_CULL_FRONT_FACE | SI_NGG_CULL_BACK_FACE;
2046 } else {
2047 /* Polygon mode can't use view and small primitive culling,
2048 * because it draws points or lines where the culling depends
2049 * on the point or line width.
2050 */
2051 if (!rs->polygon_mode_enabled)
2052 ngg_culling |= SI_NGG_CULL_VIEW_SMALLPRIMS;
2053
2054 if (sctx->viewports.y_inverted ? rs->cull_back : rs->cull_front)
2055 ngg_culling |= SI_NGG_CULL_FRONT_FACE;
2056 if (sctx->viewports.y_inverted ? rs->cull_front : rs->cull_back)
2057 ngg_culling |= SI_NGG_CULL_BACK_FACE;
2058 }
2059
2060 /* Use NGG fast launch for certain non-indexed primitive types.
2061 * A draw must have at least 1 full primitive.
2062 */
2063 if (ngg_culling && !index_size && min_direct_count >= 3 && !sctx->tes_shader.cso &&
2064 !sctx->gs_shader.cso) {
2065 if (prim == PIPE_PRIM_TRIANGLES)
2066 ngg_culling |= SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST;
2067 else if (prim == PIPE_PRIM_TRIANGLE_STRIP)
2068 ngg_culling |= SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP;
2069 }
2070
2071 if (ngg_culling != old_ngg_culling) {
2072 /* If shader compilation is not ready, this setting will be rejected. */
2073 sctx->ngg_culling = ngg_culling;
2074 sctx->do_update_shaders = true;
2075 }
2076 } else if (old_ngg_culling) {
2077 sctx->ngg_culling = false;
2078 sctx->do_update_shaders = true;
2079 }
2080
2081 if (sctx->shader_has_inlinable_uniforms_mask &
2082 sctx->inlinable_uniforms_valid_mask &
2083 sctx->inlinable_uniforms_dirty_mask) {
2084 sctx->do_update_shaders = true;
2085 /* If inlinable uniforms are not valid, they are also not dirty, so clear all bits. */
2086 sctx->inlinable_uniforms_dirty_mask = 0;
2087 }
2088
2089 if (unlikely(sctx->do_update_shaders)) {
2090 if (unlikely(!si_update_shaders(sctx)))
2091 goto return_cleanup;
2092
2093 /* Insert a VGT_FLUSH when enabling fast launch changes to prevent hangs.
2094 * See issues #2418, #2426, #2434
2095 *
2096 * This is the setting that is used by the draw.
2097 */
2098 uint8_t ngg_culling = si_get_vs(sctx)->current->key.opt.ngg_culling;
2099 if (!(old_ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL) &&
2100 ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
2101 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
2102
2103 /* Set this to the correct value determined by si_update_shaders. */
2104 sctx->ngg_culling = ngg_culling;
2105 }
2106
2107 si_need_gfx_cs_space(sctx, num_draws);
2108
2109 /* If we're using a secure context, determine if cs must be secure or not */
2110 if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
2111 bool secure = si_gfx_resources_check_encrypted(sctx);
2112 if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
2113 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
2114 RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION, NULL);
2115 }
2116 }
2117
2118 /* Since we've called si_context_add_resource_size for vertex buffers,
2119 * this must be called after si_need_cs_space, because we must let
2120 * need_cs_space flush before we add buffers to the buffer list.
2121 */
2122 if (sctx->bo_list_add_all_gfx_resources)
2123 si_gfx_resources_add_all_to_bo_list(sctx);
2124
2125 if (unlikely(!si_upload_graphics_shader_descriptors(sctx) ||
2126 (sctx->vertex_buffers_dirty &&
2127 sctx->num_vertex_elements &&
2128 !si_upload_vertex_buffer_descriptors(sctx))))
2129 goto return_cleanup;
2130
2131 /* Vega10/Raven scissor bug workaround. When any context register is
2132 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2133 * registers must be written too.
2134 */
2135 unsigned masked_atoms = 0;
2136 bool gfx9_scissor_bug = false;
2137
2138 if (sctx->screen->info.has_gfx9_scissor_bug) {
2139 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2140 gfx9_scissor_bug = true;
2141
2142 if (info->count_from_stream_output ||
2143 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2144 sctx->dirty_states & si_states_that_always_roll_context())
2145 sctx->context_roll = true;
2146 }
2147
2148 /* Use optimal packet order based on whether we need to sync the pipeline. */
2149 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB |
2150 SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2151 /* If we have to wait for idle, set all states first, so that all
2152 * SET packets are processed in parallel with previous draw calls.
2153 * Then draw and prefetch at the end. This ensures that the time
2154 * the CUs are idle is very short.
2155 */
2156 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2157 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2158
2159 /* Emit all states except possibly render condition. */
2160 si_emit_all_states(sctx, info, prim, instance_count, min_direct_count,
2161 primitive_restart, masked_atoms);
2162 sctx->emit_cache_flush(sctx);
2163 /* <-- CUs are idle here. */
2164
2165 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
2166 sctx->atoms.s.render_cond.emit(sctx);
2167 sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2168 }
2169
2170 if (gfx9_scissor_bug &&
2171 (sctx->context_roll || si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
2172 sctx->atoms.s.scissors.emit(sctx);
2173 sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2174 }
2175 assert(sctx->dirty_atoms == 0);
2176
2177 si_emit_draw_packets(sctx, info, draws, num_draws,
2178 indexbuf, index_size, index_offset, instance_count,
2179 dispatch_prim_discard_cs, original_index_size);
2180 /* <-- CUs are busy here. */
2181
2182 /* Start prefetches after the draw has been started. Both will run
2183 * in parallel, but starting the draw first is more important.
2184 */
2185 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2186 cik_emit_prefetch_L2(sctx, false);
2187 } else {
2188 /* If we don't wait for idle, start prefetches first, then set
2189 * states, and draw at the end.
2190 */
2191 if (sctx->flags)
2192 sctx->emit_cache_flush(sctx);
2193
2194 /* Only prefetch the API VS and VBO descriptors. */
2195 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2196 cik_emit_prefetch_L2(sctx, true);
2197
2198 si_emit_all_states(sctx, info, prim, instance_count, min_direct_count,
2199 primitive_restart, masked_atoms);
2200
2201 if (gfx9_scissor_bug &&
2202 (sctx->context_roll || si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
2203 sctx->atoms.s.scissors.emit(sctx);
2204 sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2205 }
2206 assert(sctx->dirty_atoms == 0);
2207
2208 si_emit_draw_packets(sctx, info, draws, num_draws,
2209 indexbuf, index_size, index_offset, instance_count,
2210 dispatch_prim_discard_cs, original_index_size);
2211
2212 /* Prefetch the remaining shaders after the draw has been
2213 * started. */
2214 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2215 cik_emit_prefetch_L2(sctx, false);
2216 }
2217
2218 /* Clear the context roll flag after the draw call. */
2219 sctx->context_roll = false;
2220
2221 if (unlikely(sctx->current_saved_cs)) {
2222 si_trace_emit(sctx);
2223 si_log_draw_state(sctx, sctx->log);
2224 }
2225
2226 /* Workaround for a VGT hang when streamout is enabled.
2227 * It must be done after drawing. */
2228 if ((sctx->family == CHIP_HAWAII || sctx->family == CHIP_TONGA || sctx->family == CHIP_FIJI) &&
2229 si_get_strmout_en(sctx)) {
2230 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2231 }
2232
2233 if (unlikely(sctx->decompression_enabled)) {
2234 sctx->num_decompress_calls++;
2235 } else {
2236 sctx->num_draw_calls++;
2237 if (sctx->framebuffer.state.nr_cbufs > 1)
2238 sctx->num_mrt_draw_calls++;
2239 if (primitive_restart)
2240 sctx->num_prim_restart_calls++;
2241 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2242 sctx->num_spill_draw_calls++;
2243 }
2244
2245 return_cleanup:
2246 if (index_size && indexbuf != info->index.resource)
2247 pipe_resource_reference(&indexbuf, NULL);
2248 }
2249
si_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info)2250 static void si_draw_vbo(struct pipe_context *ctx,
2251 const struct pipe_draw_info *info)
2252 {
2253 struct pipe_draw_start_count draw = {info->start, info->count};
2254
2255 si_multi_draw_vbo(ctx, info, &draw, 1);
2256 }
2257
si_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)2258 static void si_draw_rectangle(struct blitter_context *blitter, void *vertex_elements_cso,
2259 blitter_get_vs_func get_vs, int x1, int y1, int x2, int y2,
2260 float depth, unsigned num_instances, enum blitter_attrib_type type,
2261 const union blitter_attrib *attrib)
2262 {
2263 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2264 struct si_context *sctx = (struct si_context *)pipe;
2265
2266 /* Pack position coordinates as signed int16. */
2267 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) | ((uint32_t)(y1 & 0xffff) << 16);
2268 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) | ((uint32_t)(y2 & 0xffff) << 16);
2269 sctx->vs_blit_sh_data[2] = fui(depth);
2270
2271 switch (type) {
2272 case UTIL_BLITTER_ATTRIB_COLOR:
2273 memcpy(&sctx->vs_blit_sh_data[3], attrib->color, sizeof(float) * 4);
2274 break;
2275 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2276 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2277 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord, sizeof(attrib->texcoord));
2278 break;
2279 case UTIL_BLITTER_ATTRIB_NONE:;
2280 }
2281
2282 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2283
2284 struct pipe_draw_info info = {};
2285 info.mode = SI_PRIM_RECTANGLE_LIST;
2286 info.count = 3;
2287 info.instance_count = num_instances;
2288
2289 /* Don't set per-stage shader pointers for VS. */
2290 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2291 sctx->vertex_buffer_pointer_dirty = false;
2292 sctx->vertex_buffer_user_sgprs_dirty = false;
2293
2294 si_draw_vbo(pipe, &info);
2295 }
2296
si_trace_emit(struct si_context * sctx)2297 void si_trace_emit(struct si_context *sctx)
2298 {
2299 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2300 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2301
2302 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf, 0, 4, V_370_MEM, V_370_ME, &trace_id);
2303
2304 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2305 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2306
2307 if (sctx->log)
2308 u_log_flush(sctx->log);
2309 }
2310
si_init_draw_functions(struct si_context * sctx)2311 void si_init_draw_functions(struct si_context *sctx)
2312 {
2313 sctx->b.draw_vbo = si_draw_vbo;
2314 sctx->b.multi_draw = si_multi_draw_vbo;
2315
2316 sctx->blitter->draw_rectangle = si_draw_rectangle;
2317
2318 si_init_ia_multi_vgt_param_table(sctx);
2319 }
2320