1 /* 2 * Copyright (C) 2022 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_ 18 #define ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_ 19 20 #include "../../gs201/libhwc2.1/ExynosHWCModule.h" 21 #include "ExynosHWCHelper.h" 22 23 namespace zuma { 24 25 static const char *early_wakeup_node_0_base = 26 "/sys/devices/platform/19470000.drmdecon/early_wakeup"; 27 28 typedef enum assignOrderType { 29 ORDER_AFBC, 30 ORDER_WCG, 31 ORDER_AXI, 32 } assignOrderType_t; 33 34 typedef enum DPUblockId { 35 DPUF0, 36 DPUF1, 37 DPU_BLOCK_CNT, 38 } DPUblockId_t; 39 40 const std::unordered_map<DPUblockId_t, String8> DPUBlocks = { 41 {DPUF0, String8("DPUF0")}, 42 {DPUF1, String8("DPUF1")}, 43 }; 44 45 typedef enum AXIPortId { 46 AXI0, 47 AXI1, 48 AXI_PORT_MAX_CNT, 49 AXI_DONT_CARE 50 } AXIPortId_t; 51 52 const std::map<AXIPortId_t, String8> AXIPorts = { 53 {AXI0, String8("AXI0")}, 54 {AXI1, String8("AXI1")}, 55 }; 56 57 typedef enum ConstraintRev { 58 CONSTRAINT_NONE = 0, // don't care 59 CONSTRAINT_A0, 60 CONSTRAINT_B0 61 } ConstraintRev_t; 62 63 static const dpp_channel_map_t idma_channel_map[] = { 64 /* GF physical index is switched to change assign order */ 65 /* DECON_IDMA is not used */ 66 {MPP_DPP_GFS, 0, IDMA(0), IDMA(0)}, 67 {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)}, 68 {MPP_DPP_GFS, 1, IDMA(2), IDMA(2)}, 69 {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)}, 70 {MPP_DPP_GFS, 2, IDMA(4), IDMA(4)}, 71 {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)}, 72 {MPP_DPP_GFS, 3, IDMA(6), IDMA(6)}, 73 {MPP_DPP_GFS, 4, IDMA(7), IDMA(7)}, 74 {MPP_DPP_VGRFS, 3, IDMA(8), IDMA(8)}, 75 {MPP_DPP_GFS, 5, IDMA(9), IDMA(9)}, 76 {MPP_DPP_VGRFS, 4, IDMA(10), IDMA(10)}, 77 {MPP_DPP_GFS, 6, IDMA(11), IDMA(11)}, 78 {MPP_DPP_VGRFS, 5, IDMA(12), IDMA(12)}, 79 {MPP_DPP_GFS, 7, IDMA(13), IDMA(13)}, 80 {MPP_P_TYPE_MAX, 0, ODMA_WB, IDMA(14)}, // not idma but.. 81 {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, 82 IDMA(15)} 83 }; 84 85 static const exynos_mpp_t available_otf_mpp_units[] = { 86 // Zuma has 8 Graphics-Only Layers 87 // Zuma has 6 Video-Graphics Layers 88 // Zuma has total 14 Layers 89 90 // DPP0(IDMA_GFS0) in DPUF0 is connected with AXI0 port 91 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 92 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 93 // DPP1(IDMA_VGRFS0) in DPUF0 is connected with AXI0 port 94 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 95 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 96 // DPP2(IDMA_GFS1) in DPUF0 is connected with AXI0 port 97 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 98 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 99 // DPP3(IDMA_VGRFS1) in DPUF0 is connected with AXI0 port 100 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 101 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 102 103 // DPP4(IDMA_GFS2) in DPUF0 is connected with AXI1 port 104 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT, 105 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 106 // DPP5(IDMA_VGRFS2) in DPUF0 is connected with AXI1 port 107 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT, 108 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 109 // DPP6(IDMA_GFS3) in DPUF0 is connected with AXI1 port 110 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS3", 3, 0, HWC_DISPLAY_PRIMARY_BIT, 111 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 112 113 // DPP7(IDMA_GFS4) in DPUF1 is connected with AXI1 port 114 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS4", 4, 0, HWC_DISPLAY_SECONDARY_BIT, 115 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 116 // DPP8(IDMA_VGRFS3) in DPUF1 is connected with AXI1 port 117 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS3", 3, 0, HWC_DISPLAY_SECONDARY_BIT, 118 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 119 // DPP9(IDMA_GFS5) in DPUF1 is connected with AXI1 port 120 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS5", 5, 0, HWC_DISPLAY_SECONDARY_BIT, 121 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 122 // DPP10(IDMA_VGRFS4) in DPUF1 is connected with AXI1 port 123 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS4", 4, 0, HWC_DISPLAY_SECONDARY_BIT, 124 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 125 126 // DPP11(IDMA_GFS6) in DPUF1 is connected with AXI0 port 127 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_DISPLAY_EXTERNAL_BIT, 128 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 129 // DPP12(IDMA_VGRFS5) in DPUF1 is connected with AXI0 port 130 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_DISPLAY_EXTERNAL_BIT, 131 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 132 // DPP13(IDMA_GFS7) in DPUF1 is connected with AXI0 port 133 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_DISPLAY_EXTERNAL_BIT, 134 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 135 }; 136 137 static const std::array<exynos_display_t, 3> AVAILABLE_DISPLAY_UNITS = {{ 138 {HWC_DISPLAY_PRIMARY, 0, "PrimaryDisplay", "/dev/dri/card0", ""}, 139 {HWC_DISPLAY_PRIMARY, 1, "SecondaryDisplay", "/dev/dri/card0", ""}, 140 {HWC_DISPLAY_EXTERNAL, 0, "ExternalDisplay", "/dev/dri/card0", ""} 141 }}; 142 143 /* 144 * Note : 145 * When External or Virtual display is connected, 146 * Primary amount = total - others 147 */ 148 class HWResourceIndexes { 149 private: 150 tdm_attr_t attr; 151 DPUblockId_t DPUBlockNo; 152 AXIPortId_t axiId; 153 int dispType; 154 ConstraintRev_t constraintRev; 155 156 public: HWResourceIndexes(const tdm_attr_t & _attr,const DPUblockId_t & _DPUBlockNo,const AXIPortId_t & _axiId,const int & _dispType,const ConstraintRev_t & _constraintRev)157 HWResourceIndexes(const tdm_attr_t &_attr, const DPUblockId_t &_DPUBlockNo, 158 const AXIPortId_t &_axiId, const int &_dispType, 159 const ConstraintRev_t &_constraintRev) 160 : attr(_attr), 161 DPUBlockNo(_DPUBlockNo), 162 axiId(_axiId), 163 dispType(_dispType), 164 constraintRev(_constraintRev) {} 165 bool operator<(const HWResourceIndexes& rhs) const { 166 if (attr != rhs.attr) return attr < rhs.attr; 167 168 if (DPUBlockNo != rhs.DPUBlockNo) return DPUBlockNo < rhs.DPUBlockNo; 169 170 if (dispType != rhs.dispType) return dispType < rhs.dispType; 171 172 if (axiId != AXI_DONT_CARE && rhs.axiId != AXI_DONT_CARE && axiId != rhs.axiId) 173 return axiId < rhs.axiId; 174 175 if (constraintRev != CONSTRAINT_NONE) return constraintRev < rhs.constraintRev; 176 177 return false; 178 } toString8()179 String8 toString8() const { 180 String8 log; 181 log.appendFormat("attr=%d,DPUBlockNo=%d,axiId=%d,dispType=%d,constraintRev=%d", attr, 182 DPUBlockNo, axiId, dispType, constraintRev); 183 return log; 184 } 185 }; 186 187 typedef struct HWResourceAmounts { 188 int maxAssignedAmount; 189 int totalAmount; 190 } HWResourceAmounts_t; 191 192 /* Note : 193 * When External or Virtual display is connected, 194 * Primary amount = total - others */ 195 196 const std::map<HWResourceIndexes, HWResourceAmounts_t> HWResourceTables = { 197 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 198 CONSTRAINT_NONE), 199 {80, 80}}, 200 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 201 CONSTRAINT_NONE), 202 {0, 80}}, 203 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 204 CONSTRAINT_NONE), 205 {0, 80}}, 206 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 207 CONSTRAINT_NONE), 208 {80, 80}}, 209 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 210 CONSTRAINT_NONE), 211 {80, 80}}, 212 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 213 CONSTRAINT_NONE), 214 {80, 80}}, 215 216 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 217 CONSTRAINT_NONE), 218 {2, 2}}, 219 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 220 CONSTRAINT_NONE), 221 {0, 2}}, 222 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 223 CONSTRAINT_NONE), 224 {0, 2}}, 225 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 226 CONSTRAINT_NONE), 227 {2, 2}}, 228 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 229 CONSTRAINT_NONE), 230 {2, 2}}, 231 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 232 CONSTRAINT_NONE), 233 {2, 2}}, 234 235 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 236 CONSTRAINT_NONE), 237 {2, 2}}, 238 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 239 CONSTRAINT_NONE), 240 {0, 2}}, 241 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 242 CONSTRAINT_NONE), 243 {0, 2}}, 244 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 245 CONSTRAINT_NONE), 246 {2, 2}}, 247 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 248 CONSTRAINT_NONE), 249 {2, 2}}, 250 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 251 CONSTRAINT_NONE), 252 {2, 2}}, 253 254 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 255 CONSTRAINT_NONE), 256 {4, 4}}, 257 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 258 CONSTRAINT_NONE), 259 {0, 4}}, 260 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 261 CONSTRAINT_NONE), 262 {0, 4}}, 263 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 264 CONSTRAINT_NONE), 265 {4, 4}}, 266 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 267 CONSTRAINT_NONE), 268 {4, 4}}, 269 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 270 CONSTRAINT_NONE), 271 {4, 4}}, 272 273 {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 274 CONSTRAINT_NONE), 275 {4, 4}}, 276 {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 277 CONSTRAINT_NONE), 278 {0, 4}}, 279 {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 280 CONSTRAINT_NONE), 281 {0, 4}}, 282 {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 283 CONSTRAINT_NONE), 284 {4, 4}}, 285 {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 286 CONSTRAINT_NONE), 287 {4, 4}}, 288 {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 289 CONSTRAINT_NONE), 290 {4, 4}}, 291 292 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 293 CONSTRAINT_NONE), 294 {2, 2}}, 295 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 296 CONSTRAINT_NONE), 297 {0, 2}}, 298 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 299 CONSTRAINT_NONE), 300 {0, 2}}, 301 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, 302 CONSTRAINT_NONE), 303 {2, 2}}, 304 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, 305 CONSTRAINT_NONE), 306 {2, 2}}, 307 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, 308 CONSTRAINT_NONE), 309 {2, 2}}, 310 311 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, CONSTRAINT_A0), 312 {2, 2}}, 313 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, CONSTRAINT_A0), 314 {0, 2}}, 315 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0), 316 {0, 2}}, 317 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, CONSTRAINT_A0), 318 {2, 2}}, 319 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, CONSTRAINT_A0), 320 {2, 2}}, 321 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0), 322 {2, 2}}, 323 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}}, 324 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {0, 2}}, 325 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}}, 326 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}}, 327 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {0, 2}}, 328 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}}, 329 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}}, 330 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {2, 2}}, 331 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}}, 332 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}}, 333 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {2, 2}}, 334 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}}, 335 }; 336 337 typedef enum lbWidthIndex { 338 LB_W_8_512, 339 LB_W_513_1024, 340 LB_W_1025_1536, 341 LB_W_1537_2048, 342 LB_W_2049_2304, 343 LB_W_2305_2560, 344 LB_W_2561_3072, 345 LB_W_3073_INF, 346 } lbWidthIndex_t; 347 348 typedef struct lbWidthBoundary { 349 uint32_t widthDownto; 350 uint32_t widthUpto; 351 } lbWidthBoundary_t; 352 353 const std::map<lbWidthIndex_t, lbWidthBoundary_t> LB_WIDTH_INDEX_MAP = { 354 {LB_W_8_512, {8, 512}}, 355 {LB_W_513_1024, {513, 1024}}, 356 {LB_W_1025_1536, {1025, 1536}}, 357 {LB_W_1537_2048, {1537, 2048}}, 358 {LB_W_2049_2304, {2049, 2304}}, 359 {LB_W_2305_2560, {2035, 2560}}, 360 {LB_W_2561_3072, {2561, 3072}}, 361 {LB_W_3073_INF, {3073, 0xffff}}, 362 }; 363 364 class sramAmountParams { 365 private: 366 tdm_attr_t attr; 367 uint32_t formatProperty; 368 lbWidthIndex_t widthIndex; 369 370 public: sramAmountParams(tdm_attr_t _attr,uint32_t _formatProperty,lbWidthIndex_t _widthIndex)371 sramAmountParams(tdm_attr_t _attr, uint32_t _formatProperty, lbWidthIndex_t _widthIndex) 372 : attr(_attr), formatProperty(_formatProperty), widthIndex(_widthIndex) {} 373 bool operator<(const sramAmountParams& rhs) const { 374 if (attr != rhs.attr) return attr < rhs.attr; 375 376 if (formatProperty != rhs.formatProperty) return formatProperty < rhs.formatProperty; 377 378 if (widthIndex != rhs.widthIndex) return widthIndex < rhs.widthIndex; 379 380 return false; 381 } 382 }; 383 384 enum { 385 SBWC_Y = 0, 386 SBWC_UV, 387 NON_SBWC_Y, 388 NON_SBWC_UV, 389 }; 390 391 const std::map<sramAmountParams, uint32_t> sramAmountMap = { 392 /** Non rotation **/ 393 /** BIT8 = 32bit format **/ 394 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_8_512), 4}, 395 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_513_1024), 4}, 396 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1025_1536), 8}, 397 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1537_2048), 8}, 398 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2049_2304), 12}, 399 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2305_2560), 12}, 400 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2561_3072), 12}, 401 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_3073_INF), 16}, 402 403 /** 16bit format **/ 404 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_8_512), 2}, 405 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_513_1024), 2}, 406 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1025_1536), 4}, 407 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1537_2048), 4}, 408 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2049_2304), 6}, 409 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2305_2560), 6}, 410 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2561_3072), 6}, 411 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_3073_INF), 8}, 412 413 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_8_512), 1}, 414 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_513_1024), 1}, 415 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1025_1536), 1}, 416 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1537_2048), 1}, 417 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2049_2304), 2}, 418 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2305_2560), 2}, 419 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2561_3072), 2}, 420 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_3073_INF), 2}, 421 422 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_8_512), 2}, 423 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_513_1024), 2}, 424 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1025_1536), 2}, 425 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1537_2048), 2}, 426 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2049_2304), 2}, 427 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2305_2560), 2}, 428 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2561_3072), 2}, 429 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_3073_INF), 2}, 430 431 /** Rotation **/ 432 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_8_512), 4}, 433 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_513_1024), 8}, 434 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1025_1536), 12}, 435 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1537_2048), 16}, 436 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2049_2304), 18}, 437 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2305_2560), 18}, 438 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2561_3072), 18}, 439 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_3073_INF), 18}, 440 441 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_8_512), 2}, 442 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_513_1024), 4}, 443 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1025_1536), 6}, 444 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1537_2048), 8}, 445 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2049_2304), 10}, 446 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2305_2560), 10}, 447 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2561_3072), 10}, 448 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_3073_INF), 10}, 449 450 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_8_512), 2}, 451 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_513_1024), 4}, 452 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1025_1536), 6}, 453 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1537_2048), 8}, 454 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2049_2304), 9}, 455 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2305_2560), 9}, 456 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2561_3072), 9}, 457 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_3073_INF), 9}, 458 459 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_8_512), 2}, 460 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_513_1024), 2}, 461 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1025_1536), 4}, 462 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1537_2048), 4}, 463 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2049_2304), 6}, 464 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2305_2560), 6}, 465 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2561_3072), 6}, 466 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_3073_INF), 6}, 467 468 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_8_512), 2}, 469 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_513_1024), 4}, 470 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1025_1536), 6}, 471 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1537_2048), 8}, 472 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2049_2304), 9}, 473 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2305_2560), 9}, 474 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2561_3072), 9}, 475 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_3073_INF), 9}, 476 477 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_8_512), 2}, 478 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_513_1024), 2}, 479 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1025_1536), 4}, 480 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1537_2048), 4}, 481 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2049_2304), 6}, 482 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2305_2560), 6}, 483 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2561_3072), 6}, 484 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_3073_INF), 6}, 485 486 {sramAmountParams(TDM_ATTR_ITP, BIT8, LB_W_3073_INF), 2}, 487 {sramAmountParams(TDM_ATTR_ITP, BIT10, LB_W_3073_INF), 2}, 488 489 /* It's meaning like ow, 490 * FORMAT_YUV_MASK == has no alpha, FORMAT_RGB_MASK == has alpha */ 491 {sramAmountParams(TDM_ATTR_SCALE, FORMAT_YUV_MASK, LB_W_3073_INF), 12}, 492 {sramAmountParams(TDM_ATTR_SCALE, FORMAT_RGB_MASK, LB_W_3073_INF), 16}}; 493 } // namespace zuma 494 495 #endif // ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_ 496