1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
is_memory_file(unsigned file)48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER ||
54 file == TGSI_FILE_HW_ATOMIC;
55 }
56
57
58 static bool
is_mem_query_inst(enum tgsi_opcode opcode)59 is_mem_query_inst(enum tgsi_opcode opcode)
60 {
61 return opcode == TGSI_OPCODE_RESQ ||
62 opcode == TGSI_OPCODE_TXQ ||
63 opcode == TGSI_OPCODE_TXQS ||
64 opcode == TGSI_OPCODE_LODQ;
65 }
66
67 /**
68 * Is the opcode a "true" texture instruction which samples from a
69 * texture map?
70 */
71 static bool
is_texture_inst(enum tgsi_opcode opcode)72 is_texture_inst(enum tgsi_opcode opcode)
73 {
74 return (!is_mem_query_inst(opcode) &&
75 tgsi_get_opcode_info(opcode)->is_tex);
76 }
77
78
79 /**
80 * Is the opcode an instruction which computes a derivative explicitly or
81 * implicitly?
82 */
83 static bool
computes_derivative(enum tgsi_opcode opcode)84 computes_derivative(enum tgsi_opcode opcode)
85 {
86 if (tgsi_get_opcode_info(opcode)->is_tex) {
87 return opcode != TGSI_OPCODE_TG4 &&
88 opcode != TGSI_OPCODE_TXD &&
89 opcode != TGSI_OPCODE_TXF &&
90 opcode != TGSI_OPCODE_TXF_LZ &&
91 opcode != TGSI_OPCODE_TEX_LZ &&
92 opcode != TGSI_OPCODE_TXL &&
93 opcode != TGSI_OPCODE_TXL2 &&
94 opcode != TGSI_OPCODE_TXQ &&
95 opcode != TGSI_OPCODE_TXQS;
96 }
97
98 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
99 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
100 opcode == TGSI_OPCODE_SAMPLE ||
101 opcode == TGSI_OPCODE_SAMPLE_B ||
102 opcode == TGSI_OPCODE_SAMPLE_C;
103 }
104
105
106 static void
scan_src_operand(struct tgsi_shader_info * info,const struct tgsi_full_instruction * fullinst,const struct tgsi_full_src_register * src,unsigned src_index,unsigned usage_mask_after_swizzle,bool is_interp_instruction,bool * is_mem_inst)107 scan_src_operand(struct tgsi_shader_info *info,
108 const struct tgsi_full_instruction *fullinst,
109 const struct tgsi_full_src_register *src,
110 unsigned src_index,
111 unsigned usage_mask_after_swizzle,
112 bool is_interp_instruction,
113 bool *is_mem_inst)
114 {
115 int ind = src->Register.Index;
116
117 if (info->processor == PIPE_SHADER_COMPUTE &&
118 src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
119 unsigned name, mask;
120
121 name = info->system_value_semantic_name[src->Register.Index];
122
123 switch (name) {
124 case TGSI_SEMANTIC_THREAD_ID:
125 case TGSI_SEMANTIC_BLOCK_ID:
126 mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
127 while (mask) {
128 unsigned i = u_bit_scan(&mask);
129
130 if (name == TGSI_SEMANTIC_THREAD_ID)
131 info->uses_thread_id[i] = true;
132 else
133 info->uses_block_id[i] = true;
134 }
135 break;
136 case TGSI_SEMANTIC_BLOCK_SIZE:
137 /* The block size is translated to IMM with a fixed block size. */
138 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
139 info->uses_block_size = true;
140 break;
141 case TGSI_SEMANTIC_GRID_SIZE:
142 info->uses_grid_size = true;
143 break;
144 }
145 }
146
147 /* Mark which inputs are effectively used */
148 if (src->Register.File == TGSI_FILE_INPUT) {
149 if (src->Register.Indirect) {
150 for (ind = 0; ind < info->num_inputs; ++ind) {
151 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
152 }
153 } else {
154 assert(ind >= 0);
155 assert(ind < PIPE_MAX_SHADER_INPUTS);
156 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
157 }
158
159 if (info->processor == PIPE_SHADER_FRAGMENT) {
160 unsigned name, index, input;
161
162 if (src->Register.Indirect && src->Indirect.ArrayID)
163 input = info->input_array_first[src->Indirect.ArrayID];
164 else
165 input = src->Register.Index;
166
167 name = info->input_semantic_name[input];
168 index = info->input_semantic_index[input];
169
170 if (name == TGSI_SEMANTIC_POSITION &&
171 usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
172 info->reads_z = true;
173
174 if (name == TGSI_SEMANTIC_COLOR)
175 info->colors_read |= usage_mask_after_swizzle << (index * 4);
176
177 /* Process only interpolated varyings. Don't include POSITION.
178 * Don't include integer varyings, because they are not
179 * interpolated. Don't process inputs interpolated by INTERP
180 * opcodes. Those are tracked separately.
181 */
182 if ((!is_interp_instruction || src_index != 0) &&
183 (name == TGSI_SEMANTIC_GENERIC ||
184 name == TGSI_SEMANTIC_TEXCOORD ||
185 name == TGSI_SEMANTIC_COLOR ||
186 name == TGSI_SEMANTIC_BCOLOR ||
187 name == TGSI_SEMANTIC_FOG ||
188 name == TGSI_SEMANTIC_CLIPDIST)) {
189 switch (info->input_interpolate[input]) {
190 case TGSI_INTERPOLATE_COLOR:
191 case TGSI_INTERPOLATE_PERSPECTIVE:
192 switch (info->input_interpolate_loc[input]) {
193 case TGSI_INTERPOLATE_LOC_CENTER:
194 info->uses_persp_center = TRUE;
195 break;
196 case TGSI_INTERPOLATE_LOC_CENTROID:
197 info->uses_persp_centroid = TRUE;
198 break;
199 case TGSI_INTERPOLATE_LOC_SAMPLE:
200 info->uses_persp_sample = TRUE;
201 break;
202 }
203 break;
204 case TGSI_INTERPOLATE_LINEAR:
205 switch (info->input_interpolate_loc[input]) {
206 case TGSI_INTERPOLATE_LOC_CENTER:
207 info->uses_linear_center = TRUE;
208 break;
209 case TGSI_INTERPOLATE_LOC_CENTROID:
210 info->uses_linear_centroid = TRUE;
211 break;
212 case TGSI_INTERPOLATE_LOC_SAMPLE:
213 info->uses_linear_sample = TRUE;
214 break;
215 }
216 break;
217 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
218 }
219 }
220 }
221 }
222
223 if (info->processor == PIPE_SHADER_TESS_CTRL &&
224 src->Register.File == TGSI_FILE_OUTPUT) {
225 unsigned input;
226
227 if (src->Register.Indirect && src->Indirect.ArrayID)
228 input = info->output_array_first[src->Indirect.ArrayID];
229 else
230 input = src->Register.Index;
231
232 switch (info->output_semantic_name[input]) {
233 case TGSI_SEMANTIC_PATCH:
234 info->reads_perpatch_outputs = true;
235 break;
236 case TGSI_SEMANTIC_TESSINNER:
237 case TGSI_SEMANTIC_TESSOUTER:
238 info->reads_tessfactor_outputs = true;
239 break;
240 default:
241 info->reads_pervertex_outputs = true;
242 }
243 }
244
245 /* check for indirect register reads */
246 if (src->Register.Indirect) {
247 info->indirect_files |= (1 << src->Register.File);
248 info->indirect_files_read |= (1 << src->Register.File);
249
250 /* record indirect constant buffer indexing */
251 if (src->Register.File == TGSI_FILE_CONSTANT) {
252 if (src->Register.Dimension) {
253 if (src->Dimension.Indirect)
254 info->const_buffers_indirect = info->const_buffers_declared;
255 else
256 info->const_buffers_indirect |= 1u << src->Dimension.Index;
257 } else {
258 info->const_buffers_indirect |= 1;
259 }
260 }
261 }
262
263 if (src->Register.Dimension && src->Dimension.Indirect)
264 info->dim_indirect_files |= 1u << src->Register.File;
265
266 /* Texture samplers */
267 if (src->Register.File == TGSI_FILE_SAMPLER) {
268 const unsigned index = src->Register.Index;
269
270 assert(fullinst->Instruction.Texture);
271 assert(index < PIPE_MAX_SAMPLERS);
272
273 if (is_texture_inst(fullinst->Instruction.Opcode)) {
274 const unsigned target = fullinst->Texture.Texture;
275 assert(target < TGSI_TEXTURE_UNKNOWN);
276 /* for texture instructions, check that the texture instruction
277 * target matches the previous sampler view declaration (if there
278 * was one.)
279 */
280 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
281 /* probably no sampler view declaration */
282 info->sampler_targets[index] = target;
283 } else {
284 /* Make sure the texture instruction's sampler/target info
285 * agrees with the sampler view declaration.
286 */
287 assert(info->sampler_targets[index] == target);
288 }
289 }
290 }
291
292 if (is_memory_file(src->Register.File) &&
293 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
294 *is_mem_inst = true;
295
296 if (src->Register.File == TGSI_FILE_IMAGE &&
297 (fullinst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
298 fullinst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
299 if (src->Register.Indirect)
300 info->msaa_images_declared = info->images_declared;
301 else
302 info->msaa_images_declared |= 1 << src->Register.Index;
303 }
304
305 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
306 info->writes_memory = TRUE;
307
308 if (src->Register.File == TGSI_FILE_IMAGE) {
309 if (src->Register.Indirect)
310 info->images_atomic = info->images_declared;
311 else
312 info->images_atomic |= 1 << src->Register.Index;
313 } else if (src->Register.File == TGSI_FILE_BUFFER) {
314 if (src->Register.Indirect)
315 info->shader_buffers_atomic = info->shader_buffers_declared;
316 else
317 info->shader_buffers_atomic |= 1 << src->Register.Index;
318 }
319 } else {
320 if (src->Register.File == TGSI_FILE_IMAGE) {
321 if (src->Register.Indirect)
322 info->images_load = info->images_declared;
323 else
324 info->images_load |= 1 << src->Register.Index;
325 } else if (src->Register.File == TGSI_FILE_BUFFER) {
326 if (src->Register.Indirect)
327 info->shader_buffers_load = info->shader_buffers_declared;
328 else
329 info->shader_buffers_load |= 1 << src->Register.Index;
330 }
331 }
332 }
333 }
334
335
336 static void
scan_instruction(struct tgsi_shader_info * info,const struct tgsi_full_instruction * fullinst,unsigned * current_depth)337 scan_instruction(struct tgsi_shader_info *info,
338 const struct tgsi_full_instruction *fullinst,
339 unsigned *current_depth)
340 {
341 unsigned i;
342 bool is_mem_inst = false;
343 bool is_interp_instruction = false;
344 unsigned sampler_src;
345
346 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
347 info->opcode_count[fullinst->Instruction.Opcode]++;
348
349 switch (fullinst->Instruction.Opcode) {
350 case TGSI_OPCODE_IF:
351 case TGSI_OPCODE_UIF:
352 case TGSI_OPCODE_BGNLOOP:
353 (*current_depth)++;
354 info->max_depth = MAX2(info->max_depth, *current_depth);
355 break;
356 case TGSI_OPCODE_ENDIF:
357 case TGSI_OPCODE_ENDLOOP:
358 (*current_depth)--;
359 break;
360 case TGSI_OPCODE_TEX:
361 case TGSI_OPCODE_TEX_LZ:
362 case TGSI_OPCODE_TXB:
363 case TGSI_OPCODE_TXD:
364 case TGSI_OPCODE_TXL:
365 case TGSI_OPCODE_TXP:
366 case TGSI_OPCODE_TXQ:
367 case TGSI_OPCODE_TXQS:
368 case TGSI_OPCODE_TXF:
369 case TGSI_OPCODE_TXF_LZ:
370 case TGSI_OPCODE_TEX2:
371 case TGSI_OPCODE_TXB2:
372 case TGSI_OPCODE_TXL2:
373 case TGSI_OPCODE_TG4:
374 case TGSI_OPCODE_LODQ:
375 sampler_src = fullinst->Instruction.NumSrcRegs - 1;
376 if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
377 info->uses_bindless_samplers = true;
378 break;
379 case TGSI_OPCODE_RESQ:
380 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
381 info->uses_bindless_images = true;
382 break;
383 case TGSI_OPCODE_LOAD:
384 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
385 info->uses_bindless_images = true;
386
387 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
388 info->uses_bindless_buffer_load = true;
389 else
390 info->uses_bindless_image_load = true;
391 }
392 break;
393 case TGSI_OPCODE_ATOMUADD:
394 case TGSI_OPCODE_ATOMXCHG:
395 case TGSI_OPCODE_ATOMCAS:
396 case TGSI_OPCODE_ATOMAND:
397 case TGSI_OPCODE_ATOMOR:
398 case TGSI_OPCODE_ATOMXOR:
399 case TGSI_OPCODE_ATOMUMIN:
400 case TGSI_OPCODE_ATOMUMAX:
401 case TGSI_OPCODE_ATOMIMIN:
402 case TGSI_OPCODE_ATOMIMAX:
403 case TGSI_OPCODE_ATOMFADD:
404 case TGSI_OPCODE_ATOMINC_WRAP:
405 case TGSI_OPCODE_ATOMDEC_WRAP:
406 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
407 info->uses_bindless_images = true;
408
409 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
410 info->uses_bindless_buffer_atomic = true;
411 else
412 info->uses_bindless_image_atomic = true;
413 }
414 break;
415 case TGSI_OPCODE_STORE:
416 if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File)) {
417 info->uses_bindless_images = true;
418
419 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
420 info->uses_bindless_buffer_store = true;
421 else
422 info->uses_bindless_image_store = true;
423 }
424 break;
425 case TGSI_OPCODE_FBFETCH:
426 info->uses_fbfetch = true;
427 break;
428 default:
429 break;
430 }
431
432 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
433 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
434 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
435 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
436 unsigned input;
437
438 is_interp_instruction = true;
439
440 if (src0->Register.Indirect && src0->Indirect.ArrayID)
441 input = info->input_array_first[src0->Indirect.ArrayID];
442 else
443 input = src0->Register.Index;
444
445 /* For the INTERP opcodes, the interpolation is always
446 * PERSPECTIVE unless LINEAR is specified.
447 */
448 switch (info->input_interpolate[input]) {
449 case TGSI_INTERPOLATE_COLOR:
450 case TGSI_INTERPOLATE_CONSTANT:
451 case TGSI_INTERPOLATE_PERSPECTIVE:
452 switch (fullinst->Instruction.Opcode) {
453 case TGSI_OPCODE_INTERP_CENTROID:
454 info->uses_persp_opcode_interp_centroid = TRUE;
455 break;
456 case TGSI_OPCODE_INTERP_OFFSET:
457 info->uses_persp_opcode_interp_offset = TRUE;
458 break;
459 case TGSI_OPCODE_INTERP_SAMPLE:
460 info->uses_persp_opcode_interp_sample = TRUE;
461 break;
462 }
463 break;
464
465 case TGSI_INTERPOLATE_LINEAR:
466 switch (fullinst->Instruction.Opcode) {
467 case TGSI_OPCODE_INTERP_CENTROID:
468 info->uses_linear_opcode_interp_centroid = TRUE;
469 break;
470 case TGSI_OPCODE_INTERP_OFFSET:
471 info->uses_linear_opcode_interp_offset = TRUE;
472 break;
473 case TGSI_OPCODE_INTERP_SAMPLE:
474 info->uses_linear_opcode_interp_sample = TRUE;
475 break;
476 }
477 break;
478 }
479 }
480
481 if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
482 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
483 fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
484 fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
485 fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
486 fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
487 fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
488 fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
489 info->uses_doubles = TRUE;
490
491 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
492 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
493 tgsi_util_get_inst_usage_mask(fullinst, i),
494 is_interp_instruction, &is_mem_inst);
495
496 if (fullinst->Src[i].Register.Indirect) {
497 struct tgsi_full_src_register src = {{0}};
498
499 src.Register.File = fullinst->Src[i].Indirect.File;
500 src.Register.Index = fullinst->Src[i].Indirect.Index;
501
502 scan_src_operand(info, fullinst, &src, -1,
503 1 << fullinst->Src[i].Indirect.Swizzle,
504 false, NULL);
505 }
506
507 if (fullinst->Src[i].Register.Dimension &&
508 fullinst->Src[i].Dimension.Indirect) {
509 struct tgsi_full_src_register src = {{0}};
510
511 src.Register.File = fullinst->Src[i].DimIndirect.File;
512 src.Register.Index = fullinst->Src[i].DimIndirect.Index;
513
514 scan_src_operand(info, fullinst, &src, -1,
515 1 << fullinst->Src[i].DimIndirect.Swizzle,
516 false, NULL);
517 }
518 }
519
520 if (fullinst->Instruction.Texture) {
521 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
522 struct tgsi_full_src_register src = {{0}};
523
524 src.Register.File = fullinst->TexOffsets[i].File;
525 src.Register.Index = fullinst->TexOffsets[i].Index;
526
527 /* The usage mask is suboptimal but should be safe. */
528 scan_src_operand(info, fullinst, &src, -1,
529 (1 << fullinst->TexOffsets[i].SwizzleX) |
530 (1 << fullinst->TexOffsets[i].SwizzleY) |
531 (1 << fullinst->TexOffsets[i].SwizzleZ),
532 false, &is_mem_inst);
533 }
534 }
535
536 /* check for indirect register writes */
537 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
538 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
539
540 if (dst->Register.Indirect) {
541 struct tgsi_full_src_register src = {{0}};
542
543 src.Register.File = dst->Indirect.File;
544 src.Register.Index = dst->Indirect.Index;
545
546 scan_src_operand(info, fullinst, &src, -1,
547 1 << dst->Indirect.Swizzle, false, NULL);
548
549 info->indirect_files |= (1 << dst->Register.File);
550 info->indirect_files_written |= (1 << dst->Register.File);
551 }
552
553 if (dst->Register.Dimension && dst->Dimension.Indirect) {
554 struct tgsi_full_src_register src = {{0}};
555
556 src.Register.File = dst->DimIndirect.File;
557 src.Register.Index = dst->DimIndirect.Index;
558
559 scan_src_operand(info, fullinst, &src, -1,
560 1 << dst->DimIndirect.Swizzle, false, NULL);
561
562 info->dim_indirect_files |= 1u << dst->Register.File;
563 }
564
565 if (is_memory_file(dst->Register.File)) {
566 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
567
568 is_mem_inst = true;
569 info->writes_memory = TRUE;
570
571 if (dst->Register.File == TGSI_FILE_IMAGE) {
572 if (fullinst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
573 fullinst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
574 if (dst->Register.Indirect)
575 info->msaa_images_declared = info->images_declared;
576 else
577 info->msaa_images_declared |= 1 << dst->Register.Index;
578 }
579
580 if (dst->Register.Indirect)
581 info->images_store = info->images_declared;
582 else
583 info->images_store |= 1 << dst->Register.Index;
584 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
585 if (dst->Register.Indirect)
586 info->shader_buffers_store = info->shader_buffers_declared;
587 else
588 info->shader_buffers_store |= 1 << dst->Register.Index;
589 }
590 }
591 }
592
593 if (is_mem_inst)
594 info->num_memory_instructions++;
595
596 if (computes_derivative(fullinst->Instruction.Opcode))
597 info->uses_derivatives = true;
598
599 info->num_instructions++;
600 }
601
602
603 static void
scan_declaration(struct tgsi_shader_info * info,const struct tgsi_full_declaration * fulldecl)604 scan_declaration(struct tgsi_shader_info *info,
605 const struct tgsi_full_declaration *fulldecl)
606 {
607 const uint file = fulldecl->Declaration.File;
608 const unsigned procType = info->processor;
609 uint reg;
610
611 if (fulldecl->Declaration.Array) {
612 unsigned array_id = fulldecl->Array.ArrayID;
613
614 switch (file) {
615 case TGSI_FILE_INPUT:
616 assert(array_id < ARRAY_SIZE(info->input_array_first));
617 info->input_array_first[array_id] = fulldecl->Range.First;
618 info->input_array_last[array_id] = fulldecl->Range.Last;
619 break;
620 case TGSI_FILE_OUTPUT:
621 assert(array_id < ARRAY_SIZE(info->output_array_first));
622 info->output_array_first[array_id] = fulldecl->Range.First;
623 info->output_array_last[array_id] = fulldecl->Range.Last;
624 break;
625 }
626 info->array_max[file] = MAX2(info->array_max[file], array_id);
627 }
628
629 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
630 unsigned semName = fulldecl->Semantic.Name;
631 unsigned semIndex = fulldecl->Semantic.Index +
632 (reg - fulldecl->Range.First);
633 int buffer;
634 unsigned index, target, type;
635
636 /*
637 * only first 32 regs will appear in this bitfield, if larger
638 * bits will wrap around.
639 */
640 info->file_mask[file] |= (1u << (reg & 31));
641 info->file_count[file]++;
642 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
643
644 switch (file) {
645 case TGSI_FILE_CONSTANT:
646 buffer = 0;
647
648 if (fulldecl->Declaration.Dimension)
649 buffer = fulldecl->Dim.Index2D;
650
651 info->const_file_max[buffer] =
652 MAX2(info->const_file_max[buffer], (int)reg);
653 info->const_buffers_declared |= 1u << buffer;
654 break;
655
656 case TGSI_FILE_IMAGE:
657 info->images_declared |= 1u << reg;
658 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
659 info->images_buffers |= 1 << reg;
660 break;
661
662 case TGSI_FILE_BUFFER:
663 info->shader_buffers_declared |= 1u << reg;
664 break;
665
666 case TGSI_FILE_INPUT:
667 info->input_semantic_name[reg] = (ubyte) semName;
668 info->input_semantic_index[reg] = (ubyte) semIndex;
669 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
670 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
671 info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
672
673 /* Vertex shaders can have inputs with holes between them. */
674 info->num_inputs = MAX2(info->num_inputs, reg + 1);
675
676 switch (semName) {
677 case TGSI_SEMANTIC_PRIMID:
678 info->uses_primid = true;
679 break;
680 case TGSI_SEMANTIC_POSITION:
681 info->reads_position = true;
682 break;
683 case TGSI_SEMANTIC_FACE:
684 info->uses_frontface = true;
685 break;
686 }
687 break;
688
689 case TGSI_FILE_SYSTEM_VALUE:
690 index = fulldecl->Range.First;
691
692 info->system_value_semantic_name[index] = semName;
693 info->num_system_values = MAX2(info->num_system_values, index + 1);
694
695 switch (semName) {
696 case TGSI_SEMANTIC_INSTANCEID:
697 info->uses_instanceid = TRUE;
698 break;
699 case TGSI_SEMANTIC_VERTEXID:
700 info->uses_vertexid = TRUE;
701 break;
702 case TGSI_SEMANTIC_VERTEXID_NOBASE:
703 info->uses_vertexid_nobase = TRUE;
704 break;
705 case TGSI_SEMANTIC_BASEVERTEX:
706 info->uses_basevertex = TRUE;
707 break;
708 case TGSI_SEMANTIC_DRAWID:
709 info->uses_drawid = TRUE;
710 break;
711 case TGSI_SEMANTIC_PRIMID:
712 info->uses_primid = TRUE;
713 break;
714 case TGSI_SEMANTIC_INVOCATIONID:
715 info->uses_invocationid = TRUE;
716 break;
717 case TGSI_SEMANTIC_POSITION:
718 info->reads_position = TRUE;
719 break;
720 case TGSI_SEMANTIC_FACE:
721 info->uses_frontface = TRUE;
722 break;
723 case TGSI_SEMANTIC_SAMPLEMASK:
724 info->reads_samplemask = TRUE;
725 break;
726 case TGSI_SEMANTIC_TESSINNER:
727 case TGSI_SEMANTIC_TESSOUTER:
728 info->reads_tess_factors = true;
729 break;
730 }
731 break;
732
733 case TGSI_FILE_OUTPUT:
734 info->output_semantic_name[reg] = (ubyte) semName;
735 info->output_semantic_index[reg] = (ubyte) semIndex;
736 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
737 info->num_outputs = MAX2(info->num_outputs, reg + 1);
738
739 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
740 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
741 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
742 }
743 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
744 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
745 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
746 }
747 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
748 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
749 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
750 }
751 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
752 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
753 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
754 }
755
756 switch (semName) {
757 case TGSI_SEMANTIC_PRIMID:
758 info->writes_primid = true;
759 break;
760 case TGSI_SEMANTIC_VIEWPORT_INDEX:
761 info->writes_viewport_index = true;
762 break;
763 case TGSI_SEMANTIC_LAYER:
764 info->writes_layer = true;
765 break;
766 case TGSI_SEMANTIC_PSIZE:
767 info->writes_psize = true;
768 break;
769 case TGSI_SEMANTIC_CLIPVERTEX:
770 info->writes_clipvertex = true;
771 break;
772 case TGSI_SEMANTIC_COLOR:
773 info->colors_written |= 1 << semIndex;
774 break;
775 case TGSI_SEMANTIC_STENCIL:
776 info->writes_stencil = true;
777 break;
778 case TGSI_SEMANTIC_SAMPLEMASK:
779 info->writes_samplemask = true;
780 break;
781 case TGSI_SEMANTIC_EDGEFLAG:
782 info->writes_edgeflag = true;
783 break;
784 case TGSI_SEMANTIC_POSITION:
785 if (procType == PIPE_SHADER_FRAGMENT)
786 info->writes_z = true;
787 else
788 info->writes_position = true;
789 break;
790 }
791 break;
792
793 case TGSI_FILE_SAMPLER:
794 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
795 info->samplers_declared |= 1u << reg;
796 break;
797
798 case TGSI_FILE_SAMPLER_VIEW:
799 target = fulldecl->SamplerView.Resource;
800 type = fulldecl->SamplerView.ReturnTypeX;
801
802 assert(target < TGSI_TEXTURE_UNKNOWN);
803 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
804 /* Save sampler target for this sampler index */
805 info->sampler_targets[reg] = target;
806 info->sampler_type[reg] = type;
807 } else {
808 /* if previously declared, make sure targets agree */
809 assert(info->sampler_targets[reg] == target);
810 assert(info->sampler_type[reg] == type);
811 }
812 break;
813 }
814 }
815 }
816
817
818 static void
scan_immediate(struct tgsi_shader_info * info)819 scan_immediate(struct tgsi_shader_info *info)
820 {
821 uint reg = info->immediate_count++;
822 uint file = TGSI_FILE_IMMEDIATE;
823
824 info->file_mask[file] |= (1 << reg);
825 info->file_count[file]++;
826 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
827 }
828
829
830 static void
scan_property(struct tgsi_shader_info * info,const struct tgsi_full_property * fullprop)831 scan_property(struct tgsi_shader_info *info,
832 const struct tgsi_full_property *fullprop)
833 {
834 unsigned name = fullprop->Property.PropertyName;
835 unsigned value = fullprop->u[0].Data;
836
837 assert(name < ARRAY_SIZE(info->properties));
838 info->properties[name] = value;
839
840 switch (name) {
841 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
842 info->num_written_clipdistance = value;
843 info->clipdist_writemask |= (1 << value) - 1;
844 break;
845 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
846 info->num_written_culldistance = value;
847 info->culldist_writemask |= (1 << value) - 1;
848 break;
849 }
850 }
851
852
853 /**
854 * Scan the given TGSI shader to collect information such as number of
855 * registers used, special instructions used, etc.
856 * \return info the result of the scan
857 */
858 void
tgsi_scan_shader(const struct tgsi_token * tokens,struct tgsi_shader_info * info)859 tgsi_scan_shader(const struct tgsi_token *tokens,
860 struct tgsi_shader_info *info)
861 {
862 uint procType, i;
863 struct tgsi_parse_context parse;
864 unsigned current_depth = 0;
865
866 memset(info, 0, sizeof(*info));
867 for (i = 0; i < TGSI_FILE_COUNT; i++)
868 info->file_max[i] = -1;
869 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
870 info->const_file_max[i] = -1;
871 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
872 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
873
874 /**
875 ** Setup to begin parsing input shader
876 **/
877 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
878 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
879 return;
880 }
881 procType = parse.FullHeader.Processor.Processor;
882 assert(procType == PIPE_SHADER_FRAGMENT ||
883 procType == PIPE_SHADER_VERTEX ||
884 procType == PIPE_SHADER_GEOMETRY ||
885 procType == PIPE_SHADER_TESS_CTRL ||
886 procType == PIPE_SHADER_TESS_EVAL ||
887 procType == PIPE_SHADER_COMPUTE);
888 info->processor = procType;
889 info->num_tokens = tgsi_num_tokens(parse.Tokens);
890
891 if (procType == PIPE_SHADER_GEOMETRY)
892 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
893
894 /**
895 ** Loop over incoming program tokens/instructions
896 */
897 while (!tgsi_parse_end_of_tokens(&parse)) {
898 tgsi_parse_token( &parse );
899
900 switch( parse.FullToken.Token.Type ) {
901 case TGSI_TOKEN_TYPE_INSTRUCTION:
902 scan_instruction(info, &parse.FullToken.FullInstruction,
903 ¤t_depth);
904 break;
905 case TGSI_TOKEN_TYPE_DECLARATION:
906 scan_declaration(info, &parse.FullToken.FullDeclaration);
907 break;
908 case TGSI_TOKEN_TYPE_IMMEDIATE:
909 scan_immediate(info);
910 break;
911 case TGSI_TOKEN_TYPE_PROPERTY:
912 scan_property(info, &parse.FullToken.FullProperty);
913 break;
914 default:
915 assert(!"Unexpected TGSI token type");
916 }
917 }
918
919 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
920 info->opcode_count[TGSI_OPCODE_KILL]);
921
922 /* The dimensions of the IN decleration in geometry shader have
923 * to be deduced from the type of the input primitive.
924 */
925 if (procType == PIPE_SHADER_GEOMETRY) {
926 unsigned input_primitive =
927 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
928 int num_verts = u_vertices_per_prim(input_primitive);
929 int j;
930 info->file_count[TGSI_FILE_INPUT] = num_verts;
931 info->file_max[TGSI_FILE_INPUT] =
932 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
933 for (j = 0; j < num_verts; ++j) {
934 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
935 }
936 }
937
938 tgsi_parse_free(&parse);
939 }
940
941 /**
942 * Collect information about the arrays of a given register file.
943 *
944 * @param tokens TGSI shader
945 * @param file the register file to scan through
946 * @param max_array_id number of entries in @p arrays; should be equal to the
947 * highest array id, i.e. tgsi_shader_info::array_max[file].
948 * @param arrays info for array of each ID will be written to arrays[ID - 1].
949 */
950 void
tgsi_scan_arrays(const struct tgsi_token * tokens,unsigned file,unsigned max_array_id,struct tgsi_array_info * arrays)951 tgsi_scan_arrays(const struct tgsi_token *tokens,
952 unsigned file,
953 unsigned max_array_id,
954 struct tgsi_array_info *arrays)
955 {
956 struct tgsi_parse_context parse;
957
958 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
959 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
960 return;
961 }
962
963 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
964
965 while (!tgsi_parse_end_of_tokens(&parse)) {
966 struct tgsi_full_instruction *inst;
967
968 tgsi_parse_token(&parse);
969
970 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
971 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
972
973 if (decl->Declaration.Array && decl->Declaration.File == file &&
974 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
975 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
976 assert(!array->declared);
977 array->declared = true;
978 array->range = decl->Range;
979 }
980 }
981
982 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
983 continue;
984
985 inst = &parse.FullToken.FullInstruction;
986 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
987 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
988 if (dst->Register.File != file)
989 continue;
990
991 if (dst->Register.Indirect) {
992 if (dst->Indirect.ArrayID > 0 &&
993 dst->Indirect.ArrayID <= max_array_id) {
994 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
995 } else {
996 /* Indirect writes without an ArrayID can write anywhere. */
997 for (unsigned j = 0; j < max_array_id; ++j)
998 arrays[j].writemask |= dst->Register.WriteMask;
999 }
1000 } else {
1001 /* Check whether the write falls into any of the arrays anyway. */
1002 for (unsigned j = 0; j < max_array_id; ++j) {
1003 struct tgsi_array_info *array = &arrays[j];
1004 if (array->declared &&
1005 dst->Register.Index >= array->range.First &&
1006 dst->Register.Index <= array->range.Last)
1007 array->writemask |= dst->Register.WriteMask;
1008 }
1009 }
1010 }
1011 }
1012
1013 tgsi_parse_free(&parse);
1014
1015 return;
1016 }
1017
1018 static void
check_no_subroutines(const struct tgsi_full_instruction * inst)1019 check_no_subroutines(const struct tgsi_full_instruction *inst)
1020 {
1021 switch (inst->Instruction.Opcode) {
1022 case TGSI_OPCODE_BGNSUB:
1023 case TGSI_OPCODE_ENDSUB:
1024 case TGSI_OPCODE_CAL:
1025 unreachable("subroutines unhandled");
1026 }
1027 }
1028
1029 static unsigned
get_inst_tessfactor_writemask(const struct tgsi_shader_info * info,const struct tgsi_full_instruction * inst)1030 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
1031 const struct tgsi_full_instruction *inst)
1032 {
1033 unsigned writemask = 0;
1034
1035 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
1036 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
1037
1038 if (dst->Register.File == TGSI_FILE_OUTPUT &&
1039 !dst->Register.Indirect) {
1040 unsigned name = info->output_semantic_name[dst->Register.Index];
1041
1042 if (name == TGSI_SEMANTIC_TESSINNER)
1043 writemask |= dst->Register.WriteMask;
1044 else if (name == TGSI_SEMANTIC_TESSOUTER)
1045 writemask |= dst->Register.WriteMask << 4;
1046 }
1047 }
1048 return writemask;
1049 }
1050
1051 static unsigned
get_block_tessfactor_writemask(const struct tgsi_shader_info * info,struct tgsi_parse_context * parse,unsigned end_opcode)1052 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1053 struct tgsi_parse_context *parse,
1054 unsigned end_opcode)
1055 {
1056 struct tgsi_full_instruction *inst;
1057 unsigned writemask = 0;
1058
1059 tgsi_parse_token(parse);
1060 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1061 inst = &parse->FullToken.FullInstruction;
1062 check_no_subroutines(inst);
1063
1064 while (inst->Instruction.Opcode != end_opcode) {
1065
1066 /* Recursively process nested blocks. */
1067 switch (inst->Instruction.Opcode) {
1068 case TGSI_OPCODE_IF:
1069 case TGSI_OPCODE_UIF:
1070 writemask |=
1071 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1072 break;
1073
1074 case TGSI_OPCODE_BGNLOOP:
1075 writemask |=
1076 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1077 break;
1078
1079 case TGSI_OPCODE_BARRIER:
1080 unreachable("nested BARRIER is illegal");
1081 break;
1082
1083 default:
1084 writemask |= get_inst_tessfactor_writemask(info, inst);
1085 }
1086
1087 tgsi_parse_token(parse);
1088 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1089 inst = &parse->FullToken.FullInstruction;
1090 check_no_subroutines(inst);
1091 }
1092
1093 return writemask;
1094 }
1095
1096 static void
get_if_block_tessfactor_writemask(const struct tgsi_shader_info * info,struct tgsi_parse_context * parse,unsigned * upper_block_tf_writemask,unsigned * cond_block_tf_writemask)1097 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1098 struct tgsi_parse_context *parse,
1099 unsigned *upper_block_tf_writemask,
1100 unsigned *cond_block_tf_writemask)
1101 {
1102 struct tgsi_full_instruction *inst;
1103 unsigned then_tessfactor_writemask = 0;
1104 unsigned else_tessfactor_writemask = 0;
1105 unsigned writemask;
1106 bool is_then = true;
1107
1108 tgsi_parse_token(parse);
1109 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1110 inst = &parse->FullToken.FullInstruction;
1111 check_no_subroutines(inst);
1112
1113 while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF) {
1114
1115 switch (inst->Instruction.Opcode) {
1116 case TGSI_OPCODE_ELSE:
1117 is_then = false;
1118 break;
1119
1120 /* Recursively process nested blocks. */
1121 case TGSI_OPCODE_IF:
1122 case TGSI_OPCODE_UIF:
1123 get_if_block_tessfactor_writemask(info, parse,
1124 is_then ? &then_tessfactor_writemask :
1125 &else_tessfactor_writemask,
1126 cond_block_tf_writemask);
1127 break;
1128
1129 case TGSI_OPCODE_BGNLOOP:
1130 *cond_block_tf_writemask |=
1131 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1132 break;
1133
1134 case TGSI_OPCODE_BARRIER:
1135 unreachable("nested BARRIER is illegal");
1136 break;
1137 default:
1138 /* Process an instruction in the current block. */
1139 writemask = get_inst_tessfactor_writemask(info, inst);
1140
1141 if (writemask) {
1142 if (is_then)
1143 then_tessfactor_writemask |= writemask;
1144 else
1145 else_tessfactor_writemask |= writemask;
1146 }
1147 }
1148
1149 tgsi_parse_token(parse);
1150 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1151 inst = &parse->FullToken.FullInstruction;
1152 check_no_subroutines(inst);
1153 }
1154
1155 if (then_tessfactor_writemask || else_tessfactor_writemask) {
1156 /* If both statements write the same tess factor channels,
1157 * we can say that the upper block writes them too. */
1158 *upper_block_tf_writemask |= then_tessfactor_writemask &
1159 else_tessfactor_writemask;
1160 *cond_block_tf_writemask |= then_tessfactor_writemask |
1161 else_tessfactor_writemask;
1162 }
1163 }
1164
1165 void
tgsi_scan_tess_ctrl(const struct tgsi_token * tokens,const struct tgsi_shader_info * info,struct tgsi_tessctrl_info * out)1166 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1167 const struct tgsi_shader_info *info,
1168 struct tgsi_tessctrl_info *out)
1169 {
1170 memset(out, 0, sizeof(*out));
1171
1172 if (info->processor != PIPE_SHADER_TESS_CTRL)
1173 return;
1174
1175 struct tgsi_parse_context parse;
1176 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1177 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1178 return;
1179 }
1180
1181 /* The pass works as follows:
1182 * If all codepaths write tess factors, we can say that all invocations
1183 * define tess factors.
1184 *
1185 * Each tess factor channel is tracked separately.
1186 */
1187 unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1188 unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1189
1190 /* Initial value = true. Here the pass will accumulate results from multiple
1191 * segments surrounded by barriers. If tess factors aren't written at all,
1192 * it's a shader bug and we don't care if this will be true.
1193 */
1194 out->tessfactors_are_def_in_all_invocs = true;
1195
1196 while (!tgsi_parse_end_of_tokens(&parse)) {
1197 tgsi_parse_token(&parse);
1198
1199 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1200 continue;
1201
1202 struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1203 check_no_subroutines(inst);
1204
1205 /* Process nested blocks. */
1206 switch (inst->Instruction.Opcode) {
1207 case TGSI_OPCODE_IF:
1208 case TGSI_OPCODE_UIF:
1209 get_if_block_tessfactor_writemask(info, &parse,
1210 &main_block_tf_writemask,
1211 &cond_block_tf_writemask);
1212 continue;
1213
1214 case TGSI_OPCODE_BGNLOOP:
1215 cond_block_tf_writemask |=
1216 get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDLOOP);
1217 continue;
1218
1219 case TGSI_OPCODE_BARRIER:
1220 /* The following case must be prevented:
1221 * gl_TessLevelInner = ...;
1222 * barrier();
1223 * if (gl_InvocationID == 1)
1224 * gl_TessLevelInner = ...;
1225 *
1226 * If you consider disjoint code segments separated by barriers, each
1227 * such segment that writes tess factor channels should write the same
1228 * channels in all codepaths within that segment.
1229 */
1230 if (main_block_tf_writemask || cond_block_tf_writemask) {
1231 /* Accumulate the result: */
1232 out->tessfactors_are_def_in_all_invocs &=
1233 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1234
1235 /* Analyze the next code segment from scratch. */
1236 main_block_tf_writemask = 0;
1237 cond_block_tf_writemask = 0;
1238 }
1239 continue;
1240 }
1241
1242 main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1243 }
1244
1245 /* Accumulate the result for the last code segment separated by a barrier. */
1246 if (main_block_tf_writemask || cond_block_tf_writemask) {
1247 out->tessfactors_are_def_in_all_invocs &=
1248 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1249 }
1250
1251 tgsi_parse_free(&parse);
1252 }
1253