1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DDR_IMMAP_H 9 #define DDR_IMMAP_H 10 11 #define DDR_DBUS_64 0 12 #define DDR_DBUS_32 1 13 #define DDR_DBUS_16 2 14 15 /* 16 * DDRC register file for DDRC 5.0 and above 17 */ 18 struct ccsr_ddr { 19 struct { 20 unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */ 21 unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */ 22 } bnds[4]; 23 unsigned char res_20[0x40 - 0x20]; 24 unsigned int dec[10]; /* 0x40 */ 25 unsigned char res_68[0x80 - 0x68]; 26 unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */ 27 unsigned char res_90[48]; 28 unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */ 29 unsigned char res_d0[48]; 30 unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */ 31 unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */ 32 unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */ 33 unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */ 34 unsigned int sdram_cfg; /* SDRAM Control Configuration */ 35 unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */ 36 unsigned int sdram_mode; /* SDRAM Mode Configuration */ 37 unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */ 38 unsigned int sdram_md_cntl; /* SDRAM Mode Control */ 39 unsigned int sdram_interval; /* SDRAM Interval Configuration */ 40 unsigned int sdram_data_init; /* SDRAM Data initialization */ 41 unsigned char res_12c[4]; 42 unsigned int sdram_clk_cntl; /* SDRAM Clock Control */ 43 unsigned char res_134[20]; 44 unsigned int init_addr; /* training init addr */ 45 unsigned int init_ext_addr; /* training init extended addr */ 46 unsigned char res_150[16]; 47 unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */ 48 unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */ 49 unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */ 50 unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */ 51 unsigned int zq_cntl; /* ZQ calibration control*/ 52 unsigned int wrlvl_cntl; /* write leveling control*/ 53 unsigned char reg_178[4]; 54 unsigned int ddr_sr_cntr; /* self refresh counter */ 55 unsigned int ddr_sdram_rcw_1; /* Control Words 1 */ 56 unsigned int ddr_sdram_rcw_2; /* Control Words 2 */ 57 unsigned char reg_188[8]; 58 unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */ 59 unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */ 60 unsigned char res_198[0x1a0-0x198]; 61 unsigned int ddr_sdram_rcw_3; 62 unsigned int ddr_sdram_rcw_4; 63 unsigned int ddr_sdram_rcw_5; 64 unsigned int ddr_sdram_rcw_6; 65 unsigned char res_1b0[0x200-0x1b0]; 66 unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */ 67 unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */ 68 unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */ 69 unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */ 70 unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */ 71 unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */ 72 unsigned char res_218[0x220-0x218]; 73 unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */ 74 unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */ 75 unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */ 76 unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */ 77 unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */ 78 unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */ 79 unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */ 80 unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */ 81 unsigned char res_240[0x250-0x240]; 82 unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */ 83 unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */ 84 unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */ 85 unsigned char res_258[0x260-0x25c]; 86 unsigned int sdram_cfg_3; 87 unsigned char res_264[0x270-0x264]; 88 unsigned int sdram_md_cntl_2; 89 unsigned char res_274[0x400-0x274]; 90 unsigned int dq_map[4]; 91 unsigned char res_410[0x800-0x410]; 92 unsigned int tx_cfg[4]; 93 unsigned char res_810[0xb20-0x810]; 94 unsigned int ddr_dsr1; /* Debug Status 1 */ 95 unsigned int ddr_dsr2; /* Debug Status 2 */ 96 unsigned int ddr_cdr1; /* Control Driver 1 */ 97 unsigned int ddr_cdr2; /* Control Driver 2 */ 98 unsigned char res_b30[200]; 99 unsigned int ip_rev1; /* IP Block Revision 1 */ 100 unsigned int ip_rev2; /* IP Block Revision 2 */ 101 unsigned int eor; /* Enhanced Optimization Register */ 102 unsigned char res_c04[252]; 103 unsigned int mtcr; /* Memory Test Control Register */ 104 unsigned char res_d04[28]; 105 unsigned int mtp[10]; /* Memory Test Patterns */ 106 unsigned char res_d48[184]; 107 unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/ 108 unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/ 109 unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */ 110 unsigned char res_e0c[20]; 111 unsigned int capture_data_hi; /* Data Path Read Capture High */ 112 unsigned int capture_data_lo; /* Data Path Read Capture Low */ 113 unsigned int capture_ecc; /* Data Path Read Capture ECC */ 114 unsigned char res_e2c[20]; 115 unsigned int err_detect; /* Error Detect */ 116 unsigned int err_disable; /* Error Disable */ 117 unsigned int err_int_en; 118 unsigned int capture_attributes; /* Error Attrs Capture */ 119 unsigned int capture_address; /* Error Addr Capture */ 120 unsigned int capture_ext_address; /* Error Extended Addr Capture */ 121 unsigned int err_sbe; /* Single-Bit ECC Error Management */ 122 unsigned char res_e5c[164]; 123 unsigned int debug[64]; /* debug_1 to debug_64 */ 124 }; 125 #endif /* DDR_IMMAP_H */ 126