1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * tools/testing/selftests/kvm/lib/x86_64/vmx.c
4 *
5 * Copyright (C) 2018, Google LLC.
6 */
7
8 #include "test_util.h"
9 #include "kvm_util.h"
10 #include "../kvm_util_internal.h"
11 #include "processor.h"
12 #include "vmx.h"
13
14 #define PAGE_SHIFT_4K 12
15
16 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000
17
18 bool enable_evmcs;
19
20 struct hv_enlightened_vmcs *current_evmcs;
21 struct hv_vp_assist_page *current_vp_assist;
22
23 struct eptPageTableEntry {
24 uint64_t readable:1;
25 uint64_t writable:1;
26 uint64_t executable:1;
27 uint64_t memory_type:3;
28 uint64_t ignore_pat:1;
29 uint64_t page_size:1;
30 uint64_t accessed:1;
31 uint64_t dirty:1;
32 uint64_t ignored_11_10:2;
33 uint64_t address:40;
34 uint64_t ignored_62_52:11;
35 uint64_t suppress_ve:1;
36 };
37
38 struct eptPageTablePointer {
39 uint64_t memory_type:3;
40 uint64_t page_walk_length:3;
41 uint64_t ad_enabled:1;
42 uint64_t reserved_11_07:5;
43 uint64_t address:40;
44 uint64_t reserved_63_52:12;
45 };
vcpu_enable_evmcs(struct kvm_vm * vm,int vcpu_id)46 int vcpu_enable_evmcs(struct kvm_vm *vm, int vcpu_id)
47 {
48 uint16_t evmcs_ver;
49
50 struct kvm_enable_cap enable_evmcs_cap = {
51 .cap = KVM_CAP_HYPERV_ENLIGHTENED_VMCS,
52 .args[0] = (unsigned long)&evmcs_ver
53 };
54
55 vcpu_ioctl(vm, vcpu_id, KVM_ENABLE_CAP, &enable_evmcs_cap);
56
57 /* KVM should return supported EVMCS version range */
58 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) &&
59 (evmcs_ver & 0xff) > 0,
60 "Incorrect EVMCS version range: %x:%x\n",
61 evmcs_ver & 0xff, evmcs_ver >> 8);
62
63 return evmcs_ver;
64 }
65
66 /* Allocate memory regions for nested VMX tests.
67 *
68 * Input Args:
69 * vm - The VM to allocate guest-virtual addresses in.
70 *
71 * Output Args:
72 * p_vmx_gva - The guest virtual address for the struct vmx_pages.
73 *
74 * Return:
75 * Pointer to structure with the addresses of the VMX areas.
76 */
77 struct vmx_pages *
vcpu_alloc_vmx(struct kvm_vm * vm,vm_vaddr_t * p_vmx_gva)78 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva)
79 {
80 vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm);
81 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva);
82
83 /* Setup of a region of guest memory for the vmxon region. */
84 vmx->vmxon = (void *)vm_vaddr_alloc_page(vm);
85 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon);
86 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon);
87
88 /* Setup of a region of guest memory for a vmcs. */
89 vmx->vmcs = (void *)vm_vaddr_alloc_page(vm);
90 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs);
91 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs);
92
93 /* Setup of a region of guest memory for the MSR bitmap. */
94 vmx->msr = (void *)vm_vaddr_alloc_page(vm);
95 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr);
96 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr);
97 memset(vmx->msr_hva, 0, getpagesize());
98
99 /* Setup of a region of guest memory for the shadow VMCS. */
100 vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm);
101 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs);
102 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs);
103
104 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */
105 vmx->vmread = (void *)vm_vaddr_alloc_page(vm);
106 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread);
107 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread);
108 memset(vmx->vmread_hva, 0, getpagesize());
109
110 vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm);
111 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite);
112 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite);
113 memset(vmx->vmwrite_hva, 0, getpagesize());
114
115 /* Setup of a region of guest memory for the VP Assist page. */
116 vmx->vp_assist = (void *)vm_vaddr_alloc_page(vm);
117 vmx->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)vmx->vp_assist);
118 vmx->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vp_assist);
119
120 /* Setup of a region of guest memory for the enlightened VMCS. */
121 vmx->enlightened_vmcs = (void *)vm_vaddr_alloc_page(vm);
122 vmx->enlightened_vmcs_hva =
123 addr_gva2hva(vm, (uintptr_t)vmx->enlightened_vmcs);
124 vmx->enlightened_vmcs_gpa =
125 addr_gva2gpa(vm, (uintptr_t)vmx->enlightened_vmcs);
126
127 *p_vmx_gva = vmx_gva;
128 return vmx;
129 }
130
prepare_for_vmx_operation(struct vmx_pages * vmx)131 bool prepare_for_vmx_operation(struct vmx_pages *vmx)
132 {
133 uint64_t feature_control;
134 uint64_t required;
135 unsigned long cr0;
136 unsigned long cr4;
137
138 /*
139 * Ensure bits in CR0 and CR4 are valid in VMX operation:
140 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx.
141 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx.
142 */
143 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory");
144 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1);
145 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0);
146 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory");
147
148 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory");
149 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1);
150 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0);
151 /* Enable VMX operation */
152 cr4 |= X86_CR4_VMXE;
153 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory");
154
155 /*
156 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON:
157 * Bit 0: Lock bit. If clear, VMXON causes a #GP.
158 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON
159 * outside of SMX causes a #GP.
160 */
161 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
162 required |= FEAT_CTL_LOCKED;
163 feature_control = rdmsr(MSR_IA32_FEAT_CTL);
164 if ((feature_control & required) != required)
165 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required);
166
167 /* Enter VMX root operation. */
168 *(uint32_t *)(vmx->vmxon) = vmcs_revision();
169 if (vmxon(vmx->vmxon_gpa))
170 return false;
171
172 return true;
173 }
174
load_vmcs(struct vmx_pages * vmx)175 bool load_vmcs(struct vmx_pages *vmx)
176 {
177 if (!enable_evmcs) {
178 /* Load a VMCS. */
179 *(uint32_t *)(vmx->vmcs) = vmcs_revision();
180 if (vmclear(vmx->vmcs_gpa))
181 return false;
182
183 if (vmptrld(vmx->vmcs_gpa))
184 return false;
185
186 /* Setup shadow VMCS, do not load it yet. */
187 *(uint32_t *)(vmx->shadow_vmcs) =
188 vmcs_revision() | 0x80000000ul;
189 if (vmclear(vmx->shadow_vmcs_gpa))
190 return false;
191 } else {
192 if (evmcs_vmptrld(vmx->enlightened_vmcs_gpa,
193 vmx->enlightened_vmcs))
194 return false;
195 current_evmcs->revision_id = EVMCS_VERSION;
196 }
197
198 return true;
199 }
200
201 /*
202 * Initialize the control fields to the most basic settings possible.
203 */
init_vmcs_control_fields(struct vmx_pages * vmx)204 static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
205 {
206 uint32_t sec_exec_ctl = 0;
207
208 vmwrite(VIRTUAL_PROCESSOR_ID, 0);
209 vmwrite(POSTED_INTR_NV, 0);
210
211 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS));
212
213 if (vmx->eptp_gpa) {
214 uint64_t ept_paddr;
215 struct eptPageTablePointer eptp = {
216 .memory_type = VMX_BASIC_MEM_TYPE_WB,
217 .page_walk_length = 3, /* + 1 */
218 .ad_enabled = !!(rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & VMX_EPT_VPID_CAP_AD_BITS),
219 .address = vmx->eptp_gpa >> PAGE_SHIFT_4K,
220 };
221
222 memcpy(&ept_paddr, &eptp, sizeof(ept_paddr));
223 vmwrite(EPT_POINTER, ept_paddr);
224 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT;
225 }
226
227 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl))
228 vmwrite(CPU_BASED_VM_EXEC_CONTROL,
229 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
230 else {
231 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS));
232 GUEST_ASSERT(!sec_exec_ctl);
233 }
234
235 vmwrite(EXCEPTION_BITMAP, 0);
236 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0);
237 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */
238 vmwrite(CR3_TARGET_COUNT, 0);
239 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) |
240 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */
241 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0);
242 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0);
243 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) |
244 VM_ENTRY_IA32E_MODE); /* 64-bit guest */
245 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0);
246 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0);
247 vmwrite(TPR_THRESHOLD, 0);
248
249 vmwrite(CR0_GUEST_HOST_MASK, 0);
250 vmwrite(CR4_GUEST_HOST_MASK, 0);
251 vmwrite(CR0_READ_SHADOW, get_cr0());
252 vmwrite(CR4_READ_SHADOW, get_cr4());
253
254 vmwrite(MSR_BITMAP, vmx->msr_gpa);
255 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa);
256 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa);
257 }
258
259 /*
260 * Initialize the host state fields based on the current host state, with
261 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch
262 * or vmresume.
263 */
init_vmcs_host_state(void)264 static inline void init_vmcs_host_state(void)
265 {
266 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS);
267
268 vmwrite(HOST_ES_SELECTOR, get_es());
269 vmwrite(HOST_CS_SELECTOR, get_cs());
270 vmwrite(HOST_SS_SELECTOR, get_ss());
271 vmwrite(HOST_DS_SELECTOR, get_ds());
272 vmwrite(HOST_FS_SELECTOR, get_fs());
273 vmwrite(HOST_GS_SELECTOR, get_gs());
274 vmwrite(HOST_TR_SELECTOR, get_tr());
275
276 if (exit_controls & VM_EXIT_LOAD_IA32_PAT)
277 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT));
278 if (exit_controls & VM_EXIT_LOAD_IA32_EFER)
279 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER));
280 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
281 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL,
282 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL));
283
284 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS));
285
286 vmwrite(HOST_CR0, get_cr0());
287 vmwrite(HOST_CR3, get_cr3());
288 vmwrite(HOST_CR4, get_cr4());
289 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE));
290 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE));
291 vmwrite(HOST_TR_BASE,
292 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr())));
293 vmwrite(HOST_GDTR_BASE, get_gdt().address);
294 vmwrite(HOST_IDTR_BASE, get_idt().address);
295 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP));
296 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP));
297 }
298
299 /*
300 * Initialize the guest state fields essentially as a clone of
301 * the host state fields. Some host state fields have fixed
302 * values, and we set the corresponding guest state fields accordingly.
303 */
init_vmcs_guest_state(void * rip,void * rsp)304 static inline void init_vmcs_guest_state(void *rip, void *rsp)
305 {
306 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR));
307 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR));
308 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR));
309 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR));
310 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR));
311 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR));
312 vmwrite(GUEST_LDTR_SELECTOR, 0);
313 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR));
314 vmwrite(GUEST_INTR_STATUS, 0);
315 vmwrite(GUEST_PML_INDEX, 0);
316
317 vmwrite(VMCS_LINK_POINTER, -1ll);
318 vmwrite(GUEST_IA32_DEBUGCTL, 0);
319 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT));
320 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER));
321 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL,
322 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL));
323
324 vmwrite(GUEST_ES_LIMIT, -1);
325 vmwrite(GUEST_CS_LIMIT, -1);
326 vmwrite(GUEST_SS_LIMIT, -1);
327 vmwrite(GUEST_DS_LIMIT, -1);
328 vmwrite(GUEST_FS_LIMIT, -1);
329 vmwrite(GUEST_GS_LIMIT, -1);
330 vmwrite(GUEST_LDTR_LIMIT, -1);
331 vmwrite(GUEST_TR_LIMIT, 0x67);
332 vmwrite(GUEST_GDTR_LIMIT, 0xffff);
333 vmwrite(GUEST_IDTR_LIMIT, 0xffff);
334 vmwrite(GUEST_ES_AR_BYTES,
335 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093);
336 vmwrite(GUEST_CS_AR_BYTES, 0xa09b);
337 vmwrite(GUEST_SS_AR_BYTES, 0xc093);
338 vmwrite(GUEST_DS_AR_BYTES,
339 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093);
340 vmwrite(GUEST_FS_AR_BYTES,
341 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093);
342 vmwrite(GUEST_GS_AR_BYTES,
343 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093);
344 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000);
345 vmwrite(GUEST_TR_AR_BYTES, 0x8b);
346 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
347 vmwrite(GUEST_ACTIVITY_STATE, 0);
348 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS));
349 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0);
350
351 vmwrite(GUEST_CR0, vmreadz(HOST_CR0));
352 vmwrite(GUEST_CR3, vmreadz(HOST_CR3));
353 vmwrite(GUEST_CR4, vmreadz(HOST_CR4));
354 vmwrite(GUEST_ES_BASE, 0);
355 vmwrite(GUEST_CS_BASE, 0);
356 vmwrite(GUEST_SS_BASE, 0);
357 vmwrite(GUEST_DS_BASE, 0);
358 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE));
359 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE));
360 vmwrite(GUEST_LDTR_BASE, 0);
361 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE));
362 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE));
363 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE));
364 vmwrite(GUEST_DR7, 0x400);
365 vmwrite(GUEST_RSP, (uint64_t)rsp);
366 vmwrite(GUEST_RIP, (uint64_t)rip);
367 vmwrite(GUEST_RFLAGS, 2);
368 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0);
369 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP));
370 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP));
371 }
372
prepare_vmcs(struct vmx_pages * vmx,void * guest_rip,void * guest_rsp)373 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp)
374 {
375 init_vmcs_control_fields(vmx);
376 init_vmcs_host_state();
377 init_vmcs_guest_state(guest_rip, guest_rsp);
378 }
379
nested_vmx_supported(void)380 bool nested_vmx_supported(void)
381 {
382 struct kvm_cpuid_entry2 *entry = kvm_get_supported_cpuid_entry(1);
383
384 return entry->ecx & CPUID_VMX;
385 }
386
nested_vmx_check_supported(void)387 void nested_vmx_check_supported(void)
388 {
389 if (!nested_vmx_supported()) {
390 print_skip("nested VMX not enabled");
391 exit(KSFT_SKIP);
392 }
393 }
394
nested_pg_map(struct vmx_pages * vmx,struct kvm_vm * vm,uint64_t nested_paddr,uint64_t paddr)395 void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
396 uint64_t nested_paddr, uint64_t paddr)
397 {
398 uint16_t index[4];
399 struct eptPageTableEntry *pml4e;
400
401 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use "
402 "unknown or unsupported guest mode, mode: 0x%x", vm->mode);
403
404 TEST_ASSERT((nested_paddr % vm->page_size) == 0,
405 "Nested physical address not on page boundary,\n"
406 " nested_paddr: 0x%lx vm->page_size: 0x%x",
407 nested_paddr, vm->page_size);
408 TEST_ASSERT((nested_paddr >> vm->page_shift) <= vm->max_gfn,
409 "Physical address beyond beyond maximum supported,\n"
410 " nested_paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
411 paddr, vm->max_gfn, vm->page_size);
412 TEST_ASSERT((paddr % vm->page_size) == 0,
413 "Physical address not on page boundary,\n"
414 " paddr: 0x%lx vm->page_size: 0x%x",
415 paddr, vm->page_size);
416 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
417 "Physical address beyond beyond maximum supported,\n"
418 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
419 paddr, vm->max_gfn, vm->page_size);
420
421 index[0] = (nested_paddr >> 12) & 0x1ffu;
422 index[1] = (nested_paddr >> 21) & 0x1ffu;
423 index[2] = (nested_paddr >> 30) & 0x1ffu;
424 index[3] = (nested_paddr >> 39) & 0x1ffu;
425
426 /* Allocate page directory pointer table if not present. */
427 pml4e = vmx->eptp_hva;
428 if (!pml4e[index[3]].readable) {
429 pml4e[index[3]].address = vm_alloc_page_table(vm) >> vm->page_shift;
430 pml4e[index[3]].writable = true;
431 pml4e[index[3]].readable = true;
432 pml4e[index[3]].executable = true;
433 }
434
435 /* Allocate page directory table if not present. */
436 struct eptPageTableEntry *pdpe;
437 pdpe = addr_gpa2hva(vm, pml4e[index[3]].address * vm->page_size);
438 if (!pdpe[index[2]].readable) {
439 pdpe[index[2]].address = vm_alloc_page_table(vm) >> vm->page_shift;
440 pdpe[index[2]].writable = true;
441 pdpe[index[2]].readable = true;
442 pdpe[index[2]].executable = true;
443 }
444
445 /* Allocate page table if not present. */
446 struct eptPageTableEntry *pde;
447 pde = addr_gpa2hva(vm, pdpe[index[2]].address * vm->page_size);
448 if (!pde[index[1]].readable) {
449 pde[index[1]].address = vm_alloc_page_table(vm) >> vm->page_shift;
450 pde[index[1]].writable = true;
451 pde[index[1]].readable = true;
452 pde[index[1]].executable = true;
453 }
454
455 /* Fill in page table entry. */
456 struct eptPageTableEntry *pte;
457 pte = addr_gpa2hva(vm, pde[index[1]].address * vm->page_size);
458 pte[index[0]].address = paddr >> vm->page_shift;
459 pte[index[0]].writable = true;
460 pte[index[0]].readable = true;
461 pte[index[0]].executable = true;
462
463 /*
464 * For now mark these as accessed and dirty because the only
465 * testcase we have needs that. Can be reconsidered later.
466 */
467 pte[index[0]].accessed = true;
468 pte[index[0]].dirty = true;
469 }
470
471 /*
472 * Map a range of EPT guest physical addresses to the VM's physical address
473 *
474 * Input Args:
475 * vm - Virtual Machine
476 * nested_paddr - Nested guest physical address to map
477 * paddr - VM Physical Address
478 * size - The size of the range to map
479 * eptp_memslot - Memory region slot for new virtual translation tables
480 *
481 * Output Args: None
482 *
483 * Return: None
484 *
485 * Within the VM given by vm, creates a nested guest translation for the
486 * page range starting at nested_paddr to the page range starting at paddr.
487 */
nested_map(struct vmx_pages * vmx,struct kvm_vm * vm,uint64_t nested_paddr,uint64_t paddr,uint64_t size)488 void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
489 uint64_t nested_paddr, uint64_t paddr, uint64_t size)
490 {
491 size_t page_size = vm->page_size;
492 size_t npages = size / page_size;
493
494 TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow");
495 TEST_ASSERT(paddr + size > paddr, "Paddr overflow");
496
497 while (npages--) {
498 nested_pg_map(vmx, vm, nested_paddr, paddr);
499 nested_paddr += page_size;
500 paddr += page_size;
501 }
502 }
503
504 /* Prepare an identity extended page table that maps all the
505 * physical pages in VM.
506 */
nested_map_memslot(struct vmx_pages * vmx,struct kvm_vm * vm,uint32_t memslot)507 void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm,
508 uint32_t memslot)
509 {
510 sparsebit_idx_t i, last;
511 struct userspace_mem_region *region =
512 memslot2region(vm, memslot);
513
514 i = (region->region.guest_phys_addr >> vm->page_shift) - 1;
515 last = i + (region->region.memory_size >> vm->page_shift);
516 for (;;) {
517 i = sparsebit_next_clear(region->unused_phy_pages, i);
518 if (i > last)
519 break;
520
521 nested_map(vmx, vm,
522 (uint64_t)i << vm->page_shift,
523 (uint64_t)i << vm->page_shift,
524 1 << vm->page_shift);
525 }
526 }
527
prepare_eptp(struct vmx_pages * vmx,struct kvm_vm * vm,uint32_t eptp_memslot)528 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm,
529 uint32_t eptp_memslot)
530 {
531 vmx->eptp = (void *)vm_vaddr_alloc_page(vm);
532 vmx->eptp_hva = addr_gva2hva(vm, (uintptr_t)vmx->eptp);
533 vmx->eptp_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->eptp);
534 }
535
prepare_virtualize_apic_accesses(struct vmx_pages * vmx,struct kvm_vm * vm)536 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm)
537 {
538 vmx->apic_access = (void *)vm_vaddr_alloc_page(vm);
539 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access);
540 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access);
541 }
542