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/external/tensorflow/tensorflow/core/platform/
Dram_file_system_test.py41 file_io.create_dir_v2('ram://testdirectory')
42 file_io.delete_recursively_v2('ram://testdirectory')
45 file_io.create_dir_v2('ram://testdirectory')
46 file_io.create_dir_v2('ram://testdirectory/subdir1')
47 file_io.create_dir_v2('ram://testdirectory/subdir2')
48 file_io.create_dir_v2('ram://testdirectory/subdir1/subdir3')
49 with gfile.GFile('ram://testdirectory/subdir1/subdir3/a.txt', 'w') as f:
51 file_io.delete_recursively_v2('ram://testdirectory')
52 self.assertEqual(gfile.Glob('ram://testdirectory/*'), [])
55 with gfile.GFile('ram://a.txt', 'w') as f:
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/external/arm-trusted-firmware/bl32/sp_min/
Dsp_min.ld.S15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
36 } >RAM
41 } >RAM
45 } >RAM
59 } >RAM
83 } >RAM
94 DATA_SECTION >RAM
95 RELA_SECTION >RAM
101 STACK_SECTION >RAM
102 BSS_SECTION >RAM
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/external/arm-trusted-firmware/bl2u/
Dbl2u.ld.S17 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
35 } >RAM
40 } >RAM
44 } >RAM
54 } >RAM
73 } >RAM
82 DATA_SECTION >RAM
83 STACK_SECTION >RAM
84 BSS_SECTION >RAM
85 XLAT_TABLE_SECTION >RAM
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/external/arm-trusted-firmware/bl2/
Dbl2.ld.S15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
37 } >RAM
42 } >RAM
46 } >RAM
56 } >RAM
75 } >RAM
84 DATA_SECTION >RAM
85 STACK_SECTION >RAM
86 BSS_SECTION >RAM
87 XLAT_TABLE_SECTION >RAM
[all …]
Dbl2_el3.ld.S17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
24 #define ROM RAM
104 DATA_SECTION >RAM AT>ROM
108 RELA_SECTION >RAM
109 STACK_SECTION >RAM
110 BSS_SECTION >RAM
111 XLAT_TABLE_SECTION >RAM
131 } >RAM
/external/pigweed/pw_boot_cortex_m/
Dbasic_cortex_m.ld18 * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more
81 RAM(rwx) : \
184 } >RAM AT> FLASH
212 } >RAM
220 } >RAM
233 HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);
237 "Error: Not enough RAM for desired minimum stack size.");
240 } >RAM
242 /* Represents unused space in the RAM segment. This MUST be the last section
243 * assigned to the RAM region.
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Dcore_init.c32 // 1. Static variables must be loaded from flash to RAM.
90 // Static-init RAM (load static values into ram, .data section init). in StaticMemoryInit()
95 // Zero-init RAM (.bss section init). in StaticMemoryInit()
102 // of RAM. Note that code running before this function finishes memory
105 // Be EXTREMELY careful when running code before this function finishes RAM
119 // either statically initialized RAM or zero initialized RAM. Since most in pw_boot_Entry()
137 // Run any init that must be done before static init of RAM which preps the in pw_boot_Entry()
138 // .data (static values not yet loaded into ram) and .bss sections (not yet in pw_boot_Entry()
/external/pigweed/pw_rust/examples/embedded_hello/
Dqemu-rust-nrf51822.ld18 * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more
43 RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K
156 } >RAM AT> FLASH
184 } >RAM
192 } >RAM
205 HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);
209 "Error: Not enough RAM for desired minimum stack size.");
212 } >RAM
214 /* Represents unused space in the RAM segment. This MUST be the last section
215 * assigned to the RAM region.
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Dqemu-rust-lm3s6965.ld18 * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more
43 RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 64K
156 } >RAM AT> FLASH
184 } >RAM
192 } >RAM
205 HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);
209 "Error: Not enough RAM for desired minimum stack size.");
212 } >RAM
214 /* Represents unused space in the RAM segment. This MUST be the last section
215 * assigned to the RAM region.
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/external/arm-trusted-firmware/bl32/tsp/
Dtsp.ld.S16 RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
34 } >RAM
44 } >RAM
64 } >RAM
73 DATA_SECTION >RAM
74 RELA_SECTION >RAM
80 STACK_SECTION >RAM
81 BSS_SECTION >RAM
82 XLAT_TABLE_SECTION >RAM
102 } >RAM
/external/arm-trusted-firmware/drivers/arm/gic/v3/
Dgic600ae_fmu.c33 "SPI RAM DED error",
34 "SGI RAM DED error",
36 "LPI RAM DED error",
40 "SPI RAM address decode error",
41 "SGI RAM address decode error",
43 "LPI RAM address decode error",
50 "SPI RAM SEC error",
51 "SGI RAM SEC error",
53 "LPI RAM SEC error",
69 "PPI RAM DED error",
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/external/arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/
Dble.ld.S15 RAM (rwx): ORIGIN = BLE_BASE, LENGTH = BLE_LIMIT - BLE_BASE
29 } >RAM
41 } >RAM
47 } >RAM
53 } >RAM
64 . = ORIGIN(RAM) + LENGTH(RAM) - 1;
66 } >RAM
/external/pigweed/pw_persistent_ram/
Ddocs.rst7 persistent RAM. By persistent RAM we are referring to memory which is not
24 Persistent RAM Placement
26 Persistent RAM is typically provided through specially carved out linker script
70 Persistent RAM Lifecycle Management
72 In order for persistent RAM containers to be as useful as possible, any
73 invalidation of persistent RAM and the containers therein should be executed
75 are initialized in RAM.
77 The preferred way to clear Persistent RAM is to simply zero entire persistent
78 RAM sections and/or memory regions. Pigweed's persistent containers have picked
87 1. Do not instantiate regular types/objects in persistent RAM, ensure integrity
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/external/pigweed/pw_bloat/py/
Dbloaty_config_test.py38 'RAM': {0: (int(0x20000000), int(0x20030000))},
43 5: 'RAM',
44 6: 'RAM',
46 4: 'RAM',
47 2: 'RAM',
58 0: 'RAM',
59 1: 'RAM',
72 r' replacement:"RAM"',
76 r' replacement:"RAM"',
Dlabel_test.py25 Label(name='foo()', size=100, parents=tuple(['RAM', '.heap'])),
26 Label(name='bar()', size=220, parents=tuple(['RAM', '.heap'])),
60 ds_map.insert_label_hierachy(['RAM', '.code', 'foo()'], 100)
78 Label(name='foo()', size=100, parents=tuple(['RAM'])),
79 Label(name='bar()', size=220, parents=tuple(['RAM'])),
98 Label(name='.heap', size=320, parents=tuple(['RAM'])),
113 Label(name='RAM', size=320, parents=tuple([])),
128 Label(name='RAM', size=320, parents=tuple([])),
143 Label(name='.heap', size=320, parents=tuple(['RAM'])),
176 parents=tuple(['RAM', '.heap']),
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/external/pigweed/targets/mimxrt595_evk/
Dmimxrt595_flash.ld77 RAM(rwx) : \
199 } >RAM AT> FLASH
227 } >RAM
235 } >RAM
247 HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);
251 "Error: Not enough RAM for desired minimum stack size.");
254 } >RAM
256 /* Represents unused space in the RAM segment. This MUST be the last section
257 * assigned to the RAM region.
259 .RAM.unused_space (NOLOAD) : ALIGN(4)
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/external/cpuinfo/test/dmesg/
Dzenfone-2.log7 [ 0.000000] e820: BIOS-provided physical RAM map:
50 [ 0.000000] total RAM covered: 4065M
51 [ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 8 lose cover RAM: 3063M
52 [ 0.000000] gran_size: 64K chunk_size: 128K num_reg: 8 lose cover RAM: 3063M
53 [ 0.000000] gran_size: 64K chunk_size: 256K num_reg: 8 lose cover RAM: 3063M
54 [ 0.000000] gran_size: 64K chunk_size: 512K num_reg: 8 lose cover RAM: 3063M
55 [ 0.000000] gran_size: 64K chunk_size: 1M num_reg: 8 lose cover RAM: 3063M
56 [ 0.000000] gran_size: 64K chunk_size: 2M num_reg: 8 lose cover RAM: 3063M
57 [ 0.000000] gran_size: 64K chunk_size: 4M num_reg: 8 lose cover RAM: 3831M
58 [ 0.000000] gran_size: 64K chunk_size: 8M num_reg: 8 lose cover RAM: 3983M
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/external/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/
DNvReserved.c57 // When an Index has the orderly attribute, the data is kept in RAM. This RAM is
63 // The attributes of an orderly index are maintained in RAM memory in order to
68 // of the index is kept in RAM. When an orderly Index is created or deleted, the
69 // RAM data is copied to NV backing store so that the image in the backing store
70 // matches the layout of RAM. In normal operation. The RAM data is also copied on
72 // to the backing store for RAM is when a counter is first written (TPMA_NV_WRITTEN
76 // the 'gp' PERSISTENT_DATA structure in RAM and mapped to locations in NV.
148 // If power was lost, need to re-establish the RAM data that is loaded from in NvPowerOn()
177 // Clear the RAM used for Orderly Index data in NvManufacture()
191 // This function is used to move reserved data from NV memory to RAM.
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DNvDynamic.c52 // When an Index has the orderly attribute, the data is kept in RAM. This RAM is
56 // The attributes of an orderly index are maintained in RAM memory in order to
61 // of the index is kept in RAM. When an orderly Index is created or deleted, the
62 // RAM data is copied to NV backing store so that the image in the backing store
63 // matches the layout of RAM. In normal operation. The RAM data is also copied on
65 // to the backing store for RAM is when a counter is first written (TPMA_NV_WRITTEN
69 // the 'gp' PERSISTENT_DATA structure in RAM and mapped to locations in NV.
382 //** RAM-based NV Index Data Access Functions
385 // The data layout in ram buffer is {size of(NV_handle + attributes + data
387 // for each NV Index data stored in RAM.
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/external/arm-trusted-firmware/bl31/
Dbl31.ld.S16 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
20 #define NOBITS RAM
44 } >RAM
58 } >RAM
81 } >RAM
89 #define SPM_SHIM_EXCEPTIONS_VMA RAM
105 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
117 DATA_SECTION >RAM
118 RELA_SECTION >RAM
/external/linux-kselftest/tools/testing/selftests/vm/
Dtranshuge-stress.c60 size_t ram, len; in main() local
67 ram = sysconf(_SC_PHYS_PAGES); in main()
68 if (ram > SIZE_MAX / sysconf(_SC_PAGESIZE) / 4) in main()
69 ram = SIZE_MAX / 4; in main()
71 ram *= sysconf(_SC_PAGESIZE); in main()
74 len = ram; in main()
81 " and %zd MiB of ram", len >> HPAGE_SHIFT, len >> 20, in main()
82 ram >> (20 + HPAGE_SHIFT - PAGE_SHIFT - 1)); in main()
98 map_len = ram >> (HPAGE_SHIFT - 1); in main()
/external/arm-trusted-firmware/services/std_svc/rmmd/trp/
Dlinker.lds18 RAM (rwx): ORIGIN = RMM_BASE, LENGTH = RMM_LIMIT - RMM_BASE
30 } >RAM
36 } >RAM
44 } >RAM
50 } >RAM
54 STACK_SECTION >RAM
/external/igt-gpu-tools/lib/
Dintel_os.c60 * The total amount of system RAM available in MB.
81 #error "Unknown how to get RAM size for this OS" in intel_get_total_ram_mb()
104 * The amount of unused system RAM available in MB.
152 #error "Unknown how to get available RAM for this OS" in intel_get_avail_ram_mb()
242 * least 3/4 of available RAM in intel_get_total_pinnable_mem()
318 mode & (CHECK_RAM | CHECK_SWAP) ? "RAM" : "", in __intel_check_memory()
344 * @mode: a bit field declaring whether the test will be run in RAM or in SWAP
349 * RAM and/or SWAP depending upon @mode) and determines whether there is
352 * Most tests should check that there is enough RAM to hold their working set.
353 * The rare swap thrashing tests should check that there is enough RAM + SWAP
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/external/pigweed/targets/emcraft_sf2_som/
DBUILD.gn45 # from SPI flash to external RAM. For now use the allocated eNVM flash
54 # With external RAM remapped, we use the entire internal ram for the
58 # Using external DDR RAM, we just need to make sure we go past our ROM
74 # from SPI flash to external RAM. For now use the allocated eNVM flash
83 # With external RAM remapped, we use the entire internal ram for the
87 # Using external DDR RAM, we just need to make sure we go past our ROM
/external/pigweed/pw_stm32cube_build/py/pw_stm32cube_build/
Dicf_to_ld.py118 stm32 families. It only contains regions for RAM and FLASH.
128 a string linker file with the RAM/FLASH specified by the given reginos.
131 KeyError if ld_regions does not contain 'RAM' and 'FLASH'
135 _estack = ORIGIN(RAM) + LENGTH(RAM);
142 RAM (xrw) : ORIGIN = {ld_regions['RAM'][0]}, LENGTH = {ld_regions['RAM'][1]}
237 }} >RAM AT> FLASH
251 }} >RAM
266 }} >RAM

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