| /external/go-cmp/ |
| D | Android.gen.bp | 2 // go2bp -rewrite github.com/google/go-cmp/cmp=go-cmp
5 name: "go-cmp",
6 pkgPath: "github.com/google/go-cmp/cmp",
8 "go-cmp-internal-diff",
9 "go-cmp-internal-flags",
10 "go-cmp-internal-function",
11 "go-cmp-internal-teststructs",
12 "go-cmp-internal-value",
15 "cmp/compare.go",
16 "cmp/export_unsafe.go",
[all …]
|
| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_fcmp.pnacl.ll | 6 %cmp = fcmp false float %a, %b
7 %cmp.ret_ext = zext i1 %cmp to i32
8 ret i32 %cmp.ret_ext
15 %cmp = fcmp false double %a, %b
16 %cmp.ret_ext = zext i1 %cmp to i32
17 ret i32 %cmp.ret_ext
24 %cmp = fcmp oeq float %a, %b
25 %cmp.ret_ext = zext i1 %cmp to i32
26 ret i32 %cmp.ret_ext
35 %cmp = fcmp oeq double %a, %b
[all …]
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| D | test_icmp_i1vec.ll | 5 %cmp = icmp eq <16 x i1> %a.trunc, %b.trunc
6 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
7 ret <16 x i8> %cmp.sext
14 %cmp = icmp ne <16 x i1> %a.trunc, %b.trunc
15 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
16 ret <16 x i8> %cmp.sext
23 %cmp = icmp ugt <16 x i1> %a.trunc, %b.trunc
24 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
25 ret <16 x i8> %cmp.sext
32 %cmp = icmp uge <16 x i1> %a.trunc, %b.trunc
[all …]
|
| /external/vixl/test/aarch32/traces/ |
| D | assembler-cond-rdlow-operand-imm8-cmp-t32.h | 38 0x00, 0x28 // cmp al r0 0
41 0x01, 0x28 // cmp al r0 1
44 0x02, 0x28 // cmp al r0 2
47 0x03, 0x28 // cmp al r0 3
50 0x04, 0x28 // cmp al r0 4
53 0x05, 0x28 // cmp al r0 5
56 0x06, 0x28 // cmp al r0 6
59 0x07, 0x28 // cmp al r0 7
62 0x08, 0x28 // cmp al r0 8
65 0x09, 0x28 // cmp al r0 9
[all …]
|
| D | assembler-cond-rd-operand-rn-cmp-a32.h | 38 0x02, 0x00, 0x5d, 0xb1 // cmp lt r13 r2
41 0x09, 0x00, 0x52, 0x21 // cmp cs r2 r9
44 0x01, 0x00, 0x5c, 0x11 // cmp ne r12 r1
47 0x01, 0x00, 0x50, 0x31 // cmp cc r0 r1
50 0x00, 0x00, 0x56, 0x51 // cmp pl r6 r0
53 0x06, 0x00, 0x51, 0x51 // cmp pl r1 r6
56 0x04, 0x00, 0x5a, 0x61 // cmp vs r10 r4
59 0x04, 0x00, 0x5a, 0x41 // cmp mi r10 r4
62 0x03, 0x00, 0x5c, 0xa1 // cmp ge r12 r3
65 0x00, 0x00, 0x52, 0xb1 // cmp lt r2 r0
[all …]
|
| D | assembler-cond-rd-operand-rn-cmp-t32.h | 38 0x80, 0x42 // cmp al r0 r0
41 0x88, 0x42 // cmp al r0 r1
44 0x90, 0x42 // cmp al r0 r2
47 0x98, 0x42 // cmp al r0 r3
50 0xa0, 0x42 // cmp al r0 r4
53 0xa8, 0x42 // cmp al r0 r5
56 0xb0, 0x42 // cmp al r0 r6
59 0xb8, 0x42 // cmp al r0 r7
62 0x40, 0x45 // cmp al r0 r8
65 0x48, 0x45 // cmp al r0 r9
[all …]
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| D | assembler-cond-rd-operand-const-cmp-t32.h | 38 0xb0, 0xf5, 0xff, 0x7f // cmp al r0 0x000001fe
41 0xb0, 0xf5, 0x7f, 0x7f // cmp al r0 0x000003fc
44 0xb0, 0xf5, 0xff, 0x6f // cmp al r0 0x000007f8
47 0xb0, 0xf5, 0x7f, 0x6f // cmp al r0 0x00000ff0
50 0xb0, 0xf5, 0xff, 0x5f // cmp al r0 0x00001fe0
53 0xb0, 0xf5, 0x7f, 0x5f // cmp al r0 0x00003fc0
56 0xb0, 0xf5, 0xff, 0x4f // cmp al r0 0x00007f80
59 0xb0, 0xf5, 0x7f, 0x4f // cmp al r0 0x0000ff00
62 0xb0, 0xf5, 0xff, 0x3f // cmp al r0 0x0001fe00
65 0xb0, 0xf5, 0x7f, 0x3f // cmp al r0 0x0003fc00
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to31-cmp-a32.h | 38 0x65, 0x05, 0x55, 0x71 // cmp vc r5 r5 ROR 10
41 0xe4, 0x08, 0x53, 0x11 // cmp ne r3 r4 ROR 17
44 0x6a, 0x08, 0x59, 0x21 // cmp cs r9 r10 ROR 16
47 0xe2, 0x0e, 0x50, 0xb1 // cmp lt r0 r2 ROR 29
50 0xe2, 0x0b, 0x5b, 0xe1 // cmp al r11 r2 ROR 23
53 0x81, 0x0e, 0x57, 0x81 // cmp hi r7 r1 LSL 29
56 0xe3, 0x0a, 0x55, 0x01 // cmp eq r5 r3 ROR 21
59 0xea, 0x06, 0x52, 0x51 // cmp pl r2 r10 ROR 13
62 0x81, 0x0b, 0x51, 0xb1 // cmp lt r1 r1 LSL 23
65 0xea, 0x0f, 0x5b, 0x41 // cmp mi r11 r10 ROR 31
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to31-cmp-t32.h | 38 0xbe, 0xeb, 0x78, 0x5f // cmp al r14 r8 ROR 21
41 0xb5, 0xeb, 0x3d, 0x1f // cmp al r5 r13 ROR 4
44 0xb0, 0xeb, 0x33, 0x1f // cmp al r0 r3 ROR 4
47 0xb3, 0xeb, 0xfe, 0x1f // cmp al r3 r14 ROR 7
50 0xb2, 0xeb, 0x86, 0x7f // cmp al r2 r6 LSL 30
53 0xbb, 0xeb, 0x84, 0x6f // cmp al r11 r4 LSL 26
56 0xb7, 0xeb, 0x80, 0x7f // cmp al r7 r0 LSL 30
59 0xb0, 0xeb, 0x79, 0x4f // cmp al r0 r9 ROR 17
62 0xbb, 0xeb, 0xf3, 0x7f // cmp al r11 r3 ROR 31
65 0xb8, 0xeb, 0x38, 0x5f // cmp al r8 r8 ROR 20
[all …]
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| D | assembler-cond-rdlow-operand-imm8-in-it-block-cmp-t32.h | 38 0x78, 0xbf, 0x6f, 0x29 // It vc; cmp vc r1 111
41 0x18, 0xbf, 0x86, 0x29 // It ne; cmp ne r1 134
44 0x18, 0xbf, 0x15, 0x2d // It ne; cmp ne r5 21
47 0x28, 0xbf, 0xdd, 0x2e // It cs; cmp cs r6 221
50 0x28, 0xbf, 0x64, 0x2b // It cs; cmp cs r3 100
53 0xd8, 0xbf, 0xd1, 0x2a // It le; cmp le r2 209
56 0x98, 0xbf, 0x08, 0x2f // It ls; cmp ls r7 8
59 0x28, 0xbf, 0xc9, 0x2f // It cs; cmp cs r7 201
62 0x18, 0xbf, 0x70, 0x2b // It ne; cmp ne r3 112
65 0xb8, 0xbf, 0x98, 0x2c // It lt; cmp lt r4 152
[all …]
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| D | assembler-cond-rd-operand-rn-shift-rs-cmp-a32.h | 38 0x1b, 0x0c, 0x5d, 0xc1 // cmp gt r13 r11 LSL r12
41 0x34, 0x06, 0x5c, 0xc1 // cmp gt r12 r4 LSR r6
44 0x7d, 0x02, 0x5b, 0xa1 // cmp ge r11 r13 ROR r2
47 0x58, 0x0a, 0x59, 0x81 // cmp hi r9 r8 ASR r10
50 0x1a, 0x04, 0x59, 0xe1 // cmp al r9 r10 LSL r4
53 0x3b, 0x04, 0x54, 0xc1 // cmp gt r4 r11 LSR r4
56 0x56, 0x0b, 0x54, 0x71 // cmp vc r4 r6 ASR r11
59 0x3e, 0x09, 0x59, 0x41 // cmp mi r9 r14 LSR r9
62 0x3a, 0x08, 0x55, 0x11 // cmp ne r5 r10 LSR r8
65 0x70, 0x0b, 0x53, 0x01 // cmp eq r3 r0 ROR r11
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to32-cmp-t32.h | 38 0xb7, 0xeb, 0x57, 0x1f // cmp al r7 r7 LSR 5
41 0xb0, 0xeb, 0xa3, 0x7f // cmp al r0 r3 ASR 30
44 0xba, 0xeb, 0xe5, 0x7f // cmp al r10 r5 ASR 31
47 0xbc, 0xeb, 0x29, 0x4f // cmp al r12 r9 ASR 16
50 0xb5, 0xeb, 0xe3, 0x7f // cmp al r5 r3 ASR 31
53 0xba, 0xeb, 0xa8, 0x2f // cmp al r10 r8 ASR 10
56 0xb6, 0xeb, 0xd7, 0x2f // cmp al r6 r7 LSR 11
59 0xbd, 0xeb, 0xec, 0x7f // cmp al r13 r12 ASR 31
62 0xb4, 0xeb, 0xa0, 0x5f // cmp al r4 r0 ASR 22
65 0xb3, 0xeb, 0xea, 0x5f // cmp al r3 r10 ASR 23
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to32-cmp-a32.h | 38 0xad, 0x0b, 0x5a, 0x01 // cmp eq r10 r13 LSR 23
41 0xad, 0x06, 0x5c, 0x01 // cmp eq r12 r13 LSR 13
44 0x25, 0x06, 0x5d, 0x51 // cmp pl r13 r5 LSR 12
47 0xcb, 0x06, 0x58, 0x71 // cmp vc r8 r11 ASR 13
50 0xcc, 0x00, 0x59, 0xe1 // cmp al r9 r12 ASR 1
53 0xc3, 0x0f, 0x5a, 0x61 // cmp vs r10 r3 ASR 31
56 0x4b, 0x07, 0x52, 0x51 // cmp pl r2 r11 ASR 14
59 0xaa, 0x0d, 0x5b, 0xe1 // cmp al r11 r10 LSR 27
62 0xa8, 0x09, 0x5a, 0xd1 // cmp le r10 r8 LSR 19
65 0xc2, 0x04, 0x56, 0x71 // cmp vc r6 r2 ASR 9
[all …]
|
| D | assembler-cond-rd-operand-const-can-use-pc-cmp-a32.h | 38 0xab, 0x08, 0x5a, 0x93 // cmp ls r10 0x00ab0000
41 0xff, 0x02, 0x5d, 0x93 // cmp ls r13 0xf000000f
44 0xff, 0x0d, 0x54, 0x53 // cmp pl r4 0x00003fc0
47 0xab, 0x08, 0x5f, 0x13 // cmp ne r15 0x00ab0000
50 0xab, 0x09, 0x5e, 0xb3 // cmp lt r14 0x002ac000
53 0xab, 0x00, 0x5f, 0x03 // cmp eq r15 0x000000ab
56 0xab, 0x09, 0x56, 0xe3 // cmp al r6 0x002ac000
59 0xab, 0x0b, 0x52, 0x53 // cmp pl r2 0x0002ac00
62 0x00, 0x00, 0x58, 0x43 // cmp mi r8 0x00000000
65 0xab, 0x07, 0x5d, 0x53 // cmp pl r13 0x02ac0000
[all …]
|
| D | assembler-cond-rd-operand-rn-in-it-block-cmp-t32.h | 38 0x08, 0xbf, 0x80, 0x42 // It eq; cmp eq r0 r0
41 0x08, 0xbf, 0x88, 0x42 // It eq; cmp eq r0 r1
44 0x08, 0xbf, 0x90, 0x42 // It eq; cmp eq r0 r2
47 0x08, 0xbf, 0x98, 0x42 // It eq; cmp eq r0 r3
50 0x08, 0xbf, 0xa0, 0x42 // It eq; cmp eq r0 r4
53 0x08, 0xbf, 0xa8, 0x42 // It eq; cmp eq r0 r5
56 0x08, 0xbf, 0xb0, 0x42 // It eq; cmp eq r0 r6
59 0x08, 0xbf, 0xb8, 0x42 // It eq; cmp eq r0 r7
62 0x08, 0xbf, 0x40, 0x45 // It eq; cmp eq r0 r8
65 0x08, 0xbf, 0x48, 0x45 // It eq; cmp eq r0 r9
[all …]
|
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | LowLevel.cpp | 156 TEST_F(AssemblerX8664LowLevelTest, Cmp) { in TEST_F() argument
276 /* cmp GPR, GPR */ in TEST_F()
277 TestRegReg(cmp, eax, ecx, i32, 2, 0x3B, 0xC1); in TEST_F()
278 TestRegReg(cmp, ecx, edx, i32, 2, 0x3B, 0xCA); in TEST_F()
279 TestRegReg(cmp, edx, ebx, i32, 2, 0x3B, 0xD3); in TEST_F()
280 TestRegReg(cmp, ebx, esp, i32, 2, 0x3B, 0xDC); in TEST_F()
281 TestRegReg(cmp, esp, ebp, i32, 2, 0x3B, 0xE5); in TEST_F()
282 TestRegReg(cmp, ebp, esi, i32, 2, 0x3B, 0xEE); in TEST_F()
283 TestRegReg(cmp, esi, edi, i32, 2, 0x3B, 0xF7); in TEST_F()
284 TestRegReg(cmp, edi, r8, i32, 3, 0x41, 0x3B, 0xF8); in TEST_F()
[all …]
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | icmp-shr.ll | 9 %cmp = icmp eq i8 %shr, 0
10 ret i1 %cmp
17 %cmp = icmp eq i8 %shr, 0
18 ret i1 %cmp
25 %cmp = icmp ne i8 %shr, 0
26 ret i1 %cmp
33 %cmp = icmp ne i8 %shr, 0
34 ret i1 %cmp
41 %cmp = icmp eq i8 %shr, 128
42 ret i1 %cmp
[all …]
|
| D | cast-int-fcmp-eq-0.ll | 8 %cmp = fcmp oeq float %f, 0.0
9 ret i1 %cmp
17 %cmp = fcmp oeq float %f, -0.0
18 ret i1 %cmp
26 %cmp = fcmp oeq float %f, 0.0
27 ret i1 %cmp
35 %cmp = fcmp oeq float %f, -0.0
36 ret i1 %cmp
44 %cmp = fcmp one float %f, 0.0
45 ret i1 %cmp
[all …]
|
| D | or-fcmp.ll | 8 %cmp = fcmp false double %a, %b
10 %retval = or i1 %cmp, %cmp1
16 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double %a, %b
17 ; CHECK-NEXT: ret i1 [[CMP]]
19 %cmp = fcmp oeq double %a, %b
21 %retval = or i1 %cmp, %cmp1
30 %cmp = fcmp oeq double %a, %b
32 %retval = or i1 %cmp, %cmp1
38 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double %a, %b
39 ; CHECK-NEXT: ret i1 [[CMP]]
[all …]
|
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | LowLevel.cpp | 109 TEST_F(AssemblerX8632LowLevelTest, Cmp) { in TEST_F() argument
235 /* cmp GPR, GPR */ in TEST_F()
236 TestRegReg(cmp, eax, ecx, i32, 2, 0x3B, 0xC1); in TEST_F()
237 TestRegReg(cmp, ecx, edx, i32, 2, 0x3B, 0xCA); in TEST_F()
238 TestRegReg(cmp, edx, ebx, i32, 2, 0x3B, 0xD3); in TEST_F()
239 TestRegReg(cmp, ebx, esp, i32, 2, 0x3B, 0xDC); in TEST_F()
240 TestRegReg(cmp, esp, ebp, i32, 2, 0x3B, 0xE5); in TEST_F()
241 TestRegReg(cmp, ebp, esi, i32, 2, 0x3B, 0xEE); in TEST_F()
242 TestRegReg(cmp, esi, edi, i32, 2, 0x3B, 0xF7); in TEST_F()
243 TestRegReg(cmp, edi, eax, i32, 2, 0x3B, 0xF8); in TEST_F()
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-fast-isel-icmp.ll | 6 ; CHECK: cmp w0, #31
8 %cmp = icmp eq i32 %a, 31
9 %conv = zext i1 %cmp to i32
18 %cmp = icmp eq i32 %a, -7
19 %conv = zext i1 %cmp to i32
26 ; CHECK: cmp w0, w1
28 %cmp = icmp eq i32 %a, %b
29 %conv = zext i1 %cmp to i32
36 ; CHECK: cmp w0, w1
38 %cmp = icmp ne i32 %a, %b
[all …]
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| /external/rust/crates/semver/src/ |
| D | eval.rs | 4 for cmp in &req.comparators { in matches_req()
5 if !matches_impl(cmp, ver) { in matches_req()
17 for cmp in &req.comparators { in matches_req()
18 if pre_is_compatible(cmp, ver) { in matches_req()
26 pub(crate) fn matches_comparator(cmp: &Comparator, ver: &Version) -> bool { in matches_comparator()
27 matches_impl(cmp, ver) && (ver.pre.is_empty() || pre_is_compatible(cmp, ver)) in matches_comparator()
30 fn matches_impl(cmp: &Comparator, ver: &Version) -> bool { in matches_impl()
31 match cmp.op { in matches_impl()
32 Op::Exact | Op::Wildcard => matches_exact(cmp, ver), in matches_impl()
33 Op::Greater => matches_greater(cmp, ver), in matches_impl()
[all …]
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| /external/mesa3d/src/intel/tools/tests/gen6/ |
| D | cmp.asm | 1 cmp.ge.f0.0(8) g38<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
2 cmp.l.f0.0(8) g39<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
5 cmp.ge.f0.0(8) null<1>F g38<4>.xF g36<4>.xF { align16 1Q };
6 cmp.g.f0.0(8) null<1>UD g17<4>.xUD 0x00000000UD { align16 1Q };
7 cmp.ge.f0.0(8) null<1>UD g18<4>.xUD g17<4>.xUD { align16 1Q };
8 cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q };
9 cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H };
10 cmp.z.f0.0(8) null<1>UD g9<4>.xUD 0x00000000UD { align16 1Q };
[all …]
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| /external/mesa3d/src/intel/tools/tests/gen7.5/ |
| D | cmp.asm | 1 cmp.z.f0.0(8) g7<1>D g6<8,8,1>D g2.5<0,1,0>D { align1 1Q };
2 cmp.z.f0.0(16) g11<1>D g9<8,8,1>D g2.5<0,1,0>D { align1 1H };
3 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
4 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
5 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
6 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
7 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
8 cmp.ge.f0.0(8) g15<1>D (abs)g14<4>D 1D { align16 1Q };
9 cmp.ge.f0.0(8) g16<1>F g15<4>F 0x3f800000F /* 1F */ { align16 1Q };
10 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
[all …]
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| /external/mesa3d/src/intel/tools/tests/gen7/ |
| D | cmp.asm | 1 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
2 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
3 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
4 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
5 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
6 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
7 cmp.z.f0.0(8) null<1>D g13<4>.xyyyD g6<0>.yzzzD { align16 1Q switch };
8 cmp.ge.f0.0(8) g33<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
9 cmp.l.f0.0(8) g34<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
10 cmp.ge.f0.0(8) g2<1>F g23<8,8,1>F g51<0,1,0>F { align1 1Q };
[all …]
|