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/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DInstructionConstants.java25 * In order to save memory you can use some instructions multiply,
28 * changed. Since some of these instructions like ICONST_0 occur
33 * The Instructions can also accessed directly under their names, so
171 /** Get object via its opcode, for immutable instructions like
172 * branch instructions entries are set to null.
174 Instruction[] INSTRUCTIONS = new Instruction[256]; field
183 INSTRUCTIONS[Const.NOP] = NOP; in Clinit()
184 INSTRUCTIONS[Const.ACONST_NULL] = ACONST_NULL; in Clinit()
185 INSTRUCTIONS[Const.ICONST_M1] = ICONST_M1; in Clinit()
186 INSTRUCTIONS[Const.ICONST_0] = ICONST_0; in Clinit()
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DInstructionConst.java25 * In order to save memory you can use some instructions multiply,
28 * changed. Since some of these instructions like ICONST_0 occur
33 * The Instructions can also accessed directly under their names, so
172 /** Get object via its opcode, for immutable instructions like
173 * branch instructions entries are set to null.
175 private static final Instruction[] INSTRUCTIONS = new Instruction[256]; field in InstructionConst
178 INSTRUCTIONS[Const.NOP] = NOP;
179 INSTRUCTIONS[Const.ACONST_NULL] = ACONST_NULL;
180 INSTRUCTIONS[Const.ICONST_M1] = ICONST_M1;
181 INSTRUCTIONS[Const.ICONST_0] = ICONST_0;
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/external/tensorflow/tensorflow/compiler/xla/service/
Dhlo_rematerialization_test_utils_test.cc41 // Prescriptive check to verify that all expected instructions appear. in TEST_F()
42 std::vector<HloInstruction*> instructions(computation->instructions().begin(), in TEST_F() local
43 computation->instructions().end()); in TEST_F()
44 EXPECT_EQ(instructions[0]->name(), "param"); in TEST_F()
45 EXPECT_EQ(instructions[1]->name(), "reshape"); in TEST_F()
46 EXPECT_THAT(instructions[1]->operands(), in TEST_F()
47 UnorderedElementsAre(instructions[0])); in TEST_F()
48 EXPECT_EQ(instructions[2]->name(), "broadcast"); in TEST_F()
49 EXPECT_THAT(instructions[2]->operands(), in TEST_F()
50 UnorderedElementsAre(instructions[1])); in TEST_F()
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/external/mesa3d/src/compiler/glsl/
Dir_optimization.h100 bool do_rebalance_tree(exec_list *instructions);
101 bool do_algebraic(exec_list *instructions, bool native_integers,
103 bool opt_conditional_discard(exec_list *instructions);
104 bool do_constant_folding(exec_list *instructions);
105 bool do_constant_variable(exec_list *instructions);
106 bool do_constant_variable_unlinked(exec_list *instructions);
107 bool do_copy_propagation_elements(exec_list *instructions);
108 bool do_constant_propagation(exec_list *instructions);
114 bool do_dead_code(exec_list *instructions, bool uniform_locations_assigned);
115 bool do_dead_code_local(exec_list *instructions);
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Dbuiltin_int64.h89 exec_list *const f0013_parent_instructions = body.instructions; in udivmod64()
91 /* THEN INSTRUCTIONS */ in udivmod64()
92 body.instructions = &f0013->then_instructions; in udivmod64()
105 exec_list *const f0019_parent_instructions = body.instructions; in udivmod64()
107 body.instructions = &f0019->body_instructions; in udivmod64()
112 exec_list *const f001A_parent_instructions = body.instructions; in udivmod64()
114 /* THEN INSTRUCTIONS */ in udivmod64()
115 body.instructions = &f001A->then_instructions; in udivmod64()
120 body.instructions = f001A_parent_instructions; in udivmod64()
132 exec_list *const f001C_parent_instructions = body.instructions; in udivmod64()
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/external/mesa3d/src/gallium/drivers/zink/nir_to_spirv/
Dspirv_builder.c229 spirv_buffer_prepare(&b->instructions, b->mem_ctx, 1); in spirv_builder_emit_vertex()
230 spirv_buffer_emit_word(&b->instructions, SpvOpEmitVertex | (1 << 16)); in spirv_builder_emit_vertex()
236 spirv_buffer_prepare(&b->instructions, b->mem_ctx, 1); in spirv_builder_end_primitive()
237 spirv_buffer_emit_word(&b->instructions, SpvOpEndPrimitive | (1 << 16)); in spirv_builder_end_primitive()
325 spirv_buffer_prepare(&b->instructions, b->mem_ctx, 3); in spirv_builder_emit_undef()
326 spirv_buffer_emit_word(&b->instructions, SpvOpUndef | (3 << 16)); in spirv_builder_emit_undef()
327 spirv_buffer_emit_word(&b->instructions, result_type); in spirv_builder_emit_undef()
328 spirv_buffer_emit_word(&b->instructions, result); in spirv_builder_emit_undef()
338 spirv_buffer_prepare(&b->instructions, b->mem_ctx, 5); in spirv_builder_function()
339 spirv_buffer_emit_word(&b->instructions, SpvOpFunction | (5 << 16)); in spirv_builder_function()
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/external/llvm/test/MC/Mips/
Dset-nomacro.s3 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
81 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
83 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
88 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
92 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
99 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
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/external/rust/crates/tinytemplate/src/
Dcompiler.rs6 /// template strings and generating the appropriate bytecode instructions.
27 /// instructions based on it. The parser is a simple hand-written pattern-matching parser with no
32 instructions: Vec<Instruction<'template>>, field
45 instructions: vec![], in new()
80 .push((discriminant, Block::Branch(self.instructions.len()))); in compile()
81 self.instructions in compile()
86 let num_instructions = self.instructions.len() + 1; in compile()
89 .push((discriminant, Block::Branch(self.instructions.len()))); in compile()
90 self.instructions.push(Instruction::Goto(UNKNOWN)) in compile()
94 let num_instructions = self.instructions.len(); in compile()
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/external/google-breakpad/src/common/android/include/asm-mips/
Dasm.h29 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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/external/tensorflow/tensorflow/python/util/
Ddeprecation_test.py93 instructions = "This is how you update..."
95 @deprecation.deprecated(date, instructions, warn_once=True)
107 instructions = "This is how you update..."
109 @deprecation.deprecated(date, instructions, warn_once=True)
125 instructions = "This is how you update..."
127 @deprecation.deprecated(date, instructions, warn_once=True)
142 instructions = "This is how you update..."
144 @deprecation.deprecated(date, instructions, warn_once=True)
158 instructions = "This is how you update..."
161 date, instructions, warn_once=True)(
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/external/robolectric-shadows/sandbox/src/main/java/org/robolectric/internal/bytecode/
DOldClassInstrumentor.java182 ListIterator<AbstractInsnNode> instructions, MethodInsnNode targetMethod) { in interceptInvokeVirtualMethod() argument
183 interceptInvokeVirtualMethodWithoutInvokeDynamic(mutableClass, instructions, targetMethod); in interceptInvokeVirtualMethod()
191 ListIterator<AbstractInsnNode> instructions, MethodInsnNode targetMethod) { in interceptInvokeVirtualMethodWithoutInvokeDynamic() argument
194 instructions.remove(); // remove the method invocation in interceptInvokeVirtualMethodWithoutInvokeDynamic()
198 instructions.add(new LdcInsnNode(argumentTypes.length)); in interceptInvokeVirtualMethodWithoutInvokeDynamic()
199 instructions.add(new TypeInsnNode(Opcodes.ANEWARRAY, "java/lang/Object")); in interceptInvokeVirtualMethodWithoutInvokeDynamic()
207 instructions.add(new InsnNode(Opcodes.DUP_X1)); // A B [] C [] in interceptInvokeVirtualMethodWithoutInvokeDynamic()
208 instructions.add(new InsnNode(Opcodes.SWAP)); // A B [] [] C in interceptInvokeVirtualMethodWithoutInvokeDynamic()
209 instructions.add(new LdcInsnNode(i)); // A B [] [] C 2 in interceptInvokeVirtualMethodWithoutInvokeDynamic()
210 instructions.add(new InsnNode(Opcodes.SWAP)); // A B [] [] 2 C in interceptInvokeVirtualMethodWithoutInvokeDynamic()
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/external/mesa3d/src/panfrost/midgard/
Dmidgard_schedule.c32 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
39 * execute on all). Instructions can be either vector or scalar; only scalar
40 * instructions can execute on SADD/SMUL units. Units on a given line execute
45 * all of the instructions within a bundle.
47 * Instructions consuming conditionals (branches and conditional selects)
54 * Load/store instructions are also in bundles of simply two instructions, and
55 * texture instructions have no bundling.
66 …dynarray *table, unsigned index, uint16_t mask, midgard_instruction **instructions, unsigned child) in add_dependency() argument
75 BITSET_WORD *dependents = instructions[*parent]->dependents; in add_dependency()
82 instructions[child]->nr_dependencies++; in add_dependency()
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/external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/analysis/
DLineImpl.java48 * Empty line without instructions or branches.
52 private static LineImpl getInstance(final CounterImpl instructions, in getInstance() argument
54 final int im = instructions.getMissedCount(); in getInstance()
55 final int ic = instructions.getCoveredCount(); in getInstance()
62 return new Var(instructions, branches); in getInstance()
69 Var(final CounterImpl instructions, final CounterImpl branches) { in Var() argument
70 super(instructions, branches); in Var()
74 public LineImpl increment(final ICounter instructions, in increment() argument
76 this.instructions = this.instructions.increment(instructions); in increment()
92 public LineImpl increment(final ICounter instructions, in increment() argument
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/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/analysis/filter/
DAbstractMatcherTest.java45 matcher.cursor = m.instructions.getFirst(); in skipNonOpcodes()
47 assertSame(m.instructions.getLast(), matcher.cursor); in skipNonOpcodes()
51 assertSame(m.instructions.getLast(), matcher.cursor); in skipNonOpcodes()
64 matcher.cursor = m.instructions.getFirst(); in nextIs()
69 matcher.cursor = m.instructions.getFirst(); in nextIs()
71 assertSame(m.instructions.getLast(), matcher.cursor); in nextIs()
83 matcher.cursor = m.instructions.getFirst(); in nextIsSwitch()
88 m.instructions.clear(); in nextIsSwitch()
91 matcher.cursor = m.instructions.getFirst(); in nextIsSwitch()
93 assertSame(m.instructions.getLast(), matcher.cursor); in nextIsSwitch()
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/external/swiftshader/third_party/SPIRV-Tools/source/fuzz/
Dfuzzer_pass_add_equation_instructions.h25 // Fuzzer pass that sprinkles instructions through the module that define
38 // Yields those instructions in |instructions| that have integer scalar or
41 const std::vector<opt::Instruction*>& instructions) const;
43 // Returns only instructions, that have either a scalar floating-point or a
46 const std::vector<opt::Instruction*>& instructions) const;
48 // Yields those instructions in |instructions| that have boolean scalar or
51 const std::vector<opt::Instruction*>& instructions) const;
53 // Yields those instructions in |instructions| that have a scalar numerical or
55 // are supported if both OpTypeInt and OpTypeFloat instructions can be created
59 const std::vector<opt::Instruction*>& instructions) const;
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/external/angle/third_party/vulkan-deps/spirv-tools/src/source/fuzz/
Dfuzzer_pass_add_equation_instructions.h25 // Fuzzer pass that sprinkles instructions through the module that define
38 // Yields those instructions in |instructions| that have integer scalar or
41 const std::vector<opt::Instruction*>& instructions) const;
43 // Returns only instructions, that have either a scalar floating-point or a
46 const std::vector<opt::Instruction*>& instructions) const;
48 // Yields those instructions in |instructions| that have boolean scalar or
51 const std::vector<opt::Instruction*>& instructions) const;
53 // Yields those instructions in |instructions| that have a scalar numerical or
55 // are supported if both OpTypeInt and OpTypeFloat instructions can be created
59 const std::vector<opt::Instruction*>& instructions) const;
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/external/deqp-deps/SPIRV-Tools/source/fuzz/
Dfuzzer_pass_add_equation_instructions.h25 // Fuzzer pass that sprinkles instructions through the module that define
38 // Yields those instructions in |instructions| that have integer scalar or
41 const std::vector<opt::Instruction*>& instructions) const;
43 // Returns only instructions, that have either a scalar floating-point or a
46 const std::vector<opt::Instruction*>& instructions) const;
48 // Yields those instructions in |instructions| that have boolean scalar or
51 const std::vector<opt::Instruction*>& instructions) const;
53 // Yields those instructions in |instructions| that have a scalar numerical or
55 // are supported if both OpTypeInt and OpTypeFloat instructions can be created
59 const std::vector<opt::Instruction*>& instructions) const;
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/external/llvm/docs/
DHowToUseInstrMappings.rst14 could be to use switch cases which list all the instructions along with formats
24 TableGen uses relationship models to map instructions with each other. These
27 describe all the instructions using that model. TableGen parses all the relation
29 instructions with each other. These tables are emitted in the
36 // Used to reduce search space only to the instructions using this
40 // List of fields/attributes that should be same for all the instructions in
42 // by all the instructions related by this relationship.
45 // List of fields/attributes that are same for all the instructions
55 // each column in the relation table. These are the instructions a key
67 to define a relationship model that relates predicated instructions to their
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/external/cpuinfo/src/x86/
Disa.c57 * OSXSAVE: Operating system enabled XSAVE instructions for application use: in cpuinfo_x86_detect_isa()
58 * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions supported by a chip. in cpuinfo_x86_detect_isa()
59 * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions enabled by OS. in cpuinfo_x86_detect_isa()
115 * SYSENTER/SYSEXIT instructions: in cpuinfo_x86_detect_isa()
122 * SYSCALL/SYSRET instructions: in cpuinfo_x86_detect_isa()
129 * RDMSR/WRMSR instructions: in cpuinfo_x86_detect_isa()
154 * MWAIT/MONITOR instructions: in cpuinfo_x86_detect_isa()
160 * MWAITX/MONITORX instructions: in cpuinfo_x86_detect_isa()
166 * FXSAVE/FXRSTOR instructions: in cpuinfo_x86_detect_isa()
183 * XSAVE/XRSTOR instructions: in cpuinfo_x86_detect_isa()
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/external/swiftshader/third_party/SPIRV-Tools/source/val/
Dvalidate.h46 /// @brief Updates the use vectors of all instructions that can be referenced
69 /// instructions.
71 /// This function will iterate over all instructions and check for any required
72 /// predecessor and/or successor instructions. e.g. spv::Op::OpPhi must only be
90 /// @brief Validates memory instructions
120 /// Validates Control Flow Graph instructions.
136 /// Validates type instructions.
139 /// Validates constant instructions.
142 /// Validates correctness of arithmetic instructions.
145 /// Validates correctness of composite instructions.
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/external/angle/third_party/vulkan-deps/spirv-tools/src/source/val/
Dvalidate.h41 /// @brief Updates the use vectors of all instructions that can be referenced
64 /// instructions.
66 /// This function will iterate over all instructions and check for any required
67 /// predecessor and/or successor instructions. e.g. spv::Op::OpPhi must only be
85 /// @brief Validates memory instructions
115 /// Validates Control Flow Graph instructions.
131 /// Validates type instructions.
134 /// Validates constant instructions.
137 /// Validates correctness of arithmetic instructions.
140 /// Validates correctness of composite instructions.
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/external/mesa3d/src/compiler/glsl/tests/
Dlower_int64_test.cpp51 exec_list instructions; member in expand_source
65 instructions.make_empty(); in SetUp()
66 body = new ir_factory(&instructions, mem_ctx); in SetUp()
126 check_instructions(exec_list *instructions, in check_instructions() argument
153 ASSERT_FALSE(instructions->is_empty()); in check_instructions()
154 ir = (ir_instruction *) instructions->pop_head(); in check_instructions()
163 ASSERT_FALSE(instructions->is_empty()); in check_instructions()
164 ir = (ir_instruction *) instructions->pop_head(); in check_instructions()
172 ASSERT_FALSE(instructions->is_empty()); in check_instructions()
173 ir = (ir_instruction *) instructions->pop_head(); in check_instructions()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMFixupKinds.h24 // LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
26 // 10-bit PC relative relocation for symbol addresses used in VFP instructions
31 // of Thumb2 instructions.
33 // 9-bit PC relative relocation for symbol addresses used in VFP instructions
37 // of Thumb2 instructions.
46 // 24-bit PC relative relocation for conditional branch instructions.
48 // 24-bit PC relative relocation for branch instructions. (unconditional)
51 // instructions.
54 // instructions.
57 // 12-bit fixup for Thumb B instructions.
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/external/deqp-deps/SPIRV-Tools/source/val/
Dvalidate.h46 /// @brief Updates the use vectors of all instructions that can be referenced
69 /// instructions.
71 /// This function will iterate over all instructions and check for any required
72 /// predecessor and/or successor instructions. e.g. SpvOpPhi must only be
90 /// @brief Validates memory instructions
120 /// Validates Control Flow Graph instructions.
136 /// Validates type instructions.
139 /// Validates constant instructions.
142 /// Validates correctness of arithmetic instructions.
145 /// Validates correctness of composite instructions.
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMFixupKinds.h27 // addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
30 // used in VFP instructions where the lower 2 bits are not encoded
34 // the short-swapped encoding of Thumb2 instructions.
37 // used in VFP instructions where bit 0 not encoded (so it's encoded as an
41 // the short-swapped encoding of Thumb2 instructions.
54 // instructions.
57 // branch instructions. (unconditional)
60 // uconditional branch instructions.
63 // branch unconditional branch instructions.
66 // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
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