| /external/perfetto/src/trace_processor/containers/ |
| D | row_map_unittest.cc | 29 RowMap rm(10, 20); in TEST() local
30 RowMap rm_row = rm.SingleRow(15u); in TEST()
37 RowMap rm(10, 20); in TEST() local
38 RowMap rm_copy = rm.Copy(); in TEST()
43 RowMap rm(BitVector{true, false, false, false, true, true}); in TEST() local
44 RowMap rm_copy = rm.Copy(); in TEST()
49 RowMap rm(std::vector<uint32_t>{10, 17, 20, 21}); in TEST() local
50 RowMap rm_copy = rm.Copy(); in TEST()
55 RowMap rm(10, 20); in TEST() local
56 ASSERT_EQ(rm.Get(5), 15u); in TEST()
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| D | row_map_benchmark.cc | 62 void BenchRowMapGet(benchmark::State& state, RowMap rm) { in BenchRowMapGet() argument
63 auto pool_vec = CreateIndexVector(kPoolSize, rm.size()); in BenchRowMapGet()
67 benchmark::DoNotOptimize(rm.Get(pool_vec[pool_idx])); in BenchRowMapGet()
78 RowMap rm = factory(); in BenchRowMapInsertIntoEmpty() local
80 rm.Insert(pool_vec[pool_idx]); in BenchRowMapInsertIntoEmpty()
88 RowMap rm, in BenchRowMapSelect() argument
91 benchmark::DoNotOptimize(rm.SelectRows(selector)); in BenchRowMapSelect()
131 RowMap rm(CreateRange(kSize)); in BM_RowMapSelectRangeWithRange() local
132 RowMap selector(CreateRange(rm.size())); in BM_RowMapSelectRangeWithRange()
133 BenchRowMapSelect(state, std::move(rm), std::move(selector)); in BM_RowMapSelectRangeWithRange()
[all …]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 264 QRegister rm);
277 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm);
282 Register rm);
290 Register rm);
325 Condition cond, Register rd, Register rn, Register rm, Register ra);
332 Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
346 Register rm);
350 QRegister rm);
368 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
370 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
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| D | macro-assembler-aarch32.h | 1000 // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 in Adc()
1077 // ADD<c>{<q>} <Rd>, <Rn>, <Rm> in Add()
1080 // ADD<c>{<q>} <Rdn>, <Rm> ; T2 in Add()
1174 // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 in And()
1232 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { in Asr() argument
1234 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); in Asr()
1240 // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 in Asr()
1242 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || in Asr()
1244 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && in Asr()
1247 asr(cond, rd, rm, operand); in Asr()
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| D | disasm-aarch32.h | 657 Register rm,
663 Register rm,
691 void blx(Condition cond, Register rm);
693 void bx(Condition cond, Register rm);
695 void bxj(Condition cond, Register rm);
703 void clz(Condition cond, Register rd, Register rm);
715 void crc32b(Condition cond, Register rd, Register rn, Register rm);
717 void crc32cb(Condition cond, Register rd, Register rn, Register rm);
719 void crc32ch(Condition cond, Register rd, Register rn, Register rm);
721 void crc32cw(Condition cond, Register rd, Register rn, Register rm);
[all …]
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-rm-a32.json | 28 // MNEMONIC<c> <rd>, <rn>, <rm>
35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
36 "Muls", // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
37 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
38 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
39 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
40 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
41 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
42 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
[all …]
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| D | cond-rd-rn-rm-t32.json | 28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2
36 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
37 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
38 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
39 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
40 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
41 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
42 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
43 "Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
[all …]
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| D | cond-rd-rn-operand-rm-t32.json | 28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
31 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
34 // MNEMONIC{<c>}.N SP, SP, <Rm>
35 // MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm>
36 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP
37 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers
41 // "cond-rd-rn-operand-rm-shift-amount-*-t32.json".
45 "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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| D | cond-rd-memop-rs-a32.json | 29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1
37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
[all …]
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| D | cond-rd-rn-operand-rm-a32.json | 28 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm>, <Rs>
29 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
34 // "cond-rd-rn-operand-rm-shift-amount-*-a32.json".
38 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
40 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
41 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
42 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
43 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
[all …]
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| D | cond-rd-memop-rs-shift-amount-1to31-a32.json | 29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
[all …]
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
33 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
[all …]
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ASR|LSR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, ASR|LSR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, LSL|ROR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
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| D | cond-rd-memop-rs-shift-amount-1to32-a32.json | 57 "name": "rm",
85 "name": "rm",
101 "cond", "rd", "rn", "rm"
108 "rn", "sign", "rm", "shift", "amount", "addr_mode"
116 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
131 "cond", "rd", "rn", "rm"
133 "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r8'",
141 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
143 …operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm",
146 "memop", "rm"
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| D | rd-rn-rm.json | 28 // MNEMONIC <Rd>, <Rn>, <Rm>
32 "Crc32b", // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1
33 // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1
34 "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1
35 // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1
36 "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1
37 // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1
38 "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1
39 // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1
40 "Crc32h", // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1
[all …]
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| /external/python/cpython3/Tools/unicode/ |
| D | Makefile | 12 RM = /bin/rm macro
32 $(RM) build/atarist.*
33 $(RM) build/us_ascii_quotes.*
34 $(RM) build/ibmgraph.*
35 $(RM) build/sgml.*
36 $(RM) -f build/readme.*
43 $(RM) build/cp9*
44 $(RM) -f build/readme.*
48 $(RM) -f build/isoreadme.*
52 $(RM) build/mac_dingbats.*
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| /external/python/cpython2/Tools/unicode/ |
| D | Makefile | 12 RM = /bin/rm macro
32 $(RM) build/atarist.*
33 $(RM) build/us_ascii_quotes.*
34 $(RM) build/ibmgraph.*
35 $(RM) build/sgml.*
36 $(RM) -f build/readme.*
43 $(RM) build/cp9*
44 $(RM) -f build/readme.*
48 $(RM) -f build/isoreadme.*
52 $(RM) build/mac_dingbats.*
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| /external/mesa3d/.gitlab-ci/ |
| D | create-rootfs.sh | 77 rm -rf /etc/localtime
100 rm -rf /var/log/*
103 rm -rf /usr/share/doc/*
104 rm -rf /usr/share/locale/*
105 rm -rf /usr/share/X11/locale/*
106 rm -rf /usr/share/man
107 rm -rf /usr/share/i18n/*
108 rm -rf /usr/share/info/*
109 rm -rf /usr/share/lintian/*
110 rm -rf /usr/share/common-licenses/*
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| /external/sg3_utils/src/ |
| D | Makefile.in | 823 echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
824 cd "$(DESTDIR)$(bindir)" && rm -f $$files
828 echo " rm -f" $$list; \
829 rm -f $$list || exit $$?; \
832 echo " rm -f" $$list; \
833 rm -f $$list
836 @rm -f sg_bg_ctl$(EXEEXT)
840 @rm -f sg_compare_and_write$(EXEEXT)
844 @rm -f sg_copy_results$(EXEEXT)
848 @rm -f sg_dd$(EXEEXT)
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| /external/toybox/tests/ |
| D | rm.test | 11 testing "text-file" "rm file.txt && [ ! -e file.txt ] && echo 'yes'" "yes\n" "" ""
12 rm -f file*
14 testing "-i nonexistent" "</dev/zero rm -i file.txt 2>/dev/null || echo 'yes'" "yes\n" "" ""
17 testing "empty directory" "rm -r dir && [ ! -d dir ] && echo 'yes'" "yes\n" "" ""
18 rm -rf dir
21 testing "text file(mode 000)" "rm -f file.txt && [ ! -e file.txt ] && echo 'yes'" \
23 rm -f file*
28 "rm -r file1.txt file2.txt dir1 dir2 2>/dev/null &&
31 rm -rf file* dir*
36 "rm -rf file1.txt file2.txt file3.txt dir1 dir2 dir3 2>/dev/null &&
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| /external/markdown/ |
| D | makefile | 22 rm -rf build
23 rm -rf dist
29 rm -rf build
30 rm -rf dist
48 rm -f MANIFEST
49 rm -f test-output.html
50 rm -f *.pyc
51 rm -f markdown/*.pyc
52 rm -f markdown/extensions/*.pyc
53 rm -f *.bak
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| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 33 { /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
37 { /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
41 { /* AArch64_ADCWr, ARM64_INS_ADC: adc $rd, $rn, $rm */
45 { /* AArch64_ADCXr, ARM64_INS_ADC: adc $rd, $rn, $rm */
49 { /* AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN: addhn.2s $rd, $rn, $rm */
53 { /* AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2: addhn2.4s $rd, $rn, $rm */
57 { /* AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN: addhn.4h $rd, $rn, $rm */
61 { /* AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2: addhn2.8h $rd, $rn, $rm */
65 { /* AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2: addhn2.16b $rd, $rn, $rm */
69 { /* AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN: addhn.8b $rd, $rn, $rm */
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