| /external/perfetto/test/trace_processor/diff_tests/android/ |
| D | android_bugreport_dumpstate_test.out | 274 "HARDWARE HALS (/system/xbin/su root lshal --all --types=all)","[NULL]",359
291 "LIBRANK (/system/xbin/su root librank)","[NULL]",42470
292 "LIST OF OPEN FILES (/system/xbin/su root lsof)","[NULL]",42793
297 "MODULES INFO (/system/xbin/su root sh -c cat /proc/modules | cut -d' ' -f1 | while read MOD ; …
306 "PROCRANK (/system/xbin/su root procrank)","[NULL]",173
318 "SHOW MAP 1 (/system/bin/init) (/system/xbin/su root showmap -q 1)","[NULL]",344
319 "SHOW MAP 10 ([rcuop/0]) (/system/xbin/su root showmap -q 10)","[NULL]",8
320 "SHOW MAP 100 ([irq/125-tsens-u]) (/system/xbin/su root showmap -q 100)","[NULL]",8
321 "SHOW MAP 101 ([irq/126-tsens-c]) (/system/xbin/su root showmap -q 101)","[NULL]",8
322 "SHOW MAP 1013 (/system/bin/hw/android.hidl.allocator@1.0-service) (/system/xbin/su root showmap -q…
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { in postprocessDAG() local
30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
31 LastSequentialCall = &(SUnits[su]); in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier)); in postprocessDAG()
38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable() argument
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-stp-cluster.ll | 6 ; CHECK:Cluster ld/st SU(4) - SU(3)
7 ; CHECK:Cluster ld/st SU(2) - SU(5)
8 ; CHECK:SU(4): STRXui %vreg1, %vreg0, 1
9 ; CHECK:SU(3): STRXui %vreg1, %vreg0, 2
10 ; CHECK:SU(2): STRXui %vreg1, %vreg0, 3
11 ; CHECK:SU(5): STRXui %vreg1, %vreg0, 4
27 ; CHECK:Cluster ld/st SU(4) - SU(3)
28 ; CHECK:Cluster ld/st SU(2) - SU(5)
29 ; CHECK:SU(4): STRWui %vreg1, %vreg0, 1
30 ; CHECK:SU(3): STRWui %vreg1, %vreg0, 2
[all …]
|
| D | arm64-ldp-cluster.ll | 8 ; CHECK: Cluster ld/st SU(1) - SU(2)
9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
13 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
28 ; CHECK: Cluster ld/st SU(1) - SU(2)
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
33 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNMinRegStrategy.cpp | 31 const SUnit *SU; member
35 : SU(SU_), Priority(Priority_) {} in Candidate()
44 bool isScheduled(const SUnit *SU) const { in isScheduled()
45 assert(!SU->isBoundaryNode()); in isScheduled()
46 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); in isScheduled()
49 void setIsScheduled(const SUnit *SU) { in setIsScheduled() argument
50 assert(!SU->isBoundaryNode()); in setIsScheduled()
51 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); in setIsScheduled()
54 unsigned getNumPreds(const SUnit *SU) const { in getNumPreds()
55 assert(!SU->isBoundaryNode()); in getNumPreds()
[all …]
|
| D | GCNILPSched.cpp | 24 SUnit *SU; member
27 : SU(SU_) {} in Candidate()
41 unsigned getNodePriority(const SUnit *SU) const;
48 void releasePredecessors(const SUnit* SU);
59 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
65 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
87 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const { in getNodePriority()
88 assert(SU->NodeNum < SUNumbers.size()); in getNodePriority()
89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
[all …]
|
| D | SIMachineScheduler.cpp | 197 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
198 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
199 SUnits.push_back(SU); in addUnit()
205 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
257 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
265 for (SUnit* SU : TopReadySUs) { in pickNode()
270 TryCand.SU = SU; in pickNode()
271 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
274 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
275 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
[all …]
|
| D | R600MachineScheduler.cpp | 58 SUnit *SU = nullptr; in pickNode() local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
101 SU = pickAlu(); in pickNode()
102 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
103 SU = PhysicalRegCopy.front(); in pickNode()
106 if (SU) { in pickNode()
113 if (!SU) { in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
116 if (SU) in pickNode()
121 if (!SU) { in pickNode()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 92 /// Check if scheduling of this SU is possible
97 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { in isResourceAvailable() argument
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
127 if (hasDependence(Packet[i], SU, QII)) in isResourceAvailable()
131 if (hasDependence(SU, Packet[i], QII)) in isResourceAvailable()
138 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { in reserveResources() argument
141 if (!SU) { in reserveResources()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
69 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
142 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
144 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
151 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
153 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
168 SUnit *SU = &(*SUnits)[i]; in initNodes() local
169 initNumRegDefsLeft(SU); in initNodes()
[all …]
|
| D | ScheduleDAGRRList.cpp | 211 /// IsReachable - Checks if SU is reachable from TargetSU.
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
213 return Topo.IsReachable(SU, TargetSU); in IsReachable()
216 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
219 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
222 /// AddPredQueued - Queues and update to add a predecessor edge to SUnit SU.
225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued() argument
226 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
227 SU->addPred(D); in AddPredQueued()
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
173 SUnit *SU = &(*SUnits)[i]; in initNodes() local
174 initNumRegDefsLeft(SU); in initNodes()
[all …]
|
| D | ScheduleDAGRRList.cpp | 185 /// IsReachable - Checks if SU is reachable from TargetSU.
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
196 /// AddPred - adds a predecessor edge to SUnit SU.
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
[all …]
|
| /external/cronet/third_party/icu/source/data/zone/ |
| D | sc.txt | 43 ec{"Su Càiru"}
175 ec{"Tzitade de su Mèssicu"}
181 ec{"Beulah, Dakota de su Nord"}
184 ec{"Center, Dakota de su Nord"}
187 ec{"New Salem, Dakota de su Nord"}
286 ec{"Geòrgia de su Sud"}
367 ec{"Tzitade de su Vaticanu"}
487 ld{"Ora legale de su Patzìficu USA"}
488 lg{"Ora de su Patzìficu USA"}
489 ls{"Ora istandard de su Patzìficu USA"}
[all …]
|
| /external/icu/icu4c/source/data/zone/ |
| D | sc.txt | 43 ec{"Su Càiru"}
175 ec{"Tzitade de su Mèssicu"}
181 ec{"Beulah, Dakota de su Nord"}
184 ec{"Center, Dakota de su Nord"}
187 ec{"New Salem, Dakota de su Nord"}
286 ec{"Geòrgia de su Sud"}
367 ec{"Tzitade de su Vaticanu"}
487 ld{"Ora legale de su Patzìficu USA"}
488 lg{"Ora de su Patzìficu USA"}
489 ls{"Ora istandard de su Patzìficu USA"}
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 46 getNumDecoderSlots(SUnit *SU) const { in getNumDecoderSlots()
47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const { in getCurrCycleIdx()
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) { in getCurrCycleIdx()
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const { in fitsIntoCurrentGroup()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
109 // SU should fit into current group. NumSlots should be 1 or 0, in fitsIntoCurrentGroup()
111 assert ((getNumDecoderSlots(SU) <= 1) && (CurrGroupSize < 3) && in fitsIntoCurrentGroup()
167 void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const { in dumpSU() argument
[all …]
|
| D | SystemZMachineScheduler.cpp | 29 for (auto &SU : *this) { in dump()
30 HazardRec.dumpSU(SU, dbgs()); in dump()
31 if (SU != *rbegin()) in dump()
176 for (auto *SU : Available) { in pickNode() local
178 // SU is the next candidate to be compared against current Best. in pickNode()
179 Candidate c(SU, *HazardRec); in pickNode()
181 // Remeber which SU is the best candidate. in pickNode()
182 if (Best.SU == nullptr || c < Best) { in pickNode()
187 LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts(); in pickNode()
188 dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";); in pickNode()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 101 for (const SUnit *su : L) { in dumpSUList() local
102 dbgs() << "SU(" << su->NodeNum << ")"; in dumpSUList()
103 if (su != L.back()) in dumpSUList()
227 /// MO is an operand of SU's instruction that defines a physical register. Adds
228 /// data dependencies from SU to any uses of the physical register.
229 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
246 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
247 if (UseSU == SU) in addPhysRegDataDeps()
[all …]
|
| D | MachineScheduler.cpp | 601 for (const SUnit *SU : Queue) in dump() local
602 dbgs() << SU->NodeNum << " "; in dump()
620 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
637 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However, in releaseSucc()
639 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
640 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
647 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
648 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
649 for (SDep &Succ : SU->Succs) in releaseSuccessors()
650 releaseSucc(SU, &Succ); in releaseSuccessors()
[all …]
|
| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 554 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
571 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However, in releaseSucc()
573 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
574 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
581 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
582 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
583 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
585 releaseSucc(SU, &*I); in releaseSuccessors()
593 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
610 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However, in releasePred()
[all …]
|
| D | ScheduleDAGInstrs.cpp | 80 for (auto *su : L) { in dumpSUList() local
81 dbgs() << "SU(" << su->NodeNum << ")"; in dumpSUList()
82 if (su != L.back()) in dumpSUList()
243 /// the exit SU to the register defs and use list. This is because we want to
281 /// MO is an operand of SU's instruction that defines a physical register. Add
282 /// data dependencies from SU to any uses of the physical register.
283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
295 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
296 if (UseSU == SU) in addPhysRegDataDeps()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.cpp | 178 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
179 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
180 SUnits.push_back(SU); in addUnit()
187 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
245 for (SUnit* SU : TopReadySUs) { in pickNode()
250 TryCand.SU = SU; in pickNode()
251 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
254 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
255 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
[all …]
|
| D | R600MachineScheduler.cpp | 58 SUnit *SU = nullptr; in pickNode() local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
101 SU = pickAlu(); in pickNode()
102 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
103 SU = PhysicalRegCopy.front(); in pickNode()
106 if (SU) { in pickNode()
113 if (!SU) { in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
116 if (SU) in pickNode()
121 if (!SU) { in pickNode()
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-06-12-SchedMemLatency.ll | 8 ; CHECK: SU(2){{.*}}STR{{.*}}Volatile
9 ; CHECK-NOT: ch SU
10 ; CHECK: ch SU(3): Latency=1
11 ; CHECK-NOT: ch SU
12 ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
13 ; CHECK-NOT: ch SU
14 ; CHECK: ch SU(2): Latency=1
15 ; CHECK-NOT: ch SU
18 ; CHECK: SU(2){{.*}}STR{{.*}}
19 ; CHECK-NOT: ch SU
[all …]
|
| /external/cronet/third_party/icu/source/data/locales/ |
| D | sc.txt | 212 "EEEE dd 'de' MMMM 'de' 'su' r (U)",
213 "dd 'de' MMMM 'de' 'su' r (U)",
233 GyMMMM{"MMMM 'de' 'su' r (U)"}
234 GyMMMMEd{"E d 'de' MMMM 'de' 'su' r (U)"}
235 GyMMMMd{"d 'de' MMMM 'de' 'su' r (U)"}
253 yyyyMMMM{"MMMM 'de' 'su' r (U)"}
254 yyyyMMMMEd{"E d 'de' MMMM 'de' 'su' r (U)"}
255 yyyyMMMMd{"d 'de' MMMM 'de' 'su' r (U)"}
259 yyyyQQQQ{"QQQQ 'de' 'su' r (U)"}
265 "incumintzu de su beranu",
[all …]
|