1 /******************************************************************************
2 *
3 * Copyright (C) 2018 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*!
22 ******************************************************************************
23 * \file ihevce_memory_init.c
24 *
25 * \brief
26 * This file contains functions which perform memory requirement gathering
27 * and freeing of memories of encoder at the end
28 *
29 * \date
30 * 18/09/2012
31 *
32 * \author
33 * Ittiam
34 *
35 * List of Functions
36 * <TODO: TO BE ADDED>
37 *
38 ******************************************************************************
39 */
40
41 /*****************************************************************************/
42 /* File Includes */
43 /*****************************************************************************/
44 /* System include files */
45 #include <stdio.h>
46 #include <string.h>
47 #include <stdlib.h>
48 #include <assert.h>
49 #include <stdarg.h>
50 #include <math.h>
51
52 /* User include files */
53 #include "ihevc_typedefs.h"
54 #include "itt_video_api.h"
55 #include "ihevce_api.h"
56
57 #include "rc_cntrl_param.h"
58 #include "rc_frame_info_collector.h"
59 #include "rc_look_ahead_params.h"
60
61 #include "ihevc_defs.h"
62 #include "ihevc_macros.h"
63 #include "ihevc_debug.h"
64 #include "ihevc_structs.h"
65 #include "ihevc_platform_macros.h"
66 #include "ihevc_deblk.h"
67 #include "ihevc_itrans_recon.h"
68 #include "ihevc_chroma_itrans_recon.h"
69 #include "ihevc_chroma_intra_pred.h"
70 #include "ihevc_intra_pred.h"
71 #include "ihevc_inter_pred.h"
72 #include "ihevc_mem_fns.h"
73 #include "ihevc_padding.h"
74 #include "ihevc_weighted_pred.h"
75 #include "ihevc_sao.h"
76 #include "ihevc_resi_trans.h"
77 #include "ihevc_quant_iquant_ssd.h"
78 #include "ihevc_cabac_tables.h"
79 #include "ihevc_common_tables.h"
80
81 #include "ihevce_defs.h"
82 #include "ihevce_hle_interface.h"
83 #include "ihevce_lap_enc_structs.h"
84 #include "ihevce_lap_interface.h"
85 #include "ihevce_multi_thrd_structs.h"
86 #include "ihevce_multi_thrd_funcs.h"
87 #include "ihevce_me_common_defs.h"
88 #include "ihevce_had_satd.h"
89 #include "ihevce_error_codes.h"
90 #include "ihevce_bitstream.h"
91 #include "ihevce_cabac.h"
92 #include "ihevce_rdoq_macros.h"
93 #include "ihevce_function_selector.h"
94 #include "ihevce_enc_structs.h"
95 #include "ihevce_entropy_structs.h"
96 #include "ihevce_cmn_utils_instr_set_router.h"
97 #include "ihevce_ipe_instr_set_router.h"
98 #include "ihevce_decomp_pre_intra_structs.h"
99 #include "ihevce_decomp_pre_intra_pass.h"
100 #include "ihevce_enc_loop_structs.h"
101 #include "ihevce_nbr_avail.h"
102 #include "ihevce_enc_loop_utils.h"
103 #include "ihevce_sub_pic_rc.h"
104 #include "ihevce_global_tables.h"
105 #include "ihevce_bs_compute_ctb.h"
106 #include "ihevce_cabac_rdo.h"
107 #include "ihevce_deblk.h"
108 #include "ihevce_entropy_interface.h"
109 #include "ihevce_frame_process.h"
110 #include "ihevce_ipe_pass.h"
111 #include "ihevce_rc_enc_structs.h"
112 #include "ihevce_rc_interface.h"
113 #include "hme_datatype.h"
114 #include "hme_interface.h"
115 #include "hme_common_defs.h"
116 #include "hme_defs.h"
117 #include "ihevce_me_instr_set_router.h"
118 #include "ihevce_enc_subpel_gen.h"
119 #include "ihevce_inter_pred.h"
120 #include "ihevce_mv_pred.h"
121 #include "ihevce_mv_pred_merge.h"
122 #include "ihevce_enc_loop_inter_mode_sifter.h"
123 #include "ihevce_me_pass.h"
124 #include "ihevce_coarse_me_pass.h"
125 #include "ihevce_enc_cu_recursion.h"
126 #include "ihevce_enc_loop_pass.h"
127 #include "ihevce_common_utils.h"
128 #include "ihevce_buffer_que_interface.h"
129 #include "ihevce_dep_mngr_interface.h"
130 #include "ihevce_sao.h"
131 #include "ihevce_tile_interface.h"
132
133 #include "cast_types.h"
134 #include "osal.h"
135 #include "osal_defaults.h"
136
137 /*****************************************************************************/
138 /* Function Definitions */
139 /*****************************************************************************/
140
141 /*!
142 ******************************************************************************
143 * \if Function name : ihevce_mem_manager_init \endif
144 *
145 * \brief
146 * Encoder Memory init function
147 *
148 * \param[in] Processing interface context pointer
149 *
150 * \return
151 * None
152 *
153 * \author
154 * Ittiam
155 *
156 *****************************************************************************
157 */
158 #define MAX_QUEUE 40
ihevce_mem_manager_init(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_intrf_ctxt)159 void ihevce_mem_manager_init(enc_ctxt_t *ps_enc_ctxt, ihevce_hle_ctxt_t *ps_intrf_ctxt)
160 {
161 /* local variables */
162 WORD32 total_memtabs_req = 0;
163 WORD32 total_memtabs_used = 0;
164 WORD32 total_system_memtabs = 0;
165 WORD32 ctr;
166 WORD32 buf_size;
167 WORD32 num_ctb_horz;
168 WORD32 num_ctb_vert;
169 WORD32 num_cu_in_ctb;
170 WORD32 num_pu_in_ctb;
171 WORD32 num_tu_in_ctb;
172 WORD32 ctb_size;
173 WORD32 min_cu_size;
174 WORD32 max_num_ref_pics;
175 WORD32 mem_alloc_ctrl_flag;
176 WORD32 space_for_mem_in_enc_grp = 0;
177 WORD32 space_for_mem_in_pre_enc_grp = 0;
178 WORD32 mv_bank_size;
179 WORD32 ref_idx_bank_size;
180 WORD32 a_wd[MAX_NUM_HME_LAYERS], a_ht[MAX_NUM_HME_LAYERS];
181 WORD32 a_disp_wd[MAX_NUM_HME_LAYERS], a_disp_ht[MAX_NUM_HME_LAYERS];
182 WORD32 a_ctb_align_wd[MAX_NUM_HME_LAYERS], a_ctb_align_ht[MAX_NUM_HME_LAYERS];
183 WORD32 n_enc_layers = 1, n_tot_layers;
184 WORD32 num_bufs_preenc_me_que, num_bufs_L0_ipe_enc, max_delay_preenc_l0_que;
185 WORD32 i, i4_resolution_id = ps_enc_ctxt->i4_resolution_id; //counter
186 WORD32 i4_num_bitrate_inst;
187 iv_mem_rec_t *ps_memtab;
188 WORD32 i4_field_pic, i4_total_queues = 0;
189
190 recon_pic_buf_t **pps_pre_enc_pic_bufs;
191 frm_proc_ent_cod_ctxt_t **pps_frm_proc_ent_cod_bufs[IHEVCE_MAX_NUM_BITRATES];
192 pre_enc_me_ctxt_t **pps_pre_enc_bufs;
193 me_enc_rdopt_ctxt_t **pps_me_enc_bufs;
194 pre_enc_L0_ipe_encloop_ctxt_t **pps_L0_ipe_enc_bufs;
195 /*get number of input buffer required based on requirement from each stage*/
196 ihevce_lap_enc_buf_t **pps_lap_enc_input_bufs;
197 WORD32 i4_num_enc_loop_frm_pllel;
198 WORD32 i4_num_me_frm_pllel;
199 /*msr: These are parameters required to allocate input buffer,
200 encoder needs to be initilized before getting requirements hence filled once static params are initilized*/
201 WORD32 num_input_buf_per_queue, i4_yuv_min_size, i4_luma_min_size;
202
203 i4_num_bitrate_inst = ps_enc_ctxt->i4_num_bitrates;
204 i4_field_pic = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_field_pic;
205 ps_intrf_ctxt->i4_gpu_mem_size = 0;
206
207 /*Initialize the thrd id flag and all deafult values for sub pic rc */
208 {
209 WORD32 i, j, k;
210
211 for(i = 0; i < MAX_NUM_ENC_LOOP_PARALLEL; i++)
212 {
213 for(j = 0; j < IHEVCE_MAX_NUM_BITRATES; j++)
214 {
215 ps_enc_ctxt->s_multi_thrd.ai4_acc_ctb_ctr[i][j] = 0;
216 ps_enc_ctxt->s_multi_thrd.ai4_ctb_ctr[i][j] = 0;
217
218 ps_enc_ctxt->s_multi_thrd.ai4_threshold_reached[i][j] = 0;
219
220 ps_enc_ctxt->s_multi_thrd.ai4_curr_qp_acc[i][j] = 0;
221
222 ps_enc_ctxt->s_multi_thrd.af_acc_hdr_bits_scale_err[i][j] = 0;
223
224 for(k = 0; k < MAX_NUM_FRM_PROC_THRDS_ENC; k++)
225 {
226 ps_enc_ctxt->s_multi_thrd.ai4_thrd_id_valid_flag[i][j][k] = -1;
227 }
228 }
229 }
230 }
231
232 #define ENABLE_FRM_PARALLEL
233 #ifdef ENABLE_FRM_PARALLEL
234 i4_num_enc_loop_frm_pllel = MAX_NUM_ENC_LOOP_PARALLEL;
235 i4_num_me_frm_pllel = MAX_NUM_ME_PARALLEL;
236 #else
237 i4_num_enc_loop_frm_pllel = 1;
238 i4_num_me_frm_pllel = 1;
239 #endif
240
241 ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel = i4_num_enc_loop_frm_pllel;
242 ps_enc_ctxt->i4_max_fr_enc_loop_parallel_rc = i4_num_enc_loop_frm_pllel;
243 ps_enc_ctxt->s_multi_thrd.i4_num_me_frm_pllel = i4_num_me_frm_pllel;
244 ps_enc_ctxt->s_multi_thrd.i4_force_end_flag = 0;
245
246 ps_enc_ctxt->i4_ref_mbr_id = 0;
247 /* get the ctb size from max cu size */
248 ctb_size = ps_enc_ctxt->ps_stat_prms->s_config_prms.i4_max_log2_cu_size;
249
250 /* get the min cu size from config params */
251 min_cu_size = ps_enc_ctxt->ps_stat_prms->s_config_prms.i4_min_log2_cu_size;
252
253 /* convert to actual width */
254 ctb_size = 1 << ctb_size;
255 min_cu_size = 1 << min_cu_size;
256
257 /* Get the width and heights of different decomp layers */
258 *a_wd =
259 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
260 .i4_width +
261 SET_CTB_ALIGN(
262 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
263 .i4_width,
264 min_cu_size);
265 *a_ht =
266 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
267 .i4_height +
268 SET_CTB_ALIGN(
269 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
270 .i4_height,
271 min_cu_size);
272
273 n_tot_layers = hme_derive_num_layers(n_enc_layers, a_wd, a_ht, a_disp_wd, a_disp_ht);
274 hme_coarse_get_layer1_mv_bank_ref_idx_size(
275 n_tot_layers,
276 a_wd,
277 a_ht,
278 ((ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
279 ? ((DEFAULT_MAX_REFERENCE_PICS) << i4_field_pic)
280 : ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames),
281 (S32 *)(&mv_bank_size),
282 (S32 *)(&ref_idx_bank_size));
283 if(n_tot_layers < 3)
284 {
285 WORD32 error_code;
286 error_code = IHEVCE_NUM_DECOMP_LYRS_NOT_SUPPORTED;
287 ps_intrf_ctxt->i4_error_code = IHEVCE_SETUNSUPPORTEDINPUT(error_code);
288 return;
289 }
290
291 /* calculate num cu,pu,tu in ctb */
292 num_cu_in_ctb = ctb_size / MIN_CU_SIZE;
293 num_cu_in_ctb *= num_cu_in_ctb;
294
295 num_pu_in_ctb = ctb_size / MIN_PU_SIZE;
296 num_pu_in_ctb *= num_pu_in_ctb;
297
298 num_tu_in_ctb = ctb_size / MIN_PU_SIZE;
299 num_tu_in_ctb *= num_tu_in_ctb;
300
301 /* calcuate the number of ctb horizontally*/
302 num_ctb_horz =
303 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
304 .i4_width +
305 SET_CTB_ALIGN(
306 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
307 .i4_width,
308 ctb_size);
309 num_ctb_horz = num_ctb_horz / ctb_size;
310
311 /* calcuate the number of ctb vertically*/
312 num_ctb_vert =
313 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
314 .i4_height +
315 SET_CTB_ALIGN(
316 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
317 .i4_height,
318 ctb_size);
319 num_ctb_vert = num_ctb_vert / ctb_size;
320
321 /* align all the decomp layer dimensions to CTB alignment */
322 for(ctr = 0; ctr < n_tot_layers; ctr++)
323 {
324 a_ctb_align_wd[ctr] = a_wd[ctr] + SET_CTB_ALIGN(a_wd[ctr], ctb_size);
325
326 a_ctb_align_ht[ctr] = a_ht[ctr] + SET_CTB_ALIGN(a_ht[ctr], ctb_size);
327 }
328
329 /* SEI related parametert initialization */
330
331 ps_enc_ctxt->u4_cur_pic_encode_cnt = 0;
332
333 /* store the frame level ctb parameters which will be constant for the session */
334 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size = ctb_size;
335 ps_enc_ctxt->s_frm_ctb_prms.i4_min_cu_size = min_cu_size;
336 ps_enc_ctxt->s_frm_ctb_prms.i4_num_cus_in_ctb = num_cu_in_ctb;
337 ps_enc_ctxt->s_frm_ctb_prms.i4_num_pus_in_ctb = num_pu_in_ctb;
338 ps_enc_ctxt->s_frm_ctb_prms.i4_num_tus_in_ctb = num_tu_in_ctb;
339
340 /* intialize cra poc to default value */
341 ps_enc_ctxt->i4_cra_poc = 0;
342
343 /* initialise the memory alloc control flag */
344 mem_alloc_ctrl_flag = ps_enc_ctxt->ps_stat_prms->s_multi_thrd_prms.i4_memory_alloc_ctrl_flag;
345
346 /* decide the memory space for enc_grp and pre_enc_grp based on control flag */
347 if(0 == mem_alloc_ctrl_flag)
348 {
349 /* normal memory */
350 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NORMAL_MEM;
351 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NORMAL_MEM;
352 }
353 else if(1 == mem_alloc_ctrl_flag)
354 {
355 /* only NUMA Node 0 memory allocation */
356 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
357 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
358 }
359 else if(2 == mem_alloc_ctrl_flag)
360 {
361 /* Both NUMA Node 0 & Node 1 memory allocation */
362 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
363 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE1_MEM;
364 }
365 else
366 {
367 /* should not enter here */
368 ASSERT(0);
369 }
370
371 {
372 if(ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel > 1)
373 {
374 num_bufs_preenc_me_que = MIN_L1_L0_STAGGER_NON_SEQ +
375 ps_enc_ctxt->ps_stat_prms->s_lap_prms.i4_rc_look_ahead_pics +
376 (MAX_L0_IPE_ENC_STAGGER - 1) + NUM_BUFS_DECOMP_HME;
377 }
378 else
379 {
380 num_bufs_preenc_me_que = MIN_L1_L0_STAGGER_NON_SEQ +
381 ps_enc_ctxt->ps_stat_prms->s_lap_prms.i4_rc_look_ahead_pics +
382 (MIN_L0_IPE_ENC_STAGGER - 1) + NUM_BUFS_DECOMP_HME;
383 }
384
385 /*The number of buffers to support stagger between L0 IPE, ME and enc loop. This is a separate queue to store L0 IPE
386 output to save memory since this is not used in L1 stage*/
387 if(ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel > 1)
388 {
389 num_bufs_L0_ipe_enc = MAX_L0_IPE_ENC_STAGGER;
390 }
391 else
392 {
393 num_bufs_L0_ipe_enc = MIN_L0_IPE_ENC_STAGGER;
394 }
395
396 max_delay_preenc_l0_que = MIN_L1_L0_STAGGER_NON_SEQ +
397 ps_enc_ctxt->ps_stat_prms->s_lap_prms.i4_rc_look_ahead_pics + 1;
398 }
399
400 /* ------------ popluate the lap static parameters ------------- */
401 ps_enc_ctxt->s_lap_stat_prms.i4_max_closed_gop_period =
402 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_closed_gop_period;
403
404 ps_enc_ctxt->s_lap_stat_prms.i4_min_closed_gop_period =
405 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_min_closed_gop_period;
406
407 ps_enc_ctxt->s_lap_stat_prms.i4_max_cra_open_gop_period =
408 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_cra_open_gop_period;
409
410 ps_enc_ctxt->s_lap_stat_prms.i4_max_i_open_gop_period =
411 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_i_open_gop_period;
412
413 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
414 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames;
415
416 ps_enc_ctxt->s_lap_stat_prms.i4_max_temporal_layers =
417 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_temporal_layers;
418
419 ps_enc_ctxt->s_lap_stat_prms.i4_width = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_width;
420
421 ps_enc_ctxt->s_lap_stat_prms.i4_height = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_height;
422
423 ps_enc_ctxt->s_lap_stat_prms.i4_enable_logo = ps_enc_ctxt->ps_stat_prms->i4_enable_logo;
424
425 ps_enc_ctxt->s_lap_stat_prms.i4_src_interlace_field =
426 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_field_pic;
427 ps_enc_ctxt->s_lap_stat_prms.i4_frame_rate =
428 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_frm_rate_num /
429 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_frm_rate_denom;
430
431 ps_enc_ctxt->s_lap_stat_prms.i4_blu_ray_spec = ps_enc_ctxt->i4_blu_ray_spec;
432
433 ps_enc_ctxt->s_lap_stat_prms.i4_internal_bit_depth =
434 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth;
435
436 ps_enc_ctxt->s_lap_stat_prms.i4_input_bit_depth =
437 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_input_bit_depth;
438
439 ps_enc_ctxt->s_lap_stat_prms.u1_chroma_array_type =
440 (ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV) ? 2 : 1;
441
442 ps_enc_ctxt->s_lap_stat_prms.i4_rc_pass_num = ps_enc_ctxt->ps_stat_prms->s_pass_prms.i4_pass;
443
444 if(0 == i4_resolution_id)
445 {
446 for(ctr = 0; ctr < ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_num_res_layers; ctr++)
447 {
448 ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] =
449 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ctr].i4_quality_preset;
450
451 if(ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] == IHEVCE_QUALITY_P7)
452 {
453 ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] = IHEVCE_QUALITY_P6;
454 }
455 }
456 }
457 memcpy(
458 &ps_enc_ctxt->s_lap_stat_prms.s_lap_params,
459 &ps_enc_ctxt->ps_stat_prms->s_lap_prms,
460 sizeof(ihevce_lap_params_t));
461
462 /* copy the create prms as runtime prms */
463 memcpy(
464 &ps_enc_ctxt->s_runtime_src_prms,
465 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
466 sizeof(ihevce_src_params_t));
467 /*Copy the target params*/
468 memcpy(
469 &ps_enc_ctxt->s_runtime_tgt_params,
470 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
471 sizeof(ihevce_tgt_params_t));
472 ps_enc_ctxt->s_lap_stat_prms.e_arch_type = ps_enc_ctxt->ps_stat_prms->e_arch_type;
473 ps_enc_ctxt->s_lap_stat_prms.u1_is_popcnt_available = ps_enc_ctxt->u1_is_popcnt_available;
474
475 /* copy the create prms as runtime prms */
476 memcpy(
477 &ps_enc_ctxt->s_runtime_src_prms,
478 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
479 sizeof(ihevce_src_params_t));
480 /*Copy the target params*/
481 memcpy(
482 &ps_enc_ctxt->s_runtime_tgt_params,
483 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
484 sizeof(ihevce_tgt_params_t));
485
486 /* copy the run time coding parameters */
487 memcpy(
488 &ps_enc_ctxt->s_runtime_coding_prms,
489 &ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms,
490 sizeof(ihevce_coding_params_t));
491 /*change in run time parameter*/
492 if(ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
493 {
494 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames = (DEFAULT_MAX_REFERENCE_PICS)
495 << i4_field_pic;
496 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
497 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
498 }
499 ASSERT(i4_num_enc_loop_frm_pllel == i4_num_me_frm_pllel);
500
501 if((1 == i4_num_enc_loop_frm_pllel) && (1 == i4_num_me_frm_pllel))
502 {
503 max_num_ref_pics = ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
504 }
505 else
506 {
507 max_num_ref_pics =
508 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames * i4_num_enc_loop_frm_pllel;
509 }
510 /* --------------------------------------------------------------------- */
511 /* -------------- Collating the number of memtabs required ------------ */
512 /* --------------------------------------------------------------------- */
513
514 /* Memtabs for syntactical tiles */
515 total_memtabs_req += ihevce_tiles_get_num_mem_recs();
516
517 /* ---------- Enc loop Memtabs --------- */
518 total_memtabs_req +=
519 ihevce_enc_loop_get_num_mem_recs(i4_num_bitrate_inst, i4_num_enc_loop_frm_pllel);
520 /* ---------- ME Memtabs --------------- */
521 total_memtabs_req += ihevce_me_get_num_mem_recs(i4_num_me_frm_pllel);
522
523 /* ---------- Coarse ME Memtabs --------------- */
524 total_memtabs_req += ihevce_coarse_me_get_num_mem_recs();
525 /* ---------- IPE Memtabs -------------- */
526 total_memtabs_req += ihevce_ipe_get_num_mem_recs();
527
528 /* ---------- ECD Memtabs -------------- */
529 for(i = 0; i < i4_num_bitrate_inst; i++)
530 {
531 total_memtabs_req += ihevce_entropy_get_num_mem_recs();
532 }
533 if(0 == ps_enc_ctxt->i4_resolution_id)
534 {
535 /* ---------- LAP Memtabs--------------- */
536 total_memtabs_req += ihevce_lap_get_num_mem_recs();
537 }
538 /* ---------- Decomp Pre Intra Memtabs--------------- */
539 total_memtabs_req += ihevce_decomp_pre_intra_get_num_mem_recs();
540
541 /* ---------- RC memtabs --------------- */
542 for(i = 0; i < i4_num_bitrate_inst; i++)
543 {
544 total_memtabs_req += ihevce_rc_get_num_mem_recs(); /*HEVC_RC*/
545 }
546
547 /* ---------- System Memtabs ----------- */
548 total_memtabs_req += TOTAL_SYSTEM_MEM_RECS; //increment this based on final requirement
549
550 /* -----Frameproc Entcod Que Memtabs --- */
551 /* one queue for each bit-rate is used */
552 for(i = 0; i < i4_num_bitrate_inst; i++)
553 {
554 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
555 }
556 /* mrs:memtab for one queue for encoder owned input queue, This is only request for memtab, currently more than
557 required memtabs are allocated. Hence my change of using memtab for yuv buffers is surviving. Only memtab
558 usage and initialization needs to be exact sync*/
559 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
560
561 /* ---Pre-encode Encode Que Mem requests -- */
562 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
563
564 /* -----ME / Enc-RD opt Que Mem requests --- */
565 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
566
567 /* ----Pre-encode L0 IPE to enc Que Mem requests -- */
568 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
569
570 /* --- ME-EncLoop Dep Mngr Row-Row Mem requests -- */
571 total_memtabs_req += NUM_ME_ENC_BUFS * ihevce_dmgr_get_num_mem_recs();
572
573 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem requests -- */
574 total_memtabs_req += i4_num_enc_loop_frm_pllel * ihevce_dmgr_get_num_mem_recs();
575
576 /* --- Prev. frame EncLoop Done for re-encode Dep Mngr Frm-Frm Mem requests -- */
577 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
578
579 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem requests -- */
580 total_memtabs_req += i4_num_me_frm_pllel * ihevce_dmgr_get_num_mem_recs();
581
582 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem requests -- */
583 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
584
585 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem requests -- */
586 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
587
588 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem requests -- */
589 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
590
591 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem requests -- */
592 total_memtabs_req +=
593 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * ihevce_dmgr_get_num_mem_recs();
594
595 /* ----- allocate memomry for memtabs --- */
596 {
597 iv_mem_rec_t s_memtab;
598
599 s_memtab.i4_size = sizeof(iv_mem_rec_t);
600 s_memtab.i4_mem_size = total_memtabs_req * sizeof(iv_mem_rec_t);
601 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
602 s_memtab.i4_mem_alignment = 4;
603
604 ps_intrf_ctxt->ihevce_mem_alloc(
605 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->ps_stat_prms->s_sys_api, &s_memtab);
606 if(s_memtab.pv_base == NULL)
607 {
608 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
609 return;
610 }
611
612 ps_memtab = (iv_mem_rec_t *)s_memtab.pv_base;
613 }
614
615 /* --------------------------------------------------------------------- */
616 /* ------------------ Collating memory requirements ------------------- */
617 /* --------------------------------------------------------------------- */
618
619 /* ----------- Tiles mem requests -------------*/
620 total_memtabs_used += ihevce_tiles_get_mem_recs(
621 &ps_memtab[total_memtabs_used],
622 ps_enc_ctxt->ps_stat_prms,
623 &ps_enc_ctxt->s_frm_ctb_prms,
624 i4_resolution_id,
625 space_for_mem_in_enc_grp);
626
627 /* ---------- Enc loop Mem requests --------- */
628 total_memtabs_used += ihevce_enc_loop_get_mem_recs(
629 &ps_memtab[total_memtabs_used],
630 ps_enc_ctxt->ps_stat_prms,
631 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
632 i4_num_bitrate_inst,
633 i4_num_enc_loop_frm_pllel,
634 space_for_mem_in_enc_grp,
635 i4_resolution_id);
636 /* ---------- ME Mem requests --------------- */
637 total_memtabs_used += ihevce_me_get_mem_recs(
638 &ps_memtab[total_memtabs_used],
639 ps_enc_ctxt->ps_stat_prms,
640 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
641 space_for_mem_in_enc_grp,
642 i4_resolution_id,
643 i4_num_me_frm_pllel);
644
645 /* ---------- Coarse ME Mem requests --------------- */
646 total_memtabs_used += ihevce_coarse_me_get_mem_recs(
647 &ps_memtab[total_memtabs_used],
648 ps_enc_ctxt->ps_stat_prms,
649 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
650 space_for_mem_in_pre_enc_grp,
651 i4_resolution_id);
652 /* ---------- IPE Mem requests -------------- */
653 total_memtabs_used += ihevce_ipe_get_mem_recs(
654 &ps_memtab[total_memtabs_used],
655 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
656 space_for_mem_in_pre_enc_grp);
657 /* ---------- ECD Mem requests -------------- */
658 i4_num_bitrate_inst = ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id]
659 .i4_num_bitrate_instances;
660 for(i = 0; i < i4_num_bitrate_inst; i++)
661 {
662 total_memtabs_used += ihevce_entropy_get_mem_recs(
663 &ps_memtab[total_memtabs_used],
664 ps_enc_ctxt->ps_stat_prms,
665 space_for_mem_in_pre_enc_grp,
666 i4_resolution_id);
667 }
668
669 if(0 == i4_resolution_id)
670 {
671 /* ---------- LAP Mem requests--------------- */
672 total_memtabs_used +=
673 ihevce_lap_get_mem_recs(&ps_memtab[total_memtabs_used], space_for_mem_in_pre_enc_grp);
674 }
675
676 /* -------- DECOMPOSITION PRE INTRA Mem requests-------- */
677 total_memtabs_used += ihevce_decomp_pre_intra_get_mem_recs(
678 &ps_memtab[total_memtabs_used],
679 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
680 space_for_mem_in_pre_enc_grp);
681
682 /* ---------- RC Mem requests --------------- */
683 for(i = 0; i < i4_num_bitrate_inst; i++)
684 {
685 total_memtabs_used += ihevce_rc_get_mem_recs(
686 &ps_memtab[total_memtabs_used],
687 ps_enc_ctxt->ps_stat_prms,
688 space_for_mem_in_pre_enc_grp,
689 &ps_enc_ctxt->ps_stat_prms->s_sys_api);
690 }
691
692 /* ---------- System Mem requests ----------- */
693
694 /* allocate memory for pps tile */
695 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
696
697 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
698
699 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
700 {
701 ps_memtab[total_memtabs_used].i4_mem_size =
702 (ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols *
703 ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_rows) *
704 (sizeof(tile_t));
705 }
706 else
707 {
708 ps_memtab[total_memtabs_used].i4_mem_size = sizeof(tile_t);
709 }
710
711 /* increment the memtab counter */
712 total_memtabs_used++;
713 total_system_memtabs++;
714
715 /* recon picture buffer pointer array */
716 for(i = 0; i < i4_num_bitrate_inst; i++)
717 {
718 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
719
720 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
721
722 ps_memtab[total_memtabs_used].i4_mem_size =
723 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * (sizeof(recon_pic_buf_t *));
724
725 /* increment the memtab counter */
726 total_memtabs_used++;
727 total_system_memtabs++;
728 }
729
730 /* recon picture buffers structures */
731 for(i = 0; i < i4_num_bitrate_inst; i++)
732 {
733 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
734
735 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
736
737 ps_memtab[total_memtabs_used].i4_mem_size =
738 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * (sizeof(recon_pic_buf_t));
739
740 /* increment the memtab counter */
741 total_memtabs_used++;
742 total_system_memtabs++;
743 }
744
745 /* reference/recon picture buffers */
746 for(i = 0; i < i4_num_bitrate_inst; i++)
747 {
748 WORD32 i4_chroma_buf_size_shift =
749 -(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth <= 8) +
750 (ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV);
751
752 buf_size = ((num_ctb_horz * ctb_size) + (PAD_HORZ << 1));
753 buf_size = buf_size * ((num_ctb_vert * ctb_size) + (PAD_VERT << 1));
754 buf_size = buf_size * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS);
755
756 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
757
758 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
759
760 /* If HBD, both 8bit and 16 bit luma buffers are required, whereas only 16bit chroma buffers are required */
761 ps_memtab[total_memtabs_used].i4_mem_size =
762 /* Luma */
763 (buf_size * ((ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth > 8)
764 ? BUFFER_SIZE_MULTIPLIER_IF_HBD
765 : 1)) +
766 /* Chroma */
767 (SHL_NEG(buf_size, i4_chroma_buf_size_shift));
768
769 /* increment the memtab counter */
770 total_memtabs_used++;
771 total_system_memtabs++;
772 }
773 /* reference/recon picture subpel planes */
774 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
775
776 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
777
778 ps_memtab[total_memtabs_used].i4_mem_size =
779 buf_size * (3 + L0ME_IN_OPENLOOP_MODE); /* 3 planes */
780
781 /* increment the memtab counter */
782 total_memtabs_used++;
783 total_system_memtabs++;
784 /* reference colocated MV bank */
785 /* Keep memory for an extra CTB at the right and bottom of frame.
786 This extra space is needed by dist-encoding and unused in non-dist-encoding */
787 buf_size = (num_ctb_horz + 1) * (num_ctb_vert + 1) * num_pu_in_ctb;
788 buf_size = buf_size * sizeof(pu_col_mv_t) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
789 i4_num_bitrate_inst;
790
791 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
792
793 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
794
795 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
796
797 /* increment the memtab counter */
798 total_memtabs_used++;
799 total_system_memtabs++;
800
801 /* reference colocated MV bank map */
802 /* Keep memory for an extra CTB at the right and bottom of frame.
803 This extra space is needed by dist-encoding and unused in non-dist-encoding */
804 buf_size = (num_ctb_horz + 1) * (num_ctb_vert + 1) * num_pu_in_ctb;
805 buf_size = buf_size * sizeof(UWORD8) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
806 i4_num_bitrate_inst;
807
808 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
809
810 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
811
812 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
813
814 /* increment the memtab counter */
815 total_memtabs_used++;
816 total_system_memtabs++;
817
818 /* reference collocated MV bank map offsets map */
819 buf_size = num_ctb_horz * num_ctb_vert;
820 buf_size = buf_size * sizeof(UWORD16) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
821 i4_num_bitrate_inst;
822
823 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
824
825 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
826
827 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
828
829 /* increment the memtab counter */
830 total_memtabs_used++;
831 total_system_memtabs++;
832
833 /* reference colocated MV bank ctb offset */
834 buf_size = num_ctb_horz;
835 buf_size = buf_size * num_ctb_vert;
836 buf_size = buf_size * sizeof(UWORD32) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
837 i4_num_bitrate_inst;
838
839 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
840
841 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
842
843 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
844
845 /* increment the memtab counter */
846 total_memtabs_used++;
847 total_system_memtabs++;
848
849 /* recon picture buffer pointer array for pre enc group */
850 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
851
852 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
853
854 ps_memtab[total_memtabs_used].i4_mem_size =
855 (max_num_ref_pics + 1) * (sizeof(recon_pic_buf_t *));
856
857 /* increment the memtab counter */
858 total_memtabs_used++;
859 total_system_memtabs++;
860
861 /* recon picture buffers structures for pre enc group */
862 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
863
864 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
865
866 ps_memtab[total_memtabs_used].i4_mem_size = (max_num_ref_pics + 1) * (sizeof(recon_pic_buf_t));
867
868 /* increment the memtab counter */
869 total_memtabs_used++;
870 total_system_memtabs++;
871 {
872 num_input_buf_per_queue = ihevce_lap_get_num_ip_bufs(&ps_enc_ctxt->s_lap_stat_prms);
873 {
874 WORD32 i4_count_temp = 0, i4_last_queue_length;
875
876 /*First allocate the memory for the buffer based on resolution*/
877 WORD32 ctb_align_pic_wd = ps_enc_ctxt->s_runtime_tgt_params.i4_width +
878 SET_CTB_ALIGN(
879 ps_enc_ctxt->s_runtime_tgt_params.i4_width,
880 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size);
881
882 WORD32 ctb_align_pic_ht = ps_enc_ctxt->s_runtime_tgt_params.i4_height +
883 SET_CTB_ALIGN(
884 ps_enc_ctxt->s_runtime_tgt_params.i4_height,
885 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size);
886
887 i4_last_queue_length = (num_input_buf_per_queue % MAX_QUEUE);
888
889 if((num_input_buf_per_queue % MAX_QUEUE) == 0)
890 i4_last_queue_length = MAX_QUEUE;
891
892 ps_enc_ctxt->i4_num_input_buf_per_queue = num_input_buf_per_queue;
893 i4_yuv_min_size =
894 (ctb_align_pic_wd * ctb_align_pic_ht) +
895 ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
896 ? (ctb_align_pic_wd * ctb_align_pic_ht)
897 : ((ctb_align_pic_wd * ctb_align_pic_ht) >> 1));
898 i4_luma_min_size = (ctb_align_pic_wd * ctb_align_pic_ht);
899
900 /*Inorder to allocate memory for the large buffer sizes overflowing WORD32 we are splitting the memtabs using i4_total_hbd_queues and MAX_HBD_QUEUE*/
901 i4_total_queues = num_input_buf_per_queue / MAX_QUEUE;
902
903 if((num_input_buf_per_queue % MAX_QUEUE) != 0)
904 {
905 i4_total_queues++;
906 }
907
908 ASSERT(i4_total_queues < 5);
909
910 for(i4_count_temp = 0; i4_count_temp < i4_total_queues; i4_count_temp++)
911 {
912 ps_memtab[total_memtabs_used].i4_mem_alignment = 32;
913
914 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
915 /*Memory size for yuv buffer of one frame * num of input required to stored in the queue*/
916 if((i4_count_temp < (i4_total_queues - 1)))
917 ps_memtab[total_memtabs_used].i4_mem_size = i4_yuv_min_size * MAX_QUEUE;
918 else
919 ps_memtab[total_memtabs_used].i4_mem_size =
920 (i4_yuv_min_size)*i4_last_queue_length;
921
922 /* increment the memtab counter */
923 total_memtabs_used++;
924 total_system_memtabs++;
925 }
926 }
927 /*memory for input buffer structure*/
928 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
929
930 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
931
932 ps_memtab[total_memtabs_used].i4_mem_size =
933 (num_input_buf_per_queue) * (sizeof(ihevce_lap_enc_buf_t *));
934
935 /* increment the memtab counter */
936 total_memtabs_used++;
937 total_system_memtabs++;
938
939 /* frame process/entropy coding buffer structures */
940 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
941
942 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
943
944 ps_memtab[total_memtabs_used].i4_mem_size =
945 (num_input_buf_per_queue) * (sizeof(ihevce_lap_enc_buf_t));
946 /* increment the memtab counter */
947 total_memtabs_used++;
948 total_system_memtabs++;
949
950 /*input synch ctrl command*/
951 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
952
953 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
954
955 ps_memtab[total_memtabs_used].i4_mem_size =
956 (num_input_buf_per_queue) * (ENC_COMMAND_BUFF_SIZE);
957
958 total_memtabs_used++;
959 total_system_memtabs++;
960 }
961
962 /* Pre-encode/encode coding buffer pointer array */
963 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
964
965 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
966
967 ps_memtab[total_memtabs_used].i4_mem_size =
968 (num_bufs_preenc_me_que) * (sizeof(pre_enc_me_ctxt_t *));
969
970 /* increment the memtab counter */
971 total_memtabs_used++;
972 total_system_memtabs++;
973
974 /* frame process/entropy coding buffer structures */
975 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
976
977 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
978
979 ps_memtab[total_memtabs_used].i4_mem_size =
980 (num_bufs_preenc_me_que) * (sizeof(pre_enc_me_ctxt_t));
981
982 /* increment the memtab counter */
983 total_memtabs_used++;
984 total_system_memtabs++;
985
986 /* Pre-encode L0 IPE output to ME buffer pointer*/
987 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
988
989 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
990
991 ps_memtab[total_memtabs_used].i4_mem_size =
992 (num_bufs_L0_ipe_enc) * (sizeof(pre_enc_L0_ipe_encloop_ctxt_t *));
993
994 /* increment the memtab counter */
995 total_memtabs_used++;
996 total_system_memtabs++;
997
998 /* Pre-encode L0 IPE output to ME buffer */
999 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1000
1001 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1002
1003 ps_memtab[total_memtabs_used].i4_mem_size =
1004 (num_bufs_L0_ipe_enc) * (sizeof(pre_enc_L0_ipe_encloop_ctxt_t));
1005
1006 /* increment the memtab counter */
1007 total_memtabs_used++;
1008 total_system_memtabs++;
1009
1010 /* CTB analyse Frame level */
1011 buf_size = num_ctb_horz;
1012 buf_size = buf_size * num_ctb_vert;
1013 buf_size = buf_size * sizeof(ctb_analyse_t) * num_bufs_preenc_me_que;
1014
1015 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1016
1017 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1018
1019 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1020
1021 /* increment the memtab counter */
1022 total_memtabs_used++;
1023 total_system_memtabs++;
1024
1025 /* ME layer ctxt pointer */
1026 buf_size = sizeof(layer_ctxt_t) * num_bufs_preenc_me_que;
1027
1028 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1029
1030 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1031
1032 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1033
1034 /* increment the memtab counter */
1035 total_memtabs_used++;
1036 total_system_memtabs++;
1037
1038 /* ME layer MV bank ctxt pointer */
1039 buf_size = sizeof(layer_mv_t) * num_bufs_preenc_me_que;
1040
1041 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1042
1043 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1044
1045 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1046
1047 /* increment the memtab counter */
1048 total_memtabs_used++;
1049 total_system_memtabs++;
1050
1051 /* ME layer MV bank pointer */
1052 buf_size = mv_bank_size * num_bufs_preenc_me_que;
1053
1054 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1055
1056 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1057
1058 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1059
1060 /* increment the memtab counter */
1061 total_memtabs_used++;
1062 total_system_memtabs++;
1063
1064 /* ME layer ref idx bank pointer */
1065 buf_size = ref_idx_bank_size * num_bufs_preenc_me_que;
1066
1067 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1068
1069 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1070
1071 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1072
1073 /* increment the memtab counter */
1074 total_memtabs_used++;
1075 total_system_memtabs++;
1076 /* Frame level array to store 8x8 intra cost */
1077 buf_size = (num_ctb_horz * ctb_size) >> 3;
1078 buf_size *= ((num_ctb_vert * ctb_size) >> 3);
1079 buf_size *= sizeof(double) * num_bufs_preenc_me_que;
1080
1081 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1082
1083 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1084
1085 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1086
1087 /* increment the memtab counter */
1088 total_memtabs_used++;
1089 total_system_memtabs++;
1090
1091 /* Frame level array to store ctb intra cost and modes */
1092 buf_size = (num_ctb_horz * num_ctb_vert);
1093 buf_size *= sizeof(ipe_l0_ctb_analyse_for_me_t) * num_bufs_L0_ipe_enc;
1094
1095 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1096
1097 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1098
1099 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1100
1101 /* increment the memtab counter */
1102 total_memtabs_used++;
1103 total_system_memtabs++;
1104
1105 /*
1106 * Layer early decision buffer L1 buf.Since the pre intra analysis always
1107 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1108 * height in layer to mutiple of 32.
1109 */
1110 buf_size = (a_ctb_align_wd[1] >> 5) * (a_ctb_align_ht[1] >> 5) * sizeof(ihevce_ed_ctb_l1_t) *
1111 num_bufs_preenc_me_que;
1112
1113 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1114
1115 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1116
1117 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1118
1119 /* increment the memtab counter */
1120 total_memtabs_used++;
1121 total_system_memtabs++;
1122
1123 /*
1124 * Layer early decision buffer L1 buf.Since the pre intra analysis always
1125 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1126 * height in layer to mutiple of 32.
1127 */
1128 buf_size = (a_ctb_align_wd[1] >> 2) * (a_ctb_align_ht[1] >> 2) * sizeof(ihevce_ed_blk_t) *
1129 num_bufs_preenc_me_que;
1130
1131 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1132
1133 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1134
1135 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1136
1137 /* increment the memtab counter */
1138 total_memtabs_used++;
1139 total_system_memtabs++;
1140
1141 /*
1142 * Layer early decision buffer L2 buf.Since the pre intra analysis always
1143 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1144 * height in layer to mutiple of 16.
1145 */
1146 buf_size = (a_ctb_align_wd[2] >> 2) * (a_ctb_align_ht[2] >> 2) * sizeof(ihevce_ed_blk_t) *
1147 num_bufs_preenc_me_que;
1148
1149 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1150
1151 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1152
1153 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1154
1155 /* increment the memtab counter */
1156 total_memtabs_used++;
1157 total_system_memtabs++;
1158
1159 /* following is the buffer requirement of
1160 que between me and enc*/
1161
1162 /* me/enc que buffer pointer array */
1163 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1164
1165 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1166
1167 ps_memtab[total_memtabs_used].i4_mem_size = (NUM_ME_ENC_BUFS) * (sizeof(me_enc_rdopt_ctxt_t *));
1168
1169 /* increment the memtab counter */
1170 total_memtabs_used++;
1171 total_system_memtabs++;
1172
1173 /* fme/enc que buffer structures */
1174 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1175
1176 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1177
1178 ps_memtab[total_memtabs_used].i4_mem_size = (NUM_ME_ENC_BUFS) * (sizeof(me_enc_rdopt_ctxt_t));
1179
1180 /* increment the memtab counter */
1181 total_memtabs_used++;
1182 total_system_memtabs++;
1183
1184 /* Job Queue related memory */
1185 /* max num ctb rows is doubled to take care worst case */
1186 /* requirements because of HME layers */
1187 buf_size = (MAX_NUM_VERT_UNITS_FRM) * (NUM_ENC_JOBS_QUES)*NUM_ME_ENC_BUFS; //PING_PONG_BUF;
1188 /* In tile case, based on the number of column tiles,
1189 we will have separate jobQ per column tile */
1190 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
1191 {
1192 buf_size *= ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols;
1193 }
1194 buf_size *= sizeof(job_queue_t);
1195 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1196
1197 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1198
1199 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1200
1201 /* increment the memtab counter */
1202 total_memtabs_used++;
1203 total_system_memtabs++;
1204
1205 /* cur_ctb_cu_tree_t Frame level */
1206 buf_size = num_ctb_horz * MAX_NUM_NODES_CU_TREE;
1207 buf_size = buf_size * num_ctb_vert;
1208
1209 /* ps_cu_analyse_inter buffer is used to popualte outputs form ME after using cu analyse form IPE */
1210 buf_size = buf_size * sizeof(cur_ctb_cu_tree_t) * NUM_ME_ENC_BUFS;
1211
1212 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1213
1214 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1215
1216 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1217
1218 /* increment the memtab counter */
1219 total_memtabs_used++;
1220 total_system_memtabs++;
1221
1222 /* me_ctb_data_t Frame level */
1223 buf_size = num_ctb_horz * num_ctb_vert;
1224
1225 /* This buffer is used to */
1226 buf_size = buf_size * sizeof(me_ctb_data_t) * NUM_ME_ENC_BUFS;
1227
1228 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1229
1230 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1231
1232 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1233
1234 /* increment the memtab counter */
1235 total_memtabs_used++;
1236 total_system_memtabs++;
1237
1238 /* following is for each bit-rate */
1239 for(i = 0; i < i4_num_bitrate_inst; i++)
1240 {
1241 /* frame process/entropy coding buffer pointer array */
1242 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1243
1244 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1245
1246 ps_memtab[total_memtabs_used].i4_mem_size =
1247 (NUM_FRMPROC_ENTCOD_BUFS) * (sizeof(frm_proc_ent_cod_ctxt_t *));
1248
1249 /* increment the memtab counter */
1250 total_memtabs_used++;
1251 total_system_memtabs++;
1252
1253 /* frame process/entropy coding buffer structures */
1254 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1255
1256 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1257
1258 ps_memtab[total_memtabs_used].i4_mem_size =
1259 (NUM_FRMPROC_ENTCOD_BUFS) * (sizeof(frm_proc_ent_cod_ctxt_t));
1260
1261 /* increment the memtab counter */
1262 total_memtabs_used++;
1263 total_system_memtabs++;
1264
1265 /* CTB enc loop Frame level */
1266 buf_size = num_ctb_horz;
1267 buf_size = buf_size * num_ctb_vert;
1268 buf_size = buf_size * sizeof(ctb_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1269
1270 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1271
1272 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1273
1274 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1275
1276 /* increment the memtab counter */
1277 total_memtabs_used++;
1278 total_system_memtabs++;
1279
1280 /* CU enc loop Frame level */
1281 buf_size = num_ctb_horz * num_cu_in_ctb;
1282 buf_size = buf_size * num_ctb_vert;
1283 buf_size = buf_size * sizeof(cu_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1284
1285 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1286
1287 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1288
1289 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1290
1291 /* increment the memtab counter */
1292 total_memtabs_used++;
1293 total_system_memtabs++;
1294
1295 /* TU enc loop Frame level */
1296 buf_size = num_ctb_horz * num_tu_in_ctb;
1297 buf_size = buf_size * num_ctb_vert;
1298 buf_size = buf_size * sizeof(tu_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1299
1300 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1301
1302 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1303
1304 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1305
1306 /* increment the memtab counter */
1307 total_memtabs_used++;
1308 total_system_memtabs++;
1309
1310 /* PU enc loop Frame level */
1311 buf_size = num_ctb_horz * num_pu_in_ctb;
1312 buf_size = buf_size * num_ctb_vert;
1313 buf_size = buf_size * sizeof(pu_t) * NUM_FRMPROC_ENTCOD_BUFS;
1314
1315 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1316
1317 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1318
1319 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1320
1321 /* increment the memtab counter */
1322 total_memtabs_used++;
1323 total_system_memtabs++;
1324
1325 /* Coeffs Frame level */
1326 buf_size =
1327 num_ctb_horz * ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1328 ? (num_tu_in_ctb << 1)
1329 : ((num_tu_in_ctb * 3) >> 1));
1330 buf_size = buf_size * num_ctb_vert;
1331 buf_size = buf_size * sizeof(UWORD8) * MAX_SCAN_COEFFS_BYTES_4x4 * NUM_FRMPROC_ENTCOD_BUFS;
1332
1333 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1334
1335 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1336
1337 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1338
1339 /* increment the memtab counter */
1340 total_memtabs_used++;
1341 total_system_memtabs++;
1342
1343 /* SEI Payload Data */
1344 buf_size = sizeof(UWORD8) * MAX_NUMBER_OF_SEI_PAYLOAD * MAX_SEI_PAYLOAD_PER_TLV *
1345 NUM_FRMPROC_ENTCOD_BUFS;
1346
1347 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1348 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1349
1350 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1351
1352 /* increment the memtab counter */
1353 total_memtabs_used++;
1354 total_system_memtabs++;
1355 }
1356
1357 /* ------ Working mem frame level -------*/
1358 buf_size = ((num_ctb_horz * ctb_size) + 16);
1359 buf_size *= ((num_ctb_vert * ctb_size) + 23);
1360 buf_size *= sizeof(WORD16);
1361 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1362
1363 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1364
1365 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1366
1367 /* increment the memtab counter */
1368 total_memtabs_used++;
1369 total_system_memtabs++;
1370 /* Job Queue related memory */
1371 /* max num ctb rows is doubled to take care worst case */
1372 /* requirements because of HME layers */
1373 buf_size = (MAX_NUM_VERT_UNITS_FRM) * (NUM_PRE_ENC_JOBS_QUES) * (max_delay_preenc_l0_que);
1374 buf_size *= sizeof(job_queue_t);
1375
1376 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1377
1378 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1379
1380 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1381
1382 /* increment the memtab counter */
1383 total_memtabs_used++;
1384 total_system_memtabs++;
1385
1386 /* check on the system memtabs */
1387 ASSERT(total_system_memtabs <= TOTAL_SYSTEM_MEM_RECS);
1388
1389 /* -----Frameproc Entcod Que Mem requests --- */
1390 /* derive for each bit-rate */
1391 for(i = 0; i < i4_num_bitrate_inst; i++)
1392 {
1393 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1394 &ps_memtab[total_memtabs_used], NUM_FRMPROC_ENTCOD_BUFS, space_for_mem_in_enc_grp);
1395 }
1396 /*mrs: Request memory for the input yuv queue*/
1397 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1398 &ps_memtab[total_memtabs_used], num_input_buf_per_queue, space_for_mem_in_enc_grp);
1399 /*------ The encoder owned input buffer queue*/
1400 /* -----Pre-encode Encode Que Mem requests --- */
1401 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1402 &ps_memtab[total_memtabs_used], num_bufs_preenc_me_que, space_for_mem_in_enc_grp);
1403
1404 /* -----ME / Enc-RD opt Que Mem requests --- */
1405 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1406 &ps_memtab[total_memtabs_used], NUM_ME_ENC_BUFS, space_for_mem_in_enc_grp);
1407
1408 /* -----Pre-encode L0 IPE to enc Que Mem requests --- */
1409 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1410 &ps_memtab[total_memtabs_used], num_bufs_L0_ipe_enc, space_for_mem_in_enc_grp);
1411
1412 /* ---------- Dependency Manager allocations -------- */
1413 {
1414 /* --- ME-EncLoop Dep Mngr Row-Row Mem requests -- */
1415 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
1416 {
1417 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1418 &ps_memtab[total_memtabs_used],
1419 DEP_MNGR_ROW_ROW_SYNC,
1420 (a_ctb_align_ht[0] / ctb_size),
1421 ps_enc_ctxt->ps_stat_prms->s_app_tile_params
1422 .i4_num_tile_cols, /* Number of Col Tiles */
1423 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1424 space_for_mem_in_enc_grp);
1425 }
1426
1427 for(ctr = 0; ctr < i4_num_enc_loop_frm_pllel; ctr++)
1428 {
1429 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem requests -- */
1430 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1431 &ps_memtab[total_memtabs_used],
1432 DEP_MNGR_FRM_FRM_SYNC,
1433 (a_ctb_align_ht[0] / ctb_size),
1434 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1435 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1436 space_for_mem_in_enc_grp);
1437 }
1438 /* --- Prev. frame EncLoop Done for re-encode Dep Mngr Frm-Frm Mem requests -- */
1439 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1440 &ps_memtab[total_memtabs_used],
1441 DEP_MNGR_FRM_FRM_SYNC,
1442 (a_ctb_align_ht[0] / ctb_size),
1443 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1444 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1445 space_for_mem_in_enc_grp);
1446 for(ctr = 0; ctr < i4_num_me_frm_pllel; ctr++)
1447 {
1448 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem requests -- */
1449 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1450 &ps_memtab[total_memtabs_used],
1451 DEP_MNGR_FRM_FRM_SYNC,
1452 (a_ctb_align_ht[0] / ctb_size),
1453 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1454 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1455 space_for_mem_in_enc_grp);
1456 }
1457
1458 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem requests -- */
1459 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1460 &ps_memtab[total_memtabs_used],
1461 DEP_MNGR_FRM_FRM_SYNC,
1462 (a_ctb_align_ht[0] / ctb_size),
1463 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1464 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1465 space_for_mem_in_enc_grp);
1466
1467 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem requests -- */
1468 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1469 &ps_memtab[total_memtabs_used],
1470 DEP_MNGR_FRM_FRM_SYNC,
1471 (a_ctb_align_ht[0] / ctb_size),
1472 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1473 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1474 space_for_mem_in_enc_grp);
1475
1476 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem requests -- */
1477 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1478 &ps_memtab[total_memtabs_used],
1479 DEP_MNGR_FRM_FRM_SYNC,
1480 (a_ctb_align_ht[0] / ctb_size),
1481 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1482 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1483 space_for_mem_in_enc_grp);
1484
1485 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem requests -- */
1486 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
1487 {
1488 WORD32 i4_num_units = num_ctb_horz * num_ctb_vert;
1489
1490 total_memtabs_used += ihevce_dmgr_map_get_mem_recs(
1491 &ps_memtab[total_memtabs_used],
1492 i4_num_units,
1493 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1494 space_for_mem_in_enc_grp);
1495 }
1496 }
1497
1498 /* ----- allocate memory as per requests ---- */
1499
1500 /* check on memtabs requested v/s memtabs used */
1501 //ittiam : should put an assert
1502
1503 //ASSERT(total_memtabs_used == total_memtabs_req);
1504
1505 for(ctr = 0; ctr < total_memtabs_used; ctr++)
1506 {
1507 UWORD8 *pu1_mem = NULL;
1508 ps_intrf_ctxt->ihevce_mem_alloc(
1509 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->ps_stat_prms->s_sys_api, &ps_memtab[ctr]);
1510
1511 pu1_mem = (UWORD8 *)ps_memtab[ctr].pv_base;
1512
1513 if(NULL == pu1_mem)
1514 {
1515 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
1516 return;
1517 }
1518
1519 memset(pu1_mem, 0, ps_memtab[ctr].i4_mem_size);
1520 }
1521
1522 /* --------------------------------------------------------------------- */
1523 /* --------- Initialisation of Modules & System memory ----------------- */
1524 /* --------------------------------------------------------------------- */
1525
1526 /* store the final allocated memtabs */
1527 ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs = total_memtabs_used;
1528 ps_enc_ctxt->s_mem_mngr.ps_create_memtab = ps_memtab;
1529
1530 /* ---------- Tiles Mem init --------- */
1531 ps_enc_ctxt->ps_tile_params_base = (ihevce_tile_params_t *)ihevce_tiles_mem_init(
1532 ps_memtab, ps_enc_ctxt->ps_stat_prms, ps_enc_ctxt, i4_resolution_id);
1533
1534 ps_memtab += ihevce_tiles_get_num_mem_recs();
1535
1536 /* ---------- Enc loop Mem init --------- */
1537 ps_enc_ctxt->s_module_ctxt.pv_enc_loop_ctxt = ihevce_enc_loop_init(
1538 ps_memtab,
1539 ps_enc_ctxt->ps_stat_prms,
1540 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1541 ps_intrf_ctxt->pv_osal_handle,
1542 &ps_enc_ctxt->s_func_selector,
1543 &ps_enc_ctxt->s_rc_quant,
1544 ps_enc_ctxt->ps_tile_params_base,
1545 i4_resolution_id,
1546 i4_num_enc_loop_frm_pllel,
1547 ps_enc_ctxt->u1_is_popcnt_available);
1548
1549 ps_memtab += ihevce_enc_loop_get_num_mem_recs(i4_num_bitrate_inst, i4_num_enc_loop_frm_pllel);
1550 /* ---------- ME Mem init --------------- */
1551 ps_enc_ctxt->s_module_ctxt.pv_me_ctxt = ihevce_me_init(
1552 ps_memtab,
1553 ps_enc_ctxt->ps_stat_prms,
1554 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1555 ps_intrf_ctxt->pv_osal_handle,
1556 &ps_enc_ctxt->s_rc_quant,
1557 (void *)ps_enc_ctxt->ps_tile_params_base,
1558 i4_resolution_id,
1559 i4_num_me_frm_pllel,
1560 ps_enc_ctxt->u1_is_popcnt_available);
1561
1562 ps_memtab += ihevce_me_get_num_mem_recs(i4_num_me_frm_pllel);
1563
1564 /* ---------- Coarse ME Mem init --------------- */
1565 ps_enc_ctxt->s_module_ctxt.pv_coarse_me_ctxt = ihevce_coarse_me_init(
1566 ps_memtab,
1567 ps_enc_ctxt->ps_stat_prms,
1568 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1569 ps_intrf_ctxt->pv_osal_handle,
1570 i4_resolution_id,
1571 ps_enc_ctxt->u1_is_popcnt_available);
1572
1573 ps_memtab += ihevce_coarse_me_get_num_mem_recs();
1574 /* ---------- IPE Mem init -------------- */
1575 ps_enc_ctxt->s_module_ctxt.pv_ipe_ctxt = ihevce_ipe_init(
1576 ps_memtab,
1577 ps_enc_ctxt->ps_stat_prms,
1578 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1579 ps_enc_ctxt->i4_ref_mbr_id,
1580 &ps_enc_ctxt->s_func_selector,
1581 &ps_enc_ctxt->s_rc_quant,
1582 i4_resolution_id,
1583 ps_enc_ctxt->u1_is_popcnt_available);
1584
1585 ps_memtab += ihevce_ipe_get_num_mem_recs();
1586
1587 ps_enc_ctxt->s_rc_quant.i2_max_qp = 51;
1588 ps_enc_ctxt->s_rc_quant.i2_min_qp = 0;
1589 ps_enc_ctxt->s_rc_quant.i1_qp_offset = 0;
1590 ps_enc_ctxt->s_rc_quant.i2_max_qscale =
1591 228 << 3; // Q3 format is mantained for accuarate calc at lower qp
1592 ps_enc_ctxt->s_rc_quant.i2_min_qscale = 1;
1593
1594 /* ---------- ECD Mem init -------------- */
1595 for(i = 0; i < i4_num_bitrate_inst; i++)
1596 {
1597 ps_enc_ctxt->s_module_ctxt.apv_ent_cod_ctxt[i] = ihevce_entropy_init(
1598 ps_memtab,
1599 ps_enc_ctxt->ps_stat_prms,
1600 (void *)ps_enc_ctxt->ps_tile_params_base,
1601 i4_resolution_id);
1602
1603 ps_memtab += ihevce_entropy_get_num_mem_recs();
1604 }
1605
1606 /* ---------- LAP Mem init--------------- */
1607 if(i4_resolution_id == 0)
1608 {
1609 ps_enc_ctxt->s_module_ctxt.pv_lap_ctxt =
1610 ihevce_lap_init(ps_memtab, &ps_enc_ctxt->s_lap_stat_prms, ps_enc_ctxt->ps_stat_prms);
1611
1612 ps_memtab += ihevce_lap_get_num_mem_recs();
1613 }
1614 /*-----------DECOMPOSITION PRE INTRA init----*/
1615 ps_enc_ctxt->s_module_ctxt.pv_decomp_pre_intra_ctxt = ihevce_decomp_pre_intra_init(
1616 ps_memtab,
1617 ps_enc_ctxt->ps_stat_prms,
1618 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1619 &ps_enc_ctxt->s_func_selector,
1620 i4_resolution_id,
1621 ps_enc_ctxt->u1_is_popcnt_available);
1622
1623 ps_memtab += ihevce_decomp_pre_intra_get_num_mem_recs();
1624
1625 /* ---------- RC Mem init --------------- */
1626 for(i = 0; i < i4_num_bitrate_inst; i++)
1627 {
1628 /*swaping of buf_id for 0th and reference bitrate location, as encoder
1629 assumes always 0th loc for reference bitrate and app must receive in
1630 the configured order*/
1631 if(i == 0)
1632 {
1633 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1634 ps_memtab,
1635 ps_enc_ctxt->ps_stat_prms,
1636 ps_enc_ctxt->i4_ref_mbr_id,
1637 &ps_enc_ctxt->s_rc_quant,
1638 ps_enc_ctxt->i4_resolution_id,
1639 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1640 }
1641 else if(i == ps_enc_ctxt->i4_ref_mbr_id)
1642 {
1643 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1644 ps_memtab,
1645 ps_enc_ctxt->ps_stat_prms,
1646 0,
1647 &ps_enc_ctxt->s_rc_quant,
1648 ps_enc_ctxt->i4_resolution_id,
1649 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1650 }
1651 else
1652 {
1653 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1654 ps_memtab,
1655 ps_enc_ctxt->ps_stat_prms,
1656 i,
1657 &ps_enc_ctxt->s_rc_quant,
1658 ps_enc_ctxt->i4_resolution_id,
1659 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1660 }
1661 ps_memtab += ihevce_rc_get_num_mem_recs();
1662 }
1663
1664 /* ---------- System Mem init ----------- */
1665 {
1666 recon_pic_buf_t **pps_pic_bufs[IHEVCE_MAX_NUM_BITRATES];
1667 recon_pic_buf_t *ps_pic_bufs[IHEVCE_MAX_NUM_BITRATES];
1668 void *pv_recon_buf[IHEVCE_MAX_NUM_BITRATES];
1669 #if(SRC_PADDING_FOR_TRAQO || ENABLE_SSD_CALC_RC)
1670 void *pv_recon_buf_source[IHEVCE_MAX_NUM_BITRATES] = { NULL };
1671 #endif
1672 void *pv_uv_recon_buf[IHEVCE_MAX_NUM_BITRATES];
1673 UWORD8 *pu1_subpel_buf;
1674 pu_col_mv_t *ps_col_mv;
1675 UWORD8 *pu1_col_mv_map;
1676 UWORD16 *pu2_col_num_pu_map;
1677 UWORD32 *pu4_col_mv_off;
1678 WORD32 luma_frm_size;
1679 WORD32 recon_stride; /* stride for Y and UV(interleave) */
1680 WORD32 luma_frm_height; /* including padding */
1681 WORD32 num_pu_in_frm;
1682
1683 /* pps tile memory */
1684 for(i = 0; i < i4_num_bitrate_inst; i++)
1685 {
1686 ps_enc_ctxt->as_pps[i].ps_tile = (tile_t *)ps_memtab->pv_base;
1687 }
1688
1689 ps_memtab++; /* increment the memtabs */
1690
1691 /* recon picture buffer pointer array */
1692 for(i = 0; i < i4_num_bitrate_inst; i++)
1693 {
1694 pps_pic_bufs[i] = (recon_pic_buf_t **)ps_memtab->pv_base;
1695 ps_memtab++; /* increment the memtabs */
1696 }
1697
1698 /* recon picture buffers structures */
1699 for(i = 0; i < i4_num_bitrate_inst; i++)
1700 {
1701 ps_pic_bufs[i] = (recon_pic_buf_t *)ps_memtab->pv_base;
1702 ps_memtab++; /* increment the memtabs */
1703 }
1704
1705 /* reference/recon picture buffers */
1706 for(i = 0; i < i4_num_bitrate_inst; i++)
1707 {
1708 pv_recon_buf[i] = ps_memtab->pv_base;
1709 ps_memtab++; /* increment the memtabs */
1710 }
1711 /* reference/recon picture subpel planes */
1712 pu1_subpel_buf = (UWORD8 *)ps_memtab->pv_base;
1713 /* increment the memtabs */
1714 ps_memtab++;
1715 /* reference colocated MV bank */
1716 ps_col_mv = (pu_col_mv_t *)ps_memtab->pv_base;
1717 /* increment the memtabs */
1718 ps_memtab++;
1719
1720 /* reference colocated MV bank map */
1721 pu1_col_mv_map = (UWORD8 *)ps_memtab->pv_base;
1722 /* increment the memtabs */
1723 ps_memtab++;
1724
1725 /* reference collocated MV bank map offsets map */
1726 pu2_col_num_pu_map = (UWORD16 *)ps_memtab->pv_base;
1727 /* increment the memtabs */
1728 ps_memtab++;
1729
1730 /* reference colocated MV bank ctb offset */
1731 pu4_col_mv_off = (UWORD32 *)ps_memtab->pv_base;
1732 /* increment the memtabs */
1733 ps_memtab++;
1734
1735 /* compute the stride and frame height after accounting for padding */
1736 recon_stride = ((num_ctb_horz * ctb_size) + (PAD_HORZ << 1));
1737 luma_frm_height = ((num_ctb_vert * ctb_size) + (PAD_VERT << 1));
1738 luma_frm_size = recon_stride * luma_frm_height;
1739 /* The subpel buffer is also incremented to take care of padding */
1740 /* Both luma and subpel buffer use same stride */
1741 pu1_subpel_buf += (recon_stride * PAD_VERT);
1742 pu1_subpel_buf += PAD_HORZ;
1743
1744 /* Keep memory for an extra CTB at the right and bottom of frame.
1745 This extra space is needed by dist-encoding and unused in non-dist-encoding */
1746 num_pu_in_frm = (num_ctb_horz + 1) * num_pu_in_ctb * (num_ctb_vert + 1);
1747
1748 for(i = 0; i < i4_num_bitrate_inst; i++)
1749 {
1750 pv_uv_recon_buf[i] = pv_recon_buf[i];
1751
1752 /* increment the recon buffer to take care of padding */
1753 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + (recon_stride * PAD_VERT) + PAD_HORZ;
1754
1755 /* chroma buffer starts at the end of luma buffer */
1756 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + luma_frm_size;
1757 if(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth == 8)
1758 {
1759 /* increment the chroma recon buffer to take care of padding */
1760 /* vert padding halved but horiz is same due to uv interleave */
1761 pv_uv_recon_buf[i] =
1762 (UWORD8 *)pv_uv_recon_buf[i] + (recon_stride * (PAD_VERT >> 1)) +
1763 ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1764 ? (recon_stride * (PAD_VERT >> 1))
1765 : 0);
1766 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + PAD_HORZ;
1767 }
1768
1769 /* loop to initialise all the memories */
1770 /* initialize recon buffers */
1771 /* only YUV buffers are allocated for each bit-rate instnaces.
1772 Subpel buffers and col buffers are made NULL for auxiliary bit-rate instances,
1773 since ME and IPE happens only for reference bit-rate instnace */
1774 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
1775 {
1776 pps_pic_bufs[i][ctr] =
1777 ps_pic_bufs[i]; //check the index of pps [i] should be first or last index?!!
1778
1779 ps_pic_bufs[i]->s_yuv_buf_desc.i4_size = sizeof(iv_enc_yuv_buf_t);
1780 ps_pic_bufs[i]->s_yuv_buf_desc.pv_y_buf = pv_recon_buf[i];
1781 ps_pic_bufs[i]->s_yuv_buf_desc.pv_v_buf = NULL;
1782 {
1783 ps_pic_bufs[i]->s_yuv_buf_desc.pv_u_buf = pv_uv_recon_buf[i];
1784 }
1785 ps_pic_bufs[i]->apu1_y_sub_pel_planes[0] = ((i == 0) ? pu1_subpel_buf : NULL);
1786 ps_pic_bufs[i]->apu1_y_sub_pel_planes[1] =
1787 ((i == 0) ? (pu1_subpel_buf + luma_frm_size) : NULL);
1788 ps_pic_bufs[i]->apu1_y_sub_pel_planes[2] =
1789 ((i == 0) ? (pu1_subpel_buf + (luma_frm_size * 2)) : NULL);
1790 ps_pic_bufs[i]->ps_frm_col_mv = ps_col_mv;
1791 ps_pic_bufs[i]->pu1_frm_pu_map = pu1_col_mv_map;
1792 ps_pic_bufs[i]->pu2_num_pu_map = pu2_col_num_pu_map;
1793 ps_pic_bufs[i]->pu4_pu_off = pu4_col_mv_off;
1794 ps_pic_bufs[i]->i4_is_free = 1;
1795 ps_pic_bufs[i]->i4_poc = -1;
1796 ps_pic_bufs[i]->i4_display_num = -1;
1797 ps_pic_bufs[i]->i4_buf_id = ctr;
1798
1799 /* frame level buff increments */
1800 ps_col_mv += num_pu_in_frm;
1801 pu1_col_mv_map += num_pu_in_frm;
1802 pu2_col_num_pu_map += (num_ctb_horz * num_ctb_vert);
1803 pu4_col_mv_off += (num_ctb_horz * num_ctb_vert);
1804
1805 if(ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1806 {
1807 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + (luma_frm_size << 1);
1808 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + (luma_frm_size << 1);
1809 }
1810 else
1811 {
1812 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + ((3 * luma_frm_size) >> 1);
1813 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + ((3 * luma_frm_size) >> 1);
1814 }
1815 pu1_subpel_buf += ((3 + L0ME_IN_OPENLOOP_MODE) * luma_frm_size); /* 3 planes */
1816 ps_pic_bufs[i]++;
1817 } //ctr ends
1818
1819 /* store the queue pointer and num buffs to context */
1820 ps_enc_ctxt->pps_recon_buf_q[i] = pps_pic_bufs[i];
1821 ps_enc_ctxt->ai4_num_buf_recon_q[i] = (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS);
1822
1823 } //bitrate ctr ends
1824
1825 } //end of system memory init
1826
1827 /* Pre encode group recon buffer containier NO Buffers will be allocated / used */
1828 {
1829 recon_pic_buf_t *ps_pic_bufs;
1830
1831 /* recon picture buffer pointer array */
1832 pps_pre_enc_pic_bufs = (recon_pic_buf_t **)ps_memtab->pv_base;
1833 /* increment the memtabs */
1834 ps_memtab++;
1835
1836 /* recon picture buffers structures */
1837 ps_pic_bufs = (recon_pic_buf_t *)ps_memtab->pv_base;
1838 /* increment the memtabs */
1839 ps_memtab++;
1840
1841 /* loop to initialise all the memories */
1842 for(ctr = 0; ctr < (max_num_ref_pics + 1); ctr++)
1843 {
1844 pps_pre_enc_pic_bufs[ctr] = ps_pic_bufs;
1845
1846 ps_pic_bufs->s_yuv_buf_desc.i4_size = sizeof(iv_enc_yuv_buf_t);
1847 ps_pic_bufs->s_yuv_buf_desc.pv_y_buf = NULL;
1848 ps_pic_bufs->s_yuv_buf_desc.pv_u_buf = NULL;
1849 ps_pic_bufs->s_yuv_buf_desc.pv_v_buf = NULL;
1850 ps_pic_bufs->apu1_y_sub_pel_planes[0] = NULL;
1851 ps_pic_bufs->apu1_y_sub_pel_planes[1] = NULL;
1852 ps_pic_bufs->apu1_y_sub_pel_planes[2] = NULL;
1853 ps_pic_bufs->ps_frm_col_mv = NULL;
1854 ps_pic_bufs->pu1_frm_pu_map = NULL;
1855 ps_pic_bufs->pu2_num_pu_map = NULL;
1856 ps_pic_bufs->pu4_pu_off = NULL;
1857 ps_pic_bufs->i4_is_free = 1;
1858 ps_pic_bufs->i4_poc = -1;
1859 ps_pic_bufs->i4_buf_id = ctr;
1860
1861 /* frame level buff increments */
1862 ps_pic_bufs++;
1863 }
1864
1865 /* store the queue pointer and num buffs to context */
1866 ps_enc_ctxt->pps_pre_enc_recon_buf_q = pps_pre_enc_pic_bufs;
1867 ps_enc_ctxt->i4_pre_enc_num_buf_recon_q = (max_num_ref_pics + 1);
1868 }
1869
1870 /* Frame level buffers and Que between pre-encode & encode */
1871 {
1872 pre_enc_me_ctxt_t *ps_pre_enc_bufs;
1873 pre_enc_L0_ipe_encloop_ctxt_t *ps_L0_ipe_enc_bufs;
1874 ihevce_lap_enc_buf_t *ps_lap_enc_input_buf;
1875 ctb_analyse_t *ps_ctb_analyse;
1876 UWORD8 *pu1_me_lyr_ctxt;
1877 UWORD8 *pu1_me_lyr_bank_ctxt;
1878 UWORD8 *pu1_mv_bank;
1879 UWORD8 *pu1_ref_idx_bank;
1880 double *plf_intra_8x8_cost;
1881 ipe_l0_ctb_analyse_for_me_t *ps_ipe_analyse_ctb;
1882 ihevce_ed_ctb_l1_t *ps_ed_ctb_l1;
1883 ihevce_ed_blk_t *ps_layer1_buf;
1884 ihevce_ed_blk_t *ps_layer2_buf;
1885 UWORD8 *pu1_lap_input_yuv_buf[4];
1886 UWORD8 *pu1_input_synch_ctrl_cmd;
1887 WORD32 i4_count = 0;
1888 /*initialize the memory for input buffer*/
1889 {
1890 for(i4_count = 0; i4_count < i4_total_queues; i4_count++)
1891 {
1892 pu1_lap_input_yuv_buf[i4_count] = (UWORD8 *)ps_memtab->pv_base;
1893 /* increment the memtabs */
1894 ps_memtab++;
1895 }
1896 pps_lap_enc_input_bufs = (ihevce_lap_enc_buf_t **)ps_memtab->pv_base;
1897 /* increment the memtabs */
1898 ps_memtab++;
1899
1900 /*memory for the input buffer structure*/
1901 ps_lap_enc_input_buf = (ihevce_lap_enc_buf_t *)ps_memtab->pv_base;
1902 ps_memtab++;
1903
1904 pu1_input_synch_ctrl_cmd = (UWORD8 *)ps_memtab->pv_base;
1905 ps_memtab++;
1906 }
1907 /* pre encode /encode coding buffer pointer array */
1908 pps_pre_enc_bufs = (pre_enc_me_ctxt_t **)ps_memtab->pv_base;
1909 /* increment the memtabs */
1910 ps_memtab++;
1911
1912 /* pre encode /encode buffer structure */
1913 ps_pre_enc_bufs = (pre_enc_me_ctxt_t *)ps_memtab->pv_base;
1914 /* increment the memtabs */
1915 ps_memtab++;
1916
1917 /* Pre-encode L0 IPE output to ME buffer pointer */
1918 pps_L0_ipe_enc_bufs = (pre_enc_L0_ipe_encloop_ctxt_t **)ps_memtab->pv_base;
1919 /* increment the memtabs */
1920 ps_memtab++;
1921
1922 /* Pre-encode L0 IPE output to ME buffer */
1923 ps_L0_ipe_enc_bufs = (pre_enc_L0_ipe_encloop_ctxt_t *)ps_memtab->pv_base;
1924 /* increment the memtabs */
1925 ps_memtab++;
1926
1927 /* CTB analyse Frame level */
1928 ps_ctb_analyse = (ctb_analyse_t *)ps_memtab->pv_base;
1929 /* increment the memtabs */
1930 ps_memtab++;
1931
1932 /* ME layer ctxt Frame level */
1933 pu1_me_lyr_ctxt = (UWORD8 *)ps_memtab->pv_base;
1934 /* increment the memtabs */
1935 ps_memtab++;
1936
1937 /* ME layer bank ctxt Frame level */
1938 pu1_me_lyr_bank_ctxt = (UWORD8 *)ps_memtab->pv_base;
1939 /* increment the memtabs */
1940 ps_memtab++;
1941
1942 /* ME layer MV bank Frame level */
1943 pu1_mv_bank = (UWORD8 *)ps_memtab->pv_base;
1944 /* increment the memtabs */
1945 ps_memtab++;
1946
1947 /* ME layer ref idx bank Frame level */
1948 pu1_ref_idx_bank = (UWORD8 *)ps_memtab->pv_base;
1949 /* increment the memtabs */
1950 ps_memtab++;
1951 /* 8x8 intra costs for entire frame */
1952 plf_intra_8x8_cost = (double *)ps_memtab->pv_base;
1953 ps_memtab++;
1954
1955 /* ctb intra costs and modes for entire frame */
1956 ps_ipe_analyse_ctb = (ipe_l0_ctb_analyse_for_me_t *)ps_memtab->pv_base;
1957 ps_memtab++;
1958
1959 /*Contains ctb level information at pre-intra stage */
1960 ps_ed_ctb_l1 = (ihevce_ed_ctb_l1_t *)ps_memtab->pv_base;
1961 ps_memtab++;
1962
1963 /* Layer L1 buf */
1964 ps_layer1_buf = (ihevce_ed_blk_t *)ps_memtab->pv_base;
1965 /* increment the memtabs */
1966 ps_memtab++;
1967
1968 /* Layer2 buf */
1969 ps_layer2_buf = (ihevce_ed_blk_t *)ps_memtab->pv_base;
1970 /* increment the memtabs */
1971 ps_memtab++;
1972
1973 /* loop to initialise all the memories*/
1974 /*mrs: assign individual input yuv frame pointers here*/
1975
1976 i4_count = 0;
1977 /* loop to initialise the buffer pointer */
1978 for(ctr = 0; ctr < num_input_buf_per_queue; ctr++)
1979 {
1980 pps_lap_enc_input_bufs[ctr] = &ps_lap_enc_input_buf[ctr];
1981
1982 pps_lap_enc_input_bufs[ctr]->s_input_buf.i4_size = sizeof(iv_input_data_ctrl_buffs_t);
1983
1984 pps_lap_enc_input_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs = pu1_input_synch_ctrl_cmd;
1985
1986 pps_lap_enc_input_bufs[ctr]->s_input_buf.s_input_buf.i4_size = sizeof(iv_yuv_buf_t);
1987
1988 pu1_input_synch_ctrl_cmd += ENC_COMMAND_BUFF_SIZE;
1989 /*pointer to i/p buf initialised to null in case of run time allocation*/
1990
1991 {
1992 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_y_buf =
1993 pu1_lap_input_yuv_buf[i4_count];
1994
1995 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_u_buf =
1996 pu1_lap_input_yuv_buf[i4_count] + i4_luma_min_size;
1997
1998 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_v_buf =
1999 NULL; /*since yuv 420 format*/
2000
2001 pu1_lap_input_yuv_buf[i4_count] += i4_yuv_min_size;
2002
2003 if(((ctr + 1) % MAX_QUEUE) == 0)
2004 i4_count++;
2005 }
2006 }
2007 for(ctr = 0; ctr < num_bufs_preenc_me_que; ctr++)
2008 {
2009 pps_pre_enc_bufs[ctr] = ps_pre_enc_bufs;
2010
2011 ps_pre_enc_bufs->ps_ctb_analyse = ps_ctb_analyse;
2012 ps_pre_enc_bufs->pv_me_lyr_ctxt = (void *)pu1_me_lyr_ctxt;
2013 ps_pre_enc_bufs->pv_me_lyr_bnk_ctxt = (void *)pu1_me_lyr_bank_ctxt;
2014 ps_pre_enc_bufs->pv_me_mv_bank = (void *)pu1_mv_bank;
2015 ps_pre_enc_bufs->pv_me_ref_idx = (void *)pu1_ref_idx_bank;
2016 ps_pre_enc_bufs->ps_layer1_buf = ps_layer1_buf;
2017 ps_pre_enc_bufs->ps_layer2_buf = ps_layer2_buf;
2018 ps_pre_enc_bufs->ps_ed_ctb_l1 = ps_ed_ctb_l1;
2019 ps_pre_enc_bufs->plf_intra_8x8_cost = plf_intra_8x8_cost;
2020
2021 ps_ctb_analyse += num_ctb_horz * num_ctb_vert;
2022 pu1_me_lyr_ctxt += sizeof(layer_ctxt_t);
2023 pu1_me_lyr_bank_ctxt += sizeof(layer_mv_t);
2024 pu1_mv_bank += mv_bank_size;
2025 pu1_ref_idx_bank += ref_idx_bank_size;
2026 plf_intra_8x8_cost +=
2027 (((num_ctb_horz * ctb_size) >> 3) * ((num_ctb_vert * ctb_size) >> 3));
2028 ps_ed_ctb_l1 += (a_ctb_align_wd[1] >> 5) * (a_ctb_align_ht[1] >> 5);
2029 ps_layer1_buf += (a_ctb_align_wd[1] >> 2) * (a_ctb_align_ht[1] >> 2);
2030 ps_layer2_buf += (a_ctb_align_wd[2] >> 2) * (a_ctb_align_ht[2] >> 2);
2031 ps_pre_enc_bufs++;
2032 }
2033
2034 for(ctr = 0; ctr < num_bufs_L0_ipe_enc; ctr++)
2035 {
2036 pps_L0_ipe_enc_bufs[ctr] = ps_L0_ipe_enc_bufs;
2037 ps_L0_ipe_enc_bufs->ps_ipe_analyse_ctb = ps_ipe_analyse_ctb;
2038 ps_ipe_analyse_ctb += num_ctb_horz * num_ctb_vert;
2039 ps_L0_ipe_enc_bufs++;
2040 }
2041 }
2042
2043 /* Frame level que between ME and Enc rd-opt */
2044 {
2045 me_enc_rdopt_ctxt_t *ps_me_enc_bufs;
2046 job_queue_t *ps_job_q_enc;
2047 me_ctb_data_t *ps_cur_ctb_me_data;
2048 cur_ctb_cu_tree_t *ps_cur_ctb_cu_tree;
2049
2050 /* pre encode /encode coding buffer pointer array */
2051 pps_me_enc_bufs = (me_enc_rdopt_ctxt_t **)ps_memtab->pv_base;
2052 /* increment the memtabs */
2053 ps_memtab++;
2054
2055 /* pre encode /encode buffer structure */
2056 ps_me_enc_bufs = (me_enc_rdopt_ctxt_t *)ps_memtab->pv_base;
2057 /* increment the memtabs */
2058 ps_memtab++;
2059
2060 /*me and enc job queue memory */
2061 ps_job_q_enc = (job_queue_t *)ps_memtab->pv_base;
2062 /* increment the memtabs */
2063 ps_memtab++;
2064
2065 /*ctb me data memory*/
2066 ps_cur_ctb_cu_tree = (cur_ctb_cu_tree_t *)ps_memtab->pv_base;
2067 /* increment the memtabs */
2068 ps_memtab++;
2069
2070 /*ctb me data memory*/
2071 ps_cur_ctb_me_data = (me_ctb_data_t *)ps_memtab->pv_base;
2072 /* increment the memtabs */
2073 ps_memtab++;
2074
2075 /* loop to initialise all the memories */
2076 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
2077 {
2078 pps_me_enc_bufs[ctr] = ps_me_enc_bufs;
2079
2080 ps_me_enc_bufs->ps_job_q_enc = ps_job_q_enc;
2081 ps_me_enc_bufs->ps_cur_ctb_cu_tree = ps_cur_ctb_cu_tree;
2082 ps_me_enc_bufs->ps_cur_ctb_me_data = ps_cur_ctb_me_data;
2083
2084 ps_job_q_enc += (MAX_NUM_VERT_UNITS_FRM * NUM_ENC_JOBS_QUES);
2085 /* In tile case, based on the number of column tiles,
2086 increment jobQ per column tile */
2087 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
2088 {
2089 WORD32 col_tile_ctr;
2090 for(col_tile_ctr = 1;
2091 col_tile_ctr < ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols;
2092 col_tile_ctr++)
2093 {
2094 ps_job_q_enc += (MAX_NUM_VERT_UNITS_FRM * NUM_ENC_JOBS_QUES);
2095 }
2096 }
2097
2098 ps_cur_ctb_cu_tree += (num_ctb_horz * MAX_NUM_NODES_CU_TREE * num_ctb_vert);
2099 ps_cur_ctb_me_data += (num_ctb_horz * num_ctb_vert);
2100
2101 ps_me_enc_bufs++;
2102 }
2103 }
2104 /* Frame level Que between frame process & entropy */
2105 for(i = 0; i < i4_num_bitrate_inst; i++)
2106 {
2107 frm_proc_ent_cod_ctxt_t *ps_frmp_ent_bufs;
2108 ctb_enc_loop_out_t *ps_ctb;
2109 cu_enc_loop_out_t *ps_cu;
2110 tu_enc_loop_out_t *ps_tu;
2111 pu_t *ps_pu;
2112 UWORD8 *pu1_coeffs;
2113 WORD32 num_ctb_in_frm;
2114 WORD32 coeff_size;
2115 UWORD8 *pu1_sei_payload;
2116
2117 /* frame process/entropy coding buffer pointer array */
2118 pps_frm_proc_ent_cod_bufs[i] = (frm_proc_ent_cod_ctxt_t **)ps_memtab->pv_base;
2119 /* increment the memtabs */
2120 ps_memtab++;
2121
2122 /* frame process/entropy coding buffer structure */
2123 ps_frmp_ent_bufs = (frm_proc_ent_cod_ctxt_t *)ps_memtab->pv_base;
2124 /* increment the memtabs */
2125 ps_memtab++;
2126
2127 /* CTB enc loop Frame level */
2128 ps_ctb = (ctb_enc_loop_out_t *)ps_memtab->pv_base;
2129 /* increment the memtabs */
2130 ps_memtab++;
2131
2132 /* CU enc loop Frame level */
2133 ps_cu = (cu_enc_loop_out_t *)ps_memtab->pv_base;
2134 /* increment the memtabs */
2135 ps_memtab++;
2136
2137 /* TU enc loop Frame level */
2138 ps_tu = (tu_enc_loop_out_t *)ps_memtab->pv_base;
2139 /* increment the memtabs */
2140 ps_memtab++;
2141
2142 /* PU enc loop Frame level */
2143 ps_pu = (pu_t *)ps_memtab->pv_base;
2144 /* increment the memtabs */
2145 ps_memtab++;
2146
2147 /* Coeffs Frame level */
2148 pu1_coeffs = (UWORD8 *)ps_memtab->pv_base;
2149 /* increment the memtabs */
2150 ps_memtab++;
2151
2152 /* CC User Data */
2153 pu1_sei_payload = (UWORD8 *)ps_memtab->pv_base;
2154 ps_memtab++;
2155
2156 num_ctb_in_frm = num_ctb_horz * num_ctb_vert;
2157
2158 /* calculate the coeff size */
2159 coeff_size =
2160 num_ctb_horz * ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
2161 ? (num_tu_in_ctb << 1)
2162 : ((num_tu_in_ctb * 3) >> 1));
2163 coeff_size = coeff_size * num_ctb_vert * MAX_SCAN_COEFFS_BYTES_4x4;
2164 /* loop to initialise all the memories */
2165 for(ctr = 0; ctr < NUM_FRMPROC_ENTCOD_BUFS; ctr++)
2166 {
2167 WORD32 num_sei;
2168 pps_frm_proc_ent_cod_bufs[i][ctr] = ps_frmp_ent_bufs;
2169
2170 ps_frmp_ent_bufs->ps_frm_ctb_data = ps_ctb;
2171 ps_frmp_ent_bufs->ps_frm_cu_data = ps_cu;
2172 ps_frmp_ent_bufs->ps_frm_pu_data = ps_pu;
2173 ps_frmp_ent_bufs->ps_frm_tu_data = ps_tu;
2174 ps_frmp_ent_bufs->pv_coeff_data = pu1_coeffs;
2175
2176 /* memset the slice headers and buffer to keep track */
2177 memset(&ps_frmp_ent_bufs->s_slice_hdr, 0, sizeof(slice_header_t));
2178
2179 /*PIC_INFO*/
2180 memset(&ps_frmp_ent_bufs->s_pic_level_info, 0, sizeof(s_pic_level_acc_info_t));
2181
2182 ps_ctb += num_ctb_in_frm;
2183 ps_cu += num_ctb_in_frm * num_cu_in_ctb;
2184 ps_pu += num_ctb_in_frm * num_pu_in_ctb;
2185 ps_tu += num_ctb_in_frm * num_tu_in_ctb;
2186
2187 pu1_coeffs += coeff_size;
2188
2189 for(num_sei = 0; num_sei < MAX_NUMBER_OF_SEI_PAYLOAD; num_sei++)
2190 {
2191 ps_frmp_ent_bufs->as_sei_payload[num_sei].pu1_sei_payload = pu1_sei_payload;
2192 ps_frmp_ent_bufs->as_sei_payload[num_sei].u4_payload_type = 0;
2193 ps_frmp_ent_bufs->as_sei_payload[num_sei].u4_payload_length = 0;
2194 pu1_sei_payload += MAX_SEI_PAYLOAD_PER_TLV;
2195 }
2196
2197 ps_frmp_ent_bufs++;
2198 }
2199 }
2200
2201 /* Working memory for encoder */
2202 ps_enc_ctxt->pu1_frm_lvl_wkg_mem = (UWORD8 *)ps_memtab->pv_base;
2203 ps_memtab++;
2204
2205 /* Job Que memory */
2206 /* Job que memory distribution is as follows _______
2207 enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_ENC_JOBS_QUES)------------>|_______|
2208 enc_group_pong -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_ENC_JOBS_QUES)------------>|_______|
2209 pre_enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_PRE_ENC_JOBS_QUES)---->|_______|
2210 pre_enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_PRE_ENC_JOBS_QUES)---->|_______|
2211 */
2212
2213 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[0] = (job_queue_t *)ps_memtab->pv_base;
2214 for(ctr = 1; ctr < max_delay_preenc_l0_que; ctr++)
2215 {
2216 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[ctr] =
2217 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[0] +
2218 (MAX_NUM_VERT_UNITS_FRM * NUM_PRE_ENC_JOBS_QUES * ctr);
2219 }
2220 ps_memtab++;
2221
2222 /* -----Frameproc Entcod Que mem_init --- */
2223 /* init ptrs for each bit-rate */
2224 for(i = 0; i < i4_num_bitrate_inst; i++)
2225 {
2226 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_FRM_PRS_ENT_COD_Q + i] = ihevce_buff_que_init(
2227 ps_memtab, NUM_FRMPROC_ENTCOD_BUFS, (void **)pps_frm_proc_ent_cod_bufs[i]);
2228 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2229 }
2230 /*mrs*/
2231 /* ----Encoder owned input buffer queue init----*/
2232 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_ENC_INPUT_Q] =
2233 ihevce_buff_que_init(ps_memtab, num_input_buf_per_queue, (void **)pps_lap_enc_input_bufs);
2234 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2235
2236 /* -----Pre-Encode / Encode Que mem_init --- */
2237 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_PRE_ENC_ME_Q] =
2238 ihevce_buff_que_init(ps_memtab, num_bufs_preenc_me_que, (void **)pps_pre_enc_bufs);
2239
2240 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2241
2242 /* -----ME / Enc-RD opt Que mem_init --- */
2243 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_ME_ENC_RDOPT_Q] =
2244 ihevce_buff_que_init(ps_memtab, NUM_ME_ENC_BUFS, (void **)pps_me_enc_bufs);
2245
2246 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2247
2248 /* -----Pre-Encode L0 IPE to enc queue --- */
2249 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_L0_IPE_ENC_Q] =
2250 ihevce_buff_que_init(ps_memtab, num_bufs_L0_ipe_enc, (void **)pps_L0_ipe_enc_bufs);
2251
2252 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2253
2254 /* ---------- Dependency Manager allocations -------- */
2255 {
2256 osal_sem_attr_t attr = OSAL_DEFAULT_SEM_ATTR;
2257 WORD32 i1_is_sem_enabled;
2258
2259 if(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id]
2260 .i4_quality_preset >= IHEVCE_QUALITY_P4)
2261 {
2262 i1_is_sem_enabled = 0;
2263 }
2264 else
2265 {
2266 i1_is_sem_enabled = 1;
2267 }
2268
2269 /* allocate semaphores for all the threads in pre-enc and enc */
2270 for(ctr = 0; ctr < ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds; ctr++)
2271 {
2272 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle[ctr] =
2273 osal_sem_create(ps_intrf_ctxt->pv_osal_handle, &attr);
2274 if(NULL == ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle[ctr])
2275 {
2276 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2277 return;
2278 }
2279 }
2280
2281 for(ctr = 0; ctr < ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds; ctr++)
2282 {
2283 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle[ctr] =
2284 osal_sem_create(ps_intrf_ctxt->pv_osal_handle, &attr);
2285 if(NULL == ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle[ctr])
2286 {
2287 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2288 return;
2289 }
2290 }
2291
2292 /* --- ME-EncLoop Dep Mngr Row-Row Init -- */
2293 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
2294 {
2295 me_enc_rdopt_ctxt_t *ps_me_enc_bufs = pps_me_enc_bufs[ctr];
2296
2297 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me = ihevce_dmgr_init(
2298 ps_memtab,
2299 ps_intrf_ctxt->pv_osal_handle,
2300 DEP_MNGR_ROW_ROW_SYNC,
2301 (a_ctb_align_ht[0] / ctb_size),
2302 (a_ctb_align_wd[0] / ctb_size),
2303 ps_enc_ctxt->ps_tile_params_base->i4_num_tile_cols, /* Number of Col Tiles */
2304 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2305 i1_is_sem_enabled /*Sem Disabled/Enabled*/
2306 );
2307 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2308
2309 /* Register Enc group semaphore handles */
2310 ihevce_dmgr_reg_sem_hdls(
2311 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me,
2312 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2313 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2314
2315 /* Register the handle in multithread ctxt also for free purpose */
2316 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_encloop_dep_me[ctr] =
2317 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me;
2318 }
2319
2320 for(ctr = 0; ctr < i4_num_enc_loop_frm_pllel; ctr++)
2321 {
2322 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem Init -- */
2323 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_done[ctr] = ihevce_dmgr_init(
2324 ps_memtab,
2325 ps_intrf_ctxt->pv_osal_handle,
2326 DEP_MNGR_FRM_FRM_SYNC,
2327 (a_ctb_align_ht[0] / ctb_size),
2328 (a_ctb_align_wd[0] / ctb_size),
2329 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2330 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2331 1 /*Sem Enabled*/
2332 );
2333 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2334
2335 /* Register Enc group semaphore handles */
2336 ihevce_dmgr_reg_sem_hdls(
2337 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_done[ctr],
2338 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2339 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2340 }
2341 /* --- Prev. frame EncLoop Done Dep Mngr for re-encode Frm-Frm Mem Init -- */
2342 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_enc_done_for_reenc = ihevce_dmgr_init(
2343 ps_memtab,
2344 ps_intrf_ctxt->pv_osal_handle,
2345 DEP_MNGR_FRM_FRM_SYNC,
2346 (a_ctb_align_ht[0] / ctb_size),
2347 (a_ctb_align_wd[0] / ctb_size),
2348 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2349 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2350 1 /*Sem Enabled*/
2351 );
2352 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2353
2354 /* Register Enc group semaphore handles */
2355 ihevce_dmgr_reg_sem_hdls(
2356 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_enc_done_for_reenc,
2357 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2358 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2359 for(ctr = 0; ctr < i4_num_me_frm_pllel; ctr++)
2360 {
2361 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem Init -- */
2362 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_me_done[ctr] = ihevce_dmgr_init(
2363 ps_memtab,
2364 ps_intrf_ctxt->pv_osal_handle,
2365 DEP_MNGR_FRM_FRM_SYNC,
2366 (a_ctb_align_ht[0] / ctb_size),
2367 (a_ctb_align_wd[0] / ctb_size),
2368 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2369 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2370 1 /*Sem Enabled*/
2371 );
2372 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2373
2374 /* Register Enc group semaphore handles */
2375 ihevce_dmgr_reg_sem_hdls(
2376 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_me_done[ctr],
2377 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2378 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2379 }
2380 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem Init -- */
2381 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l1 = ihevce_dmgr_init(
2382 ps_memtab,
2383 ps_intrf_ctxt->pv_osal_handle,
2384 DEP_MNGR_FRM_FRM_SYNC,
2385 (a_ctb_align_ht[0] / ctb_size),
2386 (a_ctb_align_wd[0] / ctb_size),
2387 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2388 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2389 1 /*Sem Enabled*/
2390 );
2391 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2392
2393 /* Register Pre-Enc group semaphore handles */
2394 ihevce_dmgr_reg_sem_hdls(
2395 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l1,
2396 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2397 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2398
2399 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem Init -- */
2400 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_coarse_me = ihevce_dmgr_init(
2401 ps_memtab,
2402 ps_intrf_ctxt->pv_osal_handle,
2403 DEP_MNGR_FRM_FRM_SYNC,
2404 (a_ctb_align_ht[0] / ctb_size),
2405 (a_ctb_align_wd[0] / ctb_size),
2406 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2407 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2408 1 /*Sem Enabled*/
2409 );
2410 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2411
2412 /* Register Pre-Enc group semaphore handles */
2413 ihevce_dmgr_reg_sem_hdls(
2414 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_coarse_me,
2415 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2416 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2417
2418 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem Init -- */
2419 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l0 = ihevce_dmgr_init(
2420 ps_memtab,
2421 ps_intrf_ctxt->pv_osal_handle,
2422 DEP_MNGR_FRM_FRM_SYNC,
2423 (a_ctb_align_ht[0] / ctb_size),
2424 (a_ctb_align_wd[0] / ctb_size),
2425 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2426 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2427 1 /*Sem Enabled*/
2428 );
2429 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2430
2431 /* Register Pre-Enc group semaphore handles */
2432 ihevce_dmgr_reg_sem_hdls(
2433 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l0,
2434 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2435 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2436
2437 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem init -- */
2438 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
2439 {
2440 WORD32 ai4_tile_xtra_ctb[4] = { 0 };
2441
2442 ps_enc_ctxt->pps_recon_buf_q[0][ctr]->pv_dep_mngr_recon = ihevce_dmgr_map_init(
2443 ps_memtab,
2444 num_ctb_vert,
2445 num_ctb_horz,
2446 i1_is_sem_enabled, /*Sem Disabled/Enabled*/
2447 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2448 ai4_tile_xtra_ctb);
2449
2450 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2451
2452 /* Register Enc group semaphore handles */
2453 ihevce_dmgr_reg_sem_hdls(
2454 ps_enc_ctxt->pps_recon_buf_q[0][ctr]->pv_dep_mngr_recon,
2455 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2456 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2457 }
2458
2459 /* ------ Module level register semaphores -------- */
2460 ihevce_coarse_me_reg_thrds_sem(
2461 ps_enc_ctxt->s_module_ctxt.pv_coarse_me_ctxt,
2462 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2463 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2464
2465 ihevce_enc_loop_reg_sem_hdls(
2466 ps_enc_ctxt->s_module_ctxt.pv_enc_loop_ctxt,
2467 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2468 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2469 }
2470
2471 /* copy the run time source parameters from create time prms */
2472 memcpy(
2473 &ps_enc_ctxt->s_runtime_src_prms,
2474 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
2475 sizeof(ihevce_src_params_t));
2476
2477 memcpy(
2478 &ps_enc_ctxt->s_runtime_tgt_params,
2479 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
2480 sizeof(ihevce_tgt_params_t));
2481
2482 /* copy the run time coding parameters from create time prms */
2483 memcpy(
2484 &ps_enc_ctxt->s_runtime_coding_prms,
2485 &ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms,
2486 sizeof(ihevce_coding_params_t));
2487
2488 /*change in run time parameter*/
2489 if(ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
2490 {
2491 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames = (DEFAULT_MAX_REFERENCE_PICS)
2492 << i4_field_pic;
2493
2494 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
2495 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
2496 }
2497
2498 /* populate the frame level ctb parameters based on run time params */
2499 ihevce_set_pre_enc_prms(ps_enc_ctxt);
2500
2501 return;
2502 }
2503
2504 /*!
2505 ******************************************************************************
2506 * \if Function name : ihevce_mem_manager_que_init \endif
2507 *
2508 * \brief
2509 * Encoder Que memory init function
2510 *
2511 * \param[in] Encoder context pointer
2512 * \param[in] High level Encoder context pointer
2513 * \param[in] Buffer descriptors
2514 *
2515 * \return
2516 * None
2517 *
2518 * \author
2519 * Ittiam
2520 *
2521 *****************************************************************************
2522 */
ihevce_mem_manager_que_init(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_hle_ctxt,iv_input_data_ctrl_buffs_desc_t * ps_input_data_ctrl_buffs_desc,iv_input_asynch_ctrl_buffs_desc_t * ps_input_asynch_ctrl_buffs_desc,iv_output_data_buffs_desc_t * ps_output_data_buffs_desc,iv_recon_data_buffs_desc_t * ps_recon_data_buffs_desc)2523 void ihevce_mem_manager_que_init(
2524 enc_ctxt_t *ps_enc_ctxt,
2525 ihevce_hle_ctxt_t *ps_hle_ctxt,
2526 iv_input_data_ctrl_buffs_desc_t *ps_input_data_ctrl_buffs_desc,
2527 iv_input_asynch_ctrl_buffs_desc_t *ps_input_asynch_ctrl_buffs_desc,
2528 iv_output_data_buffs_desc_t *ps_output_data_buffs_desc,
2529 iv_recon_data_buffs_desc_t *ps_recon_data_buffs_desc)
2530 {
2531 /* local variables */
2532 WORD32 total_memtabs_req = 0;
2533 WORD32 total_memtabs_used = 0;
2534 WORD32 ctr;
2535 iv_mem_rec_t *ps_memtab;
2536 WORD32 i; //counter variable
2537 iv_output_data_buffs_desc_t *ps_out_desc;
2538 iv_recon_data_buffs_desc_t *ps_rec_desc;
2539 WORD32 i4_num_bitrate_inst; //number of bit-rate instance
2540 /* storing 0th instance's pointer. This will be used for assigning buffer queue handles for input/output queues */
2541 enc_ctxt_t *ps_enc_ctxt_base = (enc_ctxt_t *)ps_hle_ctxt->apv_enc_hdl[0];
2542
2543 i4_num_bitrate_inst = ps_enc_ctxt->i4_num_bitrates;
2544 //ps_hle_ctxt->ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[0].i4_num_bitrate_instances;
2545
2546 /* --------------------------------------------------------------------- */
2547 /* -------------- Collating the number of memtabs required ------------ */
2548 /* --------------------------------------------------------------------- */
2549
2550 /* ------ Input Data Que Memtab -------- */
2551 if(0 == ps_enc_ctxt->i4_resolution_id)
2552 {
2553 /* array of pointers for input */
2554 total_memtabs_req++;
2555
2556 /* pointers for input desc */
2557 total_memtabs_req++;
2558
2559 /* que manager buffer requirements */
2560 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2561
2562 /* ------ Input Control Que memtab ----- */
2563 /* array of pointers for input control */
2564 total_memtabs_req++;
2565
2566 /* pointers for input control desc */
2567 total_memtabs_req++;
2568
2569 /* que manager buffer requirements */
2570 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2571 }
2572
2573 /* ------ Output Data Que Memtab -------- */
2574 for(i = 0; i < i4_num_bitrate_inst; i++)
2575 {
2576 /* array of pointers for output */
2577 total_memtabs_req++;
2578
2579 /* pointers for output desc */
2580 total_memtabs_req++;
2581
2582 /* que manager buffer requirements */
2583 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2584 }
2585
2586 /* ------ Recon Data Que Memtab -------- */
2587 for(i = 0; i < i4_num_bitrate_inst; i++)
2588 {
2589 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2590 {
2591 /* array of pointers for input */
2592 total_memtabs_req++;
2593
2594 /* pointers for input desc */
2595 total_memtabs_req++;
2596
2597 /* que manager buffer requirements */
2598 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2599 }
2600 }
2601
2602 /* ----- allocate memomry for memtabs --- */
2603 {
2604 iv_mem_rec_t s_memtab;
2605
2606 s_memtab.i4_size = sizeof(iv_mem_rec_t);
2607 s_memtab.i4_mem_size = total_memtabs_req * sizeof(iv_mem_rec_t);
2608 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2609 s_memtab.i4_mem_alignment = 4;
2610
2611 ps_hle_ctxt->ihevce_mem_alloc(
2612 ps_hle_ctxt->pv_mem_mgr_hdl, &ps_hle_ctxt->ps_static_cfg_prms->s_sys_api, &s_memtab);
2613 if(s_memtab.pv_base == NULL)
2614 {
2615 ps_hle_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2616 return;
2617 }
2618 ps_memtab = (iv_mem_rec_t *)s_memtab.pv_base;
2619 }
2620
2621 /* --------------------------------------------------------------------- */
2622 /* ------------------ Collating memory requirements ------------------- */
2623 /* --------------------------------------------------------------------- */
2624 if(0 == ps_enc_ctxt->i4_resolution_id)
2625 {
2626 /* ------ Input Data Que memory requests -------- */
2627 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2628
2629 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2630
2631 ps_memtab[total_memtabs_used].i4_mem_size =
2632 ((ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs) * (sizeof(ihevce_lap_enc_buf_t *)));
2633
2634 /* increment the memtab counter */
2635 total_memtabs_used++;
2636
2637 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2638
2639 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2640
2641 ps_memtab[total_memtabs_used].i4_mem_size =
2642 ((ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs) * (sizeof(ihevce_lap_enc_buf_t)));
2643
2644 /* increment the memtab counter */
2645 total_memtabs_used++;
2646
2647 /* call the Que manager get mem recs */
2648 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2649 &ps_memtab[total_memtabs_used],
2650 ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs,
2651 IV_EXT_CACHEABLE_NORMAL_MEM);
2652
2653 /* ------ Input Control Que memory requests -------- */
2654 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2655
2656 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2657
2658 ps_memtab[total_memtabs_used].i4_mem_size =
2659 ((ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs) *
2660 (sizeof(iv_input_ctrl_buffs_t *)));
2661
2662 /* increment the memtab counter */
2663 total_memtabs_used++;
2664
2665 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2666
2667 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2668
2669 ps_memtab[total_memtabs_used].i4_mem_size =
2670 ((ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs) *
2671 (sizeof(iv_input_ctrl_buffs_t)));
2672
2673 /* increment the memtab counter */
2674 total_memtabs_used++;
2675
2676 /* call the Que manager get mem recs */
2677 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2678 &ps_memtab[total_memtabs_used],
2679 ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs,
2680 IV_EXT_CACHEABLE_NORMAL_MEM);
2681 }
2682
2683 /* ------ Output data Que memory requests -------- */
2684 ps_out_desc = ps_output_data_buffs_desc;
2685 for(i = 0; i < i4_num_bitrate_inst; i++)
2686 {
2687 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2688
2689 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2690
2691 ps_memtab[total_memtabs_used].i4_mem_size =
2692 ((ps_out_desc->i4_num_bitstream_bufs) * (sizeof(iv_output_data_buffs_t *)));
2693
2694 /* increment the memtab counter */
2695 total_memtabs_used++;
2696
2697 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2698
2699 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2700
2701 ps_memtab[total_memtabs_used].i4_mem_size =
2702 ((ps_out_desc->i4_num_bitstream_bufs) * (sizeof(iv_output_data_buffs_t)));
2703
2704 /* increment the memtab counter */
2705 total_memtabs_used++;
2706
2707 /* call the Que manager get mem recs */
2708 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2709 &ps_memtab[total_memtabs_used],
2710 ps_out_desc->i4_num_bitstream_bufs,
2711 IV_EXT_CACHEABLE_NORMAL_MEM);
2712 ps_out_desc++;
2713 }
2714
2715 //recon_dump
2716 /* ------ Recon Data Que memory requests -------- */
2717 ps_rec_desc = ps_recon_data_buffs_desc;
2718 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2719 {
2720 for(i = 0; i < i4_num_bitrate_inst; i++)
2721 {
2722 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2723
2724 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2725
2726 ps_memtab[total_memtabs_used].i4_mem_size =
2727 ((ps_rec_desc->i4_num_recon_bufs) * (sizeof(iv_enc_recon_data_buffs_t *)));
2728
2729 /* increment the memtab counter */
2730 total_memtabs_used++;
2731
2732 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2733
2734 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2735
2736 ps_memtab[total_memtabs_used].i4_mem_size =
2737 ((ps_rec_desc->i4_num_recon_bufs) * (sizeof(iv_enc_recon_data_buffs_t)));
2738
2739 /* increment the memtab counter */
2740 total_memtabs_used++;
2741
2742 /* call the Que manager get mem recs */
2743 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2744 &ps_memtab[total_memtabs_used],
2745 ps_rec_desc->i4_num_recon_bufs,
2746 IV_EXT_CACHEABLE_NORMAL_MEM);
2747
2748 ps_rec_desc++;
2749 }
2750 }
2751
2752 /* ----- allocate memory as per requests ---- */
2753
2754 /* check on memtabs requested v/s memtabs used */
2755 //ittiam : should put an assert
2756 ASSERT(total_memtabs_req == total_memtabs_used);
2757 for(ctr = 0; ctr < total_memtabs_used; ctr++)
2758 {
2759 UWORD8 *pu1_mem = NULL;
2760 ps_hle_ctxt->ihevce_mem_alloc(
2761 ps_hle_ctxt->pv_mem_mgr_hdl,
2762 &ps_hle_ctxt->ps_static_cfg_prms->s_sys_api,
2763 &ps_memtab[ctr]);
2764
2765 pu1_mem = (UWORD8 *)ps_memtab[ctr].pv_base;
2766
2767 if(NULL == pu1_mem)
2768 {
2769 ps_hle_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2770 return;
2771 }
2772 }
2773
2774 /* store the final allocated memtabs */
2775 ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs = total_memtabs_used;
2776 ps_enc_ctxt->s_mem_mngr.ps_q_memtab = ps_memtab;
2777
2778 /* --------------------------------------------------------------------- */
2779 /* -------------- Initialisation of Queues memory ---------------------- */
2780 /* --------------------------------------------------------------------- */
2781
2782 /* ---------- Input Data Que Mem init --------------- */
2783 if(0 == ps_enc_ctxt->i4_resolution_id)
2784 {
2785 ihevce_lap_enc_buf_t **pps_inp_bufs;
2786 ihevce_lap_enc_buf_t *ps_inp_bufs;
2787
2788 pps_inp_bufs = (ihevce_lap_enc_buf_t **)ps_memtab->pv_base;
2789 ps_memtab++;
2790
2791 ps_inp_bufs = (ihevce_lap_enc_buf_t *)ps_memtab->pv_base;
2792 ps_memtab++;
2793
2794 /* loop to initialise the buffer pointer */
2795 for(ctr = 0; ctr < ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs; ctr++)
2796 {
2797 pps_inp_bufs[ctr] = &ps_inp_bufs[ctr];
2798
2799 pps_inp_bufs[ctr]->s_input_buf.i4_size = sizeof(iv_input_data_ctrl_buffs_t);
2800
2801 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.i4_size = sizeof(iv_yuv_buf_t);
2802
2803 /*pointer to i/p buf initialised to null in case of run time allocation*/
2804 if(ps_hle_ctxt->i4_create_time_input_allocation == 1)
2805 {
2806 pps_inp_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs =
2807 ps_input_data_ctrl_buffs_desc->ppv_synch_ctrl_bufs[ctr];
2808
2809 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_y_buf =
2810 ps_input_data_ctrl_buffs_desc->ppv_y_buf[ctr];
2811
2812 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_u_buf =
2813 ps_input_data_ctrl_buffs_desc->ppv_u_buf[ctr];
2814
2815 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_v_buf =
2816 ps_input_data_ctrl_buffs_desc->ppv_v_buf[ctr];
2817 }
2818 else
2819 {
2820 pps_inp_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs = NULL;
2821
2822 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_y_buf = NULL;
2823
2824 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_u_buf = NULL;
2825
2826 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_v_buf = NULL;
2827 }
2828 }
2829
2830 /* Get the input data buffer Q handle */
2831 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q] = ihevce_buff_que_init(
2832 ps_memtab, ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs, (void **)pps_inp_bufs);
2833
2834 /* increment the memtab pointer */
2835 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2836 }
2837 else
2838 {
2839 /* Get the input data buffer Q handle from 0th instance */
2840 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q] =
2841 ps_enc_ctxt_base->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q];
2842 }
2843
2844 /* ---------- Input control Que Mem init --------------- */
2845 if(0 == ps_enc_ctxt->i4_resolution_id)
2846 {
2847 iv_input_ctrl_buffs_t **pps_inp_bufs;
2848 iv_input_ctrl_buffs_t *ps_inp_bufs;
2849
2850 pps_inp_bufs = (iv_input_ctrl_buffs_t **)ps_memtab->pv_base;
2851 ps_memtab++;
2852
2853 ps_inp_bufs = (iv_input_ctrl_buffs_t *)ps_memtab->pv_base;
2854 ps_memtab++;
2855
2856 /* loop to initialise the buffer pointer */
2857 for(ctr = 0; ctr < ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs; ctr++)
2858 {
2859 pps_inp_bufs[ctr] = &ps_inp_bufs[ctr];
2860
2861 pps_inp_bufs[ctr]->i4_size = sizeof(iv_input_ctrl_buffs_t);
2862
2863 pps_inp_bufs[ctr]->pv_asynch_ctrl_bufs =
2864 ps_input_asynch_ctrl_buffs_desc->ppv_asynch_ctrl_bufs[ctr];
2865 }
2866
2867 /* Get the input control buffer Q handle */
2868 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q] = ihevce_buff_que_init(
2869 ps_memtab,
2870 ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs,
2871 (void **)pps_inp_bufs);
2872
2873 /* increment the memtab pointer */
2874 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2875 }
2876 else
2877 {
2878 /* Get the input control buffer Q handle from 0th instance */
2879 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q] =
2880 ps_enc_ctxt_base->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q];
2881 }
2882
2883 /* ---------- Output data Que Mem init --------------- */
2884 ps_out_desc = ps_output_data_buffs_desc;
2885 for(i = 0; i < i4_num_bitrate_inst; i++)
2886 {
2887 iv_output_data_buffs_t **pps_out_bufs;
2888 iv_output_data_buffs_t *ps_out_bufs;
2889
2890 pps_out_bufs = (iv_output_data_buffs_t **)ps_memtab->pv_base;
2891 ps_memtab++;
2892
2893 ps_out_bufs = (iv_output_data_buffs_t *)ps_memtab->pv_base;
2894 ps_memtab++;
2895
2896 /* loop to initialise the buffer pointer */
2897 for(ctr = 0; ctr < ps_out_desc->i4_num_bitstream_bufs; ctr++)
2898 {
2899 pps_out_bufs[ctr] = &ps_out_bufs[ctr];
2900
2901 pps_out_bufs[ctr]->i4_size = sizeof(iv_output_data_buffs_t);
2902
2903 pps_out_bufs[ctr]->i4_bitstream_buf_size = ps_out_desc->i4_size_bitstream_buf;
2904
2905 /*pointer to o/p buf initialised to null in case of run time allocation*/
2906 if(ps_hle_ctxt->i4_create_time_output_allocation == 1)
2907 {
2908 pps_out_bufs[ctr]->pv_bitstream_bufs = ps_out_desc->ppv_bitstream_bufs[ctr];
2909 }
2910 else
2911 {
2912 pps_out_bufs[ctr]->pv_bitstream_bufs = NULL;
2913 }
2914 }
2915
2916 /* Get the output data buffer Q handle */
2917 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_OUTPUT_DATA_Q + i] = ihevce_buff_que_init(
2918 ps_memtab, ps_out_desc->i4_num_bitstream_bufs, (void **)pps_out_bufs);
2919
2920 /* increment the memtab pointer */
2921 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2922
2923 ps_out_desc++;
2924 }
2925
2926 /* ----------Recon data Que Mem init --------------- */
2927 ps_rec_desc = ps_recon_data_buffs_desc;
2928 for(i = 0; i < i4_num_bitrate_inst; i++)
2929 {
2930 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2931 {
2932 iv_enc_recon_data_buffs_t **pps_recon_bufs;
2933 iv_enc_recon_data_buffs_t *ps_recon_bufs;
2934
2935 pps_recon_bufs = (iv_enc_recon_data_buffs_t **)ps_memtab->pv_base;
2936 ps_memtab++;
2937
2938 ps_recon_bufs = (iv_enc_recon_data_buffs_t *)ps_memtab->pv_base;
2939 ps_memtab++;
2940
2941 /* loop to initialise the buffer pointer */
2942 for(ctr = 0; ctr < ps_rec_desc->i4_num_recon_bufs; ctr++)
2943 {
2944 pps_recon_bufs[ctr] = &ps_recon_bufs[ctr];
2945
2946 pps_recon_bufs[ctr]->i4_size = sizeof(iv_enc_recon_data_buffs_t);
2947
2948 pps_recon_bufs[ctr]->pv_y_buf = ps_rec_desc->ppv_y_buf[ctr];
2949
2950 pps_recon_bufs[ctr]->pv_cb_buf = ps_rec_desc->ppv_u_buf[ctr];
2951
2952 pps_recon_bufs[ctr]->pv_cr_buf = ps_rec_desc->ppv_v_buf[ctr];
2953 }
2954
2955 /* Get the output data buffer Q handle */
2956 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_RECON_DATA_Q + i] = ihevce_buff_que_init(
2957 ps_memtab, ps_rec_desc->i4_num_recon_bufs, (void **)pps_recon_bufs);
2958
2959 /* increment the memtab pointer */
2960 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2961
2962 ps_rec_desc++;
2963 }
2964 else
2965 {
2966 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_RECON_DATA_Q + i] = NULL;
2967 }
2968 }
2969
2970 return;
2971 }
2972
2973 /*!
2974 ******************************************************************************
2975 * \if Function name : ihevce_mem_manager_free \endif
2976 *
2977 * \brief
2978 * Encoder memory free function
2979 *
2980 * \param[in] Processing interface context pointer
2981 *
2982 * \return
2983 * None
2984 *
2985 * \author
2986 * Ittiam
2987 *
2988 *****************************************************************************
2989 */
ihevce_mem_manager_free(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_intrf_ctxt)2990 void ihevce_mem_manager_free(enc_ctxt_t *ps_enc_ctxt, ihevce_hle_ctxt_t *ps_intrf_ctxt)
2991 {
2992 WORD32 ctr;
2993
2994 /* run a loop to free all the memory allocated create time */
2995 for(ctr = 0; ctr < ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs; ctr++)
2996 {
2997 ps_intrf_ctxt->ihevce_mem_free(
2998 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->s_mem_mngr.ps_create_memtab[ctr]);
2999 }
3000
3001 /* free the memtab memory */
3002 {
3003 iv_mem_rec_t s_memtab;
3004
3005 s_memtab.i4_size = sizeof(iv_mem_rec_t);
3006 s_memtab.i4_mem_size = ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs * sizeof(iv_mem_rec_t);
3007 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
3008 s_memtab.i4_mem_alignment = 4;
3009 s_memtab.pv_base = (void *)ps_enc_ctxt->s_mem_mngr.ps_create_memtab;
3010
3011 ps_intrf_ctxt->ihevce_mem_free(ps_intrf_ctxt->pv_mem_mgr_hdl, &s_memtab);
3012 }
3013
3014 if(1 == ps_enc_ctxt->i4_io_queues_created)
3015 {
3016 /* run a loop to free all the memory allocated durign que creation */
3017 for(ctr = 0; ctr < ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs; ctr++)
3018 {
3019 ps_intrf_ctxt->ihevce_mem_free(
3020 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->s_mem_mngr.ps_q_memtab[ctr]);
3021 }
3022
3023 /* free the memtab memory */
3024 {
3025 iv_mem_rec_t s_memtab;
3026
3027 s_memtab.i4_size = sizeof(iv_mem_rec_t);
3028 s_memtab.i4_mem_size = ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs * sizeof(iv_mem_rec_t);
3029 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
3030 s_memtab.i4_mem_alignment = 4;
3031 s_memtab.pv_base = (void *)ps_enc_ctxt->s_mem_mngr.ps_q_memtab;
3032
3033 ps_intrf_ctxt->ihevce_mem_free(ps_intrf_ctxt->pv_mem_mgr_hdl, &s_memtab);
3034 }
3035 }
3036 return;
3037 }
3038