1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 SmallVectorImpl<NearMissInfo> *NearMisses, 22 bool matchingInlineAsm, 23 unsigned VariantID = 0); 24 OperandMatchResultTy MatchOperandParserImpl( 25 OperandVector &Operands, 26 StringRef Mnemonic, 27 bool ParseForAllFeatures = false); 28 OperandMatchResultTy tryCustomParseOperand( 29 OperandVector &Operands, 30 unsigned MCK); 31 32#endif // GET_ASSEMBLER_HEADER_INFO 33 34 35#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 36#undef GET_OPERAND_DIAGNOSTIC_TYPES 37 38 Match_AlignedMemory16, 39 Match_AlignedMemory32, 40 Match_AlignedMemory64, 41 Match_AlignedMemory64or128, 42 Match_AlignedMemory64or128or256, 43 Match_AlignedMemoryNone, 44 Match_ComplexRotationEven, 45 Match_ComplexRotationOdd, 46 Match_CondCodeRestrictedFP, 47 Match_CondCodeRestrictedI, 48 Match_CondCodeRestrictedS, 49 Match_CondCodeRestrictedU, 50 Match_DPR, 51 Match_DPR_8, 52 Match_DPR_RegList, 53 Match_DPR_VFP2, 54 Match_DupAlignedMemory16, 55 Match_DupAlignedMemory32, 56 Match_DupAlignedMemory64, 57 Match_DupAlignedMemory64or128, 58 Match_DupAlignedMemoryNone, 59 Match_GPR, 60 Match_GPRnopc, 61 Match_GPRsp, 62 Match_GPRwithAPSR, 63 Match_GPRwithZR, 64 Match_GPRwithZRnosp, 65 Match_Imm0_1, 66 Match_Imm0_15, 67 Match_Imm0_239, 68 Match_Imm0_255, 69 Match_Imm0_3, 70 Match_Imm0_31, 71 Match_Imm0_32, 72 Match_Imm0_4095, 73 Match_Imm0_63, 74 Match_Imm0_65535, 75 Match_Imm0_65535Expr, 76 Match_Imm0_7, 77 Match_Imm16, 78 Match_Imm1_15, 79 Match_Imm1_31, 80 Match_Imm1_7, 81 Match_Imm24bit, 82 Match_Imm256_65535Expr, 83 Match_Imm32, 84 Match_Imm8, 85 Match_Imm8_255, 86 Match_ImmRange1_16, 87 Match_ImmRange1_32, 88 Match_ImmThumbSR, 89 Match_LELabel, 90 Match_MVELongShift, 91 Match_MVEShiftImm1_15, 92 Match_MVEShiftImm1_7, 93 Match_MVEVcvtImm16, 94 Match_MVEVcvtImm32, 95 Match_MveSaturate, 96 Match_PKHLSLImm, 97 Match_QPR, 98 Match_QPR_8, 99 Match_QPR_VFP2, 100 Match_SPR, 101 Match_SPRRegList, 102 Match_SPR_8, 103 Match_SetEndImm, 104 Match_ShrImm16, 105 Match_ShrImm32, 106 Match_ShrImm64, 107 Match_ShrImm8, 108 Match_VIDUP_imm, 109 Match_VecListFourMQ, 110 Match_VecListTwoMQ, 111 Match_WLSLabel, 112 Match_hGPR, 113 Match_rGPR, 114 Match_tGPR, 115 Match_tGPREven, 116 Match_tGPROdd, 117 END_OPERAND_DIAGNOSTIC_TYPES 118#endif // GET_OPERAND_DIAGNOSTIC_TYPES 119 120 121#ifdef GET_REGISTER_MATCHER 122#undef GET_REGISTER_MATCHER 123 124// Bits for subtarget features that participate in instruction matching. 125enum SubtargetFeatureBits : uint8_t { 126 Feature_HasV4TBit = 29, 127 Feature_HasV5TBit = 30, 128 Feature_HasV5TEBit = 31, 129 Feature_HasV6Bit = 32, 130 Feature_HasV6MBit = 34, 131 Feature_HasV8MBaselineBit = 39, 132 Feature_HasV8MMainlineBit = 40, 133 Feature_HasV8_1MMainlineBit = 41, 134 Feature_HasMVEIntBit = 23, 135 Feature_HasMVEFloatBit = 22, 136 Feature_HasFPRegsBit = 15, 137 Feature_HasFPRegs16Bit = 16, 138 Feature_HasFPRegs64Bit = 17, 139 Feature_HasFPRegsV8_1MBit = 18, 140 Feature_HasV6T2Bit = 35, 141 Feature_HasV6KBit = 33, 142 Feature_HasV7Bit = 36, 143 Feature_HasV8Bit = 38, 144 Feature_PreV8Bit = 56, 145 Feature_HasV8_1aBit = 42, 146 Feature_HasV8_2aBit = 43, 147 Feature_HasV8_3aBit = 44, 148 Feature_HasV8_4aBit = 45, 149 Feature_HasV8_5aBit = 46, 150 Feature_HasVFP2Bit = 47, 151 Feature_HasVFP3Bit = 48, 152 Feature_HasVFP4Bit = 49, 153 Feature_HasDPVFPBit = 7, 154 Feature_HasFPARMv8Bit = 14, 155 Feature_HasNEONBit = 24, 156 Feature_HasSHA2Bit = 27, 157 Feature_HasAESBit = 1, 158 Feature_HasCryptoBit = 4, 159 Feature_HasDotProdBit = 11, 160 Feature_HasCRCBit = 3, 161 Feature_HasRASBit = 25, 162 Feature_HasLOBBit = 20, 163 Feature_HasFP16Bit = 12, 164 Feature_HasFullFP16Bit = 19, 165 Feature_HasFP16FMLBit = 13, 166 Feature_HasDivideInThumbBit = 10, 167 Feature_HasDivideInARMBit = 9, 168 Feature_HasDSPBit = 8, 169 Feature_HasDBBit = 5, 170 Feature_HasDFBBit = 6, 171 Feature_HasV7ClrexBit = 37, 172 Feature_HasAcquireReleaseBit = 2, 173 Feature_HasMPBit = 21, 174 Feature_HasVirtualizationBit = 50, 175 Feature_HasTrustZoneBit = 28, 176 Feature_Has8MSecExtBit = 0, 177 Feature_IsThumbBit = 54, 178 Feature_IsThumb2Bit = 55, 179 Feature_IsMClassBit = 52, 180 Feature_IsNotMClassBit = 53, 181 Feature_IsARMBit = 51, 182 Feature_UseNaClTrapBit = 57, 183 Feature_UseNegativeImmediatesBit = 58, 184 Feature_HasSBBit = 26, 185}; 186 187static unsigned MatchRegisterName(StringRef Name) { 188 switch (Name.size()) { 189 default: break; 190 case 2: // 45 strings to match. 191 switch (Name[0]) { 192 default: break; 193 case 'd': // 10 strings to match. 194 switch (Name[1]) { 195 default: break; 196 case '0': // 1 string to match. 197 return 19; // "d0" 198 case '1': // 1 string to match. 199 return 20; // "d1" 200 case '2': // 1 string to match. 201 return 21; // "d2" 202 case '3': // 1 string to match. 203 return 22; // "d3" 204 case '4': // 1 string to match. 205 return 23; // "d4" 206 case '5': // 1 string to match. 207 return 24; // "d5" 208 case '6': // 1 string to match. 209 return 25; // "d6" 210 case '7': // 1 string to match. 211 return 26; // "d7" 212 case '8': // 1 string to match. 213 return 27; // "d8" 214 case '9': // 1 string to match. 215 return 28; // "d9" 216 } 217 break; 218 case 'l': // 1 string to match. 219 if (Name[1] != 'r') 220 break; 221 return 13; // "lr" 222 case 'p': // 2 strings to match. 223 switch (Name[1]) { 224 default: break; 225 case '0': // 1 string to match. 226 return 55; // "p0" 227 case 'c': // 1 string to match. 228 return 14; // "pc" 229 } 230 break; 231 case 'q': // 10 strings to match. 232 switch (Name[1]) { 233 default: break; 234 case '0': // 1 string to match. 235 return 56; // "q0" 236 case '1': // 1 string to match. 237 return 57; // "q1" 238 case '2': // 1 string to match. 239 return 58; // "q2" 240 case '3': // 1 string to match. 241 return 59; // "q3" 242 case '4': // 1 string to match. 243 return 60; // "q4" 244 case '5': // 1 string to match. 245 return 61; // "q5" 246 case '6': // 1 string to match. 247 return 62; // "q6" 248 case '7': // 1 string to match. 249 return 63; // "q7" 250 case '8': // 1 string to match. 251 return 64; // "q8" 252 case '9': // 1 string to match. 253 return 65; // "q9" 254 } 255 break; 256 case 'r': // 10 strings to match. 257 switch (Name[1]) { 258 default: break; 259 case '0': // 1 string to match. 260 return 72; // "r0" 261 case '1': // 1 string to match. 262 return 73; // "r1" 263 case '2': // 1 string to match. 264 return 74; // "r2" 265 case '3': // 1 string to match. 266 return 75; // "r3" 267 case '4': // 1 string to match. 268 return 76; // "r4" 269 case '5': // 1 string to match. 270 return 77; // "r5" 271 case '6': // 1 string to match. 272 return 78; // "r6" 273 case '7': // 1 string to match. 274 return 79; // "r7" 275 case '8': // 1 string to match. 276 return 80; // "r8" 277 case '9': // 1 string to match. 278 return 81; // "r9" 279 } 280 break; 281 case 's': // 11 strings to match. 282 switch (Name[1]) { 283 default: break; 284 case '0': // 1 string to match. 285 return 85; // "s0" 286 case '1': // 1 string to match. 287 return 86; // "s1" 288 case '2': // 1 string to match. 289 return 87; // "s2" 290 case '3': // 1 string to match. 291 return 88; // "s3" 292 case '4': // 1 string to match. 293 return 89; // "s4" 294 case '5': // 1 string to match. 295 return 90; // "s5" 296 case '6': // 1 string to match. 297 return 91; // "s6" 298 case '7': // 1 string to match. 299 return 92; // "s7" 300 case '8': // 1 string to match. 301 return 93; // "s8" 302 case '9': // 1 string to match. 303 return 94; // "s9" 304 case 'p': // 1 string to match. 305 return 15; // "sp" 306 } 307 break; 308 case 'z': // 1 string to match. 309 if (Name[1] != 'r') 310 break; 311 return 18; // "zr" 312 } 313 break; 314 case 3: // 54 strings to match. 315 switch (Name[0]) { 316 default: break; 317 case 'd': // 22 strings to match. 318 switch (Name[1]) { 319 default: break; 320 case '1': // 10 strings to match. 321 switch (Name[2]) { 322 default: break; 323 case '0': // 1 string to match. 324 return 29; // "d10" 325 case '1': // 1 string to match. 326 return 30; // "d11" 327 case '2': // 1 string to match. 328 return 31; // "d12" 329 case '3': // 1 string to match. 330 return 32; // "d13" 331 case '4': // 1 string to match. 332 return 33; // "d14" 333 case '5': // 1 string to match. 334 return 34; // "d15" 335 case '6': // 1 string to match. 336 return 35; // "d16" 337 case '7': // 1 string to match. 338 return 36; // "d17" 339 case '8': // 1 string to match. 340 return 37; // "d18" 341 case '9': // 1 string to match. 342 return 38; // "d19" 343 } 344 break; 345 case '2': // 10 strings to match. 346 switch (Name[2]) { 347 default: break; 348 case '0': // 1 string to match. 349 return 39; // "d20" 350 case '1': // 1 string to match. 351 return 40; // "d21" 352 case '2': // 1 string to match. 353 return 41; // "d22" 354 case '3': // 1 string to match. 355 return 42; // "d23" 356 case '4': // 1 string to match. 357 return 43; // "d24" 358 case '5': // 1 string to match. 359 return 44; // "d25" 360 case '6': // 1 string to match. 361 return 45; // "d26" 362 case '7': // 1 string to match. 363 return 46; // "d27" 364 case '8': // 1 string to match. 365 return 47; // "d28" 366 case '9': // 1 string to match. 367 return 48; // "d29" 368 } 369 break; 370 case '3': // 2 strings to match. 371 switch (Name[2]) { 372 default: break; 373 case '0': // 1 string to match. 374 return 49; // "d30" 375 case '1': // 1 string to match. 376 return 50; // "d31" 377 } 378 break; 379 } 380 break; 381 case 'q': // 6 strings to match. 382 if (Name[1] != '1') 383 break; 384 switch (Name[2]) { 385 default: break; 386 case '0': // 1 string to match. 387 return 66; // "q10" 388 case '1': // 1 string to match. 389 return 67; // "q11" 390 case '2': // 1 string to match. 391 return 68; // "q12" 392 case '3': // 1 string to match. 393 return 69; // "q13" 394 case '4': // 1 string to match. 395 return 70; // "q14" 396 case '5': // 1 string to match. 397 return 71; // "q15" 398 } 399 break; 400 case 'r': // 3 strings to match. 401 if (Name[1] != '1') 402 break; 403 switch (Name[2]) { 404 default: break; 405 case '0': // 1 string to match. 406 return 82; // "r10" 407 case '1': // 1 string to match. 408 return 83; // "r11" 409 case '2': // 1 string to match. 410 return 84; // "r12" 411 } 412 break; 413 case 's': // 22 strings to match. 414 switch (Name[1]) { 415 default: break; 416 case '1': // 10 strings to match. 417 switch (Name[2]) { 418 default: break; 419 case '0': // 1 string to match. 420 return 95; // "s10" 421 case '1': // 1 string to match. 422 return 96; // "s11" 423 case '2': // 1 string to match. 424 return 97; // "s12" 425 case '3': // 1 string to match. 426 return 98; // "s13" 427 case '4': // 1 string to match. 428 return 99; // "s14" 429 case '5': // 1 string to match. 430 return 100; // "s15" 431 case '6': // 1 string to match. 432 return 101; // "s16" 433 case '7': // 1 string to match. 434 return 102; // "s17" 435 case '8': // 1 string to match. 436 return 103; // "s18" 437 case '9': // 1 string to match. 438 return 104; // "s19" 439 } 440 break; 441 case '2': // 10 strings to match. 442 switch (Name[2]) { 443 default: break; 444 case '0': // 1 string to match. 445 return 105; // "s20" 446 case '1': // 1 string to match. 447 return 106; // "s21" 448 case '2': // 1 string to match. 449 return 107; // "s22" 450 case '3': // 1 string to match. 451 return 108; // "s23" 452 case '4': // 1 string to match. 453 return 109; // "s24" 454 case '5': // 1 string to match. 455 return 110; // "s25" 456 case '6': // 1 string to match. 457 return 111; // "s26" 458 case '7': // 1 string to match. 459 return 112; // "s27" 460 case '8': // 1 string to match. 461 return 113; // "s28" 462 case '9': // 1 string to match. 463 return 114; // "s29" 464 } 465 break; 466 case '3': // 2 strings to match. 467 switch (Name[2]) { 468 default: break; 469 case '0': // 1 string to match. 470 return 115; // "s30" 471 case '1': // 1 string to match. 472 return 116; // "s31" 473 } 474 break; 475 } 476 break; 477 case 'v': // 1 string to match. 478 if (memcmp(Name.data()+1, "pr", 2) != 0) 479 break; 480 return 17; // "vpr" 481 } 482 break; 483 case 4: // 3 strings to match. 484 switch (Name[0]) { 485 default: break; 486 case 'a': // 1 string to match. 487 if (memcmp(Name.data()+1, "psr", 3) != 0) 488 break; 489 return 1; // "apsr" 490 case 'c': // 1 string to match. 491 if (memcmp(Name.data()+1, "psr", 3) != 0) 492 break; 493 return 3; // "cpsr" 494 case 's': // 1 string to match. 495 if (memcmp(Name.data()+1, "psr", 3) != 0) 496 break; 497 return 16; // "spsr" 498 } 499 break; 500 case 5: // 6 strings to match. 501 switch (Name[0]) { 502 default: break; 503 case 'f': // 3 strings to match. 504 if (Name[1] != 'p') 505 break; 506 switch (Name[2]) { 507 default: break; 508 case 'e': // 1 string to match. 509 if (memcmp(Name.data()+3, "xc", 2) != 0) 510 break; 511 return 6; // "fpexc" 512 case 's': // 2 strings to match. 513 switch (Name[3]) { 514 default: break; 515 case 'c': // 1 string to match. 516 if (Name[4] != 'r') 517 break; 518 return 8; // "fpscr" 519 case 'i': // 1 string to match. 520 if (Name[4] != 'd') 521 break; 522 return 11; // "fpsid" 523 } 524 break; 525 } 526 break; 527 case 'm': // 3 strings to match. 528 if (memcmp(Name.data()+1, "vfr", 3) != 0) 529 break; 530 switch (Name[4]) { 531 default: break; 532 case '0': // 1 string to match. 533 return 52; // "mvfr0" 534 case '1': // 1 string to match. 535 return 53; // "mvfr1" 536 case '2': // 1 string to match. 537 return 54; // "mvfr2" 538 } 539 break; 540 } 541 break; 542 case 6: // 2 strings to match. 543 if (memcmp(Name.data()+0, "fp", 2) != 0) 544 break; 545 switch (Name[2]) { 546 default: break; 547 case 'c': // 1 string to match. 548 if (memcmp(Name.data()+3, "xts", 3) != 0) 549 break; 550 return 5; // "fpcxts" 551 case 'i': // 1 string to match. 552 if (memcmp(Name.data()+3, "nst", 3) != 0) 553 break; 554 return 7; // "fpinst" 555 } 556 break; 557 case 7: // 3 strings to match. 558 switch (Name[0]) { 559 default: break; 560 case 'f': // 2 strings to match. 561 if (Name[1] != 'p') 562 break; 563 switch (Name[2]) { 564 default: break; 565 case 'c': // 1 string to match. 566 if (memcmp(Name.data()+3, "xtns", 4) != 0) 567 break; 568 return 4; // "fpcxtns" 569 case 'i': // 1 string to match. 570 if (memcmp(Name.data()+3, "nst2", 4) != 0) 571 break; 572 return 51; // "fpinst2" 573 } 574 break; 575 case 'i': // 1 string to match. 576 if (memcmp(Name.data()+1, "tstate", 6) != 0) 577 break; 578 return 12; // "itstate" 579 } 580 break; 581 case 9: // 1 string to match. 582 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0) 583 break; 584 return 2; // "apsr_nzcv" 585 case 10: // 1 string to match. 586 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0) 587 break; 588 return 9; // "fpscr_nzcv" 589 case 12: // 1 string to match. 590 if (memcmp(Name.data()+0, "fpscr_nzcvqc", 12) != 0) 591 break; 592 return 10; // "fpscr_nzcvqc" 593 } 594 return 0; 595} 596 597#endif // GET_REGISTER_MATCHER 598 599 600#ifdef GET_SUBTARGET_FEATURE_NAME 601#undef GET_SUBTARGET_FEATURE_NAME 602 603// User-level names for subtarget features that participate in 604// instruction matching. 605static const char *getSubtargetFeatureName(uint64_t Val) { 606 switch(Val) { 607 case Feature_HasV4TBit: return "armv4t"; 608 case Feature_HasV5TBit: return "armv5t"; 609 case Feature_HasV5TEBit: return "armv5te"; 610 case Feature_HasV6Bit: return "armv6"; 611 case Feature_HasV6MBit: return "armv6m or armv6t2"; 612 case Feature_HasV8MBaselineBit: return "armv8m.base"; 613 case Feature_HasV8MMainlineBit: return "armv8m.main"; 614 case Feature_HasV8_1MMainlineBit: return "armv8.1m.main"; 615 case Feature_HasMVEIntBit: return "mve"; 616 case Feature_HasMVEFloatBit: return "mve.fp"; 617 case Feature_HasFPRegsBit: return "fp registers"; 618 case Feature_HasFPRegs16Bit: return "16-bit fp registers"; 619 case Feature_HasFPRegs64Bit: return "64-bit fp registers"; 620 case Feature_HasFPRegsV8_1MBit: return "armv8.1m.main with FP or MVE"; 621 case Feature_HasV6T2Bit: return "armv6t2"; 622 case Feature_HasV6KBit: return "armv6k"; 623 case Feature_HasV7Bit: return "armv7"; 624 case Feature_HasV8Bit: return "armv8"; 625 case Feature_PreV8Bit: return "armv7 or earlier"; 626 case Feature_HasV8_1aBit: return "armv8.1a"; 627 case Feature_HasV8_2aBit: return "armv8.2a"; 628 case Feature_HasV8_3aBit: return "armv8.3a"; 629 case Feature_HasV8_4aBit: return "armv8.4a"; 630 case Feature_HasV8_5aBit: return "armv8.5a"; 631 case Feature_HasVFP2Bit: return "VFP2"; 632 case Feature_HasVFP3Bit: return "VFP3"; 633 case Feature_HasVFP4Bit: return "VFP4"; 634 case Feature_HasDPVFPBit: return "double precision VFP"; 635 case Feature_HasFPARMv8Bit: return "FPARMv8"; 636 case Feature_HasNEONBit: return "NEON"; 637 case Feature_HasSHA2Bit: return "sha2"; 638 case Feature_HasAESBit: return "aes"; 639 case Feature_HasCryptoBit: return "crypto"; 640 case Feature_HasDotProdBit: return "dotprod"; 641 case Feature_HasCRCBit: return "crc"; 642 case Feature_HasRASBit: return "ras"; 643 case Feature_HasLOBBit: return "lob"; 644 case Feature_HasFP16Bit: return "half-float conversions"; 645 case Feature_HasFullFP16Bit: return "full half-float"; 646 case Feature_HasFP16FMLBit: return "full half-float fml"; 647 case Feature_HasDivideInThumbBit: return "divide in THUMB"; 648 case Feature_HasDivideInARMBit: return "divide in ARM"; 649 case Feature_HasDSPBit: return "dsp"; 650 case Feature_HasDBBit: return "data-barriers"; 651 case Feature_HasDFBBit: return "full-data-barrier"; 652 case Feature_HasV7ClrexBit: return "v7 clrex"; 653 case Feature_HasAcquireReleaseBit: return "acquire/release"; 654 case Feature_HasMPBit: return "mp-extensions"; 655 case Feature_HasVirtualizationBit: return "virtualization-extensions"; 656 case Feature_HasTrustZoneBit: return "TrustZone"; 657 case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions"; 658 case Feature_IsThumbBit: return "thumb"; 659 case Feature_IsThumb2Bit: return "thumb2"; 660 case Feature_IsMClassBit: return "armv*m"; 661 case Feature_IsNotMClassBit: return "!armv*m"; 662 case Feature_IsARMBit: return "arm-mode"; 663 case Feature_UseNaClTrapBit: return "NaCl"; 664 case Feature_UseNegativeImmediatesBit: return "NegativeImmediates"; 665 case Feature_HasSBBit: return "sb"; 666 default: return "(unknown)"; 667 } 668} 669 670#endif // GET_SUBTARGET_FEATURE_NAME 671 672 673#ifdef GET_MATCHER_IMPLEMENTATION 674#undef GET_MATCHER_IMPLEMENTATION 675 676static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { 677 switch (VariantID) { 678 case 0: 679 break; 680 } 681 switch (Mnemonic.size()) { 682 default: break; 683 case 3: // 4 strings to match. 684 switch (Mnemonic[0]) { 685 default: break; 686 case 'r': // 1 string to match. 687 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 688 break; 689 Mnemonic = "rfeia"; // "rfe" 690 return; 691 case 's': // 3 strings to match. 692 switch (Mnemonic[1]) { 693 default: break; 694 case 'm': // 1 string to match. 695 if (Mnemonic[2] != 'i') 696 break; 697 Mnemonic = "smc"; // "smi" 698 return; 699 case 'r': // 1 string to match. 700 if (Mnemonic[2] != 's') 701 break; 702 Mnemonic = "srsia"; // "srs" 703 return; 704 case 'w': // 1 string to match. 705 if (Mnemonic[2] != 'i') 706 break; 707 Mnemonic = "svc"; // "swi" 708 return; 709 } 710 break; 711 } 712 break; 713 case 4: // 10 strings to match. 714 switch (Mnemonic[0]) { 715 default: break; 716 case 'f': // 8 strings to match. 717 switch (Mnemonic[1]) { 718 default: break; 719 case 'l': // 2 strings to match. 720 if (Mnemonic[2] != 'd') 721 break; 722 switch (Mnemonic[3]) { 723 default: break; 724 case 'd': // 1 string to match. 725 if (Features.test(Feature_HasVFP2Bit)) // "fldd" 726 Mnemonic = "vldr"; 727 return; 728 case 's': // 1 string to match. 729 if (Features.test(Feature_HasVFP2Bit)) // "flds" 730 Mnemonic = "vldr"; 731 return; 732 } 733 break; 734 case 'm': // 4 strings to match. 735 switch (Mnemonic[2]) { 736 default: break; 737 case 'r': // 2 strings to match. 738 switch (Mnemonic[3]) { 739 default: break; 740 case 's': // 1 string to match. 741 if (Features.test(Feature_HasVFP2Bit)) // "fmrs" 742 Mnemonic = "vmov"; 743 return; 744 case 'x': // 1 string to match. 745 if (Features.test(Feature_HasVFP2Bit)) // "fmrx" 746 Mnemonic = "vmrs"; 747 return; 748 } 749 break; 750 case 's': // 1 string to match. 751 if (Mnemonic[3] != 'r') 752 break; 753 if (Features.test(Feature_HasVFP2Bit)) // "fmsr" 754 Mnemonic = "vmov"; 755 return; 756 case 'x': // 1 string to match. 757 if (Mnemonic[3] != 'r') 758 break; 759 if (Features.test(Feature_HasVFP2Bit)) // "fmxr" 760 Mnemonic = "vmsr"; 761 return; 762 } 763 break; 764 case 's': // 2 strings to match. 765 if (Mnemonic[2] != 't') 766 break; 767 switch (Mnemonic[3]) { 768 default: break; 769 case 'd': // 1 string to match. 770 if (Features.test(Feature_HasVFP2Bit)) // "fstd" 771 Mnemonic = "vstr"; 772 return; 773 case 's': // 1 string to match. 774 if (Features.test(Feature_HasVFP2Bit)) // "fsts" 775 Mnemonic = "vstr"; 776 return; 777 } 778 break; 779 } 780 break; 781 case 'v': // 2 strings to match. 782 switch (Mnemonic[1]) { 783 default: break; 784 case 'l': // 1 string to match. 785 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 786 break; 787 Mnemonic = "vldmia"; // "vldm" 788 return; 789 case 's': // 1 string to match. 790 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 791 break; 792 Mnemonic = "vstmia"; // "vstm" 793 return; 794 } 795 break; 796 } 797 break; 798 case 5: // 51 strings to match. 799 switch (Mnemonic[0]) { 800 default: break; 801 case 'f': // 18 strings to match. 802 switch (Mnemonic[1]) { 803 default: break; 804 case 'a': // 2 strings to match. 805 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0) 806 break; 807 switch (Mnemonic[4]) { 808 default: break; 809 case 'd': // 1 string to match. 810 if (Features.test(Feature_HasVFP2Bit)) // "faddd" 811 Mnemonic = "vadd.f64"; 812 return; 813 case 's': // 1 string to match. 814 if (Features.test(Feature_HasVFP2Bit)) // "fadds" 815 Mnemonic = "vadd.f32"; 816 return; 817 } 818 break; 819 case 'c': // 4 strings to match. 820 switch (Mnemonic[2]) { 821 default: break; 822 case 'm': // 2 strings to match. 823 if (Mnemonic[3] != 'p') 824 break; 825 switch (Mnemonic[4]) { 826 default: break; 827 case 'd': // 1 string to match. 828 if (Features.test(Feature_HasVFP2Bit)) // "fcmpd" 829 Mnemonic = "vcmp.f64"; 830 return; 831 case 's': // 1 string to match. 832 if (Features.test(Feature_HasVFP2Bit)) // "fcmps" 833 Mnemonic = "vcmp.f32"; 834 return; 835 } 836 break; 837 case 'p': // 2 strings to match. 838 if (Mnemonic[3] != 'y') 839 break; 840 switch (Mnemonic[4]) { 841 default: break; 842 case 'd': // 1 string to match. 843 if (Features.test(Feature_HasVFP2Bit)) // "fcpyd" 844 Mnemonic = "vmov.f64"; 845 return; 846 case 's': // 1 string to match. 847 if (Features.test(Feature_HasVFP2Bit)) // "fcpys" 848 Mnemonic = "vmov.f32"; 849 return; 850 } 851 break; 852 } 853 break; 854 case 'd': // 2 strings to match. 855 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0) 856 break; 857 switch (Mnemonic[4]) { 858 default: break; 859 case 'd': // 1 string to match. 860 if (Features.test(Feature_HasVFP2Bit)) // "fdivd" 861 Mnemonic = "vdiv.f64"; 862 return; 863 case 's': // 1 string to match. 864 if (Features.test(Feature_HasVFP2Bit)) // "fdivs" 865 Mnemonic = "vdiv.f32"; 866 return; 867 } 868 break; 869 case 'm': // 8 strings to match. 870 switch (Mnemonic[2]) { 871 default: break; 872 case 'a': // 2 strings to match. 873 if (Mnemonic[3] != 'c') 874 break; 875 switch (Mnemonic[4]) { 876 default: break; 877 case 'd': // 1 string to match. 878 if (Features.test(Feature_HasVFP2Bit)) // "fmacd" 879 Mnemonic = "vmla.f64"; 880 return; 881 case 's': // 1 string to match. 882 if (Features.test(Feature_HasVFP2Bit)) // "fmacs" 883 Mnemonic = "vmla.f32"; 884 return; 885 } 886 break; 887 case 'd': // 1 string to match. 888 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0) 889 break; 890 if (Features.test(Feature_HasVFP2Bit)) // "fmdrr" 891 Mnemonic = "vmov"; 892 return; 893 case 'r': // 3 strings to match. 894 switch (Mnemonic[3]) { 895 default: break; 896 case 'd': // 2 strings to match. 897 switch (Mnemonic[4]) { 898 default: break; 899 case 'd': // 1 string to match. 900 if (Features.test(Feature_HasVFP2Bit)) // "fmrdd" 901 Mnemonic = "vmov"; 902 return; 903 case 's': // 1 string to match. 904 if (Features.test(Feature_HasVFP2Bit)) // "fmrds" 905 Mnemonic = "vmov"; 906 return; 907 } 908 break; 909 case 'r': // 1 string to match. 910 if (Mnemonic[4] != 'd') 911 break; 912 if (Features.test(Feature_HasVFP2Bit)) // "fmrrd" 913 Mnemonic = "vmov"; 914 return; 915 } 916 break; 917 case 'u': // 2 strings to match. 918 if (Mnemonic[3] != 'l') 919 break; 920 switch (Mnemonic[4]) { 921 default: break; 922 case 'd': // 1 string to match. 923 if (Features.test(Feature_HasVFP2Bit)) // "fmuld" 924 Mnemonic = "vmul.f64"; 925 return; 926 case 's': // 1 string to match. 927 if (Features.test(Feature_HasVFP2Bit)) // "fmuls" 928 Mnemonic = "vmul.f32"; 929 return; 930 } 931 break; 932 } 933 break; 934 case 'n': // 2 strings to match. 935 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0) 936 break; 937 switch (Mnemonic[4]) { 938 default: break; 939 case 'd': // 1 string to match. 940 if (Features.test(Feature_HasVFP2Bit)) // "fnegd" 941 Mnemonic = "vneg.f64"; 942 return; 943 case 's': // 1 string to match. 944 if (Features.test(Feature_HasVFP2Bit)) // "fnegs" 945 Mnemonic = "vneg.f32"; 946 return; 947 } 948 break; 949 } 950 break; 951 case 'l': // 3 strings to match. 952 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0) 953 break; 954 switch (Mnemonic[3]) { 955 default: break; 956 case 'e': // 1 string to match. 957 if (Mnemonic[4] != 'a') 958 break; 959 Mnemonic = "ldmdb"; // "ldmea" 960 return; 961 case 'f': // 1 string to match. 962 if (Mnemonic[4] != 'd') 963 break; 964 Mnemonic = "ldm"; // "ldmfd" 965 return; 966 case 'i': // 1 string to match. 967 if (Mnemonic[4] != 'a') 968 break; 969 Mnemonic = "ldm"; // "ldmia" 970 return; 971 } 972 break; 973 case 'r': // 4 strings to match. 974 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 975 break; 976 switch (Mnemonic[3]) { 977 default: break; 978 case 'e': // 2 strings to match. 979 switch (Mnemonic[4]) { 980 default: break; 981 case 'a': // 1 string to match. 982 Mnemonic = "rfedb"; // "rfeea" 983 return; 984 case 'd': // 1 string to match. 985 Mnemonic = "rfeib"; // "rfeed" 986 return; 987 } 988 break; 989 case 'f': // 2 strings to match. 990 switch (Mnemonic[4]) { 991 default: break; 992 case 'a': // 1 string to match. 993 Mnemonic = "rfeda"; // "rfefa" 994 return; 995 case 'd': // 1 string to match. 996 Mnemonic = "rfeia"; // "rfefd" 997 return; 998 } 999 break; 1000 } 1001 break; 1002 case 's': // 7 strings to match. 1003 switch (Mnemonic[1]) { 1004 default: break; 1005 case 'r': // 4 strings to match. 1006 if (Mnemonic[2] != 's') 1007 break; 1008 switch (Mnemonic[3]) { 1009 default: break; 1010 case 'e': // 2 strings to match. 1011 switch (Mnemonic[4]) { 1012 default: break; 1013 case 'a': // 1 string to match. 1014 Mnemonic = "srsia"; // "srsea" 1015 return; 1016 case 'd': // 1 string to match. 1017 Mnemonic = "srsda"; // "srsed" 1018 return; 1019 } 1020 break; 1021 case 'f': // 2 strings to match. 1022 switch (Mnemonic[4]) { 1023 default: break; 1024 case 'a': // 1 string to match. 1025 Mnemonic = "srsib"; // "srsfa" 1026 return; 1027 case 'd': // 1 string to match. 1028 Mnemonic = "srsdb"; // "srsfd" 1029 return; 1030 } 1031 break; 1032 } 1033 break; 1034 case 't': // 3 strings to match. 1035 if (Mnemonic[2] != 'm') 1036 break; 1037 switch (Mnemonic[3]) { 1038 default: break; 1039 case 'e': // 1 string to match. 1040 if (Mnemonic[4] != 'a') 1041 break; 1042 Mnemonic = "stm"; // "stmea" 1043 return; 1044 case 'f': // 1 string to match. 1045 if (Mnemonic[4] != 'd') 1046 break; 1047 Mnemonic = "stmdb"; // "stmfd" 1048 return; 1049 case 'i': // 1 string to match. 1050 if (Mnemonic[4] != 'a') 1051 break; 1052 Mnemonic = "stm"; // "stmia" 1053 return; 1054 } 1055 break; 1056 } 1057 break; 1058 case 'v': // 19 strings to match. 1059 switch (Mnemonic[1]) { 1060 default: break; 1061 case 'a': // 3 strings to match. 1062 switch (Mnemonic[2]) { 1063 default: break; 1064 case 'b': // 1 string to match. 1065 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0) 1066 break; 1067 if (Features.test(Feature_HasNEONBit)) // "vabsq" 1068 Mnemonic = "vabs"; 1069 return; 1070 case 'd': // 1 string to match. 1071 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 1072 break; 1073 if (Features.test(Feature_HasNEONBit)) // "vaddq" 1074 Mnemonic = "vadd"; 1075 return; 1076 case 'n': // 1 string to match. 1077 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 1078 break; 1079 if (Features.test(Feature_HasNEONBit)) // "vandq" 1080 Mnemonic = "vand"; 1081 return; 1082 } 1083 break; 1084 case 'b': // 1 string to match. 1085 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0) 1086 break; 1087 if (Features.test(Feature_HasNEONBit)) // "vbicq" 1088 Mnemonic = "vbic"; 1089 return; 1090 case 'c': // 3 strings to match. 1091 switch (Mnemonic[2]) { 1092 default: break; 1093 case 'e': // 1 string to match. 1094 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0) 1095 break; 1096 if (Features.test(Feature_HasNEONBit)) // "vceqq" 1097 Mnemonic = "vceq"; 1098 return; 1099 case 'l': // 1 string to match. 1100 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0) 1101 break; 1102 if (Features.test(Feature_HasNEONBit)) // "vcleq" 1103 Mnemonic = "vcle"; 1104 return; 1105 case 'v': // 1 string to match. 1106 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0) 1107 break; 1108 if (Features.test(Feature_HasNEONBit)) // "vcvtq" 1109 Mnemonic = "vcvt"; 1110 return; 1111 } 1112 break; 1113 case 'e': // 1 string to match. 1114 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0) 1115 break; 1116 if (Features.test(Feature_HasNEONBit)) // "veorq" 1117 Mnemonic = "veor"; 1118 return; 1119 case 'm': // 5 strings to match. 1120 switch (Mnemonic[2]) { 1121 default: break; 1122 case 'a': // 1 string to match. 1123 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0) 1124 break; 1125 if (Features.test(Feature_HasNEONBit)) // "vmaxq" 1126 Mnemonic = "vmax"; 1127 return; 1128 case 'i': // 1 string to match. 1129 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1130 break; 1131 if (Features.test(Feature_HasNEONBit)) // "vminq" 1132 Mnemonic = "vmin"; 1133 return; 1134 case 'o': // 1 string to match. 1135 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0) 1136 break; 1137 if (Features.test(Feature_HasNEONBit)) // "vmovq" 1138 Mnemonic = "vmov"; 1139 return; 1140 case 'u': // 1 string to match. 1141 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0) 1142 break; 1143 if (Features.test(Feature_HasNEONBit)) // "vmulq" 1144 Mnemonic = "vmul"; 1145 return; 1146 case 'v': // 1 string to match. 1147 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1148 break; 1149 if (Features.test(Feature_HasNEONBit)) // "vmvnq" 1150 Mnemonic = "vmvn"; 1151 return; 1152 } 1153 break; 1154 case 'o': // 1 string to match. 1155 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0) 1156 break; 1157 if (Features.test(Feature_HasNEONBit)) // "vorrq" 1158 Mnemonic = "vorr"; 1159 return; 1160 case 's': // 4 strings to match. 1161 switch (Mnemonic[2]) { 1162 default: break; 1163 case 'h': // 2 strings to match. 1164 switch (Mnemonic[3]) { 1165 default: break; 1166 case 'l': // 1 string to match. 1167 if (Mnemonic[4] != 'q') 1168 break; 1169 if (Features.test(Feature_HasNEONBit)) // "vshlq" 1170 Mnemonic = "vshl"; 1171 return; 1172 case 'r': // 1 string to match. 1173 if (Mnemonic[4] != 'q') 1174 break; 1175 if (Features.test(Feature_HasNEONBit)) // "vshrq" 1176 Mnemonic = "vshr"; 1177 return; 1178 } 1179 break; 1180 case 'u': // 1 string to match. 1181 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0) 1182 break; 1183 if (Features.test(Feature_HasNEONBit)) // "vsubq" 1184 Mnemonic = "vsub"; 1185 return; 1186 case 'w': // 1 string to match. 1187 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0) 1188 break; 1189 if (Features.test(Feature_HasNEONBit)) // "vswpq" 1190 Mnemonic = "vswp"; 1191 return; 1192 } 1193 break; 1194 case 'z': // 1 string to match. 1195 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0) 1196 break; 1197 if (Features.test(Feature_HasNEONBit)) // "vzipq" 1198 Mnemonic = "vzip"; 1199 return; 1200 } 1201 break; 1202 } 1203 break; 1204 case 6: // 10 strings to match. 1205 if (Mnemonic[0] != 'f') 1206 break; 1207 switch (Mnemonic[1]) { 1208 default: break; 1209 case 's': // 4 strings to match. 1210 switch (Mnemonic[2]) { 1211 default: break; 1212 case 'i': // 2 strings to match. 1213 if (memcmp(Mnemonic.data()+3, "to", 2) != 0) 1214 break; 1215 switch (Mnemonic[5]) { 1216 default: break; 1217 case 'd': // 1 string to match. 1218 if (Features.test(Feature_HasVFP2Bit)) // "fsitod" 1219 Mnemonic = "vcvt.f64.s32"; 1220 return; 1221 case 's': // 1 string to match. 1222 if (Features.test(Feature_HasVFP2Bit)) // "fsitos" 1223 Mnemonic = "vcvt.f32.s32"; 1224 return; 1225 } 1226 break; 1227 case 'q': // 2 strings to match. 1228 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0) 1229 break; 1230 switch (Mnemonic[5]) { 1231 default: break; 1232 case 'd': // 1 string to match. 1233 if (Features.test(Feature_HasVFP2Bit)) // "fsqrtd" 1234 Mnemonic = "vsqrt"; 1235 return; 1236 case 's': // 1 string to match. 1237 if (Features.test(Feature_HasVFP2Bit)) // "fsqrts" 1238 Mnemonic = "vsqrt"; 1239 return; 1240 } 1241 break; 1242 } 1243 break; 1244 case 't': // 4 strings to match. 1245 if (Mnemonic[2] != 'o') 1246 break; 1247 switch (Mnemonic[3]) { 1248 default: break; 1249 case 's': // 2 strings to match. 1250 if (Mnemonic[4] != 'i') 1251 break; 1252 switch (Mnemonic[5]) { 1253 default: break; 1254 case 'd': // 1 string to match. 1255 if (Features.test(Feature_HasVFP2Bit)) // "ftosid" 1256 Mnemonic = "vcvtr.s32.f64"; 1257 return; 1258 case 's': // 1 string to match. 1259 if (Features.test(Feature_HasVFP2Bit)) // "ftosis" 1260 Mnemonic = "vcvtr.s32.f32"; 1261 return; 1262 } 1263 break; 1264 case 'u': // 2 strings to match. 1265 if (Mnemonic[4] != 'i') 1266 break; 1267 switch (Mnemonic[5]) { 1268 default: break; 1269 case 'd': // 1 string to match. 1270 if (Features.test(Feature_HasVFP2Bit)) // "ftouid" 1271 Mnemonic = "vcvtr.u32.f64"; 1272 return; 1273 case 's': // 1 string to match. 1274 if (Features.test(Feature_HasVFP2Bit)) // "ftouis" 1275 Mnemonic = "vcvtr.u32.f32"; 1276 return; 1277 } 1278 break; 1279 } 1280 break; 1281 case 'u': // 2 strings to match. 1282 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0) 1283 break; 1284 switch (Mnemonic[5]) { 1285 default: break; 1286 case 'd': // 1 string to match. 1287 if (Features.test(Feature_HasVFP2Bit)) // "fuitod" 1288 Mnemonic = "vcvt.f64.u32"; 1289 return; 1290 case 's': // 1 string to match. 1291 if (Features.test(Feature_HasVFP2Bit)) // "fuitos" 1292 Mnemonic = "vcvt.f32.u32"; 1293 return; 1294 } 1295 break; 1296 } 1297 break; 1298 case 7: // 9 strings to match. 1299 switch (Mnemonic[0]) { 1300 default: break; 1301 case 'f': // 8 strings to match. 1302 switch (Mnemonic[1]) { 1303 default: break; 1304 case 'l': // 2 strings to match. 1305 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 1306 break; 1307 switch (Mnemonic[4]) { 1308 default: break; 1309 case 'e': // 1 string to match. 1310 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1311 break; 1312 if (Features.test(Feature_HasVFP2Bit)) // "fldmeax" 1313 Mnemonic = "fldmdbx"; 1314 return; 1315 case 'f': // 1 string to match. 1316 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1317 break; 1318 if (Features.test(Feature_HasVFP2Bit)) // "fldmfdx" 1319 Mnemonic = "fldmiax"; 1320 return; 1321 } 1322 break; 1323 case 's': // 2 strings to match. 1324 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 1325 break; 1326 switch (Mnemonic[4]) { 1327 default: break; 1328 case 'e': // 1 string to match. 1329 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1330 break; 1331 if (Features.test(Feature_HasVFP2Bit)) // "fstmeax" 1332 Mnemonic = "fstmiax"; 1333 return; 1334 case 'f': // 1 string to match. 1335 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1336 break; 1337 if (Features.test(Feature_HasVFP2Bit)) // "fstmfdx" 1338 Mnemonic = "fstmdbx"; 1339 return; 1340 } 1341 break; 1342 case 't': // 4 strings to match. 1343 if (Mnemonic[2] != 'o') 1344 break; 1345 switch (Mnemonic[3]) { 1346 default: break; 1347 case 's': // 2 strings to match. 1348 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1349 break; 1350 switch (Mnemonic[6]) { 1351 default: break; 1352 case 'd': // 1 string to match. 1353 if (Features.test(Feature_HasVFP2Bit)) // "ftosizd" 1354 Mnemonic = "vcvt.s32.f64"; 1355 return; 1356 case 's': // 1 string to match. 1357 if (Features.test(Feature_HasVFP2Bit)) // "ftosizs" 1358 Mnemonic = "vcvt.s32.f32"; 1359 return; 1360 } 1361 break; 1362 case 'u': // 2 strings to match. 1363 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1364 break; 1365 switch (Mnemonic[6]) { 1366 default: break; 1367 case 'd': // 1 string to match. 1368 if (Features.test(Feature_HasVFP2Bit)) // "ftouizd" 1369 Mnemonic = "vcvt.u32.f64"; 1370 return; 1371 case 's': // 1 string to match. 1372 if (Features.test(Feature_HasVFP2Bit)) // "ftouizs" 1373 Mnemonic = "vcvt.u32.f32"; 1374 return; 1375 } 1376 break; 1377 } 1378 break; 1379 } 1380 break; 1381 case 'v': // 1 string to match. 1382 if (memcmp(Mnemonic.data()+1, "ldrb.8", 6) != 0) 1383 break; 1384 Mnemonic = "vldrb.u8"; // "vldrb.8" 1385 return; 1386 } 1387 break; 1388 case 8: // 13 strings to match. 1389 switch (Mnemonic[0]) { 1390 default: break; 1391 case 'q': // 1 string to match. 1392 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0) 1393 break; 1394 Mnemonic = "qsax"; // "qsubaddx" 1395 return; 1396 case 's': // 2 strings to match. 1397 switch (Mnemonic[1]) { 1398 default: break; 1399 case 'a': // 1 string to match. 1400 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1401 break; 1402 Mnemonic = "sasx"; // "saddsubx" 1403 return; 1404 case 's': // 1 string to match. 1405 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1406 break; 1407 Mnemonic = "ssax"; // "ssubaddx" 1408 return; 1409 } 1410 break; 1411 case 'u': // 2 strings to match. 1412 switch (Mnemonic[1]) { 1413 default: break; 1414 case 'a': // 1 string to match. 1415 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1416 break; 1417 Mnemonic = "uasx"; // "uaddsubx" 1418 return; 1419 case 's': // 1 string to match. 1420 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1421 break; 1422 Mnemonic = "usax"; // "usubaddx" 1423 return; 1424 } 1425 break; 1426 case 'v': // 8 strings to match. 1427 switch (Mnemonic[1]) { 1428 default: break; 1429 case 'l': // 6 strings to match. 1430 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1431 break; 1432 switch (Mnemonic[4]) { 1433 default: break; 1434 case 'b': // 3 strings to match. 1435 switch (Mnemonic[5]) { 1436 default: break; 1437 case '.': // 1 string to match. 1438 if (memcmp(Mnemonic.data()+6, "s8", 2) != 0) 1439 break; 1440 Mnemonic = "vldrb.u8"; // "vldrb.s8" 1441 return; 1442 case 'e': // 1 string to match. 1443 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0) 1444 break; 1445 Mnemonic = "vldrbe.u8"; // "vldrbe.8" 1446 return; 1447 case 't': // 1 string to match. 1448 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0) 1449 break; 1450 Mnemonic = "vldrbt.u8"; // "vldrbt.8" 1451 return; 1452 } 1453 break; 1454 case 'd': // 1 string to match. 1455 if (memcmp(Mnemonic.data()+5, ".64", 3) != 0) 1456 break; 1457 Mnemonic = "vldrd.u64"; // "vldrd.64" 1458 return; 1459 case 'h': // 1 string to match. 1460 if (memcmp(Mnemonic.data()+5, ".16", 3) != 0) 1461 break; 1462 Mnemonic = "vldrh.u16"; // "vldrh.16" 1463 return; 1464 case 'w': // 1 string to match. 1465 if (memcmp(Mnemonic.data()+5, ".32", 3) != 0) 1466 break; 1467 Mnemonic = "vldrw.u32"; // "vldrw.32" 1468 return; 1469 } 1470 break; 1471 case 's': // 2 strings to match. 1472 if (memcmp(Mnemonic.data()+2, "trb.", 4) != 0) 1473 break; 1474 switch (Mnemonic[6]) { 1475 default: break; 1476 case 's': // 1 string to match. 1477 if (Mnemonic[7] != '8') 1478 break; 1479 Mnemonic = "vstrb.8"; // "vstrb.s8" 1480 return; 1481 case 'u': // 1 string to match. 1482 if (Mnemonic[7] != '8') 1483 break; 1484 Mnemonic = "vstrb.8"; // "vstrb.u8" 1485 return; 1486 } 1487 break; 1488 } 1489 break; 1490 } 1491 break; 1492 case 9: // 35 strings to match. 1493 switch (Mnemonic[0]) { 1494 default: break; 1495 case 's': // 2 strings to match. 1496 if (Mnemonic[1] != 'h') 1497 break; 1498 switch (Mnemonic[2]) { 1499 default: break; 1500 case 'a': // 1 string to match. 1501 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1502 break; 1503 Mnemonic = "shasx"; // "shaddsubx" 1504 return; 1505 case 's': // 1 string to match. 1506 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1507 break; 1508 Mnemonic = "shsax"; // "shsubaddx" 1509 return; 1510 } 1511 break; 1512 case 'u': // 4 strings to match. 1513 switch (Mnemonic[1]) { 1514 default: break; 1515 case 'h': // 2 strings to match. 1516 switch (Mnemonic[2]) { 1517 default: break; 1518 case 'a': // 1 string to match. 1519 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1520 break; 1521 Mnemonic = "uhasx"; // "uhaddsubx" 1522 return; 1523 case 's': // 1 string to match. 1524 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1525 break; 1526 Mnemonic = "uhsax"; // "uhsubaddx" 1527 return; 1528 } 1529 break; 1530 case 'q': // 2 strings to match. 1531 switch (Mnemonic[2]) { 1532 default: break; 1533 case 'a': // 1 string to match. 1534 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1535 break; 1536 Mnemonic = "uqasx"; // "uqaddsubx" 1537 return; 1538 case 's': // 1 string to match. 1539 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1540 break; 1541 Mnemonic = "uqsax"; // "uqsubaddx" 1542 return; 1543 } 1544 break; 1545 } 1546 break; 1547 case 'v': // 29 strings to match. 1548 switch (Mnemonic[1]) { 1549 default: break; 1550 case 'l': // 14 strings to match. 1551 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1552 break; 1553 switch (Mnemonic[4]) { 1554 default: break; 1555 case 'b': // 2 strings to match. 1556 switch (Mnemonic[5]) { 1557 default: break; 1558 case 'e': // 1 string to match. 1559 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0) 1560 break; 1561 Mnemonic = "vldrbe.u8"; // "vldrbe.s8" 1562 return; 1563 case 't': // 1 string to match. 1564 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0) 1565 break; 1566 Mnemonic = "vldrbt.u8"; // "vldrbt.s8" 1567 return; 1568 } 1569 break; 1570 case 'd': // 4 strings to match. 1571 switch (Mnemonic[5]) { 1572 default: break; 1573 case '.': // 2 strings to match. 1574 switch (Mnemonic[6]) { 1575 default: break; 1576 case 'f': // 1 string to match. 1577 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1578 break; 1579 Mnemonic = "vldrd.u64"; // "vldrd.f64" 1580 return; 1581 case 's': // 1 string to match. 1582 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1583 break; 1584 Mnemonic = "vldrd.u64"; // "vldrd.s64" 1585 return; 1586 } 1587 break; 1588 case 'e': // 1 string to match. 1589 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0) 1590 break; 1591 Mnemonic = "vldrde.u64"; // "vldrde.64" 1592 return; 1593 case 't': // 1 string to match. 1594 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0) 1595 break; 1596 Mnemonic = "vldrdt.u64"; // "vldrdt.64" 1597 return; 1598 } 1599 break; 1600 case 'h': // 4 strings to match. 1601 switch (Mnemonic[5]) { 1602 default: break; 1603 case '.': // 2 strings to match. 1604 switch (Mnemonic[6]) { 1605 default: break; 1606 case 'f': // 1 string to match. 1607 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1608 break; 1609 Mnemonic = "vldrh.u16"; // "vldrh.f16" 1610 return; 1611 case 's': // 1 string to match. 1612 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1613 break; 1614 Mnemonic = "vldrh.u16"; // "vldrh.s16" 1615 return; 1616 } 1617 break; 1618 case 'e': // 1 string to match. 1619 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0) 1620 break; 1621 Mnemonic = "vldrhe.u16"; // "vldrhe.16" 1622 return; 1623 case 't': // 1 string to match. 1624 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0) 1625 break; 1626 Mnemonic = "vldrht.u16"; // "vldrht.16" 1627 return; 1628 } 1629 break; 1630 case 'w': // 4 strings to match. 1631 switch (Mnemonic[5]) { 1632 default: break; 1633 case '.': // 2 strings to match. 1634 switch (Mnemonic[6]) { 1635 default: break; 1636 case 'f': // 1 string to match. 1637 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1638 break; 1639 Mnemonic = "vldrw.u32"; // "vldrw.f32" 1640 return; 1641 case 's': // 1 string to match. 1642 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1643 break; 1644 Mnemonic = "vldrw.u32"; // "vldrw.s32" 1645 return; 1646 } 1647 break; 1648 case 'e': // 1 string to match. 1649 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0) 1650 break; 1651 Mnemonic = "vldrwe.u32"; // "vldrwe.32" 1652 return; 1653 case 't': // 1 string to match. 1654 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0) 1655 break; 1656 Mnemonic = "vldrwt.u32"; // "vldrwt.32" 1657 return; 1658 } 1659 break; 1660 } 1661 break; 1662 case 'm': // 2 strings to match. 1663 if (memcmp(Mnemonic.data()+2, "ovq.f", 5) != 0) 1664 break; 1665 switch (Mnemonic[7]) { 1666 default: break; 1667 case '3': // 1 string to match. 1668 if (Mnemonic[8] != '2') 1669 break; 1670 if (Features.test(Feature_HasNEONBit)) // "vmovq.f32" 1671 Mnemonic = "vmov.f32"; 1672 return; 1673 case '6': // 1 string to match. 1674 if (Mnemonic[8] != '4') 1675 break; 1676 if (Features.test(Feature_HasNEONBit)) // "vmovq.f64" 1677 Mnemonic = "vmov.f64"; 1678 return; 1679 } 1680 break; 1681 case 's': // 13 strings to match. 1682 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0) 1683 break; 1684 switch (Mnemonic[4]) { 1685 default: break; 1686 case 'b': // 4 strings to match. 1687 switch (Mnemonic[5]) { 1688 default: break; 1689 case 'e': // 2 strings to match. 1690 if (Mnemonic[6] != '.') 1691 break; 1692 switch (Mnemonic[7]) { 1693 default: break; 1694 case 's': // 1 string to match. 1695 if (Mnemonic[8] != '8') 1696 break; 1697 Mnemonic = "vstrbe.8"; // "vstrbe.s8" 1698 return; 1699 case 'u': // 1 string to match. 1700 if (Mnemonic[8] != '8') 1701 break; 1702 Mnemonic = "vstrbe.8"; // "vstrbe.u8" 1703 return; 1704 } 1705 break; 1706 case 't': // 2 strings to match. 1707 if (Mnemonic[6] != '.') 1708 break; 1709 switch (Mnemonic[7]) { 1710 default: break; 1711 case 's': // 1 string to match. 1712 if (Mnemonic[8] != '8') 1713 break; 1714 Mnemonic = "vstrbt.8"; // "vstrbt.s8" 1715 return; 1716 case 'u': // 1 string to match. 1717 if (Mnemonic[8] != '8') 1718 break; 1719 Mnemonic = "vstrbt.8"; // "vstrbt.u8" 1720 return; 1721 } 1722 break; 1723 } 1724 break; 1725 case 'd': // 3 strings to match. 1726 if (Mnemonic[5] != '.') 1727 break; 1728 switch (Mnemonic[6]) { 1729 default: break; 1730 case 'f': // 1 string to match. 1731 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1732 break; 1733 Mnemonic = "vstrd.64"; // "vstrd.f64" 1734 return; 1735 case 's': // 1 string to match. 1736 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1737 break; 1738 Mnemonic = "vstrd.64"; // "vstrd.s64" 1739 return; 1740 case 'u': // 1 string to match. 1741 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1742 break; 1743 Mnemonic = "vstrd.64"; // "vstrd.u64" 1744 return; 1745 } 1746 break; 1747 case 'h': // 3 strings to match. 1748 if (Mnemonic[5] != '.') 1749 break; 1750 switch (Mnemonic[6]) { 1751 default: break; 1752 case 'f': // 1 string to match. 1753 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1754 break; 1755 Mnemonic = "vstrh.16"; // "vstrh.f16" 1756 return; 1757 case 's': // 1 string to match. 1758 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1759 break; 1760 Mnemonic = "vstrh.16"; // "vstrh.s16" 1761 return; 1762 case 'u': // 1 string to match. 1763 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1764 break; 1765 Mnemonic = "vstrh.16"; // "vstrh.u16" 1766 return; 1767 } 1768 break; 1769 case 'w': // 3 strings to match. 1770 if (Mnemonic[5] != '.') 1771 break; 1772 switch (Mnemonic[6]) { 1773 default: break; 1774 case 'f': // 1 string to match. 1775 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1776 break; 1777 Mnemonic = "vstrw.32"; // "vstrw.f32" 1778 return; 1779 case 's': // 1 string to match. 1780 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1781 break; 1782 Mnemonic = "vstrw.32"; // "vstrw.s32" 1783 return; 1784 case 'u': // 1 string to match. 1785 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1786 break; 1787 Mnemonic = "vstrw.32"; // "vstrw.u32" 1788 return; 1789 } 1790 break; 1791 } 1792 break; 1793 } 1794 break; 1795 } 1796 break; 1797 case 10: // 30 strings to match. 1798 if (Mnemonic[0] != 'v') 1799 break; 1800 switch (Mnemonic[1]) { 1801 default: break; 1802 case 'l': // 12 strings to match. 1803 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1804 break; 1805 switch (Mnemonic[4]) { 1806 default: break; 1807 case 'd': // 4 strings to match. 1808 switch (Mnemonic[5]) { 1809 default: break; 1810 case 'e': // 2 strings to match. 1811 if (Mnemonic[6] != '.') 1812 break; 1813 switch (Mnemonic[7]) { 1814 default: break; 1815 case 'f': // 1 string to match. 1816 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1817 break; 1818 Mnemonic = "vldrde.u64"; // "vldrde.f64" 1819 return; 1820 case 's': // 1 string to match. 1821 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1822 break; 1823 Mnemonic = "vldrde.u64"; // "vldrde.s64" 1824 return; 1825 } 1826 break; 1827 case 't': // 2 strings to match. 1828 if (Mnemonic[6] != '.') 1829 break; 1830 switch (Mnemonic[7]) { 1831 default: break; 1832 case 'f': // 1 string to match. 1833 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1834 break; 1835 Mnemonic = "vldrdt.u64"; // "vldrdt.f64" 1836 return; 1837 case 's': // 1 string to match. 1838 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1839 break; 1840 Mnemonic = "vldrdt.u64"; // "vldrdt.s64" 1841 return; 1842 } 1843 break; 1844 } 1845 break; 1846 case 'h': // 4 strings to match. 1847 switch (Mnemonic[5]) { 1848 default: break; 1849 case 'e': // 2 strings to match. 1850 if (Mnemonic[6] != '.') 1851 break; 1852 switch (Mnemonic[7]) { 1853 default: break; 1854 case 'f': // 1 string to match. 1855 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1856 break; 1857 Mnemonic = "vldrhe.u16"; // "vldrhe.f16" 1858 return; 1859 case 's': // 1 string to match. 1860 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1861 break; 1862 Mnemonic = "vldrhe.u16"; // "vldrhe.s16" 1863 return; 1864 } 1865 break; 1866 case 't': // 2 strings to match. 1867 if (Mnemonic[6] != '.') 1868 break; 1869 switch (Mnemonic[7]) { 1870 default: break; 1871 case 'f': // 1 string to match. 1872 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1873 break; 1874 Mnemonic = "vldrht.u16"; // "vldrht.f16" 1875 return; 1876 case 's': // 1 string to match. 1877 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1878 break; 1879 Mnemonic = "vldrht.u16"; // "vldrht.s16" 1880 return; 1881 } 1882 break; 1883 } 1884 break; 1885 case 'w': // 4 strings to match. 1886 switch (Mnemonic[5]) { 1887 default: break; 1888 case 'e': // 2 strings to match. 1889 if (Mnemonic[6] != '.') 1890 break; 1891 switch (Mnemonic[7]) { 1892 default: break; 1893 case 'f': // 1 string to match. 1894 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1895 break; 1896 Mnemonic = "vldrwe.u32"; // "vldrwe.f32" 1897 return; 1898 case 's': // 1 string to match. 1899 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1900 break; 1901 Mnemonic = "vldrwe.u32"; // "vldrwe.s32" 1902 return; 1903 } 1904 break; 1905 case 't': // 2 strings to match. 1906 if (Mnemonic[6] != '.') 1907 break; 1908 switch (Mnemonic[7]) { 1909 default: break; 1910 case 'f': // 1 string to match. 1911 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1912 break; 1913 Mnemonic = "vldrwt.u32"; // "vldrwt.f32" 1914 return; 1915 case 's': // 1 string to match. 1916 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1917 break; 1918 Mnemonic = "vldrwt.u32"; // "vldrwt.s32" 1919 return; 1920 } 1921 break; 1922 } 1923 break; 1924 } 1925 break; 1926 case 's': // 18 strings to match. 1927 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0) 1928 break; 1929 switch (Mnemonic[4]) { 1930 default: break; 1931 case 'd': // 6 strings to match. 1932 switch (Mnemonic[5]) { 1933 default: break; 1934 case 'e': // 3 strings to match. 1935 if (Mnemonic[6] != '.') 1936 break; 1937 switch (Mnemonic[7]) { 1938 default: break; 1939 case 'f': // 1 string to match. 1940 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1941 break; 1942 Mnemonic = "vstrde.64"; // "vstrde.f64" 1943 return; 1944 case 's': // 1 string to match. 1945 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1946 break; 1947 Mnemonic = "vstrde.64"; // "vstrde.s64" 1948 return; 1949 case 'u': // 1 string to match. 1950 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1951 break; 1952 Mnemonic = "vstrde.64"; // "vstrde.u64" 1953 return; 1954 } 1955 break; 1956 case 't': // 3 strings to match. 1957 if (Mnemonic[6] != '.') 1958 break; 1959 switch (Mnemonic[7]) { 1960 default: break; 1961 case 'f': // 1 string to match. 1962 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1963 break; 1964 Mnemonic = "vstrdt.64"; // "vstrdt.f64" 1965 return; 1966 case 's': // 1 string to match. 1967 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1968 break; 1969 Mnemonic = "vstrdt.64"; // "vstrdt.s64" 1970 return; 1971 case 'u': // 1 string to match. 1972 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1973 break; 1974 Mnemonic = "vstrdt.64"; // "vstrdt.u64" 1975 return; 1976 } 1977 break; 1978 } 1979 break; 1980 case 'h': // 6 strings to match. 1981 switch (Mnemonic[5]) { 1982 default: break; 1983 case 'e': // 3 strings to match. 1984 if (Mnemonic[6] != '.') 1985 break; 1986 switch (Mnemonic[7]) { 1987 default: break; 1988 case 'f': // 1 string to match. 1989 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1990 break; 1991 Mnemonic = "vstrhe.16"; // "vstrhe.f16" 1992 return; 1993 case 's': // 1 string to match. 1994 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1995 break; 1996 Mnemonic = "vstrhe.16"; // "vstrhe.s16" 1997 return; 1998 case 'u': // 1 string to match. 1999 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2000 break; 2001 Mnemonic = "vstrhe.16"; // "vstrhe.u16" 2002 return; 2003 } 2004 break; 2005 case 't': // 3 strings to match. 2006 if (Mnemonic[6] != '.') 2007 break; 2008 switch (Mnemonic[7]) { 2009 default: break; 2010 case 'f': // 1 string to match. 2011 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2012 break; 2013 Mnemonic = "vstrht.16"; // "vstrht.f16" 2014 return; 2015 case 's': // 1 string to match. 2016 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2017 break; 2018 Mnemonic = "vstrht.16"; // "vstrht.s16" 2019 return; 2020 case 'u': // 1 string to match. 2021 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2022 break; 2023 Mnemonic = "vstrht.16"; // "vstrht.u16" 2024 return; 2025 } 2026 break; 2027 } 2028 break; 2029 case 'w': // 6 strings to match. 2030 switch (Mnemonic[5]) { 2031 default: break; 2032 case 'e': // 3 strings to match. 2033 if (Mnemonic[6] != '.') 2034 break; 2035 switch (Mnemonic[7]) { 2036 default: break; 2037 case 'f': // 1 string to match. 2038 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2039 break; 2040 Mnemonic = "vstrwe.32"; // "vstrwe.f32" 2041 return; 2042 case 's': // 1 string to match. 2043 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2044 break; 2045 Mnemonic = "vstrwe.32"; // "vstrwe.s32" 2046 return; 2047 case 'u': // 1 string to match. 2048 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2049 break; 2050 Mnemonic = "vstrwe.32"; // "vstrwe.u32" 2051 return; 2052 } 2053 break; 2054 case 't': // 3 strings to match. 2055 if (Mnemonic[6] != '.') 2056 break; 2057 switch (Mnemonic[7]) { 2058 default: break; 2059 case 'f': // 1 string to match. 2060 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2061 break; 2062 Mnemonic = "vstrwt.32"; // "vstrwt.f32" 2063 return; 2064 case 's': // 1 string to match. 2065 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2066 break; 2067 Mnemonic = "vstrwt.32"; // "vstrwt.s32" 2068 return; 2069 case 'u': // 1 string to match. 2070 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2071 break; 2072 Mnemonic = "vstrwt.32"; // "vstrwt.u32" 2073 return; 2074 } 2075 break; 2076 } 2077 break; 2078 } 2079 break; 2080 } 2081 break; 2082 case 11: // 2 strings to match. 2083 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0) 2084 break; 2085 switch (Mnemonic[8]) { 2086 default: break; 2087 case 'f': // 1 string to match. 2088 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 2089 break; 2090 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.f32" 2091 Mnemonic = "vrecpe.f32"; 2092 return; 2093 case 'u': // 1 string to match. 2094 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 2095 break; 2096 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.u32" 2097 Mnemonic = "vrecpe.u32"; 2098 return; 2099 } 2100 break; 2101 } 2102} 2103 2104enum { 2105 Tie0_1_1, 2106 Tie0_2_2, 2107 Tie0_2_4, 2108 Tie0_3_3, 2109 Tie0_4_4, 2110 Tie0_4_5, 2111 Tie1_1_1, 2112 Tie1_2_2, 2113 Tie1_3_3, 2114 Tie1_4_4, 2115 Tie2_4_4, 2116}; 2117 2118static const uint8_t TiedAsmOperandTable[][3] = { 2119 /* Tie0_1_1 */ { 0, 1, 1 }, 2120 /* Tie0_2_2 */ { 0, 2, 2 }, 2121 /* Tie0_2_4 */ { 0, 2, 4 }, 2122 /* Tie0_3_3 */ { 0, 3, 3 }, 2123 /* Tie0_4_4 */ { 0, 4, 4 }, 2124 /* Tie0_4_5 */ { 0, 4, 5 }, 2125 /* Tie1_1_1 */ { 1, 1, 1 }, 2126 /* Tie1_2_2 */ { 1, 2, 2 }, 2127 /* Tie1_3_3 */ { 1, 3, 3 }, 2128 /* Tie1_4_4 */ { 1, 4, 4 }, 2129 /* Tie2_4_4 */ { 2, 4, 4 }, 2130}; 2131 2132namespace { 2133enum OperatorConversionKind { 2134 CVT_Done, 2135 CVT_Reg, 2136 CVT_Tied, 2137 CVT_95_Reg, 2138 CVT_95_addCCOutOperands, 2139 CVT_95_addCondCodeOperands, 2140 CVT_95_addRegShiftedRegOperands, 2141 CVT_95_addModImmOperands, 2142 CVT_95_addModImmNotOperands, 2143 CVT_95_addRegShiftedImmOperands, 2144 CVT_95_addImmOperands, 2145 CVT_95_addT2SOImmNotOperands, 2146 CVT_95_addImm0_95_4095NegOperands, 2147 CVT_95_addImm0_95_508s4Operands, 2148 CVT_regSP, 2149 CVT_95_addImm0_95_508s4NegOperands, 2150 CVT_95_addT2SOImmNegOperands, 2151 CVT_95_addThumbModImmNeg8_95_255Operands, 2152 CVT_95_addModImmNegOperands, 2153 CVT_95_addImm0_95_1020s4Operands, 2154 CVT_95_addThumbModImmNeg1_95_7Operands, 2155 CVT_95_addUnsignedOffset_95_b8s2Operands, 2156 CVT_95_addAdrLabelOperands, 2157 CVT_95_addARMBranchTargetOperands, 2158 CVT_cvtThumbBranches, 2159 CVT_95_addBitfieldOperands, 2160 CVT_95_addITCondCodeOperands, 2161 CVT_imm_95_0, 2162 CVT_95_addThumbBranchTargetOperands, 2163 CVT_95_addCoprocNumOperands, 2164 CVT_95_addCoprocRegOperands, 2165 CVT_95_addITCondCodeInvOperands, 2166 CVT_95_addRegListWithAPSROperands, 2167 CVT_95_addProcIFlagsOperands, 2168 CVT_imm_95_20, 2169 CVT_regZR, 2170 CVT_imm_95_12, 2171 CVT_imm_95_15, 2172 CVT_95_addMemBarrierOptOperands, 2173 CVT_imm_95_16, 2174 CVT_95_addFPImmOperands, 2175 CVT_95_addDPRRegListOperands, 2176 CVT_imm_95_1, 2177 CVT_95_addInstSyncBarrierOptOperands, 2178 CVT_95_addITMaskOperands, 2179 CVT_95_addMemNoOffsetOperands, 2180 CVT_95_addAddrMode5Operands, 2181 CVT_95_addCoprocOptionOperands, 2182 CVT_95_addPostIdxImm8s4Operands, 2183 CVT_95_addRegListOperands, 2184 CVT_95_addThumbMemPCOperands, 2185 CVT_95_addConstPoolAsmImmOperands, 2186 CVT_95_addMemThumbRIs4Operands, 2187 CVT_95_addMemThumbRROperands, 2188 CVT_95_addMemThumbSPIOperands, 2189 CVT_95_addMemImm12OffsetOperands, 2190 CVT_95_addMemImmOffsetOperands, 2191 CVT_95_addMemRegOffsetOperands, 2192 CVT_95_addMemUImm12OffsetOperands, 2193 CVT_95_addT2MemRegOffsetOperands, 2194 CVT_95_addMemPCRelImm12Operands, 2195 CVT_95_addAM2OffsetImmOperands, 2196 CVT_95_addPostIdxRegShiftedOperands, 2197 CVT_95_addMemThumbRIs1Operands, 2198 CVT_95_addMemImm8s4OffsetOperands, 2199 CVT_95_addAddrMode3Operands, 2200 CVT_95_addAM3OffsetOperands, 2201 CVT_95_addMemImm0_95_1020s4OffsetOperands, 2202 CVT_95_addMemThumbRIs2Operands, 2203 CVT_95_addPostIdxRegOperands, 2204 CVT_95_addPostIdxImm8Operands, 2205 CVT_reg0, 2206 CVT_regCPSR, 2207 CVT_imm_95_14, 2208 CVT_95_addBankedRegOperands, 2209 CVT_95_addMSRMaskOperands, 2210 CVT_cvtThumbMultiply, 2211 CVT_regR8, 2212 CVT_regR0, 2213 CVT_95_addPKHASRImmOperands, 2214 CVT_imm_95_4, 2215 CVT_95_addImm1_95_32Operands, 2216 CVT_imm_95_5, 2217 CVT_95_addMveSaturateOperands, 2218 CVT_95_addShifterImmOperands, 2219 CVT_95_addImm1_95_16Operands, 2220 CVT_95_addRotImmOperands, 2221 CVT_95_addMemTBBOperands, 2222 CVT_95_addMemTBHOperands, 2223 CVT_95_addTraceSyncBarrierOptOperands, 2224 CVT_95_addVPTPredNOperands, 2225 CVT_95_addVPTPredROperands, 2226 CVT_95_addNEONi16splatNotOperands, 2227 CVT_95_addNEONi32splatNotOperands, 2228 CVT_95_addNEONi16splatOperands, 2229 CVT_95_addNEONi32splatOperands, 2230 CVT_95_addComplexRotationOddOperands, 2231 CVT_95_addComplexRotationEvenOperands, 2232 CVT_95_addVectorIndex64Operands, 2233 CVT_95_addVectorIndex32Operands, 2234 CVT_95_addFBits16Operands, 2235 CVT_95_addFBits32Operands, 2236 CVT_95_addPowerTwoOperands, 2237 CVT_95_addVectorIndex16Operands, 2238 CVT_95_addVectorIndex8Operands, 2239 CVT_95_addVecListOperands, 2240 CVT_95_addDupAlignedMemory16Operands, 2241 CVT_95_addAlignedMemory64or128Operands, 2242 CVT_95_addAlignedMemory64or128or256Operands, 2243 CVT_95_addAlignedMemory64Operands, 2244 CVT_95_addVecListIndexedOperands, 2245 CVT_95_addAlignedMemory16Operands, 2246 CVT_95_addDupAlignedMemory32Operands, 2247 CVT_95_addAlignedMemory32Operands, 2248 CVT_95_addDupAlignedMemoryNoneOperands, 2249 CVT_95_addAlignedMemoryNoneOperands, 2250 CVT_95_addAlignedMemoryOperands, 2251 CVT_95_addDupAlignedMemory64Operands, 2252 CVT_95_addMVEVecListOperands, 2253 CVT_95_addMemNoOffsetT2Operands, 2254 CVT_95_addMemNoOffsetT2NoSpOperands, 2255 CVT_95_addDupAlignedMemory64or128Operands, 2256 CVT_95_addSPRRegListOperands, 2257 CVT_95_addMemImm7s4OffsetOperands, 2258 CVT_95_addAddrMode5FP16Operands, 2259 CVT_95_addImm7s4Operands, 2260 CVT_95_addMemRegRQOffsetOperands, 2261 CVT_95_addMemNoOffsetTOperands, 2262 CVT_95_addImm7Shift0Operands, 2263 CVT_95_addImm7Shift1Operands, 2264 CVT_95_addImm7Shift2Operands, 2265 CVT_95_addNEONi32vmovOperands, 2266 CVT_95_addNEONvmovi8ReplicateOperands, 2267 CVT_95_addNEONvmovi16ReplicateOperands, 2268 CVT_95_addNEONi32vmovNegOperands, 2269 CVT_95_addNEONvmovi32ReplicateOperands, 2270 CVT_95_addNEONi64splatOperands, 2271 CVT_95_addNEONi8splatOperands, 2272 CVT_95_addMVEVectorIndexOperands, 2273 CVT_95_addMVEPairVectorIndexOperands, 2274 CVT_cvtMVEVMOVQtoDReg, 2275 CVT_95_addNEONinvi8ReplicateOperands, 2276 CVT_95_addFPDRegListWithVPROperands, 2277 CVT_95_addFPSRegListWithVPROperands, 2278 CVT_imm_95_2, 2279 CVT_imm_95_3, 2280 CVT_NUM_CONVERTERS 2281}; 2282 2283enum InstructionConversionKind { 2284 Convert_NoOperands, 2285 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, 2286 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 2287 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 2288 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 2289 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 2290 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 2291 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2292 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2293 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2294 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 2295 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, 2296 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, 2297 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, 2298 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 2299 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, 2300 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, 2301 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, 2302 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, 2303 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, 2304 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, 2305 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 2306 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, 2307 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, 2308 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, 2309 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, 2310 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, 2311 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, 2312 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, 2313 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, 2314 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, 2315 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, 2316 Convert__Reg1_1__Imm0_40951_3__CondCode2_0, 2317 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, 2318 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2319 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 2320 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 2321 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, 2322 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, 2323 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, 2324 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, 2325 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, 2326 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, 2327 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, 2328 Convert__Reg1_1__Imm1_2__CondCode2_0, 2329 Convert__Reg1_1__AdrLabel1_2__CondCode2_0, 2330 Convert__Reg1_2__Imm1_3__CondCode2_0, 2331 Convert__Reg1_1__Tie0_1_1__Reg1_2, 2332 Convert__Reg1_1__Reg1_2, 2333 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 2334 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2335 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2336 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 2337 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, 2338 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, 2339 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, 2340 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, 2341 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 2342 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, 2343 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 2344 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, 2345 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, 2346 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, 2347 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, 2348 Convert__ARMBranchTarget1_1__CondCode2_0, 2349 ConvertCustom_cvtThumbBranches, 2350 Convert__Imm1_1__Imm1_2__CondCode2_0, 2351 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, 2352 Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, 2353 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, 2354 Convert__Imm1_1__Reg1_2__CondCode2_0, 2355 Convert__imm_95_0, 2356 Convert__Imm0_2551_0, 2357 Convert__Imm0_655351_0, 2358 Convert__ARMBranchTarget1_0, 2359 Convert__CondCode2_0__ThumbBranchTarget1_1, 2360 Convert__Reg1_0, 2361 Convert__ThumbBranchTarget1_0, 2362 Convert__Reg1_1__CondCode2_0, 2363 Convert__CondCode2_0__Reg1_1, 2364 Convert__CondCode2_0__ARMBranchTarget1_1, 2365 Convert__CondCode2_0, 2366 Convert__Reg1_0__ThumbBranchTarget1_1, 2367 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2368 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2369 Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, 2370 Convert__CondCode2_0__RegListWithAPSR1_1, 2371 Convert__Reg1_1__Reg1_2__CondCode2_0, 2372 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, 2373 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, 2374 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, 2375 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, 2376 Convert__Reg1_1__T2SOImm1_2__CondCode2_0, 2377 Convert__Reg1_1__ModImm1_2__CondCode2_0, 2378 Convert__Reg1_2__Reg1_3__CondCode2_0, 2379 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, 2380 Convert__Reg1_2__T2SOImm1_3__CondCode2_0, 2381 Convert__Reg1_1__Imm0_2551_2__CondCode2_0, 2382 Convert__Imm0_311_0, 2383 Convert__Imm0_311_1, 2384 Convert__Imm1_0__ProcIFlags1_1, 2385 Convert__Imm1_0__ProcIFlags1_2, 2386 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, 2387 Convert__Imm1_0__ProcIFlags1_1__Imm1_2, 2388 Convert__Imm1_0__ProcIFlags1_2__Imm1_3, 2389 Convert__Reg1_0__Reg1_1__Reg1_2, 2390 Convert__imm_95_20__CondCode2_0, 2391 Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, 2392 Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, 2393 Convert__Imm0_151_1__CondCode2_0, 2394 Convert__imm_95_12, 2395 Convert__imm_95_12__CondCode2_0, 2396 Convert__Reg1_0__Reg1_1, 2397 Convert__imm_95_15, 2398 Convert__imm_95_15__CondCode2_0, 2399 Convert__MemBarrierOpt1_0, 2400 Convert__MemBarrierOpt1_1__CondCode2_0, 2401 Convert__imm_95_0__CondCode2_0, 2402 Convert__imm_95_16__CondCode2_0, 2403 Convert__Reg1_1__FPImm1_2__CondCode2_0, 2404 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, 2405 Convert__Reg1_1__CondCode2_0__DPRRegList1_2, 2406 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, 2407 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, 2408 Convert__Imm0_2391_1__CondCode2_0, 2409 Convert__Imm0_2391_2__CondCode2_0, 2410 Convert__Imm0_631_0, 2411 Convert__Imm0_655351_1, 2412 Convert__InstSyncBarrierOpt1_0, 2413 Convert__InstSyncBarrierOpt1_1__CondCode2_0, 2414 Convert__ITCondCode1_1__ITMask1_0, 2415 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, 2416 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, 2417 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, 2418 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, 2419 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, 2420 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, 2421 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, 2422 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, 2423 Convert__Reg1_1__CondCode2_0__RegList1_2, 2424 Convert__Reg1_2__CondCode2_0__RegList1_3, 2425 Convert__Reg1_1__CondCode2_0__RegList1_3, 2426 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, 2427 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, 2428 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, 2429 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, 2430 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, 2431 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, 2432 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, 2433 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, 2434 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, 2435 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, 2436 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, 2437 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, 2438 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, 2439 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, 2440 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, 2441 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, 2442 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, 2443 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, 2444 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, 2445 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, 2446 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, 2447 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, 2448 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, 2449 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, 2450 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, 2451 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 2452 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 2453 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, 2454 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, 2455 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, 2456 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, 2457 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, 2458 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, 2459 Convert__Reg1_1__AddrMode33_2__CondCode2_0, 2460 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, 2461 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, 2462 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, 2463 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, 2464 Convert__LELabel1_0, 2465 Convert__imm_95_0__Reg1_0__LELabel1_1, 2466 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, 2467 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, 2468 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, 2469 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 2470 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, 2471 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 2472 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 2473 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, 2474 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, 2475 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2476 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 2477 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2478 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, 2479 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2480 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, 2481 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, 2482 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 2483 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 2484 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, 2485 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, 2486 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, 2487 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, 2488 Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, 2489 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 2490 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 2491 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 2492 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 2493 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, 2494 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, 2495 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, 2496 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2497 Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, 2498 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, 2499 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, 2500 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, 2501 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, 2502 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, 2503 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 2504 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2505 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, 2506 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2507 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, 2508 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, 2509 Convert__Reg1_1__BankedReg1_2__CondCode2_0, 2510 Convert__Reg1_1__MSRMask1_2__CondCode2_0, 2511 Convert__BankedReg1_1__Reg1_2__CondCode2_0, 2512 Convert__MSRMask1_1__Reg1_2__CondCode2_0, 2513 Convert__MSRMask1_1__ModImm1_2__CondCode2_0, 2514 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, 2515 ConvertCustom_cvtThumbMultiply, 2516 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, 2517 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 2518 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 2519 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2520 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, 2521 Convert__regR8__regR8__imm_95_14__imm_95_0, 2522 Convert__regR0__regR0__CondCode2_0__reg0, 2523 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 2524 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, 2525 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, 2526 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, 2527 Convert__MemImm12Offset2_0, 2528 Convert__MemRegOffset3_0, 2529 Convert__Imm1_1__CondCode2_0, 2530 Convert__MemNegImm8Offset2_1__CondCode2_0, 2531 Convert__MemUImm12Offset2_1__CondCode2_0, 2532 Convert__T2MemRegOffset3_1__CondCode2_0, 2533 Convert__MemPCRelImm121_1__CondCode2_0, 2534 Convert__CondCode2_0__RegList1_1, 2535 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, 2536 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, 2537 Convert__imm_95_4__imm_95_14__imm_95_0, 2538 Convert__imm_95_4, 2539 Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, 2540 Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, 2541 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, 2542 Convert__SetEndImm1_0, 2543 Convert__Imm0_11_0, 2544 Convert__imm_95_4__CondCode2_0, 2545 Convert__imm_95_5__CondCode2_0, 2546 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, 2547 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, 2548 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, 2549 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, 2550 Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, 2551 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, 2552 Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, 2553 Convert__Imm0_311_2, 2554 Convert__Imm0_311_1__CondCode2_0, 2555 Convert__Imm0_311_2__CondCode2_0, 2556 Convert__Imm0_311_3__CondCode2_0, 2557 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, 2558 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, 2559 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, 2560 Convert__imm_95_0__imm_95_14__imm_95_0, 2561 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, 2562 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, 2563 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, 2564 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, 2565 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, 2566 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, 2567 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, 2568 Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, 2569 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 2570 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, 2571 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 2572 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, 2573 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, 2574 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, 2575 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, 2576 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, 2577 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, 2578 Convert__Imm0_2551_3__CondCode2_0, 2579 Convert__Imm0_2551_1__CondCode2_0, 2580 Convert__Imm24bit1_1__CondCode2_0, 2581 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 2582 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, 2583 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 2584 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, 2585 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 2586 Convert__MemTBB2_1__CondCode2_0, 2587 Convert__MemTBH2_1__CondCode2_0, 2588 Convert__TraceSyncBarrierOpt1_0, 2589 Convert__TraceSyncBarrierOpt1_1__CondCode2_0, 2590 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, 2591 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, 2592 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, 2593 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, 2594 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, 2595 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, 2596 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 2597 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, 2598 Convert__Reg1_2__Reg1_3__VPTPredR3_0, 2599 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, 2600 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, 2601 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0, 2602 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0, 2603 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, 2604 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN2_0, 2605 Convert__Reg1_2__Reg1_3__VPTPredN2_0, 2606 Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, 2607 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, 2608 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, 2609 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, 2610 Convert__Reg1_2__imm_95_0__InvertedExpandImm0_161_3__VPTPredN2_0, 2611 Convert__Reg1_2__imm_95_0__InvertedExpandImm8_161_3__VPTPredN2_0, 2612 Convert__Reg1_2__imm_95_0__InvertedExpandImm0_321_3__VPTPredN2_0, 2613 Convert__Reg1_2__imm_95_0__InvertedExpandImm8_321_3__VPTPredN2_0, 2614 Convert__Reg1_2__imm_95_0__InvertedExpandImm16_321_3__VPTPredN2_0, 2615 Convert__Reg1_2__imm_95_0__InvertedExpandImm24_321_3__VPTPredN2_0, 2616 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, 2617 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, 2618 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, 2619 Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0, 2620 Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0, 2621 Convert__Reg1_2__Tie0_1_1__ExpandImm161_3__VPTPredN2_0, 2622 Convert__Reg1_2__Tie0_1_1__ExpandImm241_3__VPTPredN2_0, 2623 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, 2624 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, 2625 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, 2626 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, 2627 Convert__Reg1_2__Reg1_2__CondCode2_0, 2628 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, 2629 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, 2630 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, 2631 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN2_0, 2632 Convert__Reg1_2__CondCode2_0, 2633 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, 2634 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, 2635 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, 2636 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, 2637 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0, 2638 Convert__imm_95_0__Reg1_2__VPTPredN2_0, 2639 Convert__Reg1_3__Reg1_4__CondCode2_0, 2640 Convert__Reg1_3__Reg1_4__VPTPredR3_0, 2641 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, 2642 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, 2643 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, 2644 Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, 2645 Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, 2646 Convert__Reg1_2__Reg1_3, 2647 Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0, 2648 Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, 2649 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 2650 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 2651 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, 2652 Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, 2653 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, 2654 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, 2655 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, 2656 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, 2657 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, 2658 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, 2659 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, 2660 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, 2661 Convert__Reg1_1__Reg1_2__Reg1_3, 2662 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, 2663 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, 2664 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2665 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, 2666 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, 2667 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2668 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, 2669 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, 2670 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, 2671 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2672 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2673 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2674 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2675 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2676 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2677 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2678 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2679 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 2680 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2681 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, 2682 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2683 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2684 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2685 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 2686 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 2687 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 2688 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 2689 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 2690 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2691 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2692 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2693 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2694 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2695 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 2696 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2697 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 2698 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2699 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2700 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, 2701 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 2702 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 2703 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2704 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, 2705 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2706 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2707 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2708 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2709 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2710 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2711 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2712 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, 2713 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2714 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2715 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 2716 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2717 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2718 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2719 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 2720 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2721 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 2722 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2723 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2724 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2725 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2726 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2727 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 2728 Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, 2729 Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, 2730 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2731 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2732 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2733 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, 2734 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2735 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2736 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2737 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2738 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2739 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2740 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2741 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2742 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2743 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2744 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2745 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2746 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2747 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, 2748 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, 2749 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, 2750 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, 2751 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2752 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2753 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2754 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, 2755 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2756 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2757 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2758 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2759 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2760 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2761 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, 2762 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2763 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2764 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2765 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2766 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2767 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2768 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2769 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2770 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2771 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2772 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2773 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2774 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2775 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2776 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, 2777 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, 2778 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, 2779 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, 2780 Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, 2781 Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, 2782 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, 2783 Convert__Reg1_1__CondCode2_0__SPRRegList1_2, 2784 Convert__MemImm7s4Offset2_2__CondCode2_0, 2785 Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, 2786 Convert__Reg1_1__AddrMode52_2__CondCode2_0, 2787 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, 2788 Convert__Reg1_2__AddrMode52_3__CondCode2_0, 2789 Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, 2790 Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, 2791 Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, 2792 Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, 2793 Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, 2794 Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN2_0, 2795 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, 2796 Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, 2797 Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0, 2798 Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, 2799 Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, 2800 Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN2_0, 2801 Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, 2802 Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, 2803 Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, 2804 Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN2_0, 2805 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, 2806 Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, 2807 Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0, 2808 Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, 2809 Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN2_0, 2810 Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, 2811 Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN2_0, 2812 Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0, 2813 Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0, 2814 Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, 2815 Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, 2816 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2817 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2818 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, 2819 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, 2820 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, 2821 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, 2822 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, 2823 Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR3_0, 2824 Convert__Reg1_2__FPImm1_3__CondCode2_0, 2825 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, 2826 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, 2827 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, 2828 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, 2829 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, 2830 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, 2831 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, 2832 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, 2833 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, 2834 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, 2835 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, 2836 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, 2837 Convert__Reg1_2__FPImm1_3__VPTPredR3_0, 2838 Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0, 2839 Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0, 2840 Convert__Reg1_2__NEONi64splat1_3__VPTPredR3_0, 2841 Convert__Reg1_2__NEONi8splat1_3__VPTPredR3_0, 2842 Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, 2843 Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, 2844 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, 2845 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, 2846 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, 2847 Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, 2848 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, 2849 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, 2850 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, 2851 Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, 2852 ConvertCustom_cvtMVEVMOVQtoDReg, 2853 Convert__Reg1_1__imm_95_0__CondCode2_0, 2854 Convert__imm_95_0__Reg1_2__CondCode2_0, 2855 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 2856 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 2857 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2858 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2859 Convert__Reg1_1__Reg1_2__VPTPredR3_0, 2860 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, 2861 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, 2862 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, 2863 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, 2864 Convert__imm_95_0__imm_95_0__VPTPredN2_0, 2865 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, 2866 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, 2867 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, 2868 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, 2869 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN2_0, 2870 Convert__ITMask1_0, 2871 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, 2872 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, 2873 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, 2874 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, 2875 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, 2876 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, 2877 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, 2878 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, 2879 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, 2880 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, 2881 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, 2882 Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, 2883 Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, 2884 Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, 2885 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, 2886 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, 2887 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, 2888 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, 2889 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, 2890 Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, 2891 Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, 2892 Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, 2893 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, 2894 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, 2895 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, 2896 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, 2897 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, 2898 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, 2899 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, 2900 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, 2901 Convert__CondCode2_0__FPDRegListWithVPR1_1, 2902 Convert__CondCode2_0__FPSRegListWithVPR1_1, 2903 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, 2904 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, 2905 Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN2_0, 2906 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, 2907 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, 2908 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, 2909 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, 2910 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, 2911 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, 2912 Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, 2913 Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, 2914 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, 2915 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, 2916 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN2_0, 2917 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN2_0, 2918 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN2_0, 2919 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN2_0, 2920 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2921 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2922 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2923 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2924 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2925 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, 2926 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2927 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, 2928 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2929 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, 2930 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2931 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, 2932 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, 2933 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 2934 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 2935 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, 2936 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 2937 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 2938 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, 2939 Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, 2940 Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, 2941 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 2942 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 2943 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 2944 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 2945 Convert__VecListFourMQ1_1__MemNoOffsetT21_2, 2946 Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, 2947 Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, 2948 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, 2949 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, 2950 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0, 2951 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, 2952 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, 2953 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, 2954 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, 2955 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, 2956 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, 2957 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, 2958 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, 2959 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, 2960 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, 2961 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, 2962 Convert__imm_95_2__CondCode2_0, 2963 Convert__imm_95_3__CondCode2_0, 2964 Convert__Reg1_0__Reg1_1__WLSLabel1_2, 2965 Convert__Reg1_1__Reg1_2__WLSLabel1_3, 2966 Convert__imm_95_1__CondCode2_0, 2967 CVT_NUM_SIGNATURES 2968}; 2969 2970} // end anonymous namespace 2971 2972static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = { 2973 // Convert_NoOperands 2974 { CVT_Done }, 2975 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1 2976 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2977 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 2978 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2979 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 2980 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2981 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 2982 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2983 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 2984 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2985 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 2986 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2987 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 2988 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2989 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 2990 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2991 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 2992 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2993 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 2994 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2995 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0 2996 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2997 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0 2998 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2999 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0 3000 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3001 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 3002 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3003 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0 3004 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3005 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0 3006 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3007 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0 3008 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3009 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0 3010 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3011 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0 3012 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3013 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0 3014 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3015 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 3016 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3017 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0 3018 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3019 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1 3020 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3021 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1 3022 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3023 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1 3024 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3025 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0 3026 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3027 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0 3028 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3029 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0 3030 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3031 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0 3032 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3033 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0 3034 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3035 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0 3036 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3037 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0 3038 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3039 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0 3040 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3041 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 3042 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3043 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 3044 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3045 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 3046 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3047 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1 3048 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3049 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1 3050 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3051 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1 3052 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3053 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0 3054 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3055 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0 3056 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3057 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0 3058 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3059 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0 3060 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3061 // Convert__Reg1_1__Imm1_2__CondCode2_0 3062 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3063 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0 3064 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3065 // Convert__Reg1_2__Imm1_3__CondCode2_0 3066 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3067 // Convert__Reg1_1__Tie0_1_1__Reg1_2 3068 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done }, 3069 // Convert__Reg1_1__Reg1_2 3070 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 3071 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 3072 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3073 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 3074 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3075 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 3076 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3077 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 3078 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3079 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0 3080 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3081 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1 3082 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3083 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0 3084 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3085 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0 3086 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3087 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 3088 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3089 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1 3090 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3091 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 3092 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3093 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0 3094 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3095 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0 3096 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3097 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0 3098 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3099 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0 3100 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3101 // Convert__ARMBranchTarget1_1__CondCode2_0 3102 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3103 // ConvertCustom_cvtThumbBranches 3104 { CVT_cvtThumbBranches, 0, CVT_Done }, 3105 // Convert__Imm1_1__Imm1_2__CondCode2_0 3106 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3107 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0 3108 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3109 // Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3 3110 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done }, 3111 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0 3112 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3113 // Convert__Imm1_1__Reg1_2__CondCode2_0 3114 { CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3115 // Convert__imm_95_0 3116 { CVT_imm_95_0, 0, CVT_Done }, 3117 // Convert__Imm0_2551_0 3118 { CVT_95_addImmOperands, 1, CVT_Done }, 3119 // Convert__Imm0_655351_0 3120 { CVT_95_addImmOperands, 1, CVT_Done }, 3121 // Convert__ARMBranchTarget1_0 3122 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done }, 3123 // Convert__CondCode2_0__ThumbBranchTarget1_1 3124 { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 3125 // Convert__Reg1_0 3126 { CVT_95_Reg, 1, CVT_Done }, 3127 // Convert__ThumbBranchTarget1_0 3128 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done }, 3129 // Convert__Reg1_1__CondCode2_0 3130 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3131 // Convert__CondCode2_0__Reg1_1 3132 { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done }, 3133 // Convert__CondCode2_0__ARMBranchTarget1_1 3134 { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done }, 3135 // Convert__CondCode2_0 3136 { CVT_95_addCondCodeOperands, 1, CVT_Done }, 3137 // Convert__Reg1_0__ThumbBranchTarget1_1 3138 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 3139 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3140 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3141 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3142 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3143 // Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2 3144 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addITCondCodeInvOperands, 3, CVT_Done }, 3145 // Convert__CondCode2_0__RegListWithAPSR1_1 3146 { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListWithAPSROperands, 2, CVT_Done }, 3147 // Convert__Reg1_1__Reg1_2__CondCode2_0 3148 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3149 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0 3150 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3151 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0 3152 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3153 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0 3154 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3155 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0 3156 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3157 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0 3158 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3159 // Convert__Reg1_1__ModImm1_2__CondCode2_0 3160 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3161 // Convert__Reg1_2__Reg1_3__CondCode2_0 3162 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3163 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0 3164 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3165 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0 3166 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3167 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0 3168 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3169 // Convert__Imm0_311_0 3170 { CVT_95_addImmOperands, 1, CVT_Done }, 3171 // Convert__Imm0_311_1 3172 { CVT_95_addImmOperands, 2, CVT_Done }, 3173 // Convert__Imm1_0__ProcIFlags1_1 3174 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done }, 3175 // Convert__Imm1_0__ProcIFlags1_2 3176 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done }, 3177 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2 3178 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 3179 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2 3180 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 3181 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3 3182 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, 3183 // Convert__Reg1_0__Reg1_1__Reg1_2 3184 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 3185 // Convert__imm_95_20__CondCode2_0 3186 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3187 // Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3 3188 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done }, 3189 // Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1 3190 { CVT_95_Reg, 1, CVT_regZR, 0, CVT_regZR, 0, CVT_95_addITCondCodeInvOperands, 2, CVT_Done }, 3191 // Convert__Imm0_151_1__CondCode2_0 3192 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3193 // Convert__imm_95_12 3194 { CVT_imm_95_12, 0, CVT_Done }, 3195 // Convert__imm_95_12__CondCode2_0 3196 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3197 // Convert__Reg1_0__Reg1_1 3198 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 3199 // Convert__imm_95_15 3200 { CVT_imm_95_15, 0, CVT_Done }, 3201 // Convert__imm_95_15__CondCode2_0 3202 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3203 // Convert__MemBarrierOpt1_0 3204 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done }, 3205 // Convert__MemBarrierOpt1_1__CondCode2_0 3206 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3207 // Convert__imm_95_0__CondCode2_0 3208 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3209 // Convert__imm_95_16__CondCode2_0 3210 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3211 // Convert__Reg1_1__FPImm1_2__CondCode2_0 3212 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3213 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3 3214 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done }, 3215 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2 3216 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 3217 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0 3218 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3219 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0 3220 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3221 // Convert__Imm0_2391_1__CondCode2_0 3222 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3223 // Convert__Imm0_2391_2__CondCode2_0 3224 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3225 // Convert__Imm0_631_0 3226 { CVT_95_addImmOperands, 1, CVT_Done }, 3227 // Convert__Imm0_655351_1 3228 { CVT_95_addImmOperands, 2, CVT_Done }, 3229 // Convert__InstSyncBarrierOpt1_0 3230 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done }, 3231 // Convert__InstSyncBarrierOpt1_1__CondCode2_0 3232 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3233 // Convert__ITCondCode1_1__ITMask1_0 3234 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done }, 3235 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0 3236 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3237 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0 3238 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3239 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0 3240 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3241 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0 3242 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3243 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0 3244 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3245 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2 3246 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done }, 3247 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3 3248 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done }, 3249 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3 3250 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done }, 3251 // Convert__Reg1_1__CondCode2_0__RegList1_2 3252 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 3253 // Convert__Reg1_2__CondCode2_0__RegList1_3 3254 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3255 // Convert__Reg1_1__CondCode2_0__RegList1_3 3256 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3257 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3 3258 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3259 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4 3260 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done }, 3261 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0 3262 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3263 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0 3264 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3265 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0 3266 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3267 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0 3268 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3269 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0 3270 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3271 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0 3272 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3273 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0 3274 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3275 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0 3276 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3277 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0 3278 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3279 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0 3280 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3281 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0 3282 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3283 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0 3284 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3285 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0 3286 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3287 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0 3288 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3289 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0 3290 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3291 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0 3292 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3293 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0 3294 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3295 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0 3296 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3297 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0 3298 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3299 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0 3300 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3301 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0 3302 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3303 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0 3304 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3305 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0 3306 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3307 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 3308 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3309 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 3310 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3311 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0 3312 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3313 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0 3314 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3315 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0 3316 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3317 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0 3318 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3319 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0 3320 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3321 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0 3322 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3323 // Convert__Reg1_1__AddrMode33_2__CondCode2_0 3324 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3325 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0 3326 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3327 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0 3328 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3329 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0 3330 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3331 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0 3332 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3333 // Convert__LELabel1_0 3334 { CVT_95_addImmOperands, 1, CVT_Done }, 3335 // Convert__imm_95_0__Reg1_0__LELabel1_1 3336 { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 3337 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1 3338 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3339 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0 3340 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3341 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0 3342 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3343 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 3344 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3345 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1 3346 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3347 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 3348 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3349 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 3350 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3351 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0 3352 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3353 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0 3354 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3355 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 3356 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3357 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 3358 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3359 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3360 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3361 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0 3362 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 3363 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3364 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3365 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0 3366 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3367 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4 3368 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 3369 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 3370 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3371 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 3372 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3373 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0 3374 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3375 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0 3376 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3377 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0 3378 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3379 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0 3380 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3381 // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1 3382 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3383 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 3384 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3385 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 3386 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3387 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 3388 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3389 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 3390 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3391 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0 3392 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3393 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0 3394 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3395 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0 3396 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3397 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 3398 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3399 // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0 3400 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3401 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR 3402 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3403 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR 3404 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3405 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR 3406 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3407 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR 3408 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3409 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0 3410 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3411 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 3412 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3413 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3414 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3415 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0 3416 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 3417 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3418 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3419 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0 3420 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3421 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4 3422 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 3423 // Convert__Reg1_1__BankedReg1_2__CondCode2_0 3424 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3425 // Convert__Reg1_1__MSRMask1_2__CondCode2_0 3426 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3427 // Convert__BankedReg1_1__Reg1_2__CondCode2_0 3428 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3429 // Convert__MSRMask1_1__Reg1_2__CondCode2_0 3430 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3431 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0 3432 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3433 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0 3434 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3435 // ConvertCustom_cvtThumbMultiply 3436 { CVT_cvtThumbMultiply, 0, CVT_Done }, 3437 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1 3438 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3439 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 3440 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3441 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 3442 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3443 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 3444 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3445 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0 3446 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3447 // Convert__regR8__regR8__imm_95_14__imm_95_0 3448 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3449 // Convert__regR0__regR0__CondCode2_0__reg0 3450 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3451 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 3452 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3453 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0 3454 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3455 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0 3456 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3457 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0 3458 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3459 // Convert__MemImm12Offset2_0 3460 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done }, 3461 // Convert__MemRegOffset3_0 3462 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done }, 3463 // Convert__Imm1_1__CondCode2_0 3464 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3465 // Convert__MemNegImm8Offset2_1__CondCode2_0 3466 { CVT_95_addMemImmOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3467 // Convert__MemUImm12Offset2_1__CondCode2_0 3468 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3469 // Convert__T2MemRegOffset3_1__CondCode2_0 3470 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3471 // Convert__MemPCRelImm121_1__CondCode2_0 3472 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3473 // Convert__CondCode2_0__RegList1_1 3474 { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 3475 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1 3476 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 3477 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2 3478 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 3479 // Convert__imm_95_4__imm_95_14__imm_95_0 3480 { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3481 // Convert__imm_95_4 3482 { CVT_imm_95_4, 0, CVT_Done }, 3483 // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0 3484 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3485 // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0 3486 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3487 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0 3488 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3489 // Convert__SetEndImm1_0 3490 { CVT_95_addImmOperands, 1, CVT_Done }, 3491 // Convert__Imm0_11_0 3492 { CVT_95_addImmOperands, 1, CVT_Done }, 3493 // Convert__imm_95_4__CondCode2_0 3494 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3495 // Convert__imm_95_5__CondCode2_0 3496 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3497 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3 3498 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3499 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0 3500 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3501 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0 3502 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3503 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0 3504 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3505 // Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0 3506 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3507 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0 3508 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addMveSaturateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3509 // Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0 3510 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3511 // Convert__Imm0_311_2 3512 { CVT_95_addImmOperands, 3, CVT_Done }, 3513 // Convert__Imm0_311_1__CondCode2_0 3514 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3515 // Convert__Imm0_311_2__CondCode2_0 3516 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3517 // Convert__Imm0_311_3__CondCode2_0 3518 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3519 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0 3520 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3521 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0 3522 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3523 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0 3524 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3525 // Convert__imm_95_0__imm_95_14__imm_95_0 3526 { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3527 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0 3528 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3529 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0 3530 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3531 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0 3532 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3533 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0 3534 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3535 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0 3536 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3537 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0 3538 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3539 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0 3540 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3541 // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0 3542 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3543 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 3544 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3545 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0 3546 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3547 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 3548 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3549 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0 3550 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3551 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0 3552 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3553 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0 3554 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3555 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0 3556 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3557 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0 3558 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3559 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0 3560 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3561 // Convert__Imm0_2551_3__CondCode2_0 3562 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3563 // Convert__Imm0_2551_1__CondCode2_0 3564 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3565 // Convert__Imm24bit1_1__CondCode2_0 3566 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3567 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 3568 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3569 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0 3570 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3571 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 3572 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3573 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0 3574 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3575 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 3576 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3577 // Convert__MemTBB2_1__CondCode2_0 3578 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3579 // Convert__MemTBH2_1__CondCode2_0 3580 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3581 // Convert__TraceSyncBarrierOpt1_0 3582 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done }, 3583 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0 3584 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3585 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0 3586 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3587 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0 3588 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3589 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0 3590 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3591 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0 3592 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3593 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0 3594 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3595 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0 3596 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3597 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 3598 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3599 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0 3600 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3601 // Convert__Reg1_2__Reg1_3__VPTPredR3_0 3602 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3603 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0 3604 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3605 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0 3606 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3607 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0 3608 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3609 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0 3610 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3611 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0 3612 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3613 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN2_0 3614 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3615 // Convert__Reg1_2__Reg1_3__VPTPredN2_0 3616 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3617 // Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0 3618 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3619 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0 3620 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3621 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0 3622 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3623 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0 3624 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3625 // Convert__Reg1_2__imm_95_0__InvertedExpandImm0_161_3__VPTPredN2_0 3626 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3627 // Convert__Reg1_2__imm_95_0__InvertedExpandImm8_161_3__VPTPredN2_0 3628 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3629 // Convert__Reg1_2__imm_95_0__InvertedExpandImm0_321_3__VPTPredN2_0 3630 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3631 // Convert__Reg1_2__imm_95_0__InvertedExpandImm8_321_3__VPTPredN2_0 3632 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3633 // Convert__Reg1_2__imm_95_0__InvertedExpandImm16_321_3__VPTPredN2_0 3634 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3635 // Convert__Reg1_2__imm_95_0__InvertedExpandImm24_321_3__VPTPredN2_0 3636 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3637 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0 3638 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3639 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0 3640 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3641 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0 3642 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3643 // Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0 3644 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3645 // Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0 3646 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3647 // Convert__Reg1_2__Tie0_1_1__ExpandImm161_3__VPTPredN2_0 3648 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3649 // Convert__Reg1_2__Tie0_1_1__ExpandImm241_3__VPTPredN2_0 3650 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3651 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0 3652 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3653 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0 3654 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3655 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4 3656 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done }, 3657 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0 3658 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationOddOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3659 // Convert__Reg1_2__Reg1_2__CondCode2_0 3660 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3661 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4 3662 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done }, 3663 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5 3664 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 3665 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5 3666 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 3667 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN2_0 3668 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3669 // Convert__Reg1_2__CondCode2_0 3670 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3671 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0 3672 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3673 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0 3674 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3675 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0 3676 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3677 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0 3678 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3679 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0 3680 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3681 // Convert__imm_95_0__Reg1_2__VPTPredN2_0 3682 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3683 // Convert__Reg1_3__Reg1_4__CondCode2_0 3684 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3685 // Convert__Reg1_3__Reg1_4__VPTPredR3_0 3686 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3687 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0 3688 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3689 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0 3690 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3691 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0 3692 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3693 // Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0 3694 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3695 // Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0 3696 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3697 // Convert__Reg1_2__Reg1_3 3698 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3699 // Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0 3700 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3701 // Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0 3702 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_addPowerTwoOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3703 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 3704 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3705 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 3706 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3707 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0 3708 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3709 // Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0 3710 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addPowerTwoOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3711 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0 3712 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3713 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0 3714 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3715 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0 3716 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3717 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0 3718 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3719 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0 3720 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3721 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0 3722 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3723 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0 3724 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3725 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0 3726 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3727 // Convert__Reg1_1__Reg1_2__Reg1_3 3728 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3729 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4 3730 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done }, 3731 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4 3732 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done }, 3733 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3734 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3735 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0 3736 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3737 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0 3738 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3739 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3740 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3741 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0 3742 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3743 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0 3744 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3745 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0 3746 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3747 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3748 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3749 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3750 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3751 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3752 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3753 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3754 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3755 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3756 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3757 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3758 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3759 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3760 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3761 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3762 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3763 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 3764 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3765 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3766 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3767 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0 3768 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3769 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 3770 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3771 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3772 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3773 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3774 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3775 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 3776 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3777 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 3778 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3779 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 3780 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3781 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 3782 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3783 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 3784 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3785 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3786 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3787 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3788 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3789 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3790 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3791 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3792 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3793 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3794 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3795 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 3796 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3797 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3798 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3799 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 3800 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3801 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3802 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3803 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3804 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3805 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0 3806 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3807 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 3808 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3809 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 3810 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3811 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3812 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3813 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0 3814 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3815 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3816 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3817 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3818 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3819 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3820 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3821 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3822 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3823 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3824 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3825 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3826 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3827 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3828 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3829 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0 3830 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3831 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3832 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3833 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3834 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3835 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 3836 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3837 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3838 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3839 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3840 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3841 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3842 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3843 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 3844 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3845 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3846 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3847 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 3848 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3849 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3850 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3851 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3852 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3853 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3854 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3855 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3856 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3857 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3858 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3859 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 3860 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3861 // Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2 3862 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 3863 // Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3 3864 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done }, 3865 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3866 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3867 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3868 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3869 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3870 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3871 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0 3872 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3873 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3874 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3875 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3876 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3877 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3878 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3879 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3880 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3881 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3882 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3883 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3884 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3885 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3886 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3887 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3888 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3889 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3890 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3891 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3892 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3893 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3894 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3895 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3896 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3897 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3898 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3899 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0 3900 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3901 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0 3902 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3903 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0 3904 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3905 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0 3906 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3907 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3908 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3909 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3910 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3911 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3912 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3913 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0 3914 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3915 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3916 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3917 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 3918 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3919 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 3920 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3921 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 3922 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3923 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 3924 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3925 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3926 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3927 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0 3928 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3929 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3930 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3931 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3932 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3933 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 3934 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3935 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3936 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3937 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3938 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3939 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 3940 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3941 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3942 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3943 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 3944 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3945 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3946 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3947 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 3948 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3949 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3950 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3951 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3952 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3953 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3954 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3955 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3956 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3957 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0 3958 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3959 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0 3960 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3961 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0 3962 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3963 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0 3964 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3965 // Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2 3966 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 3967 // Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3 3968 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done }, 3969 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3 3970 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done }, 3971 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2 3972 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 3973 // Convert__MemImm7s4Offset2_2__CondCode2_0 3974 { CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3975 // Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0 3976 { CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3977 // Convert__Reg1_1__AddrMode52_2__CondCode2_0 3978 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3979 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0 3980 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3981 // Convert__Reg1_2__AddrMode52_3__CondCode2_0 3982 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3983 // Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0 3984 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3985 // Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0 3986 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3987 // Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0 3988 { CVT_imm_95_0, 0, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3989 // Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0 3990 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3991 // Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0 3992 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3993 // Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN2_0 3994 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3995 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0 3996 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3997 // Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0 3998 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3999 // Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0 4000 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4001 // Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0 4002 { CVT_95_addMemNoOffsetT2Operands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4003 // Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0 4004 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4005 // Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN2_0 4006 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4007 // Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0 4008 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4009 // Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0 4010 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4011 // Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0 4012 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4013 // Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN2_0 4014 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4015 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0 4016 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4017 // Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0 4018 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4019 // Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0 4020 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4021 // Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0 4022 { CVT_95_addMemNoOffsetT2Operands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4023 // Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN2_0 4024 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4025 // Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0 4026 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4027 // Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN2_0 4028 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4029 // Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0 4030 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4031 // Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0 4032 { CVT_95_addMemNoOffsetT2Operands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4033 // Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0 4034 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4035 // Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0 4036 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4037 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 4038 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4039 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 4040 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4041 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0 4042 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4043 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0 4044 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4045 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0 4046 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4047 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0 4048 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4049 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0 4050 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4051 // Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR3_0 4052 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4053 // Convert__Reg1_2__FPImm1_3__CondCode2_0 4054 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4055 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0 4056 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4057 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0 4058 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4059 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0 4060 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4061 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0 4062 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4063 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0 4064 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4065 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0 4066 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4067 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0 4068 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4069 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0 4070 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4071 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0 4072 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4073 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0 4074 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4075 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0 4076 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4077 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0 4078 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4079 // Convert__Reg1_2__FPImm1_3__VPTPredR3_0 4080 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4081 // Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0 4082 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4083 // Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0 4084 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4085 // Convert__Reg1_2__NEONi64splat1_3__VPTPredR3_0 4086 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4087 // Convert__Reg1_2__NEONi8splat1_3__VPTPredR3_0 4088 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4089 // Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0 4090 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4091 // Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0 4092 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4093 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0 4094 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4095 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0 4096 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4097 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0 4098 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4099 // Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0 4100 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4101 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0 4102 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4103 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0 4104 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4105 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0 4106 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4107 // Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0 4108 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addMVEPairVectorIndexOperands, 3, CVT_95_addMVEPairVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4109 // ConvertCustom_cvtMVEVMOVQtoDReg 4110 { CVT_cvtMVEVMOVQtoDReg, 0, CVT_Done }, 4111 // Convert__Reg1_1__imm_95_0__CondCode2_0 4112 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4113 // Convert__imm_95_0__Reg1_2__CondCode2_0 4114 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4115 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 4116 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4117 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 4118 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4119 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 4120 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4121 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 4122 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4123 // Convert__Reg1_1__Reg1_2__VPTPredR3_0 4124 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4125 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0 4126 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4127 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0 4128 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4129 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0 4130 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4131 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0 4132 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4133 // Convert__imm_95_0__imm_95_0__VPTPredN2_0 4134 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4135 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1 4136 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done }, 4137 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1 4138 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done }, 4139 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2 4140 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 4141 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2 4142 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 4143 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN2_0 4144 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4145 // Convert__ITMask1_0 4146 { CVT_95_addITMaskOperands, 1, CVT_Done }, 4147 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2 4148 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4149 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2 4150 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4151 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2 4152 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4153 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2 4154 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4155 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0 4156 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4157 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0 4158 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4159 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0 4160 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4161 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0 4162 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4163 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0 4164 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4165 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0 4166 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4167 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0 4168 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4169 // Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0 4170 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4171 // Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0 4172 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4173 // Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0 4174 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4175 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0 4176 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4177 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0 4178 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4179 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0 4180 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4181 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0 4182 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4183 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0 4184 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4185 // Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0 4186 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4187 // Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0 4188 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4189 // Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0 4190 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4191 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0 4192 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4193 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0 4194 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4195 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0 4196 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4197 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0 4198 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4199 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0 4200 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4201 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0 4202 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4203 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0 4204 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4205 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0 4206 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4207 // Convert__CondCode2_0__FPDRegListWithVPR1_1 4208 { CVT_95_addCondCodeOperands, 1, CVT_95_addFPDRegListWithVPROperands, 2, CVT_Done }, 4209 // Convert__CondCode2_0__FPSRegListWithVPR1_1 4210 { CVT_95_addCondCodeOperands, 1, CVT_95_addFPSRegListWithVPROperands, 2, CVT_Done }, 4211 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3 4212 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 4213 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4 4214 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done }, 4215 // Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN2_0 4216 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4217 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0 4218 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4219 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0 4220 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4221 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0 4222 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4223 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0 4224 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4225 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0 4226 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4227 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0 4228 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4229 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0 4230 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4231 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0 4232 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4233 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0 4234 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4235 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0 4236 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4237 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN2_0 4238 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4239 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN2_0 4240 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4241 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN2_0 4242 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4243 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN2_0 4244 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4245 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 4246 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4247 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 4248 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4249 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 4250 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4251 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 4252 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4253 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 4254 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4255 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0 4256 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4257 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 4258 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4259 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0 4260 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4261 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 4262 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4263 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0 4264 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4265 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 4266 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4267 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0 4268 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4269 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0 4270 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4271 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 4272 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4273 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 4274 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4275 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0 4276 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4277 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 4278 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4279 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 4280 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4281 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0 4282 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4283 // Convert__VecListTwoMQ1_1__MemNoOffsetT21_2 4284 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 4285 // Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3 4286 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done }, 4287 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 4288 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4289 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 4290 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4291 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 4292 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4293 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 4294 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4295 // Convert__VecListFourMQ1_1__MemNoOffsetT21_2 4296 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 4297 // Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3 4298 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done }, 4299 // Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0 4300 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_imm_95_0, 0, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4301 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0 4302 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4303 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0 4304 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4305 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0 4306 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4307 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0 4308 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4309 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0 4310 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4311 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0 4312 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4313 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0 4314 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4315 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0 4316 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4317 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0 4318 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4319 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0 4320 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4321 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0 4322 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4323 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0 4324 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4325 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0 4326 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4327 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0 4328 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4329 // Convert__imm_95_2__CondCode2_0 4330 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4331 // Convert__imm_95_3__CondCode2_0 4332 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4333 // Convert__Reg1_0__Reg1_1__WLSLabel1_2 4334 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 4335 // Convert__Reg1_1__Reg1_2__WLSLabel1_3 4336 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 4337 // Convert__imm_95_1__CondCode2_0 4338 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4339}; 4340 4341void ARMAsmParser:: 4342convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 4343 const OperandVector &Operands) { 4344 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4345 const uint8_t *Converter = ConversionTable[Kind]; 4346 unsigned OpIdx; 4347 Inst.setOpcode(Opcode); 4348 for (const uint8_t *p = Converter; *p; p+= 2) { 4349 OpIdx = *(p + 1); 4350 switch (*p) { 4351 default: llvm_unreachable("invalid conversion entry!"); 4352 case CVT_Reg: 4353 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 4354 break; 4355 case CVT_Tied: { 4356 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 4357 std::begin(TiedAsmOperandTable)) && 4358 "Tied operand not found"); 4359 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 4360 if (TiedResOpnd != (uint8_t) -1) 4361 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 4362 break; 4363 } 4364 case CVT_95_Reg: 4365 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 4366 break; 4367 case CVT_95_addCCOutOperands: 4368 static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1); 4369 break; 4370 case CVT_95_addCondCodeOperands: 4371 static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2); 4372 break; 4373 case CVT_95_addRegShiftedRegOperands: 4374 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3); 4375 break; 4376 case CVT_95_addModImmOperands: 4377 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1); 4378 break; 4379 case CVT_95_addModImmNotOperands: 4380 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1); 4381 break; 4382 case CVT_95_addRegShiftedImmOperands: 4383 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2); 4384 break; 4385 case CVT_95_addImmOperands: 4386 static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); 4387 break; 4388 case CVT_95_addT2SOImmNotOperands: 4389 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1); 4390 break; 4391 case CVT_95_addImm0_95_4095NegOperands: 4392 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1); 4393 break; 4394 case CVT_95_addImm0_95_508s4Operands: 4395 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1); 4396 break; 4397 case CVT_regSP: 4398 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4399 break; 4400 case CVT_95_addImm0_95_508s4NegOperands: 4401 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1); 4402 break; 4403 case CVT_95_addT2SOImmNegOperands: 4404 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1); 4405 break; 4406 case CVT_95_addThumbModImmNeg8_95_255Operands: 4407 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1); 4408 break; 4409 case CVT_95_addModImmNegOperands: 4410 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1); 4411 break; 4412 case CVT_95_addImm0_95_1020s4Operands: 4413 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1); 4414 break; 4415 case CVT_95_addThumbModImmNeg1_95_7Operands: 4416 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1); 4417 break; 4418 case CVT_95_addUnsignedOffset_95_b8s2Operands: 4419 static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1); 4420 break; 4421 case CVT_95_addAdrLabelOperands: 4422 static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1); 4423 break; 4424 case CVT_95_addARMBranchTargetOperands: 4425 static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1); 4426 break; 4427 case CVT_cvtThumbBranches: 4428 cvtThumbBranches(Inst, Operands); 4429 break; 4430 case CVT_95_addBitfieldOperands: 4431 static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1); 4432 break; 4433 case CVT_95_addITCondCodeOperands: 4434 static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1); 4435 break; 4436 case CVT_imm_95_0: 4437 Inst.addOperand(MCOperand::createImm(0)); 4438 break; 4439 case CVT_95_addThumbBranchTargetOperands: 4440 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1); 4441 break; 4442 case CVT_95_addCoprocNumOperands: 4443 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1); 4444 break; 4445 case CVT_95_addCoprocRegOperands: 4446 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1); 4447 break; 4448 case CVT_95_addITCondCodeInvOperands: 4449 static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeInvOperands(Inst, 1); 4450 break; 4451 case CVT_95_addRegListWithAPSROperands: 4452 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListWithAPSROperands(Inst, 1); 4453 break; 4454 case CVT_95_addProcIFlagsOperands: 4455 static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1); 4456 break; 4457 case CVT_imm_95_20: 4458 Inst.addOperand(MCOperand::createImm(20)); 4459 break; 4460 case CVT_regZR: 4461 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 4462 break; 4463 case CVT_imm_95_12: 4464 Inst.addOperand(MCOperand::createImm(12)); 4465 break; 4466 case CVT_imm_95_15: 4467 Inst.addOperand(MCOperand::createImm(15)); 4468 break; 4469 case CVT_95_addMemBarrierOptOperands: 4470 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1); 4471 break; 4472 case CVT_imm_95_16: 4473 Inst.addOperand(MCOperand::createImm(16)); 4474 break; 4475 case CVT_95_addFPImmOperands: 4476 static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1); 4477 break; 4478 case CVT_95_addDPRRegListOperands: 4479 static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1); 4480 break; 4481 case CVT_imm_95_1: 4482 Inst.addOperand(MCOperand::createImm(1)); 4483 break; 4484 case CVT_95_addInstSyncBarrierOptOperands: 4485 static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1); 4486 break; 4487 case CVT_95_addITMaskOperands: 4488 static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1); 4489 break; 4490 case CVT_95_addMemNoOffsetOperands: 4491 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1); 4492 break; 4493 case CVT_95_addAddrMode5Operands: 4494 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2); 4495 break; 4496 case CVT_95_addCoprocOptionOperands: 4497 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1); 4498 break; 4499 case CVT_95_addPostIdxImm8s4Operands: 4500 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1); 4501 break; 4502 case CVT_95_addRegListOperands: 4503 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1); 4504 break; 4505 case CVT_95_addThumbMemPCOperands: 4506 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1); 4507 break; 4508 case CVT_95_addConstPoolAsmImmOperands: 4509 static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1); 4510 break; 4511 case CVT_95_addMemThumbRIs4Operands: 4512 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2); 4513 break; 4514 case CVT_95_addMemThumbRROperands: 4515 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2); 4516 break; 4517 case CVT_95_addMemThumbSPIOperands: 4518 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2); 4519 break; 4520 case CVT_95_addMemImm12OffsetOperands: 4521 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2); 4522 break; 4523 case CVT_95_addMemImmOffsetOperands: 4524 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImmOffsetOperands(Inst, 2); 4525 break; 4526 case CVT_95_addMemRegOffsetOperands: 4527 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3); 4528 break; 4529 case CVT_95_addMemUImm12OffsetOperands: 4530 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2); 4531 break; 4532 case CVT_95_addT2MemRegOffsetOperands: 4533 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3); 4534 break; 4535 case CVT_95_addMemPCRelImm12Operands: 4536 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1); 4537 break; 4538 case CVT_95_addAM2OffsetImmOperands: 4539 static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2); 4540 break; 4541 case CVT_95_addPostIdxRegShiftedOperands: 4542 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2); 4543 break; 4544 case CVT_95_addMemThumbRIs1Operands: 4545 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2); 4546 break; 4547 case CVT_95_addMemImm8s4OffsetOperands: 4548 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2); 4549 break; 4550 case CVT_95_addAddrMode3Operands: 4551 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3); 4552 break; 4553 case CVT_95_addAM3OffsetOperands: 4554 static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2); 4555 break; 4556 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 4557 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2); 4558 break; 4559 case CVT_95_addMemThumbRIs2Operands: 4560 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2); 4561 break; 4562 case CVT_95_addPostIdxRegOperands: 4563 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2); 4564 break; 4565 case CVT_95_addPostIdxImm8Operands: 4566 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1); 4567 break; 4568 case CVT_reg0: 4569 Inst.addOperand(MCOperand::createReg(0)); 4570 break; 4571 case CVT_regCPSR: 4572 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 4573 break; 4574 case CVT_imm_95_14: 4575 Inst.addOperand(MCOperand::createImm(14)); 4576 break; 4577 case CVT_95_addBankedRegOperands: 4578 static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1); 4579 break; 4580 case CVT_95_addMSRMaskOperands: 4581 static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1); 4582 break; 4583 case CVT_cvtThumbMultiply: 4584 cvtThumbMultiply(Inst, Operands); 4585 break; 4586 case CVT_regR8: 4587 Inst.addOperand(MCOperand::createReg(ARM::R8)); 4588 break; 4589 case CVT_regR0: 4590 Inst.addOperand(MCOperand::createReg(ARM::R0)); 4591 break; 4592 case CVT_95_addPKHASRImmOperands: 4593 static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1); 4594 break; 4595 case CVT_imm_95_4: 4596 Inst.addOperand(MCOperand::createImm(4)); 4597 break; 4598 case CVT_95_addImm1_95_32Operands: 4599 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1); 4600 break; 4601 case CVT_imm_95_5: 4602 Inst.addOperand(MCOperand::createImm(5)); 4603 break; 4604 case CVT_95_addMveSaturateOperands: 4605 static_cast<ARMOperand&>(*Operands[OpIdx]).addMveSaturateOperands(Inst, 1); 4606 break; 4607 case CVT_95_addShifterImmOperands: 4608 static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1); 4609 break; 4610 case CVT_95_addImm1_95_16Operands: 4611 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1); 4612 break; 4613 case CVT_95_addRotImmOperands: 4614 static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1); 4615 break; 4616 case CVT_95_addMemTBBOperands: 4617 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2); 4618 break; 4619 case CVT_95_addMemTBHOperands: 4620 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2); 4621 break; 4622 case CVT_95_addTraceSyncBarrierOptOperands: 4623 static_cast<ARMOperand&>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1); 4624 break; 4625 case CVT_95_addVPTPredNOperands: 4626 static_cast<ARMOperand&>(*Operands[OpIdx]).addVPTPredNOperands(Inst, 2); 4627 break; 4628 case CVT_95_addVPTPredROperands: 4629 static_cast<ARMOperand&>(*Operands[OpIdx]).addVPTPredROperands(Inst, 3); 4630 break; 4631 case CVT_95_addNEONi16splatNotOperands: 4632 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1); 4633 break; 4634 case CVT_95_addNEONi32splatNotOperands: 4635 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1); 4636 break; 4637 case CVT_95_addNEONi16splatOperands: 4638 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1); 4639 break; 4640 case CVT_95_addNEONi32splatOperands: 4641 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1); 4642 break; 4643 case CVT_95_addComplexRotationOddOperands: 4644 static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1); 4645 break; 4646 case CVT_95_addComplexRotationEvenOperands: 4647 static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1); 4648 break; 4649 case CVT_95_addVectorIndex64Operands: 4650 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1); 4651 break; 4652 case CVT_95_addVectorIndex32Operands: 4653 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1); 4654 break; 4655 case CVT_95_addFBits16Operands: 4656 static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1); 4657 break; 4658 case CVT_95_addFBits32Operands: 4659 static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1); 4660 break; 4661 case CVT_95_addPowerTwoOperands: 4662 static_cast<ARMOperand&>(*Operands[OpIdx]).addPowerTwoOperands(Inst, 1); 4663 break; 4664 case CVT_95_addVectorIndex16Operands: 4665 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1); 4666 break; 4667 case CVT_95_addVectorIndex8Operands: 4668 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1); 4669 break; 4670 case CVT_95_addVecListOperands: 4671 static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1); 4672 break; 4673 case CVT_95_addDupAlignedMemory16Operands: 4674 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2); 4675 break; 4676 case CVT_95_addAlignedMemory64or128Operands: 4677 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2); 4678 break; 4679 case CVT_95_addAlignedMemory64or128or256Operands: 4680 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2); 4681 break; 4682 case CVT_95_addAlignedMemory64Operands: 4683 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2); 4684 break; 4685 case CVT_95_addVecListIndexedOperands: 4686 static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2); 4687 break; 4688 case CVT_95_addAlignedMemory16Operands: 4689 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2); 4690 break; 4691 case CVT_95_addDupAlignedMemory32Operands: 4692 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2); 4693 break; 4694 case CVT_95_addAlignedMemory32Operands: 4695 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2); 4696 break; 4697 case CVT_95_addDupAlignedMemoryNoneOperands: 4698 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2); 4699 break; 4700 case CVT_95_addAlignedMemoryNoneOperands: 4701 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2); 4702 break; 4703 case CVT_95_addAlignedMemoryOperands: 4704 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2); 4705 break; 4706 case CVT_95_addDupAlignedMemory64Operands: 4707 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2); 4708 break; 4709 case CVT_95_addMVEVecListOperands: 4710 static_cast<ARMOperand&>(*Operands[OpIdx]).addMVEVecListOperands(Inst, 1); 4711 break; 4712 case CVT_95_addMemNoOffsetT2Operands: 4713 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetT2Operands(Inst, 1); 4714 break; 4715 case CVT_95_addMemNoOffsetT2NoSpOperands: 4716 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetT2NoSpOperands(Inst, 1); 4717 break; 4718 case CVT_95_addDupAlignedMemory64or128Operands: 4719 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2); 4720 break; 4721 case CVT_95_addSPRRegListOperands: 4722 static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1); 4723 break; 4724 case CVT_95_addMemImm7s4OffsetOperands: 4725 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm7s4OffsetOperands(Inst, 2); 4726 break; 4727 case CVT_95_addAddrMode5FP16Operands: 4728 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2); 4729 break; 4730 case CVT_95_addImm7s4Operands: 4731 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm7s4Operands(Inst, 1); 4732 break; 4733 case CVT_95_addMemRegRQOffsetOperands: 4734 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegRQOffsetOperands(Inst, 2); 4735 break; 4736 case CVT_95_addMemNoOffsetTOperands: 4737 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetTOperands(Inst, 1); 4738 break; 4739 case CVT_95_addImm7Shift0Operands: 4740 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm7Shift0Operands(Inst, 1); 4741 break; 4742 case CVT_95_addImm7Shift1Operands: 4743 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm7Shift1Operands(Inst, 1); 4744 break; 4745 case CVT_95_addImm7Shift2Operands: 4746 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm7Shift2Operands(Inst, 1); 4747 break; 4748 case CVT_95_addNEONi32vmovOperands: 4749 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1); 4750 break; 4751 case CVT_95_addNEONvmovi8ReplicateOperands: 4752 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1); 4753 break; 4754 case CVT_95_addNEONvmovi16ReplicateOperands: 4755 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1); 4756 break; 4757 case CVT_95_addNEONi32vmovNegOperands: 4758 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1); 4759 break; 4760 case CVT_95_addNEONvmovi32ReplicateOperands: 4761 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1); 4762 break; 4763 case CVT_95_addNEONi64splatOperands: 4764 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1); 4765 break; 4766 case CVT_95_addNEONi8splatOperands: 4767 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1); 4768 break; 4769 case CVT_95_addMVEVectorIndexOperands: 4770 static_cast<ARMOperand&>(*Operands[OpIdx]).addMVEVectorIndexOperands(Inst, 1); 4771 break; 4772 case CVT_95_addMVEPairVectorIndexOperands: 4773 static_cast<ARMOperand&>(*Operands[OpIdx]).addMVEPairVectorIndexOperands(Inst, 1); 4774 break; 4775 case CVT_cvtMVEVMOVQtoDReg: 4776 cvtMVEVMOVQtoDReg(Inst, Operands); 4777 break; 4778 case CVT_95_addNEONinvi8ReplicateOperands: 4779 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1); 4780 break; 4781 case CVT_95_addFPDRegListWithVPROperands: 4782 static_cast<ARMOperand&>(*Operands[OpIdx]).addFPDRegListWithVPROperands(Inst, 1); 4783 break; 4784 case CVT_95_addFPSRegListWithVPROperands: 4785 static_cast<ARMOperand&>(*Operands[OpIdx]).addFPSRegListWithVPROperands(Inst, 1); 4786 break; 4787 case CVT_imm_95_2: 4788 Inst.addOperand(MCOperand::createImm(2)); 4789 break; 4790 case CVT_imm_95_3: 4791 Inst.addOperand(MCOperand::createImm(3)); 4792 break; 4793 } 4794 } 4795} 4796 4797void ARMAsmParser:: 4798convertToMapAndConstraints(unsigned Kind, 4799 const OperandVector &Operands) { 4800 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4801 unsigned NumMCOperands = 0; 4802 const uint8_t *Converter = ConversionTable[Kind]; 4803 for (const uint8_t *p = Converter; *p; p+= 2) { 4804 switch (*p) { 4805 default: llvm_unreachable("invalid conversion entry!"); 4806 case CVT_Reg: 4807 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4808 Operands[*(p + 1)]->setConstraint("r"); 4809 ++NumMCOperands; 4810 break; 4811 case CVT_Tied: 4812 ++NumMCOperands; 4813 break; 4814 case CVT_95_Reg: 4815 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4816 Operands[*(p + 1)]->setConstraint("r"); 4817 NumMCOperands += 1; 4818 break; 4819 case CVT_95_addCCOutOperands: 4820 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4821 Operands[*(p + 1)]->setConstraint("m"); 4822 NumMCOperands += 1; 4823 break; 4824 case CVT_95_addCondCodeOperands: 4825 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4826 Operands[*(p + 1)]->setConstraint("m"); 4827 NumMCOperands += 2; 4828 break; 4829 case CVT_95_addRegShiftedRegOperands: 4830 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4831 Operands[*(p + 1)]->setConstraint("m"); 4832 NumMCOperands += 3; 4833 break; 4834 case CVT_95_addModImmOperands: 4835 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4836 Operands[*(p + 1)]->setConstraint("m"); 4837 NumMCOperands += 1; 4838 break; 4839 case CVT_95_addModImmNotOperands: 4840 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4841 Operands[*(p + 1)]->setConstraint("m"); 4842 NumMCOperands += 1; 4843 break; 4844 case CVT_95_addRegShiftedImmOperands: 4845 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4846 Operands[*(p + 1)]->setConstraint("m"); 4847 NumMCOperands += 2; 4848 break; 4849 case CVT_95_addImmOperands: 4850 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4851 Operands[*(p + 1)]->setConstraint("m"); 4852 NumMCOperands += 1; 4853 break; 4854 case CVT_95_addT2SOImmNotOperands: 4855 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4856 Operands[*(p + 1)]->setConstraint("m"); 4857 NumMCOperands += 1; 4858 break; 4859 case CVT_95_addImm0_95_4095NegOperands: 4860 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4861 Operands[*(p + 1)]->setConstraint("m"); 4862 NumMCOperands += 1; 4863 break; 4864 case CVT_95_addImm0_95_508s4Operands: 4865 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4866 Operands[*(p + 1)]->setConstraint("m"); 4867 NumMCOperands += 1; 4868 break; 4869 case CVT_regSP: 4870 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4871 Operands[*(p + 1)]->setConstraint("m"); 4872 ++NumMCOperands; 4873 break; 4874 case CVT_95_addImm0_95_508s4NegOperands: 4875 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4876 Operands[*(p + 1)]->setConstraint("m"); 4877 NumMCOperands += 1; 4878 break; 4879 case CVT_95_addT2SOImmNegOperands: 4880 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4881 Operands[*(p + 1)]->setConstraint("m"); 4882 NumMCOperands += 1; 4883 break; 4884 case CVT_95_addThumbModImmNeg8_95_255Operands: 4885 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4886 Operands[*(p + 1)]->setConstraint("m"); 4887 NumMCOperands += 1; 4888 break; 4889 case CVT_95_addModImmNegOperands: 4890 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4891 Operands[*(p + 1)]->setConstraint("m"); 4892 NumMCOperands += 1; 4893 break; 4894 case CVT_95_addImm0_95_1020s4Operands: 4895 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4896 Operands[*(p + 1)]->setConstraint("m"); 4897 NumMCOperands += 1; 4898 break; 4899 case CVT_95_addThumbModImmNeg1_95_7Operands: 4900 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4901 Operands[*(p + 1)]->setConstraint("m"); 4902 NumMCOperands += 1; 4903 break; 4904 case CVT_95_addUnsignedOffset_95_b8s2Operands: 4905 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4906 Operands[*(p + 1)]->setConstraint("m"); 4907 NumMCOperands += 1; 4908 break; 4909 case CVT_95_addAdrLabelOperands: 4910 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4911 Operands[*(p + 1)]->setConstraint("m"); 4912 NumMCOperands += 1; 4913 break; 4914 case CVT_95_addARMBranchTargetOperands: 4915 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4916 Operands[*(p + 1)]->setConstraint("m"); 4917 NumMCOperands += 1; 4918 break; 4919 case CVT_95_addBitfieldOperands: 4920 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4921 Operands[*(p + 1)]->setConstraint("m"); 4922 NumMCOperands += 1; 4923 break; 4924 case CVT_95_addITCondCodeOperands: 4925 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4926 Operands[*(p + 1)]->setConstraint("m"); 4927 NumMCOperands += 1; 4928 break; 4929 case CVT_imm_95_0: 4930 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4931 Operands[*(p + 1)]->setConstraint(""); 4932 ++NumMCOperands; 4933 break; 4934 case CVT_95_addThumbBranchTargetOperands: 4935 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4936 Operands[*(p + 1)]->setConstraint("m"); 4937 NumMCOperands += 1; 4938 break; 4939 case CVT_95_addCoprocNumOperands: 4940 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4941 Operands[*(p + 1)]->setConstraint("m"); 4942 NumMCOperands += 1; 4943 break; 4944 case CVT_95_addCoprocRegOperands: 4945 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4946 Operands[*(p + 1)]->setConstraint("m"); 4947 NumMCOperands += 1; 4948 break; 4949 case CVT_95_addITCondCodeInvOperands: 4950 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4951 Operands[*(p + 1)]->setConstraint("m"); 4952 NumMCOperands += 1; 4953 break; 4954 case CVT_95_addRegListWithAPSROperands: 4955 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4956 Operands[*(p + 1)]->setConstraint("m"); 4957 NumMCOperands += 1; 4958 break; 4959 case CVT_95_addProcIFlagsOperands: 4960 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4961 Operands[*(p + 1)]->setConstraint("m"); 4962 NumMCOperands += 1; 4963 break; 4964 case CVT_imm_95_20: 4965 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4966 Operands[*(p + 1)]->setConstraint(""); 4967 ++NumMCOperands; 4968 break; 4969 case CVT_regZR: 4970 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4971 Operands[*(p + 1)]->setConstraint("m"); 4972 ++NumMCOperands; 4973 break; 4974 case CVT_imm_95_12: 4975 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4976 Operands[*(p + 1)]->setConstraint(""); 4977 ++NumMCOperands; 4978 break; 4979 case CVT_imm_95_15: 4980 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4981 Operands[*(p + 1)]->setConstraint(""); 4982 ++NumMCOperands; 4983 break; 4984 case CVT_95_addMemBarrierOptOperands: 4985 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4986 Operands[*(p + 1)]->setConstraint("m"); 4987 NumMCOperands += 1; 4988 break; 4989 case CVT_imm_95_16: 4990 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4991 Operands[*(p + 1)]->setConstraint(""); 4992 ++NumMCOperands; 4993 break; 4994 case CVT_95_addFPImmOperands: 4995 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4996 Operands[*(p + 1)]->setConstraint("m"); 4997 NumMCOperands += 1; 4998 break; 4999 case CVT_95_addDPRRegListOperands: 5000 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5001 Operands[*(p + 1)]->setConstraint("m"); 5002 NumMCOperands += 1; 5003 break; 5004 case CVT_imm_95_1: 5005 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5006 Operands[*(p + 1)]->setConstraint(""); 5007 ++NumMCOperands; 5008 break; 5009 case CVT_95_addInstSyncBarrierOptOperands: 5010 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5011 Operands[*(p + 1)]->setConstraint("m"); 5012 NumMCOperands += 1; 5013 break; 5014 case CVT_95_addITMaskOperands: 5015 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5016 Operands[*(p + 1)]->setConstraint("m"); 5017 NumMCOperands += 1; 5018 break; 5019 case CVT_95_addMemNoOffsetOperands: 5020 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5021 Operands[*(p + 1)]->setConstraint("m"); 5022 NumMCOperands += 1; 5023 break; 5024 case CVT_95_addAddrMode5Operands: 5025 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5026 Operands[*(p + 1)]->setConstraint("m"); 5027 NumMCOperands += 2; 5028 break; 5029 case CVT_95_addCoprocOptionOperands: 5030 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5031 Operands[*(p + 1)]->setConstraint("m"); 5032 NumMCOperands += 1; 5033 break; 5034 case CVT_95_addPostIdxImm8s4Operands: 5035 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5036 Operands[*(p + 1)]->setConstraint("m"); 5037 NumMCOperands += 1; 5038 break; 5039 case CVT_95_addRegListOperands: 5040 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5041 Operands[*(p + 1)]->setConstraint("m"); 5042 NumMCOperands += 1; 5043 break; 5044 case CVT_95_addThumbMemPCOperands: 5045 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5046 Operands[*(p + 1)]->setConstraint("m"); 5047 NumMCOperands += 1; 5048 break; 5049 case CVT_95_addConstPoolAsmImmOperands: 5050 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5051 Operands[*(p + 1)]->setConstraint("m"); 5052 NumMCOperands += 1; 5053 break; 5054 case CVT_95_addMemThumbRIs4Operands: 5055 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5056 Operands[*(p + 1)]->setConstraint("m"); 5057 NumMCOperands += 2; 5058 break; 5059 case CVT_95_addMemThumbRROperands: 5060 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5061 Operands[*(p + 1)]->setConstraint("m"); 5062 NumMCOperands += 2; 5063 break; 5064 case CVT_95_addMemThumbSPIOperands: 5065 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5066 Operands[*(p + 1)]->setConstraint("m"); 5067 NumMCOperands += 2; 5068 break; 5069 case CVT_95_addMemImm12OffsetOperands: 5070 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5071 Operands[*(p + 1)]->setConstraint("m"); 5072 NumMCOperands += 2; 5073 break; 5074 case CVT_95_addMemImmOffsetOperands: 5075 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5076 Operands[*(p + 1)]->setConstraint("m"); 5077 NumMCOperands += 2; 5078 break; 5079 case CVT_95_addMemRegOffsetOperands: 5080 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5081 Operands[*(p + 1)]->setConstraint("m"); 5082 NumMCOperands += 3; 5083 break; 5084 case CVT_95_addMemUImm12OffsetOperands: 5085 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5086 Operands[*(p + 1)]->setConstraint("m"); 5087 NumMCOperands += 2; 5088 break; 5089 case CVT_95_addT2MemRegOffsetOperands: 5090 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5091 Operands[*(p + 1)]->setConstraint("m"); 5092 NumMCOperands += 3; 5093 break; 5094 case CVT_95_addMemPCRelImm12Operands: 5095 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5096 Operands[*(p + 1)]->setConstraint("m"); 5097 NumMCOperands += 1; 5098 break; 5099 case CVT_95_addAM2OffsetImmOperands: 5100 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5101 Operands[*(p + 1)]->setConstraint("m"); 5102 NumMCOperands += 2; 5103 break; 5104 case CVT_95_addPostIdxRegShiftedOperands: 5105 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5106 Operands[*(p + 1)]->setConstraint("m"); 5107 NumMCOperands += 2; 5108 break; 5109 case CVT_95_addMemThumbRIs1Operands: 5110 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5111 Operands[*(p + 1)]->setConstraint("m"); 5112 NumMCOperands += 2; 5113 break; 5114 case CVT_95_addMemImm8s4OffsetOperands: 5115 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5116 Operands[*(p + 1)]->setConstraint("m"); 5117 NumMCOperands += 2; 5118 break; 5119 case CVT_95_addAddrMode3Operands: 5120 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5121 Operands[*(p + 1)]->setConstraint("m"); 5122 NumMCOperands += 3; 5123 break; 5124 case CVT_95_addAM3OffsetOperands: 5125 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5126 Operands[*(p + 1)]->setConstraint("m"); 5127 NumMCOperands += 2; 5128 break; 5129 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 5130 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5131 Operands[*(p + 1)]->setConstraint("m"); 5132 NumMCOperands += 2; 5133 break; 5134 case CVT_95_addMemThumbRIs2Operands: 5135 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5136 Operands[*(p + 1)]->setConstraint("m"); 5137 NumMCOperands += 2; 5138 break; 5139 case CVT_95_addPostIdxRegOperands: 5140 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5141 Operands[*(p + 1)]->setConstraint("m"); 5142 NumMCOperands += 2; 5143 break; 5144 case CVT_95_addPostIdxImm8Operands: 5145 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5146 Operands[*(p + 1)]->setConstraint("m"); 5147 NumMCOperands += 1; 5148 break; 5149 case CVT_reg0: 5150 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5151 Operands[*(p + 1)]->setConstraint("m"); 5152 ++NumMCOperands; 5153 break; 5154 case CVT_regCPSR: 5155 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5156 Operands[*(p + 1)]->setConstraint("m"); 5157 ++NumMCOperands; 5158 break; 5159 case CVT_imm_95_14: 5160 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5161 Operands[*(p + 1)]->setConstraint(""); 5162 ++NumMCOperands; 5163 break; 5164 case CVT_95_addBankedRegOperands: 5165 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5166 Operands[*(p + 1)]->setConstraint("m"); 5167 NumMCOperands += 1; 5168 break; 5169 case CVT_95_addMSRMaskOperands: 5170 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5171 Operands[*(p + 1)]->setConstraint("m"); 5172 NumMCOperands += 1; 5173 break; 5174 case CVT_regR8: 5175 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5176 Operands[*(p + 1)]->setConstraint("m"); 5177 ++NumMCOperands; 5178 break; 5179 case CVT_regR0: 5180 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5181 Operands[*(p + 1)]->setConstraint("m"); 5182 ++NumMCOperands; 5183 break; 5184 case CVT_95_addPKHASRImmOperands: 5185 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5186 Operands[*(p + 1)]->setConstraint("m"); 5187 NumMCOperands += 1; 5188 break; 5189 case CVT_imm_95_4: 5190 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5191 Operands[*(p + 1)]->setConstraint(""); 5192 ++NumMCOperands; 5193 break; 5194 case CVT_95_addImm1_95_32Operands: 5195 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5196 Operands[*(p + 1)]->setConstraint("m"); 5197 NumMCOperands += 1; 5198 break; 5199 case CVT_imm_95_5: 5200 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5201 Operands[*(p + 1)]->setConstraint(""); 5202 ++NumMCOperands; 5203 break; 5204 case CVT_95_addMveSaturateOperands: 5205 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5206 Operands[*(p + 1)]->setConstraint("m"); 5207 NumMCOperands += 1; 5208 break; 5209 case CVT_95_addShifterImmOperands: 5210 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5211 Operands[*(p + 1)]->setConstraint("m"); 5212 NumMCOperands += 1; 5213 break; 5214 case CVT_95_addImm1_95_16Operands: 5215 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5216 Operands[*(p + 1)]->setConstraint("m"); 5217 NumMCOperands += 1; 5218 break; 5219 case CVT_95_addRotImmOperands: 5220 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5221 Operands[*(p + 1)]->setConstraint("m"); 5222 NumMCOperands += 1; 5223 break; 5224 case CVT_95_addMemTBBOperands: 5225 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5226 Operands[*(p + 1)]->setConstraint("m"); 5227 NumMCOperands += 2; 5228 break; 5229 case CVT_95_addMemTBHOperands: 5230 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5231 Operands[*(p + 1)]->setConstraint("m"); 5232 NumMCOperands += 2; 5233 break; 5234 case CVT_95_addTraceSyncBarrierOptOperands: 5235 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5236 Operands[*(p + 1)]->setConstraint("m"); 5237 NumMCOperands += 1; 5238 break; 5239 case CVT_95_addVPTPredNOperands: 5240 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5241 Operands[*(p + 1)]->setConstraint("m"); 5242 NumMCOperands += 2; 5243 break; 5244 case CVT_95_addVPTPredROperands: 5245 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5246 Operands[*(p + 1)]->setConstraint("m"); 5247 NumMCOperands += 3; 5248 break; 5249 case CVT_95_addNEONi16splatNotOperands: 5250 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5251 Operands[*(p + 1)]->setConstraint("m"); 5252 NumMCOperands += 1; 5253 break; 5254 case CVT_95_addNEONi32splatNotOperands: 5255 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5256 Operands[*(p + 1)]->setConstraint("m"); 5257 NumMCOperands += 1; 5258 break; 5259 case CVT_95_addNEONi16splatOperands: 5260 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5261 Operands[*(p + 1)]->setConstraint("m"); 5262 NumMCOperands += 1; 5263 break; 5264 case CVT_95_addNEONi32splatOperands: 5265 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5266 Operands[*(p + 1)]->setConstraint("m"); 5267 NumMCOperands += 1; 5268 break; 5269 case CVT_95_addComplexRotationOddOperands: 5270 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5271 Operands[*(p + 1)]->setConstraint("m"); 5272 NumMCOperands += 1; 5273 break; 5274 case CVT_95_addComplexRotationEvenOperands: 5275 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5276 Operands[*(p + 1)]->setConstraint("m"); 5277 NumMCOperands += 1; 5278 break; 5279 case CVT_95_addVectorIndex64Operands: 5280 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5281 Operands[*(p + 1)]->setConstraint("m"); 5282 NumMCOperands += 1; 5283 break; 5284 case CVT_95_addVectorIndex32Operands: 5285 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5286 Operands[*(p + 1)]->setConstraint("m"); 5287 NumMCOperands += 1; 5288 break; 5289 case CVT_95_addFBits16Operands: 5290 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5291 Operands[*(p + 1)]->setConstraint("m"); 5292 NumMCOperands += 1; 5293 break; 5294 case CVT_95_addFBits32Operands: 5295 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5296 Operands[*(p + 1)]->setConstraint("m"); 5297 NumMCOperands += 1; 5298 break; 5299 case CVT_95_addPowerTwoOperands: 5300 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5301 Operands[*(p + 1)]->setConstraint("m"); 5302 NumMCOperands += 1; 5303 break; 5304 case CVT_95_addVectorIndex16Operands: 5305 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5306 Operands[*(p + 1)]->setConstraint("m"); 5307 NumMCOperands += 1; 5308 break; 5309 case CVT_95_addVectorIndex8Operands: 5310 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5311 Operands[*(p + 1)]->setConstraint("m"); 5312 NumMCOperands += 1; 5313 break; 5314 case CVT_95_addVecListOperands: 5315 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5316 Operands[*(p + 1)]->setConstraint("m"); 5317 NumMCOperands += 1; 5318 break; 5319 case CVT_95_addDupAlignedMemory16Operands: 5320 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5321 Operands[*(p + 1)]->setConstraint("m"); 5322 NumMCOperands += 2; 5323 break; 5324 case CVT_95_addAlignedMemory64or128Operands: 5325 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5326 Operands[*(p + 1)]->setConstraint("m"); 5327 NumMCOperands += 2; 5328 break; 5329 case CVT_95_addAlignedMemory64or128or256Operands: 5330 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5331 Operands[*(p + 1)]->setConstraint("m"); 5332 NumMCOperands += 2; 5333 break; 5334 case CVT_95_addAlignedMemory64Operands: 5335 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5336 Operands[*(p + 1)]->setConstraint("m"); 5337 NumMCOperands += 2; 5338 break; 5339 case CVT_95_addVecListIndexedOperands: 5340 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5341 Operands[*(p + 1)]->setConstraint("m"); 5342 NumMCOperands += 2; 5343 break; 5344 case CVT_95_addAlignedMemory16Operands: 5345 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5346 Operands[*(p + 1)]->setConstraint("m"); 5347 NumMCOperands += 2; 5348 break; 5349 case CVT_95_addDupAlignedMemory32Operands: 5350 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5351 Operands[*(p + 1)]->setConstraint("m"); 5352 NumMCOperands += 2; 5353 break; 5354 case CVT_95_addAlignedMemory32Operands: 5355 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5356 Operands[*(p + 1)]->setConstraint("m"); 5357 NumMCOperands += 2; 5358 break; 5359 case CVT_95_addDupAlignedMemoryNoneOperands: 5360 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5361 Operands[*(p + 1)]->setConstraint("m"); 5362 NumMCOperands += 2; 5363 break; 5364 case CVT_95_addAlignedMemoryNoneOperands: 5365 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5366 Operands[*(p + 1)]->setConstraint("m"); 5367 NumMCOperands += 2; 5368 break; 5369 case CVT_95_addAlignedMemoryOperands: 5370 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5371 Operands[*(p + 1)]->setConstraint("m"); 5372 NumMCOperands += 2; 5373 break; 5374 case CVT_95_addDupAlignedMemory64Operands: 5375 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5376 Operands[*(p + 1)]->setConstraint("m"); 5377 NumMCOperands += 2; 5378 break; 5379 case CVT_95_addMVEVecListOperands: 5380 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5381 Operands[*(p + 1)]->setConstraint("m"); 5382 NumMCOperands += 1; 5383 break; 5384 case CVT_95_addMemNoOffsetT2Operands: 5385 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5386 Operands[*(p + 1)]->setConstraint("m"); 5387 NumMCOperands += 1; 5388 break; 5389 case CVT_95_addMemNoOffsetT2NoSpOperands: 5390 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5391 Operands[*(p + 1)]->setConstraint("m"); 5392 NumMCOperands += 1; 5393 break; 5394 case CVT_95_addDupAlignedMemory64or128Operands: 5395 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5396 Operands[*(p + 1)]->setConstraint("m"); 5397 NumMCOperands += 2; 5398 break; 5399 case CVT_95_addSPRRegListOperands: 5400 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5401 Operands[*(p + 1)]->setConstraint("m"); 5402 NumMCOperands += 1; 5403 break; 5404 case CVT_95_addMemImm7s4OffsetOperands: 5405 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5406 Operands[*(p + 1)]->setConstraint("m"); 5407 NumMCOperands += 2; 5408 break; 5409 case CVT_95_addAddrMode5FP16Operands: 5410 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5411 Operands[*(p + 1)]->setConstraint("m"); 5412 NumMCOperands += 2; 5413 break; 5414 case CVT_95_addImm7s4Operands: 5415 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5416 Operands[*(p + 1)]->setConstraint("m"); 5417 NumMCOperands += 1; 5418 break; 5419 case CVT_95_addMemRegRQOffsetOperands: 5420 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5421 Operands[*(p + 1)]->setConstraint("m"); 5422 NumMCOperands += 2; 5423 break; 5424 case CVT_95_addMemNoOffsetTOperands: 5425 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5426 Operands[*(p + 1)]->setConstraint("m"); 5427 NumMCOperands += 1; 5428 break; 5429 case CVT_95_addImm7Shift0Operands: 5430 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5431 Operands[*(p + 1)]->setConstraint("m"); 5432 NumMCOperands += 1; 5433 break; 5434 case CVT_95_addImm7Shift1Operands: 5435 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5436 Operands[*(p + 1)]->setConstraint("m"); 5437 NumMCOperands += 1; 5438 break; 5439 case CVT_95_addImm7Shift2Operands: 5440 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5441 Operands[*(p + 1)]->setConstraint("m"); 5442 NumMCOperands += 1; 5443 break; 5444 case CVT_95_addNEONi32vmovOperands: 5445 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5446 Operands[*(p + 1)]->setConstraint("m"); 5447 NumMCOperands += 1; 5448 break; 5449 case CVT_95_addNEONvmovi8ReplicateOperands: 5450 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5451 Operands[*(p + 1)]->setConstraint("m"); 5452 NumMCOperands += 1; 5453 break; 5454 case CVT_95_addNEONvmovi16ReplicateOperands: 5455 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5456 Operands[*(p + 1)]->setConstraint("m"); 5457 NumMCOperands += 1; 5458 break; 5459 case CVT_95_addNEONi32vmovNegOperands: 5460 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5461 Operands[*(p + 1)]->setConstraint("m"); 5462 NumMCOperands += 1; 5463 break; 5464 case CVT_95_addNEONvmovi32ReplicateOperands: 5465 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5466 Operands[*(p + 1)]->setConstraint("m"); 5467 NumMCOperands += 1; 5468 break; 5469 case CVT_95_addNEONi64splatOperands: 5470 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5471 Operands[*(p + 1)]->setConstraint("m"); 5472 NumMCOperands += 1; 5473 break; 5474 case CVT_95_addNEONi8splatOperands: 5475 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5476 Operands[*(p + 1)]->setConstraint("m"); 5477 NumMCOperands += 1; 5478 break; 5479 case CVT_95_addMVEVectorIndexOperands: 5480 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5481 Operands[*(p + 1)]->setConstraint("m"); 5482 NumMCOperands += 1; 5483 break; 5484 case CVT_95_addMVEPairVectorIndexOperands: 5485 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5486 Operands[*(p + 1)]->setConstraint("m"); 5487 NumMCOperands += 1; 5488 break; 5489 case CVT_95_addNEONinvi8ReplicateOperands: 5490 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5491 Operands[*(p + 1)]->setConstraint("m"); 5492 NumMCOperands += 1; 5493 break; 5494 case CVT_95_addFPDRegListWithVPROperands: 5495 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5496 Operands[*(p + 1)]->setConstraint("m"); 5497 NumMCOperands += 1; 5498 break; 5499 case CVT_95_addFPSRegListWithVPROperands: 5500 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5501 Operands[*(p + 1)]->setConstraint("m"); 5502 NumMCOperands += 1; 5503 break; 5504 case CVT_imm_95_2: 5505 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5506 Operands[*(p + 1)]->setConstraint(""); 5507 ++NumMCOperands; 5508 break; 5509 case CVT_imm_95_3: 5510 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5511 Operands[*(p + 1)]->setConstraint(""); 5512 ++NumMCOperands; 5513 break; 5514 } 5515 } 5516} 5517 5518namespace { 5519 5520/// MatchClassKind - The kinds of classes which participate in 5521/// instruction matching. 5522enum MatchClassKind { 5523 InvalidMatchClass = 0, 5524 OptionalMatchClass = 1, 5525 MCK__DOT_d, // '.d' 5526 MCK__DOT_f, // '.f' 5527 MCK__DOT_s16, // '.s16' 5528 MCK__DOT_s32, // '.s32' 5529 MCK__DOT_s64, // '.s64' 5530 MCK__DOT_s8, // '.s8' 5531 MCK__DOT_u16, // '.u16' 5532 MCK__DOT_u32, // '.u32' 5533 MCK__DOT_u64, // '.u64' 5534 MCK__DOT_u8, // '.u8' 5535 MCK__DOT_f32, // '.f32' 5536 MCK__DOT_f64, // '.f64' 5537 MCK__DOT_i16, // '.i16' 5538 MCK__DOT_i32, // '.i32' 5539 MCK__DOT_i64, // '.i64' 5540 MCK__DOT_i8, // '.i8' 5541 MCK__DOT_p16, // '.p16' 5542 MCK__DOT_p8, // '.p8' 5543 MCK__EXCLAIM_, // '!' 5544 MCK__HASH_0, // '#0' 5545 MCK__HASH_16, // '#16' 5546 MCK__HASH_8, // '#8' 5547 MCK__DOT_16, // '.16' 5548 MCK__DOT_32, // '.32' 5549 MCK__DOT_64, // '.64' 5550 MCK__DOT_8, // '.8' 5551 MCK__DOT_f16, // '.f16' 5552 MCK__DOT_p64, // '.p64' 5553 MCK__DOT_w, // '.w' 5554 MCK__91_, // '[' 5555 MCK__93_, // ']' 5556 MCK__94_, // '^' 5557 MCK__123_, // '{' 5558 MCK__125_, // '}' 5559 MCK_LAST_TOKEN = MCK__125_, 5560 MCK_Reg94, // derived register class 5561 MCK_Reg78, // derived register class 5562 MCK_Reg23, // derived register class 5563 MCK_APSR, // register class 'APSR' 5564 MCK_APSR_NZCV, // register class 'APSR_NZCV' 5565 MCK_CCR, // register class 'CCR,CPSR' 5566 MCK_FPCXTNS, // register class 'FPCXTNS' 5567 MCK_FPCXTS, // register class 'FPCXTS' 5568 MCK_FPEXC, // register class 'FPEXC' 5569 MCK_FPINST, // register class 'FPINST' 5570 MCK_FPINST2, // register class 'FPINST2' 5571 MCK_FPSCR, // register class 'FPSCR' 5572 MCK_FPSCR_NZCVQC, // register class 'FPSCR_NZCVQC' 5573 MCK_FPSID, // register class 'FPSID' 5574 MCK_GPRlr, // register class 'GPRlr,LR' 5575 MCK_GPRsp, // register class 'GPRsp,SP' 5576 MCK_MVFR0, // register class 'MVFR0' 5577 MCK_MVFR1, // register class 'MVFR1' 5578 MCK_MVFR2, // register class 'MVFR2' 5579 MCK_P0, // register class 'P0' 5580 MCK_PC, // register class 'PC' 5581 MCK_SPSR, // register class 'SPSR' 5582 MCK_VCCR, // register class 'VCCR,VPR' 5583 MCK_cl_FPSCR_NZCV, // register class 'cl_FPSCR_NZCV' 5584 MCK_Reg119, // derived register class 5585 MCK_Reg92, // derived register class 5586 MCK_Reg87, // derived register class 5587 MCK_Reg79, // derived register class 5588 MCK_Reg22, // derived register class 5589 MCK_Reg15, // derived register class 5590 MCK_Reg11, // derived register class 5591 MCK_Reg120, // derived register class 5592 MCK_Reg107, // derived register class 5593 MCK_Reg102, // derived register class 5594 MCK_Reg93, // derived register class 5595 MCK_Reg91, // derived register class 5596 MCK_Reg80, // derived register class 5597 MCK_Reg64, // derived register class 5598 MCK_Reg14, // derived register class 5599 MCK_Reg121, // derived register class 5600 MCK_Reg112, // derived register class 5601 MCK_Reg108, // derived register class 5602 MCK_Reg103, // derived register class 5603 MCK_Reg88, // derived register class 5604 MCK_Reg81, // derived register class 5605 MCK_Reg65, // derived register class 5606 MCK_Reg21, // derived register class 5607 MCK_Reg16, // derived register class 5608 MCK_Reg12, // derived register class 5609 MCK_Reg0, // derived register class 5610 MCK_QPR_8, // register class 'QPR_8' 5611 MCK_Reg82, // derived register class 5612 MCK_Reg76, // derived register class 5613 MCK_tcGPR, // register class 'tcGPR' 5614 MCK_Reg122, // derived register class 5615 MCK_Reg113, // derived register class 5616 MCK_Reg95, // derived register class 5617 MCK_Reg83, // derived register class 5618 MCK_Reg77, // derived register class 5619 MCK_Reg59, // derived register class 5620 MCK_Reg20, // derived register class 5621 MCK_GPRPairnosp, // register class 'GPRPairnosp' 5622 MCK_tGPROdd, // register class 'tGPROdd' 5623 MCK_Reg123, // derived register class 5624 MCK_Reg109, // derived register class 5625 MCK_Reg104, // derived register class 5626 MCK_Reg96, // derived register class 5627 MCK_Reg84, // derived register class 5628 MCK_Reg74, // derived register class 5629 MCK_Reg66, // derived register class 5630 MCK_Reg39, // derived register class 5631 MCK_Reg18, // derived register class 5632 MCK_GPRPair, // register class 'GPRPair' 5633 MCK_Reg124, // derived register class 5634 MCK_Reg114, // derived register class 5635 MCK_Reg110, // derived register class 5636 MCK_Reg105, // derived register class 5637 MCK_Reg97, // derived register class 5638 MCK_Reg85, // derived register class 5639 MCK_Reg75, // derived register class 5640 MCK_Reg67, // derived register class 5641 MCK_Reg60, // derived register class 5642 MCK_Reg40, // derived register class 5643 MCK_DPR_8, // register class 'DPR_8' 5644 MCK_MQPR, // register class 'MQPR,QPR_VFP2' 5645 MCK_hGPR, // register class 'hGPR' 5646 MCK_tGPR, // register class 'tGPR' 5647 MCK_tGPREven, // register class 'tGPREven' 5648 MCK_tGPRwithpc, // register class 'tGPRwithpc' 5649 MCK_Reg115, // derived register class 5650 MCK_Reg72, // derived register class 5651 MCK_QQQQPR, // register class 'QQQQPR' 5652 MCK_Reg125, // derived register class 5653 MCK_Reg116, // derived register class 5654 MCK_Reg98, // derived register class 5655 MCK_Reg73, // derived register class 5656 MCK_Reg61, // derived register class 5657 MCK_rGPR, // register class 'rGPR' 5658 MCK_Reg111, // derived register class 5659 MCK_Reg106, // derived register class 5660 MCK_Reg99, // derived register class 5661 MCK_Reg70, // derived register class 5662 MCK_Reg37, // derived register class 5663 MCK_GPRnopc, // register class 'GPRnopc' 5664 MCK_GPRwithAPSRnosp, // register class 'GPRwithAPSRnosp' 5665 MCK_GPRwithZRnosp, // register class 'GPRwithZRnosp' 5666 MCK_QQPR, // register class 'QQPR' 5667 MCK_Reg117, // derived register class 5668 MCK_Reg100, // derived register class 5669 MCK_Reg71, // derived register class 5670 MCK_Reg62, // derived register class 5671 MCK_Reg38, // derived register class 5672 MCK_DPR_VFP2, // register class 'DPR_VFP2' 5673 MCK_GPR, // register class 'GPR' 5674 MCK_GPRwithAPSR, // register class 'GPRwithAPSR' 5675 MCK_GPRwithZR, // register class 'GPRwithZR' 5676 MCK_QPR, // register class 'QPR' 5677 MCK_SPR_8, // register class 'SPR_8' 5678 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc' 5679 MCK_DQuad, // register class 'DQuad' 5680 MCK_DPairSpc, // register class 'DPairSpc' 5681 MCK_DTriple, // register class 'DTriple' 5682 MCK_DPair, // register class 'DPair' 5683 MCK_DPR, // register class 'DPR' 5684 MCK_HPR, // register class 'HPR,SPR' 5685 MCK_FPWithVPR, // register class 'FPWithVPR' 5686 MCK_LAST_REGISTER = MCK_FPWithVPR, 5687 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand' 5688 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand' 5689 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget' 5690 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand' 5691 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand' 5692 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand' 5693 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand' 5694 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand' 5695 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand' 5696 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand' 5697 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand' 5698 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand' 5699 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand' 5700 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand' 5701 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand' 5702 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand' 5703 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand' 5704 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand' 5705 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand' 5706 MCK_BankedReg, // user defined class 'BankedRegOperand' 5707 MCK_Bitfield, // user defined class 'BitfieldAsmOperand' 5708 MCK_CCOut, // user defined class 'CCOutOperand' 5709 MCK_CondCode, // user defined class 'CondCodeOperand' 5710 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand' 5711 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand' 5712 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand' 5713 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand' 5714 MCK_FPDRegListWithVPR, // user defined class 'FPDRegListWithVPRAsmOperand' 5715 MCK_FPImm, // user defined class 'FPImmOperand' 5716 MCK_FPSRegListWithVPR, // user defined class 'FPSRegListWithVPRAsmOperand' 5717 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand' 5718 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand' 5719 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand' 5720 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand' 5721 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand' 5722 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand' 5723 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand' 5724 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand' 5725 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand' 5726 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand' 5727 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand' 5728 MCK_Imm16, // user defined class 'Imm16AsmOperand' 5729 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand' 5730 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand' 5731 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand' 5732 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand' 5733 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand' 5734 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand' 5735 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand' 5736 MCK_Imm32, // user defined class 'Imm32AsmOperand' 5737 MCK_Imm8, // user defined class 'Imm8AsmOperand' 5738 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand' 5739 MCK_Imm, // user defined class 'ImmAsmOperand' 5740 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand' 5741 MCK_MSRMask, // user defined class 'MSRMaskOperand' 5742 MCK_MVEShiftImm1_15, // user defined class 'MVEShiftImm1_15AsmOperand' 5743 MCK_MVEShiftImm1_7, // user defined class 'MVEShiftImm1_7AsmOperand' 5744 MCK_VIDUP_imm, // user defined class 'MVE_VIDUP_imm_asmoperand' 5745 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand' 5746 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand' 5747 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand' 5748 MCK_MemImm7Shift0Offset, // user defined class 'MemImm7Shift0OffsetAsmOperand' 5749 MCK_MemImm7Shift0OffsetWB, // user defined class 'MemImm7Shift0OffsetWBAsmOperand' 5750 MCK_MemImm7Shift1Offset, // user defined class 'MemImm7Shift1OffsetAsmOperand' 5751 MCK_MemImm7Shift1OffsetWB, // user defined class 'MemImm7Shift1OffsetWBAsmOperand' 5752 MCK_MemImm7Shift2Offset, // user defined class 'MemImm7Shift2OffsetAsmOperand' 5753 MCK_MemImm7Shift2OffsetWB, // user defined class 'MemImm7Shift2OffsetWBAsmOperand' 5754 MCK_MemImm7s4Offset, // user defined class 'MemImm7s4OffsetAsmOperand' 5755 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand' 5756 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand' 5757 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand' 5758 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand' 5759 MCK_MemNoOffsetT2, // user defined class 'MemNoOffsetT2AsmOperand' 5760 MCK_MemNoOffsetT2NoSp, // user defined class 'MemNoOffsetT2NoSpAsmOperand' 5761 MCK_MemNoOffsetT, // user defined class 'MemNoOffsetTAsmOperand' 5762 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand' 5763 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand' 5764 MCK_MemRegQS2Offset, // user defined class 'MemRegQS2OffsetAsmOperand' 5765 MCK_MemRegQS3Offset, // user defined class 'MemRegQS3OffsetAsmOperand' 5766 MCK_MemRegRQS0Offset, // user defined class 'MemRegRQS0OffsetAsmOperand' 5767 MCK_MemRegRQS1Offset, // user defined class 'MemRegRQS1OffsetAsmOperand' 5768 MCK_MemRegRQS2Offset, // user defined class 'MemRegRQS2OffsetAsmOperand' 5769 MCK_MemRegRQS3Offset, // user defined class 'MemRegRQS3OffsetAsmOperand' 5770 MCK_ModImm, // user defined class 'ModImmAsmOperand' 5771 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand' 5772 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand' 5773 MCK_MveSaturate, // user defined class 'MveSaturateOperand' 5774 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand' 5775 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand' 5776 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand' 5777 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand' 5778 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand' 5779 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand' 5780 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand' 5781 MCK_RegList, // user defined class 'RegListAsmOperand' 5782 MCK_RegListWithAPSR, // user defined class 'RegListWithAPSRAsmOperand' 5783 MCK_RotImm, // user defined class 'RotImmAsmOperand' 5784 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand' 5785 MCK_SetEndImm, // user defined class 'SetEndAsmOperand' 5786 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand' 5787 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand' 5788 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand' 5789 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget' 5790 MCK_ThumbMemPC, // user defined class 'ThumbMemPC' 5791 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand' 5792 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand' 5793 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand' 5794 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand' 5795 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2' 5796 MCK_VPTPredN, // user defined class 'VPTPredNOperand' 5797 MCK_VPTPredR, // user defined class 'VPTPredROperand' 5798 MCK_VecListTwoMQ, // user defined class 'VecList2QAsmOperand' 5799 MCK_VecListFourMQ, // user defined class 'VecList4QAsmOperand' 5800 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand' 5801 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand' 5802 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand' 5803 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand' 5804 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand' 5805 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand' 5806 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand' 5807 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand' 5808 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand' 5809 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand' 5810 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand' 5811 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand' 5812 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand' 5813 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand' 5814 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand' 5815 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand' 5816 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand' 5817 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand' 5818 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand' 5819 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand' 5820 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand' 5821 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand' 5822 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand' 5823 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand' 5824 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand' 5825 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand' 5826 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand' 5827 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand' 5828 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand' 5829 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand' 5830 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand' 5831 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand' 5832 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand' 5833 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand' 5834 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand' 5835 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand' 5836 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand' 5837 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand' 5838 MCK_MVEPairVectorIndex0, // user defined class 'anonymous_4470' 5839 MCK_MVEPairVectorIndex2, // user defined class 'anonymous_4471' 5840 MCK_ComplexRotationEven, // user defined class 'anonymous_4480' 5841 MCK_ComplexRotationOdd, // user defined class 'anonymous_4481' 5842 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_5635' 5843 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_5637' 5844 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_5640' 5845 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_5642' 5846 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_5649' 5847 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_5651' 5848 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_5662' 5849 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_5665' 5850 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_5672' 5851 MCK_ExpandImm0, // user defined class 'anonymous_6197' 5852 MCK_ExpandImm8, // user defined class 'anonymous_6198' 5853 MCK_ExpandImm16, // user defined class 'anonymous_6199' 5854 MCK_ExpandImm24, // user defined class 'anonymous_6200' 5855 MCK_InvertedExpandImm0_16, // user defined class 'anonymous_6201' 5856 MCK_InvertedExpandImm8_16, // user defined class 'anonymous_6202' 5857 MCK_InvertedExpandImm0_32, // user defined class 'anonymous_6203' 5858 MCK_InvertedExpandImm8_32, // user defined class 'anonymous_6204' 5859 MCK_InvertedExpandImm16_32, // user defined class 'anonymous_6205' 5860 MCK_InvertedExpandImm24_32, // user defined class 'anonymous_6206' 5861 MCK_MVEVectorIndex4, // user defined class 'anonymous_6484' 5862 MCK_MVEVectorIndex8, // user defined class 'anonymous_6486' 5863 MCK_MVEVectorIndex16, // user defined class 'anonymous_6488' 5864 MCK_MVEVcvtImm32, // user defined class 'anonymous_6982' 5865 MCK_MVEVcvtImm16, // user defined class 'anonymous_6984' 5866 MCK_TMemImm7Shift0Offset, // user defined class 'anonymous_7320' 5867 MCK_TMemImm7Shift1Offset, // user defined class 'anonymous_7323' 5868 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand' 5869 MCK_FBits16, // user defined class 'fbits16_asm_operand' 5870 MCK_FBits32, // user defined class 'fbits32_asm_operand' 5871 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand' 5872 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand' 5873 MCK_ITMask, // user defined class 'it_mask_asmoperand' 5874 MCK_ITCondCode, // user defined class 'it_pred_asmoperand' 5875 MCK_LELabel, // user defined class 'lelabel_u11_asmoperand' 5876 MCK_MVELongShift, // user defined class 'mve_shift_imm' 5877 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand' 5878 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand' 5879 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand' 5880 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand' 5881 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand' 5882 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand' 5883 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand' 5884 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand' 5885 MCK_CondCodeNoAL, // user defined class 'pred_noal_asmoperand' 5886 MCK_CondCodeNoALInv, // user defined class 'pred_noal_inv_asmoperand' 5887 MCK_CondCodeRestrictedFP, // user defined class 'pred_restricted_fp_asmoperand' 5888 MCK_CondCodeRestrictedI, // user defined class 'pred_restricted_i_asmoperand' 5889 MCK_CondCodeRestrictedS, // user defined class 'pred_restricted_s_asmoperand' 5890 MCK_CondCodeRestrictedU, // user defined class 'pred_restricted_u_asmoperand' 5891 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand' 5892 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand' 5893 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand' 5894 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand' 5895 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand' 5896 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand' 5897 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand' 5898 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand' 5899 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand' 5900 MCK_Imm7s4, // user defined class 't2am_imm7s4_offset_asmoperand' 5901 MCK_Imm7Shift0, // user defined class 't2am_imm7shift0OffsetAsmOperand' 5902 MCK_Imm7Shift1, // user defined class 't2am_imm7shift1OffsetAsmOperand' 5903 MCK_Imm7Shift2, // user defined class 't2am_imm7shift2OffsetAsmOperand' 5904 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand' 5905 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand' 5906 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand' 5907 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand' 5908 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand' 5909 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand' 5910 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand' 5911 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand' 5912 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand' 5913 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand' 5914 MCK_WLSLabel, // user defined class 'wlslabel_u11_asmoperand' 5915 NumMatchClassKinds 5916}; 5917 5918} // end anonymous namespace 5919 5920static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) { 5921 switch (MatchResult) { 5922 case ARMAsmParser::Match_GPRsp: 5923 return "operand must be a register sp"; 5924 case ARMAsmParser::Match_QPR_8: 5925 return "operand must be a register in range [q0, q3]"; 5926 case ARMAsmParser::Match_tGPROdd: 5927 return "operand must be an odd-numbered register in range [r1,r11]"; 5928 case ARMAsmParser::Match_DPR_8: 5929 return "operand must be a register in range [d0, d7]"; 5930 case ARMAsmParser::Match_QPR_VFP2: 5931 return "operand must be a register in range [q0, q7]"; 5932 case ARMAsmParser::Match_hGPR: 5933 return "operand must be a register in range [r8, r15]"; 5934 case ARMAsmParser::Match_tGPR: 5935 return "operand must be a register in range [r0, r7]"; 5936 case ARMAsmParser::Match_tGPREven: 5937 return "operand must be an even-numbered register"; 5938 case ARMAsmParser::Match_GPRnopc: 5939 return "operand must be a register in range [r0, r14]"; 5940 case ARMAsmParser::Match_GPRwithZRnosp: 5941 return "operand must be a register in range [r0, r12] or r14 or zr"; 5942 case ARMAsmParser::Match_DPR_VFP2: 5943 return "operand must be a register in range [d0, d15]"; 5944 case ARMAsmParser::Match_GPR: 5945 return "operand must be a register in range [r0, r15]"; 5946 case ARMAsmParser::Match_GPRwithAPSR: 5947 return "operand must be a register in range [r0, r14] or apsr_nzcv"; 5948 case ARMAsmParser::Match_GPRwithZR: 5949 return "operand must be a register in range [r0, r14] or zr"; 5950 case ARMAsmParser::Match_QPR: 5951 return "operand must be a register in range [q0, q15]"; 5952 case ARMAsmParser::Match_SPR_8: 5953 return "operand must be a register in range [s0, s15]"; 5954 case ARMAsmParser::Match_SPR: 5955 return "operand must be a register in range [s0, s31]"; 5956 case ARMAsmParser::Match_AlignedMemory16: 5957 return "alignment must be 16 or omitted"; 5958 case ARMAsmParser::Match_AlignedMemory32: 5959 return "alignment must be 32 or omitted"; 5960 case ARMAsmParser::Match_AlignedMemory64: 5961 return "alignment must be 64 or omitted"; 5962 case ARMAsmParser::Match_AlignedMemory64or128: 5963 return "alignment must be 64, 128 or omitted"; 5964 case ARMAsmParser::Match_AlignedMemory64or128or256: 5965 return "alignment must be 64, 128, 256 or omitted"; 5966 case ARMAsmParser::Match_AlignedMemoryNone: 5967 return "alignment must be omitted"; 5968 case ARMAsmParser::Match_DupAlignedMemory16: 5969 return "alignment must be 16 or omitted"; 5970 case ARMAsmParser::Match_DupAlignedMemory32: 5971 return "alignment must be 32 or omitted"; 5972 case ARMAsmParser::Match_DupAlignedMemory64: 5973 return "alignment must be 64 or omitted"; 5974 case ARMAsmParser::Match_DupAlignedMemory64or128: 5975 return "alignment must be 64, 128 or omitted"; 5976 case ARMAsmParser::Match_DupAlignedMemoryNone: 5977 return "alignment must be omitted"; 5978 case ARMAsmParser::Match_Imm0_15: 5979 return "operand must be an immediate in the range [0,15]"; 5980 case ARMAsmParser::Match_Imm0_1: 5981 return "operand must be an immediate in the range [0,1]"; 5982 case ARMAsmParser::Match_Imm0_239: 5983 return "operand must be an immediate in the range [0,239]"; 5984 case ARMAsmParser::Match_Imm0_255: 5985 return "operand must be an immediate in the range [0,255]"; 5986 case ARMAsmParser::Match_Imm0_31: 5987 return "operand must be an immediate in the range [0,31]"; 5988 case ARMAsmParser::Match_Imm0_32: 5989 return "operand must be an immediate in the range [0,32]"; 5990 case ARMAsmParser::Match_Imm0_3: 5991 return "operand must be an immediate in the range [0,3]"; 5992 case ARMAsmParser::Match_Imm0_63: 5993 return "operand must be an immediate in the range [0,63]"; 5994 case ARMAsmParser::Match_Imm0_65535: 5995 return "operand must be an immediate in the range [0,65535]"; 5996 case ARMAsmParser::Match_Imm0_65535Expr: 5997 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 5998 case ARMAsmParser::Match_Imm0_7: 5999 return "operand must be an immediate in the range [0,7]"; 6000 case ARMAsmParser::Match_Imm16: 6001 return "operand must be an immediate in the range [16,16]"; 6002 case ARMAsmParser::Match_Imm1_15: 6003 return "operand must be an immediate in the range [1,15]"; 6004 case ARMAsmParser::Match_ImmRange1_16: 6005 return "operand must be an immediate in the range [1,16]"; 6006 case ARMAsmParser::Match_Imm1_31: 6007 return "operand must be an immediate in the range [1,31]"; 6008 case ARMAsmParser::Match_ImmRange1_32: 6009 return "operand must be an immediate in the range [1,32]"; 6010 case ARMAsmParser::Match_Imm1_7: 6011 return "operand must be an immediate in the range [1,7]"; 6012 case ARMAsmParser::Match_Imm24bit: 6013 return "operand must be an immediate in the range [0,0xffffff]"; 6014 case ARMAsmParser::Match_Imm256_65535Expr: 6015 return "operand must be an immediate in the range [256,65535]"; 6016 case ARMAsmParser::Match_Imm32: 6017 return "operand must be an immediate in the range [32,32]"; 6018 case ARMAsmParser::Match_Imm8: 6019 return "operand must be an immediate in the range [8,8]"; 6020 case ARMAsmParser::Match_Imm8_255: 6021 return "operand must be an immediate in the range [8,255]"; 6022 case ARMAsmParser::Match_MVEShiftImm1_15: 6023 return "operand must be an immediate in the range [1,16]"; 6024 case ARMAsmParser::Match_MVEShiftImm1_7: 6025 return "operand must be an immediate in the range [1,8]"; 6026 case ARMAsmParser::Match_VIDUP_imm: 6027 return "vector increment immediate must be 1, 2, 4 or 8"; 6028 case ARMAsmParser::Match_MveSaturate: 6029 return "saturate operand must be 48 or 64"; 6030 case ARMAsmParser::Match_PKHLSLImm: 6031 return "operand must be an immediate in the range [0,31]"; 6032 case ARMAsmParser::Match_SPRRegList: 6033 return "operand must be a list of registers in range [s0, s31]"; 6034 case ARMAsmParser::Match_SetEndImm: 6035 return "operand must be an immediate in the range [0,1]"; 6036 case ARMAsmParser::Match_ImmThumbSR: 6037 return "operand must be an immediate in the range [1,32]"; 6038 case ARMAsmParser::Match_VecListTwoMQ: 6039 return "operand must be a list of two consecutive q-registers in range [q0,q7]"; 6040 case ARMAsmParser::Match_VecListFourMQ: 6041 return "operand must be a list of four consecutive q-registers in range [q0,q7]"; 6042 case ARMAsmParser::Match_ComplexRotationEven: 6043 return "complex rotation must be 0, 90, 180 or 270"; 6044 case ARMAsmParser::Match_ComplexRotationOdd: 6045 return "complex rotation must be 90 or 270"; 6046 case ARMAsmParser::Match_MVEVcvtImm32: 6047 return "MVE fixed-point immediate operand must be between 1 and 32"; 6048 case ARMAsmParser::Match_MVEVcvtImm16: 6049 return "MVE fixed-point immediate operand must be between 1 and 16"; 6050 case ARMAsmParser::Match_Imm0_4095: 6051 return "operand must be an immediate in the range [0,4095]"; 6052 case ARMAsmParser::Match_LELabel: 6053 return "loop start is out of range or not a negative multiple of 2"; 6054 case ARMAsmParser::Match_MVELongShift: 6055 return "operand must be an immediate in the range [1,32]"; 6056 case ARMAsmParser::Match_CondCodeRestrictedFP: 6057 return "condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE"; 6058 case ARMAsmParser::Match_CondCodeRestrictedI: 6059 return "condition code for sign-independent integer comparison must be EQ or NE"; 6060 case ARMAsmParser::Match_CondCodeRestrictedS: 6061 return "condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE"; 6062 case ARMAsmParser::Match_CondCodeRestrictedU: 6063 return "condition code for unsigned integer comparison must be EQ, NE, HS or HI"; 6064 case ARMAsmParser::Match_ShrImm16: 6065 return "operand must be an immediate in the range [1,16]"; 6066 case ARMAsmParser::Match_ShrImm32: 6067 return "operand must be an immediate in the range [1,32]"; 6068 case ARMAsmParser::Match_ShrImm64: 6069 return "operand must be an immediate in the range [1,64]"; 6070 case ARMAsmParser::Match_ShrImm8: 6071 return "operand must be an immediate in the range [1,8]"; 6072 case ARMAsmParser::Match_WLSLabel: 6073 return "loop end is out of range or not a positive multiple of 2"; 6074 default: 6075 return nullptr; 6076 } 6077} 6078 6079static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 6080 switch (RegisterClass) { 6081 case MCK_GPRsp: 6082 return ARMAsmParser::Match_GPRsp; 6083 case MCK_QPR_8: 6084 return ARMAsmParser::Match_QPR_8; 6085 case MCK_tGPROdd: 6086 return ARMAsmParser::Match_tGPROdd; 6087 case MCK_DPR_8: 6088 return ARMAsmParser::Match_DPR_8; 6089 case MCK_MQPR: 6090 return ARMAsmParser::Match_QPR_VFP2; 6091 case MCK_hGPR: 6092 return ARMAsmParser::Match_hGPR; 6093 case MCK_tGPR: 6094 return ARMAsmParser::Match_tGPR; 6095 case MCK_tGPREven: 6096 return ARMAsmParser::Match_tGPREven; 6097 case MCK_rGPR: 6098 return ARMAsmParser::Match_rGPR; 6099 case MCK_GPRnopc: 6100 return ARMAsmParser::Match_GPRnopc; 6101 case MCK_GPRwithZRnosp: 6102 return ARMAsmParser::Match_GPRwithZRnosp; 6103 case MCK_DPR_VFP2: 6104 return ARMAsmParser::Match_DPR_VFP2; 6105 case MCK_GPR: 6106 return ARMAsmParser::Match_GPR; 6107 case MCK_GPRwithAPSR: 6108 return ARMAsmParser::Match_GPRwithAPSR; 6109 case MCK_GPRwithZR: 6110 return ARMAsmParser::Match_GPRwithZR; 6111 case MCK_QPR: 6112 return ARMAsmParser::Match_QPR; 6113 case MCK_SPR_8: 6114 return ARMAsmParser::Match_SPR_8; 6115 case MCK_DPR: 6116 return ARMAsmParser::Match_DPR; 6117 case MCK_HPR: 6118 return ARMAsmParser::Match_SPR; 6119 default: 6120 return MCTargetAsmParser::Match_InvalidOperand; 6121 } 6122} 6123 6124static MatchClassKind matchTokenString(StringRef Name) { 6125 switch (Name.size()) { 6126 default: break; 6127 case 1: // 6 strings to match. 6128 switch (Name[0]) { 6129 default: break; 6130 case '!': // 1 string to match. 6131 return MCK__EXCLAIM_; // "!" 6132 case '[': // 1 string to match. 6133 return MCK__91_; // "[" 6134 case ']': // 1 string to match. 6135 return MCK__93_; // "]" 6136 case '^': // 1 string to match. 6137 return MCK__94_; // "^" 6138 case '{': // 1 string to match. 6139 return MCK__123_; // "{" 6140 case '}': // 1 string to match. 6141 return MCK__125_; // "}" 6142 } 6143 break; 6144 case 2: // 6 strings to match. 6145 switch (Name[0]) { 6146 default: break; 6147 case '#': // 2 strings to match. 6148 switch (Name[1]) { 6149 default: break; 6150 case '0': // 1 string to match. 6151 return MCK__HASH_0; // "#0" 6152 case '8': // 1 string to match. 6153 return MCK__HASH_8; // "#8" 6154 } 6155 break; 6156 case '.': // 4 strings to match. 6157 switch (Name[1]) { 6158 default: break; 6159 case '8': // 1 string to match. 6160 return MCK__DOT_8; // ".8" 6161 case 'd': // 1 string to match. 6162 return MCK__DOT_d; // ".d" 6163 case 'f': // 1 string to match. 6164 return MCK__DOT_f; // ".f" 6165 case 'w': // 1 string to match. 6166 return MCK__DOT_w; // ".w" 6167 } 6168 break; 6169 } 6170 break; 6171 case 3: // 8 strings to match. 6172 switch (Name[0]) { 6173 default: break; 6174 case '#': // 1 string to match. 6175 if (memcmp(Name.data()+1, "16", 2) != 0) 6176 break; 6177 return MCK__HASH_16; // "#16" 6178 case '.': // 7 strings to match. 6179 switch (Name[1]) { 6180 default: break; 6181 case '1': // 1 string to match. 6182 if (Name[2] != '6') 6183 break; 6184 return MCK__DOT_16; // ".16" 6185 case '3': // 1 string to match. 6186 if (Name[2] != '2') 6187 break; 6188 return MCK__DOT_32; // ".32" 6189 case '6': // 1 string to match. 6190 if (Name[2] != '4') 6191 break; 6192 return MCK__DOT_64; // ".64" 6193 case 'i': // 1 string to match. 6194 if (Name[2] != '8') 6195 break; 6196 return MCK__DOT_i8; // ".i8" 6197 case 'p': // 1 string to match. 6198 if (Name[2] != '8') 6199 break; 6200 return MCK__DOT_p8; // ".p8" 6201 case 's': // 1 string to match. 6202 if (Name[2] != '8') 6203 break; 6204 return MCK__DOT_s8; // ".s8" 6205 case 'u': // 1 string to match. 6206 if (Name[2] != '8') 6207 break; 6208 return MCK__DOT_u8; // ".u8" 6209 } 6210 break; 6211 } 6212 break; 6213 case 4: // 14 strings to match. 6214 if (Name[0] != '.') 6215 break; 6216 switch (Name[1]) { 6217 default: break; 6218 case 'f': // 3 strings to match. 6219 switch (Name[2]) { 6220 default: break; 6221 case '1': // 1 string to match. 6222 if (Name[3] != '6') 6223 break; 6224 return MCK__DOT_f16; // ".f16" 6225 case '3': // 1 string to match. 6226 if (Name[3] != '2') 6227 break; 6228 return MCK__DOT_f32; // ".f32" 6229 case '6': // 1 string to match. 6230 if (Name[3] != '4') 6231 break; 6232 return MCK__DOT_f64; // ".f64" 6233 } 6234 break; 6235 case 'i': // 3 strings to match. 6236 switch (Name[2]) { 6237 default: break; 6238 case '1': // 1 string to match. 6239 if (Name[3] != '6') 6240 break; 6241 return MCK__DOT_i16; // ".i16" 6242 case '3': // 1 string to match. 6243 if (Name[3] != '2') 6244 break; 6245 return MCK__DOT_i32; // ".i32" 6246 case '6': // 1 string to match. 6247 if (Name[3] != '4') 6248 break; 6249 return MCK__DOT_i64; // ".i64" 6250 } 6251 break; 6252 case 'p': // 2 strings to match. 6253 switch (Name[2]) { 6254 default: break; 6255 case '1': // 1 string to match. 6256 if (Name[3] != '6') 6257 break; 6258 return MCK__DOT_p16; // ".p16" 6259 case '6': // 1 string to match. 6260 if (Name[3] != '4') 6261 break; 6262 return MCK__DOT_p64; // ".p64" 6263 } 6264 break; 6265 case 's': // 3 strings to match. 6266 switch (Name[2]) { 6267 default: break; 6268 case '1': // 1 string to match. 6269 if (Name[3] != '6') 6270 break; 6271 return MCK__DOT_s16; // ".s16" 6272 case '3': // 1 string to match. 6273 if (Name[3] != '2') 6274 break; 6275 return MCK__DOT_s32; // ".s32" 6276 case '6': // 1 string to match. 6277 if (Name[3] != '4') 6278 break; 6279 return MCK__DOT_s64; // ".s64" 6280 } 6281 break; 6282 case 'u': // 3 strings to match. 6283 switch (Name[2]) { 6284 default: break; 6285 case '1': // 1 string to match. 6286 if (Name[3] != '6') 6287 break; 6288 return MCK__DOT_u16; // ".u16" 6289 case '3': // 1 string to match. 6290 if (Name[3] != '2') 6291 break; 6292 return MCK__DOT_u32; // ".u32" 6293 case '6': // 1 string to match. 6294 if (Name[3] != '4') 6295 break; 6296 return MCK__DOT_u64; // ".u64" 6297 } 6298 break; 6299 } 6300 break; 6301 } 6302 return InvalidMatchClass; 6303} 6304 6305/// isSubclass - Compute whether \p A is a subclass of \p B. 6306static bool isSubclass(MatchClassKind A, MatchClassKind B) { 6307 if (A == B) 6308 return true; 6309 6310 switch (A) { 6311 default: 6312 return false; 6313 6314 case MCK__DOT_d: 6315 switch (B) { 6316 default: return false; 6317 case MCK__DOT_f64: return true; 6318 case MCK__DOT_64: return true; 6319 } 6320 6321 case MCK__DOT_f: 6322 switch (B) { 6323 default: return false; 6324 case MCK__DOT_f32: return true; 6325 case MCK__DOT_32: return true; 6326 } 6327 6328 case MCK__DOT_s16: 6329 switch (B) { 6330 default: return false; 6331 case MCK__DOT_i16: return true; 6332 case MCK__DOT_16: return true; 6333 } 6334 6335 case MCK__DOT_s32: 6336 switch (B) { 6337 default: return false; 6338 case MCK__DOT_i32: return true; 6339 case MCK__DOT_32: return true; 6340 } 6341 6342 case MCK__DOT_s64: 6343 switch (B) { 6344 default: return false; 6345 case MCK__DOT_i64: return true; 6346 case MCK__DOT_64: return true; 6347 } 6348 6349 case MCK__DOT_s8: 6350 switch (B) { 6351 default: return false; 6352 case MCK__DOT_i8: return true; 6353 case MCK__DOT_8: return true; 6354 } 6355 6356 case MCK__DOT_u16: 6357 switch (B) { 6358 default: return false; 6359 case MCK__DOT_i16: return true; 6360 case MCK__DOT_16: return true; 6361 } 6362 6363 case MCK__DOT_u32: 6364 switch (B) { 6365 default: return false; 6366 case MCK__DOT_i32: return true; 6367 case MCK__DOT_32: return true; 6368 } 6369 6370 case MCK__DOT_u64: 6371 switch (B) { 6372 default: return false; 6373 case MCK__DOT_i64: return true; 6374 case MCK__DOT_64: return true; 6375 } 6376 6377 case MCK__DOT_u8: 6378 switch (B) { 6379 default: return false; 6380 case MCK__DOT_i8: return true; 6381 case MCK__DOT_8: return true; 6382 } 6383 6384 case MCK__DOT_f32: 6385 return B == MCK__DOT_32; 6386 6387 case MCK__DOT_f64: 6388 return B == MCK__DOT_64; 6389 6390 case MCK__DOT_i16: 6391 return B == MCK__DOT_16; 6392 6393 case MCK__DOT_i32: 6394 return B == MCK__DOT_32; 6395 6396 case MCK__DOT_i64: 6397 return B == MCK__DOT_64; 6398 6399 case MCK__DOT_i8: 6400 return B == MCK__DOT_8; 6401 6402 case MCK__DOT_p16: 6403 return B == MCK__DOT_16; 6404 6405 case MCK__DOT_p8: 6406 return B == MCK__DOT_8; 6407 6408 case MCK_Reg94: 6409 switch (B) { 6410 default: return false; 6411 case MCK_Reg93: return true; 6412 case MCK_Reg91: return true; 6413 case MCK_GPRPair: return true; 6414 } 6415 6416 case MCK_Reg78: 6417 switch (B) { 6418 default: return false; 6419 case MCK_Reg79: return true; 6420 case MCK_Reg80: return true; 6421 case MCK_Reg81: return true; 6422 case MCK_Reg82: return true; 6423 case MCK_Reg83: return true; 6424 case MCK_Reg84: return true; 6425 case MCK_Reg85: return true; 6426 case MCK_QQQQPR: return true; 6427 } 6428 6429 case MCK_Reg23: 6430 switch (B) { 6431 default: return false; 6432 case MCK_Reg14: return true; 6433 case MCK_Reg21: return true; 6434 case MCK_tcGPR: return true; 6435 case MCK_Reg20: return true; 6436 case MCK_Reg18: return true; 6437 case MCK_hGPR: return true; 6438 case MCK_tGPREven: return true; 6439 case MCK_rGPR: return true; 6440 case MCK_GPRnopc: return true; 6441 case MCK_GPRwithAPSRnosp: return true; 6442 case MCK_GPRwithZRnosp: return true; 6443 case MCK_GPR: return true; 6444 case MCK_GPRwithAPSR: return true; 6445 case MCK_GPRwithZR: return true; 6446 } 6447 6448 case MCK_APSR: 6449 return B == MCK_GPRwithAPSRnosp; 6450 6451 case MCK_APSR_NZCV: 6452 return B == MCK_GPRwithAPSR; 6453 6454 case MCK_GPRlr: 6455 switch (B) { 6456 default: return false; 6457 case MCK_Reg21: return true; 6458 case MCK_Reg20: return true; 6459 case MCK_Reg18: return true; 6460 case MCK_hGPR: return true; 6461 case MCK_tGPREven: return true; 6462 case MCK_rGPR: return true; 6463 case MCK_GPRnopc: return true; 6464 case MCK_GPRwithAPSRnosp: return true; 6465 case MCK_GPRwithZRnosp: return true; 6466 case MCK_GPR: return true; 6467 case MCK_GPRwithAPSR: return true; 6468 case MCK_GPRwithZR: return true; 6469 } 6470 6471 case MCK_GPRsp: 6472 switch (B) { 6473 default: return false; 6474 case MCK_Reg18: return true; 6475 case MCK_hGPR: return true; 6476 case MCK_GPRnopc: return true; 6477 case MCK_GPR: return true; 6478 case MCK_GPRwithAPSR: return true; 6479 case MCK_GPRwithZR: return true; 6480 } 6481 6482 case MCK_PC: 6483 switch (B) { 6484 default: return false; 6485 case MCK_hGPR: return true; 6486 case MCK_tGPRwithpc: return true; 6487 case MCK_GPR: return true; 6488 } 6489 6490 case MCK_VCCR: 6491 return B == MCK_FPWithVPR; 6492 6493 case MCK_Reg119: 6494 switch (B) { 6495 default: return false; 6496 case MCK_Reg120: return true; 6497 case MCK_Reg121: return true; 6498 case MCK_Reg76: return true; 6499 case MCK_Reg122: return true; 6500 case MCK_Reg77: return true; 6501 case MCK_Reg123: return true; 6502 case MCK_Reg74: return true; 6503 case MCK_Reg124: return true; 6504 case MCK_Reg75: return true; 6505 case MCK_Reg72: return true; 6506 case MCK_Reg125: return true; 6507 case MCK_Reg73: return true; 6508 case MCK_Reg70: return true; 6509 case MCK_Reg71: return true; 6510 case MCK_DQuad: return true; 6511 } 6512 6513 case MCK_Reg92: 6514 switch (B) { 6515 default: return false; 6516 case MCK_Reg93: return true; 6517 case MCK_GPRPairnosp: return true; 6518 case MCK_GPRPair: return true; 6519 } 6520 6521 case MCK_Reg87: 6522 switch (B) { 6523 default: return false; 6524 case MCK_Reg91: return true; 6525 case MCK_Reg88: return true; 6526 case MCK_GPRPairnosp: return true; 6527 case MCK_GPRPair: return true; 6528 } 6529 6530 case MCK_Reg79: 6531 switch (B) { 6532 default: return false; 6533 case MCK_Reg80: return true; 6534 case MCK_Reg81: return true; 6535 case MCK_Reg82: return true; 6536 case MCK_Reg83: return true; 6537 case MCK_Reg84: return true; 6538 case MCK_Reg85: return true; 6539 case MCK_QQQQPR: return true; 6540 } 6541 6542 case MCK_Reg22: 6543 switch (B) { 6544 default: return false; 6545 case MCK_Reg20: return true; 6546 case MCK_tGPROdd: return true; 6547 case MCK_Reg18: return true; 6548 case MCK_hGPR: return true; 6549 case MCK_rGPR: return true; 6550 case MCK_GPRnopc: return true; 6551 case MCK_GPRwithAPSRnosp: return true; 6552 case MCK_GPRwithZRnosp: return true; 6553 case MCK_GPR: return true; 6554 case MCK_GPRwithAPSR: return true; 6555 case MCK_GPRwithZR: return true; 6556 } 6557 6558 case MCK_Reg15: 6559 switch (B) { 6560 default: return false; 6561 case MCK_Reg16: return true; 6562 case MCK_Reg0: return true; 6563 case MCK_tcGPR: return true; 6564 case MCK_tGPROdd: return true; 6565 case MCK_tGPR: return true; 6566 case MCK_tGPRwithpc: return true; 6567 case MCK_rGPR: return true; 6568 case MCK_GPRnopc: return true; 6569 case MCK_GPRwithAPSRnosp: return true; 6570 case MCK_GPRwithZRnosp: return true; 6571 case MCK_GPR: return true; 6572 case MCK_GPRwithAPSR: return true; 6573 case MCK_GPRwithZR: return true; 6574 } 6575 6576 case MCK_Reg11: 6577 switch (B) { 6578 default: return false; 6579 case MCK_Reg14: return true; 6580 case MCK_Reg12: return true; 6581 case MCK_Reg0: return true; 6582 case MCK_tcGPR: return true; 6583 case MCK_tGPR: return true; 6584 case MCK_tGPREven: return true; 6585 case MCK_tGPRwithpc: return true; 6586 case MCK_rGPR: return true; 6587 case MCK_GPRnopc: return true; 6588 case MCK_GPRwithAPSRnosp: return true; 6589 case MCK_GPRwithZRnosp: return true; 6590 case MCK_GPR: return true; 6591 case MCK_GPRwithAPSR: return true; 6592 case MCK_GPRwithZR: return true; 6593 } 6594 6595 case MCK_Reg120: 6596 switch (B) { 6597 default: return false; 6598 case MCK_Reg121: return true; 6599 case MCK_Reg122: return true; 6600 case MCK_Reg77: return true; 6601 case MCK_Reg123: return true; 6602 case MCK_Reg74: return true; 6603 case MCK_Reg124: return true; 6604 case MCK_Reg75: return true; 6605 case MCK_Reg72: return true; 6606 case MCK_Reg125: return true; 6607 case MCK_Reg73: return true; 6608 case MCK_Reg70: return true; 6609 case MCK_Reg71: return true; 6610 case MCK_DQuad: return true; 6611 } 6612 6613 case MCK_Reg107: 6614 switch (B) { 6615 default: return false; 6616 case MCK_Reg108: return true; 6617 case MCK_Reg95: return true; 6618 case MCK_Reg109: return true; 6619 case MCK_Reg96: return true; 6620 case MCK_Reg110: return true; 6621 case MCK_Reg97: return true; 6622 case MCK_Reg98: return true; 6623 case MCK_Reg111: return true; 6624 case MCK_Reg99: return true; 6625 case MCK_Reg100: return true; 6626 case MCK_DTriple: return true; 6627 } 6628 6629 case MCK_Reg102: 6630 switch (B) { 6631 default: return false; 6632 case MCK_Reg103: return true; 6633 case MCK_Reg95: return true; 6634 case MCK_Reg104: return true; 6635 case MCK_Reg96: return true; 6636 case MCK_Reg105: return true; 6637 case MCK_Reg97: return true; 6638 case MCK_Reg98: return true; 6639 case MCK_Reg106: return true; 6640 case MCK_Reg99: return true; 6641 case MCK_Reg100: return true; 6642 case MCK_DTriple: return true; 6643 } 6644 6645 case MCK_Reg93: 6646 return B == MCK_GPRPair; 6647 6648 case MCK_Reg91: 6649 return B == MCK_GPRPair; 6650 6651 case MCK_Reg80: 6652 switch (B) { 6653 default: return false; 6654 case MCK_Reg81: return true; 6655 case MCK_Reg82: return true; 6656 case MCK_Reg83: return true; 6657 case MCK_Reg84: return true; 6658 case MCK_Reg85: return true; 6659 case MCK_QQQQPR: return true; 6660 } 6661 6662 case MCK_Reg64: 6663 switch (B) { 6664 default: return false; 6665 case MCK_Reg65: return true; 6666 case MCK_Reg76: return true; 6667 case MCK_Reg77: return true; 6668 case MCK_Reg74: return true; 6669 case MCK_Reg66: return true; 6670 case MCK_Reg75: return true; 6671 case MCK_Reg67: return true; 6672 case MCK_Reg72: return true; 6673 case MCK_Reg73: return true; 6674 case MCK_Reg70: return true; 6675 case MCK_QQPR: return true; 6676 case MCK_Reg71: return true; 6677 case MCK_DQuad: return true; 6678 } 6679 6680 case MCK_Reg14: 6681 switch (B) { 6682 default: return false; 6683 case MCK_tcGPR: return true; 6684 case MCK_tGPREven: return true; 6685 case MCK_rGPR: return true; 6686 case MCK_GPRnopc: return true; 6687 case MCK_GPRwithAPSRnosp: return true; 6688 case MCK_GPRwithZRnosp: return true; 6689 case MCK_GPR: return true; 6690 case MCK_GPRwithAPSR: return true; 6691 case MCK_GPRwithZR: return true; 6692 } 6693 6694 case MCK_Reg121: 6695 switch (B) { 6696 default: return false; 6697 case MCK_Reg122: return true; 6698 case MCK_Reg123: return true; 6699 case MCK_Reg124: return true; 6700 case MCK_Reg75: return true; 6701 case MCK_Reg72: return true; 6702 case MCK_Reg125: return true; 6703 case MCK_Reg73: return true; 6704 case MCK_Reg70: return true; 6705 case MCK_Reg71: return true; 6706 case MCK_DQuad: return true; 6707 } 6708 6709 case MCK_Reg112: 6710 switch (B) { 6711 default: return false; 6712 case MCK_Reg113: return true; 6713 case MCK_Reg114: return true; 6714 case MCK_Reg115: return true; 6715 case MCK_Reg116: return true; 6716 case MCK_Reg117: return true; 6717 case MCK_DTripleSpc: return true; 6718 } 6719 6720 case MCK_Reg108: 6721 switch (B) { 6722 default: return false; 6723 case MCK_Reg109: return true; 6724 case MCK_Reg110: return true; 6725 case MCK_Reg97: return true; 6726 case MCK_Reg98: return true; 6727 case MCK_Reg111: return true; 6728 case MCK_Reg99: return true; 6729 case MCK_Reg100: return true; 6730 case MCK_DTriple: return true; 6731 } 6732 6733 case MCK_Reg103: 6734 switch (B) { 6735 default: return false; 6736 case MCK_Reg104: return true; 6737 case MCK_Reg96: return true; 6738 case MCK_Reg105: return true; 6739 case MCK_Reg97: return true; 6740 case MCK_Reg98: return true; 6741 case MCK_Reg106: return true; 6742 case MCK_Reg99: return true; 6743 case MCK_Reg100: return true; 6744 case MCK_DTriple: return true; 6745 } 6746 6747 case MCK_Reg88: 6748 switch (B) { 6749 default: return false; 6750 case MCK_GPRPairnosp: return true; 6751 case MCK_GPRPair: return true; 6752 } 6753 6754 case MCK_Reg81: 6755 switch (B) { 6756 default: return false; 6757 case MCK_Reg82: return true; 6758 case MCK_Reg83: return true; 6759 case MCK_Reg84: return true; 6760 case MCK_Reg85: return true; 6761 case MCK_QQQQPR: return true; 6762 } 6763 6764 case MCK_Reg65: 6765 switch (B) { 6766 default: return false; 6767 case MCK_Reg74: return true; 6768 case MCK_Reg66: return true; 6769 case MCK_Reg75: return true; 6770 case MCK_Reg67: return true; 6771 case MCK_Reg72: return true; 6772 case MCK_Reg73: return true; 6773 case MCK_Reg70: return true; 6774 case MCK_QQPR: return true; 6775 case MCK_Reg71: return true; 6776 case MCK_DQuad: return true; 6777 } 6778 6779 case MCK_Reg21: 6780 switch (B) { 6781 default: return false; 6782 case MCK_Reg20: return true; 6783 case MCK_Reg18: return true; 6784 case MCK_hGPR: return true; 6785 case MCK_tGPREven: return true; 6786 case MCK_rGPR: return true; 6787 case MCK_GPRnopc: return true; 6788 case MCK_GPRwithAPSRnosp: return true; 6789 case MCK_GPRwithZRnosp: return true; 6790 case MCK_GPR: return true; 6791 case MCK_GPRwithAPSR: return true; 6792 case MCK_GPRwithZR: return true; 6793 } 6794 6795 case MCK_Reg16: 6796 switch (B) { 6797 default: return false; 6798 case MCK_tGPROdd: return true; 6799 case MCK_tGPR: return true; 6800 case MCK_tGPRwithpc: return true; 6801 case MCK_rGPR: return true; 6802 case MCK_GPRnopc: return true; 6803 case MCK_GPRwithAPSRnosp: return true; 6804 case MCK_GPRwithZRnosp: return true; 6805 case MCK_GPR: return true; 6806 case MCK_GPRwithAPSR: return true; 6807 case MCK_GPRwithZR: return true; 6808 } 6809 6810 case MCK_Reg12: 6811 switch (B) { 6812 default: return false; 6813 case MCK_tGPR: return true; 6814 case MCK_tGPREven: return true; 6815 case MCK_tGPRwithpc: return true; 6816 case MCK_rGPR: return true; 6817 case MCK_GPRnopc: return true; 6818 case MCK_GPRwithAPSRnosp: return true; 6819 case MCK_GPRwithZRnosp: return true; 6820 case MCK_GPR: return true; 6821 case MCK_GPRwithAPSR: return true; 6822 case MCK_GPRwithZR: return true; 6823 } 6824 6825 case MCK_Reg0: 6826 switch (B) { 6827 default: return false; 6828 case MCK_tcGPR: return true; 6829 case MCK_tGPR: return true; 6830 case MCK_tGPRwithpc: return true; 6831 case MCK_rGPR: return true; 6832 case MCK_GPRnopc: return true; 6833 case MCK_GPRwithAPSRnosp: return true; 6834 case MCK_GPRwithZRnosp: return true; 6835 case MCK_GPR: return true; 6836 case MCK_GPRwithAPSR: return true; 6837 case MCK_GPRwithZR: return true; 6838 } 6839 6840 case MCK_QPR_8: 6841 switch (B) { 6842 default: return false; 6843 case MCK_Reg39: return true; 6844 case MCK_Reg40: return true; 6845 case MCK_MQPR: return true; 6846 case MCK_Reg37: return true; 6847 case MCK_Reg38: return true; 6848 case MCK_QPR: return true; 6849 case MCK_DPair: return true; 6850 } 6851 6852 case MCK_Reg82: 6853 switch (B) { 6854 default: return false; 6855 case MCK_Reg83: return true; 6856 case MCK_Reg84: return true; 6857 case MCK_Reg85: return true; 6858 case MCK_QQQQPR: return true; 6859 } 6860 6861 case MCK_Reg76: 6862 switch (B) { 6863 default: return false; 6864 case MCK_Reg77: return true; 6865 case MCK_Reg74: return true; 6866 case MCK_Reg75: return true; 6867 case MCK_Reg72: return true; 6868 case MCK_Reg73: return true; 6869 case MCK_Reg70: return true; 6870 case MCK_Reg71: return true; 6871 case MCK_DQuad: return true; 6872 } 6873 6874 case MCK_tcGPR: 6875 switch (B) { 6876 default: return false; 6877 case MCK_rGPR: return true; 6878 case MCK_GPRnopc: return true; 6879 case MCK_GPRwithAPSRnosp: return true; 6880 case MCK_GPRwithZRnosp: return true; 6881 case MCK_GPR: return true; 6882 case MCK_GPRwithAPSR: return true; 6883 case MCK_GPRwithZR: return true; 6884 } 6885 6886 case MCK_Reg122: 6887 switch (B) { 6888 default: return false; 6889 case MCK_Reg123: return true; 6890 case MCK_Reg124: return true; 6891 case MCK_Reg72: return true; 6892 case MCK_Reg125: return true; 6893 case MCK_Reg73: return true; 6894 case MCK_Reg70: return true; 6895 case MCK_Reg71: return true; 6896 case MCK_DQuad: return true; 6897 } 6898 6899 case MCK_Reg113: 6900 switch (B) { 6901 default: return false; 6902 case MCK_Reg114: return true; 6903 case MCK_Reg115: return true; 6904 case MCK_Reg116: return true; 6905 case MCK_Reg117: return true; 6906 case MCK_DTripleSpc: return true; 6907 } 6908 6909 case MCK_Reg95: 6910 switch (B) { 6911 default: return false; 6912 case MCK_Reg96: return true; 6913 case MCK_Reg97: return true; 6914 case MCK_Reg98: return true; 6915 case MCK_Reg99: return true; 6916 case MCK_Reg100: return true; 6917 case MCK_DTriple: return true; 6918 } 6919 6920 case MCK_Reg83: 6921 switch (B) { 6922 default: return false; 6923 case MCK_Reg84: return true; 6924 case MCK_Reg85: return true; 6925 case MCK_QQQQPR: return true; 6926 } 6927 6928 case MCK_Reg77: 6929 switch (B) { 6930 default: return false; 6931 case MCK_Reg74: return true; 6932 case MCK_Reg75: return true; 6933 case MCK_Reg72: return true; 6934 case MCK_Reg73: return true; 6935 case MCK_Reg70: return true; 6936 case MCK_Reg71: return true; 6937 case MCK_DQuad: return true; 6938 } 6939 6940 case MCK_Reg59: 6941 switch (B) { 6942 default: return false; 6943 case MCK_Reg60: return true; 6944 case MCK_Reg61: return true; 6945 case MCK_Reg62: return true; 6946 case MCK_DPairSpc: return true; 6947 } 6948 6949 case MCK_Reg20: 6950 switch (B) { 6951 default: return false; 6952 case MCK_Reg18: return true; 6953 case MCK_hGPR: return true; 6954 case MCK_rGPR: return true; 6955 case MCK_GPRnopc: return true; 6956 case MCK_GPRwithAPSRnosp: return true; 6957 case MCK_GPRwithZRnosp: return true; 6958 case MCK_GPR: return true; 6959 case MCK_GPRwithAPSR: return true; 6960 case MCK_GPRwithZR: return true; 6961 } 6962 6963 case MCK_GPRPairnosp: 6964 return B == MCK_GPRPair; 6965 6966 case MCK_tGPROdd: 6967 switch (B) { 6968 default: return false; 6969 case MCK_rGPR: return true; 6970 case MCK_GPRnopc: return true; 6971 case MCK_GPRwithAPSRnosp: return true; 6972 case MCK_GPRwithZRnosp: return true; 6973 case MCK_GPR: return true; 6974 case MCK_GPRwithAPSR: return true; 6975 case MCK_GPRwithZR: return true; 6976 } 6977 6978 case MCK_Reg123: 6979 switch (B) { 6980 default: return false; 6981 case MCK_Reg124: return true; 6982 case MCK_Reg125: return true; 6983 case MCK_Reg73: return true; 6984 case MCK_Reg70: return true; 6985 case MCK_Reg71: return true; 6986 case MCK_DQuad: return true; 6987 } 6988 6989 case MCK_Reg109: 6990 switch (B) { 6991 default: return false; 6992 case MCK_Reg110: return true; 6993 case MCK_Reg98: return true; 6994 case MCK_Reg111: return true; 6995 case MCK_Reg99: return true; 6996 case MCK_Reg100: return true; 6997 case MCK_DTriple: return true; 6998 } 6999 7000 case MCK_Reg104: 7001 switch (B) { 7002 default: return false; 7003 case MCK_Reg105: return true; 7004 case MCK_Reg98: return true; 7005 case MCK_Reg106: return true; 7006 case MCK_Reg99: return true; 7007 case MCK_Reg100: return true; 7008 case MCK_DTriple: return true; 7009 } 7010 7011 case MCK_Reg96: 7012 switch (B) { 7013 default: return false; 7014 case MCK_Reg97: return true; 7015 case MCK_Reg98: return true; 7016 case MCK_Reg99: return true; 7017 case MCK_Reg100: return true; 7018 case MCK_DTriple: return true; 7019 } 7020 7021 case MCK_Reg84: 7022 switch (B) { 7023 default: return false; 7024 case MCK_Reg85: return true; 7025 case MCK_QQQQPR: return true; 7026 } 7027 7028 case MCK_Reg74: 7029 switch (B) { 7030 default: return false; 7031 case MCK_Reg75: return true; 7032 case MCK_Reg72: return true; 7033 case MCK_Reg73: return true; 7034 case MCK_Reg70: return true; 7035 case MCK_Reg71: return true; 7036 case MCK_DQuad: return true; 7037 } 7038 7039 case MCK_Reg66: 7040 switch (B) { 7041 default: return false; 7042 case MCK_Reg67: return true; 7043 case MCK_Reg72: return true; 7044 case MCK_Reg73: return true; 7045 case MCK_Reg70: return true; 7046 case MCK_QQPR: return true; 7047 case MCK_Reg71: return true; 7048 case MCK_DQuad: return true; 7049 } 7050 7051 case MCK_Reg39: 7052 switch (B) { 7053 default: return false; 7054 case MCK_Reg40: return true; 7055 case MCK_Reg37: return true; 7056 case MCK_Reg38: return true; 7057 case MCK_DPair: return true; 7058 } 7059 7060 case MCK_Reg18: 7061 switch (B) { 7062 default: return false; 7063 case MCK_hGPR: return true; 7064 case MCK_GPRnopc: return true; 7065 case MCK_GPR: return true; 7066 case MCK_GPRwithAPSR: return true; 7067 case MCK_GPRwithZR: return true; 7068 } 7069 7070 case MCK_Reg124: 7071 switch (B) { 7072 default: return false; 7073 case MCK_Reg125: return true; 7074 case MCK_Reg71: return true; 7075 case MCK_DQuad: return true; 7076 } 7077 7078 case MCK_Reg114: 7079 switch (B) { 7080 default: return false; 7081 case MCK_Reg115: return true; 7082 case MCK_Reg116: return true; 7083 case MCK_Reg117: return true; 7084 case MCK_DTripleSpc: return true; 7085 } 7086 7087 case MCK_Reg110: 7088 switch (B) { 7089 default: return false; 7090 case MCK_Reg111: return true; 7091 case MCK_Reg100: return true; 7092 case MCK_DTriple: return true; 7093 } 7094 7095 case MCK_Reg105: 7096 switch (B) { 7097 default: return false; 7098 case MCK_Reg106: return true; 7099 case MCK_Reg99: return true; 7100 case MCK_Reg100: return true; 7101 case MCK_DTriple: return true; 7102 } 7103 7104 case MCK_Reg97: 7105 switch (B) { 7106 default: return false; 7107 case MCK_Reg98: return true; 7108 case MCK_Reg99: return true; 7109 case MCK_Reg100: return true; 7110 case MCK_DTriple: return true; 7111 } 7112 7113 case MCK_Reg85: 7114 return B == MCK_QQQQPR; 7115 7116 case MCK_Reg75: 7117 switch (B) { 7118 default: return false; 7119 case MCK_Reg72: return true; 7120 case MCK_Reg73: return true; 7121 case MCK_Reg70: return true; 7122 case MCK_Reg71: return true; 7123 case MCK_DQuad: return true; 7124 } 7125 7126 case MCK_Reg67: 7127 switch (B) { 7128 default: return false; 7129 case MCK_Reg70: return true; 7130 case MCK_QQPR: return true; 7131 case MCK_Reg71: return true; 7132 case MCK_DQuad: return true; 7133 } 7134 7135 case MCK_Reg60: 7136 switch (B) { 7137 default: return false; 7138 case MCK_Reg61: return true; 7139 case MCK_Reg62: return true; 7140 case MCK_DPairSpc: return true; 7141 } 7142 7143 case MCK_Reg40: 7144 switch (B) { 7145 default: return false; 7146 case MCK_Reg37: return true; 7147 case MCK_Reg38: return true; 7148 case MCK_DPair: return true; 7149 } 7150 7151 case MCK_DPR_8: 7152 switch (B) { 7153 default: return false; 7154 case MCK_DPR_VFP2: return true; 7155 case MCK_DPR: return true; 7156 case MCK_FPWithVPR: return true; 7157 } 7158 7159 case MCK_MQPR: 7160 switch (B) { 7161 default: return false; 7162 case MCK_Reg37: return true; 7163 case MCK_Reg38: return true; 7164 case MCK_QPR: return true; 7165 case MCK_DPair: return true; 7166 } 7167 7168 case MCK_hGPR: 7169 return B == MCK_GPR; 7170 7171 case MCK_tGPR: 7172 switch (B) { 7173 default: return false; 7174 case MCK_tGPRwithpc: return true; 7175 case MCK_rGPR: return true; 7176 case MCK_GPRnopc: return true; 7177 case MCK_GPRwithAPSRnosp: return true; 7178 case MCK_GPRwithZRnosp: return true; 7179 case MCK_GPR: return true; 7180 case MCK_GPRwithAPSR: return true; 7181 case MCK_GPRwithZR: return true; 7182 } 7183 7184 case MCK_tGPREven: 7185 switch (B) { 7186 default: return false; 7187 case MCK_rGPR: return true; 7188 case MCK_GPRnopc: return true; 7189 case MCK_GPRwithAPSRnosp: return true; 7190 case MCK_GPRwithZRnosp: return true; 7191 case MCK_GPR: return true; 7192 case MCK_GPRwithAPSR: return true; 7193 case MCK_GPRwithZR: return true; 7194 } 7195 7196 case MCK_tGPRwithpc: 7197 return B == MCK_GPR; 7198 7199 case MCK_Reg115: 7200 switch (B) { 7201 default: return false; 7202 case MCK_Reg116: return true; 7203 case MCK_Reg117: return true; 7204 case MCK_DTripleSpc: return true; 7205 } 7206 7207 case MCK_Reg72: 7208 switch (B) { 7209 default: return false; 7210 case MCK_Reg73: return true; 7211 case MCK_Reg70: return true; 7212 case MCK_Reg71: return true; 7213 case MCK_DQuad: return true; 7214 } 7215 7216 case MCK_Reg125: 7217 return B == MCK_DQuad; 7218 7219 case MCK_Reg116: 7220 switch (B) { 7221 default: return false; 7222 case MCK_Reg117: return true; 7223 case MCK_DTripleSpc: return true; 7224 } 7225 7226 case MCK_Reg98: 7227 switch (B) { 7228 default: return false; 7229 case MCK_Reg99: return true; 7230 case MCK_Reg100: return true; 7231 case MCK_DTriple: return true; 7232 } 7233 7234 case MCK_Reg73: 7235 switch (B) { 7236 default: return false; 7237 case MCK_Reg70: return true; 7238 case MCK_Reg71: return true; 7239 case MCK_DQuad: return true; 7240 } 7241 7242 case MCK_Reg61: 7243 switch (B) { 7244 default: return false; 7245 case MCK_Reg62: return true; 7246 case MCK_DPairSpc: return true; 7247 } 7248 7249 case MCK_rGPR: 7250 switch (B) { 7251 default: return false; 7252 case MCK_GPRnopc: return true; 7253 case MCK_GPRwithAPSRnosp: return true; 7254 case MCK_GPRwithZRnosp: return true; 7255 case MCK_GPR: return true; 7256 case MCK_GPRwithAPSR: return true; 7257 case MCK_GPRwithZR: return true; 7258 } 7259 7260 case MCK_Reg111: 7261 return B == MCK_DTriple; 7262 7263 case MCK_Reg106: 7264 return B == MCK_DTriple; 7265 7266 case MCK_Reg99: 7267 switch (B) { 7268 default: return false; 7269 case MCK_Reg100: return true; 7270 case MCK_DTriple: return true; 7271 } 7272 7273 case MCK_Reg70: 7274 switch (B) { 7275 default: return false; 7276 case MCK_Reg71: return true; 7277 case MCK_DQuad: return true; 7278 } 7279 7280 case MCK_Reg37: 7281 switch (B) { 7282 default: return false; 7283 case MCK_Reg38: return true; 7284 case MCK_DPair: return true; 7285 } 7286 7287 case MCK_GPRnopc: 7288 switch (B) { 7289 default: return false; 7290 case MCK_GPR: return true; 7291 case MCK_GPRwithAPSR: return true; 7292 case MCK_GPRwithZR: return true; 7293 } 7294 7295 case MCK_GPRwithZRnosp: 7296 return B == MCK_GPRwithZR; 7297 7298 case MCK_QQPR: 7299 return B == MCK_DQuad; 7300 7301 case MCK_Reg117: 7302 return B == MCK_DTripleSpc; 7303 7304 case MCK_Reg100: 7305 return B == MCK_DTriple; 7306 7307 case MCK_Reg71: 7308 return B == MCK_DQuad; 7309 7310 case MCK_Reg62: 7311 return B == MCK_DPairSpc; 7312 7313 case MCK_Reg38: 7314 return B == MCK_DPair; 7315 7316 case MCK_DPR_VFP2: 7317 switch (B) { 7318 default: return false; 7319 case MCK_DPR: return true; 7320 case MCK_FPWithVPR: return true; 7321 } 7322 7323 case MCK_QPR: 7324 return B == MCK_DPair; 7325 7326 case MCK_SPR_8: 7327 switch (B) { 7328 default: return false; 7329 case MCK_HPR: return true; 7330 case MCK_FPWithVPR: return true; 7331 } 7332 7333 case MCK_DPR: 7334 return B == MCK_FPWithVPR; 7335 7336 case MCK_HPR: 7337 return B == MCK_FPWithVPR; 7338 } 7339} 7340 7341static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 7342 ARMOperand &Operand = (ARMOperand&)GOp; 7343 if (Kind == InvalidMatchClass) 7344 return MCTargetAsmParser::Match_InvalidOperand; 7345 7346 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 7347 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 7348 MCTargetAsmParser::Match_Success : 7349 MCTargetAsmParser::Match_InvalidOperand; 7350 7351 switch (Kind) { 7352 default: break; 7353 // 'AM2OffsetImm' class 7354 case MCK_AM2OffsetImm: { 7355 DiagnosticPredicate DP(Operand.isAM2OffsetImm()); 7356 if (DP.isMatch()) 7357 return MCTargetAsmParser::Match_Success; 7358 break; 7359 } 7360 // 'AM3Offset' class 7361 case MCK_AM3Offset: { 7362 DiagnosticPredicate DP(Operand.isAM3Offset()); 7363 if (DP.isMatch()) 7364 return MCTargetAsmParser::Match_Success; 7365 break; 7366 } 7367 // 'ARMBranchTarget' class 7368 case MCK_ARMBranchTarget: { 7369 DiagnosticPredicate DP(Operand.isARMBranchTarget()); 7370 if (DP.isMatch()) 7371 return MCTargetAsmParser::Match_Success; 7372 break; 7373 } 7374 // 'AddrMode3' class 7375 case MCK_AddrMode3: { 7376 DiagnosticPredicate DP(Operand.isAddrMode3()); 7377 if (DP.isMatch()) 7378 return MCTargetAsmParser::Match_Success; 7379 break; 7380 } 7381 // 'AddrMode5' class 7382 case MCK_AddrMode5: { 7383 DiagnosticPredicate DP(Operand.isAddrMode5()); 7384 if (DP.isMatch()) 7385 return MCTargetAsmParser::Match_Success; 7386 break; 7387 } 7388 // 'AddrMode5FP16' class 7389 case MCK_AddrMode5FP16: { 7390 DiagnosticPredicate DP(Operand.isAddrMode5FP16()); 7391 if (DP.isMatch()) 7392 return MCTargetAsmParser::Match_Success; 7393 break; 7394 } 7395 // 'AlignedMemory16' class 7396 case MCK_AlignedMemory16: { 7397 DiagnosticPredicate DP(Operand.isAlignedMemory16()); 7398 if (DP.isMatch()) 7399 return MCTargetAsmParser::Match_Success; 7400 if (DP.isNearMatch()) 7401 return ARMAsmParser::Match_AlignedMemory16; 7402 break; 7403 } 7404 // 'AlignedMemory32' class 7405 case MCK_AlignedMemory32: { 7406 DiagnosticPredicate DP(Operand.isAlignedMemory32()); 7407 if (DP.isMatch()) 7408 return MCTargetAsmParser::Match_Success; 7409 if (DP.isNearMatch()) 7410 return ARMAsmParser::Match_AlignedMemory32; 7411 break; 7412 } 7413 // 'AlignedMemory64' class 7414 case MCK_AlignedMemory64: { 7415 DiagnosticPredicate DP(Operand.isAlignedMemory64()); 7416 if (DP.isMatch()) 7417 return MCTargetAsmParser::Match_Success; 7418 if (DP.isNearMatch()) 7419 return ARMAsmParser::Match_AlignedMemory64; 7420 break; 7421 } 7422 // 'AlignedMemory64or128' class 7423 case MCK_AlignedMemory64or128: { 7424 DiagnosticPredicate DP(Operand.isAlignedMemory64or128()); 7425 if (DP.isMatch()) 7426 return MCTargetAsmParser::Match_Success; 7427 if (DP.isNearMatch()) 7428 return ARMAsmParser::Match_AlignedMemory64or128; 7429 break; 7430 } 7431 // 'AlignedMemory64or128or256' class 7432 case MCK_AlignedMemory64or128or256: { 7433 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256()); 7434 if (DP.isMatch()) 7435 return MCTargetAsmParser::Match_Success; 7436 if (DP.isNearMatch()) 7437 return ARMAsmParser::Match_AlignedMemory64or128or256; 7438 break; 7439 } 7440 // 'AlignedMemoryNone' class 7441 case MCK_AlignedMemoryNone: { 7442 DiagnosticPredicate DP(Operand.isAlignedMemoryNone()); 7443 if (DP.isMatch()) 7444 return MCTargetAsmParser::Match_Success; 7445 if (DP.isNearMatch()) 7446 return ARMAsmParser::Match_AlignedMemoryNone; 7447 break; 7448 } 7449 // 'AlignedMemory' class 7450 case MCK_AlignedMemory: { 7451 DiagnosticPredicate DP(Operand.isAlignedMemory()); 7452 if (DP.isMatch()) 7453 return MCTargetAsmParser::Match_Success; 7454 break; 7455 } 7456 // 'DupAlignedMemory16' class 7457 case MCK_DupAlignedMemory16: { 7458 DiagnosticPredicate DP(Operand.isDupAlignedMemory16()); 7459 if (DP.isMatch()) 7460 return MCTargetAsmParser::Match_Success; 7461 if (DP.isNearMatch()) 7462 return ARMAsmParser::Match_DupAlignedMemory16; 7463 break; 7464 } 7465 // 'DupAlignedMemory32' class 7466 case MCK_DupAlignedMemory32: { 7467 DiagnosticPredicate DP(Operand.isDupAlignedMemory32()); 7468 if (DP.isMatch()) 7469 return MCTargetAsmParser::Match_Success; 7470 if (DP.isNearMatch()) 7471 return ARMAsmParser::Match_DupAlignedMemory32; 7472 break; 7473 } 7474 // 'DupAlignedMemory64' class 7475 case MCK_DupAlignedMemory64: { 7476 DiagnosticPredicate DP(Operand.isDupAlignedMemory64()); 7477 if (DP.isMatch()) 7478 return MCTargetAsmParser::Match_Success; 7479 if (DP.isNearMatch()) 7480 return ARMAsmParser::Match_DupAlignedMemory64; 7481 break; 7482 } 7483 // 'DupAlignedMemory64or128' class 7484 case MCK_DupAlignedMemory64or128: { 7485 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128()); 7486 if (DP.isMatch()) 7487 return MCTargetAsmParser::Match_Success; 7488 if (DP.isNearMatch()) 7489 return ARMAsmParser::Match_DupAlignedMemory64or128; 7490 break; 7491 } 7492 // 'DupAlignedMemoryNone' class 7493 case MCK_DupAlignedMemoryNone: { 7494 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone()); 7495 if (DP.isMatch()) 7496 return MCTargetAsmParser::Match_Success; 7497 if (DP.isNearMatch()) 7498 return ARMAsmParser::Match_DupAlignedMemoryNone; 7499 break; 7500 } 7501 // 'AdrLabel' class 7502 case MCK_AdrLabel: { 7503 DiagnosticPredicate DP(Operand.isAdrLabel()); 7504 if (DP.isMatch()) 7505 return MCTargetAsmParser::Match_Success; 7506 break; 7507 } 7508 // 'BankedReg' class 7509 case MCK_BankedReg: { 7510 DiagnosticPredicate DP(Operand.isBankedReg()); 7511 if (DP.isMatch()) 7512 return MCTargetAsmParser::Match_Success; 7513 break; 7514 } 7515 // 'Bitfield' class 7516 case MCK_Bitfield: { 7517 DiagnosticPredicate DP(Operand.isBitfield()); 7518 if (DP.isMatch()) 7519 return MCTargetAsmParser::Match_Success; 7520 break; 7521 } 7522 // 'CCOut' class 7523 case MCK_CCOut: { 7524 DiagnosticPredicate DP(Operand.isCCOut()); 7525 if (DP.isMatch()) 7526 return MCTargetAsmParser::Match_Success; 7527 break; 7528 } 7529 // 'CondCode' class 7530 case MCK_CondCode: { 7531 DiagnosticPredicate DP(Operand.isCondCode()); 7532 if (DP.isMatch()) 7533 return MCTargetAsmParser::Match_Success; 7534 break; 7535 } 7536 // 'CoprocNum' class 7537 case MCK_CoprocNum: { 7538 DiagnosticPredicate DP(Operand.isCoprocNum()); 7539 if (DP.isMatch()) 7540 return MCTargetAsmParser::Match_Success; 7541 break; 7542 } 7543 // 'CoprocOption' class 7544 case MCK_CoprocOption: { 7545 DiagnosticPredicate DP(Operand.isCoprocOption()); 7546 if (DP.isMatch()) 7547 return MCTargetAsmParser::Match_Success; 7548 break; 7549 } 7550 // 'CoprocReg' class 7551 case MCK_CoprocReg: { 7552 DiagnosticPredicate DP(Operand.isCoprocReg()); 7553 if (DP.isMatch()) 7554 return MCTargetAsmParser::Match_Success; 7555 break; 7556 } 7557 // 'DPRRegList' class 7558 case MCK_DPRRegList: { 7559 DiagnosticPredicate DP(Operand.isDPRRegList()); 7560 if (DP.isMatch()) 7561 return MCTargetAsmParser::Match_Success; 7562 if (DP.isNearMatch()) 7563 return ARMAsmParser::Match_DPR_RegList; 7564 break; 7565 } 7566 // 'FPDRegListWithVPR' class 7567 case MCK_FPDRegListWithVPR: { 7568 DiagnosticPredicate DP(Operand.isFPDRegListWithVPR()); 7569 if (DP.isMatch()) 7570 return MCTargetAsmParser::Match_Success; 7571 break; 7572 } 7573 // 'FPImm' class 7574 case MCK_FPImm: { 7575 DiagnosticPredicate DP(Operand.isFPImm()); 7576 if (DP.isMatch()) 7577 return MCTargetAsmParser::Match_Success; 7578 break; 7579 } 7580 // 'FPSRegListWithVPR' class 7581 case MCK_FPSRegListWithVPR: { 7582 DiagnosticPredicate DP(Operand.isFPSRegListWithVPR()); 7583 if (DP.isMatch()) 7584 return MCTargetAsmParser::Match_Success; 7585 break; 7586 } 7587 // 'Imm0_15' class 7588 case MCK_Imm0_15: { 7589 DiagnosticPredicate DP(Operand.isImmediate<0,15>()); 7590 if (DP.isMatch()) 7591 return MCTargetAsmParser::Match_Success; 7592 if (DP.isNearMatch()) 7593 return ARMAsmParser::Match_Imm0_15; 7594 break; 7595 } 7596 // 'Imm0_1' class 7597 case MCK_Imm0_1: { 7598 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 7599 if (DP.isMatch()) 7600 return MCTargetAsmParser::Match_Success; 7601 if (DP.isNearMatch()) 7602 return ARMAsmParser::Match_Imm0_1; 7603 break; 7604 } 7605 // 'Imm0_239' class 7606 case MCK_Imm0_239: { 7607 DiagnosticPredicate DP(Operand.isImmediate<0,239>()); 7608 if (DP.isMatch()) 7609 return MCTargetAsmParser::Match_Success; 7610 if (DP.isNearMatch()) 7611 return ARMAsmParser::Match_Imm0_239; 7612 break; 7613 } 7614 // 'Imm0_255' class 7615 case MCK_Imm0_255: { 7616 DiagnosticPredicate DP(Operand.isImmediate<0,255>()); 7617 if (DP.isMatch()) 7618 return MCTargetAsmParser::Match_Success; 7619 if (DP.isNearMatch()) 7620 return ARMAsmParser::Match_Imm0_255; 7621 break; 7622 } 7623 // 'Imm0_31' class 7624 case MCK_Imm0_31: { 7625 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 7626 if (DP.isMatch()) 7627 return MCTargetAsmParser::Match_Success; 7628 if (DP.isNearMatch()) 7629 return ARMAsmParser::Match_Imm0_31; 7630 break; 7631 } 7632 // 'Imm0_32' class 7633 case MCK_Imm0_32: { 7634 DiagnosticPredicate DP(Operand.isImmediate<0,32>()); 7635 if (DP.isMatch()) 7636 return MCTargetAsmParser::Match_Success; 7637 if (DP.isNearMatch()) 7638 return ARMAsmParser::Match_Imm0_32; 7639 break; 7640 } 7641 // 'Imm0_3' class 7642 case MCK_Imm0_3: { 7643 DiagnosticPredicate DP(Operand.isImmediate<0,3>()); 7644 if (DP.isMatch()) 7645 return MCTargetAsmParser::Match_Success; 7646 if (DP.isNearMatch()) 7647 return ARMAsmParser::Match_Imm0_3; 7648 break; 7649 } 7650 // 'Imm0_63' class 7651 case MCK_Imm0_63: { 7652 DiagnosticPredicate DP(Operand.isImmediate<0,63>()); 7653 if (DP.isMatch()) 7654 return MCTargetAsmParser::Match_Success; 7655 if (DP.isNearMatch()) 7656 return ARMAsmParser::Match_Imm0_63; 7657 break; 7658 } 7659 // 'Imm0_65535' class 7660 case MCK_Imm0_65535: { 7661 DiagnosticPredicate DP(Operand.isImmediate<0,65535>()); 7662 if (DP.isMatch()) 7663 return MCTargetAsmParser::Match_Success; 7664 if (DP.isNearMatch()) 7665 return ARMAsmParser::Match_Imm0_65535; 7666 break; 7667 } 7668 // 'Imm0_65535Expr' class 7669 case MCK_Imm0_65535Expr: { 7670 DiagnosticPredicate DP(Operand.isImm0_65535Expr()); 7671 if (DP.isMatch()) 7672 return MCTargetAsmParser::Match_Success; 7673 if (DP.isNearMatch()) 7674 return ARMAsmParser::Match_Imm0_65535Expr; 7675 break; 7676 } 7677 // 'Imm0_7' class 7678 case MCK_Imm0_7: { 7679 DiagnosticPredicate DP(Operand.isImmediate<0,7>()); 7680 if (DP.isMatch()) 7681 return MCTargetAsmParser::Match_Success; 7682 if (DP.isNearMatch()) 7683 return ARMAsmParser::Match_Imm0_7; 7684 break; 7685 } 7686 // 'Imm16' class 7687 case MCK_Imm16: { 7688 DiagnosticPredicate DP(Operand.isImmediate<16,16>()); 7689 if (DP.isMatch()) 7690 return MCTargetAsmParser::Match_Success; 7691 if (DP.isNearMatch()) 7692 return ARMAsmParser::Match_Imm16; 7693 break; 7694 } 7695 // 'Imm1_15' class 7696 case MCK_Imm1_15: { 7697 DiagnosticPredicate DP(Operand.isImmediate<1,15>()); 7698 if (DP.isMatch()) 7699 return MCTargetAsmParser::Match_Success; 7700 if (DP.isNearMatch()) 7701 return ARMAsmParser::Match_Imm1_15; 7702 break; 7703 } 7704 // 'Imm1_16' class 7705 case MCK_Imm1_16: { 7706 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 7707 if (DP.isMatch()) 7708 return MCTargetAsmParser::Match_Success; 7709 if (DP.isNearMatch()) 7710 return ARMAsmParser::Match_ImmRange1_16; 7711 break; 7712 } 7713 // 'Imm1_31' class 7714 case MCK_Imm1_31: { 7715 DiagnosticPredicate DP(Operand.isImmediate<1,31>()); 7716 if (DP.isMatch()) 7717 return MCTargetAsmParser::Match_Success; 7718 if (DP.isNearMatch()) 7719 return ARMAsmParser::Match_Imm1_31; 7720 break; 7721 } 7722 // 'Imm1_32' class 7723 case MCK_Imm1_32: { 7724 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 7725 if (DP.isMatch()) 7726 return MCTargetAsmParser::Match_Success; 7727 if (DP.isNearMatch()) 7728 return ARMAsmParser::Match_ImmRange1_32; 7729 break; 7730 } 7731 // 'Imm1_7' class 7732 case MCK_Imm1_7: { 7733 DiagnosticPredicate DP(Operand.isImmediate<1,7>()); 7734 if (DP.isMatch()) 7735 return MCTargetAsmParser::Match_Success; 7736 if (DP.isNearMatch()) 7737 return ARMAsmParser::Match_Imm1_7; 7738 break; 7739 } 7740 // 'Imm24bit' class 7741 case MCK_Imm24bit: { 7742 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>()); 7743 if (DP.isMatch()) 7744 return MCTargetAsmParser::Match_Success; 7745 if (DP.isNearMatch()) 7746 return ARMAsmParser::Match_Imm24bit; 7747 break; 7748 } 7749 // 'Imm256_65535Expr' class 7750 case MCK_Imm256_65535Expr: { 7751 DiagnosticPredicate DP(Operand.isImmediate<256,65535>()); 7752 if (DP.isMatch()) 7753 return MCTargetAsmParser::Match_Success; 7754 if (DP.isNearMatch()) 7755 return ARMAsmParser::Match_Imm256_65535Expr; 7756 break; 7757 } 7758 // 'Imm32' class 7759 case MCK_Imm32: { 7760 DiagnosticPredicate DP(Operand.isImmediate<32,32>()); 7761 if (DP.isMatch()) 7762 return MCTargetAsmParser::Match_Success; 7763 if (DP.isNearMatch()) 7764 return ARMAsmParser::Match_Imm32; 7765 break; 7766 } 7767 // 'Imm8' class 7768 case MCK_Imm8: { 7769 DiagnosticPredicate DP(Operand.isImmediate<8,8>()); 7770 if (DP.isMatch()) 7771 return MCTargetAsmParser::Match_Success; 7772 if (DP.isNearMatch()) 7773 return ARMAsmParser::Match_Imm8; 7774 break; 7775 } 7776 // 'Imm8_255' class 7777 case MCK_Imm8_255: { 7778 DiagnosticPredicate DP(Operand.isImmediate<8,255>()); 7779 if (DP.isMatch()) 7780 return MCTargetAsmParser::Match_Success; 7781 if (DP.isNearMatch()) 7782 return ARMAsmParser::Match_Imm8_255; 7783 break; 7784 } 7785 // 'Imm' class 7786 case MCK_Imm: { 7787 DiagnosticPredicate DP(Operand.isImm()); 7788 if (DP.isMatch()) 7789 return MCTargetAsmParser::Match_Success; 7790 break; 7791 } 7792 // 'InstSyncBarrierOpt' class 7793 case MCK_InstSyncBarrierOpt: { 7794 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt()); 7795 if (DP.isMatch()) 7796 return MCTargetAsmParser::Match_Success; 7797 break; 7798 } 7799 // 'MSRMask' class 7800 case MCK_MSRMask: { 7801 DiagnosticPredicate DP(Operand.isMSRMask()); 7802 if (DP.isMatch()) 7803 return MCTargetAsmParser::Match_Success; 7804 break; 7805 } 7806 // 'MVEShiftImm1_15' class 7807 case MCK_MVEShiftImm1_15: { 7808 DiagnosticPredicate DP(Operand.isImmediate<1,15>()); 7809 if (DP.isMatch()) 7810 return MCTargetAsmParser::Match_Success; 7811 if (DP.isNearMatch()) 7812 return ARMAsmParser::Match_MVEShiftImm1_15; 7813 break; 7814 } 7815 // 'MVEShiftImm1_7' class 7816 case MCK_MVEShiftImm1_7: { 7817 DiagnosticPredicate DP(Operand.isImmediate<1,7>()); 7818 if (DP.isMatch()) 7819 return MCTargetAsmParser::Match_Success; 7820 if (DP.isNearMatch()) 7821 return ARMAsmParser::Match_MVEShiftImm1_7; 7822 break; 7823 } 7824 // 'VIDUP_imm' class 7825 case MCK_VIDUP_imm: { 7826 DiagnosticPredicate DP(Operand.isPowerTwoInRange<1,8>()); 7827 if (DP.isMatch()) 7828 return MCTargetAsmParser::Match_Success; 7829 if (DP.isNearMatch()) 7830 return ARMAsmParser::Match_VIDUP_imm; 7831 break; 7832 } 7833 // 'MemBarrierOpt' class 7834 case MCK_MemBarrierOpt: { 7835 DiagnosticPredicate DP(Operand.isMemBarrierOpt()); 7836 if (DP.isMatch()) 7837 return MCTargetAsmParser::Match_Success; 7838 break; 7839 } 7840 // 'MemImm0_1020s4Offset' class 7841 case MCK_MemImm0_1020s4Offset: { 7842 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset()); 7843 if (DP.isMatch()) 7844 return MCTargetAsmParser::Match_Success; 7845 break; 7846 } 7847 // 'MemImm12Offset' class 7848 case MCK_MemImm12Offset: { 7849 DiagnosticPredicate DP(Operand.isMemImm12Offset()); 7850 if (DP.isMatch()) 7851 return MCTargetAsmParser::Match_Success; 7852 break; 7853 } 7854 // 'MemImm7Shift0Offset' class 7855 case MCK_MemImm7Shift0Offset: { 7856 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>()); 7857 if (DP.isMatch()) 7858 return MCTargetAsmParser::Match_Success; 7859 break; 7860 } 7861 // 'MemImm7Shift0OffsetWB' class 7862 case MCK_MemImm7Shift0OffsetWB: { 7863 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>()); 7864 if (DP.isMatch()) 7865 return MCTargetAsmParser::Match_Success; 7866 break; 7867 } 7868 // 'MemImm7Shift1Offset' class 7869 case MCK_MemImm7Shift1Offset: { 7870 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>()); 7871 if (DP.isMatch()) 7872 return MCTargetAsmParser::Match_Success; 7873 break; 7874 } 7875 // 'MemImm7Shift1OffsetWB' class 7876 case MCK_MemImm7Shift1OffsetWB: { 7877 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>()); 7878 if (DP.isMatch()) 7879 return MCTargetAsmParser::Match_Success; 7880 break; 7881 } 7882 // 'MemImm7Shift2Offset' class 7883 case MCK_MemImm7Shift2Offset: { 7884 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>()); 7885 if (DP.isMatch()) 7886 return MCTargetAsmParser::Match_Success; 7887 break; 7888 } 7889 // 'MemImm7Shift2OffsetWB' class 7890 case MCK_MemImm7Shift2OffsetWB: { 7891 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>()); 7892 if (DP.isMatch()) 7893 return MCTargetAsmParser::Match_Success; 7894 break; 7895 } 7896 // 'MemImm7s4Offset' class 7897 case MCK_MemImm7s4Offset: { 7898 DiagnosticPredicate DP(Operand.isMemImm7s4Offset()); 7899 if (DP.isMatch()) 7900 return MCTargetAsmParser::Match_Success; 7901 break; 7902 } 7903 // 'MemImm8Offset' class 7904 case MCK_MemImm8Offset: { 7905 DiagnosticPredicate DP(Operand.isMemImm8Offset()); 7906 if (DP.isMatch()) 7907 return MCTargetAsmParser::Match_Success; 7908 break; 7909 } 7910 // 'MemImm8s4Offset' class 7911 case MCK_MemImm8s4Offset: { 7912 DiagnosticPredicate DP(Operand.isMemImm8s4Offset()); 7913 if (DP.isMatch()) 7914 return MCTargetAsmParser::Match_Success; 7915 break; 7916 } 7917 // 'MemNegImm8Offset' class 7918 case MCK_MemNegImm8Offset: { 7919 DiagnosticPredicate DP(Operand.isMemNegImm8Offset()); 7920 if (DP.isMatch()) 7921 return MCTargetAsmParser::Match_Success; 7922 break; 7923 } 7924 // 'MemNoOffset' class 7925 case MCK_MemNoOffset: { 7926 DiagnosticPredicate DP(Operand.isMemNoOffset()); 7927 if (DP.isMatch()) 7928 return MCTargetAsmParser::Match_Success; 7929 break; 7930 } 7931 // 'MemNoOffsetT2' class 7932 case MCK_MemNoOffsetT2: { 7933 DiagnosticPredicate DP(Operand.isMemNoOffsetT2()); 7934 if (DP.isMatch()) 7935 return MCTargetAsmParser::Match_Success; 7936 break; 7937 } 7938 // 'MemNoOffsetT2NoSp' class 7939 case MCK_MemNoOffsetT2NoSp: { 7940 DiagnosticPredicate DP(Operand.isMemNoOffsetT2NoSp()); 7941 if (DP.isMatch()) 7942 return MCTargetAsmParser::Match_Success; 7943 break; 7944 } 7945 // 'MemNoOffsetT' class 7946 case MCK_MemNoOffsetT: { 7947 DiagnosticPredicate DP(Operand.isMemNoOffsetT()); 7948 if (DP.isMatch()) 7949 return MCTargetAsmParser::Match_Success; 7950 break; 7951 } 7952 // 'MemPosImm8Offset' class 7953 case MCK_MemPosImm8Offset: { 7954 DiagnosticPredicate DP(Operand.isMemPosImm8Offset()); 7955 if (DP.isMatch()) 7956 return MCTargetAsmParser::Match_Success; 7957 break; 7958 } 7959 // 'MemRegOffset' class 7960 case MCK_MemRegOffset: { 7961 DiagnosticPredicate DP(Operand.isMemRegOffset()); 7962 if (DP.isMatch()) 7963 return MCTargetAsmParser::Match_Success; 7964 break; 7965 } 7966 // 'MemRegQS2Offset' class 7967 case MCK_MemRegQS2Offset: { 7968 DiagnosticPredicate DP(Operand.isMemRegQOffset<2>()); 7969 if (DP.isMatch()) 7970 return MCTargetAsmParser::Match_Success; 7971 break; 7972 } 7973 // 'MemRegQS3Offset' class 7974 case MCK_MemRegQS3Offset: { 7975 DiagnosticPredicate DP(Operand.isMemRegQOffset<3>()); 7976 if (DP.isMatch()) 7977 return MCTargetAsmParser::Match_Success; 7978 break; 7979 } 7980 // 'MemRegRQS0Offset' class 7981 case MCK_MemRegRQS0Offset: { 7982 DiagnosticPredicate DP(Operand.isMemRegRQOffset<0>()); 7983 if (DP.isMatch()) 7984 return MCTargetAsmParser::Match_Success; 7985 break; 7986 } 7987 // 'MemRegRQS1Offset' class 7988 case MCK_MemRegRQS1Offset: { 7989 DiagnosticPredicate DP(Operand.isMemRegRQOffset<1>()); 7990 if (DP.isMatch()) 7991 return MCTargetAsmParser::Match_Success; 7992 break; 7993 } 7994 // 'MemRegRQS2Offset' class 7995 case MCK_MemRegRQS2Offset: { 7996 DiagnosticPredicate DP(Operand.isMemRegRQOffset<2>()); 7997 if (DP.isMatch()) 7998 return MCTargetAsmParser::Match_Success; 7999 break; 8000 } 8001 // 'MemRegRQS3Offset' class 8002 case MCK_MemRegRQS3Offset: { 8003 DiagnosticPredicate DP(Operand.isMemRegRQOffset<3>()); 8004 if (DP.isMatch()) 8005 return MCTargetAsmParser::Match_Success; 8006 break; 8007 } 8008 // 'ModImm' class 8009 case MCK_ModImm: { 8010 DiagnosticPredicate DP(Operand.isModImm()); 8011 if (DP.isMatch()) 8012 return MCTargetAsmParser::Match_Success; 8013 break; 8014 } 8015 // 'ModImmNeg' class 8016 case MCK_ModImmNeg: { 8017 DiagnosticPredicate DP(Operand.isModImmNeg()); 8018 if (DP.isMatch()) 8019 return MCTargetAsmParser::Match_Success; 8020 break; 8021 } 8022 // 'ModImmNot' class 8023 case MCK_ModImmNot: { 8024 DiagnosticPredicate DP(Operand.isModImmNot()); 8025 if (DP.isMatch()) 8026 return MCTargetAsmParser::Match_Success; 8027 break; 8028 } 8029 // 'MveSaturate' class 8030 case MCK_MveSaturate: { 8031 DiagnosticPredicate DP(Operand.isMveSaturateOp()); 8032 if (DP.isMatch()) 8033 return MCTargetAsmParser::Match_Success; 8034 if (DP.isNearMatch()) 8035 return ARMAsmParser::Match_MveSaturate; 8036 break; 8037 } 8038 // 'PKHASRImm' class 8039 case MCK_PKHASRImm: { 8040 DiagnosticPredicate DP(Operand.isPKHASRImm()); 8041 if (DP.isMatch()) 8042 return MCTargetAsmParser::Match_Success; 8043 break; 8044 } 8045 // 'PKHLSLImm' class 8046 case MCK_PKHLSLImm: { 8047 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 8048 if (DP.isMatch()) 8049 return MCTargetAsmParser::Match_Success; 8050 if (DP.isNearMatch()) 8051 return ARMAsmParser::Match_PKHLSLImm; 8052 break; 8053 } 8054 // 'PostIdxImm8' class 8055 case MCK_PostIdxImm8: { 8056 DiagnosticPredicate DP(Operand.isPostIdxImm8()); 8057 if (DP.isMatch()) 8058 return MCTargetAsmParser::Match_Success; 8059 break; 8060 } 8061 // 'PostIdxImm8s4' class 8062 case MCK_PostIdxImm8s4: { 8063 DiagnosticPredicate DP(Operand.isPostIdxImm8s4()); 8064 if (DP.isMatch()) 8065 return MCTargetAsmParser::Match_Success; 8066 break; 8067 } 8068 // 'PostIdxReg' class 8069 case MCK_PostIdxReg: { 8070 DiagnosticPredicate DP(Operand.isPostIdxReg()); 8071 if (DP.isMatch()) 8072 return MCTargetAsmParser::Match_Success; 8073 break; 8074 } 8075 // 'PostIdxRegShifted' class 8076 case MCK_PostIdxRegShifted: { 8077 DiagnosticPredicate DP(Operand.isPostIdxRegShifted()); 8078 if (DP.isMatch()) 8079 return MCTargetAsmParser::Match_Success; 8080 break; 8081 } 8082 // 'ProcIFlags' class 8083 case MCK_ProcIFlags: { 8084 DiagnosticPredicate DP(Operand.isProcIFlags()); 8085 if (DP.isMatch()) 8086 return MCTargetAsmParser::Match_Success; 8087 break; 8088 } 8089 // 'RegList' class 8090 case MCK_RegList: { 8091 DiagnosticPredicate DP(Operand.isRegList()); 8092 if (DP.isMatch()) 8093 return MCTargetAsmParser::Match_Success; 8094 break; 8095 } 8096 // 'RegListWithAPSR' class 8097 case MCK_RegListWithAPSR: { 8098 DiagnosticPredicate DP(Operand.isRegListWithAPSR()); 8099 if (DP.isMatch()) 8100 return MCTargetAsmParser::Match_Success; 8101 break; 8102 } 8103 // 'RotImm' class 8104 case MCK_RotImm: { 8105 DiagnosticPredicate DP(Operand.isRotImm()); 8106 if (DP.isMatch()) 8107 return MCTargetAsmParser::Match_Success; 8108 break; 8109 } 8110 // 'SPRRegList' class 8111 case MCK_SPRRegList: { 8112 DiagnosticPredicate DP(Operand.isSPRRegList()); 8113 if (DP.isMatch()) 8114 return MCTargetAsmParser::Match_Success; 8115 if (DP.isNearMatch()) 8116 return ARMAsmParser::Match_SPRRegList; 8117 break; 8118 } 8119 // 'SetEndImm' class 8120 case MCK_SetEndImm: { 8121 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 8122 if (DP.isMatch()) 8123 return MCTargetAsmParser::Match_Success; 8124 if (DP.isNearMatch()) 8125 return ARMAsmParser::Match_SetEndImm; 8126 break; 8127 } 8128 // 'RegShiftedImm' class 8129 case MCK_RegShiftedImm: { 8130 DiagnosticPredicate DP(Operand.isRegShiftedImm()); 8131 if (DP.isMatch()) 8132 return MCTargetAsmParser::Match_Success; 8133 break; 8134 } 8135 // 'RegShiftedReg' class 8136 case MCK_RegShiftedReg: { 8137 DiagnosticPredicate DP(Operand.isRegShiftedReg()); 8138 if (DP.isMatch()) 8139 return MCTargetAsmParser::Match_Success; 8140 break; 8141 } 8142 // 'ShifterImm' class 8143 case MCK_ShifterImm: { 8144 DiagnosticPredicate DP(Operand.isShifterImm()); 8145 if (DP.isMatch()) 8146 return MCTargetAsmParser::Match_Success; 8147 break; 8148 } 8149 // 'ThumbBranchTarget' class 8150 case MCK_ThumbBranchTarget: { 8151 DiagnosticPredicate DP(Operand.isThumbBranchTarget()); 8152 if (DP.isMatch()) 8153 return MCTargetAsmParser::Match_Success; 8154 break; 8155 } 8156 // 'ThumbMemPC' class 8157 case MCK_ThumbMemPC: { 8158 DiagnosticPredicate DP(Operand.isThumbMemPC()); 8159 if (DP.isMatch()) 8160 return MCTargetAsmParser::Match_Success; 8161 break; 8162 } 8163 // 'ThumbModImmNeg1_7' class 8164 case MCK_ThumbModImmNeg1_7: { 8165 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7()); 8166 if (DP.isMatch()) 8167 return MCTargetAsmParser::Match_Success; 8168 break; 8169 } 8170 // 'ThumbModImmNeg8_255' class 8171 case MCK_ThumbModImmNeg8_255: { 8172 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255()); 8173 if (DP.isMatch()) 8174 return MCTargetAsmParser::Match_Success; 8175 break; 8176 } 8177 // 'ImmThumbSR' class 8178 case MCK_ImmThumbSR: { 8179 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 8180 if (DP.isMatch()) 8181 return MCTargetAsmParser::Match_Success; 8182 if (DP.isNearMatch()) 8183 return ARMAsmParser::Match_ImmThumbSR; 8184 break; 8185 } 8186 // 'TraceSyncBarrierOpt' class 8187 case MCK_TraceSyncBarrierOpt: { 8188 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt()); 8189 if (DP.isMatch()) 8190 return MCTargetAsmParser::Match_Success; 8191 break; 8192 } 8193 // 'UnsignedOffset_b8s2' class 8194 case MCK_UnsignedOffset_b8s2: { 8195 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>()); 8196 if (DP.isMatch()) 8197 return MCTargetAsmParser::Match_Success; 8198 break; 8199 } 8200 // 'VPTPredN' class 8201 case MCK_VPTPredN: { 8202 DiagnosticPredicate DP(Operand.isVPTPred()); 8203 if (DP.isMatch()) 8204 return MCTargetAsmParser::Match_Success; 8205 break; 8206 } 8207 // 'VPTPredR' class 8208 case MCK_VPTPredR: { 8209 DiagnosticPredicate DP(Operand.isVPTPred()); 8210 if (DP.isMatch()) 8211 return MCTargetAsmParser::Match_Success; 8212 break; 8213 } 8214 // 'VecListTwoMQ' class 8215 case MCK_VecListTwoMQ: { 8216 DiagnosticPredicate DP(Operand.isVecListTwoMQ()); 8217 if (DP.isMatch()) 8218 return MCTargetAsmParser::Match_Success; 8219 if (DP.isNearMatch()) 8220 return ARMAsmParser::Match_VecListTwoMQ; 8221 break; 8222 } 8223 // 'VecListFourMQ' class 8224 case MCK_VecListFourMQ: { 8225 DiagnosticPredicate DP(Operand.isVecListFourMQ()); 8226 if (DP.isMatch()) 8227 return MCTargetAsmParser::Match_Success; 8228 if (DP.isNearMatch()) 8229 return ARMAsmParser::Match_VecListFourMQ; 8230 break; 8231 } 8232 // 'VecListDPairAllLanes' class 8233 case MCK_VecListDPairAllLanes: { 8234 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes()); 8235 if (DP.isMatch()) 8236 return MCTargetAsmParser::Match_Success; 8237 break; 8238 } 8239 // 'VecListDPair' class 8240 case MCK_VecListDPair: { 8241 DiagnosticPredicate DP(Operand.isVecListDPair()); 8242 if (DP.isMatch()) 8243 return MCTargetAsmParser::Match_Success; 8244 break; 8245 } 8246 // 'VecListDPairSpacedAllLanes' class 8247 case MCK_VecListDPairSpacedAllLanes: { 8248 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes()); 8249 if (DP.isMatch()) 8250 return MCTargetAsmParser::Match_Success; 8251 break; 8252 } 8253 // 'VecListDPairSpaced' class 8254 case MCK_VecListDPairSpaced: { 8255 DiagnosticPredicate DP(Operand.isVecListDPairSpaced()); 8256 if (DP.isMatch()) 8257 return MCTargetAsmParser::Match_Success; 8258 break; 8259 } 8260 // 'VecListFourDAllLanes' class 8261 case MCK_VecListFourDAllLanes: { 8262 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes()); 8263 if (DP.isMatch()) 8264 return MCTargetAsmParser::Match_Success; 8265 break; 8266 } 8267 // 'VecListFourD' class 8268 case MCK_VecListFourD: { 8269 DiagnosticPredicate DP(Operand.isVecListFourD()); 8270 if (DP.isMatch()) 8271 return MCTargetAsmParser::Match_Success; 8272 break; 8273 } 8274 // 'VecListFourDByteIndexed' class 8275 case MCK_VecListFourDByteIndexed: { 8276 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed()); 8277 if (DP.isMatch()) 8278 return MCTargetAsmParser::Match_Success; 8279 break; 8280 } 8281 // 'VecListFourDHWordIndexed' class 8282 case MCK_VecListFourDHWordIndexed: { 8283 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed()); 8284 if (DP.isMatch()) 8285 return MCTargetAsmParser::Match_Success; 8286 break; 8287 } 8288 // 'VecListFourDWordIndexed' class 8289 case MCK_VecListFourDWordIndexed: { 8290 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed()); 8291 if (DP.isMatch()) 8292 return MCTargetAsmParser::Match_Success; 8293 break; 8294 } 8295 // 'VecListFourQAllLanes' class 8296 case MCK_VecListFourQAllLanes: { 8297 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes()); 8298 if (DP.isMatch()) 8299 return MCTargetAsmParser::Match_Success; 8300 break; 8301 } 8302 // 'VecListFourQ' class 8303 case MCK_VecListFourQ: { 8304 DiagnosticPredicate DP(Operand.isVecListFourQ()); 8305 if (DP.isMatch()) 8306 return MCTargetAsmParser::Match_Success; 8307 break; 8308 } 8309 // 'VecListFourQHWordIndexed' class 8310 case MCK_VecListFourQHWordIndexed: { 8311 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed()); 8312 if (DP.isMatch()) 8313 return MCTargetAsmParser::Match_Success; 8314 break; 8315 } 8316 // 'VecListFourQWordIndexed' class 8317 case MCK_VecListFourQWordIndexed: { 8318 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed()); 8319 if (DP.isMatch()) 8320 return MCTargetAsmParser::Match_Success; 8321 break; 8322 } 8323 // 'VecListOneDAllLanes' class 8324 case MCK_VecListOneDAllLanes: { 8325 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes()); 8326 if (DP.isMatch()) 8327 return MCTargetAsmParser::Match_Success; 8328 break; 8329 } 8330 // 'VecListOneD' class 8331 case MCK_VecListOneD: { 8332 DiagnosticPredicate DP(Operand.isVecListOneD()); 8333 if (DP.isMatch()) 8334 return MCTargetAsmParser::Match_Success; 8335 break; 8336 } 8337 // 'VecListOneDByteIndexed' class 8338 case MCK_VecListOneDByteIndexed: { 8339 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed()); 8340 if (DP.isMatch()) 8341 return MCTargetAsmParser::Match_Success; 8342 break; 8343 } 8344 // 'VecListOneDHWordIndexed' class 8345 case MCK_VecListOneDHWordIndexed: { 8346 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed()); 8347 if (DP.isMatch()) 8348 return MCTargetAsmParser::Match_Success; 8349 break; 8350 } 8351 // 'VecListOneDWordIndexed' class 8352 case MCK_VecListOneDWordIndexed: { 8353 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed()); 8354 if (DP.isMatch()) 8355 return MCTargetAsmParser::Match_Success; 8356 break; 8357 } 8358 // 'VecListThreeDAllLanes' class 8359 case MCK_VecListThreeDAllLanes: { 8360 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes()); 8361 if (DP.isMatch()) 8362 return MCTargetAsmParser::Match_Success; 8363 break; 8364 } 8365 // 'VecListThreeD' class 8366 case MCK_VecListThreeD: { 8367 DiagnosticPredicate DP(Operand.isVecListThreeD()); 8368 if (DP.isMatch()) 8369 return MCTargetAsmParser::Match_Success; 8370 break; 8371 } 8372 // 'VecListThreeDByteIndexed' class 8373 case MCK_VecListThreeDByteIndexed: { 8374 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed()); 8375 if (DP.isMatch()) 8376 return MCTargetAsmParser::Match_Success; 8377 break; 8378 } 8379 // 'VecListThreeDHWordIndexed' class 8380 case MCK_VecListThreeDHWordIndexed: { 8381 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed()); 8382 if (DP.isMatch()) 8383 return MCTargetAsmParser::Match_Success; 8384 break; 8385 } 8386 // 'VecListThreeDWordIndexed' class 8387 case MCK_VecListThreeDWordIndexed: { 8388 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed()); 8389 if (DP.isMatch()) 8390 return MCTargetAsmParser::Match_Success; 8391 break; 8392 } 8393 // 'VecListThreeQAllLanes' class 8394 case MCK_VecListThreeQAllLanes: { 8395 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes()); 8396 if (DP.isMatch()) 8397 return MCTargetAsmParser::Match_Success; 8398 break; 8399 } 8400 // 'VecListThreeQ' class 8401 case MCK_VecListThreeQ: { 8402 DiagnosticPredicate DP(Operand.isVecListThreeQ()); 8403 if (DP.isMatch()) 8404 return MCTargetAsmParser::Match_Success; 8405 break; 8406 } 8407 // 'VecListThreeQHWordIndexed' class 8408 case MCK_VecListThreeQHWordIndexed: { 8409 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed()); 8410 if (DP.isMatch()) 8411 return MCTargetAsmParser::Match_Success; 8412 break; 8413 } 8414 // 'VecListThreeQWordIndexed' class 8415 case MCK_VecListThreeQWordIndexed: { 8416 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed()); 8417 if (DP.isMatch()) 8418 return MCTargetAsmParser::Match_Success; 8419 break; 8420 } 8421 // 'VecListTwoDByteIndexed' class 8422 case MCK_VecListTwoDByteIndexed: { 8423 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed()); 8424 if (DP.isMatch()) 8425 return MCTargetAsmParser::Match_Success; 8426 break; 8427 } 8428 // 'VecListTwoDHWordIndexed' class 8429 case MCK_VecListTwoDHWordIndexed: { 8430 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed()); 8431 if (DP.isMatch()) 8432 return MCTargetAsmParser::Match_Success; 8433 break; 8434 } 8435 // 'VecListTwoDWordIndexed' class 8436 case MCK_VecListTwoDWordIndexed: { 8437 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed()); 8438 if (DP.isMatch()) 8439 return MCTargetAsmParser::Match_Success; 8440 break; 8441 } 8442 // 'VecListTwoQHWordIndexed' class 8443 case MCK_VecListTwoQHWordIndexed: { 8444 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed()); 8445 if (DP.isMatch()) 8446 return MCTargetAsmParser::Match_Success; 8447 break; 8448 } 8449 // 'VecListTwoQWordIndexed' class 8450 case MCK_VecListTwoQWordIndexed: { 8451 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed()); 8452 if (DP.isMatch()) 8453 return MCTargetAsmParser::Match_Success; 8454 break; 8455 } 8456 // 'VectorIndex16' class 8457 case MCK_VectorIndex16: { 8458 DiagnosticPredicate DP(Operand.isVectorIndex16()); 8459 if (DP.isMatch()) 8460 return MCTargetAsmParser::Match_Success; 8461 break; 8462 } 8463 // 'VectorIndex32' class 8464 case MCK_VectorIndex32: { 8465 DiagnosticPredicate DP(Operand.isVectorIndex32()); 8466 if (DP.isMatch()) 8467 return MCTargetAsmParser::Match_Success; 8468 break; 8469 } 8470 // 'VectorIndex64' class 8471 case MCK_VectorIndex64: { 8472 DiagnosticPredicate DP(Operand.isVectorIndex64()); 8473 if (DP.isMatch()) 8474 return MCTargetAsmParser::Match_Success; 8475 break; 8476 } 8477 // 'VectorIndex8' class 8478 case MCK_VectorIndex8: { 8479 DiagnosticPredicate DP(Operand.isVectorIndex8()); 8480 if (DP.isMatch()) 8481 return MCTargetAsmParser::Match_Success; 8482 break; 8483 } 8484 // 'MemTBB' class 8485 case MCK_MemTBB: { 8486 DiagnosticPredicate DP(Operand.isMemTBB()); 8487 if (DP.isMatch()) 8488 return MCTargetAsmParser::Match_Success; 8489 break; 8490 } 8491 // 'MemTBH' class 8492 case MCK_MemTBH: { 8493 DiagnosticPredicate DP(Operand.isMemTBH()); 8494 if (DP.isMatch()) 8495 return MCTargetAsmParser::Match_Success; 8496 break; 8497 } 8498 // 'MVEPairVectorIndex0' class 8499 case MCK_MVEPairVectorIndex0: { 8500 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<0, 1>()); 8501 if (DP.isMatch()) 8502 return MCTargetAsmParser::Match_Success; 8503 break; 8504 } 8505 // 'MVEPairVectorIndex2' class 8506 case MCK_MVEPairVectorIndex2: { 8507 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<2, 3>()); 8508 if (DP.isMatch()) 8509 return MCTargetAsmParser::Match_Success; 8510 break; 8511 } 8512 // 'ComplexRotationEven' class 8513 case MCK_ComplexRotationEven: { 8514 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>()); 8515 if (DP.isMatch()) 8516 return MCTargetAsmParser::Match_Success; 8517 if (DP.isNearMatch()) 8518 return ARMAsmParser::Match_ComplexRotationEven; 8519 break; 8520 } 8521 // 'ComplexRotationOdd' class 8522 case MCK_ComplexRotationOdd: { 8523 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>()); 8524 if (DP.isMatch()) 8525 return MCTargetAsmParser::Match_Success; 8526 if (DP.isNearMatch()) 8527 return ARMAsmParser::Match_ComplexRotationOdd; 8528 break; 8529 } 8530 // 'NEONi16vmovi8Replicate' class 8531 case MCK_NEONi16vmovi8Replicate: { 8532 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>()); 8533 if (DP.isMatch()) 8534 return MCTargetAsmParser::Match_Success; 8535 break; 8536 } 8537 // 'NEONi16invi8Replicate' class 8538 case MCK_NEONi16invi8Replicate: { 8539 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>()); 8540 if (DP.isMatch()) 8541 return MCTargetAsmParser::Match_Success; 8542 break; 8543 } 8544 // 'NEONi32vmovi8Replicate' class 8545 case MCK_NEONi32vmovi8Replicate: { 8546 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>()); 8547 if (DP.isMatch()) 8548 return MCTargetAsmParser::Match_Success; 8549 break; 8550 } 8551 // 'NEONi32invi8Replicate' class 8552 case MCK_NEONi32invi8Replicate: { 8553 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>()); 8554 if (DP.isMatch()) 8555 return MCTargetAsmParser::Match_Success; 8556 break; 8557 } 8558 // 'NEONi64vmovi8Replicate' class 8559 case MCK_NEONi64vmovi8Replicate: { 8560 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>()); 8561 if (DP.isMatch()) 8562 return MCTargetAsmParser::Match_Success; 8563 break; 8564 } 8565 // 'NEONi64invi8Replicate' class 8566 case MCK_NEONi64invi8Replicate: { 8567 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>()); 8568 if (DP.isMatch()) 8569 return MCTargetAsmParser::Match_Success; 8570 break; 8571 } 8572 // 'NEONi32vmovi16Replicate' class 8573 case MCK_NEONi32vmovi16Replicate: { 8574 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>()); 8575 if (DP.isMatch()) 8576 return MCTargetAsmParser::Match_Success; 8577 break; 8578 } 8579 // 'NEONi64vmovi16Replicate' class 8580 case MCK_NEONi64vmovi16Replicate: { 8581 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>()); 8582 if (DP.isMatch()) 8583 return MCTargetAsmParser::Match_Success; 8584 break; 8585 } 8586 // 'NEONi64vmovi32Replicate' class 8587 case MCK_NEONi64vmovi32Replicate: { 8588 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>()); 8589 if (DP.isMatch()) 8590 return MCTargetAsmParser::Match_Success; 8591 break; 8592 } 8593 // 'ExpandImm0' class 8594 case MCK_ExpandImm0: { 8595 DiagnosticPredicate DP(Operand.isExpImm<0>()); 8596 if (DP.isMatch()) 8597 return MCTargetAsmParser::Match_Success; 8598 break; 8599 } 8600 // 'ExpandImm8' class 8601 case MCK_ExpandImm8: { 8602 DiagnosticPredicate DP(Operand.isExpImm<8>()); 8603 if (DP.isMatch()) 8604 return MCTargetAsmParser::Match_Success; 8605 break; 8606 } 8607 // 'ExpandImm16' class 8608 case MCK_ExpandImm16: { 8609 DiagnosticPredicate DP(Operand.isExpImm<16>()); 8610 if (DP.isMatch()) 8611 return MCTargetAsmParser::Match_Success; 8612 break; 8613 } 8614 // 'ExpandImm24' class 8615 case MCK_ExpandImm24: { 8616 DiagnosticPredicate DP(Operand.isExpImm<24>()); 8617 if (DP.isMatch()) 8618 return MCTargetAsmParser::Match_Success; 8619 break; 8620 } 8621 // 'InvertedExpandImm0_16' class 8622 case MCK_InvertedExpandImm0_16: { 8623 DiagnosticPredicate DP(Operand.isInvertedExpImm<0,16>()); 8624 if (DP.isMatch()) 8625 return MCTargetAsmParser::Match_Success; 8626 break; 8627 } 8628 // 'InvertedExpandImm8_16' class 8629 case MCK_InvertedExpandImm8_16: { 8630 DiagnosticPredicate DP(Operand.isInvertedExpImm<8,16>()); 8631 if (DP.isMatch()) 8632 return MCTargetAsmParser::Match_Success; 8633 break; 8634 } 8635 // 'InvertedExpandImm0_32' class 8636 case MCK_InvertedExpandImm0_32: { 8637 DiagnosticPredicate DP(Operand.isInvertedExpImm<0,32>()); 8638 if (DP.isMatch()) 8639 return MCTargetAsmParser::Match_Success; 8640 break; 8641 } 8642 // 'InvertedExpandImm8_32' class 8643 case MCK_InvertedExpandImm8_32: { 8644 DiagnosticPredicate DP(Operand.isInvertedExpImm<8,32>()); 8645 if (DP.isMatch()) 8646 return MCTargetAsmParser::Match_Success; 8647 break; 8648 } 8649 // 'InvertedExpandImm16_32' class 8650 case MCK_InvertedExpandImm16_32: { 8651 DiagnosticPredicate DP(Operand.isInvertedExpImm<16,32>()); 8652 if (DP.isMatch()) 8653 return MCTargetAsmParser::Match_Success; 8654 break; 8655 } 8656 // 'InvertedExpandImm24_32' class 8657 case MCK_InvertedExpandImm24_32: { 8658 DiagnosticPredicate DP(Operand.isInvertedExpImm<24,32>()); 8659 if (DP.isMatch()) 8660 return MCTargetAsmParser::Match_Success; 8661 break; 8662 } 8663 // 'MVEVectorIndex4' class 8664 case MCK_MVEVectorIndex4: { 8665 DiagnosticPredicate DP(Operand.isVectorIndexInRange<4>()); 8666 if (DP.isMatch()) 8667 return MCTargetAsmParser::Match_Success; 8668 break; 8669 } 8670 // 'MVEVectorIndex8' class 8671 case MCK_MVEVectorIndex8: { 8672 DiagnosticPredicate DP(Operand.isVectorIndexInRange<8>()); 8673 if (DP.isMatch()) 8674 return MCTargetAsmParser::Match_Success; 8675 break; 8676 } 8677 // 'MVEVectorIndex16' class 8678 case MCK_MVEVectorIndex16: { 8679 DiagnosticPredicate DP(Operand.isVectorIndexInRange<16>()); 8680 if (DP.isMatch()) 8681 return MCTargetAsmParser::Match_Success; 8682 break; 8683 } 8684 // 'MVEVcvtImm32' class 8685 case MCK_MVEVcvtImm32: { 8686 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 8687 if (DP.isMatch()) 8688 return MCTargetAsmParser::Match_Success; 8689 if (DP.isNearMatch()) 8690 return ARMAsmParser::Match_MVEVcvtImm32; 8691 break; 8692 } 8693 // 'MVEVcvtImm16' class 8694 case MCK_MVEVcvtImm16: { 8695 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 8696 if (DP.isMatch()) 8697 return MCTargetAsmParser::Match_Success; 8698 if (DP.isNearMatch()) 8699 return ARMAsmParser::Match_MVEVcvtImm16; 8700 break; 8701 } 8702 // 'TMemImm7Shift0Offset' class 8703 case MCK_TMemImm7Shift0Offset: { 8704 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::tGPRRegClassID>()); 8705 if (DP.isMatch()) 8706 return MCTargetAsmParser::Match_Success; 8707 break; 8708 } 8709 // 'TMemImm7Shift1Offset' class 8710 case MCK_TMemImm7Shift1Offset: { 8711 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::tGPRRegClassID>()); 8712 if (DP.isMatch()) 8713 return MCTargetAsmParser::Match_Success; 8714 break; 8715 } 8716 // 'ConstPoolAsmImm' class 8717 case MCK_ConstPoolAsmImm: { 8718 DiagnosticPredicate DP(Operand.isConstPoolAsmImm()); 8719 if (DP.isMatch()) 8720 return MCTargetAsmParser::Match_Success; 8721 break; 8722 } 8723 // 'FBits16' class 8724 case MCK_FBits16: { 8725 DiagnosticPredicate DP(Operand.isFBits16()); 8726 if (DP.isMatch()) 8727 return MCTargetAsmParser::Match_Success; 8728 break; 8729 } 8730 // 'FBits32' class 8731 case MCK_FBits32: { 8732 DiagnosticPredicate DP(Operand.isFBits32()); 8733 if (DP.isMatch()) 8734 return MCTargetAsmParser::Match_Success; 8735 break; 8736 } 8737 // 'Imm0_4095' class 8738 case MCK_Imm0_4095: { 8739 DiagnosticPredicate DP(Operand.isImmediate<0,4095>()); 8740 if (DP.isMatch()) 8741 return MCTargetAsmParser::Match_Success; 8742 if (DP.isNearMatch()) 8743 return ARMAsmParser::Match_Imm0_4095; 8744 break; 8745 } 8746 // 'Imm0_4095Neg' class 8747 case MCK_Imm0_4095Neg: { 8748 DiagnosticPredicate DP(Operand.isImm0_4095Neg()); 8749 if (DP.isMatch()) 8750 return MCTargetAsmParser::Match_Success; 8751 break; 8752 } 8753 // 'ITMask' class 8754 case MCK_ITMask: { 8755 DiagnosticPredicate DP(Operand.isITMask()); 8756 if (DP.isMatch()) 8757 return MCTargetAsmParser::Match_Success; 8758 break; 8759 } 8760 // 'ITCondCode' class 8761 case MCK_ITCondCode: { 8762 DiagnosticPredicate DP(Operand.isITCondCode()); 8763 if (DP.isMatch()) 8764 return MCTargetAsmParser::Match_Success; 8765 break; 8766 } 8767 // 'LELabel' class 8768 case MCK_LELabel: { 8769 DiagnosticPredicate DP(Operand.isLEOffset()); 8770 if (DP.isMatch()) 8771 return MCTargetAsmParser::Match_Success; 8772 if (DP.isNearMatch()) 8773 return ARMAsmParser::Match_LELabel; 8774 break; 8775 } 8776 // 'MVELongShift' class 8777 case MCK_MVELongShift: { 8778 DiagnosticPredicate DP(Operand.isMVELongShift()); 8779 if (DP.isMatch()) 8780 return MCTargetAsmParser::Match_Success; 8781 if (DP.isNearMatch()) 8782 return ARMAsmParser::Match_MVELongShift; 8783 break; 8784 } 8785 // 'NEONi16splat' class 8786 case MCK_NEONi16splat: { 8787 DiagnosticPredicate DP(Operand.isNEONi16splat()); 8788 if (DP.isMatch()) 8789 return MCTargetAsmParser::Match_Success; 8790 break; 8791 } 8792 // 'NEONi32splat' class 8793 case MCK_NEONi32splat: { 8794 DiagnosticPredicate DP(Operand.isNEONi32splat()); 8795 if (DP.isMatch()) 8796 return MCTargetAsmParser::Match_Success; 8797 break; 8798 } 8799 // 'NEONi64splat' class 8800 case MCK_NEONi64splat: { 8801 DiagnosticPredicate DP(Operand.isNEONi64splat()); 8802 if (DP.isMatch()) 8803 return MCTargetAsmParser::Match_Success; 8804 break; 8805 } 8806 // 'NEONi8splat' class 8807 case MCK_NEONi8splat: { 8808 DiagnosticPredicate DP(Operand.isNEONi8splat()); 8809 if (DP.isMatch()) 8810 return MCTargetAsmParser::Match_Success; 8811 break; 8812 } 8813 // 'NEONi16splatNot' class 8814 case MCK_NEONi16splatNot: { 8815 DiagnosticPredicate DP(Operand.isNEONi16splatNot()); 8816 if (DP.isMatch()) 8817 return MCTargetAsmParser::Match_Success; 8818 break; 8819 } 8820 // 'NEONi32splatNot' class 8821 case MCK_NEONi32splatNot: { 8822 DiagnosticPredicate DP(Operand.isNEONi32splatNot()); 8823 if (DP.isMatch()) 8824 return MCTargetAsmParser::Match_Success; 8825 break; 8826 } 8827 // 'NEONi32vmov' class 8828 case MCK_NEONi32vmov: { 8829 DiagnosticPredicate DP(Operand.isNEONi32vmov()); 8830 if (DP.isMatch()) 8831 return MCTargetAsmParser::Match_Success; 8832 break; 8833 } 8834 // 'NEONi32vmovNeg' class 8835 case MCK_NEONi32vmovNeg: { 8836 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg()); 8837 if (DP.isMatch()) 8838 return MCTargetAsmParser::Match_Success; 8839 break; 8840 } 8841 // 'CondCodeNoAL' class 8842 case MCK_CondCodeNoAL: { 8843 DiagnosticPredicate DP(Operand.isITCondCodeNoAL()); 8844 if (DP.isMatch()) 8845 return MCTargetAsmParser::Match_Success; 8846 break; 8847 } 8848 // 'CondCodeNoALInv' class 8849 case MCK_CondCodeNoALInv: { 8850 DiagnosticPredicate DP(Operand.isITCondCodeNoAL()); 8851 if (DP.isMatch()) 8852 return MCTargetAsmParser::Match_Success; 8853 break; 8854 } 8855 // 'CondCodeRestrictedFP' class 8856 case MCK_CondCodeRestrictedFP: { 8857 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedFP()); 8858 if (DP.isMatch()) 8859 return MCTargetAsmParser::Match_Success; 8860 if (DP.isNearMatch()) 8861 return ARMAsmParser::Match_CondCodeRestrictedFP; 8862 break; 8863 } 8864 // 'CondCodeRestrictedI' class 8865 case MCK_CondCodeRestrictedI: { 8866 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedI()); 8867 if (DP.isMatch()) 8868 return MCTargetAsmParser::Match_Success; 8869 if (DP.isNearMatch()) 8870 return ARMAsmParser::Match_CondCodeRestrictedI; 8871 break; 8872 } 8873 // 'CondCodeRestrictedS' class 8874 case MCK_CondCodeRestrictedS: { 8875 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedS()); 8876 if (DP.isMatch()) 8877 return MCTargetAsmParser::Match_Success; 8878 if (DP.isNearMatch()) 8879 return ARMAsmParser::Match_CondCodeRestrictedS; 8880 break; 8881 } 8882 // 'CondCodeRestrictedU' class 8883 case MCK_CondCodeRestrictedU: { 8884 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedU()); 8885 if (DP.isMatch()) 8886 return MCTargetAsmParser::Match_Success; 8887 if (DP.isNearMatch()) 8888 return ARMAsmParser::Match_CondCodeRestrictedU; 8889 break; 8890 } 8891 // 'ShrImm16' class 8892 case MCK_ShrImm16: { 8893 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 8894 if (DP.isMatch()) 8895 return MCTargetAsmParser::Match_Success; 8896 if (DP.isNearMatch()) 8897 return ARMAsmParser::Match_ShrImm16; 8898 break; 8899 } 8900 // 'ShrImm32' class 8901 case MCK_ShrImm32: { 8902 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 8903 if (DP.isMatch()) 8904 return MCTargetAsmParser::Match_Success; 8905 if (DP.isNearMatch()) 8906 return ARMAsmParser::Match_ShrImm32; 8907 break; 8908 } 8909 // 'ShrImm64' class 8910 case MCK_ShrImm64: { 8911 DiagnosticPredicate DP(Operand.isImmediate<1,64>()); 8912 if (DP.isMatch()) 8913 return MCTargetAsmParser::Match_Success; 8914 if (DP.isNearMatch()) 8915 return ARMAsmParser::Match_ShrImm64; 8916 break; 8917 } 8918 // 'ShrImm8' class 8919 case MCK_ShrImm8: { 8920 DiagnosticPredicate DP(Operand.isImmediate<1,8>()); 8921 if (DP.isMatch()) 8922 return MCTargetAsmParser::Match_Success; 8923 if (DP.isNearMatch()) 8924 return ARMAsmParser::Match_ShrImm8; 8925 break; 8926 } 8927 // 'T2SOImm' class 8928 case MCK_T2SOImm: { 8929 DiagnosticPredicate DP(Operand.isT2SOImm()); 8930 if (DP.isMatch()) 8931 return MCTargetAsmParser::Match_Success; 8932 break; 8933 } 8934 // 'T2SOImmNeg' class 8935 case MCK_T2SOImmNeg: { 8936 DiagnosticPredicate DP(Operand.isT2SOImmNeg()); 8937 if (DP.isMatch()) 8938 return MCTargetAsmParser::Match_Success; 8939 break; 8940 } 8941 // 'T2SOImmNot' class 8942 case MCK_T2SOImmNot: { 8943 DiagnosticPredicate DP(Operand.isT2SOImmNot()); 8944 if (DP.isMatch()) 8945 return MCTargetAsmParser::Match_Success; 8946 break; 8947 } 8948 // 'MemUImm12Offset' class 8949 case MCK_MemUImm12Offset: { 8950 DiagnosticPredicate DP(Operand.isMemUImm12Offset()); 8951 if (DP.isMatch()) 8952 return MCTargetAsmParser::Match_Success; 8953 break; 8954 } 8955 // 'T2MemRegOffset' class 8956 case MCK_T2MemRegOffset: { 8957 DiagnosticPredicate DP(Operand.isT2MemRegOffset()); 8958 if (DP.isMatch()) 8959 return MCTargetAsmParser::Match_Success; 8960 break; 8961 } 8962 // 'Imm7s4' class 8963 case MCK_Imm7s4: { 8964 DiagnosticPredicate DP(Operand.isImm7s4()); 8965 if (DP.isMatch()) 8966 return MCTargetAsmParser::Match_Success; 8967 break; 8968 } 8969 // 'Imm7Shift0' class 8970 case MCK_Imm7Shift0: { 8971 DiagnosticPredicate DP(Operand.isImm7Shift0()); 8972 if (DP.isMatch()) 8973 return MCTargetAsmParser::Match_Success; 8974 break; 8975 } 8976 // 'Imm7Shift1' class 8977 case MCK_Imm7Shift1: { 8978 DiagnosticPredicate DP(Operand.isImm7Shift1()); 8979 if (DP.isMatch()) 8980 return MCTargetAsmParser::Match_Success; 8981 break; 8982 } 8983 // 'Imm7Shift2' class 8984 case MCK_Imm7Shift2: { 8985 DiagnosticPredicate DP(Operand.isImm7Shift2()); 8986 if (DP.isMatch()) 8987 return MCTargetAsmParser::Match_Success; 8988 break; 8989 } 8990 // 'Imm8s4' class 8991 case MCK_Imm8s4: { 8992 DiagnosticPredicate DP(Operand.isImm8s4()); 8993 if (DP.isMatch()) 8994 return MCTargetAsmParser::Match_Success; 8995 break; 8996 } 8997 // 'MemPCRelImm12' class 8998 case MCK_MemPCRelImm12: { 8999 DiagnosticPredicate DP(Operand.isMemPCRelImm12()); 9000 if (DP.isMatch()) 9001 return MCTargetAsmParser::Match_Success; 9002 break; 9003 } 9004 // 'MemThumbRIs1' class 9005 case MCK_MemThumbRIs1: { 9006 DiagnosticPredicate DP(Operand.isMemThumbRIs1()); 9007 if (DP.isMatch()) 9008 return MCTargetAsmParser::Match_Success; 9009 break; 9010 } 9011 // 'MemThumbRIs2' class 9012 case MCK_MemThumbRIs2: { 9013 DiagnosticPredicate DP(Operand.isMemThumbRIs2()); 9014 if (DP.isMatch()) 9015 return MCTargetAsmParser::Match_Success; 9016 break; 9017 } 9018 // 'MemThumbRIs4' class 9019 case MCK_MemThumbRIs4: { 9020 DiagnosticPredicate DP(Operand.isMemThumbRIs4()); 9021 if (DP.isMatch()) 9022 return MCTargetAsmParser::Match_Success; 9023 break; 9024 } 9025 // 'MemThumbRR' class 9026 case MCK_MemThumbRR: { 9027 DiagnosticPredicate DP(Operand.isMemThumbRR()); 9028 if (DP.isMatch()) 9029 return MCTargetAsmParser::Match_Success; 9030 break; 9031 } 9032 // 'MemThumbSPI' class 9033 case MCK_MemThumbSPI: { 9034 DiagnosticPredicate DP(Operand.isMemThumbSPI()); 9035 if (DP.isMatch()) 9036 return MCTargetAsmParser::Match_Success; 9037 break; 9038 } 9039 // 'Imm0_1020s4' class 9040 case MCK_Imm0_1020s4: { 9041 DiagnosticPredicate DP(Operand.isImm0_1020s4()); 9042 if (DP.isMatch()) 9043 return MCTargetAsmParser::Match_Success; 9044 break; 9045 } 9046 // 'Imm0_508s4' class 9047 case MCK_Imm0_508s4: { 9048 DiagnosticPredicate DP(Operand.isImm0_508s4()); 9049 if (DP.isMatch()) 9050 return MCTargetAsmParser::Match_Success; 9051 break; 9052 } 9053 // 'Imm0_508s4Neg' class 9054 case MCK_Imm0_508s4Neg: { 9055 DiagnosticPredicate DP(Operand.isImm0_508s4Neg()); 9056 if (DP.isMatch()) 9057 return MCTargetAsmParser::Match_Success; 9058 break; 9059 } 9060 // 'WLSLabel' class 9061 case MCK_WLSLabel: { 9062 DiagnosticPredicate DP(Operand.isUnsignedOffset<11, 1>()); 9063 if (DP.isMatch()) 9064 return MCTargetAsmParser::Match_Success; 9065 if (DP.isNearMatch()) 9066 return ARMAsmParser::Match_WLSLabel; 9067 break; 9068 } 9069 } // end switch (Kind) 9070 9071 if (Operand.isReg()) { 9072 MatchClassKind OpKind; 9073 switch (Operand.getReg()) { 9074 default: OpKind = InvalidMatchClass; break; 9075 case ARM::R0: OpKind = MCK_Reg11; break; 9076 case ARM::R1: OpKind = MCK_Reg15; break; 9077 case ARM::R2: OpKind = MCK_Reg11; break; 9078 case ARM::R3: OpKind = MCK_Reg15; break; 9079 case ARM::R4: OpKind = MCK_Reg12; break; 9080 case ARM::R5: OpKind = MCK_Reg16; break; 9081 case ARM::R6: OpKind = MCK_Reg12; break; 9082 case ARM::R7: OpKind = MCK_Reg16; break; 9083 case ARM::R8: OpKind = MCK_Reg21; break; 9084 case ARM::R9: OpKind = MCK_Reg22; break; 9085 case ARM::R10: OpKind = MCK_Reg21; break; 9086 case ARM::R11: OpKind = MCK_Reg22; break; 9087 case ARM::R12: OpKind = MCK_Reg23; break; 9088 case ARM::SP: OpKind = MCK_GPRsp; break; 9089 case ARM::LR: OpKind = MCK_GPRlr; break; 9090 case ARM::PC: OpKind = MCK_PC; break; 9091 case ARM::S0: OpKind = MCK_SPR_8; break; 9092 case ARM::S1: OpKind = MCK_SPR_8; break; 9093 case ARM::S2: OpKind = MCK_SPR_8; break; 9094 case ARM::S3: OpKind = MCK_SPR_8; break; 9095 case ARM::S4: OpKind = MCK_SPR_8; break; 9096 case ARM::S5: OpKind = MCK_SPR_8; break; 9097 case ARM::S6: OpKind = MCK_SPR_8; break; 9098 case ARM::S7: OpKind = MCK_SPR_8; break; 9099 case ARM::S8: OpKind = MCK_SPR_8; break; 9100 case ARM::S9: OpKind = MCK_SPR_8; break; 9101 case ARM::S10: OpKind = MCK_SPR_8; break; 9102 case ARM::S11: OpKind = MCK_SPR_8; break; 9103 case ARM::S12: OpKind = MCK_SPR_8; break; 9104 case ARM::S13: OpKind = MCK_SPR_8; break; 9105 case ARM::S14: OpKind = MCK_SPR_8; break; 9106 case ARM::S15: OpKind = MCK_SPR_8; break; 9107 case ARM::S16: OpKind = MCK_HPR; break; 9108 case ARM::S17: OpKind = MCK_HPR; break; 9109 case ARM::S18: OpKind = MCK_HPR; break; 9110 case ARM::S19: OpKind = MCK_HPR; break; 9111 case ARM::S20: OpKind = MCK_HPR; break; 9112 case ARM::S21: OpKind = MCK_HPR; break; 9113 case ARM::S22: OpKind = MCK_HPR; break; 9114 case ARM::S23: OpKind = MCK_HPR; break; 9115 case ARM::S24: OpKind = MCK_HPR; break; 9116 case ARM::S25: OpKind = MCK_HPR; break; 9117 case ARM::S26: OpKind = MCK_HPR; break; 9118 case ARM::S27: OpKind = MCK_HPR; break; 9119 case ARM::S28: OpKind = MCK_HPR; break; 9120 case ARM::S29: OpKind = MCK_HPR; break; 9121 case ARM::S30: OpKind = MCK_HPR; break; 9122 case ARM::S31: OpKind = MCK_HPR; break; 9123 case ARM::D0: OpKind = MCK_DPR_8; break; 9124 case ARM::D1: OpKind = MCK_DPR_8; break; 9125 case ARM::D2: OpKind = MCK_DPR_8; break; 9126 case ARM::D3: OpKind = MCK_DPR_8; break; 9127 case ARM::D4: OpKind = MCK_DPR_8; break; 9128 case ARM::D5: OpKind = MCK_DPR_8; break; 9129 case ARM::D6: OpKind = MCK_DPR_8; break; 9130 case ARM::D7: OpKind = MCK_DPR_8; break; 9131 case ARM::D8: OpKind = MCK_DPR_VFP2; break; 9132 case ARM::D9: OpKind = MCK_DPR_VFP2; break; 9133 case ARM::D10: OpKind = MCK_DPR_VFP2; break; 9134 case ARM::D11: OpKind = MCK_DPR_VFP2; break; 9135 case ARM::D12: OpKind = MCK_DPR_VFP2; break; 9136 case ARM::D13: OpKind = MCK_DPR_VFP2; break; 9137 case ARM::D14: OpKind = MCK_DPR_VFP2; break; 9138 case ARM::D15: OpKind = MCK_DPR_VFP2; break; 9139 case ARM::D16: OpKind = MCK_DPR; break; 9140 case ARM::D17: OpKind = MCK_DPR; break; 9141 case ARM::D18: OpKind = MCK_DPR; break; 9142 case ARM::D19: OpKind = MCK_DPR; break; 9143 case ARM::D20: OpKind = MCK_DPR; break; 9144 case ARM::D21: OpKind = MCK_DPR; break; 9145 case ARM::D22: OpKind = MCK_DPR; break; 9146 case ARM::D23: OpKind = MCK_DPR; break; 9147 case ARM::D24: OpKind = MCK_DPR; break; 9148 case ARM::D25: OpKind = MCK_DPR; break; 9149 case ARM::D26: OpKind = MCK_DPR; break; 9150 case ARM::D27: OpKind = MCK_DPR; break; 9151 case ARM::D28: OpKind = MCK_DPR; break; 9152 case ARM::D29: OpKind = MCK_DPR; break; 9153 case ARM::D30: OpKind = MCK_DPR; break; 9154 case ARM::D31: OpKind = MCK_DPR; break; 9155 case ARM::Q0: OpKind = MCK_QPR_8; break; 9156 case ARM::Q1: OpKind = MCK_QPR_8; break; 9157 case ARM::Q2: OpKind = MCK_QPR_8; break; 9158 case ARM::Q3: OpKind = MCK_QPR_8; break; 9159 case ARM::Q4: OpKind = MCK_MQPR; break; 9160 case ARM::Q5: OpKind = MCK_MQPR; break; 9161 case ARM::Q6: OpKind = MCK_MQPR; break; 9162 case ARM::Q7: OpKind = MCK_MQPR; break; 9163 case ARM::Q8: OpKind = MCK_QPR; break; 9164 case ARM::Q9: OpKind = MCK_QPR; break; 9165 case ARM::Q10: OpKind = MCK_QPR; break; 9166 case ARM::Q11: OpKind = MCK_QPR; break; 9167 case ARM::Q12: OpKind = MCK_QPR; break; 9168 case ARM::Q13: OpKind = MCK_QPR; break; 9169 case ARM::Q14: OpKind = MCK_QPR; break; 9170 case ARM::Q15: OpKind = MCK_QPR; break; 9171 case ARM::CPSR: OpKind = MCK_CCR; break; 9172 case ARM::APSR: OpKind = MCK_APSR; break; 9173 case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break; 9174 case ARM::SPSR: OpKind = MCK_SPSR; break; 9175 case ARM::FPSCR: OpKind = MCK_FPSCR; break; 9176 case ARM::FPSCR_NZCV: OpKind = MCK_cl_FPSCR_NZCV; break; 9177 case ARM::FPSID: OpKind = MCK_FPSID; break; 9178 case ARM::MVFR2: OpKind = MCK_MVFR2; break; 9179 case ARM::MVFR1: OpKind = MCK_MVFR1; break; 9180 case ARM::MVFR0: OpKind = MCK_MVFR0; break; 9181 case ARM::FPEXC: OpKind = MCK_FPEXC; break; 9182 case ARM::FPINST: OpKind = MCK_FPINST; break; 9183 case ARM::FPINST2: OpKind = MCK_FPINST2; break; 9184 case ARM::VPR: OpKind = MCK_VCCR; break; 9185 case ARM::FPSCR_NZCVQC: OpKind = MCK_FPSCR_NZCVQC; break; 9186 case ARM::P0: OpKind = MCK_P0; break; 9187 case ARM::FPCXTNS: OpKind = MCK_FPCXTNS; break; 9188 case ARM::FPCXTS: OpKind = MCK_FPCXTS; break; 9189 case ARM::ZR: OpKind = MCK_GPRwithZRnosp; break; 9190 case ARM::D0_D2: OpKind = MCK_Reg59; break; 9191 case ARM::D1_D3: OpKind = MCK_Reg59; break; 9192 case ARM::D2_D4: OpKind = MCK_Reg59; break; 9193 case ARM::D3_D5: OpKind = MCK_Reg59; break; 9194 case ARM::D4_D6: OpKind = MCK_Reg59; break; 9195 case ARM::D5_D7: OpKind = MCK_Reg59; break; 9196 case ARM::D6_D8: OpKind = MCK_Reg60; break; 9197 case ARM::D7_D9: OpKind = MCK_Reg60; break; 9198 case ARM::D8_D10: OpKind = MCK_Reg61; break; 9199 case ARM::D9_D11: OpKind = MCK_Reg61; break; 9200 case ARM::D10_D12: OpKind = MCK_Reg61; break; 9201 case ARM::D11_D13: OpKind = MCK_Reg61; break; 9202 case ARM::D12_D14: OpKind = MCK_Reg61; break; 9203 case ARM::D13_D15: OpKind = MCK_Reg61; break; 9204 case ARM::D14_D16: OpKind = MCK_Reg62; break; 9205 case ARM::D15_D17: OpKind = MCK_Reg62; break; 9206 case ARM::D16_D18: OpKind = MCK_DPairSpc; break; 9207 case ARM::D17_D19: OpKind = MCK_DPairSpc; break; 9208 case ARM::D18_D20: OpKind = MCK_DPairSpc; break; 9209 case ARM::D19_D21: OpKind = MCK_DPairSpc; break; 9210 case ARM::D20_D22: OpKind = MCK_DPairSpc; break; 9211 case ARM::D21_D23: OpKind = MCK_DPairSpc; break; 9212 case ARM::D22_D24: OpKind = MCK_DPairSpc; break; 9213 case ARM::D23_D25: OpKind = MCK_DPairSpc; break; 9214 case ARM::D24_D26: OpKind = MCK_DPairSpc; break; 9215 case ARM::D25_D27: OpKind = MCK_DPairSpc; break; 9216 case ARM::D26_D28: OpKind = MCK_DPairSpc; break; 9217 case ARM::D27_D29: OpKind = MCK_DPairSpc; break; 9218 case ARM::D28_D30: OpKind = MCK_DPairSpc; break; 9219 case ARM::D29_D31: OpKind = MCK_DPairSpc; break; 9220 case ARM::Q0_Q1: OpKind = MCK_Reg64; break; 9221 case ARM::Q1_Q2: OpKind = MCK_Reg64; break; 9222 case ARM::Q2_Q3: OpKind = MCK_Reg64; break; 9223 case ARM::Q3_Q4: OpKind = MCK_Reg65; break; 9224 case ARM::Q4_Q5: OpKind = MCK_Reg66; break; 9225 case ARM::Q5_Q6: OpKind = MCK_Reg66; break; 9226 case ARM::Q6_Q7: OpKind = MCK_Reg66; break; 9227 case ARM::Q7_Q8: OpKind = MCK_Reg67; break; 9228 case ARM::Q8_Q9: OpKind = MCK_QQPR; break; 9229 case ARM::Q9_Q10: OpKind = MCK_QQPR; break; 9230 case ARM::Q10_Q11: OpKind = MCK_QQPR; break; 9231 case ARM::Q11_Q12: OpKind = MCK_QQPR; break; 9232 case ARM::Q12_Q13: OpKind = MCK_QQPR; break; 9233 case ARM::Q13_Q14: OpKind = MCK_QQPR; break; 9234 case ARM::Q14_Q15: OpKind = MCK_QQPR; break; 9235 case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg78; break; 9236 case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg79; break; 9237 case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg80; break; 9238 case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg81; break; 9239 case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg82; break; 9240 case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg83; break; 9241 case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg84; break; 9242 case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg85; break; 9243 case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break; 9244 case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break; 9245 case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break; 9246 case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break; 9247 case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break; 9248 case ARM::R0_R1: OpKind = MCK_Reg87; break; 9249 case ARM::R2_R3: OpKind = MCK_Reg87; break; 9250 case ARM::R4_R5: OpKind = MCK_Reg88; break; 9251 case ARM::R6_R7: OpKind = MCK_Reg88; break; 9252 case ARM::R8_R9: OpKind = MCK_Reg92; break; 9253 case ARM::R10_R11: OpKind = MCK_Reg92; break; 9254 case ARM::R12_SP: OpKind = MCK_Reg94; break; 9255 case ARM::D0_D1_D2: OpKind = MCK_Reg102; break; 9256 case ARM::D1_D2_D3: OpKind = MCK_Reg107; break; 9257 case ARM::D2_D3_D4: OpKind = MCK_Reg102; break; 9258 case ARM::D3_D4_D5: OpKind = MCK_Reg107; break; 9259 case ARM::D4_D5_D6: OpKind = MCK_Reg102; break; 9260 case ARM::D5_D6_D7: OpKind = MCK_Reg107; break; 9261 case ARM::D6_D7_D8: OpKind = MCK_Reg103; break; 9262 case ARM::D7_D8_D9: OpKind = MCK_Reg108; break; 9263 case ARM::D8_D9_D10: OpKind = MCK_Reg104; break; 9264 case ARM::D9_D10_D11: OpKind = MCK_Reg109; break; 9265 case ARM::D10_D11_D12: OpKind = MCK_Reg104; break; 9266 case ARM::D11_D12_D13: OpKind = MCK_Reg109; break; 9267 case ARM::D12_D13_D14: OpKind = MCK_Reg104; break; 9268 case ARM::D13_D14_D15: OpKind = MCK_Reg109; break; 9269 case ARM::D14_D15_D16: OpKind = MCK_Reg105; break; 9270 case ARM::D15_D16_D17: OpKind = MCK_Reg110; break; 9271 case ARM::D16_D17_D18: OpKind = MCK_Reg106; break; 9272 case ARM::D17_D18_D19: OpKind = MCK_Reg111; break; 9273 case ARM::D18_D19_D20: OpKind = MCK_Reg106; break; 9274 case ARM::D19_D20_D21: OpKind = MCK_Reg111; break; 9275 case ARM::D20_D21_D22: OpKind = MCK_Reg106; break; 9276 case ARM::D21_D22_D23: OpKind = MCK_Reg111; break; 9277 case ARM::D22_D23_D24: OpKind = MCK_Reg106; break; 9278 case ARM::D23_D24_D25: OpKind = MCK_Reg111; break; 9279 case ARM::D24_D25_D26: OpKind = MCK_Reg106; break; 9280 case ARM::D25_D26_D27: OpKind = MCK_Reg111; break; 9281 case ARM::D26_D27_D28: OpKind = MCK_Reg106; break; 9282 case ARM::D27_D28_D29: OpKind = MCK_Reg111; break; 9283 case ARM::D28_D29_D30: OpKind = MCK_Reg106; break; 9284 case ARM::D29_D30_D31: OpKind = MCK_Reg111; break; 9285 case ARM::D0_D2_D4: OpKind = MCK_Reg112; break; 9286 case ARM::D1_D3_D5: OpKind = MCK_Reg112; break; 9287 case ARM::D2_D4_D6: OpKind = MCK_Reg112; break; 9288 case ARM::D3_D5_D7: OpKind = MCK_Reg112; break; 9289 case ARM::D4_D6_D8: OpKind = MCK_Reg113; break; 9290 case ARM::D5_D7_D9: OpKind = MCK_Reg113; break; 9291 case ARM::D6_D8_D10: OpKind = MCK_Reg114; break; 9292 case ARM::D7_D9_D11: OpKind = MCK_Reg114; break; 9293 case ARM::D8_D10_D12: OpKind = MCK_Reg115; break; 9294 case ARM::D9_D11_D13: OpKind = MCK_Reg115; break; 9295 case ARM::D10_D12_D14: OpKind = MCK_Reg115; break; 9296 case ARM::D11_D13_D15: OpKind = MCK_Reg115; break; 9297 case ARM::D12_D14_D16: OpKind = MCK_Reg116; break; 9298 case ARM::D13_D15_D17: OpKind = MCK_Reg116; break; 9299 case ARM::D14_D16_D18: OpKind = MCK_Reg117; break; 9300 case ARM::D15_D17_D19: OpKind = MCK_Reg117; break; 9301 case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break; 9302 case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break; 9303 case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break; 9304 case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break; 9305 case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break; 9306 case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break; 9307 case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break; 9308 case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break; 9309 case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break; 9310 case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break; 9311 case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break; 9312 case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break; 9313 case ARM::D1_D2: OpKind = MCK_Reg39; break; 9314 case ARM::D3_D4: OpKind = MCK_Reg39; break; 9315 case ARM::D5_D6: OpKind = MCK_Reg39; break; 9316 case ARM::D7_D8: OpKind = MCK_Reg40; break; 9317 case ARM::D9_D10: OpKind = MCK_Reg37; break; 9318 case ARM::D11_D12: OpKind = MCK_Reg37; break; 9319 case ARM::D13_D14: OpKind = MCK_Reg37; break; 9320 case ARM::D15_D16: OpKind = MCK_Reg38; break; 9321 case ARM::D17_D18: OpKind = MCK_DPair; break; 9322 case ARM::D19_D20: OpKind = MCK_DPair; break; 9323 case ARM::D21_D22: OpKind = MCK_DPair; break; 9324 case ARM::D23_D24: OpKind = MCK_DPair; break; 9325 case ARM::D25_D26: OpKind = MCK_DPair; break; 9326 case ARM::D27_D28: OpKind = MCK_DPair; break; 9327 case ARM::D29_D30: OpKind = MCK_DPair; break; 9328 case ARM::D1_D2_D3_D4: OpKind = MCK_Reg119; break; 9329 case ARM::D3_D4_D5_D6: OpKind = MCK_Reg119; break; 9330 case ARM::D5_D6_D7_D8: OpKind = MCK_Reg120; break; 9331 case ARM::D7_D8_D9_D10: OpKind = MCK_Reg121; break; 9332 case ARM::D9_D10_D11_D12: OpKind = MCK_Reg122; break; 9333 case ARM::D11_D12_D13_D14: OpKind = MCK_Reg122; break; 9334 case ARM::D13_D14_D15_D16: OpKind = MCK_Reg123; break; 9335 case ARM::D15_D16_D17_D18: OpKind = MCK_Reg124; break; 9336 case ARM::D17_D18_D19_D20: OpKind = MCK_Reg125; break; 9337 case ARM::D19_D20_D21_D22: OpKind = MCK_Reg125; break; 9338 case ARM::D21_D22_D23_D24: OpKind = MCK_Reg125; break; 9339 case ARM::D23_D24_D25_D26: OpKind = MCK_Reg125; break; 9340 case ARM::D25_D26_D27_D28: OpKind = MCK_Reg125; break; 9341 case ARM::D27_D28_D29_D30: OpKind = MCK_Reg125; break; 9342 } 9343 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 9344 getDiagKindFromRegisterClass(Kind); 9345 } 9346 9347 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 9348 return getDiagKindFromRegisterClass(Kind); 9349 9350 return MCTargetAsmParser::Match_InvalidOperand; 9351} 9352 9353#ifndef NDEBUG 9354const char *getMatchClassName(MatchClassKind Kind) { 9355 switch (Kind) { 9356 case InvalidMatchClass: return "InvalidMatchClass"; 9357 case OptionalMatchClass: return "OptionalMatchClass"; 9358 case MCK__DOT_d: return "MCK__DOT_d"; 9359 case MCK__DOT_f: return "MCK__DOT_f"; 9360 case MCK__DOT_s16: return "MCK__DOT_s16"; 9361 case MCK__DOT_s32: return "MCK__DOT_s32"; 9362 case MCK__DOT_s64: return "MCK__DOT_s64"; 9363 case MCK__DOT_s8: return "MCK__DOT_s8"; 9364 case MCK__DOT_u16: return "MCK__DOT_u16"; 9365 case MCK__DOT_u32: return "MCK__DOT_u32"; 9366 case MCK__DOT_u64: return "MCK__DOT_u64"; 9367 case MCK__DOT_u8: return "MCK__DOT_u8"; 9368 case MCK__DOT_f32: return "MCK__DOT_f32"; 9369 case MCK__DOT_f64: return "MCK__DOT_f64"; 9370 case MCK__DOT_i16: return "MCK__DOT_i16"; 9371 case MCK__DOT_i32: return "MCK__DOT_i32"; 9372 case MCK__DOT_i64: return "MCK__DOT_i64"; 9373 case MCK__DOT_i8: return "MCK__DOT_i8"; 9374 case MCK__DOT_p16: return "MCK__DOT_p16"; 9375 case MCK__DOT_p8: return "MCK__DOT_p8"; 9376 case MCK__EXCLAIM_: return "MCK__EXCLAIM_"; 9377 case MCK__HASH_0: return "MCK__HASH_0"; 9378 case MCK__HASH_16: return "MCK__HASH_16"; 9379 case MCK__HASH_8: return "MCK__HASH_8"; 9380 case MCK__DOT_16: return "MCK__DOT_16"; 9381 case MCK__DOT_32: return "MCK__DOT_32"; 9382 case MCK__DOT_64: return "MCK__DOT_64"; 9383 case MCK__DOT_8: return "MCK__DOT_8"; 9384 case MCK__DOT_f16: return "MCK__DOT_f16"; 9385 case MCK__DOT_p64: return "MCK__DOT_p64"; 9386 case MCK__DOT_w: return "MCK__DOT_w"; 9387 case MCK__91_: return "MCK__91_"; 9388 case MCK__93_: return "MCK__93_"; 9389 case MCK__94_: return "MCK__94_"; 9390 case MCK__123_: return "MCK__123_"; 9391 case MCK__125_: return "MCK__125_"; 9392 case MCK_Reg94: return "MCK_Reg94"; 9393 case MCK_Reg78: return "MCK_Reg78"; 9394 case MCK_Reg23: return "MCK_Reg23"; 9395 case MCK_APSR: return "MCK_APSR"; 9396 case MCK_APSR_NZCV: return "MCK_APSR_NZCV"; 9397 case MCK_CCR: return "MCK_CCR"; 9398 case MCK_FPCXTNS: return "MCK_FPCXTNS"; 9399 case MCK_FPCXTS: return "MCK_FPCXTS"; 9400 case MCK_FPEXC: return "MCK_FPEXC"; 9401 case MCK_FPINST: return "MCK_FPINST"; 9402 case MCK_FPINST2: return "MCK_FPINST2"; 9403 case MCK_FPSCR: return "MCK_FPSCR"; 9404 case MCK_FPSCR_NZCVQC: return "MCK_FPSCR_NZCVQC"; 9405 case MCK_FPSID: return "MCK_FPSID"; 9406 case MCK_GPRlr: return "MCK_GPRlr"; 9407 case MCK_GPRsp: return "MCK_GPRsp"; 9408 case MCK_MVFR0: return "MCK_MVFR0"; 9409 case MCK_MVFR1: return "MCK_MVFR1"; 9410 case MCK_MVFR2: return "MCK_MVFR2"; 9411 case MCK_P0: return "MCK_P0"; 9412 case MCK_PC: return "MCK_PC"; 9413 case MCK_SPSR: return "MCK_SPSR"; 9414 case MCK_VCCR: return "MCK_VCCR"; 9415 case MCK_cl_FPSCR_NZCV: return "MCK_cl_FPSCR_NZCV"; 9416 case MCK_Reg119: return "MCK_Reg119"; 9417 case MCK_Reg92: return "MCK_Reg92"; 9418 case MCK_Reg87: return "MCK_Reg87"; 9419 case MCK_Reg79: return "MCK_Reg79"; 9420 case MCK_Reg22: return "MCK_Reg22"; 9421 case MCK_Reg15: return "MCK_Reg15"; 9422 case MCK_Reg11: return "MCK_Reg11"; 9423 case MCK_Reg120: return "MCK_Reg120"; 9424 case MCK_Reg107: return "MCK_Reg107"; 9425 case MCK_Reg102: return "MCK_Reg102"; 9426 case MCK_Reg93: return "MCK_Reg93"; 9427 case MCK_Reg91: return "MCK_Reg91"; 9428 case MCK_Reg80: return "MCK_Reg80"; 9429 case MCK_Reg64: return "MCK_Reg64"; 9430 case MCK_Reg14: return "MCK_Reg14"; 9431 case MCK_Reg121: return "MCK_Reg121"; 9432 case MCK_Reg112: return "MCK_Reg112"; 9433 case MCK_Reg108: return "MCK_Reg108"; 9434 case MCK_Reg103: return "MCK_Reg103"; 9435 case MCK_Reg88: return "MCK_Reg88"; 9436 case MCK_Reg81: return "MCK_Reg81"; 9437 case MCK_Reg65: return "MCK_Reg65"; 9438 case MCK_Reg21: return "MCK_Reg21"; 9439 case MCK_Reg16: return "MCK_Reg16"; 9440 case MCK_Reg12: return "MCK_Reg12"; 9441 case MCK_Reg0: return "MCK_Reg0"; 9442 case MCK_QPR_8: return "MCK_QPR_8"; 9443 case MCK_Reg82: return "MCK_Reg82"; 9444 case MCK_Reg76: return "MCK_Reg76"; 9445 case MCK_tcGPR: return "MCK_tcGPR"; 9446 case MCK_Reg122: return "MCK_Reg122"; 9447 case MCK_Reg113: return "MCK_Reg113"; 9448 case MCK_Reg95: return "MCK_Reg95"; 9449 case MCK_Reg83: return "MCK_Reg83"; 9450 case MCK_Reg77: return "MCK_Reg77"; 9451 case MCK_Reg59: return "MCK_Reg59"; 9452 case MCK_Reg20: return "MCK_Reg20"; 9453 case MCK_GPRPairnosp: return "MCK_GPRPairnosp"; 9454 case MCK_tGPROdd: return "MCK_tGPROdd"; 9455 case MCK_Reg123: return "MCK_Reg123"; 9456 case MCK_Reg109: return "MCK_Reg109"; 9457 case MCK_Reg104: return "MCK_Reg104"; 9458 case MCK_Reg96: return "MCK_Reg96"; 9459 case MCK_Reg84: return "MCK_Reg84"; 9460 case MCK_Reg74: return "MCK_Reg74"; 9461 case MCK_Reg66: return "MCK_Reg66"; 9462 case MCK_Reg39: return "MCK_Reg39"; 9463 case MCK_Reg18: return "MCK_Reg18"; 9464 case MCK_GPRPair: return "MCK_GPRPair"; 9465 case MCK_Reg124: return "MCK_Reg124"; 9466 case MCK_Reg114: return "MCK_Reg114"; 9467 case MCK_Reg110: return "MCK_Reg110"; 9468 case MCK_Reg105: return "MCK_Reg105"; 9469 case MCK_Reg97: return "MCK_Reg97"; 9470 case MCK_Reg85: return "MCK_Reg85"; 9471 case MCK_Reg75: return "MCK_Reg75"; 9472 case MCK_Reg67: return "MCK_Reg67"; 9473 case MCK_Reg60: return "MCK_Reg60"; 9474 case MCK_Reg40: return "MCK_Reg40"; 9475 case MCK_DPR_8: return "MCK_DPR_8"; 9476 case MCK_MQPR: return "MCK_MQPR"; 9477 case MCK_hGPR: return "MCK_hGPR"; 9478 case MCK_tGPR: return "MCK_tGPR"; 9479 case MCK_tGPREven: return "MCK_tGPREven"; 9480 case MCK_tGPRwithpc: return "MCK_tGPRwithpc"; 9481 case MCK_Reg115: return "MCK_Reg115"; 9482 case MCK_Reg72: return "MCK_Reg72"; 9483 case MCK_QQQQPR: return "MCK_QQQQPR"; 9484 case MCK_Reg125: return "MCK_Reg125"; 9485 case MCK_Reg116: return "MCK_Reg116"; 9486 case MCK_Reg98: return "MCK_Reg98"; 9487 case MCK_Reg73: return "MCK_Reg73"; 9488 case MCK_Reg61: return "MCK_Reg61"; 9489 case MCK_rGPR: return "MCK_rGPR"; 9490 case MCK_Reg111: return "MCK_Reg111"; 9491 case MCK_Reg106: return "MCK_Reg106"; 9492 case MCK_Reg99: return "MCK_Reg99"; 9493 case MCK_Reg70: return "MCK_Reg70"; 9494 case MCK_Reg37: return "MCK_Reg37"; 9495 case MCK_GPRnopc: return "MCK_GPRnopc"; 9496 case MCK_GPRwithAPSRnosp: return "MCK_GPRwithAPSRnosp"; 9497 case MCK_GPRwithZRnosp: return "MCK_GPRwithZRnosp"; 9498 case MCK_QQPR: return "MCK_QQPR"; 9499 case MCK_Reg117: return "MCK_Reg117"; 9500 case MCK_Reg100: return "MCK_Reg100"; 9501 case MCK_Reg71: return "MCK_Reg71"; 9502 case MCK_Reg62: return "MCK_Reg62"; 9503 case MCK_Reg38: return "MCK_Reg38"; 9504 case MCK_DPR_VFP2: return "MCK_DPR_VFP2"; 9505 case MCK_GPR: return "MCK_GPR"; 9506 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR"; 9507 case MCK_GPRwithZR: return "MCK_GPRwithZR"; 9508 case MCK_QPR: return "MCK_QPR"; 9509 case MCK_SPR_8: return "MCK_SPR_8"; 9510 case MCK_DTripleSpc: return "MCK_DTripleSpc"; 9511 case MCK_DQuad: return "MCK_DQuad"; 9512 case MCK_DPairSpc: return "MCK_DPairSpc"; 9513 case MCK_DTriple: return "MCK_DTriple"; 9514 case MCK_DPair: return "MCK_DPair"; 9515 case MCK_DPR: return "MCK_DPR"; 9516 case MCK_HPR: return "MCK_HPR"; 9517 case MCK_FPWithVPR: return "MCK_FPWithVPR"; 9518 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm"; 9519 case MCK_AM3Offset: return "MCK_AM3Offset"; 9520 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget"; 9521 case MCK_AddrMode3: return "MCK_AddrMode3"; 9522 case MCK_AddrMode5: return "MCK_AddrMode5"; 9523 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16"; 9524 case MCK_AlignedMemory16: return "MCK_AlignedMemory16"; 9525 case MCK_AlignedMemory32: return "MCK_AlignedMemory32"; 9526 case MCK_AlignedMemory64: return "MCK_AlignedMemory64"; 9527 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128"; 9528 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256"; 9529 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone"; 9530 case MCK_AlignedMemory: return "MCK_AlignedMemory"; 9531 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16"; 9532 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32"; 9533 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64"; 9534 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128"; 9535 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone"; 9536 case MCK_AdrLabel: return "MCK_AdrLabel"; 9537 case MCK_BankedReg: return "MCK_BankedReg"; 9538 case MCK_Bitfield: return "MCK_Bitfield"; 9539 case MCK_CCOut: return "MCK_CCOut"; 9540 case MCK_CondCode: return "MCK_CondCode"; 9541 case MCK_CoprocNum: return "MCK_CoprocNum"; 9542 case MCK_CoprocOption: return "MCK_CoprocOption"; 9543 case MCK_CoprocReg: return "MCK_CoprocReg"; 9544 case MCK_DPRRegList: return "MCK_DPRRegList"; 9545 case MCK_FPDRegListWithVPR: return "MCK_FPDRegListWithVPR"; 9546 case MCK_FPImm: return "MCK_FPImm"; 9547 case MCK_FPSRegListWithVPR: return "MCK_FPSRegListWithVPR"; 9548 case MCK_Imm0_15: return "MCK_Imm0_15"; 9549 case MCK_Imm0_1: return "MCK_Imm0_1"; 9550 case MCK_Imm0_239: return "MCK_Imm0_239"; 9551 case MCK_Imm0_255: return "MCK_Imm0_255"; 9552 case MCK_Imm0_31: return "MCK_Imm0_31"; 9553 case MCK_Imm0_32: return "MCK_Imm0_32"; 9554 case MCK_Imm0_3: return "MCK_Imm0_3"; 9555 case MCK_Imm0_63: return "MCK_Imm0_63"; 9556 case MCK_Imm0_65535: return "MCK_Imm0_65535"; 9557 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr"; 9558 case MCK_Imm0_7: return "MCK_Imm0_7"; 9559 case MCK_Imm16: return "MCK_Imm16"; 9560 case MCK_Imm1_15: return "MCK_Imm1_15"; 9561 case MCK_Imm1_16: return "MCK_Imm1_16"; 9562 case MCK_Imm1_31: return "MCK_Imm1_31"; 9563 case MCK_Imm1_32: return "MCK_Imm1_32"; 9564 case MCK_Imm1_7: return "MCK_Imm1_7"; 9565 case MCK_Imm24bit: return "MCK_Imm24bit"; 9566 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr"; 9567 case MCK_Imm32: return "MCK_Imm32"; 9568 case MCK_Imm8: return "MCK_Imm8"; 9569 case MCK_Imm8_255: return "MCK_Imm8_255"; 9570 case MCK_Imm: return "MCK_Imm"; 9571 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt"; 9572 case MCK_MSRMask: return "MCK_MSRMask"; 9573 case MCK_MVEShiftImm1_15: return "MCK_MVEShiftImm1_15"; 9574 case MCK_MVEShiftImm1_7: return "MCK_MVEShiftImm1_7"; 9575 case MCK_VIDUP_imm: return "MCK_VIDUP_imm"; 9576 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt"; 9577 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset"; 9578 case MCK_MemImm12Offset: return "MCK_MemImm12Offset"; 9579 case MCK_MemImm7Shift0Offset: return "MCK_MemImm7Shift0Offset"; 9580 case MCK_MemImm7Shift0OffsetWB: return "MCK_MemImm7Shift0OffsetWB"; 9581 case MCK_MemImm7Shift1Offset: return "MCK_MemImm7Shift1Offset"; 9582 case MCK_MemImm7Shift1OffsetWB: return "MCK_MemImm7Shift1OffsetWB"; 9583 case MCK_MemImm7Shift2Offset: return "MCK_MemImm7Shift2Offset"; 9584 case MCK_MemImm7Shift2OffsetWB: return "MCK_MemImm7Shift2OffsetWB"; 9585 case MCK_MemImm7s4Offset: return "MCK_MemImm7s4Offset"; 9586 case MCK_MemImm8Offset: return "MCK_MemImm8Offset"; 9587 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset"; 9588 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset"; 9589 case MCK_MemNoOffset: return "MCK_MemNoOffset"; 9590 case MCK_MemNoOffsetT2: return "MCK_MemNoOffsetT2"; 9591 case MCK_MemNoOffsetT2NoSp: return "MCK_MemNoOffsetT2NoSp"; 9592 case MCK_MemNoOffsetT: return "MCK_MemNoOffsetT"; 9593 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset"; 9594 case MCK_MemRegOffset: return "MCK_MemRegOffset"; 9595 case MCK_MemRegQS2Offset: return "MCK_MemRegQS2Offset"; 9596 case MCK_MemRegQS3Offset: return "MCK_MemRegQS3Offset"; 9597 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset"; 9598 case MCK_MemRegRQS1Offset: return "MCK_MemRegRQS1Offset"; 9599 case MCK_MemRegRQS2Offset: return "MCK_MemRegRQS2Offset"; 9600 case MCK_MemRegRQS3Offset: return "MCK_MemRegRQS3Offset"; 9601 case MCK_ModImm: return "MCK_ModImm"; 9602 case MCK_ModImmNeg: return "MCK_ModImmNeg"; 9603 case MCK_ModImmNot: return "MCK_ModImmNot"; 9604 case MCK_MveSaturate: return "MCK_MveSaturate"; 9605 case MCK_PKHASRImm: return "MCK_PKHASRImm"; 9606 case MCK_PKHLSLImm: return "MCK_PKHLSLImm"; 9607 case MCK_PostIdxImm8: return "MCK_PostIdxImm8"; 9608 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4"; 9609 case MCK_PostIdxReg: return "MCK_PostIdxReg"; 9610 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted"; 9611 case MCK_ProcIFlags: return "MCK_ProcIFlags"; 9612 case MCK_RegList: return "MCK_RegList"; 9613 case MCK_RegListWithAPSR: return "MCK_RegListWithAPSR"; 9614 case MCK_RotImm: return "MCK_RotImm"; 9615 case MCK_SPRRegList: return "MCK_SPRRegList"; 9616 case MCK_SetEndImm: return "MCK_SetEndImm"; 9617 case MCK_RegShiftedImm: return "MCK_RegShiftedImm"; 9618 case MCK_RegShiftedReg: return "MCK_RegShiftedReg"; 9619 case MCK_ShifterImm: return "MCK_ShifterImm"; 9620 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget"; 9621 case MCK_ThumbMemPC: return "MCK_ThumbMemPC"; 9622 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7"; 9623 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255"; 9624 case MCK_ImmThumbSR: return "MCK_ImmThumbSR"; 9625 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt"; 9626 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2"; 9627 case MCK_VPTPredN: return "MCK_VPTPredN"; 9628 case MCK_VPTPredR: return "MCK_VPTPredR"; 9629 case MCK_VecListTwoMQ: return "MCK_VecListTwoMQ"; 9630 case MCK_VecListFourMQ: return "MCK_VecListFourMQ"; 9631 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes"; 9632 case MCK_VecListDPair: return "MCK_VecListDPair"; 9633 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes"; 9634 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced"; 9635 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes"; 9636 case MCK_VecListFourD: return "MCK_VecListFourD"; 9637 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed"; 9638 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed"; 9639 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed"; 9640 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes"; 9641 case MCK_VecListFourQ: return "MCK_VecListFourQ"; 9642 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed"; 9643 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed"; 9644 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes"; 9645 case MCK_VecListOneD: return "MCK_VecListOneD"; 9646 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed"; 9647 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed"; 9648 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed"; 9649 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes"; 9650 case MCK_VecListThreeD: return "MCK_VecListThreeD"; 9651 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed"; 9652 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed"; 9653 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed"; 9654 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes"; 9655 case MCK_VecListThreeQ: return "MCK_VecListThreeQ"; 9656 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed"; 9657 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed"; 9658 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed"; 9659 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed"; 9660 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed"; 9661 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed"; 9662 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed"; 9663 case MCK_VectorIndex16: return "MCK_VectorIndex16"; 9664 case MCK_VectorIndex32: return "MCK_VectorIndex32"; 9665 case MCK_VectorIndex64: return "MCK_VectorIndex64"; 9666 case MCK_VectorIndex8: return "MCK_VectorIndex8"; 9667 case MCK_MemTBB: return "MCK_MemTBB"; 9668 case MCK_MemTBH: return "MCK_MemTBH"; 9669 case MCK_MVEPairVectorIndex0: return "MCK_MVEPairVectorIndex0"; 9670 case MCK_MVEPairVectorIndex2: return "MCK_MVEPairVectorIndex2"; 9671 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven"; 9672 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd"; 9673 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate"; 9674 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate"; 9675 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate"; 9676 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate"; 9677 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate"; 9678 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate"; 9679 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate"; 9680 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate"; 9681 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate"; 9682 case MCK_ExpandImm0: return "MCK_ExpandImm0"; 9683 case MCK_ExpandImm8: return "MCK_ExpandImm8"; 9684 case MCK_ExpandImm16: return "MCK_ExpandImm16"; 9685 case MCK_ExpandImm24: return "MCK_ExpandImm24"; 9686 case MCK_InvertedExpandImm0_16: return "MCK_InvertedExpandImm0_16"; 9687 case MCK_InvertedExpandImm8_16: return "MCK_InvertedExpandImm8_16"; 9688 case MCK_InvertedExpandImm0_32: return "MCK_InvertedExpandImm0_32"; 9689 case MCK_InvertedExpandImm8_32: return "MCK_InvertedExpandImm8_32"; 9690 case MCK_InvertedExpandImm16_32: return "MCK_InvertedExpandImm16_32"; 9691 case MCK_InvertedExpandImm24_32: return "MCK_InvertedExpandImm24_32"; 9692 case MCK_MVEVectorIndex4: return "MCK_MVEVectorIndex4"; 9693 case MCK_MVEVectorIndex8: return "MCK_MVEVectorIndex8"; 9694 case MCK_MVEVectorIndex16: return "MCK_MVEVectorIndex16"; 9695 case MCK_MVEVcvtImm32: return "MCK_MVEVcvtImm32"; 9696 case MCK_MVEVcvtImm16: return "MCK_MVEVcvtImm16"; 9697 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset"; 9698 case MCK_TMemImm7Shift1Offset: return "MCK_TMemImm7Shift1Offset"; 9699 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm"; 9700 case MCK_FBits16: return "MCK_FBits16"; 9701 case MCK_FBits32: return "MCK_FBits32"; 9702 case MCK_Imm0_4095: return "MCK_Imm0_4095"; 9703 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg"; 9704 case MCK_ITMask: return "MCK_ITMask"; 9705 case MCK_ITCondCode: return "MCK_ITCondCode"; 9706 case MCK_LELabel: return "MCK_LELabel"; 9707 case MCK_MVELongShift: return "MCK_MVELongShift"; 9708 case MCK_NEONi16splat: return "MCK_NEONi16splat"; 9709 case MCK_NEONi32splat: return "MCK_NEONi32splat"; 9710 case MCK_NEONi64splat: return "MCK_NEONi64splat"; 9711 case MCK_NEONi8splat: return "MCK_NEONi8splat"; 9712 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot"; 9713 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot"; 9714 case MCK_NEONi32vmov: return "MCK_NEONi32vmov"; 9715 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg"; 9716 case MCK_CondCodeNoAL: return "MCK_CondCodeNoAL"; 9717 case MCK_CondCodeNoALInv: return "MCK_CondCodeNoALInv"; 9718 case MCK_CondCodeRestrictedFP: return "MCK_CondCodeRestrictedFP"; 9719 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI"; 9720 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS"; 9721 case MCK_CondCodeRestrictedU: return "MCK_CondCodeRestrictedU"; 9722 case MCK_ShrImm16: return "MCK_ShrImm16"; 9723 case MCK_ShrImm32: return "MCK_ShrImm32"; 9724 case MCK_ShrImm64: return "MCK_ShrImm64"; 9725 case MCK_ShrImm8: return "MCK_ShrImm8"; 9726 case MCK_T2SOImm: return "MCK_T2SOImm"; 9727 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg"; 9728 case MCK_T2SOImmNot: return "MCK_T2SOImmNot"; 9729 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset"; 9730 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset"; 9731 case MCK_Imm7s4: return "MCK_Imm7s4"; 9732 case MCK_Imm7Shift0: return "MCK_Imm7Shift0"; 9733 case MCK_Imm7Shift1: return "MCK_Imm7Shift1"; 9734 case MCK_Imm7Shift2: return "MCK_Imm7Shift2"; 9735 case MCK_Imm8s4: return "MCK_Imm8s4"; 9736 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12"; 9737 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1"; 9738 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2"; 9739 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4"; 9740 case MCK_MemThumbRR: return "MCK_MemThumbRR"; 9741 case MCK_MemThumbSPI: return "MCK_MemThumbSPI"; 9742 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4"; 9743 case MCK_Imm0_508s4: return "MCK_Imm0_508s4"; 9744 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg"; 9745 case MCK_WLSLabel: return "MCK_WLSLabel"; 9746 case NumMatchClassKinds: return "NumMatchClassKinds"; 9747 } 9748 llvm_unreachable("unhandled MatchClassKind!"); 9749} 9750 9751#endif // NDEBUG 9752FeatureBitset ARMAsmParser:: 9753ComputeAvailableFeatures(const FeatureBitset& FB) const { 9754 FeatureBitset Features; 9755 if ((FB[ARM::HasV4TOps])) 9756 Features.set(Feature_HasV4TBit); 9757 if ((FB[ARM::HasV5TOps])) 9758 Features.set(Feature_HasV5TBit); 9759 if ((FB[ARM::HasV5TEOps])) 9760 Features.set(Feature_HasV5TEBit); 9761 if ((FB[ARM::HasV6Ops])) 9762 Features.set(Feature_HasV6Bit); 9763 if ((FB[ARM::HasV6MOps])) 9764 Features.set(Feature_HasV6MBit); 9765 if ((FB[ARM::HasV8MBaselineOps])) 9766 Features.set(Feature_HasV8MBaselineBit); 9767 if ((FB[ARM::HasV8MMainlineOps])) 9768 Features.set(Feature_HasV8MMainlineBit); 9769 if ((FB[ARM::HasV8_1MMainlineOps])) 9770 Features.set(Feature_HasV8_1MMainlineBit); 9771 if ((FB[ARM::HasMVEIntegerOps])) 9772 Features.set(Feature_HasMVEIntBit); 9773 if ((FB[ARM::HasMVEFloatOps])) 9774 Features.set(Feature_HasMVEFloatBit); 9775 if ((FB[ARM::FeatureFPRegs])) 9776 Features.set(Feature_HasFPRegsBit); 9777 if ((FB[ARM::FeatureFPRegs16])) 9778 Features.set(Feature_HasFPRegs16Bit); 9779 if ((FB[ARM::FeatureFPRegs64])) 9780 Features.set(Feature_HasFPRegs64Bit); 9781 if ((FB[ARM::FeatureFPRegs]) && (FB[ARM::HasV8_1MMainlineOps])) 9782 Features.set(Feature_HasFPRegsV8_1MBit); 9783 if ((FB[ARM::HasV6T2Ops])) 9784 Features.set(Feature_HasV6T2Bit); 9785 if ((FB[ARM::HasV6KOps])) 9786 Features.set(Feature_HasV6KBit); 9787 if ((FB[ARM::HasV7Ops])) 9788 Features.set(Feature_HasV7Bit); 9789 if ((FB[ARM::HasV8Ops])) 9790 Features.set(Feature_HasV8Bit); 9791 if ((!FB[ARM::HasV8Ops])) 9792 Features.set(Feature_PreV8Bit); 9793 if ((FB[ARM::HasV8_1aOps])) 9794 Features.set(Feature_HasV8_1aBit); 9795 if ((FB[ARM::HasV8_2aOps])) 9796 Features.set(Feature_HasV8_2aBit); 9797 if ((FB[ARM::HasV8_3aOps])) 9798 Features.set(Feature_HasV8_3aBit); 9799 if ((FB[ARM::HasV8_4aOps])) 9800 Features.set(Feature_HasV8_4aBit); 9801 if ((FB[ARM::HasV8_5aOps])) 9802 Features.set(Feature_HasV8_5aBit); 9803 if ((FB[ARM::FeatureVFP2_SP])) 9804 Features.set(Feature_HasVFP2Bit); 9805 if ((FB[ARM::FeatureVFP3_D16_SP])) 9806 Features.set(Feature_HasVFP3Bit); 9807 if ((FB[ARM::FeatureVFP4_D16_SP])) 9808 Features.set(Feature_HasVFP4Bit); 9809 if ((FB[ARM::FeatureFP64])) 9810 Features.set(Feature_HasDPVFPBit); 9811 if ((FB[ARM::FeatureFPARMv8_D16_SP])) 9812 Features.set(Feature_HasFPARMv8Bit); 9813 if ((FB[ARM::FeatureNEON])) 9814 Features.set(Feature_HasNEONBit); 9815 if ((FB[ARM::FeatureSHA2])) 9816 Features.set(Feature_HasSHA2Bit); 9817 if ((FB[ARM::FeatureAES])) 9818 Features.set(Feature_HasAESBit); 9819 if ((FB[ARM::FeatureCrypto])) 9820 Features.set(Feature_HasCryptoBit); 9821 if ((FB[ARM::FeatureDotProd])) 9822 Features.set(Feature_HasDotProdBit); 9823 if ((FB[ARM::FeatureCRC])) 9824 Features.set(Feature_HasCRCBit); 9825 if ((FB[ARM::FeatureRAS])) 9826 Features.set(Feature_HasRASBit); 9827 if ((FB[ARM::FeatureLOB])) 9828 Features.set(Feature_HasLOBBit); 9829 if ((FB[ARM::FeatureFP16])) 9830 Features.set(Feature_HasFP16Bit); 9831 if ((FB[ARM::FeatureFullFP16])) 9832 Features.set(Feature_HasFullFP16Bit); 9833 if ((FB[ARM::FeatureFP16FML])) 9834 Features.set(Feature_HasFP16FMLBit); 9835 if ((FB[ARM::FeatureHWDivThumb])) 9836 Features.set(Feature_HasDivideInThumbBit); 9837 if ((FB[ARM::FeatureHWDivARM])) 9838 Features.set(Feature_HasDivideInARMBit); 9839 if ((FB[ARM::FeatureDSP])) 9840 Features.set(Feature_HasDSPBit); 9841 if ((FB[ARM::FeatureDB])) 9842 Features.set(Feature_HasDBBit); 9843 if ((FB[ARM::FeatureDFB])) 9844 Features.set(Feature_HasDFBBit); 9845 if ((FB[ARM::FeatureV7Clrex])) 9846 Features.set(Feature_HasV7ClrexBit); 9847 if ((FB[ARM::FeatureAcquireRelease])) 9848 Features.set(Feature_HasAcquireReleaseBit); 9849 if ((FB[ARM::FeatureMP])) 9850 Features.set(Feature_HasMPBit); 9851 if ((FB[ARM::FeatureVirtualization])) 9852 Features.set(Feature_HasVirtualizationBit); 9853 if ((FB[ARM::FeatureTrustZone])) 9854 Features.set(Feature_HasTrustZoneBit); 9855 if ((FB[ARM::Feature8MSecExt])) 9856 Features.set(Feature_Has8MSecExtBit); 9857 if ((FB[ARM::ModeThumb])) 9858 Features.set(Feature_IsThumbBit); 9859 if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2])) 9860 Features.set(Feature_IsThumb2Bit); 9861 if ((FB[ARM::FeatureMClass])) 9862 Features.set(Feature_IsMClassBit); 9863 if ((!FB[ARM::FeatureMClass])) 9864 Features.set(Feature_IsNotMClassBit); 9865 if ((!FB[ARM::ModeThumb])) 9866 Features.set(Feature_IsARMBit); 9867 if ((FB[ARM::FeatureNaClTrap])) 9868 Features.set(Feature_UseNaClTrapBit); 9869 if ((!FB[ARM::FeatureNoNegativeImmediates])) 9870 Features.set(Feature_UseNegativeImmediatesBit); 9871 if ((FB[ARM::FeatureSB])) 9872 Features.set(Feature_HasSBBit); 9873 return Features; 9874} 9875 9876static const char *const MnemonicTable = 9877 "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a" 9878 "esmc\003and\003asr\004asrl\001b\002bf\003bfc\006bfcsel\003bfi\003bfl\004" 9879 "bflx\003bfx\003bic\004bkpt\002bl\003blx\005blxns\002bx\003bxj\004bxns\004" 9880 "cbnz\003cbz\003cdp\004cdp2\004cinc\004cinv\005clrex\004clrm\003clz\003c" 9881 "mn\003cmp\004cneg\003cps\006crc32b\007crc32cb\007crc32ch\007crc32cw\006" 9882 "crc32h\006crc32w\004csdb\004csel\004cset\005csetm\005csinc\005csinv\005" 9883 "csneg\003dbg\005dcps1\005dcps2\005dcps3\003dfb\003dls\005dlstp\003dmb\003" 9884 "dsb\003eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fcon" 9885 "std\007fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fst" 9886 "mdbx\007fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\004" 9887 "lctp\003lda\004ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003l" 9888 "dc\004ldc2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004" 9889 "ldrb\005ldrbt\004ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005" 9890 "ldrht\005ldrsb\006ldrsbt\005ldrsh\006ldrsht\004ldrt\002le\004letp\003ls" 9891 "l\004lsll\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003" 9892 "mov\004movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003mrs\003m" 9893 "sr\003mul\003mvn\003neg\003nop\003orn\003orr\005pkhbt\005pkhtb\003pld\004" 9894 "pldw\003pli\003pop\005pssbb\004push\004qadd\006qadd16\005qadd8\004qasx\005" 9895 "qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004rbit\003rev\005rev" 9896 "16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003ror\003rrx\003rsb\003" 9897 "rsc\006sadd16\005sadd8\004sasx\002sb\003sbc\004sbfx\004sdiv\003sel\006s" 9898 "etend\006setpan\003sev\004sevl\002sg\005sha1c\005sha1h\005sha1m\005sha1" 9899 "p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsha256su0\tsha256su1\007" 9900 "shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003smc\006smla" 9901 "bb\006smlabt\005smlad\006smladx\005smlal\007smlalbb\007smlalbt\006smlal" 9902 "d\007smlaldx\007smlaltb\007smlaltt\006smlatb\006smlatt\006smlawb\006sml" 9903 "awt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smmlar\005smmls" 9904 "\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006smulbt\005" 9905 "smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smusdx\006sqr" 9906 "shr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb\005srshr\006srshrl\005" 9907 "srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb\006ssub16\005ssub8\003" 9908 "stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006stlexb\006stlex" 9909 "d\006stlexh\004stlh\003stm\005stmda\005stmdb\005stmib\003str\004strb\005" 9910 "strbt\004strd\005strex\006strexb\006strexd\006strexh\004strh\005strht\004" 9911 "strt\003sub\004subs\004subw\003svc\003swp\004swpb\005sxtab\007sxtab16\005" 9912 "sxtah\004sxtb\006sxtb16\004sxth\003tbb\003tbh\003teq\004trap\003tsb\003" 9913 "tst\002tt\003tta\004ttat\003ttt\006uadd16\005uadd8\004uasx\004ubfx\003u" 9914 "df\004udiv\007uhadd16\006uhadd8\005uhasx\005uhsax\007uhsub16\006uhsub8\005" 9915 "umaal\005umlal\005umull\007uqadd16\006uqadd8\005uqasx\006uqrshl\007uqrs" 9916 "hll\005uqsax\005uqshl\006uqshll\007uqsub16\006uqsub8\005urshr\006urshrl" 9917 "\005usad8\006usada8\004usat\006usat16\004usax\006usub16\005usub8\005uxt" 9918 "ab\007uxtab16\005uxtah\004uxtb\006uxtb16\004uxth\004vaba\005vabal\005va" 9919 "bav\004vabd\005vabdl\004vabs\005vacge\005vacgt\005vacle\005vaclt\004vad" 9920 "c\005vadci\004vadd\006vaddhn\005vaddl\006vaddlv\007vaddlva\005vaddv\006" 9921 "vaddva\005vaddw\004vand\004vbic\004vbif\004vbit\005vbrsr\004vbsl\005vca" 9922 "dd\004vceq\004vcge\004vcgt\004vcle\004vcls\004vclt\004vclz\005vcmla\004" 9923 "vcmp\005vcmpe\005vcmul\004vcnt\004vctp\004vcvt\005vcvta\005vcvtb\005vcv" 9924 "tm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\005vddup\004vdiv\004vdup\006vdwd" 9925 "up\004veor\004vext\004vfma\005vfmal\005vfmas\004vfms\005vfmsl\005vfnma\005" 9926 "vfnms\005vhadd\006vhcadd\005vhsub\005vidup\004vins\006viwdup\005vjcvt\004" 9927 "vld1\004vld2\005vld20\005vld21\004vld3\004vld4\005vld40\005vld41\005vld" 9928 "42\005vld43\006vldmdb\006vldmia\004vldr\005vldrb\005vldrd\005vldrh\005v" 9929 "ldrw\005vlldm\005vlstm\004vmax\005vmaxa\006vmaxav\006vmaxnm\007vmaxnma\010" 9930 "vmaxnmav\007vmaxnmv\005vmaxv\004vmin\005vmina\006vminav\006vminnm\007vm" 9931 "innma\010vminnmav\007vminnmv\005vminv\004vmla\007vmladav\010vmladava\tv" 9932 "mladavax\010vmladavx\005vmlal\010vmlaldav\tvmlaldava\nvmlaldavax\tvmlal" 9933 "davx\006vmlalv\007vmlalva\005vmlas\005vmlav\006vmlava\004vmls\007vmlsda" 9934 "v\010vmlsdava\tvmlsdavax\010vmlsdavx\005vmlsl\010vmlsldav\tvmlsldava\nv" 9935 "mlsldavax\tvmlsldavx\004vmov\005vmovl\006vmovlb\006vmovlt\005vmovn\006v" 9936 "movnb\006vmovnt\005vmovx\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006v" 9937 "mullb\006vmullt\004vmvn\004vneg\005vnmla\005vnmls\005vnmul\004vorn\004v" 9938 "orr\006vpadal\005vpadd\006vpaddl\005vpmax\005vpmin\005vpnot\004vpop\005" 9939 "vpsel\004vpst\003vpt\005vpush\005vqabs\005vqadd\010vqdmladh\tvqdmladhx\007" 9940 "vqdmlah\007vqdmlal\010vqdmlash\010vqdmlsdh\tvqdmlsdhx\007vqdmlsl\007vqd" 9941 "mulh\007vqdmull\010vqdmullb\010vqdmullt\006vqmovn\007vqmovnb\007vqmovnt" 9942 "\007vqmovun\010vqmovunb\010vqmovunt\005vqneg\tvqrdmladh\nvqrdmladhx\010" 9943 "vqrdmlah\tvqrdmlash\tvqrdmlsdh\nvqrdmlsdhx\010vqrdmlsh\010vqrdmulh\006v" 9944 "qrshl\007vqrshrn\010vqrshrnb\010vqrshrnt\010vqrshrun\tvqrshrunb\tvqrshr" 9945 "unt\005vqshl\006vqshlu\006vqshrn\007vqshrnb\007vqshrnt\007vqshrun\010vq" 9946 "shrunb\010vqshrunt\005vqsub\007vraddhn\006vrecpe\006vrecps\006vrev16\006" 9947 "vrev32\006vrev64\006vrhadd\006vrinta\006vrintm\006vrintn\006vrintp\006v" 9948 "rintr\006vrintx\006vrintz\nvrmlaldavh\013vrmlaldavha\014vrmlaldavhax\013" 9949 "vrmlaldavhx\010vrmlalvh\tvrmlalvha\nvrmlsldavh\013vrmlsldavha\014vrmlsl" 9950 "davhax\013vrmlsldavhx\006vrmulh\005vrshl\005vrshr\006vrshrn\007vrshrnb\007" 9951 "vrshrnt\007vrsqrte\007vrsqrts\005vrsra\007vrsubhn\004vsbc\005vsbci\007v" 9952 "scclrm\005vsdot\006vseleq\006vselge\006vselgt\006vselvs\004vshl\005vshl" 9953 "c\005vshll\006vshllb\006vshllt\004vshr\005vshrn\006vshrnb\006vshrnt\004" 9954 "vsli\005vsqrt\004vsra\004vsri\004vst1\004vst2\005vst20\005vst21\004vst3" 9955 "\004vst4\005vst40\005vst41\005vst42\005vst43\006vstmdb\006vstmia\004vst" 9956 "r\005vstrb\005vstrd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsu" 9957 "bw\004vswp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\004vuzp\004vzip\003" 9958 "wfe\003wfi\003wls\005wlstp\005yield"; 9959 9960// Feature bitsets. 9961enum : uint8_t { 9962 AMFBS_None, 9963 AMFBS_Has8MSecExt, 9964 AMFBS_HasDB, 9965 AMFBS_HasDFB, 9966 AMFBS_HasDotProd, 9967 AMFBS_HasFP16, 9968 AMFBS_HasFPARMv8, 9969 AMFBS_HasFPRegs, 9970 AMFBS_HasFPRegs16, 9971 AMFBS_HasFPRegs64, 9972 AMFBS_HasFPRegsV8_1M, 9973 AMFBS_HasFullFP16, 9974 AMFBS_HasMVEFloat, 9975 AMFBS_HasMVEInt, 9976 AMFBS_HasNEON, 9977 AMFBS_HasV8_1MMainline, 9978 AMFBS_HasVFP2, 9979 AMFBS_HasVFP3, 9980 AMFBS_HasVFP4, 9981 AMFBS_IsARM, 9982 AMFBS_IsThumb, 9983 AMFBS_IsThumb2, 9984 AMFBS_HasDB_IsThumb2, 9985 AMFBS_HasDSP_IsThumb2, 9986 AMFBS_HasFPARMv8_HasDPVFP, 9987 AMFBS_HasFPARMv8_HasV8_3a, 9988 AMFBS_HasFPRegs_HasV8_1MMainline, 9989 AMFBS_HasMVEInt_IsThumb, 9990 AMFBS_HasNEON_HasFP16, 9991 AMFBS_HasNEON_HasFP16FML, 9992 AMFBS_HasNEON_HasFullFP16, 9993 AMFBS_HasNEON_HasV8_1a, 9994 AMFBS_HasNEON_HasV8_3a, 9995 AMFBS_HasNEON_HasVFP4, 9996 AMFBS_HasV8_HasCrypto, 9997 AMFBS_HasV8_HasNEON, 9998 AMFBS_HasV8MMainline_Has8MSecExt, 9999 AMFBS_HasV8_1MMainline_Has8MSecExt, 10000 AMFBS_HasV8_1MMainline_HasFPRegs, 10001 AMFBS_HasV8_1MMainline_HasMVEInt, 10002 AMFBS_HasVFP2_HasDPVFP, 10003 AMFBS_HasVFP3_HasDPVFP, 10004 AMFBS_HasVFP4_HasDPVFP, 10005 AMFBS_IsARM_HasAcquireRelease, 10006 AMFBS_IsARM_HasDB, 10007 AMFBS_IsARM_HasDFB, 10008 AMFBS_IsARM_HasDivideInARM, 10009 AMFBS_IsARM_HasRAS, 10010 AMFBS_IsARM_HasSB, 10011 AMFBS_IsARM_HasTrustZone, 10012 AMFBS_IsARM_HasV4T, 10013 AMFBS_IsARM_HasV5T, 10014 AMFBS_IsARM_HasV5TE, 10015 AMFBS_IsARM_HasV6, 10016 AMFBS_IsARM_HasV6K, 10017 AMFBS_IsARM_HasV6T2, 10018 AMFBS_IsARM_HasV7, 10019 AMFBS_IsARM_HasV8, 10020 AMFBS_IsARM_HasV8_4a, 10021 AMFBS_IsARM_HasVirtualization, 10022 AMFBS_IsARM_PreV8, 10023 AMFBS_IsARM_UseNaClTrap, 10024 AMFBS_IsARM_UseNegativeImmediates, 10025 AMFBS_IsThumb_Has8MSecExt, 10026 AMFBS_IsThumb_HasAcquireRelease, 10027 AMFBS_IsThumb_HasDB, 10028 AMFBS_IsThumb_HasV5T, 10029 AMFBS_IsThumb_HasV6, 10030 AMFBS_IsThumb_HasV6M, 10031 AMFBS_IsThumb_HasV7Clrex, 10032 AMFBS_IsThumb_HasV8, 10033 AMFBS_IsThumb_HasV8MBaseline, 10034 AMFBS_IsThumb_HasV8_4a, 10035 AMFBS_IsThumb_HasVirtualization, 10036 AMFBS_IsThumb_IsMClass, 10037 AMFBS_IsThumb_IsNotMClass, 10038 AMFBS_IsThumb_UseNegativeImmediates, 10039 AMFBS_IsThumb2_HasDSP, 10040 AMFBS_IsThumb2_HasRAS, 10041 AMFBS_IsThumb2_HasSB, 10042 AMFBS_IsThumb2_HasTrustZone, 10043 AMFBS_IsThumb2_HasV7, 10044 AMFBS_IsThumb2_HasV8, 10045 AMFBS_IsThumb2_HasVirtualization, 10046 AMFBS_IsThumb2_IsNotMClass, 10047 AMFBS_IsThumb2_PreV8, 10048 AMFBS_IsThumb2_UseNegativeImmediates, 10049 AMFBS_PreV8_IsThumb2, 10050 AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, 10051 AMFBS_HasNEON_HasV8_3a_HasFullFP16, 10052 AMFBS_HasV8_HasNEON_HasFullFP16, 10053 AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, 10054 AMFBS_IsARM_HasV7_HasMP, 10055 AMFBS_IsARM_HasV8_HasCRC, 10056 AMFBS_IsARM_HasV8_HasV8_1a, 10057 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, 10058 AMFBS_IsThumb_HasV5T_IsNotMClass, 10059 AMFBS_IsThumb2_HasV7_HasMP, 10060 AMFBS_IsThumb2_HasV8_HasCRC, 10061 AMFBS_IsThumb2_HasV8_HasV8_1a, 10062 AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, 10063 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, 10064}; 10065 10066static constexpr FeatureBitset FeatureBitsets[] = { 10067 {}, // AMFBS_None 10068 {Feature_Has8MSecExtBit, }, 10069 {Feature_HasDBBit, }, 10070 {Feature_HasDFBBit, }, 10071 {Feature_HasDotProdBit, }, 10072 {Feature_HasFP16Bit, }, 10073 {Feature_HasFPARMv8Bit, }, 10074 {Feature_HasFPRegsBit, }, 10075 {Feature_HasFPRegs16Bit, }, 10076 {Feature_HasFPRegs64Bit, }, 10077 {Feature_HasFPRegsV8_1MBit, }, 10078 {Feature_HasFullFP16Bit, }, 10079 {Feature_HasMVEFloatBit, }, 10080 {Feature_HasMVEIntBit, }, 10081 {Feature_HasNEONBit, }, 10082 {Feature_HasV8_1MMainlineBit, }, 10083 {Feature_HasVFP2Bit, }, 10084 {Feature_HasVFP3Bit, }, 10085 {Feature_HasVFP4Bit, }, 10086 {Feature_IsARMBit, }, 10087 {Feature_IsThumbBit, }, 10088 {Feature_IsThumb2Bit, }, 10089 {Feature_HasDBBit, Feature_IsThumb2Bit, }, 10090 {Feature_HasDSPBit, Feature_IsThumb2Bit, }, 10091 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, 10092 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, 10093 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, 10094 {Feature_HasMVEIntBit, Feature_IsThumbBit, }, 10095 {Feature_HasNEONBit, Feature_HasFP16Bit, }, 10096 {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, 10097 {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 10098 {Feature_HasNEONBit, Feature_HasV8_1aBit, }, 10099 {Feature_HasNEONBit, Feature_HasV8_3aBit, }, 10100 {Feature_HasNEONBit, Feature_HasVFP4Bit, }, 10101 {Feature_HasV8Bit, Feature_HasCryptoBit, }, 10102 {Feature_HasV8Bit, Feature_HasNEONBit, }, 10103 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, 10104 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, 10105 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, 10106 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, 10107 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, 10108 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, 10109 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, 10110 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, 10111 {Feature_IsARMBit, Feature_HasDBBit, }, 10112 {Feature_IsARMBit, Feature_HasDFBBit, }, 10113 {Feature_IsARMBit, Feature_HasDivideInARMBit, }, 10114 {Feature_IsARMBit, Feature_HasRASBit, }, 10115 {Feature_IsARMBit, Feature_HasSBBit, }, 10116 {Feature_IsARMBit, Feature_HasTrustZoneBit, }, 10117 {Feature_IsARMBit, Feature_HasV4TBit, }, 10118 {Feature_IsARMBit, Feature_HasV5TBit, }, 10119 {Feature_IsARMBit, Feature_HasV5TEBit, }, 10120 {Feature_IsARMBit, Feature_HasV6Bit, }, 10121 {Feature_IsARMBit, Feature_HasV6KBit, }, 10122 {Feature_IsARMBit, Feature_HasV6T2Bit, }, 10123 {Feature_IsARMBit, Feature_HasV7Bit, }, 10124 {Feature_IsARMBit, Feature_HasV8Bit, }, 10125 {Feature_IsARMBit, Feature_HasV8_4aBit, }, 10126 {Feature_IsARMBit, Feature_HasVirtualizationBit, }, 10127 {Feature_IsARMBit, Feature_PreV8Bit, }, 10128 {Feature_IsARMBit, Feature_UseNaClTrapBit, }, 10129 {Feature_IsARMBit, Feature_UseNegativeImmediatesBit, }, 10130 {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, 10131 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, 10132 {Feature_IsThumbBit, Feature_HasDBBit, }, 10133 {Feature_IsThumbBit, Feature_HasV5TBit, }, 10134 {Feature_IsThumbBit, Feature_HasV6Bit, }, 10135 {Feature_IsThumbBit, Feature_HasV6MBit, }, 10136 {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, 10137 {Feature_IsThumbBit, Feature_HasV8Bit, }, 10138 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 10139 {Feature_IsThumbBit, Feature_HasV8_4aBit, }, 10140 {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, 10141 {Feature_IsThumbBit, Feature_IsMClassBit, }, 10142 {Feature_IsThumbBit, Feature_IsNotMClassBit, }, 10143 {Feature_IsThumbBit, Feature_UseNegativeImmediatesBit, }, 10144 {Feature_IsThumb2Bit, Feature_HasDSPBit, }, 10145 {Feature_IsThumb2Bit, Feature_HasRASBit, }, 10146 {Feature_IsThumb2Bit, Feature_HasSBBit, }, 10147 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, 10148 {Feature_IsThumb2Bit, Feature_HasV7Bit, }, 10149 {Feature_IsThumb2Bit, Feature_HasV8Bit, }, 10150 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, 10151 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, 10152 {Feature_IsThumb2Bit, Feature_PreV8Bit, }, 10153 {Feature_IsThumb2Bit, Feature_UseNegativeImmediatesBit, }, 10154 {Feature_PreV8Bit, Feature_IsThumb2Bit, }, 10155 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 10156 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, 10157 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 10158 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 10159 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, 10160 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCRCBit, }, 10161 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 10162 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 10163 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, 10164 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, 10165 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCRCBit, }, 10166 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 10167 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, 10168 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, 10169}; 10170 10171namespace { 10172 struct MatchEntry { 10173 uint16_t Mnemonic; 10174 uint16_t Opcode; 10175 uint16_t ConvertFn; 10176 uint8_t RequiredFeaturesIdx; 10177 uint16_t Classes[18]; 10178 StringRef getMnemonic() const { 10179 return StringRef(MnemonicTable + Mnemonic + 1, 10180 MnemonicTable[Mnemonic]); 10181 } 10182 }; 10183 10184 // Predicate for searching for an opcode. 10185 struct LessOpcode { 10186 bool operator()(const MatchEntry &LHS, StringRef RHS) { 10187 return LHS.getMnemonic() < RHS; 10188 } 10189 bool operator()(StringRef LHS, const MatchEntry &RHS) { 10190 return LHS < RHS.getMnemonic(); 10191 } 10192 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 10193 return LHS.getMnemonic() < RHS.getMnemonic(); 10194 } 10195 }; 10196} // end anonymous namespace 10197 10198static const MatchEntry MatchTable0[] = { 10199 { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, AMFBS_IsThumb, { }, }, 10200 { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10201 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10202 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10203 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10204 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10205 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10206 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10207 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10208 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10209 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10210 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10211 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10212 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10213 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10214 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10215 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10216 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10217 { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, }, 10218 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 10219 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10220 { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 10221 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 10222 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 10223 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10224 { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10225 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, }, 10226 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10227 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10228 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10229 { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 10230 { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 10231 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10232 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10233 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10234 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 10235 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10236 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10237 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10238 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 10239 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10240 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10241 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 10242 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10243 { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 10244 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 10245 { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, }, 10246 { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, }, 10247 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 10248 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 10249 { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, }, 10250 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, }, 10251 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10252 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNeg }, }, 10253 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 10254 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10255 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10256 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 10257 { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 10258 { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 10259 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 10260 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10261 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10262 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 10263 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10264 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10265 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10266 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 10267 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10268 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10269 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 10270 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10271 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10272 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 10273 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10274 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10275 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 10276 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10277 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 10278 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10279 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 10280 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10281 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 10282 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10283 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10284 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 10285 { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, }, 10286 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10287 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, }, 10288 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, }, 10289 { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10290 { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10291 { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10292 { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10293 { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10294 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10295 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10296 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10297 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10298 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10299 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10300 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10301 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10302 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10303 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10304 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10305 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10306 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 10307 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10308 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10309 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10310 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10311 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10312 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10313 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10314 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10315 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10316 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10317 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10318 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10319 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10320 { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10321 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 10322 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10323 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 10324 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10325 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 10326 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10327 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 10328 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 10329 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10330 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10331 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10332 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 10333 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10334 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10335 { 58 /* asrl */, ARM::MVE_ASRLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, }, 10336 { 58 /* asrl */, ARM::MVE_ASRLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 10337 { 63 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10338 { 63 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm }, }, 10339 { 63 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 10340 { 63 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, }, 10341 { 63 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, }, 10342 { 65 /* bf */, ARM::t2BFi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, }, 10343 { 68 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, }, 10344 { 68 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, }, 10345 { 72 /* bfcsel */, ARM::t2BFic, Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_CondCodeNoAL }, }, 10346 { 79 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, }, 10347 { 79 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, }, 10348 { 83 /* bfl */, ARM::t2BFLi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, }, 10349 { 87 /* bflx */, ARM::t2BFLr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, }, 10350 { 92 /* bfx */, ARM::t2BFr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, }, 10351 { 96 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10352 { 96 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10353 { 96 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10354 { 96 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10355 { 96 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10356 { 96 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10357 { 96 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10358 { 96 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10359 { 96 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10360 { 96 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10361 { 96 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10362 { 96 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10363 { 96 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10364 { 96 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 10365 { 96 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10366 { 96 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10367 { 96 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10368 { 96 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10369 { 96 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10370 { 96 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10371 { 96 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10372 { 96 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10373 { 96 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10374 { 96 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10375 { 96 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10376 { 96 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10377 { 96 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10378 { 100 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, }, 10379 { 100 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, AMFBS_IsThumb, { }, }, 10380 { 100 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, }, 10381 { 100 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, }, 10382 { 105 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, }, 10383 { 105 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10384 { 105 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 10385 { 108 /* blx */, ARM::BLX, Convert__Reg1_0, AMFBS_IsARM_HasV5T, { MCK_GPR }, }, 10386 { 108 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, AMFBS_IsARM_HasV5T, { MCK_ThumbBranchTarget }, }, 10387 { 108 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR }, }, 10388 { 108 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_HasV5T, { MCK_CondCode, MCK_GPR }, }, 10389 { 108 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, AMFBS_IsThumb_HasV5T_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10390 { 112 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 10391 { 118 /* bx */, ARM::BX, Convert__Reg1_0, AMFBS_IsARM_HasV4T, { MCK_GPR }, }, 10392 { 118 /* bx */, ARM::BX_RET, Convert__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPRlr }, }, 10393 { 118 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPR }, }, 10394 { 118 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR }, }, 10395 { 121 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, }, 10396 { 121 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, }, 10397 { 125 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPR }, }, 10398 { 130 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10399 { 135 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10400 { 139 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10401 { 139 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10402 { 143 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10403 { 143 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10404 { 148 /* cinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10405 { 153 /* cinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10406 { 158 /* clrex */, ARM::CLREX, Convert_NoOperands, AMFBS_IsARM_HasV6K, { }, }, 10407 { 158 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, AMFBS_IsThumb_HasV7Clrex, { MCK_CondCode }, }, 10408 { 164 /* clrm */, ARM::t2CLRM, Convert__CondCode2_0__RegListWithAPSR1_1, AMFBS_HasV8_1MMainline, { MCK_CondCode, MCK_RegListWithAPSR }, }, 10409 { 169 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10410 { 169 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10411 { 173 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10412 { 173 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 10413 { 173 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10414 { 173 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 10415 { 173 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10416 { 173 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10417 { 173 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 10418 { 173 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10419 { 173 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10420 { 173 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10421 { 173 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 10422 { 173 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10423 { 173 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 10424 { 177 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10425 { 177 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 10426 { 177 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 10427 { 177 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10428 { 177 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10429 { 177 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10430 { 177 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 10431 { 177 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10432 { 177 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10433 { 177 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10434 { 177 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10435 { 177 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 10436 { 177 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10437 { 177 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 10438 { 181 /* cneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10439 { 186 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, }, 10440 { 186 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 10441 { 186 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, }, 10442 { 186 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, }, 10443 { 186 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsThumb, { MCK_Imm, MCK_ProcIFlags }, }, 10444 { 186 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, }, 10445 { 186 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, }, 10446 { 186 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, }, 10447 { 186 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, AMFBS_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, }, 10448 { 190 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10449 { 190 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10450 { 197 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10451 { 197 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10452 { 205 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10453 { 205 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10454 { 213 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10455 { 213 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10456 { 221 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10457 { 221 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10458 { 228 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10459 { 228 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10460 { 235 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 10461 { 235 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, }, 10462 { 235 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 10463 { 240 /* csel */, ARM::t2CSEL, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10464 { 245 /* cset */, ARM::t2CSINC, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, }, 10465 { 250 /* csetm */, ARM::t2CSINV, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, }, 10466 { 256 /* csinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10467 { 262 /* csinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10468 { 268 /* csneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10469 { 274 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasV7, { MCK_CondCode, MCK_Imm0_15 }, }, 10470 { 274 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, }, 10471 { 278 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 10472 { 284 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 10473 { 290 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 10474 { 296 /* dfb */, ARM::DSB, Convert__imm_95_12, AMFBS_IsARM_HasDFB, { }, }, 10475 { 296 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, AMFBS_HasDFB, { MCK_CondCode }, }, 10476 { 300 /* dls */, ARM::t2DLS, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR }, }, 10477 { 304 /* dlstp */, ARM::MVE_DLSTP_16, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR }, }, 10478 { 304 /* dlstp */, ARM::MVE_DLSTP_32, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR }, }, 10479 { 304 /* dlstp */, ARM::MVE_DLSTP_64, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR }, }, 10480 { 304 /* dlstp */, ARM::MVE_DLSTP_8, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR }, }, 10481 { 310 /* dmb */, ARM::DMB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 10482 { 310 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 10483 { 310 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, }, 10484 { 310 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 10485 { 314 /* dsb */, ARM::DSB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 10486 { 314 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 10487 { 314 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, }, 10488 { 314 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 10489 { 318 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10490 { 318 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10491 { 318 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10492 { 318 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10493 { 318 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10494 { 318 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10495 { 318 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10496 { 318 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10497 { 318 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10498 { 318 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10499 { 318 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10500 { 318 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10501 { 318 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10502 { 318 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10503 { 318 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10504 { 318 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10505 { 318 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10506 { 318 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10507 { 318 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10508 { 318 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10509 { 318 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10510 { 322 /* eret */, ARM::ERET, Convert__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode }, }, 10511 { 322 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2_HasVirtualization, { MCK_CondCode }, }, 10512 { 327 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsARM_HasRAS, { MCK_CondCode }, }, 10513 { 327 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode }, }, 10514 { 327 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode, MCK__DOT_w }, }, 10515 { 331 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10516 { 337 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10517 { 343 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR }, }, 10518 { 350 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, }, 10519 { 357 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, }, 10520 { 365 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, }, 10521 { 373 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10522 { 381 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 10523 { 381 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10524 { 389 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 10525 { 395 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 10526 { 401 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode }, }, 10527 { 408 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10528 { 416 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 10529 { 416 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10530 { 424 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10531 { 430 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10532 { 436 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, }, 10533 { 436 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_Imm0_239 }, }, 10534 { 436 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, }, 10535 { 436 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, }, 10536 { 441 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, AMFBS_IsThumb_HasV8, { MCK_Imm0_63 }, }, 10537 { 441 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, AMFBS_IsARM_HasV8, { MCK_Imm0_65535 }, }, 10538 { 445 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, AMFBS_IsARM_HasVirtualization, { MCK_Imm0_65535 }, }, 10539 { 445 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, AMFBS_IsThumb2, { MCK_Imm0_65535 }, }, 10540 { 445 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, AMFBS_IsThumb2_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, }, 10541 { 449 /* isb */, ARM::ISB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 10542 { 449 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 10543 { 449 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_InstSyncBarrierOpt }, }, 10544 { 449 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, }, 10545 { 453 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, }, 10546 { 453 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, }, 10547 { 456 /* lctp */, ARM::MVE_LCTP, Convert__CondCode2_0, AMFBS_HasMVEInt, { MCK_CondCode }, }, 10548 { 461 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10549 { 461 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10550 { 465 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10551 { 465 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10552 { 470 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10553 { 470 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10554 { 476 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10555 { 476 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10556 { 483 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 10557 { 483 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 10558 { 490 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10559 { 490 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10560 { 497 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10561 { 497 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10562 { 502 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10563 { 502 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10564 { 502 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10565 { 502 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10566 { 502 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10567 { 502 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10568 { 502 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10569 { 502 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10570 { 506 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10571 { 506 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10572 { 506 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10573 { 506 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10574 { 506 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10575 { 506 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10576 { 506 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10577 { 506 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10578 { 511 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10579 { 511 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10580 { 511 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10581 { 511 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10582 { 511 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10583 { 511 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10584 { 511 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10585 { 511 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10586 { 517 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10587 { 517 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 10588 { 517 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10589 { 517 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 10590 { 517 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10591 { 517 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 10592 { 517 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10593 { 517 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 10594 { 522 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, }, 10595 { 522 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10596 { 522 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10597 { 522 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 10598 { 522 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 10599 { 522 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10600 { 522 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10601 { 522 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 10602 { 522 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10603 { 522 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 10604 { 526 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10605 { 526 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10606 { 526 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 10607 { 526 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 10608 { 532 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10609 { 532 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10610 { 532 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 10611 { 532 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10612 { 532 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10613 { 532 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 10614 { 532 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10615 { 532 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 10616 { 538 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 10617 { 538 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 10618 { 538 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 10619 { 538 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 10620 { 544 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, }, 10621 { 544 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, }, 10622 { 544 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 10623 { 544 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 10624 { 544 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 10625 { 544 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, }, 10626 { 544 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 10627 { 544 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 10628 { 544 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 10629 { 544 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 10630 { 544 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 10631 { 544 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 10632 { 544 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 10633 { 544 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, }, 10634 { 544 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, }, 10635 { 544 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, }, 10636 { 544 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 10637 { 544 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 10638 { 544 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, }, 10639 { 544 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 10640 { 544 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 10641 { 544 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 10642 { 544 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 10643 { 544 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 10644 { 544 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 10645 { 548 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 10646 { 548 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 10647 { 548 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10648 { 548 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 10649 { 548 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 10650 { 548 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 10651 { 548 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 10652 { 548 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 10653 { 548 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10654 { 548 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 10655 { 548 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 10656 { 548 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 10657 { 548 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10658 { 548 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 10659 { 548 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 10660 { 548 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 10661 { 548 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 10662 { 548 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 10663 { 548 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 10664 { 553 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 10665 { 553 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10666 { 553 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 10667 { 553 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 10668 { 559 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 10669 { 559 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 10670 { 559 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 10671 { 559 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 10672 { 559 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 10673 { 559 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 10674 { 564 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 10675 { 564 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10676 { 570 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10677 { 570 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10678 { 577 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 10679 { 577 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 10680 { 584 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10681 { 584 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10682 { 591 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 10683 { 591 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 10684 { 591 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10685 { 591 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 10686 { 591 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 10687 { 591 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 10688 { 591 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10689 { 591 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 10690 { 591 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 10691 { 591 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 10692 { 591 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 10693 { 591 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10694 { 591 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 10695 { 591 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 10696 { 591 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 10697 { 591 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 10698 { 596 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 10699 { 596 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 10700 { 596 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 10701 { 602 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 10702 { 602 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10703 { 602 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 10704 { 602 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 10705 { 602 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 10706 { 602 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10707 { 602 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 10708 { 602 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 10709 { 602 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 10710 { 602 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 10711 { 602 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10712 { 602 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 10713 { 602 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 10714 { 602 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 10715 { 602 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 10716 { 608 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 10717 { 608 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 10718 { 608 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 10719 { 615 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 10720 { 615 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10721 { 615 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 10722 { 615 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 10723 { 615 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 10724 { 615 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10725 { 615 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 10726 { 615 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 10727 { 615 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 10728 { 615 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 10729 { 615 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 10730 { 615 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 10731 { 615 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 10732 { 615 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 10733 { 615 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 10734 { 621 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 10735 { 621 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 10736 { 621 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 10737 { 628 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 10738 { 628 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 10739 { 628 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 10740 { 628 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 10741 { 633 /* le */, ARM::t2LE, Convert__LELabel1_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_LELabel }, }, 10742 { 633 /* le */, ARM::t2LEUpdate, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_LELabel }, }, 10743 { 636 /* letp */, ARM::MVE_LETP, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_HasMVEInt, { MCK_GPRlr, MCK_LELabel }, }, 10744 { 641 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10745 { 641 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, }, 10746 { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10747 { 641 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, }, 10748 { 641 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10749 { 641 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 10750 { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10751 { 641 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, }, 10752 { 641 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, }, 10753 { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10754 { 641 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 10755 { 641 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, }, 10756 { 641 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10757 { 641 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 10758 { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10759 { 641 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 10760 { 641 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, }, 10761 { 645 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, }, 10762 { 645 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 10763 { 650 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10764 { 650 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 10765 { 650 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10766 { 650 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 10767 { 650 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10768 { 650 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 10769 { 650 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10770 { 650 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 10771 { 650 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 10772 { 650 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10773 { 650 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10774 { 650 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10775 { 650 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 10776 { 650 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10777 { 650 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10778 { 654 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 10779 { 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 10780 { 659 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 10781 { 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10782 { 659 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10783 { 663 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 10784 { 663 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 10785 { 663 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10786 { 663 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10787 { 668 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 10788 { 668 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 10789 { 673 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 10790 { 673 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 10791 { 679 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10792 { 679 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10793 { 679 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10794 { 683 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10795 { 683 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10796 { 687 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, }, 10797 { 687 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, }, 10798 { 687 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10799 { 687 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 10800 { 687 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10801 { 687 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10802 { 687 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10803 { 687 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 10804 { 687 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, }, 10805 { 687 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 10806 { 687 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 10807 { 687 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10808 { 687 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10809 { 687 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10810 { 687 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10811 { 687 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10812 { 687 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 10813 { 687 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10814 { 687 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 10815 { 687 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10816 { 687 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 10817 { 691 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb, { MCK_tGPR, MCK_tGPR }, }, 10818 { 691 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, AMFBS_IsThumb, { MCK_tGPR, MCK_Imm0_255 }, }, 10819 { 691 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10820 { 691 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 10821 { 691 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10822 { 691 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10823 { 691 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10824 { 691 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 10825 { 691 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10826 { 691 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 10827 { 696 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 10828 { 696 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, }, 10829 { 701 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 10830 { 701 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 10831 { 706 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 10832 { 706 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 10833 { 706 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10834 { 706 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10835 { 710 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 10836 { 710 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 10837 { 710 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10838 { 710 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10839 { 715 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 10840 { 715 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 10841 { 720 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 10842 { 720 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 10843 { 726 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, }, 10844 { 726 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, }, 10845 { 726 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, }, 10846 { 726 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, }, 10847 { 726 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, }, 10848 { 726 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, }, 10849 { 726 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, }, 10850 { 726 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, }, 10851 { 726 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, }, 10852 { 730 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, }, 10853 { 730 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, }, 10854 { 730 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 10855 { 730 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 10856 { 730 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, }, 10857 { 730 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, }, 10858 { 734 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10859 { 734 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10860 { 734 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10861 { 734 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10862 { 734 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 10863 { 734 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10864 { 734 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10865 { 738 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10866 { 738 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10867 { 738 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 10868 { 738 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10869 { 738 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10870 { 738 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10871 { 738 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10872 { 738 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10873 { 738 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10874 { 738 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10875 { 738 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10876 { 738 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10877 { 738 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10878 { 742 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10879 { 742 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10880 { 742 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10881 { 746 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__imm_95_0, AMFBS_IsThumb, { }, }, 10882 { 746 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 10883 { 746 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 10884 { 746 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, }, 10885 { 746 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 10886 { 750 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10887 { 750 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10888 { 750 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10889 { 750 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10890 { 750 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10891 { 750 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10892 { 750 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10893 { 750 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10894 { 754 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10895 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10896 { 754 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10897 { 754 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10898 { 754 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10899 { 754 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10900 { 754 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10901 { 754 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10902 { 754 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10903 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10904 { 754 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10905 { 754 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10906 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10907 { 754 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10908 { 754 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10909 { 754 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10910 { 754 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10911 { 754 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10912 { 754 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10913 { 754 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10914 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10915 { 754 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10916 { 754 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10917 { 758 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10918 { 758 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10919 { 758 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, }, 10920 { 758 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, }, 10921 { 764 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10922 { 764 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10923 { 764 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, }, 10924 { 764 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, }, 10925 { 770 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, }, 10926 { 770 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, }, 10927 { 770 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm }, }, 10928 { 770 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 10929 { 770 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, }, 10930 { 770 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, }, 10931 { 770 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 10932 { 774 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemImm12Offset }, }, 10933 { 774 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemRegOffset }, }, 10934 { 774 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 10935 { 774 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, }, 10936 { 774 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, }, 10937 { 779 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7, { MCK_MemImm12Offset }, }, 10938 { 779 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7, { MCK_MemRegOffset }, }, 10939 { 779 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_Imm }, }, 10940 { 779 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 10941 { 779 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, }, 10942 { 779 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, }, 10943 { 779 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 10944 { 783 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, }, 10945 { 783 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 10946 { 783 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, }, 10947 { 783 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 10948 { 787 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__imm_95_0, AMFBS_HasDB_IsThumb2, { }, }, 10949 { 787 /* pssbb */, ARM::DSB, Convert__imm_95_4, AMFBS_IsARM_HasDB, { }, }, 10950 { 793 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, }, 10951 { 793 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 10952 { 793 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, }, 10953 { 793 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 10954 { 798 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10955 { 798 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10956 { 803 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10957 { 803 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10958 { 810 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10959 { 810 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10960 { 816 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10961 { 816 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10962 { 821 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10963 { 821 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10964 { 827 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10965 { 827 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10966 { 833 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10967 { 833 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10968 { 838 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10969 { 838 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10970 { 843 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10971 { 843 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10972 { 850 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10973 { 850 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10974 { 856 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10975 { 856 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10976 { 861 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10977 { 861 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10978 { 861 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10979 { 861 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10980 { 865 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10981 { 865 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10982 { 865 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10983 { 865 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10984 { 871 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10985 { 871 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10986 { 871 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10987 { 871 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10988 { 877 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 10989 { 877 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 10990 { 883 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 10991 { 883 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 10992 { 883 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 10993 { 883 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 10994 { 889 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 10995 { 889 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 10996 { 889 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 10997 { 889 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 10998 { 895 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 10999 { 895 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 11000 { 901 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11001 { 901 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11002 { 901 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm0_31 }, }, 11003 { 901 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11004 { 901 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 11005 { 901 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11006 { 901 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm0_31 }, }, 11007 { 901 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11008 { 901 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, }, 11009 { 901 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11010 { 901 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 11011 { 901 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11012 { 901 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, }, 11013 { 905 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11014 { 905 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11015 { 909 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11016 { 909 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11017 { 909 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11018 { 909 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11019 { 909 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11020 { 909 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11021 { 909 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11022 { 909 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__HASH_0 }, }, 11023 { 909 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11024 { 909 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11025 { 909 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11026 { 909 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11027 { 909 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11028 { 909 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11029 { 909 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11030 { 909 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11031 { 913 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11032 { 913 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11033 { 913 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11034 { 913 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11035 { 913 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11036 { 913 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11037 { 913 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11038 { 913 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11039 { 917 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11040 { 917 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11041 { 924 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11042 { 924 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11043 { 930 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11044 { 930 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11045 { 935 /* sb */, ARM::SB, Convert_NoOperands, AMFBS_IsARM_HasSB, { }, }, 11046 { 935 /* sb */, ARM::t2SB, Convert_NoOperands, AMFBS_IsThumb2_HasSB, { }, }, 11047 { 938 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11048 { 938 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11049 { 938 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11050 { 938 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11051 { 938 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 11052 { 938 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11053 { 938 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11054 { 938 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11055 { 938 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11056 { 938 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 11057 { 938 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11058 { 938 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11059 { 938 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11060 { 938 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 11061 { 938 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11062 { 938 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11063 { 938 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11064 { 942 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 11065 { 942 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 11066 { 947 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11067 { 947 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11068 { 952 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11069 { 952 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11070 { 956 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, AMFBS_IsThumb_IsNotMClass, { MCK_SetEndImm }, }, 11071 { 956 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, }, 11072 { 963 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, AMFBS_IsARM_HasV8_HasV8_1a, { MCK_Imm0_1 }, }, 11073 { 963 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, AMFBS_IsThumb2_HasV8_HasV8_1a, { MCK_Imm0_1 }, }, 11074 { 970 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 11075 { 970 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 11076 { 970 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11077 { 974 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, }, 11078 { 974 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 11079 { 974 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode, MCK__DOT_w }, }, 11080 { 979 /* sg */, ARM::t2SG, Convert__CondCode2_0, AMFBS_Has8MSecExt, { MCK_CondCode }, }, 11081 { 982 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11082 { 988 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11083 { 994 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11084 { 1000 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11085 { 1006 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11086 { 1014 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11087 { 1022 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11088 { 1030 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11089 { 1039 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11090 { 1049 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11091 { 1059 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11092 { 1059 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11093 { 1067 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11094 { 1067 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11095 { 1074 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11096 { 1074 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11097 { 1080 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11098 { 1080 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11099 { 1086 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11100 { 1086 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11101 { 1094 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11102 { 1094 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11103 { 1101 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 11104 { 1101 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 11105 { 1105 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11106 { 1105 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11107 { 1112 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11108 { 1112 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11109 { 1119 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11110 { 1119 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11111 { 1125 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11112 { 1125 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11113 { 1132 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11114 { 1132 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11115 { 1132 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11116 { 1138 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11117 { 1138 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11118 { 1146 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11119 { 1146 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11120 { 1154 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11121 { 1154 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11122 { 1161 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11123 { 1161 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11124 { 1169 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11125 { 1169 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11126 { 1177 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11127 { 1177 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11128 { 1185 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11129 { 1185 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11130 { 1192 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11131 { 1192 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11132 { 1199 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11133 { 1199 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11134 { 1206 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11135 { 1206 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11136 { 1213 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11137 { 1213 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11138 { 1219 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11139 { 1219 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11140 { 1226 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11141 { 1226 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11142 { 1233 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11143 { 1233 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11144 { 1241 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11145 { 1241 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11146 { 1247 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11147 { 1247 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11148 { 1254 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11149 { 1254 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11150 { 1260 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11151 { 1260 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11152 { 1267 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11153 { 1267 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11154 { 1273 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11155 { 1273 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11156 { 1280 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11157 { 1280 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11158 { 1286 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11159 { 1286 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11160 { 1293 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11161 { 1293 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11162 { 1300 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11163 { 1300 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11164 { 1307 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11165 { 1307 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11166 { 1307 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11167 { 1313 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11168 { 1313 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11169 { 1320 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11170 { 1320 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11171 { 1327 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11172 { 1327 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11173 { 1334 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11174 { 1334 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11175 { 1341 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11176 { 1341 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11177 { 1347 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11178 { 1347 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11179 { 1354 /* sqrshr */, ARM::MVE_SQRSHR, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11180 { 1361 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, }, 11181 { 1369 /* sqshl */, ARM::MVE_SQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11182 { 1375 /* sqshll */, ARM::MVE_SQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11183 { 1382 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11184 { 1382 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11185 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11186 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11187 { 1388 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11188 { 1388 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11189 { 1388 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 11190 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11191 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11192 { 1388 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 11193 { 1388 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11194 { 1388 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11195 { 1394 /* srshr */, ARM::MVE_SRSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11196 { 1400 /* srshrl */, ARM::MVE_SRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11197 { 1407 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11198 { 1407 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11199 { 1407 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 11200 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11201 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11202 { 1407 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 11203 { 1407 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11204 { 1407 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11205 { 1413 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11206 { 1413 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11207 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11208 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11209 { 1419 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, }, 11210 { 1419 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, }, 11211 { 1419 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, }, 11212 { 1419 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, }, 11213 { 1424 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, }, 11214 { 1424 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, }, 11215 { 1431 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11216 { 1431 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11217 { 1436 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__imm_95_0, AMFBS_HasDB_IsThumb2, { }, }, 11218 { 1436 /* ssbb */, ARM::DSB, Convert__imm_95_0, AMFBS_IsARM_HasDB, { }, }, 11219 { 1441 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11220 { 1441 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11221 { 1448 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11222 { 1448 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11223 { 1454 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11224 { 1454 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11225 { 1454 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11226 { 1454 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11227 { 1454 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11228 { 1454 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11229 { 1454 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11230 { 1454 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11231 { 1458 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11232 { 1458 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11233 { 1458 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11234 { 1458 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11235 { 1458 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11236 { 1458 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11237 { 1458 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11238 { 1458 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11239 { 1463 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11240 { 1463 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11241 { 1463 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11242 { 1463 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11243 { 1463 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11244 { 1463 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11245 { 1463 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11246 { 1463 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11247 { 1469 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11248 { 1469 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11249 { 1469 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11250 { 1469 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11251 { 1469 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11252 { 1469 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11253 { 1469 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11254 { 1469 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11255 { 1474 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11256 { 1474 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11257 { 1478 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11258 { 1478 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11259 { 1483 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11260 { 1483 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11261 { 1489 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11262 { 1489 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11263 { 1496 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 11264 { 1496 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11265 { 1503 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11266 { 1503 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11267 { 1510 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11268 { 1510 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11269 { 1515 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11270 { 1515 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11271 { 1515 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11272 { 1515 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11273 { 1515 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 11274 { 1515 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11275 { 1515 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11276 { 1515 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11277 { 1515 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11278 { 1515 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11279 { 1519 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11280 { 1519 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11281 { 1519 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11282 { 1519 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11283 { 1525 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11284 { 1525 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11285 { 1525 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11286 { 1525 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11287 { 1525 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11288 { 1525 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11289 { 1525 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11290 { 1525 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11291 { 1531 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11292 { 1531 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11293 { 1531 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11294 { 1531 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11295 { 1537 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 11296 { 1537 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11297 { 1537 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 11298 { 1537 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 11299 { 1537 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 11300 { 1537 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 11301 { 1537 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 11302 { 1537 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 11303 { 1537 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 11304 { 1537 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 11305 { 1537 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11306 { 1537 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, }, 11307 { 1537 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11308 { 1537 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11309 { 1537 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11310 { 1537 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11311 { 1541 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 11312 { 1541 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11313 { 1541 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 11314 { 1541 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11315 { 1541 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11316 { 1541 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 11317 { 1541 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 11318 { 1541 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 11319 { 1541 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 11320 { 1541 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11321 { 1541 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11322 { 1541 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11323 { 1541 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11324 { 1541 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11325 { 1541 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11326 { 1546 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 11327 { 1546 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11328 { 1546 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11329 { 1546 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11330 { 1552 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 11331 { 1552 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 11332 { 1552 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 11333 { 1552 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11334 { 1552 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11335 { 1552 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11336 { 1557 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 11337 { 1557 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11338 { 1563 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11339 { 1563 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11340 { 1570 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 11341 { 1570 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11342 { 1577 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11343 { 1577 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11344 { 1584 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 11345 { 1584 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11346 { 1584 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 11347 { 1584 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11348 { 1584 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11349 { 1584 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 11350 { 1584 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 11351 { 1584 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 11352 { 1584 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11353 { 1584 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11354 { 1584 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11355 { 1584 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11356 { 1589 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 11357 { 1589 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 11358 { 1589 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, }, 11359 { 1595 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 11360 { 1595 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11361 { 1595 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11362 { 1595 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11363 { 1600 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 11364 { 1600 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 11365 { 1600 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 11366 { 1600 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, }, 11367 { 1600 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11368 { 1600 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 11369 { 1600 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 11370 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11371 { 1600 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 11372 { 1600 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11373 { 1600 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11374 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11375 { 1600 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 11376 { 1600 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11377 { 1600 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11378 { 1600 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 11379 { 1600 /* sub */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 11380 { 1600 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 11381 { 1600 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 11382 { 1600 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 11383 { 1600 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, }, 11384 { 1600 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 11385 { 1600 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 11386 { 1600 /* sub */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 11387 { 1600 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 11388 { 1600 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 11389 { 1600 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 11390 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 11391 { 1600 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 11392 { 1600 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 11393 { 1600 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11394 { 1600 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11395 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11396 { 1600 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 11397 { 1600 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11398 { 1600 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11399 { 1600 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 11400 { 1600 /* sub */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 11401 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 11402 { 1600 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 11403 { 1600 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 11404 { 1600 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11405 { 1604 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, }, 11406 { 1609 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 11407 { 1609 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 11408 { 1609 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 11409 { 1609 /* subw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 11410 { 1609 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 11411 { 1609 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 11412 { 1614 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, }, 11413 { 1614 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, }, 11414 { 1618 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 11415 { 1622 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 11416 { 1627 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11417 { 1627 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11418 { 1627 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11419 { 1627 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11420 { 1633 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11421 { 1633 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11422 { 1633 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11423 { 1633 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11424 { 1641 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11425 { 1641 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11426 { 1641 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11427 { 1641 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11428 { 1647 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11429 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11430 { 1647 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11431 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11432 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11433 { 1647 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11434 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11435 { 1652 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11436 { 1652 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11437 { 1652 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11438 { 1652 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11439 { 1652 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11440 { 1659 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11441 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11442 { 1659 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11443 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11444 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11445 { 1659 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11446 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11447 { 1664 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBB }, }, 11448 { 1668 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBH }, }, 11449 { 1672 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11450 { 1672 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11451 { 1672 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11452 { 1672 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11453 { 1672 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11454 { 1672 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11455 { 1672 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11456 { 1672 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11457 { 1672 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11458 { 1672 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11459 { 1676 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, AMFBS_IsARM_UseNaClTrap, { }, }, 11460 { 1676 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, }, 11461 { 1676 /* trap */, ARM::tTRAP, Convert_NoOperands, AMFBS_IsThumb, { }, }, 11462 { 1681 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, AMFBS_IsARM_HasV8_4a, { MCK_TraceSyncBarrierOpt }, }, 11463 { 1681 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, }, 11464 { 1685 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11465 { 1685 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11466 { 1685 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11467 { 1685 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11468 { 1685 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11469 { 1685 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11470 { 1685 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11471 { 1685 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11472 { 1685 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11473 { 1685 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11474 { 1685 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11475 { 1689 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 11476 { 1692 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 11477 { 1696 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 11478 { 1701 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 11479 { 1705 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11480 { 1705 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11481 { 1712 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11482 { 1712 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11483 { 1718 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11484 { 1718 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11485 { 1723 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 11486 { 1723 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 11487 { 1728 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, }, 11488 { 1728 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, }, 11489 { 1728 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, }, 11490 { 1732 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11491 { 1732 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11492 { 1737 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11493 { 1737 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11494 { 1745 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11495 { 1745 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11496 { 1752 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11497 { 1752 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11498 { 1758 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11499 { 1758 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11500 { 1764 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11501 { 1764 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11502 { 1772 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11503 { 1772 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11504 { 1779 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11505 { 1779 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11506 { 1785 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11507 { 1785 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11508 { 1785 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11509 { 1791 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11510 { 1791 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11511 { 1791 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11512 { 1797 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11513 { 1797 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11514 { 1805 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11515 { 1805 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11516 { 1812 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11517 { 1812 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11518 { 1818 /* uqrshl */, ARM::MVE_UQRSHL, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11519 { 1825 /* uqrshll */, ARM::MVE_UQRSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, }, 11520 { 1833 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11521 { 1833 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11522 { 1839 /* uqshl */, ARM::MVE_UQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11523 { 1845 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11524 { 1852 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11525 { 1852 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11526 { 1860 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11527 { 1860 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11528 { 1867 /* urshr */, ARM::MVE_URSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11529 { 1873 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11530 { 1880 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11531 { 1880 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11532 { 1886 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11533 { 1886 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11534 { 1893 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, }, 11535 { 1893 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, }, 11536 { 1893 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, }, 11537 { 1893 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, }, 11538 { 1898 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, }, 11539 { 1898 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, }, 11540 { 1905 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11541 { 1905 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11542 { 1910 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11543 { 1910 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11544 { 1917 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11545 { 1917 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11546 { 1923 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11547 { 1923 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11548 { 1923 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11549 { 1923 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11550 { 1929 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11551 { 1929 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11552 { 1929 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11553 { 1929 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11554 { 1937 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11555 { 1937 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11556 { 1937 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11557 { 1937 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11558 { 1943 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11559 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11560 { 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11561 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11562 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11563 { 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11564 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11565 { 1948 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11566 { 1948 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11567 { 1948 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11568 { 1948 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11569 { 1948 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11570 { 1955 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11571 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11572 { 1955 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11573 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11574 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11575 { 1955 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 11576 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11577 { 1960 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11578 { 1960 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11579 { 1960 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11580 { 1960 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11581 { 1960 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11582 { 1960 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11583 { 1960 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11584 { 1960 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11585 { 1960 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11586 { 1960 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11587 { 1960 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11588 { 1960 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11589 { 1965 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11590 { 1965 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11591 { 1965 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11592 { 1965 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11593 { 1965 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11594 { 1965 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11595 { 1971 /* vabav */, ARM::MVE_VABAVs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11596 { 1971 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11597 { 1971 /* vabav */, ARM::MVE_VABAVs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11598 { 1971 /* vabav */, ARM::MVE_VABAVu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11599 { 1971 /* vabav */, ARM::MVE_VABAVu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11600 { 1971 /* vabav */, ARM::MVE_VABAVu8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 11601 { 1977 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11602 { 1977 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11603 { 1977 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11604 { 1977 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11605 { 1977 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11606 { 1977 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11607 { 1977 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 11608 { 1977 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 11609 { 1977 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 11610 { 1977 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 11611 { 1977 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 11612 { 1977 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 11613 { 1977 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11614 { 1977 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11615 { 1977 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11616 { 1977 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11617 { 1977 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11618 { 1977 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11619 { 1977 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11620 { 1977 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11621 { 1977 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11622 { 1977 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11623 { 1977 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11624 { 1977 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11625 { 1977 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11626 { 1977 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11627 { 1977 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11628 { 1977 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11629 { 1977 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11630 { 1977 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11631 { 1977 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11632 { 1977 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11633 { 1977 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11634 { 1977 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11635 { 1977 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11636 { 1977 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11637 { 1977 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11638 { 1977 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11639 { 1977 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11640 { 1977 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11641 { 1982 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11642 { 1982 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11643 { 1982 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11644 { 1982 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11645 { 1982 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11646 { 1982 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11647 { 1988 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11648 { 1988 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11649 { 1988 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11650 { 1988 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11651 { 1988 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11652 { 1988 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11653 { 1988 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11654 { 1988 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11655 { 1988 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11656 { 1988 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11657 { 1988 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11658 { 1988 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11659 { 1988 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11660 { 1988 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 11661 { 1988 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 11662 { 1988 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 11663 { 1988 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 11664 { 1988 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 11665 { 1993 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11666 { 1993 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11667 { 1993 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11668 { 1993 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11669 { 1993 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11670 { 1993 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11671 { 1993 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11672 { 1993 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11673 { 1999 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11674 { 1999 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11675 { 1999 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11676 { 1999 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11677 { 1999 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11678 { 1999 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11679 { 1999 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11680 { 1999 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11681 { 2005 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11682 { 2005 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11683 { 2005 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11684 { 2005 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11685 { 2005 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11686 { 2005 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11687 { 2005 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11688 { 2005 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11689 { 2011 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11690 { 2011 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11691 { 2011 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11692 { 2011 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11693 { 2011 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11694 { 2011 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11695 { 2011 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11696 { 2011 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11697 { 2017 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11698 { 2022 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11699 { 2028 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11700 { 2028 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11701 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11702 { 2028 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11703 { 2028 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 11704 { 2028 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 11705 { 2028 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 11706 { 2028 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 11707 { 2028 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 11708 { 2028 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 11709 { 2028 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 11710 { 2028 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 11711 { 2028 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11712 { 2028 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11713 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11714 { 2028 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11715 { 2028 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11716 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11717 { 2028 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11718 { 2028 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11719 { 2028 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11720 { 2028 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11721 { 2028 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11722 { 2028 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11723 { 2028 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11724 { 2028 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11725 { 2028 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11726 { 2028 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11727 { 2028 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11728 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11729 { 2028 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11730 { 2028 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11731 { 2028 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11732 { 2028 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11733 { 2028 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11734 { 2028 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11735 { 2028 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11736 { 2028 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11737 { 2028 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11738 { 2028 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11739 { 2033 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11740 { 2033 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11741 { 2033 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11742 { 2040 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11743 { 2040 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11744 { 2040 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11745 { 2040 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11746 { 2040 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11747 { 2040 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11748 { 2046 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 11749 { 2046 /* vaddlv */, ARM::MVE_VADDLVu32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 11750 { 2053 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 11751 { 2053 /* vaddlva */, ARM::MVE_VADDLVu32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 11752 { 2061 /* vaddv */, ARM::MVE_VADDVs16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, }, 11753 { 2061 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, }, 11754 { 2061 /* vaddv */, ARM::MVE_VADDVs8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, }, 11755 { 2061 /* vaddv */, ARM::MVE_VADDVu16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, }, 11756 { 2061 /* vaddv */, ARM::MVE_VADDVu32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, }, 11757 { 2061 /* vaddv */, ARM::MVE_VADDVu8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, }, 11758 { 2067 /* vaddva */, ARM::MVE_VADDVs16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, }, 11759 { 2067 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, }, 11760 { 2067 /* vaddva */, ARM::MVE_VADDVs8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, }, 11761 { 2067 /* vaddva */, ARM::MVE_VADDVu16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, }, 11762 { 2067 /* vaddva */, ARM::MVE_VADDVu32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, }, 11763 { 2067 /* vaddva */, ARM::MVE_VADDVu8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, }, 11764 { 2074 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 11765 { 2074 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 11766 { 2074 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 11767 { 2074 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 11768 { 2074 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 11769 { 2074 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 11770 { 2074 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11771 { 2074 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11772 { 2074 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11773 { 2074 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11774 { 2074 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11775 { 2074 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11776 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 11777 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 11778 { 2080 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, }, 11779 { 2080 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, }, 11780 { 2080 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, }, 11781 { 2080 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, }, 11782 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11783 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11784 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11785 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11786 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 11787 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 11788 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11789 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11790 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11791 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11792 { 2080 /* vand */, ARM::MVE_VANDIZ0v8i16, Convert__Reg1_2__imm_95_0__InvertedExpandImm0_161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_InvertedExpandImm0_16 }, }, 11793 { 2080 /* vand */, ARM::MVE_VANDIZ8v8i16, Convert__Reg1_2__imm_95_0__InvertedExpandImm8_161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_InvertedExpandImm8_16 }, }, 11794 { 2080 /* vand */, ARM::MVE_VANDIZ0v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm0_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm0_32 }, }, 11795 { 2080 /* vand */, ARM::MVE_VANDIZ8v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm8_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm8_32 }, }, 11796 { 2080 /* vand */, ARM::MVE_VANDIZ16v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm16_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm16_32 }, }, 11797 { 2080 /* vand */, ARM::MVE_VANDIZ24v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm24_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm24_32 }, }, 11798 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11799 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11800 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11801 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11802 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11803 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11804 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11805 { 2080 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11806 { 2080 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11807 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11808 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11809 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11810 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11811 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11812 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11813 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11814 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11815 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11816 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11817 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11818 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 11819 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 11820 { 2085 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 11821 { 2085 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 11822 { 2085 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 11823 { 2085 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 11824 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11825 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11826 { 2085 /* vbic */, ARM::MVE_VBICIZ0v8i16, Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_ExpandImm0 }, }, 11827 { 2085 /* vbic */, ARM::MVE_VBICIZ8v8i16, Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_ExpandImm8 }, }, 11828 { 2085 /* vbic */, ARM::MVE_VBICIZ0v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm0 }, }, 11829 { 2085 /* vbic */, ARM::MVE_VBICIZ8v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm8 }, }, 11830 { 2085 /* vbic */, ARM::MVE_VBICIZ16v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm16 }, }, 11831 { 2085 /* vbic */, ARM::MVE_VBICIZ24v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm241_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm24 }, }, 11832 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11833 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11834 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11835 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11836 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11837 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11838 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11839 { 2085 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11840 { 2085 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11841 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11842 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11843 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11844 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11845 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11846 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11847 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11848 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11849 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11850 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11851 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 11852 { 2090 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11853 { 2090 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11854 { 2090 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11855 { 2090 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11856 { 2090 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11857 { 2090 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11858 { 2090 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11859 { 2090 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11860 { 2090 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11861 { 2090 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11862 { 2095 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11863 { 2095 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11864 { 2095 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11865 { 2095 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11866 { 2095 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11867 { 2095 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11868 { 2095 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11869 { 2095 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11870 { 2095 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11871 { 2095 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11872 { 2100 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11873 { 2100 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11874 { 2100 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 11875 { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11876 { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11877 { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11878 { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11879 { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11880 { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11881 { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11882 { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11883 { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11884 { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11885 { 2111 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 11886 { 2111 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 11887 { 2111 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 11888 { 2111 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 11889 { 2111 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 11890 { 2111 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 11891 { 2111 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 11892 { 2111 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 11893 { 2111 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 11894 { 2117 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 11895 { 2117 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11896 { 2117 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 11897 { 2117 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11898 { 2117 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__HASH_0 }, }, 11899 { 2117 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 11900 { 2117 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__HASH_0 }, }, 11901 { 2117 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 11902 { 2117 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__HASH_0 }, }, 11903 { 2117 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 11904 { 2117 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__HASH_0 }, }, 11905 { 2117 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 11906 { 2117 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__HASH_0 }, }, 11907 { 2117 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 11908 { 2117 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__HASH_0 }, }, 11909 { 2117 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 11910 { 2117 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 11911 { 2117 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11912 { 2117 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 11913 { 2117 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11914 { 2117 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11915 { 2117 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11916 { 2117 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11917 { 2117 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11918 { 2117 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11919 { 2117 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11920 { 2117 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11921 { 2117 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11922 { 2117 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11923 { 2117 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11924 { 2117 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11925 { 2117 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11926 { 2117 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11927 { 2117 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11928 { 2117 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11929 { 2117 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11930 { 2117 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11931 { 2117 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11932 { 2117 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11933 { 2117 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11934 { 2122 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 11935 { 2122 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11936 { 2122 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 11937 { 2122 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11938 { 2122 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 11939 { 2122 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11940 { 2122 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 11941 { 2122 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11942 { 2122 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 11943 { 2122 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11944 { 2122 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 11945 { 2122 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11946 { 2122 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 11947 { 2122 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 11948 { 2122 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 11949 { 2122 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 11950 { 2122 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 11951 { 2122 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 11952 { 2122 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 11953 { 2122 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11954 { 2122 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 11955 { 2122 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11956 { 2122 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 11957 { 2122 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11958 { 2122 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 11959 { 2122 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11960 { 2122 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11961 { 2122 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11962 { 2122 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11963 { 2122 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11964 { 2122 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11965 { 2122 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11966 { 2122 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11967 { 2122 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11968 { 2122 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11969 { 2122 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11970 { 2122 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11971 { 2122 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11972 { 2122 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11973 { 2122 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11974 { 2122 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11975 { 2122 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11976 { 2122 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11977 { 2122 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11978 { 2122 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11979 { 2122 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11980 { 2122 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11981 { 2122 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11982 { 2122 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 11983 { 2122 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11984 { 2122 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 11985 { 2122 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11986 { 2127 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 11987 { 2127 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11988 { 2127 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 11989 { 2127 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11990 { 2127 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 11991 { 2127 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11992 { 2127 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 11993 { 2127 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11994 { 2127 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 11995 { 2127 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11996 { 2127 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 11997 { 2127 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11998 { 2127 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 11999 { 2127 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12000 { 2127 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12001 { 2127 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12002 { 2127 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12003 { 2127 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12004 { 2127 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12005 { 2127 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12006 { 2127 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12007 { 2127 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12008 { 2127 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12009 { 2127 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12010 { 2127 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12011 { 2127 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12012 { 2127 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12013 { 2127 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12014 { 2127 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12015 { 2127 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12016 { 2127 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12017 { 2127 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12018 { 2127 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12019 { 2127 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12020 { 2127 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12021 { 2127 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12022 { 2127 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12023 { 2127 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12024 { 2127 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12025 { 2127 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12026 { 2127 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12027 { 2127 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12028 { 2127 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12029 { 2127 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12030 { 2127 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12031 { 2127 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12032 { 2127 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12033 { 2127 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12034 { 2127 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12035 { 2127 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12036 { 2127 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12037 { 2127 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12038 { 2132 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12039 { 2132 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12040 { 2132 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12041 { 2132 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12042 { 2132 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12043 { 2132 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12044 { 2132 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12045 { 2132 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12046 { 2132 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12047 { 2132 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12048 { 2132 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12049 { 2132 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12050 { 2132 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12051 { 2132 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12052 { 2132 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12053 { 2132 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12054 { 2132 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12055 { 2132 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12056 { 2132 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12057 { 2132 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12058 { 2132 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12059 { 2132 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12060 { 2132 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12061 { 2132 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12062 { 2132 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12063 { 2132 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12064 { 2132 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12065 { 2132 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12066 { 2132 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12067 { 2132 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12068 { 2132 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12069 { 2132 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12070 { 2132 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12071 { 2132 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12072 { 2132 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12073 { 2132 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12074 { 2137 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12075 { 2137 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12076 { 2137 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12077 { 2137 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12078 { 2137 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12079 { 2137 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12080 { 2137 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 12081 { 2137 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 12082 { 2137 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 12083 { 2142 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12084 { 2142 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12085 { 2142 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12086 { 2142 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12087 { 2142 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12088 { 2142 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12089 { 2142 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12090 { 2142 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12091 { 2142 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12092 { 2142 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12093 { 2142 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12094 { 2142 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12095 { 2142 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12096 { 2142 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12097 { 2142 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12098 { 2142 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12099 { 2142 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12100 { 2142 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12101 { 2142 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12102 { 2142 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12103 { 2142 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12104 { 2142 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12105 { 2142 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12106 { 2142 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12107 { 2142 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12108 { 2142 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12109 { 2142 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12110 { 2142 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12111 { 2142 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12112 { 2142 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12113 { 2142 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12114 { 2142 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12115 { 2142 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12116 { 2142 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12117 { 2142 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12118 { 2142 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12119 { 2147 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 12120 { 2147 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 12121 { 2147 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 12122 { 2147 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 12123 { 2147 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 12124 { 2147 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 12125 { 2147 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 12126 { 2147 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 12127 { 2147 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, }, 12128 { 2152 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 12129 { 2152 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 12130 { 2152 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 12131 { 2152 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 12132 { 2152 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 12133 { 2152 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 12134 { 2152 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 12135 { 2152 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 12136 { 2152 /* vcmla */, ARM::MVE_VCMLAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12137 { 2152 /* vcmla */, ARM::MVE_VCMLAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12138 { 2158 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, }, 12139 { 2158 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12140 { 2158 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, }, 12141 { 2158 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12142 { 2158 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, }, 12143 { 2158 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12144 { 2158 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12145 { 2158 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12146 { 2158 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12147 { 2158 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12148 { 2158 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12149 { 2158 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12150 { 2158 /* vcmp */, ARM::MVE_VCMPu16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12151 { 2158 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12152 { 2158 /* vcmp */, ARM::MVE_VCMPu32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12153 { 2158 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12154 { 2158 /* vcmp */, ARM::MVE_VCMPu8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12155 { 2158 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12156 { 2158 /* vcmp */, ARM::MVE_VCMPf32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 12157 { 2158 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 12158 { 2158 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12159 { 2158 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12160 { 2158 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12161 { 2158 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12162 { 2158 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12163 { 2158 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12164 { 2158 /* vcmp */, ARM::MVE_VCMPf16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 12165 { 2158 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 12166 { 2163 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, }, 12167 { 2163 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12168 { 2163 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, }, 12169 { 2163 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12170 { 2163 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, }, 12171 { 2163 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12172 { 2169 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12173 { 2169 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12174 { 2175 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 12175 { 2175 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 12176 { 2180 /* vctp */, ARM::MVE_VCTP16, Convert__imm_95_0__Reg1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_rGPR }, }, 12177 { 2180 /* vctp */, ARM::MVE_VCTP32, Convert__imm_95_0__Reg1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_rGPR }, }, 12178 { 2180 /* vctp */, ARM::MVE_VCTP64, Convert__imm_95_0__Reg1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_rGPR }, }, 12179 { 2180 /* vctp */, ARM::MVE_VCTP8, Convert__imm_95_0__Reg1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_rGPR }, }, 12180 { 2185 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12181 { 2185 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12182 { 2185 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12183 { 2185 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12184 { 2185 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12185 { 2185 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12186 { 2185 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12187 { 2185 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12188 { 2185 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12189 { 2185 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12190 { 2185 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12191 { 2185 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12192 { 2185 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12193 { 2185 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12194 { 2185 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12195 { 2185 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12196 { 2185 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 12197 { 2185 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12198 { 2185 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12199 { 2185 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 12200 { 2185 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12201 { 2185 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, }, 12202 { 2185 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, }, 12203 { 2185 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, }, 12204 { 2185 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, }, 12205 { 2185 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12206 { 2185 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12207 { 2185 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 12208 { 2185 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12209 { 2185 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12210 { 2185 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 12211 { 2185 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, }, 12212 { 2185 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12213 { 2185 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12214 { 2185 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12215 { 2185 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12216 { 2185 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 12217 { 2185 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 12218 { 2185 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 12219 { 2185 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 12220 { 2185 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12221 { 2185 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12222 { 2185 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12223 { 2185 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12224 { 2185 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12225 { 2185 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12226 { 2185 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12227 { 2185 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12228 { 2185 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12229 { 2185 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12230 { 2185 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12231 { 2185 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12232 { 2185 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12233 { 2185 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12234 { 2185 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12235 { 2185 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12236 { 2185 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12237 { 2185 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12238 { 2185 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12239 { 2185 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12240 { 2185 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12241 { 2185 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12242 { 2185 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12243 { 2185 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12244 { 2185 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12245 { 2185 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12246 { 2185 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12247 { 2185 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12248 { 2185 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12249 { 2185 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12250 { 2185 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12251 { 2185 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12252 { 2185 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12253 { 2185 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12254 { 2185 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12255 { 2185 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12256 { 2185 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12257 { 2185 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12258 { 2185 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12259 { 2185 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12260 { 2185 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12261 { 2185 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12262 { 2185 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12263 { 2185 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12264 { 2185 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12265 { 2185 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12266 { 2185 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12267 { 2185 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12268 { 2185 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12269 { 2185 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12270 { 2185 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12271 { 2185 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12272 { 2185 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12273 { 2185 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12274 { 2185 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12275 { 2185 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12276 { 2185 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12277 { 2185 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12278 { 2185 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12279 { 2185 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12280 { 2185 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12281 { 2185 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12282 { 2185 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12283 { 2185 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12284 { 2190 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12285 { 2190 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12286 { 2190 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12287 { 2190 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12288 { 2190 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12289 { 2190 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12290 { 2190 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12291 { 2190 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12292 { 2190 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12293 { 2190 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12294 { 2190 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12295 { 2190 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12296 { 2190 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12297 { 2190 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12298 { 2190 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12299 { 2190 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12300 { 2190 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12301 { 2190 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12302 { 2196 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12303 { 2196 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 12304 { 2196 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12305 { 2196 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12306 { 2196 /* vcvtb */, ARM::MVE_VCVTf32f16bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12307 { 2196 /* vcvtb */, ARM::MVE_VCVTf16f32bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12308 { 2202 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12309 { 2202 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12310 { 2202 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12311 { 2202 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12312 { 2202 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12313 { 2202 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12314 { 2202 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12315 { 2202 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12316 { 2202 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12317 { 2202 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12318 { 2202 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12319 { 2202 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12320 { 2202 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12321 { 2202 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12322 { 2202 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12323 { 2202 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12324 { 2202 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12325 { 2202 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12326 { 2208 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12327 { 2208 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12328 { 2208 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12329 { 2208 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12330 { 2208 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12331 { 2208 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12332 { 2208 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12333 { 2208 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12334 { 2208 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12335 { 2208 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12336 { 2208 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12337 { 2208 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12338 { 2208 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12339 { 2208 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12340 { 2208 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12341 { 2208 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12342 { 2208 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12343 { 2208 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12344 { 2214 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12345 { 2214 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12346 { 2214 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12347 { 2214 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12348 { 2214 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12349 { 2214 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12350 { 2214 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12351 { 2214 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12352 { 2214 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12353 { 2214 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12354 { 2214 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12355 { 2214 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12356 { 2214 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12357 { 2214 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12358 { 2214 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12359 { 2214 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12360 { 2214 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12361 { 2214 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12362 { 2220 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12363 { 2220 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12364 { 2220 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12365 { 2220 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12366 { 2220 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12367 { 2220 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12368 { 2226 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12369 { 2226 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 12370 { 2226 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12371 { 2226 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12372 { 2226 /* vcvtt */, ARM::MVE_VCVTf32f16th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12373 { 2226 /* vcvtt */, ARM::MVE_VCVTf16f32th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12374 { 2232 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12375 { 2232 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12376 { 2232 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12377 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12378 { 2238 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12379 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12380 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12381 { 2238 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12382 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12383 { 2243 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, }, 12384 { 2243 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, }, 12385 { 2243 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, }, 12386 { 2243 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, }, 12387 { 2243 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, }, 12388 { 2243 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, }, 12389 { 2243 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, }, 12390 { 2243 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, }, 12391 { 2243 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, }, 12392 { 2243 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, }, 12393 { 2243 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, }, 12394 { 2243 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, }, 12395 { 2243 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, }, 12396 { 2243 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, }, 12397 { 2243 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, }, 12398 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12399 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12400 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12401 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 12402 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 12403 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 12404 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 12405 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 12406 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 12407 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 12408 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 12409 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 12410 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 12411 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12412 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12413 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12414 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12415 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12416 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12417 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12418 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12419 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12420 { 2255 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12421 { 2255 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12422 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12423 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12424 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12425 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12426 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12427 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12428 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12429 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12430 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12431 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12432 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12433 { 2260 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12434 { 2260 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 12435 { 2260 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12436 { 2260 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 12437 { 2260 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12438 { 2260 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12439 { 2260 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 12440 { 2260 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12441 { 2260 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 12442 { 2260 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12443 { 2260 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 12444 { 2260 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12445 { 2260 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 12446 { 2260 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 12447 { 2265 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12448 { 2265 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12449 { 2265 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12450 { 2265 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12451 { 2265 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12452 { 2265 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12453 { 2265 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12454 { 2265 /* vfma */, ARM::MVE_VFMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12455 { 2265 /* vfma */, ARM::MVE_VFMA_qr_f32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12456 { 2265 /* vfma */, ARM::MVE_VFMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12457 { 2265 /* vfma */, ARM::MVE_VFMA_qr_f16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12458 { 2270 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12459 { 2270 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, }, 12460 { 2270 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 12461 { 2270 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, }, 12462 { 2276 /* vfmas */, ARM::MVE_VFMA_qr_Sf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12463 { 2276 /* vfmas */, ARM::MVE_VFMA_qr_Sf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12464 { 2282 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12465 { 2282 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12466 { 2282 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12467 { 2282 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12468 { 2282 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12469 { 2282 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12470 { 2282 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12471 { 2282 /* vfms */, ARM::MVE_VFMSf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12472 { 2282 /* vfms */, ARM::MVE_VFMSf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12473 { 2287 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12474 { 2287 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, }, 12475 { 2287 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 12476 { 2287 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, }, 12477 { 2293 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12478 { 2293 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12479 { 2293 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12480 { 2299 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12481 { 2299 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12482 { 2299 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12483 { 2305 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12484 { 2305 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12485 { 2305 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12486 { 2305 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12487 { 2305 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12488 { 2305 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12489 { 2305 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12490 { 2305 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12491 { 2305 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12492 { 2305 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12493 { 2305 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12494 { 2305 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12495 { 2305 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12496 { 2305 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12497 { 2305 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12498 { 2305 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12499 { 2305 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12500 { 2305 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12501 { 2305 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12502 { 2305 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12503 { 2305 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12504 { 2305 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12505 { 2305 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12506 { 2305 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12507 { 2305 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12508 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12509 { 2305 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12510 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12511 { 2305 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12512 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12513 { 2305 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12514 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12515 { 2305 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12516 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12517 { 2305 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12518 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12519 { 2311 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12520 { 2311 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12521 { 2311 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12522 { 2318 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12523 { 2318 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12524 { 2318 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12525 { 2318 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12526 { 2318 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12527 { 2318 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12528 { 2318 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12529 { 2318 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12530 { 2318 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12531 { 2318 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12532 { 2318 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12533 { 2318 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12534 { 2318 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12535 { 2318 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12536 { 2318 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12537 { 2318 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12538 { 2318 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12539 { 2318 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12540 { 2318 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12541 { 2318 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12542 { 2318 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12543 { 2318 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12544 { 2318 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12545 { 2318 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12546 { 2318 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12547 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12548 { 2318 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12549 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12550 { 2318 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12551 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12552 { 2318 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12553 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12554 { 2318 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12555 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12556 { 2318 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12557 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12558 { 2324 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12559 { 2324 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12560 { 2324 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12561 { 2330 /* vins */, ARM::VINSH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12562 { 2335 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12563 { 2335 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12564 { 2335 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12565 { 2342 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12566 { 2348 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 12567 { 2348 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12568 { 2348 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12569 { 2348 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, }, 12570 { 2348 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 12571 { 2348 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 12572 { 2348 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12573 { 2348 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 12574 { 2348 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12575 { 2348 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12576 { 2348 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, }, 12577 { 2348 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 12578 { 2348 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 12579 { 2348 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12580 { 2348 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12581 { 2348 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12582 { 2348 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 12583 { 2348 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12584 { 2348 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, }, 12585 { 2348 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12586 { 2348 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12587 { 2348 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, }, 12588 { 2348 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 12589 { 2348 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 12590 { 2348 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12591 { 2348 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12592 { 2348 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 12593 { 2348 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12594 { 2348 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12595 { 2348 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12596 { 2348 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12597 { 2348 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12598 { 2348 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 12599 { 2348 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12600 { 2348 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 12601 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 12602 { 2348 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 12603 { 2348 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12604 { 2348 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12605 { 2348 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12606 { 2348 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12607 { 2348 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12608 { 2348 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12609 { 2348 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12610 { 2348 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12611 { 2348 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12612 { 2348 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12613 { 2348 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12614 { 2348 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 12615 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 12616 { 2348 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 12617 { 2348 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12618 { 2348 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12619 { 2348 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12620 { 2348 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12621 { 2348 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12622 { 2348 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12623 { 2348 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12624 { 2348 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 12625 { 2348 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12626 { 2348 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12627 { 2348 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12628 { 2348 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12629 { 2348 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12630 { 2348 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12631 { 2348 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12632 { 2348 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12633 { 2348 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12634 { 2348 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12635 { 2348 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12636 { 2348 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 12637 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12638 { 2348 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12639 { 2348 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12640 { 2348 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12641 { 2348 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12642 { 2348 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12643 { 2348 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12644 { 2348 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 12645 { 2348 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12646 { 2348 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12647 { 2353 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 12648 { 2353 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12649 { 2353 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, }, 12650 { 2353 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 12651 { 2353 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12652 { 2353 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 12653 { 2353 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 12654 { 2353 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, }, 12655 { 2353 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12656 { 2353 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, }, 12657 { 2353 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 12658 { 2353 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12659 { 2353 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 12660 { 2353 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 12661 { 2353 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 12662 { 2353 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 12663 { 2353 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, }, 12664 { 2353 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 12665 { 2353 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12666 { 2353 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 12667 { 2353 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12668 { 2353 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12669 { 2353 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12670 { 2353 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12671 { 2353 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12672 { 2353 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12673 { 2353 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12674 { 2353 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12675 { 2353 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12676 { 2353 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12677 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 12678 { 2353 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 12679 { 2353 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 12680 { 2353 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 12681 { 2353 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 12682 { 2353 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 12683 { 2353 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12684 { 2353 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12685 { 2353 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 12686 { 2353 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 12687 { 2353 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12688 { 2353 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12689 { 2353 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12690 { 2353 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12691 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12692 { 2353 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 12693 { 2353 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12694 { 2353 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 12695 { 2353 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12696 { 2353 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 12697 { 2353 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12698 { 2353 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12699 { 2353 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12700 { 2353 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 12701 { 2353 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12702 { 2353 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12703 { 2353 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12704 { 2353 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12705 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 12706 { 2353 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 12707 { 2358 /* vld20 */, ARM::MVE_VLD20_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12708 { 2358 /* vld20 */, ARM::MVE_VLD20_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12709 { 2358 /* vld20 */, ARM::MVE_VLD20_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12710 { 2358 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12711 { 2358 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12712 { 2358 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12713 { 2364 /* vld21 */, ARM::MVE_VLD21_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12714 { 2364 /* vld21 */, ARM::MVE_VLD21_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12715 { 2364 /* vld21 */, ARM::MVE_VLD21_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 12716 { 2364 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12717 { 2364 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12718 { 2364 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12719 { 2370 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 12720 { 2370 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12721 { 2370 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 12722 { 2370 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 12723 { 2370 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 12724 { 2370 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 12725 { 2370 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 12726 { 2370 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12727 { 2370 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 12728 { 2370 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 12729 { 2370 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 12730 { 2370 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 12731 { 2370 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 12732 { 2370 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 12733 { 2370 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 12734 { 2370 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 12735 { 2370 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 12736 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12737 { 2370 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12738 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12739 { 2370 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12740 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12741 { 2370 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12742 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12743 { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12744 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12745 { 2370 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 12746 { 2370 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12747 { 2370 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12748 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12749 { 2370 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12750 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12751 { 2370 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12752 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12753 { 2370 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12754 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12755 { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12756 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12757 { 2370 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 12758 { 2370 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12759 { 2370 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12760 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12761 { 2370 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12762 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12763 { 2370 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 12764 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 12765 { 2370 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 12766 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12767 { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12768 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12769 { 2370 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 12770 { 2370 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12771 { 2370 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12772 { 2370 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12773 { 2370 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12774 { 2370 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12775 { 2370 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12776 { 2370 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12777 { 2370 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12778 { 2370 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12779 { 2370 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12780 { 2370 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12781 { 2370 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12782 { 2370 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12783 { 2370 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12784 { 2370 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12785 { 2370 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12786 { 2370 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12787 { 2370 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12788 { 2370 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12789 { 2370 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12790 { 2370 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12791 { 2370 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12792 { 2370 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12793 { 2370 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 12794 { 2375 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, }, 12795 { 2375 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12796 { 2375 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 12797 { 2375 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, }, 12798 { 2375 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 12799 { 2375 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 12800 { 2375 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, }, 12801 { 2375 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12802 { 2375 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 12803 { 2375 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, }, 12804 { 2375 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 12805 { 2375 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 12806 { 2375 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, }, 12807 { 2375 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 12808 { 2375 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 12809 { 2375 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, }, 12810 { 2375 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 12811 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 12812 { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 12813 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12814 { 2375 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12815 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12816 { 2375 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 12817 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 12818 { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 12819 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12820 { 2375 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12821 { 2375 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 12822 { 2375 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 12823 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 12824 { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 12825 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12826 { 2375 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12827 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12828 { 2375 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12829 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 12830 { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 12831 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12832 { 2375 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12833 { 2375 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 12834 { 2375 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 12835 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12836 { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12837 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12838 { 2375 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12839 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 12840 { 2375 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 12841 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12842 { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12843 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 12844 { 2375 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 12845 { 2375 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12846 { 2375 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12847 { 2375 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12848 { 2375 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12849 { 2375 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12850 { 2375 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 12851 { 2375 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12852 { 2375 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12853 { 2375 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12854 { 2375 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12855 { 2375 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12856 { 2375 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12857 { 2375 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12858 { 2375 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12859 { 2375 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12860 { 2375 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12861 { 2375 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12862 { 2375 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 12863 { 2375 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12864 { 2375 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12865 { 2375 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12866 { 2375 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12867 { 2375 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12868 { 2375 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 12869 { 2380 /* vld40 */, ARM::MVE_VLD40_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12870 { 2380 /* vld40 */, ARM::MVE_VLD40_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12871 { 2380 /* vld40 */, ARM::MVE_VLD40_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12872 { 2380 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12873 { 2380 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12874 { 2380 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12875 { 2386 /* vld41 */, ARM::MVE_VLD41_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12876 { 2386 /* vld41 */, ARM::MVE_VLD41_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12877 { 2386 /* vld41 */, ARM::MVE_VLD41_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12878 { 2386 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12879 { 2386 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12880 { 2386 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12881 { 2392 /* vld42 */, ARM::MVE_VLD42_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12882 { 2392 /* vld42 */, ARM::MVE_VLD42_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12883 { 2392 /* vld42 */, ARM::MVE_VLD42_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12884 { 2392 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12885 { 2392 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12886 { 2392 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12887 { 2398 /* vld43 */, ARM::MVE_VLD43_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12888 { 2398 /* vld43 */, ARM::MVE_VLD43_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12889 { 2398 /* vld43 */, ARM::MVE_VLD43_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 12890 { 2398 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12891 { 2398 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12892 { 2398 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 12893 { 2404 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 12894 { 2404 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 12895 { 2411 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 12896 { 2411 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 12897 { 2411 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 12898 { 2411 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 12899 { 2418 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset }, }, 12900 { 2418 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, }, 12901 { 2418 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, }, 12902 { 2418 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, }, 12903 { 2418 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, }, 12904 { 2418 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, }, 12905 { 2418 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 12906 { 2418 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 12907 { 2418 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 12908 { 2418 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 12909 { 2418 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 12910 { 2418 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12911 { 2418 /* vldr */, ARM::VLDR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12912 { 2418 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12913 { 2418 /* vldr */, ARM::VLDR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12914 { 2418 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12915 { 2418 /* vldr */, ARM::VLDR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12916 { 2418 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12917 { 2418 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12918 { 2418 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12919 { 2418 /* vldr */, ARM::VLDR_P0_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12920 { 2418 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 12921 { 2418 /* vldr */, ARM::VLDR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 12922 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12923 { 2423 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12924 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12925 { 2423 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12926 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12927 { 2423 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12928 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12929 { 2423 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12930 { 2423 /* vldrb */, ARM::MVE_VLDRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0Offset }, }, 12931 { 2423 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12932 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 12933 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12934 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 12935 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12936 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 12937 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12938 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 12939 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12940 { 2423 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, }, 12941 { 2423 /* vldrb */, ARM::MVE_VLDRBU8_post, Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemNoOffsetT2, MCK_Imm7Shift0 }, }, 12942 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset }, }, 12943 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12944 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS3Offset }, }, 12945 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, }, 12946 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12947 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 12948 { 2435 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 12949 { 2435 /* vldrh */, ARM::MVE_VLDRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1Offset }, }, 12950 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12951 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 12952 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12953 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 12954 { 2435 /* vldrh */, ARM::MVE_VLDRHU32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 12955 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 12956 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 12957 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, }, 12958 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_post, Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT2, MCK_Imm7Shift1 }, }, 12959 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 12960 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 12961 { 2441 /* vldrw */, ARM::MVE_VLDRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2Offset }, }, 12962 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset }, }, 12963 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12964 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS2Offset }, }, 12965 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, }, 12966 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_post, Convert__MemNoOffsetT21_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT2, MCK_Imm7Shift2 }, }, 12967 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, }, 12968 { 2447 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 12969 { 2453 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 12970 { 2459 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12971 { 2459 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12972 { 2459 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12973 { 2459 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12974 { 2459 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12975 { 2459 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12976 { 2459 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12977 { 2459 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12978 { 2459 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12979 { 2459 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12980 { 2459 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12981 { 2459 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12982 { 2459 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12983 { 2459 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12984 { 2459 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12985 { 2459 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12986 { 2459 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12987 { 2459 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12988 { 2459 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12989 { 2459 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12990 { 2459 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12991 { 2459 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12992 { 2459 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12993 { 2459 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12994 { 2459 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12995 { 2459 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12996 { 2459 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12997 { 2459 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12998 { 2459 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12999 { 2459 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13000 { 2459 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13001 { 2459 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13002 { 2459 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13003 { 2459 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13004 { 2459 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13005 { 2459 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13006 { 2459 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13007 { 2459 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13008 { 2464 /* vmaxa */, ARM::MVE_VMAXAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13009 { 2464 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13010 { 2464 /* vmaxa */, ARM::MVE_VMAXAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13011 { 2470 /* vmaxav */, ARM::MVE_VMAXAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13012 { 2470 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13013 { 2470 /* vmaxav */, ARM::MVE_VMAXAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13014 { 2477 /* vmaxnm */, ARM::NEON_VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13015 { 2477 /* vmaxnm */, ARM::NEON_VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13016 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13017 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13018 { 2477 /* vmaxnm */, ARM::NEON_VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13019 { 2477 /* vmaxnm */, ARM::NEON_VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13020 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13021 { 2477 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13022 { 2477 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13023 { 2484 /* vmaxnma */, ARM::MVE_VMAXNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 13024 { 2484 /* vmaxnma */, ARM::MVE_VMAXNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 13025 { 2492 /* vmaxnmav */, ARM::MVE_VMAXNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13026 { 2492 /* vmaxnmav */, ARM::MVE_VMAXNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13027 { 2501 /* vmaxnmv */, ARM::MVE_VMAXNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13028 { 2501 /* vmaxnmv */, ARM::MVE_VMAXNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13029 { 2509 /* vmaxv */, ARM::MVE_VMAXVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13030 { 2509 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13031 { 2509 /* vmaxv */, ARM::MVE_VMAXVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13032 { 2509 /* vmaxv */, ARM::MVE_VMAXVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, }, 13033 { 2509 /* vmaxv */, ARM::MVE_VMAXVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, }, 13034 { 2509 /* vmaxv */, ARM::MVE_VMAXVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, }, 13035 { 2515 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13036 { 2515 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13037 { 2515 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13038 { 2515 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13039 { 2515 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13040 { 2515 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13041 { 2515 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13042 { 2515 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13043 { 2515 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13044 { 2515 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13045 { 2515 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13046 { 2515 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13047 { 2515 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13048 { 2515 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13049 { 2515 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13050 { 2515 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13051 { 2515 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13052 { 2515 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13053 { 2515 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13054 { 2515 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13055 { 2515 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13056 { 2515 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13057 { 2515 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13058 { 2515 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13059 { 2515 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13060 { 2515 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13061 { 2515 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13062 { 2515 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13063 { 2515 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13064 { 2515 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13065 { 2515 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13066 { 2515 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13067 { 2515 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13068 { 2515 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13069 { 2515 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13070 { 2515 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13071 { 2515 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13072 { 2515 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13073 { 2520 /* vmina */, ARM::MVE_VMINAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13074 { 2520 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13075 { 2520 /* vmina */, ARM::MVE_VMINAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13076 { 2526 /* vminav */, ARM::MVE_VMINAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13077 { 2526 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13078 { 2526 /* vminav */, ARM::MVE_VMINAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13079 { 2533 /* vminnm */, ARM::NEON_VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13080 { 2533 /* vminnm */, ARM::NEON_VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13081 { 2533 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13082 { 2533 /* vminnm */, ARM::VFP_VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13083 { 2533 /* vminnm */, ARM::NEON_VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13084 { 2533 /* vminnm */, ARM::NEON_VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13085 { 2533 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13086 { 2533 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13087 { 2533 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13088 { 2540 /* vminnma */, ARM::MVE_VMINNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 13089 { 2540 /* vminnma */, ARM::MVE_VMINNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 13090 { 2548 /* vminnmav */, ARM::MVE_VMINNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13091 { 2548 /* vminnmav */, ARM::MVE_VMINNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13092 { 2557 /* vminnmv */, ARM::MVE_VMINNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13093 { 2557 /* vminnmv */, ARM::MVE_VMINNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13094 { 2565 /* vminv */, ARM::MVE_VMINVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13095 { 2565 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13096 { 2565 /* vminv */, ARM::MVE_VMINVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13097 { 2565 /* vminv */, ARM::MVE_VMINVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, }, 13098 { 2565 /* vminv */, ARM::MVE_VMINVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, }, 13099 { 2565 /* vminv */, ARM::MVE_VMINVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, }, 13100 { 2571 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13101 { 2571 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13102 { 2571 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13103 { 2571 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13104 { 2571 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13105 { 2571 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13106 { 2571 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13107 { 2571 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13108 { 2571 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13109 { 2571 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13110 { 2571 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13111 { 2571 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13112 { 2571 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13113 { 2571 /* vmla */, ARM::MVE_VMLA_qr_s16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13114 { 2571 /* vmla */, ARM::MVE_VMLA_qr_s32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13115 { 2571 /* vmla */, ARM::MVE_VMLA_qr_s8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13116 { 2571 /* vmla */, ARM::MVE_VMLA_qr_u16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13117 { 2571 /* vmla */, ARM::MVE_VMLA_qr_u32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13118 { 2571 /* vmla */, ARM::MVE_VMLA_qr_u8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13119 { 2571 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13120 { 2571 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13121 { 2571 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13122 { 2571 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13123 { 2571 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13124 { 2571 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13125 { 2571 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13126 { 2571 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13127 { 2576 /* vmladav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13128 { 2576 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13129 { 2576 /* vmladav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13130 { 2576 /* vmladav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13131 { 2576 /* vmladav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13132 { 2576 /* vmladav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13133 { 2584 /* vmladava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13134 { 2584 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13135 { 2584 /* vmladava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13136 { 2584 /* vmladava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13137 { 2584 /* vmladava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13138 { 2584 /* vmladava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13139 { 2593 /* vmladavax */, ARM::MVE_VMLADAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13140 { 2593 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13141 { 2593 /* vmladavax */, ARM::MVE_VMLADAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13142 { 2603 /* vmladavx */, ARM::MVE_VMLADAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13143 { 2603 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13144 { 2603 /* vmladavx */, ARM::MVE_VMLADAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13145 { 2612 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13146 { 2612 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13147 { 2612 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13148 { 2612 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13149 { 2612 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13150 { 2612 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13151 { 2612 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13152 { 2612 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13153 { 2612 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13154 { 2612 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13155 { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13156 { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13157 { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13158 { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13159 { 2627 /* vmlaldava */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13160 { 2627 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13161 { 2627 /* vmlaldava */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13162 { 2627 /* vmlaldava */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13163 { 2637 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13164 { 2637 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13165 { 2648 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13166 { 2648 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13167 { 2658 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13168 { 2658 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13169 { 2658 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13170 { 2658 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13171 { 2665 /* vmlalva */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13172 { 2665 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13173 { 2665 /* vmlalva */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13174 { 2665 /* vmlalva */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13175 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_s16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13176 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_s32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13177 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_s8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13178 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_u16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13179 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_u32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13180 { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_u8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13181 { 2679 /* vmlav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13182 { 2679 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13183 { 2679 /* vmlav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13184 { 2679 /* vmlav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13185 { 2679 /* vmlav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13186 { 2679 /* vmlav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13187 { 2685 /* vmlava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13188 { 2685 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13189 { 2685 /* vmlava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13190 { 2685 /* vmlava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13191 { 2685 /* vmlava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13192 { 2685 /* vmlava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13193 { 2692 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13194 { 2692 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13195 { 2692 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13196 { 2692 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13197 { 2692 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13198 { 2692 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13199 { 2692 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13200 { 2692 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13201 { 2692 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13202 { 2692 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13203 { 2692 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13204 { 2692 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13205 { 2692 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13206 { 2692 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13207 { 2692 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13208 { 2692 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13209 { 2692 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13210 { 2692 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13211 { 2692 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13212 { 2692 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13213 { 2692 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13214 { 2697 /* vmlsdav */, ARM::MVE_VMLSDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13215 { 2697 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13216 { 2697 /* vmlsdav */, ARM::MVE_VMLSDAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13217 { 2705 /* vmlsdava */, ARM::MVE_VMLSDAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13218 { 2705 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13219 { 2705 /* vmlsdava */, ARM::MVE_VMLSDAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13220 { 2714 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13221 { 2714 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13222 { 2714 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13223 { 2724 /* vmlsdavx */, ARM::MVE_VMLSDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13224 { 2724 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13225 { 2724 /* vmlsdavx */, ARM::MVE_VMLSDAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13226 { 2733 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13227 { 2733 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13228 { 2733 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13229 { 2733 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13230 { 2733 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13231 { 2733 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13232 { 2733 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13233 { 2733 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13234 { 2733 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13235 { 2733 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13236 { 2739 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13237 { 2739 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13238 { 2748 /* vmlsldava */, ARM::MVE_VMLSLDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13239 { 2748 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13240 { 2758 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13241 { 2758 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13242 { 2769 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13243 { 2769 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13244 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, }, 13245 { 2779 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 13246 { 2779 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 13247 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, }, 13248 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 13249 { 2779 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, }, 13250 { 2779 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, }, 13251 { 2779 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, }, 13252 { 2779 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, }, 13253 { 2779 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, }, 13254 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 13255 { 2779 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, }, 13256 { 2779 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs64, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 13257 { 2779 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, }, 13258 { 2779 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, }, 13259 { 2779 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 13260 { 2779 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, }, 13261 { 2779 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 13262 { 2779 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, }, 13263 { 2779 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 13264 { 2779 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 13265 { 2779 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 13266 { 2779 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, }, 13267 { 2779 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 13268 { 2779 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 13269 { 2779 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 13270 { 2779 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, }, 13271 { 2779 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 13272 { 2779 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 13273 { 2779 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, }, 13274 { 2779 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, }, 13275 { 2779 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 13276 { 2779 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 13277 { 2779 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, }, 13278 { 2779 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, }, 13279 { 2779 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, }, 13280 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, }, 13281 { 2779 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 13282 { 2779 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 13283 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, }, 13284 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, }, 13285 { 2779 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 13286 { 2779 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 13287 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, }, 13288 { 2779 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 13289 { 2779 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 13290 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, }, 13291 { 2779 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 13292 { 2779 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 13293 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, }, 13294 { 2779 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, }, 13295 { 2779 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, }, 13296 { 2779 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, }, 13297 { 2779 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, }, 13298 { 2779 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, }, 13299 { 2779 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, }, 13300 { 2779 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 13301 { 2779 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, }, 13302 { 2779 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, }, 13303 { 2779 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, }, 13304 { 2779 /* vmov */, ARM::MVE_VMOV_from_lane_s16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, }, 13305 { 2779 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 13306 { 2779 /* vmov */, ARM::MVE_VMOV_from_lane_s8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, }, 13307 { 2779 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 13308 { 2779 /* vmov */, ARM::MVE_VMOV_from_lane_u16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, }, 13309 { 2779 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 13310 { 2779 /* vmov */, ARM::MVE_VMOV_from_lane_u8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, }, 13311 { 2779 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 13312 { 2779 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, }, 13313 { 2779 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, }, 13314 { 2779 /* vmov */, ARM::MVE_VMOV_to_lane_16, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_16, MCK_MQPR, MCK_MVEVectorIndex8, MCK_rGPR }, }, 13315 { 2779 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, }, 13316 { 2779 /* vmov */, ARM::MVE_VMOV_to_lane_32, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_MQPR, MCK_MVEVectorIndex4, MCK_rGPR }, }, 13317 { 2779 /* vmov */, ARM::MVE_VMOV_from_lane_32, Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex4 }, }, 13318 { 2779 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, }, 13319 { 2779 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, }, 13320 { 2779 /* vmov */, ARM::MVE_VMOV_to_lane_8, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_8, MCK_MQPR, MCK_MVEVectorIndex16, MCK_rGPR }, }, 13321 { 2779 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, }, 13322 { 2779 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, }, 13323 { 2779 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, }, 13324 { 2779 /* vmov */, ARM::MVE_VMOV_q_rr, Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0, MCK_rGPR, MCK_rGPR }, }, 13325 { 2779 /* vmov */, ARM::MVE_VMOV_rr_q, ConvertCustom_cvtMVEVMOVQtoDReg, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0 }, }, 13326 { 2784 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 13327 { 2784 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 13328 { 2784 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 13329 { 2784 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 13330 { 2784 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 13331 { 2784 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 13332 { 2790 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13333 { 2790 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13334 { 2790 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13335 { 2790 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, }, 13336 { 2797 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13337 { 2797 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13338 { 2797 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13339 { 2797 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, }, 13340 { 2804 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, }, 13341 { 2804 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, }, 13342 { 2804 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, }, 13343 { 2810 /* vmovnb */, ARM::MVE_VMOVNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 13344 { 2810 /* vmovnb */, ARM::MVE_VMOVNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 13345 { 2817 /* vmovnt */, ARM::MVE_VMOVNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 13346 { 2817 /* vmovnt */, ARM::MVE_VMOVNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 13347 { 2824 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13348 { 2830 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, }, 13349 { 2830 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, }, 13350 { 2830 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, }, 13351 { 2830 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, }, 13352 { 2830 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, }, 13353 { 2830 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, }, 13354 { 2830 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, }, 13355 { 2830 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, }, 13356 { 2830 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, }, 13357 { 2830 /* vmrs */, ARM::VMRS_FPCXTNS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTNS }, }, 13358 { 2830 /* vmrs */, ARM::VMRS_FPCXTS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTS }, }, 13359 { 2830 /* vmrs */, ARM::VMRS_FPSCR_NZCVQC, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_FPSCR_NZCVQC }, }, 13360 { 2830 /* vmrs */, ARM::VMRS_P0, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_P0 }, }, 13361 { 2830 /* vmrs */, ARM::VMRS_VPR, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_VCCR }, }, 13362 { 2835 /* vmsr */, ARM::VMSR_FPCXTNS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_GPR }, }, 13363 { 2835 /* vmsr */, ARM::VMSR_FPCXTS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_GPR }, }, 13364 { 2835 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, }, 13365 { 2835 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, }, 13366 { 2835 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, }, 13367 { 2835 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, }, 13368 { 2835 /* vmsr */, ARM::VMSR_FPSCR_NZCVQC, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_GPR }, }, 13369 { 2835 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, }, 13370 { 2835 /* vmsr */, ARM::VMSR_P0, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_GPR }, }, 13371 { 2835 /* vmsr */, ARM::VMSR_VPR, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_GPR }, }, 13372 { 2840 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13373 { 2840 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13374 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 13375 { 2840 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 13376 { 2840 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 13377 { 2840 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 13378 { 2840 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 13379 { 2840 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 13380 { 2840 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 13381 { 2840 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 13382 { 2840 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, }, 13383 { 2840 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, }, 13384 { 2840 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13385 { 2840 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13386 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13387 { 2840 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13388 { 2840 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13389 { 2840 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13390 { 2840 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13391 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13392 { 2840 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13393 { 2840 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13394 { 2840 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13395 { 2840 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13396 { 2840 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13397 { 2840 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13398 { 2840 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13399 { 2840 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13400 { 2840 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13401 { 2840 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13402 { 2840 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13403 { 2840 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13404 { 2840 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13405 { 2840 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13406 { 2840 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13407 { 2840 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13408 { 2840 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13409 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13410 { 2840 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13411 { 2840 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13412 { 2840 /* vmul */, ARM::MVE_VMULi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13413 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13414 { 2840 /* vmul */, ARM::MVE_VMULi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13415 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13416 { 2840 /* vmul */, ARM::MVE_VMULi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13417 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13418 { 2840 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13419 { 2840 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13420 { 2840 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13421 { 2840 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13422 { 2840 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13423 { 2840 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13424 { 2840 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13425 { 2840 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13426 { 2840 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13427 { 2840 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13428 { 2845 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13429 { 2845 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13430 { 2845 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13431 { 2845 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13432 { 2845 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13433 { 2845 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13434 { 2851 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasCrypto, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13435 { 2851 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13436 { 2851 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13437 { 2851 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13438 { 2851 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13439 { 2851 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13440 { 2851 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13441 { 2851 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13442 { 2851 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13443 { 2851 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13444 { 2851 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13445 { 2851 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13446 { 2857 /* vmullb */, ARM::MVE_VMULLBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13447 { 2857 /* vmullb */, ARM::MVE_VMULLBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13448 { 2857 /* vmullb */, ARM::MVE_VMULLBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13449 { 2857 /* vmullb */, ARM::MVE_VMULLBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13450 { 2857 /* vmullb */, ARM::MVE_VMULLBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13451 { 2857 /* vmullb */, ARM::MVE_VMULLBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13452 { 2857 /* vmullb */, ARM::MVE_VMULLBp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13453 { 2857 /* vmullb */, ARM::MVE_VMULLBp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13454 { 2864 /* vmullt */, ARM::MVE_VMULLTs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13455 { 2864 /* vmullt */, ARM::MVE_VMULLTs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13456 { 2864 /* vmullt */, ARM::MVE_VMULLTs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13457 { 2864 /* vmullt */, ARM::MVE_VMULLTu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13458 { 2864 /* vmullt */, ARM::MVE_VMULLTu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13459 { 2864 /* vmullt */, ARM::MVE_VMULLTu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13460 { 2864 /* vmullt */, ARM::MVE_VMULLTp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13461 { 2864 /* vmullt */, ARM::MVE_VMULLTp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13462 { 2871 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 13463 { 2871 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 13464 { 2871 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, }, 13465 { 2871 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, }, 13466 { 2871 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 13467 { 2871 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, }, 13468 { 2871 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 13469 { 2871 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, }, 13470 { 2871 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 13471 { 2871 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 13472 { 2871 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 13473 { 2871 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, }, 13474 { 2871 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 13475 { 2871 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 13476 { 2871 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 13477 { 2871 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, }, 13478 { 2871 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 13479 { 2871 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 13480 { 2871 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, }, 13481 { 2871 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 13482 { 2871 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 13483 { 2871 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 13484 { 2871 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 13485 { 2871 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 13486 { 2871 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 13487 { 2871 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 13488 { 2871 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 13489 { 2871 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 13490 { 2871 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 13491 { 2871 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 13492 { 2871 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, }, 13493 { 2876 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13494 { 2876 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13495 { 2876 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13496 { 2876 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13497 { 2876 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13498 { 2876 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13499 { 2876 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13500 { 2876 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13501 { 2876 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 13502 { 2876 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 13503 { 2876 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13504 { 2876 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13505 { 2876 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13506 { 2876 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13507 { 2876 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13508 { 2876 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13509 { 2876 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 13510 { 2876 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 13511 { 2881 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13512 { 2881 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13513 { 2881 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13514 { 2887 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13515 { 2887 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13516 { 2887 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13517 { 2893 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13518 { 2893 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13519 { 2893 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13520 { 2899 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13521 { 2899 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13522 { 2899 /* vorn */, ARM::MVE_VORNIZ0v8i16, Convert__Reg1_2__imm_95_0__InvertedExpandImm0_161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_InvertedExpandImm0_16 }, }, 13523 { 2899 /* vorn */, ARM::MVE_VORNIZ8v8i16, Convert__Reg1_2__imm_95_0__InvertedExpandImm8_161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_InvertedExpandImm8_16 }, }, 13524 { 2899 /* vorn */, ARM::MVE_VORNIZ0v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm0_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm0_32 }, }, 13525 { 2899 /* vorn */, ARM::MVE_VORNIZ8v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm8_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm8_32 }, }, 13526 { 2899 /* vorn */, ARM::MVE_VORNIZ16v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm16_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm16_32 }, }, 13527 { 2899 /* vorn */, ARM::MVE_VORNIZ24v4i32, Convert__Reg1_2__imm_95_0__InvertedExpandImm24_321_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_InvertedExpandImm24_32 }, }, 13528 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13529 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13530 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13531 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13532 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13533 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13534 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13535 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13536 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13537 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13538 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13539 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13540 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 13541 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 13542 { 2904 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 13543 { 2904 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 13544 { 2904 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 13545 { 2904 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 13546 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 13547 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 13548 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 13549 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 13550 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 13551 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 13552 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 13553 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 13554 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13555 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13556 { 2904 /* vorr */, ARM::MVE_VORRIZ0v8i16, Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_ExpandImm0 }, }, 13557 { 2904 /* vorr */, ARM::MVE_VORRIZ8v8i16, Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_ExpandImm8 }, }, 13558 { 2904 /* vorr */, ARM::MVE_VORRIZ0v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm01_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm0 }, }, 13559 { 2904 /* vorr */, ARM::MVE_VORRIZ8v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm81_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm8 }, }, 13560 { 2904 /* vorr */, ARM::MVE_VORRIZ16v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm161_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm16 }, }, 13561 { 2904 /* vorr */, ARM::MVE_VORRIZ24v4i32, Convert__Reg1_2__Tie0_1_1__ExpandImm241_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_ExpandImm24 }, }, 13562 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13563 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13564 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13565 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13566 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13567 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13568 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13569 { 2904 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13570 { 2904 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13571 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13572 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13573 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13574 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13575 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13576 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13577 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13578 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13579 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13580 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13581 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13582 { 2909 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13583 { 2909 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13584 { 2909 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13585 { 2909 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13586 { 2909 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13587 { 2909 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13588 { 2909 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13589 { 2909 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13590 { 2909 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13591 { 2909 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13592 { 2909 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13593 { 2909 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13594 { 2916 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13595 { 2916 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 13596 { 2916 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 13597 { 2916 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 13598 { 2916 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13599 { 2916 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13600 { 2916 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13601 { 2916 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13602 { 2916 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13603 { 2916 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13604 { 2922 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13605 { 2922 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13606 { 2922 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13607 { 2922 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13608 { 2922 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13609 { 2922 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13610 { 2922 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13611 { 2922 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13612 { 2922 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13613 { 2922 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13614 { 2922 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13615 { 2922 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13616 { 2929 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13617 { 2929 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13618 { 2929 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13619 { 2929 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13620 { 2929 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13621 { 2929 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13622 { 2929 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13623 { 2929 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13624 { 2929 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13625 { 2929 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13626 { 2929 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13627 { 2929 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13628 { 2929 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13629 { 2929 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13630 { 2929 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13631 { 2929 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13632 { 2935 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13633 { 2935 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13634 { 2935 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13635 { 2935 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13636 { 2935 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13637 { 2935 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13638 { 2935 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13639 { 2935 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13640 { 2935 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13641 { 2935 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13642 { 2935 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13643 { 2935 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13644 { 2935 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13645 { 2935 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13646 { 2935 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13647 { 2935 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13648 { 2941 /* vpnot */, ARM::MVE_VPNOT, Convert__imm_95_0__imm_95_0__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN }, }, 13649 { 2947 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, }, 13650 { 2947 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, }, 13651 { 2947 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 13652 { 2947 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 13653 { 2947 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 13654 { 2947 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 13655 { 2947 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 13656 { 2947 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 13657 { 2947 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 13658 { 2947 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 13659 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13660 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13661 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13662 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13663 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13664 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13665 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13666 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13667 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13668 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13669 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13670 { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13671 { 2958 /* vpst */, ARM::MVE_VPST, Convert__ITMask1_0, AMFBS_HasMVEInt, { MCK_ITMask }, }, 13672 { 2963 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13673 { 2963 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13674 { 2963 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13675 { 2963 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13676 { 2963 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13677 { 2963 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13678 { 2963 /* vpt */, ARM::MVE_VPTv8u16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 13679 { 2963 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13680 { 2963 /* vpt */, ARM::MVE_VPTv4u32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 13681 { 2963 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13682 { 2963 /* vpt */, ARM::MVE_VPTv16u8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 13683 { 2963 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13684 { 2963 /* vpt */, ARM::MVE_VPTv4f32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 13685 { 2963 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 13686 { 2963 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13687 { 2963 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13688 { 2963 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13689 { 2963 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13690 { 2963 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13691 { 2963 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13692 { 2963 /* vpt */, ARM::MVE_VPTv8f16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 13693 { 2963 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 13694 { 2967 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, }, 13695 { 2967 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, }, 13696 { 2967 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 13697 { 2967 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 13698 { 2967 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 13699 { 2967 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 13700 { 2967 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 13701 { 2967 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 13702 { 2967 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 13703 { 2967 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 13704 { 2973 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13705 { 2973 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13706 { 2973 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13707 { 2973 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13708 { 2973 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13709 { 2973 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13710 { 2973 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13711 { 2973 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13712 { 2973 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13713 { 2979 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13714 { 2979 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13715 { 2979 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13716 { 2979 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13717 { 2979 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 13718 { 2979 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 13719 { 2979 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13720 { 2979 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13721 { 2979 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13722 { 2979 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13723 { 2979 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13724 { 2979 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13725 { 2979 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 13726 { 2979 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 13727 { 2979 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13728 { 2979 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13729 { 2979 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13730 { 2979 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13731 { 2979 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13732 { 2979 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13733 { 2979 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13734 { 2979 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13735 { 2979 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13736 { 2979 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13737 { 2979 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13738 { 2979 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13739 { 2979 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13740 { 2979 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13741 { 2979 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13742 { 2979 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13743 { 2979 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13744 { 2979 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13745 { 2979 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13746 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13747 { 2979 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13748 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13749 { 2979 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13750 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13751 { 2979 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13752 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13753 { 2979 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13754 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13755 { 2979 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13756 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13757 { 2985 /* vqdmladh */, ARM::MVE_VQDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13758 { 2985 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13759 { 2985 /* vqdmladh */, ARM::MVE_VQDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13760 { 2994 /* vqdmladhx */, ARM::MVE_VQDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13761 { 2994 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13762 { 2994 /* vqdmladhx */, ARM::MVE_VQDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13763 { 3004 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13764 { 3004 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13765 { 3004 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13766 { 3012 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13767 { 3012 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13768 { 3012 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13769 { 3012 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13770 { 3020 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13771 { 3020 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13772 { 3020 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13773 { 3029 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13774 { 3029 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13775 { 3029 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13776 { 3038 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13777 { 3038 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13778 { 3038 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13779 { 3048 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13780 { 3048 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13781 { 3048 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13782 { 3048 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13783 { 3056 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13784 { 3056 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13785 { 3056 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13786 { 3056 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13787 { 3056 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13788 { 3056 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13789 { 3056 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13790 { 3056 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13791 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13792 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13793 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13794 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13795 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13796 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13797 { 3056 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13798 { 3056 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13799 { 3056 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13800 { 3056 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13801 { 3064 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13802 { 3064 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13803 { 3064 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13804 { 3064 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13805 { 3072 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13806 { 3072 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13807 { 3072 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13808 { 3072 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13809 { 3081 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13810 { 3081 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13811 { 3081 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13812 { 3081 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13813 { 3090 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 13814 { 3090 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 13815 { 3090 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 13816 { 3090 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, }, 13817 { 3090 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, }, 13818 { 3090 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, }, 13819 { 3097 /* vqmovnb */, ARM::MVE_VQMOVNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13820 { 3097 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13821 { 3097 /* vqmovnb */, ARM::MVE_VQMOVNu16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13822 { 3097 /* vqmovnb */, ARM::MVE_VQMOVNu32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 13823 { 3105 /* vqmovnt */, ARM::MVE_VQMOVNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13824 { 3105 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13825 { 3105 /* vqmovnt */, ARM::MVE_VQMOVNu16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13826 { 3105 /* vqmovnt */, ARM::MVE_VQMOVNu32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 13827 { 3113 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 13828 { 3113 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 13829 { 3113 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 13830 { 3121 /* vqmovunb */, ARM::MVE_VQMOVUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13831 { 3121 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13832 { 3130 /* vqmovunt */, ARM::MVE_VQMOVUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13833 { 3130 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13834 { 3139 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13835 { 3139 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13836 { 3139 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13837 { 3139 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13838 { 3139 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13839 { 3139 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13840 { 3139 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13841 { 3139 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13842 { 3139 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13843 { 3145 /* vqrdmladh */, ARM::MVE_VQRDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13844 { 3145 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13845 { 3145 /* vqrdmladh */, ARM::MVE_VQRDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13846 { 3155 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13847 { 3155 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13848 { 3155 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13849 { 3166 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13850 { 3166 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13851 { 3166 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13852 { 3166 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13853 { 3166 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13854 { 3166 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13855 { 3166 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13856 { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13857 { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13858 { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13859 { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13860 { 3175 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13861 { 3175 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13862 { 3175 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13863 { 3185 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13864 { 3185 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13865 { 3185 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13866 { 3195 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13867 { 3195 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13868 { 3195 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13869 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13870 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13871 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13872 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13873 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13874 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13875 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13876 { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13877 { 3215 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13878 { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13879 { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13880 { 3215 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13881 { 3215 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13882 { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13883 { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13884 { 3215 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13885 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13886 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13887 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13888 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13889 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13890 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13891 { 3215 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13892 { 3215 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13893 { 3215 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13894 { 3215 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13895 { 3224 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13896 { 3224 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13897 { 3224 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13898 { 3224 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13899 { 3224 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 13900 { 3224 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 13901 { 3224 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13902 { 3224 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13903 { 3224 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13904 { 3224 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13905 { 3224 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13906 { 3224 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13907 { 3224 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 13908 { 3224 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 13909 { 3224 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13910 { 3224 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13911 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 13912 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 13913 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 13914 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 13915 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 13916 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 13917 { 3224 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13918 { 3224 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13919 { 3224 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13920 { 3224 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13921 { 3224 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13922 { 3224 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13923 { 3224 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13924 { 3224 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13925 { 3224 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13926 { 3224 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13927 { 3224 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13928 { 3224 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13929 { 3224 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13930 { 3224 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13931 { 3224 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13932 { 3224 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13933 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13934 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13935 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13936 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13937 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13938 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13939 { 3231 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 13940 { 3231 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 13941 { 3231 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 13942 { 3231 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 13943 { 3231 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 13944 { 3231 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 13945 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13946 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13947 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13948 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13949 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13950 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13951 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13952 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13953 { 3257 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 13954 { 3257 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 13955 { 3257 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 13956 { 3266 /* vqrshrunb */, ARM::MVE_VQRSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13957 { 3266 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13958 { 3276 /* vqrshrunt */, ARM::MVE_VQRSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 13959 { 3276 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13960 { 3286 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13961 { 3286 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 13962 { 3286 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13963 { 3286 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 13964 { 3286 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13965 { 3286 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 13966 { 3286 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13967 { 3286 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 13968 { 3286 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 13969 { 3286 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 13970 { 3286 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 13971 { 3286 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 13972 { 3286 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13973 { 3286 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 13974 { 3286 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13975 { 3286 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 13976 { 3286 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13977 { 3286 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, }, 13978 { 3286 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13979 { 3286 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, }, 13980 { 3286 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13981 { 3286 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, }, 13982 { 3286 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13983 { 3286 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, }, 13984 { 3286 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 13985 { 3286 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, }, 13986 { 3286 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 13987 { 3286 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, }, 13988 { 3286 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13989 { 3286 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, }, 13990 { 3286 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13991 { 3286 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, }, 13992 { 3286 /* vqshl */, ARM::MVE_VQSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 13993 { 3286 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 13994 { 3286 /* vqshl */, ARM::MVE_VQSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 13995 { 3286 /* vqshl */, ARM::MVE_VQSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 13996 { 3286 /* vqshl */, ARM::MVE_VQSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 13997 { 3286 /* vqshl */, ARM::MVE_VQSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 13998 { 3286 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13999 { 3286 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14000 { 3286 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14001 { 3286 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14002 { 3286 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14003 { 3286 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14004 { 3286 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14005 { 3286 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14006 { 3286 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14007 { 3286 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14008 { 3286 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14009 { 3286 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14010 { 3286 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14011 { 3286 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14012 { 3286 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14013 { 3286 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14014 { 3286 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14015 { 3286 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14016 { 3286 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14017 { 3286 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14018 { 3286 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14019 { 3286 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14020 { 3286 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14021 { 3286 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14022 { 3286 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14023 { 3286 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14024 { 3286 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14025 { 3286 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14026 { 3286 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14027 { 3286 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14028 { 3286 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14029 { 3286 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14030 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14031 { 3286 /* vqshl */, ARM::MVE_VQSHLimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14032 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14033 { 3286 /* vqshl */, ARM::MVE_VQSHLimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14034 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14035 { 3286 /* vqshl */, ARM::MVE_VQSHLimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14036 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14037 { 3286 /* vqshl */, ARM::MVE_VQSHLimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14038 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14039 { 3286 /* vqshl */, ARM::MVE_VQSHLimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14040 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14041 { 3286 /* vqshl */, ARM::MVE_VQSHLimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14042 { 3292 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 14043 { 3292 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 14044 { 3292 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 14045 { 3292 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 14046 { 3292 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 14047 { 3292 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 14048 { 3292 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 14049 { 3292 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 14050 { 3292 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14051 { 3292 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14052 { 3292 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14053 { 3292 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14054 { 3292 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14055 { 3292 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14056 { 3292 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14057 { 3292 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14058 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14059 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14060 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14061 { 3299 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14062 { 3299 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14063 { 3299 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14064 { 3299 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14065 { 3299 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14066 { 3299 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14067 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14068 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14069 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14070 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14071 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14072 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14073 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14074 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14075 { 3322 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14076 { 3322 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14077 { 3322 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14078 { 3330 /* vqshrunb */, ARM::MVE_VQSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14079 { 3330 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14080 { 3339 /* vqshrunt */, ARM::MVE_VQSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14081 { 3339 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14082 { 3348 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14083 { 3348 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14084 { 3348 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14085 { 3348 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14086 { 3348 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14087 { 3348 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14088 { 3348 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14089 { 3348 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14090 { 3348 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14091 { 3348 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14092 { 3348 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14093 { 3348 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14094 { 3348 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14095 { 3348 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14096 { 3348 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14097 { 3348 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14098 { 3348 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14099 { 3348 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14100 { 3348 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14101 { 3348 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14102 { 3348 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14103 { 3348 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14104 { 3348 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14105 { 3348 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14106 { 3348 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14107 { 3348 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14108 { 3348 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14109 { 3348 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14110 { 3348 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14111 { 3348 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14112 { 3348 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14113 { 3348 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14114 { 3348 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14115 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14116 { 3348 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14117 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14118 { 3348 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14119 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14120 { 3348 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14121 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14122 { 3348 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14123 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14124 { 3348 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14125 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14126 { 3354 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14127 { 3354 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14128 { 3354 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14129 { 3362 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14130 { 3362 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14131 { 3362 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14132 { 3362 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14133 { 3362 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14134 { 3362 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14135 { 3369 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14136 { 3369 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14137 { 3369 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14138 { 3369 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14139 { 3369 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14140 { 3369 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14141 { 3369 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14142 { 3369 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14143 { 3376 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14144 { 3376 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14145 { 3376 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14146 { 3383 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14147 { 3383 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14148 { 3383 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14149 { 3383 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14150 { 3383 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, }, 14151 { 3383 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14152 { 3390 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14153 { 3390 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14154 { 3390 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 14155 { 3390 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 14156 { 3390 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14157 { 3390 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14158 { 3390 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, }, 14159 { 3390 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, }, 14160 { 3390 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14161 { 3397 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14162 { 3397 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14163 { 3397 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14164 { 3397 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14165 { 3397 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14166 { 3397 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14167 { 3397 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14168 { 3397 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14169 { 3397 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14170 { 3397 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14171 { 3397 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14172 { 3397 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14173 { 3397 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14174 { 3397 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14175 { 3397 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14176 { 3397 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14177 { 3397 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14178 { 3397 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14179 { 3397 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14180 { 3397 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14181 { 3397 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14182 { 3397 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14183 { 3397 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14184 { 3397 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14185 { 3397 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14186 { 3397 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14187 { 3397 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14188 { 3397 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14189 { 3397 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14190 { 3397 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14191 { 3404 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14192 { 3404 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14193 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14194 { 3404 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14195 { 3404 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14196 { 3404 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14197 { 3404 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14198 { 3404 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14199 { 3404 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14200 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14201 { 3404 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14202 { 3404 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14203 { 3404 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14204 { 3404 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14205 { 3404 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14206 { 3411 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14207 { 3411 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14208 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14209 { 3411 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14210 { 3411 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14211 { 3411 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14212 { 3411 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14213 { 3411 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14214 { 3411 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14215 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14216 { 3411 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14217 { 3411 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14218 { 3411 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14219 { 3411 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14220 { 3411 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14221 { 3418 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14222 { 3418 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14223 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14224 { 3418 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14225 { 3418 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14226 { 3418 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14227 { 3418 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14228 { 3418 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14229 { 3418 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14230 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14231 { 3418 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14232 { 3418 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14233 { 3418 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14234 { 3418 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14235 { 3418 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14236 { 3425 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14237 { 3425 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14238 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14239 { 3425 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14240 { 3425 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14241 { 3425 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14242 { 3425 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14243 { 3425 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14244 { 3425 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14245 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14246 { 3425 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14247 { 3425 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14248 { 3425 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14249 { 3425 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14250 { 3425 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14251 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14252 { 3432 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14253 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14254 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14255 { 3432 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14256 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14257 { 3439 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14258 { 3439 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14259 { 3439 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14260 { 3439 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14261 { 3439 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14262 { 3439 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14263 { 3439 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14264 { 3439 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14265 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14266 { 3439 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14267 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14268 { 3439 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14269 { 3439 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14270 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14271 { 3439 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14272 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14273 { 3446 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14274 { 3446 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14275 { 3446 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14276 { 3446 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14277 { 3446 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14278 { 3446 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14279 { 3446 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14280 { 3446 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14281 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14282 { 3446 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14283 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14284 { 3446 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14285 { 3446 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14286 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14287 { 3446 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14288 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14289 { 3453 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14290 { 3453 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14291 { 3464 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14292 { 3464 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14293 { 3476 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14294 { 3489 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14295 { 3501 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14296 { 3501 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14297 { 3510 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14298 { 3510 /* vrmlalvha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14299 { 3520 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14300 { 3531 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14301 { 3543 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14302 { 3556 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14303 { 3568 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14304 { 3568 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14305 { 3568 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14306 { 3568 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14307 { 3568 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14308 { 3568 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14309 { 3575 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14310 { 3575 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14311 { 3575 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14312 { 3575 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14313 { 3575 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14314 { 3575 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14315 { 3575 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14316 { 3575 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14317 { 3575 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14318 { 3575 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14319 { 3575 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14320 { 3575 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14321 { 3575 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14322 { 3575 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14323 { 3575 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14324 { 3575 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14325 { 3575 /* vrshl */, ARM::MVE_VRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 14326 { 3575 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 14327 { 3575 /* vrshl */, ARM::MVE_VRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 14328 { 3575 /* vrshl */, ARM::MVE_VRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 14329 { 3575 /* vrshl */, ARM::MVE_VRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 14330 { 3575 /* vrshl */, ARM::MVE_VRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 14331 { 3575 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14332 { 3575 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14333 { 3575 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14334 { 3575 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14335 { 3575 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14336 { 3575 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14337 { 3575 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14338 { 3575 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14339 { 3575 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14340 { 3575 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14341 { 3575 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14342 { 3575 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14343 { 3575 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14344 { 3575 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14345 { 3575 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14346 { 3575 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14347 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14348 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14349 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14350 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14351 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14352 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14353 { 3581 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14354 { 3581 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14355 { 3581 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 14356 { 3581 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 14357 { 3581 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 14358 { 3581 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 14359 { 3581 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 14360 { 3581 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 14361 { 3581 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 14362 { 3581 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 14363 { 3581 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 14364 { 3581 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 14365 { 3581 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 14366 { 3581 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 14367 { 3581 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 14368 { 3581 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 14369 { 3581 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14370 { 3581 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14371 { 3581 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14372 { 3581 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14373 { 3581 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14374 { 3581 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14375 { 3581 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14376 { 3581 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14377 { 3581 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14378 { 3581 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14379 { 3581 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14380 { 3581 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14381 { 3581 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14382 { 3581 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14383 { 3581 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14384 { 3581 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14385 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14386 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14387 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14388 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14389 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14390 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14391 { 3587 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14392 { 3587 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14393 { 3587 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14394 { 3594 /* vrshrnb */, ARM::MVE_VRSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14395 { 3594 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14396 { 3602 /* vrshrnt */, ARM::MVE_VRSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14397 { 3602 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14398 { 3610 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14399 { 3610 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14400 { 3610 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14401 { 3610 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14402 { 3610 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14403 { 3610 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14404 { 3618 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14405 { 3618 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14406 { 3618 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14407 { 3618 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14408 { 3618 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14409 { 3618 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14410 { 3618 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14411 { 3618 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14412 { 3626 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14413 { 3626 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14414 { 3626 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 14415 { 3626 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 14416 { 3626 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 14417 { 3626 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 14418 { 3626 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 14419 { 3626 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 14420 { 3626 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 14421 { 3626 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 14422 { 3626 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 14423 { 3626 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 14424 { 3626 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 14425 { 3626 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 14426 { 3626 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 14427 { 3626 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 14428 { 3626 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14429 { 3626 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14430 { 3626 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14431 { 3626 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14432 { 3626 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14433 { 3626 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14434 { 3626 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14435 { 3626 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14436 { 3626 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14437 { 3626 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14438 { 3626 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14439 { 3626 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14440 { 3626 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14441 { 3626 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14442 { 3626 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14443 { 3626 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14444 { 3632 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14445 { 3632 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14446 { 3632 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14447 { 3640 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14448 { 3645 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14449 { 3651 /* vscclrm */, ARM::VSCCLRMD, Convert__CondCode2_0__FPDRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPDRegListWithVPR }, }, 14450 { 3651 /* vscclrm */, ARM::VSCCLRMS, Convert__CondCode2_0__FPSRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPSRegListWithVPR }, }, 14451 { 3659 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14452 { 3659 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14453 { 3659 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14454 { 3659 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14455 { 3665 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14456 { 3665 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14457 { 3665 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14458 { 3672 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14459 { 3672 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14460 { 3672 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14461 { 3679 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14462 { 3679 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14463 { 3679 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14464 { 3686 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14465 { 3686 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14466 { 3686 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14467 { 3693 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14468 { 3693 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14469 { 3693 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14470 { 3693 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14471 { 3693 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14472 { 3693 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14473 { 3693 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14474 { 3693 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14475 { 3693 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14476 { 3693 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14477 { 3693 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14478 { 3693 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14479 { 3693 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14480 { 3693 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14481 { 3693 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14482 { 3693 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14483 { 3693 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, }, 14484 { 3693 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, }, 14485 { 3693 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, }, 14486 { 3693 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, }, 14487 { 3693 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, }, 14488 { 3693 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, }, 14489 { 3693 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, }, 14490 { 3693 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, }, 14491 { 3693 /* vshl */, ARM::MVE_VSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 14492 { 3693 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 14493 { 3693 /* vshl */, ARM::MVE_VSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 14494 { 3693 /* vshl */, ARM::MVE_VSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 14495 { 3693 /* vshl */, ARM::MVE_VSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 14496 { 3693 /* vshl */, ARM::MVE_VSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 14497 { 3693 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14498 { 3693 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14499 { 3693 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14500 { 3693 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14501 { 3693 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14502 { 3693 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14503 { 3693 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14504 { 3693 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14505 { 3693 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14506 { 3693 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14507 { 3693 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14508 { 3693 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14509 { 3693 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14510 { 3693 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14511 { 3693 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14512 { 3693 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14513 { 3693 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14514 { 3693 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14515 { 3693 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14516 { 3693 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14517 { 3693 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14518 { 3693 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14519 { 3693 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14520 { 3693 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14521 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14522 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14523 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14524 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14525 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14526 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14527 { 3693 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14528 { 3693 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14529 { 3693 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14530 { 3698 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_rGPR, MCK_MVELongShift }, }, 14531 { 3704 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 14532 { 3704 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 14533 { 3704 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 14534 { 3704 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 14535 { 3704 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 14536 { 3704 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 14537 { 3704 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, }, 14538 { 3704 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, }, 14539 { 3704 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, }, 14540 { 3710 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 14541 { 3710 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 14542 { 3710 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 14543 { 3710 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 14544 { 3710 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 14545 { 3710 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 14546 { 3710 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 14547 { 3710 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 14548 { 3717 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 14549 { 3717 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 14550 { 3717 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 14551 { 3717 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 14552 { 3717 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 14553 { 3717 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 14554 { 3717 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 14555 { 3717 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 14556 { 3724 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14557 { 3724 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14558 { 3724 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 14559 { 3724 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 14560 { 3724 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 14561 { 3724 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 14562 { 3724 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 14563 { 3724 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 14564 { 3724 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 14565 { 3724 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 14566 { 3724 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 14567 { 3724 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 14568 { 3724 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 14569 { 3724 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 14570 { 3724 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 14571 { 3724 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 14572 { 3724 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14573 { 3724 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14574 { 3724 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14575 { 3724 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14576 { 3724 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14577 { 3724 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14578 { 3724 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14579 { 3724 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14580 { 3724 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14581 { 3724 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14582 { 3724 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14583 { 3724 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14584 { 3724 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14585 { 3724 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14586 { 3724 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14587 { 3724 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14588 { 3724 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14589 { 3724 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14590 { 3724 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14591 { 3724 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14592 { 3724 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14593 { 3724 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14594 { 3729 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14595 { 3729 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14596 { 3729 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14597 { 3735 /* vshrnb */, ARM::MVE_VSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14598 { 3735 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14599 { 3742 /* vshrnt */, ARM::MVE_VSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14600 { 3742 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14601 { 3749 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, }, 14602 { 3749 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, }, 14603 { 3749 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, }, 14604 { 3749 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, }, 14605 { 3749 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, }, 14606 { 3749 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, }, 14607 { 3749 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, }, 14608 { 3749 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, }, 14609 { 3749 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14610 { 3749 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14611 { 3749 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14612 { 3749 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14613 { 3749 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14614 { 3749 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14615 { 3749 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14616 { 3749 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14617 { 3749 /* vsli */, ARM::MVE_VSLIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14618 { 3749 /* vsli */, ARM::MVE_VSLIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14619 { 3749 /* vsli */, ARM::MVE_VSLIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14620 { 3754 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 14621 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 14622 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14623 { 3754 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14624 { 3754 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14625 { 3760 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14626 { 3760 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14627 { 3760 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 14628 { 3760 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 14629 { 3760 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 14630 { 3760 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 14631 { 3760 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 14632 { 3760 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 14633 { 3760 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 14634 { 3760 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 14635 { 3760 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 14636 { 3760 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 14637 { 3760 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 14638 { 3760 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 14639 { 3760 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 14640 { 3760 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 14641 { 3760 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14642 { 3760 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14643 { 3760 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14644 { 3760 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14645 { 3760 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14646 { 3760 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14647 { 3760 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14648 { 3760 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14649 { 3760 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14650 { 3760 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14651 { 3760 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14652 { 3760 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14653 { 3760 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14654 { 3760 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14655 { 3760 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14656 { 3760 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14657 { 3765 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, }, 14658 { 3765 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, }, 14659 { 3765 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, }, 14660 { 3765 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, }, 14661 { 3765 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, }, 14662 { 3765 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, }, 14663 { 3765 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, }, 14664 { 3765 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, }, 14665 { 3765 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14666 { 3765 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14667 { 3765 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14668 { 3765 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14669 { 3765 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14670 { 3765 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14671 { 3765 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14672 { 3765 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14673 { 3765 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14674 { 3765 /* vsri */, ARM::MVE_VSRIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14675 { 3765 /* vsri */, ARM::MVE_VSRIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14676 { 3770 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14677 { 3770 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14678 { 3770 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 14679 { 3770 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 14680 { 3770 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14681 { 3770 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14682 { 3770 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14683 { 3770 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 14684 { 3770 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 14685 { 3770 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14686 { 3770 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14687 { 3770 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14688 { 3770 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 14689 { 3770 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14690 { 3770 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14691 { 3770 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14692 { 3770 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 14693 { 3770 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 14694 { 3770 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14695 { 3770 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14696 { 3770 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14697 { 3770 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14698 { 3770 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14699 { 3770 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14700 { 3770 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 14701 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 14702 { 3770 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 14703 { 3770 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14704 { 3770 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14705 { 3770 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14706 { 3770 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14707 { 3770 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14708 { 3770 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14709 { 3770 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14710 { 3770 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 14711 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 14712 { 3770 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 14713 { 3770 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14714 { 3770 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14715 { 3770 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14716 { 3770 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14717 { 3770 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14718 { 3770 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14719 { 3770 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14720 { 3770 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 14721 { 3770 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14722 { 3770 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14723 { 3770 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14724 { 3770 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14725 { 3770 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14726 { 3770 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14727 { 3770 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14728 { 3770 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 14729 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14730 { 3770 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14731 { 3770 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14732 { 3770 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14733 { 3770 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 14734 { 3770 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 14735 { 3770 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14736 { 3770 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 14737 { 3770 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14738 { 3770 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, }, 14739 { 3775 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14740 { 3775 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 14741 { 3775 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14742 { 3775 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 14743 { 3775 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 14744 { 3775 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14745 { 3775 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 14746 { 3775 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14747 { 3775 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 14748 { 3775 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 14749 { 3775 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 14750 { 3775 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 14751 { 3775 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14752 { 3775 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 14753 { 3775 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14754 { 3775 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14755 { 3775 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14756 { 3775 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14757 { 3775 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14758 { 3775 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14759 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 14760 { 3775 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 14761 { 3775 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 14762 { 3775 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 14763 { 3775 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14764 { 3775 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14765 { 3775 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14766 { 3775 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14767 { 3775 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14768 { 3775 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14769 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14770 { 3775 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 14771 { 3775 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14772 { 3775 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 14773 { 3775 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14774 { 3775 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14775 { 3775 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14776 { 3775 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14777 { 3775 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14778 { 3775 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14779 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 14780 { 3775 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 14781 { 3780 /* vst20 */, ARM::MVE_VST20_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14782 { 3780 /* vst20 */, ARM::MVE_VST20_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14783 { 3780 /* vst20 */, ARM::MVE_VST20_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14784 { 3780 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14785 { 3780 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14786 { 3780 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14787 { 3786 /* vst21 */, ARM::MVE_VST21_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14788 { 3786 /* vst21 */, ARM::MVE_VST21_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14789 { 3786 /* vst21 */, ARM::MVE_VST21_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 14790 { 3786 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14791 { 3786 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14792 { 3786 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14793 { 3792 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14794 { 3792 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 14795 { 3792 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 14796 { 3792 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 14797 { 3792 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14798 { 3792 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 14799 { 3792 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 14800 { 3792 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 14801 { 3792 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 14802 { 3792 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 14803 { 3792 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 14804 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14805 { 3792 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14806 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14807 { 3792 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14808 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14809 { 3792 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 14810 { 3792 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14811 { 3792 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14812 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14813 { 3792 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14814 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14815 { 3792 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14816 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14817 { 3792 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 14818 { 3792 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14819 { 3792 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14820 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14821 { 3792 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 14822 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 14823 { 3792 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 14824 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14825 { 3792 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 14826 { 3792 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14827 { 3792 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14828 { 3792 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14829 { 3792 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14830 { 3792 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14831 { 3792 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14832 { 3792 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14833 { 3792 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14834 { 3792 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14835 { 3792 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14836 { 3792 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14837 { 3792 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14838 { 3797 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14839 { 3797 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 14840 { 3797 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 14841 { 3797 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 14842 { 3797 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14843 { 3797 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 14844 { 3797 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 14845 { 3797 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 14846 { 3797 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 14847 { 3797 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 14848 { 3797 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 14849 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14850 { 3797 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14851 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14852 { 3797 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 14853 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14854 { 3797 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14855 { 3797 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 14856 { 3797 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 14857 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14858 { 3797 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14859 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14860 { 3797 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14861 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14862 { 3797 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14863 { 3797 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 14864 { 3797 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 14865 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14866 { 3797 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14867 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 14868 { 3797 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 14869 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 14870 { 3797 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 14871 { 3797 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14872 { 3797 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14873 { 3797 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14874 { 3797 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14875 { 3797 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14876 { 3797 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 14877 { 3797 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14878 { 3797 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14879 { 3797 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14880 { 3797 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14881 { 3797 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14882 { 3797 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 14883 { 3802 /* vst40 */, ARM::MVE_VST40_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14884 { 3802 /* vst40 */, ARM::MVE_VST40_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14885 { 3802 /* vst40 */, ARM::MVE_VST40_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14886 { 3802 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14887 { 3802 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14888 { 3802 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14889 { 3808 /* vst41 */, ARM::MVE_VST41_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14890 { 3808 /* vst41 */, ARM::MVE_VST41_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14891 { 3808 /* vst41 */, ARM::MVE_VST41_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14892 { 3808 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14893 { 3808 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14894 { 3808 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14895 { 3814 /* vst42 */, ARM::MVE_VST42_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14896 { 3814 /* vst42 */, ARM::MVE_VST42_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14897 { 3814 /* vst42 */, ARM::MVE_VST42_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14898 { 3814 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14899 { 3814 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14900 { 3814 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14901 { 3820 /* vst43 */, ARM::MVE_VST43_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14902 { 3820 /* vst43 */, ARM::MVE_VST43_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14903 { 3820 /* vst43 */, ARM::MVE_VST43_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 14904 { 3820 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14905 { 3820 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14906 { 3820 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 14907 { 3826 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 14908 { 3826 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 14909 { 3833 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 14910 { 3833 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 14911 { 3833 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 14912 { 3833 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 14913 { 3840 /* vstr */, ARM::VSTR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset }, }, 14914 { 3840 /* vstr */, ARM::VSTR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, }, 14915 { 3840 /* vstr */, ARM::VSTR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, }, 14916 { 3840 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, }, 14917 { 3840 /* vstr */, ARM::VSTR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, }, 14918 { 3840 /* vstr */, ARM::VSTR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, }, 14919 { 3840 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 14920 { 3840 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 14921 { 3840 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 14922 { 3840 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 14923 { 3840 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 14924 { 3840 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14925 { 3840 /* vstr */, ARM::VSTR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14926 { 3840 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14927 { 3840 /* vstr */, ARM::VSTR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14928 { 3840 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14929 { 3840 /* vstr */, ARM::VSTR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14930 { 3840 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14931 { 3840 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14932 { 3840 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14933 { 3840 /* vstr */, ARM::VSTR_P0_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14934 { 3840 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 14935 { 3840 /* vstr */, ARM::VSTR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 14936 { 3845 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14937 { 3845 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 14938 { 3845 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14939 { 3845 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 14940 { 3845 /* vstrb */, ARM::MVE_VSTRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0Offset }, }, 14941 { 3845 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14942 { 3845 /* vstrb */, ARM::MVE_VSTRB16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 14943 { 3845 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 14944 { 3845 /* vstrb */, ARM::MVE_VSTRB32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 14945 { 3845 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 14946 { 3845 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, }, 14947 { 3845 /* vstrb */, ARM::MVE_VSTRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, }, 14948 { 3851 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset }, }, 14949 { 3851 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14950 { 3851 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS3Offset }, }, 14951 { 3851 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, }, 14952 { 3857 /* vstrh */, ARM::MVE_VSTRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1Offset }, }, 14953 { 3857 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14954 { 3857 /* vstrh */, ARM::MVE_VSTRH16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 14955 { 3857 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14956 { 3857 /* vstrh */, ARM::MVE_VSTRH32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 14957 { 3857 /* vstrh */, ARM::MVE_VSTRH32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 14958 { 3857 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, }, 14959 { 3857 /* vstrh */, ARM::MVE_VSTRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, }, 14960 { 3857 /* vstrh */, ARM::MVE_VSTRH32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 14961 { 3857 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 14962 { 3863 /* vstrw */, ARM::MVE_VSTRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2Offset }, }, 14963 { 3863 /* vstrw */, ARM::MVE_VSTRW32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset }, }, 14964 { 3863 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14965 { 3863 /* vstrw */, ARM::MVE_VSTRW32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS2Offset }, }, 14966 { 3863 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, }, 14967 { 3863 /* vstrw */, ARM::MVE_VSTRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, }, 14968 { 3863 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, }, 14969 { 3869 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14970 { 3869 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14971 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14972 { 3869 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14973 { 3869 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 14974 { 3869 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 14975 { 3869 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 14976 { 3869 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 14977 { 3869 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 14978 { 3869 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 14979 { 3869 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 14980 { 3869 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 14981 { 3869 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14982 { 3869 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14983 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14984 { 3869 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14985 { 3869 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14986 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14987 { 3869 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14988 { 3869 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14989 { 3869 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14990 { 3869 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14991 { 3869 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14992 { 3869 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14993 { 3869 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14994 { 3869 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14995 { 3869 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14996 { 3869 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14997 { 3869 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14998 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14999 { 3869 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15000 { 3869 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15001 { 3869 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15002 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15003 { 3869 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15004 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15005 { 3869 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15006 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15007 { 3869 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15008 { 3869 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15009 { 3874 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15010 { 3874 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15011 { 3874 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15012 { 3881 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15013 { 3881 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15014 { 3881 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15015 { 3881 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15016 { 3881 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15017 { 3881 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15018 { 3887 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 15019 { 3887 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 15020 { 3887 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 15021 { 3887 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 15022 { 3887 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 15023 { 3887 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 15024 { 3887 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15025 { 3887 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15026 { 3887 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15027 { 3887 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15028 { 3887 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15029 { 3887 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15030 { 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 15031 { 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 15032 { 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15033 { 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15034 { 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15035 { 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15036 { 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 15037 { 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 15038 { 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15039 { 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15040 { 3898 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 15041 { 3898 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 15042 { 3898 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 15043 { 3898 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 15044 { 3903 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 15045 { 3903 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 15046 { 3903 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 15047 { 3903 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 15048 { 3908 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15049 { 3908 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15050 { 3908 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15051 { 3908 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15052 { 3908 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15053 { 3908 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15054 { 3913 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15055 { 3913 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15056 { 3913 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15057 { 3913 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15058 { 3913 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15059 { 3913 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15060 { 3913 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15061 { 3913 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15062 { 3913 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15063 { 3913 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15064 { 3913 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15065 { 3913 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15066 { 3918 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15067 { 3918 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15068 { 3918 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15069 { 3918 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15070 { 3924 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15071 { 3924 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15072 { 3924 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15073 { 3924 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15074 { 3924 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15075 { 3924 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15076 { 3929 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15077 { 3929 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15078 { 3929 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15079 { 3929 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15080 { 3929 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15081 { 3929 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15082 { 3934 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15083 { 3934 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15084 { 3934 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15085 { 3938 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15086 { 3938 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15087 { 3938 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15088 { 3942 /* wls */, ARM::t2WLS, Convert__Reg1_0__Reg1_1__WLSLabel1_2, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15089 { 3946 /* wlstp */, ARM::MVE_WLSTP_16, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15090 { 3946 /* wlstp */, ARM::MVE_WLSTP_32, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15091 { 3946 /* wlstp */, ARM::MVE_WLSTP_64, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15092 { 3946 /* wlstp */, ARM::MVE_WLSTP_8, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15093 { 3952 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15094 { 3952 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15095 { 3952 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15096}; 15097 15098#include "llvm/Support/Debug.h" 15099#include "llvm/Support/Format.h" 15100 15101unsigned ARMAsmParser:: 15102MatchInstructionImpl(const OperandVector &Operands, 15103 MCInst &Inst, 15104 SmallVectorImpl<NearMissInfo> *NearMisses, 15105 bool matchingInlineAsm, unsigned VariantID) { 15106 // Get the current feature set. 15107 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 15108 15109 // Get the instruction mnemonic, which is the first token. 15110 StringRef Mnemonic = ((ARMOperand&)*Operands[0]).getToken(); 15111 15112 // Process all MnemonicAliases to remap the mnemonic. 15113 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 15114 15115 // Find the appropriate table for this asm variant. 15116 const MatchEntry *Start, *End; 15117 switch (VariantID) { 15118 default: llvm_unreachable("invalid variant!"); 15119 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 15120 } 15121 // Search the table. 15122 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 15123 15124 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 15125 std::distance(MnemonicRange.first, MnemonicRange.second) << 15126 " encodings with mnemonic '" << Mnemonic << "'\n"); 15127 15128 // Return a more specific error code if no mnemonics match. 15129 if (MnemonicRange.first == MnemonicRange.second) 15130 return Match_MnemonicFail; 15131 15132 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 15133 it != ie; ++it) { 15134 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 15135 bool HasRequiredFeatures = 15136 (AvailableFeatures & RequiredFeatures) == RequiredFeatures; 15137 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 15138 << MII.getName(it->Opcode) << "\n"); 15139 // Some state to record ways in which this instruction did not match. 15140 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess(); 15141 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess(); 15142 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess(); 15143 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess(); 15144 bool MultipleInvalidOperands = false; 15145 // equal_range guarantees that instruction mnemonic matches. 15146 assert(Mnemonic == it->getMnemonic()); 15147 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) { 15148 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 15149 DEBUG_WITH_TYPE("asm-matcher", 15150 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 15151 << " against actual operand at index " << ActualIdx); 15152 if (ActualIdx < Operands.size()) 15153 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 15154 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 15155 else 15156 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 15157 if (ActualIdx >= Operands.size()) { 15158 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); 15159 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 15160 if (!ThisOperandValid) { 15161 if (!OperandNearMiss) { 15162 // Record info about match failure for later use. 15163 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n"); 15164 OperandNearMiss = 15165 NearMissInfo::getTooFewOperands(Formal, it->Opcode); 15166 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) { 15167 // If more than one operand is invalid, give up on this match entry. 15168 DEBUG_WITH_TYPE( 15169 "asm-matcher", 15170 dbgs() << "second invalid operand, giving up on this opcode\n"); 15171 MultipleInvalidOperands = true; 15172 break; 15173 } 15174 } else { 15175 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n"); 15176 break; 15177 } 15178 continue; 15179 } 15180 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 15181 unsigned Diag = validateOperandClass(Actual, Formal); 15182 if (Diag == Match_Success) { 15183 DEBUG_WITH_TYPE("asm-matcher", 15184 dbgs() << "match success using generic matcher\n"); 15185 ++ActualIdx; 15186 continue; 15187 } 15188 // If the generic handler indicates an invalid operand 15189 // failure, check for a special case. 15190 if (Diag != Match_Success) { 15191 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 15192 if (TargetDiag == Match_Success) { 15193 DEBUG_WITH_TYPE("asm-matcher", 15194 dbgs() << "match success using target matcher\n"); 15195 ++ActualIdx; 15196 continue; 15197 } 15198 // If the target matcher returned a specific error code use 15199 // that, else use the one from the generic matcher. 15200 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 15201 Diag = TargetDiag; 15202 } 15203 // If current formal operand wasn't matched and it is optional 15204 // then try to match next formal operand 15205 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 15206 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 15207 continue; 15208 } 15209 if (!OperandNearMiss) { 15210 // If this is the first invalid operand we have seen, record some 15211 // information about it. 15212 DEBUG_WITH_TYPE( 15213 "asm-matcher", 15214 dbgs() 15215 << "operand match failed, recording near-miss with diag code " 15216 << Diag << "\n"); 15217 OperandNearMiss = 15218 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx); 15219 ++ActualIdx; 15220 } else { 15221 // If more than one operand is invalid, give up on this match entry. 15222 DEBUG_WITH_TYPE( 15223 "asm-matcher", 15224 dbgs() << "second operand mismatch, skipping this opcode\n"); 15225 MultipleInvalidOperands = true; 15226 break; 15227 } 15228 } 15229 15230 if (MultipleInvalidOperands) { 15231 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15232 "operand mismatches, ignoring " 15233 "this opcode\n"); 15234 continue; 15235 } 15236 if (!HasRequiredFeatures) { 15237 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; 15238 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; 15239 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) 15240 if (NewMissingFeatures[I]) 15241 dbgs() << ' ' << I; 15242 dbgs() << "\n"); 15243 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures); 15244 } 15245 15246 Inst.clear(); 15247 15248 Inst.setOpcode(it->Opcode); 15249 // We have a potential match but have not rendered the operands. 15250 // Check the target predicate to handle any context sensitive 15251 // constraints. 15252 // For example, Ties that are referenced multiple times must be 15253 // checked here to ensure the input is the same for each match 15254 // constraints. If we leave it any later the ties will have been 15255 // canonicalized 15256 unsigned MatchResult; 15257 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 15258 Inst.clear(); 15259 DEBUG_WITH_TYPE( 15260 "asm-matcher", 15261 dbgs() << "Early target match predicate failed with diag code " 15262 << MatchResult << "\n"); 15263 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 15264 } 15265 15266 // If we did not successfully match the operands, then we can't convert to 15267 // an MCInst, so bail out on this instruction variant now. 15268 if (OperandNearMiss) { 15269 // If the operand mismatch was the only problem, reprrt it as a near-miss. 15270 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) { 15271 DEBUG_WITH_TYPE( 15272 "asm-matcher", 15273 dbgs() 15274 << "Opcode result: one mismatched operand, adding near-miss\n"); 15275 NearMisses->push_back(OperandNearMiss); 15276 } else { 15277 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15278 "types of mismatch, so not " 15279 "reporting near-miss\n"); 15280 } 15281 continue; 15282 } 15283 15284 if (matchingInlineAsm) { 15285 convertToMapAndConstraints(it->ConvertFn, Operands); 15286 return Match_Success; 15287 } 15288 15289 // We have selected a definite instruction, convert the parsed 15290 // operands into the appropriate MCInst. 15291 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 15292 15293 // We have a potential match. Check the target predicate to 15294 // handle any context sensitive constraints. 15295 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 15296 DEBUG_WITH_TYPE("asm-matcher", 15297 dbgs() << "Target match predicate failed with diag code " 15298 << MatchResult << "\n"); 15299 Inst.clear(); 15300 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 15301 } 15302 15303 int NumNearMisses = ((int)(bool)OperandNearMiss + 15304 (int)(bool)FeaturesNearMiss + 15305 (int)(bool)EarlyPredicateNearMiss + 15306 (int)(bool)LatePredicateNearMiss); 15307 if (NumNearMisses == 1) { 15308 // We had exactly one type of near-miss, so add that to the list. 15309 assert(!OperandNearMiss && "OperandNearMiss was handled earlier"); 15310 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of " 15311 "mismatch, so reporting a " 15312 "near-miss\n"); 15313 if (NearMisses && FeaturesNearMiss) 15314 NearMisses->push_back(FeaturesNearMiss); 15315 else if (NearMisses && EarlyPredicateNearMiss) 15316 NearMisses->push_back(EarlyPredicateNearMiss); 15317 else if (NearMisses && LatePredicateNearMiss) 15318 NearMisses->push_back(LatePredicateNearMiss); 15319 15320 continue; 15321 } else if (NumNearMisses > 1) { 15322 // This instruction missed in more than one way, so ignore it. 15323 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15324 "types of mismatch, so not " 15325 "reporting near-miss\n"); 15326 continue; 15327 } 15328 std::string Info; 15329 if (!getParser().getTargetParser(). 15330 getTargetOptions().MCNoDeprecatedWarn && 15331 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) { 15332 SMLoc Loc = ((ARMOperand&)*Operands[0]).getStartLoc(); 15333 getParser().Warning(Loc, Info, None); 15334 } 15335 DEBUG_WITH_TYPE( 15336 "asm-matcher", 15337 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 15338 return Match_Success; 15339 } 15340 15341 // No instruction variants matched exactly. 15342 return Match_NearMisses; 15343} 15344 15345namespace { 15346 struct OperandMatchEntry { 15347 uint16_t Mnemonic; 15348 uint8_t OperandMask; 15349 uint16_t Class; 15350 uint8_t RequiredFeaturesIdx; 15351 15352 StringRef getMnemonic() const { 15353 return StringRef(MnemonicTable + Mnemonic + 1, 15354 MnemonicTable[Mnemonic]); 15355 } 15356 }; 15357 15358 // Predicate for searching for an opcode. 15359 struct LessOpcodeOperand { 15360 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 15361 return LHS.getMnemonic() < RHS; 15362 } 15363 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 15364 return LHS < RHS.getMnemonic(); 15365 } 15366 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 15367 return LHS.getMnemonic() < RHS.getMnemonic(); 15368 } 15369 }; 15370} // end anonymous namespace 15371 15372static const OperandMatchEntry OperandMatchTable[858] = { 15373 /* Operand List Mnemonic, Mask, Operand Class, Features */ 15374 { 10 /* adc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15375 { 10 /* adc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15376 { 14 /* add */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15377 { 14 /* add */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15378 { 50 /* and */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15379 { 50 /* and */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15380 { 68 /* bfc */, 4 /* 2 */, MCK_Bitfield, AMFBS_IsThumb2 }, 15381 { 68 /* bfc */, 4 /* 2 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 }, 15382 { 72 /* bfcsel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB }, 15383 { 79 /* bfi */, 8 /* 3 */, MCK_Bitfield, AMFBS_IsThumb2 }, 15384 { 79 /* bfi */, 8 /* 3 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 }, 15385 { 96 /* bic */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15386 { 96 /* bic */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15387 { 139 /* cdp */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15388 { 139 /* cdp */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15389 { 139 /* cdp */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15390 { 139 /* cdp */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15391 { 143 /* cdp2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15392 { 143 /* cdp2 */, 28 /* 2, 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15393 { 143 /* cdp2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15394 { 143 /* cdp2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15395 { 148 /* cinc */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15396 { 153 /* cinv */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15397 { 173 /* cmn */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15398 { 177 /* cmp */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15399 { 181 /* cneg */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15400 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM }, 15401 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb }, 15402 { 186 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass }, 15403 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM }, 15404 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass }, 15405 { 186 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2 }, 15406 { 240 /* csel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 15407 { 245 /* cset */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15408 { 250 /* csetm */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15409 { 256 /* csinc */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 15410 { 262 /* csinv */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 15411 { 268 /* csneg */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 15412 { 310 /* dmb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB }, 15413 { 310 /* dmb */, 2 /* 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB }, 15414 { 314 /* dsb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB }, 15415 { 314 /* dsb */, 2 /* 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB }, 15416 { 318 /* eor */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15417 { 318 /* eor */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15418 { 357 /* fconstd */, 4 /* 2 */, MCK_FPImm, AMFBS_HasVFP3 }, 15419 { 365 /* fconsts */, 4 /* 2 */, MCK_FPImm, AMFBS_HasVFP3 }, 15420 { 449 /* isb */, 1 /* 0 */, MCK_InstSyncBarrierOpt, AMFBS_IsARM_HasDB }, 15421 { 449 /* isb */, 2 /* 1 */, MCK_InstSyncBarrierOpt, AMFBS_IsThumb_HasDB }, 15422 { 453 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM }, 15423 { 453 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsThumb2 }, 15424 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15425 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15426 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15427 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15428 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15429 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15430 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15431 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15432 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15433 { 502 /* ldc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 15434 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15435 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15436 { 502 /* ldc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 15437 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15438 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15439 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15440 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15441 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15442 { 506 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15443 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15444 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15445 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15446 { 506 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15447 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15448 { 506 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15449 { 506 /* ldc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 15450 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15451 { 506 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15452 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15453 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15454 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15455 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15456 { 506 /* ldc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 15457 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15458 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15459 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15460 { 511 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15461 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15462 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15463 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15464 { 511 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15465 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15466 { 511 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15467 { 511 /* ldc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 15468 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15469 { 511 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15470 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15471 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15472 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15473 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15474 { 511 /* ldc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 15475 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15476 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15477 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15478 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15479 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15480 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15481 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15482 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15483 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15484 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15485 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15486 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15487 { 517 /* ldcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 15488 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15489 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15490 { 517 /* ldcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 15491 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15492 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15493 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15494 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15495 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15496 { 544 /* ldr */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15497 { 548 /* ldrb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15498 { 553 /* ldrbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15499 { 559 /* ldrd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM }, 15500 { 591 /* ldrh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 15501 { 596 /* ldrht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 15502 { 602 /* ldrsb */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 15503 { 608 /* ldrsbt */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 15504 { 615 /* ldrsh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 15505 { 621 /* ldrsht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 15506 { 628 /* ldrt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15507 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15508 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15509 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15510 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15511 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15512 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15513 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15514 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15515 { 663 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM }, 15516 { 663 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM }, 15517 { 663 /* mcr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15518 { 663 /* mcr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15519 { 663 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15520 { 663 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15521 { 663 /* mcr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15522 { 663 /* mcr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15523 { 668 /* mcrr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15524 { 668 /* mcrr */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15525 { 668 /* mcrr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15526 { 668 /* mcrr */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15527 { 673 /* mcrr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15528 { 673 /* mcrr2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15529 { 673 /* mcrr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15530 { 673 /* mcrr2 */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15531 { 687 /* mov */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15532 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15533 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15534 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15535 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15536 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15537 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15538 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15539 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15540 { 710 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM }, 15541 { 710 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM }, 15542 { 710 /* mrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15543 { 710 /* mrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15544 { 710 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15545 { 710 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15546 { 710 /* mrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15547 { 710 /* mrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15548 { 715 /* mrrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15549 { 715 /* mrrc */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM }, 15550 { 715 /* mrrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15551 { 715 /* mrrc */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15552 { 720 /* mrrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15553 { 720 /* mrrc2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15554 { 720 /* mrrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15555 { 720 /* mrrc2 */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15556 { 726 /* mrs */, 4 /* 2 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization }, 15557 { 726 /* mrs */, 4 /* 2 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass }, 15558 { 726 /* mrs */, 4 /* 2 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization }, 15559 { 730 /* msr */, 2 /* 1 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization }, 15560 { 730 /* msr */, 2 /* 1 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization }, 15561 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass }, 15562 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass }, 15563 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM }, 15564 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM }, 15565 { 730 /* msr */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15566 { 738 /* mvn */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15567 { 754 /* orr */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15568 { 754 /* orr */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15569 { 758 /* pkhbt */, 16 /* 4 */, MCK_PKHLSLImm, AMFBS_HasDSP_IsThumb2 }, 15570 { 758 /* pkhbt */, 16 /* 4 */, MCK_PKHLSLImm, AMFBS_IsARM_HasV6 }, 15571 { 764 /* pkhtb */, 16 /* 4 */, MCK_PKHASRImm, AMFBS_HasDSP_IsThumb2 }, 15572 { 764 /* pkhtb */, 16 /* 4 */, MCK_PKHASRImm, AMFBS_IsARM_HasV6 }, 15573 { 909 /* rsb */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15574 { 909 /* rsb */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15575 { 913 /* rsc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15576 { 913 /* rsc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15577 { 938 /* sbc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15578 { 938 /* sbc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15579 { 956 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsThumb_IsNotMClass }, 15580 { 956 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM }, 15581 { 1419 /* ssat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsThumb2 }, 15582 { 1419 /* ssat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 }, 15583 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15584 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15585 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15586 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15587 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15588 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15589 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15590 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15591 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15592 { 1454 /* stc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 15593 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15594 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15595 { 1454 /* stc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 15596 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15597 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15598 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15599 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15600 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15601 { 1458 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15602 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15603 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15604 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15605 { 1458 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15606 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15607 { 1458 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15608 { 1458 /* stc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 15609 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15610 { 1458 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15611 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15612 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15613 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15614 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15615 { 1458 /* stc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 15616 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15617 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15618 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15619 { 1463 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15620 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15621 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15622 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15623 { 1463 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15624 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15625 { 1463 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15626 { 1463 /* stc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 15627 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15628 { 1463 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15629 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15630 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15631 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15632 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15633 { 1463 /* stc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 15634 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15635 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 15636 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 15637 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15638 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15639 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15640 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15641 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15642 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15643 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15644 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15645 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15646 { 1469 /* stcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 15647 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15648 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15649 { 1469 /* stcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 15650 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15651 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 15652 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 15653 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 15654 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 15655 { 1537 /* str */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15656 { 1541 /* strb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15657 { 1546 /* strbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15658 { 1552 /* strd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM }, 15659 { 1584 /* strh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 15660 { 1589 /* strht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 15661 { 1595 /* strt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 15662 { 1600 /* sub */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15663 { 1600 /* sub */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15664 { 1627 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15665 { 1627 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15666 { 1633 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15667 { 1633 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15668 { 1641 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15669 { 1641 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15670 { 1647 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 15671 { 1647 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15672 { 1647 /* sxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 15673 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15674 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15675 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15676 { 1659 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 15677 { 1659 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15678 { 1659 /* sxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 15679 { 1672 /* teq */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15680 { 1681 /* tsb */, 1 /* 0 */, MCK_TraceSyncBarrierOpt, AMFBS_IsARM_HasV8_4a }, 15681 { 1681 /* tsb */, 2 /* 1 */, MCK_TraceSyncBarrierOpt, AMFBS_IsThumb_HasV8_4a }, 15682 { 1685 /* tst */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15683 { 1893 /* usat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsThumb2 }, 15684 { 1893 /* usat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 }, 15685 { 1923 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15686 { 1923 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15687 { 1929 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15688 { 1929 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15689 { 1937 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15690 { 1937 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15691 { 1943 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 15692 { 1943 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15693 { 1943 /* uxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 15694 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15695 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 15696 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15697 { 1955 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 15698 { 1955 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 15699 { 1955 /* uxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 15700 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15701 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15702 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15703 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15704 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15705 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15706 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15707 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15708 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15709 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15710 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15711 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 15712 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 15713 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 15714 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15715 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15716 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15717 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15718 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15719 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15720 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 15721 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 15722 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15723 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15724 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15725 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15726 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15727 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 15728 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15729 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15730 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15731 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15732 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15733 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15734 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 15735 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15736 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15737 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15738 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15739 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15740 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15741 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15742 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15743 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15744 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15745 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 15746 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15747 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15748 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15749 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15750 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15751 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15752 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15753 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15754 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15755 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15756 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15757 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 15758 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 15759 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15760 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15761 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15762 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15763 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15764 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15765 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15766 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15767 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15768 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15769 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15770 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15771 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 15772 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 15773 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15774 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15775 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15776 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15777 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15778 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15779 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15780 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15781 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15782 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15783 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15784 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15785 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15786 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15787 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15788 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15789 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15790 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 15791 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15792 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 15793 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 15794 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 15795 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15796 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15797 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15798 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15799 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15800 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15801 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15802 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 15803 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 15804 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15805 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15806 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15807 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15808 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15809 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 15810 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 15811 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15812 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15813 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15814 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15815 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15816 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 15817 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15818 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15819 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15820 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15821 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15822 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15823 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15824 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15825 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15826 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15827 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 15828 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 15829 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 15830 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 15831 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15832 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15833 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15834 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15835 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15836 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15837 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15838 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15839 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15840 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15841 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 15842 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 15843 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 15844 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 15845 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15846 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15847 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15848 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 15849 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15850 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 15851 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15852 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 15853 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15854 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15855 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 15856 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 15857 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15858 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15859 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15860 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15861 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15862 { 2358 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15863 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15864 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15865 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15866 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15867 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15868 { 2364 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 15869 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15870 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15871 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 15872 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15873 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15874 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 15875 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15876 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15877 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 15878 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15879 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15880 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 15881 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15882 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15883 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 15884 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15885 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15886 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15887 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15888 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15889 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15890 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 15891 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 15892 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15893 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15894 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15895 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15896 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 15897 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 15898 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15899 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15900 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15901 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15902 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 15903 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 15904 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15905 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15906 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15907 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15908 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 15909 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 15910 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15911 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 15912 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15913 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 15914 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 15915 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 15916 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15917 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 15918 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15919 { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 15920 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15921 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15922 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 15923 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15924 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15925 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 15926 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15927 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15928 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 15929 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15930 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15931 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 15932 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15933 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15934 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 15935 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15936 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15937 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15938 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15939 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15940 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15941 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 15942 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 15943 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15944 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15945 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15946 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15947 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 15948 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 15949 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15950 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15951 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15952 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15953 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 15954 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 15955 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15956 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15957 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15958 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15959 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 15960 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 15961 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15962 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 15963 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15964 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 15965 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 15966 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 15967 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15968 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 15969 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15970 { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 15971 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15972 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15973 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15974 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15975 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15976 { 2380 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15977 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15978 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15979 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15980 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15981 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15982 { 2386 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15983 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15984 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15985 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15986 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15987 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15988 { 2392 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15989 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15990 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15991 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15992 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15993 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15994 { 2398 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 15995 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasNEON }, 15996 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasNEON }, 15997 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasVFP3 }, 15998 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasVFP3_HasDPVFP }, 15999 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasFullFP16 }, 16000 { 2779 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasMVEInt }, 16001 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16002 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16003 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16004 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16005 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16006 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16007 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16008 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16009 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16010 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16011 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16012 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16013 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16014 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16015 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16016 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16017 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16018 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16019 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16020 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16021 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16022 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16023 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16024 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16025 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16026 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16027 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16028 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16029 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16030 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16031 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16032 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16033 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16034 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16035 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16036 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16037 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16038 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16039 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16040 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16041 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16042 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16043 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16044 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16045 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16046 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16047 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16048 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16049 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16050 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16051 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16052 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16053 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16054 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16055 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16056 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16057 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16058 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16059 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16060 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16061 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16062 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16063 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16064 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16065 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16066 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16067 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16068 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16069 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16070 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16071 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16072 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16073 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16074 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16075 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16076 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16077 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16078 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16079 { 3770 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16080 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16081 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16082 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16083 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16084 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16085 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16086 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16087 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16088 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16089 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16090 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16091 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16092 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16093 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16094 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16095 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16096 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16097 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16098 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16099 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16100 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16101 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16102 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16103 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16104 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16105 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16106 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16107 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16108 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16109 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16110 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16111 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16112 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16113 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16114 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16115 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16116 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16117 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16118 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16119 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16120 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16121 { 3775 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16122 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16123 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16124 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16125 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16126 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16127 { 3780 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16128 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16129 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16130 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16131 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16132 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16133 { 3786 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16134 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16135 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16136 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16137 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16138 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16139 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16140 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16141 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16142 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16143 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16144 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16145 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16146 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16147 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16148 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16149 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16150 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16151 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16152 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16153 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16154 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16155 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16156 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16157 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16158 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16159 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16160 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16161 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16162 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16163 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16164 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16165 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16166 { 3792 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16167 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16168 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16169 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16170 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16171 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16172 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16173 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16174 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16175 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16176 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16177 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16178 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16179 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16180 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16181 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16182 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16183 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16184 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16185 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16186 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16187 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16188 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16189 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16190 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16191 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16192 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16193 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16194 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16195 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16196 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16197 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16198 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16199 { 3797 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16200 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16201 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16202 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16203 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16204 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16205 { 3802 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16206 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16207 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16208 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16209 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16210 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16211 { 3808 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16212 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16213 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16214 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16215 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16216 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16217 { 3814 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16218 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16219 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16220 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16221 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16222 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16223 { 3820 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16224 { 3898 /* vtbl */, 8 /* 3 */, MCK_VecListDPair, AMFBS_HasNEON }, 16225 { 3898 /* vtbl */, 8 /* 3 */, MCK_VecListFourD, AMFBS_HasNEON }, 16226 { 3898 /* vtbl */, 8 /* 3 */, MCK_VecListOneD, AMFBS_HasNEON }, 16227 { 3898 /* vtbl */, 8 /* 3 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16228 { 3903 /* vtbx */, 8 /* 3 */, MCK_VecListDPair, AMFBS_HasNEON }, 16229 { 3903 /* vtbx */, 8 /* 3 */, MCK_VecListFourD, AMFBS_HasNEON }, 16230 { 3903 /* vtbx */, 8 /* 3 */, MCK_VecListOneD, AMFBS_HasNEON }, 16231 { 3903 /* vtbx */, 8 /* 3 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16232}; 16233 16234OperandMatchResultTy ARMAsmParser:: 16235tryCustomParseOperand(OperandVector &Operands, 16236 unsigned MCK) { 16237 16238 switch(MCK) { 16239 case MCK_AM3Offset: 16240 return parseAM3Offset(Operands); 16241 case MCK_BankedReg: 16242 return parseBankedRegOperand(Operands); 16243 case MCK_Bitfield: 16244 return parseBitfield(Operands); 16245 case MCK_CoprocNum: 16246 return parseCoprocNumOperand(Operands); 16247 case MCK_CoprocOption: 16248 return parseCoprocOptionOperand(Operands); 16249 case MCK_CoprocReg: 16250 return parseCoprocRegOperand(Operands); 16251 case MCK_FPImm: 16252 return parseFPImm(Operands); 16253 case MCK_InstSyncBarrierOpt: 16254 return parseInstSyncBarrierOptOperand(Operands); 16255 case MCK_MSRMask: 16256 return parseMSRMaskOperand(Operands); 16257 case MCK_MemBarrierOpt: 16258 return parseMemBarrierOptOperand(Operands); 16259 case MCK_ModImm: 16260 return parseModImm(Operands); 16261 case MCK_PKHASRImm: 16262 return parsePKHASRImm(Operands); 16263 case MCK_PKHLSLImm: 16264 return parsePKHLSLImm(Operands); 16265 case MCK_PostIdxReg: 16266 return parsePostIdxReg(Operands); 16267 case MCK_PostIdxRegShifted: 16268 return parsePostIdxReg(Operands); 16269 case MCK_ProcIFlags: 16270 return parseProcIFlagsOperand(Operands); 16271 case MCK_RotImm: 16272 return parseRotImm(Operands); 16273 case MCK_SetEndImm: 16274 return parseSetEndImm(Operands); 16275 case MCK_ShifterImm: 16276 return parseShifterImm(Operands); 16277 case MCK_TraceSyncBarrierOpt: 16278 return parseTraceSyncBarrierOptOperand(Operands); 16279 case MCK_VecListTwoMQ: 16280 return parseVectorList(Operands); 16281 case MCK_VecListFourMQ: 16282 return parseVectorList(Operands); 16283 case MCK_VecListDPairAllLanes: 16284 return parseVectorList(Operands); 16285 case MCK_VecListDPair: 16286 return parseVectorList(Operands); 16287 case MCK_VecListDPairSpacedAllLanes: 16288 return parseVectorList(Operands); 16289 case MCK_VecListDPairSpaced: 16290 return parseVectorList(Operands); 16291 case MCK_VecListFourDAllLanes: 16292 return parseVectorList(Operands); 16293 case MCK_VecListFourD: 16294 return parseVectorList(Operands); 16295 case MCK_VecListFourDByteIndexed: 16296 return parseVectorList(Operands); 16297 case MCK_VecListFourDHWordIndexed: 16298 return parseVectorList(Operands); 16299 case MCK_VecListFourDWordIndexed: 16300 return parseVectorList(Operands); 16301 case MCK_VecListFourQAllLanes: 16302 return parseVectorList(Operands); 16303 case MCK_VecListFourQ: 16304 return parseVectorList(Operands); 16305 case MCK_VecListFourQHWordIndexed: 16306 return parseVectorList(Operands); 16307 case MCK_VecListFourQWordIndexed: 16308 return parseVectorList(Operands); 16309 case MCK_VecListOneDAllLanes: 16310 return parseVectorList(Operands); 16311 case MCK_VecListOneD: 16312 return parseVectorList(Operands); 16313 case MCK_VecListOneDByteIndexed: 16314 return parseVectorList(Operands); 16315 case MCK_VecListOneDHWordIndexed: 16316 return parseVectorList(Operands); 16317 case MCK_VecListOneDWordIndexed: 16318 return parseVectorList(Operands); 16319 case MCK_VecListThreeDAllLanes: 16320 return parseVectorList(Operands); 16321 case MCK_VecListThreeD: 16322 return parseVectorList(Operands); 16323 case MCK_VecListThreeDByteIndexed: 16324 return parseVectorList(Operands); 16325 case MCK_VecListThreeDHWordIndexed: 16326 return parseVectorList(Operands); 16327 case MCK_VecListThreeDWordIndexed: 16328 return parseVectorList(Operands); 16329 case MCK_VecListThreeQAllLanes: 16330 return parseVectorList(Operands); 16331 case MCK_VecListThreeQ: 16332 return parseVectorList(Operands); 16333 case MCK_VecListThreeQHWordIndexed: 16334 return parseVectorList(Operands); 16335 case MCK_VecListThreeQWordIndexed: 16336 return parseVectorList(Operands); 16337 case MCK_VecListTwoDByteIndexed: 16338 return parseVectorList(Operands); 16339 case MCK_VecListTwoDHWordIndexed: 16340 return parseVectorList(Operands); 16341 case MCK_VecListTwoDWordIndexed: 16342 return parseVectorList(Operands); 16343 case MCK_VecListTwoQHWordIndexed: 16344 return parseVectorList(Operands); 16345 case MCK_VecListTwoQWordIndexed: 16346 return parseVectorList(Operands); 16347 case MCK_ITCondCode: 16348 return parseITCondCode(Operands); 16349 case MCK_CondCodeNoAL: 16350 return parseITCondCode(Operands); 16351 case MCK_CondCodeNoALInv: 16352 return parseITCondCode(Operands); 16353 case MCK_CondCodeRestrictedFP: 16354 return parseITCondCode(Operands); 16355 case MCK_CondCodeRestrictedI: 16356 return parseITCondCode(Operands); 16357 case MCK_CondCodeRestrictedS: 16358 return parseITCondCode(Operands); 16359 case MCK_CondCodeRestrictedU: 16360 return parseITCondCode(Operands); 16361 default: 16362 return MatchOperand_NoMatch; 16363 } 16364 return MatchOperand_NoMatch; 16365} 16366 16367OperandMatchResultTy ARMAsmParser:: 16368MatchOperandParserImpl(OperandVector &Operands, 16369 StringRef Mnemonic, 16370 bool ParseForAllFeatures) { 16371 // Get the current feature set. 16372 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 16373 16374 // Get the next operand index. 16375 unsigned NextOpNum = Operands.size() - 1; 16376 // Search the table. 16377 auto MnemonicRange = 16378 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 16379 Mnemonic, LessOpcodeOperand()); 16380 16381 if (MnemonicRange.first == MnemonicRange.second) 16382 return MatchOperand_NoMatch; 16383 16384 for (const OperandMatchEntry *it = MnemonicRange.first, 16385 *ie = MnemonicRange.second; it != ie; ++it) { 16386 // equal_range guarantees that instruction mnemonic matches. 16387 assert(Mnemonic == it->getMnemonic()); 16388 16389 // check if the available features match 16390 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 16391 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) 16392 continue; 16393 16394 // check if the operand in question has a custom parser. 16395 if (!(it->OperandMask & (1 << NextOpNum))) 16396 continue; 16397 16398 // call custom parse method to handle the operand 16399 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 16400 if (Result != MatchOperand_NoMatch) 16401 return Result; 16402 } 16403 16404 // Okay, we had no match. 16405 return MatchOperand_NoMatch; 16406} 16407 16408#endif // GET_MATCHER_IMPLEMENTATION 16409 16410 16411#ifdef GET_MNEMONIC_SPELL_CHECKER 16412#undef GET_MNEMONIC_SPELL_CHECKER 16413 16414static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { 16415 const unsigned MaxEditDist = 2; 16416 std::vector<StringRef> Candidates; 16417 StringRef Prev = ""; 16418 16419 // Find the appropriate table for this asm variant. 16420 const MatchEntry *Start, *End; 16421 switch (VariantID) { 16422 default: llvm_unreachable("invalid variant!"); 16423 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 16424 } 16425 16426 for (auto I = Start; I < End; I++) { 16427 // Ignore unsupported instructions. 16428 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; 16429 if ((FBS & RequiredFeatures) != RequiredFeatures) 16430 continue; 16431 16432 StringRef T = I->getMnemonic(); 16433 // Avoid recomputing the edit distance for the same string. 16434 if (T.equals(Prev)) 16435 continue; 16436 16437 Prev = T; 16438 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 16439 if (Dist <= MaxEditDist) 16440 Candidates.push_back(T); 16441 } 16442 16443 if (Candidates.empty()) 16444 return ""; 16445 16446 std::string Res = ", did you mean: "; 16447 unsigned i = 0; 16448 for( ; i < Candidates.size() - 1; i++) 16449 Res += Candidates[i].str() + ", "; 16450 return Res + Candidates[i].str() + "?"; 16451} 16452 16453#endif // GET_MNEMONIC_SPELL_CHECKER 16454 16455