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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Global Instruction Selector for the ARM target                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 72;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15  mutable MatcherState State;
16  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const;
18  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24  const int64_t *getMatchTable() const override;
25  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36  Feature_NoHonorSignDependentRoundingBit = 64,
37  Feature_HasV4TBit = 6,
38  Feature_NoV4TBit = 7,
39  Feature_HasV5TBit = 8,
40  Feature_NoV5TBit = 61,
41  Feature_HasV5TEBit = 12,
42  Feature_HasV6Bit = 0,
43  Feature_NoV6Bit = 10,
44  Feature_HasV6MBit = 29,
45  Feature_HasV8MBaselineBit = 33,
46  Feature_HasV8_1MMainlineBit = 59,
47  Feature_HasMVEIntBit = 58,
48  Feature_HasMVEFloatBit = 60,
49  Feature_HasFPRegsBit = 39,
50  Feature_HasFPRegs16Bit = 40,
51  Feature_HasFPRegs64Bit = 49,
52  Feature_HasV6T2Bit = 9,
53  Feature_HasV6KBit = 19,
54  Feature_HasV7Bit = 3,
55  Feature_HasV8Bit = 15,
56  Feature_PreV8Bit = 20,
57  Feature_HasV8_1aBit = 66,
58  Feature_HasV8_3aBit = 67,
59  Feature_NoVFPBit = 23,
60  Feature_HasVFP2Bit = 22,
61  Feature_HasVFP3Bit = 50,
62  Feature_HasVFP4Bit = 47,
63  Feature_HasDPVFPBit = 41,
64  Feature_HasFPARMv8Bit = 44,
65  Feature_HasNEONBit = 51,
66  Feature_HasCryptoBit = 52,
67  Feature_HasDotProdBit = 53,
68  Feature_HasCRCBit = 14,
69  Feature_HasFP16Bit = 57,
70  Feature_HasFullFP16Bit = 43,
71  Feature_HasDivideInThumbBit = 35,
72  Feature_HasDivideInARMBit = 13,
73  Feature_HasDSPBit = 34,
74  Feature_HasDBBit = 16,
75  Feature_HasV7ClrexBit = 18,
76  Feature_HasAcquireReleaseBit = 17,
77  Feature_HasMPBit = 2,
78  Feature_Has8MSecExtBit = 38,
79  Feature_HasZCZBit = 54,
80  Feature_UseNEONForFPBit = 70,
81  Feature_DontUseNEONForFPBit = 42,
82  Feature_IsThumbBit = 27,
83  Feature_IsThumb1OnlyBit = 28,
84  Feature_IsThumb2Bit = 32,
85  Feature_IsNotMClassBit = 36,
86  Feature_IsARMBit = 1,
87  Feature_IsWindowsBit = 30,
88  Feature_IsNotWindowsBit = 31,
89  Feature_IsReadTPHardBit = 62,
90  Feature_IsReadTPSoftBit = 21,
91  Feature_UseNaClTrapBit = 4,
92  Feature_DontUseNaClTrapBit = 5,
93  Feature_UseMovtBit = 37,
94  Feature_DontUseMovtBit = 24,
95  Feature_UseMovtInPicBit = 25,
96  Feature_DontUseMovtInPicBit = 26,
97  Feature_UseFPVMLxBit = 46,
98  Feature_UseMulOpsBit = 11,
99  Feature_UseFusedMACBit = 48,
100  Feature_HasFastVGETLNi32Bit = 55,
101  Feature_HasSlowVGETLNi32Bit = 68,
102  Feature_HasFastVDUP32Bit = 56,
103  Feature_HasSlowVDUP32Bit = 69,
104  Feature_UseVMOVSRBit = 45,
105  Feature_DontUseVMOVSRBit = 71,
106  Feature_IsLEBit = 63,
107  Feature_IsBEBit = 65,
108};
109
110PredicateBitset ARMInstructionSelector::
111computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
112  PredicateBitset Features;
113  if (!TM.Options.HonorSignDependentRoundingFPMath())
114    Features.set(Feature_NoHonorSignDependentRoundingBit);
115  if (Subtarget->hasV4TOps())
116    Features.set(Feature_HasV4TBit);
117  if (!Subtarget->hasV4TOps())
118    Features.set(Feature_NoV4TBit);
119  if (Subtarget->hasV5TOps())
120    Features.set(Feature_HasV5TBit);
121  if (!Subtarget->hasV5TOps())
122    Features.set(Feature_NoV5TBit);
123  if (Subtarget->hasV5TEOps())
124    Features.set(Feature_HasV5TEBit);
125  if (Subtarget->hasV6Ops())
126    Features.set(Feature_HasV6Bit);
127  if (!Subtarget->hasV6Ops())
128    Features.set(Feature_NoV6Bit);
129  if (Subtarget->hasV6MOps())
130    Features.set(Feature_HasV6MBit);
131  if (Subtarget->hasV8MBaselineOps())
132    Features.set(Feature_HasV8MBaselineBit);
133  if (Subtarget->hasV8_1MMainlineOps())
134    Features.set(Feature_HasV8_1MMainlineBit);
135  if (Subtarget->hasMVEIntegerOps())
136    Features.set(Feature_HasMVEIntBit);
137  if (Subtarget->hasMVEFloatOps())
138    Features.set(Feature_HasMVEFloatBit);
139  if (Subtarget->hasFPRegs())
140    Features.set(Feature_HasFPRegsBit);
141  if (Subtarget->hasFPRegs16())
142    Features.set(Feature_HasFPRegs16Bit);
143  if (Subtarget->hasFPRegs64())
144    Features.set(Feature_HasFPRegs64Bit);
145  if (Subtarget->hasV6T2Ops())
146    Features.set(Feature_HasV6T2Bit);
147  if (Subtarget->hasV6KOps())
148    Features.set(Feature_HasV6KBit);
149  if (Subtarget->hasV7Ops())
150    Features.set(Feature_HasV7Bit);
151  if (Subtarget->hasV8Ops())
152    Features.set(Feature_HasV8Bit);
153  if (!Subtarget->hasV8Ops())
154    Features.set(Feature_PreV8Bit);
155  if (Subtarget->hasV8_1aOps())
156    Features.set(Feature_HasV8_1aBit);
157  if (Subtarget->hasV8_3aOps())
158    Features.set(Feature_HasV8_3aBit);
159  if (!Subtarget->hasVFP2Base())
160    Features.set(Feature_NoVFPBit);
161  if (Subtarget->hasVFP2Base())
162    Features.set(Feature_HasVFP2Bit);
163  if (Subtarget->hasVFP3Base())
164    Features.set(Feature_HasVFP3Bit);
165  if (Subtarget->hasVFP4Base())
166    Features.set(Feature_HasVFP4Bit);
167  if (Subtarget->hasFP64())
168    Features.set(Feature_HasDPVFPBit);
169  if (Subtarget->hasFPARMv8Base())
170    Features.set(Feature_HasFPARMv8Bit);
171  if (Subtarget->hasNEON())
172    Features.set(Feature_HasNEONBit);
173  if (Subtarget->hasCrypto())
174    Features.set(Feature_HasCryptoBit);
175  if (Subtarget->hasDotProd())
176    Features.set(Feature_HasDotProdBit);
177  if (Subtarget->hasCRC())
178    Features.set(Feature_HasCRCBit);
179  if (Subtarget->hasFP16())
180    Features.set(Feature_HasFP16Bit);
181  if (Subtarget->hasFullFP16())
182    Features.set(Feature_HasFullFP16Bit);
183  if (Subtarget->hasDivideInThumbMode())
184    Features.set(Feature_HasDivideInThumbBit);
185  if (Subtarget->hasDivideInARMMode())
186    Features.set(Feature_HasDivideInARMBit);
187  if (Subtarget->hasDSP())
188    Features.set(Feature_HasDSPBit);
189  if (Subtarget->hasDataBarrier())
190    Features.set(Feature_HasDBBit);
191  if (Subtarget->hasV7Clrex())
192    Features.set(Feature_HasV7ClrexBit);
193  if (Subtarget->hasAcquireRelease())
194    Features.set(Feature_HasAcquireReleaseBit);
195  if (Subtarget->hasMPExtension())
196    Features.set(Feature_HasMPBit);
197  if (Subtarget->has8MSecExt())
198    Features.set(Feature_Has8MSecExtBit);
199  if (Subtarget->hasZeroCycleZeroing())
200    Features.set(Feature_HasZCZBit);
201  if (Subtarget->useNEONForSinglePrecisionFP())
202    Features.set(Feature_UseNEONForFPBit);
203  if (!Subtarget->useNEONForSinglePrecisionFP())
204    Features.set(Feature_DontUseNEONForFPBit);
205  if (Subtarget->isThumb())
206    Features.set(Feature_IsThumbBit);
207  if (Subtarget->isThumb1Only())
208    Features.set(Feature_IsThumb1OnlyBit);
209  if (Subtarget->isThumb2())
210    Features.set(Feature_IsThumb2Bit);
211  if (!Subtarget->isMClass())
212    Features.set(Feature_IsNotMClassBit);
213  if (!Subtarget->isThumb())
214    Features.set(Feature_IsARMBit);
215  if (Subtarget->isTargetWindows())
216    Features.set(Feature_IsWindowsBit);
217  if (!Subtarget->isTargetWindows())
218    Features.set(Feature_IsNotWindowsBit);
219  if (Subtarget->isReadTPHard())
220    Features.set(Feature_IsReadTPHardBit);
221  if (!Subtarget->isReadTPHard())
222    Features.set(Feature_IsReadTPSoftBit);
223  if (Subtarget->useNaClTrap())
224    Features.set(Feature_UseNaClTrapBit);
225  if (!Subtarget->useNaClTrap())
226    Features.set(Feature_DontUseNaClTrapBit);
227  if (Subtarget->useMulOps())
228    Features.set(Feature_UseMulOpsBit);
229  if (TM.Options.AllowFPOpFusion ==  FPOpFusion::Fast && Subtarget->useFPVFMx())
230    Features.set(Feature_UseFusedMACBit);
231  if (!Subtarget->hasSlowVGETLNi32())
232    Features.set(Feature_HasFastVGETLNi32Bit);
233  if (Subtarget->hasSlowVGETLNi32())
234    Features.set(Feature_HasSlowVGETLNi32Bit);
235  if (!Subtarget->hasSlowVDUP32())
236    Features.set(Feature_HasFastVDUP32Bit);
237  if (Subtarget->hasSlowVDUP32())
238    Features.set(Feature_HasSlowVDUP32Bit);
239  if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
240    Features.set(Feature_UseVMOVSRBit);
241  if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
242    Features.set(Feature_DontUseVMOVSRBit);
243  return Features;
244}
245
246void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
247  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget*)&MF.getSubtarget(), &MF);
248}
249PredicateBitset ARMInstructionSelector::
250computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
251  PredicateBitset Features;
252  if (Subtarget->useMovt())
253    Features.set(Feature_UseMovtBit);
254  if (!Subtarget->useMovt())
255    Features.set(Feature_DontUseMovtBit);
256  if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
257    Features.set(Feature_UseMovtInPicBit);
258  if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
259    Features.set(Feature_DontUseMovtInPicBit);
260  if (((Subtarget->useFPVMLx() &&  TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
261    Features.set(Feature_UseFPVMLxBit);
262  if (MF->getDataLayout().isLittleEndian())
263    Features.set(Feature_IsLEBit);
264  if (MF->getDataLayout().isBigEndian())
265    Features.set(Feature_IsBEBit);
266  return Features;
267}
268
269// LLT Objects.
270enum {
271  GILLT_s16,
272  GILLT_s32,
273  GILLT_s64,
274  GILLT_v2s32,
275  GILLT_v2s64,
276  GILLT_v4s1,
277  GILLT_v4s16,
278  GILLT_v4s32,
279  GILLT_v4s64,
280  GILLT_v8s1,
281  GILLT_v8s8,
282  GILLT_v8s16,
283  GILLT_v8s64,
284  GILLT_v16s1,
285  GILLT_v16s8,
286};
287const static size_t NumTypeObjects = 15;
288const static LLT TypeObjects[] = {
289  LLT::scalar(16),
290  LLT::scalar(32),
291  LLT::scalar(64),
292  LLT::vector(2, 32),
293  LLT::vector(2, 64),
294  LLT::vector(4, 1),
295  LLT::vector(4, 16),
296  LLT::vector(4, 32),
297  LLT::vector(4, 64),
298  LLT::vector(8, 1),
299  LLT::vector(8, 8),
300  LLT::vector(8, 16),
301  LLT::vector(8, 64),
302  LLT::vector(16, 1),
303  LLT::vector(16, 8),
304};
305
306// Feature bitsets.
307enum {
308  GIFBS_Invalid,
309  GIFBS_HasDotProd,
310  GIFBS_HasFP16,
311  GIFBS_HasFPARMv8,
312  GIFBS_HasFPRegs,
313  GIFBS_HasFullFP16,
314  GIFBS_HasMVEFloat,
315  GIFBS_HasMVEInt,
316  GIFBS_HasNEON,
317  GIFBS_HasVFP2,
318  GIFBS_HasVFP3,
319  GIFBS_HasVFP4,
320  GIFBS_IsARM,
321  GIFBS_IsThumb,
322  GIFBS_IsThumb2,
323  GIFBS_NoHonorSignDependentRounding,
324  GIFBS_DontUseNEONForFP_HasVFP2,
325  GIFBS_Has8MSecExt_IsThumb,
326  GIFBS_HasCrypto_HasV8,
327  GIFBS_HasDB_IsARM,
328  GIFBS_HasDB_IsThumb,
329  GIFBS_HasDPVFP_HasFPARMv8,
330  GIFBS_HasDPVFP_HasVFP2,
331  GIFBS_HasDPVFP_HasVFP3,
332  GIFBS_HasDPVFP_HasVFP4,
333  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
334  GIFBS_HasDSP_IsThumb2,
335  GIFBS_HasDivideInARM_IsARM,
336  GIFBS_HasFP16_HasNEON,
337  GIFBS_HasFPRegs_UseVMOVSR,
338  GIFBS_HasFullFP16_HasNEON,
339  GIFBS_HasMVEInt_HasV8_1MMainline,
340  GIFBS_HasMVEInt_IsBE,
341  GIFBS_HasMVEInt_IsLE,
342  GIFBS_HasNEON_HasV8,
343  GIFBS_HasNEON_HasV8_3a,
344  GIFBS_HasNEON_HasVFP4,
345  GIFBS_HasNEON_IsBE,
346  GIFBS_HasNEON_IsLE,
347  GIFBS_HasV5T_IsARM,
348  GIFBS_HasV5TE_IsARM,
349  GIFBS_HasV6_IsARM,
350  GIFBS_HasV6K_IsARM,
351  GIFBS_HasV6M_IsThumb,
352  GIFBS_HasV6T2_IsARM,
353  GIFBS_HasV7_IsARM,
354  GIFBS_HasV7Clrex_IsThumb,
355  GIFBS_HasV8MBaseline_IsThumb,
356  GIFBS_IsARM_NoV6,
357  GIFBS_IsARM_PreV8,
358  GIFBS_IsThumb_IsThumb1Only,
359  GIFBS_IsThumb_IsWindows,
360  GIFBS_IsThumb_UseMovt,
361  GIFBS_IsThumb2_PreV8,
362  GIFBS_IsThumb2_UseMulOps,
363  GIFBS_HasCRC_HasV8_IsARM,
364  GIFBS_HasCRC_HasV8_IsThumb2,
365  GIFBS_HasDSP_IsThumb2_UseMulOps,
366  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
367  GIFBS_HasFullFP16_HasNEON_HasV8,
368  GIFBS_HasFullFP16_HasNEON_HasV8_3a,
369  GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
370  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
371  GIFBS_HasV5TE_IsARM_UseMulOps,
372  GIFBS_HasV6_IsARM_UseMulOps,
373  GIFBS_HasV6_IsThumb_IsThumb1Only,
374  GIFBS_HasV6T2_IsARM_UseMulOps,
375  GIFBS_IsARM_NoV6_UseMulOps,
376};
377const static PredicateBitset FeatureBitsets[] {
378  {}, // GIFBS_Invalid
379  {Feature_HasDotProdBit, },
380  {Feature_HasFP16Bit, },
381  {Feature_HasFPARMv8Bit, },
382  {Feature_HasFPRegsBit, },
383  {Feature_HasFullFP16Bit, },
384  {Feature_HasMVEFloatBit, },
385  {Feature_HasMVEIntBit, },
386  {Feature_HasNEONBit, },
387  {Feature_HasVFP2Bit, },
388  {Feature_HasVFP3Bit, },
389  {Feature_HasVFP4Bit, },
390  {Feature_IsARMBit, },
391  {Feature_IsThumbBit, },
392  {Feature_IsThumb2Bit, },
393  {Feature_NoHonorSignDependentRoundingBit, },
394  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
395  {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
396  {Feature_HasCryptoBit, Feature_HasV8Bit, },
397  {Feature_HasDBBit, Feature_IsARMBit, },
398  {Feature_HasDBBit, Feature_IsThumbBit, },
399  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
400  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
401  {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
402  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
403  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
404  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
405  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
406  {Feature_HasFP16Bit, Feature_HasNEONBit, },
407  {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
408  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
409  {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
410  {Feature_HasMVEIntBit, Feature_IsBEBit, },
411  {Feature_HasMVEIntBit, Feature_IsLEBit, },
412  {Feature_HasNEONBit, Feature_HasV8Bit, },
413  {Feature_HasNEONBit, Feature_HasV8_3aBit, },
414  {Feature_HasNEONBit, Feature_HasVFP4Bit, },
415  {Feature_HasNEONBit, Feature_IsBEBit, },
416  {Feature_HasNEONBit, Feature_IsLEBit, },
417  {Feature_HasV5TBit, Feature_IsARMBit, },
418  {Feature_HasV5TEBit, Feature_IsARMBit, },
419  {Feature_HasV6Bit, Feature_IsARMBit, },
420  {Feature_HasV6KBit, Feature_IsARMBit, },
421  {Feature_HasV6MBit, Feature_IsThumbBit, },
422  {Feature_HasV6T2Bit, Feature_IsARMBit, },
423  {Feature_HasV7Bit, Feature_IsARMBit, },
424  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
425  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
426  {Feature_IsARMBit, Feature_NoV6Bit, },
427  {Feature_IsARMBit, Feature_PreV8Bit, },
428  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
429  {Feature_IsThumbBit, Feature_IsWindowsBit, },
430  {Feature_IsThumbBit, Feature_UseMovtBit, },
431  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
432  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
433  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
434  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
435  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
436  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
437  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
438  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
439  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
440  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
441  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
442  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
443  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
444  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
445  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
446};
447
448// ComplexPattern predicates.
449enum {
450  GICP_Invalid,
451};
452// See constructor for table contents
453
454// PatFrag predicates.
455enum {
456  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
457  GIPFP_I64_Predicate_VectorIndex32,
458  GIPFP_I64_Predicate_VectorIndex64,
459  GIPFP_I64_Predicate_VectorIndex8,
460  GIPFP_I64_Predicate_imm0_15,
461  GIPFP_I64_Predicate_imm0_239,
462  GIPFP_I64_Predicate_imm0_255,
463  GIPFP_I64_Predicate_imm0_31,
464  GIPFP_I64_Predicate_imm0_32,
465  GIPFP_I64_Predicate_imm0_4095,
466  GIPFP_I64_Predicate_imm0_63,
467  GIPFP_I64_Predicate_imm0_65535,
468  GIPFP_I64_Predicate_imm0_65535_neg,
469  GIPFP_I64_Predicate_imm0_7,
470  GIPFP_I64_Predicate_imm16,
471  GIPFP_I64_Predicate_imm16_31,
472  GIPFP_I64_Predicate_imm1_15,
473  GIPFP_I64_Predicate_imm1_16,
474  GIPFP_I64_Predicate_imm1_31,
475  GIPFP_I64_Predicate_imm1_7,
476  GIPFP_I64_Predicate_imm24b,
477  GIPFP_I64_Predicate_imm256_510,
478  GIPFP_I64_Predicate_imm32,
479  GIPFP_I64_Predicate_imm8,
480  GIPFP_I64_Predicate_imm8_255,
481  GIPFP_I64_Predicate_imm8_or_16,
482  GIPFP_I64_Predicate_imm_even,
483  GIPFP_I64_Predicate_imm_odd,
484  GIPFP_I64_Predicate_long_shift,
485  GIPFP_I64_Predicate_mod_imm,
486  GIPFP_I64_Predicate_pkh_asr_amt,
487  GIPFP_I64_Predicate_pkh_lsl_amt,
488  GIPFP_I64_Predicate_shr_imm16,
489  GIPFP_I64_Predicate_shr_imm32,
490  GIPFP_I64_Predicate_shr_imm64,
491  GIPFP_I64_Predicate_shr_imm8,
492  GIPFP_I64_Predicate_t2_so_imm,
493  GIPFP_I64_Predicate_t2_so_imm_neg,
494};
495bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
496  switch (PredicateID) {
497  case GIPFP_I64_Predicate_VectorIndex16: {
498
499  return ((uint64_t)Imm) < 4;
500
501    llvm_unreachable("ImmediateCode should have returned");
502    return false;
503  }
504  case GIPFP_I64_Predicate_VectorIndex32: {
505
506  return ((uint64_t)Imm) < 2;
507
508    llvm_unreachable("ImmediateCode should have returned");
509    return false;
510  }
511  case GIPFP_I64_Predicate_VectorIndex64: {
512
513  return ((uint64_t)Imm) < 1;
514
515    llvm_unreachable("ImmediateCode should have returned");
516    return false;
517  }
518  case GIPFP_I64_Predicate_VectorIndex8: {
519
520  return ((uint64_t)Imm) < 8;
521
522    llvm_unreachable("ImmediateCode should have returned");
523    return false;
524  }
525  case GIPFP_I64_Predicate_imm0_15: {
526
527  return Imm >= 0 && Imm < 16;
528
529    llvm_unreachable("ImmediateCode should have returned");
530    return false;
531  }
532  case GIPFP_I64_Predicate_imm0_239: {
533     return Imm >= 0 && Imm < 240;
534    llvm_unreachable("ImmediateCode should have returned");
535    return false;
536  }
537  case GIPFP_I64_Predicate_imm0_255: {
538     return Imm >= 0 && Imm < 256;
539    llvm_unreachable("ImmediateCode should have returned");
540    return false;
541  }
542  case GIPFP_I64_Predicate_imm0_31: {
543
544  return Imm >= 0 && Imm < 32;
545
546    llvm_unreachable("ImmediateCode should have returned");
547    return false;
548  }
549  case GIPFP_I64_Predicate_imm0_32: {
550
551  return Imm >= 0 && Imm < 33;
552
553    llvm_unreachable("ImmediateCode should have returned");
554    return false;
555  }
556  case GIPFP_I64_Predicate_imm0_4095: {
557
558  return Imm >= 0 && Imm < 4096;
559
560    llvm_unreachable("ImmediateCode should have returned");
561    return false;
562  }
563  case GIPFP_I64_Predicate_imm0_63: {
564
565  return Imm >= 0 && Imm < 64;
566
567    llvm_unreachable("ImmediateCode should have returned");
568    return false;
569  }
570  case GIPFP_I64_Predicate_imm0_65535: {
571
572  return Imm >= 0 && Imm < 65536;
573
574    llvm_unreachable("ImmediateCode should have returned");
575    return false;
576  }
577  case GIPFP_I64_Predicate_imm0_65535_neg: {
578
579  return -Imm >= 0 && -Imm < 65536;
580
581    llvm_unreachable("ImmediateCode should have returned");
582    return false;
583  }
584  case GIPFP_I64_Predicate_imm0_7: {
585
586  return Imm >= 0 && Imm < 8;
587
588    llvm_unreachable("ImmediateCode should have returned");
589    return false;
590  }
591  case GIPFP_I64_Predicate_imm16: {
592     return Imm == 16;
593    llvm_unreachable("ImmediateCode should have returned");
594    return false;
595  }
596  case GIPFP_I64_Predicate_imm16_31: {
597
598  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
599
600    llvm_unreachable("ImmediateCode should have returned");
601    return false;
602  }
603  case GIPFP_I64_Predicate_imm1_15: {
604     return Imm > 0 && Imm < 16;
605    llvm_unreachable("ImmediateCode should have returned");
606    return false;
607  }
608  case GIPFP_I64_Predicate_imm1_16: {
609
610    return Imm > 0 && Imm <= 16;
611
612    llvm_unreachable("ImmediateCode should have returned");
613    return false;
614  }
615  case GIPFP_I64_Predicate_imm1_31: {
616     return Imm > 0 && Imm < 32;
617    llvm_unreachable("ImmediateCode should have returned");
618    return false;
619  }
620  case GIPFP_I64_Predicate_imm1_7: {
621     return Imm > 0 && Imm < 8;
622    llvm_unreachable("ImmediateCode should have returned");
623    return false;
624  }
625  case GIPFP_I64_Predicate_imm24b: {
626
627  return Imm >= 0 && Imm <= 0xffffff;
628
629    llvm_unreachable("ImmediateCode should have returned");
630    return false;
631  }
632  case GIPFP_I64_Predicate_imm256_510: {
633
634  return Imm >= 256 && Imm < 511;
635
636    llvm_unreachable("ImmediateCode should have returned");
637    return false;
638  }
639  case GIPFP_I64_Predicate_imm32: {
640     return Imm == 32;
641    llvm_unreachable("ImmediateCode should have returned");
642    return false;
643  }
644  case GIPFP_I64_Predicate_imm8: {
645     return Imm == 8;
646    llvm_unreachable("ImmediateCode should have returned");
647    return false;
648  }
649  case GIPFP_I64_Predicate_imm8_255: {
650
651  return Imm >= 8 && Imm < 256;
652
653    llvm_unreachable("ImmediateCode should have returned");
654    return false;
655  }
656  case GIPFP_I64_Predicate_imm8_or_16: {
657     return Imm == 8 || Imm == 16;
658    llvm_unreachable("ImmediateCode should have returned");
659    return false;
660  }
661  case GIPFP_I64_Predicate_imm_even: {
662     return (Imm & 1) == 0;
663    llvm_unreachable("ImmediateCode should have returned");
664    return false;
665  }
666  case GIPFP_I64_Predicate_imm_odd: {
667     return (Imm & 1) == 1;
668    llvm_unreachable("ImmediateCode should have returned");
669    return false;
670  }
671  case GIPFP_I64_Predicate_long_shift: {
672     return Imm > 0 && Imm <= 32;
673    llvm_unreachable("ImmediateCode should have returned");
674    return false;
675  }
676  case GIPFP_I64_Predicate_mod_imm: {
677
678    return ARM_AM::getSOImmVal(Imm) != -1;
679
680    llvm_unreachable("ImmediateCode should have returned");
681    return false;
682  }
683  case GIPFP_I64_Predicate_pkh_asr_amt: {
684     return Imm > 0 && Imm <= 32;
685    llvm_unreachable("ImmediateCode should have returned");
686    return false;
687  }
688  case GIPFP_I64_Predicate_pkh_lsl_amt: {
689     return Imm >= 0 && Imm < 32;
690    llvm_unreachable("ImmediateCode should have returned");
691    return false;
692  }
693  case GIPFP_I64_Predicate_shr_imm16: {
694     return Imm > 0 && Imm <= 16;
695    llvm_unreachable("ImmediateCode should have returned");
696    return false;
697  }
698  case GIPFP_I64_Predicate_shr_imm32: {
699     return Imm > 0 && Imm <= 32;
700    llvm_unreachable("ImmediateCode should have returned");
701    return false;
702  }
703  case GIPFP_I64_Predicate_shr_imm64: {
704     return Imm > 0 && Imm <= 64;
705    llvm_unreachable("ImmediateCode should have returned");
706    return false;
707  }
708  case GIPFP_I64_Predicate_shr_imm8: {
709     return Imm > 0 && Imm <= 8;
710    llvm_unreachable("ImmediateCode should have returned");
711    return false;
712  }
713  case GIPFP_I64_Predicate_t2_so_imm: {
714
715    return ARM_AM::getT2SOImmVal(Imm) != -1;
716
717    llvm_unreachable("ImmediateCode should have returned");
718    return false;
719  }
720  case GIPFP_I64_Predicate_t2_so_imm_neg: {
721
722  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
723
724    llvm_unreachable("ImmediateCode should have returned");
725    return false;
726  }
727  }
728  llvm_unreachable("Unknown predicate");
729  return false;
730}
731bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
732  llvm_unreachable("Unknown predicate");
733  return false;
734}
735// PatFrag predicates.
736enum {
737  GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1,
738};
739bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
740  switch (PredicateID) {
741  case GIPFP_APInt_Predicate_arm_i32imm: {
742
743  if (Subtarget->useMovt())
744    return true;
745  return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue());
746
747    llvm_unreachable("ImmediateCode should have returned");
748    return false;
749  }
750  }
751  llvm_unreachable("Unknown predicate");
752  return false;
753}
754// PatFrag predicates.
755enum {
756  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
757  GIPFP_MI_Predicate_vfp_f32imm,
758  GIPFP_MI_Predicate_vfp_f64imm,
759};
760bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
761  const MachineFunction &MF = *MI.getParent()->getParent();
762  const MachineRegisterInfo &MRI = MF.getRegInfo();
763  (void)MRI;
764  switch (PredicateID) {
765  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
766
767    // There's better methods of implementing this check. IntImmLeaf<> would be
768    // equivalent and have less boilerplate but we need a test for C++
769    // predicates and this one causes new rules to be imported into GlobalISel
770    // without requiring additional features first.
771    const auto &MO = MI.getOperand(1);
772    if (!MO.isCImm())
773      return false;
774    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
775
776    llvm_unreachable("GISelPredicateCode should have returned");
777    return false;
778  }
779  case GIPFP_MI_Predicate_vfp_f32imm: {
780
781      const auto &MO = MI.getOperand(1);
782      if (!MO.isFPImm())
783        return false;
784      return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
785
786    llvm_unreachable("GISelPredicateCode should have returned");
787    return false;
788  }
789  case GIPFP_MI_Predicate_vfp_f64imm: {
790
791      const auto &MO = MI.getOperand(1);
792      if (!MO.isFPImm())
793        return false;
794      return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
795
796    llvm_unreachable("GISelPredicateCode should have returned");
797    return false;
798  }
799  }
800  llvm_unreachable("Unknown predicate");
801  return false;
802}
803
804ARMInstructionSelector::ComplexMatcherMemFn
805ARMInstructionSelector::ComplexPredicateFns[] = {
806  nullptr, // GICP_Invalid
807};
808
809// Custom renderers.
810enum {
811  GICR_Invalid,
812  GICR_renderVFPF32Imm,
813  GICR_renderVFPF64Imm,
814};
815ARMInstructionSelector::CustomRendererFn
816ARMInstructionSelector::CustomRenderers[] = {
817  nullptr, // GICR_Invalid
818  &ARMInstructionSelector::renderVFPF32Imm, // gi_vfp_f32imm
819  &ARMInstructionSelector::renderVFPF64Imm, // gi_vfp_f64imm
820};
821
822bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
823  MachineFunction &MF = *I.getParent()->getParent();
824  MachineRegisterInfo &MRI = MF.getRegInfo();
825  const PredicateBitset AvailableFeatures = getAvailableFeatures();
826  NewMIVector OutMIs;
827  State.MIs.clear();
828  State.MIs.push_back(&I);
829
830  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
831    return true;
832  }
833
834  return false;
835}
836
837const int64_t *ARMInstructionSelector::getMatchTable() const {
838  constexpr static int64_t MatchTable0[] = {
839    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 171, /*)*//*default:*//*Label 53*/ 102487,
840    /*TargetOpcode::G_ADD*//*Label 0*/ 141,
841    /*TargetOpcode::G_SUB*//*Label 1*/ 7399,
842    /*TargetOpcode::G_MUL*//*Label 2*/ 9654,
843    /*TargetOpcode::G_SDIV*//*Label 3*/ 10486,
844    /*TargetOpcode::G_UDIV*//*Label 4*/ 10588, 0, 0,
845    /*TargetOpcode::G_AND*//*Label 5*/ 10690,
846    /*TargetOpcode::G_OR*//*Label 6*/ 13033,
847    /*TargetOpcode::G_XOR*//*Label 7*/ 17856, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
848    /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 18957, 0, 0,
849    /*TargetOpcode::G_BITCAST*//*Label 9*/ 19251,
850    /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 28358,
851    /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 28605, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
852    /*TargetOpcode::G_INTRINSIC*//*Label 12*/ 28804,
853    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 13*/ 78400,
854    /*TargetOpcode::G_ANYEXT*//*Label 14*/ 86830,
855    /*TargetOpcode::G_TRUNC*//*Label 15*/ 86965,
856    /*TargetOpcode::G_CONSTANT*//*Label 16*/ 87244,
857    /*TargetOpcode::G_FCONSTANT*//*Label 17*/ 87441, 0, 0,
858    /*TargetOpcode::G_SEXT*//*Label 18*/ 87520, 0,
859    /*TargetOpcode::G_ZEXT*//*Label 19*/ 87655,
860    /*TargetOpcode::G_SHL*//*Label 20*/ 88177,
861    /*TargetOpcode::G_LSHR*//*Label 21*/ 88286,
862    /*TargetOpcode::G_ASHR*//*Label 22*/ 88346, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
863    /*TargetOpcode::G_SMULH*//*Label 23*/ 88564,
864    /*TargetOpcode::G_FADD*//*Label 24*/ 88666,
865    /*TargetOpcode::G_FSUB*//*Label 25*/ 89436,
866    /*TargetOpcode::G_FMUL*//*Label 26*/ 90198,
867    /*TargetOpcode::G_FMA*//*Label 27*/ 90915, 0,
868    /*TargetOpcode::G_FDIV*//*Label 28*/ 92276, 0, 0, 0, 0, 0, 0, 0,
869    /*TargetOpcode::G_FNEG*//*Label 29*/ 92442,
870    /*TargetOpcode::G_FPEXT*//*Label 30*/ 93712,
871    /*TargetOpcode::G_FPTRUNC*//*Label 31*/ 93872,
872    /*TargetOpcode::G_FPTOSI*//*Label 32*/ 94036,
873    /*TargetOpcode::G_FPTOUI*//*Label 33*/ 95151,
874    /*TargetOpcode::G_SITOFP*//*Label 34*/ 96266,
875    /*TargetOpcode::G_UITOFP*//*Label 35*/ 96717,
876    /*TargetOpcode::G_FABS*//*Label 36*/ 97168, 0, 0,
877    /*TargetOpcode::G_FMINNUM*//*Label 37*/ 97571,
878    /*TargetOpcode::G_FMAXNUM*//*Label 38*/ 97934, 0, 0, 0, 0, 0, 0,
879    /*TargetOpcode::G_SMIN*//*Label 39*/ 98297,
880    /*TargetOpcode::G_SMAX*//*Label 40*/ 98808,
881    /*TargetOpcode::G_UMIN*//*Label 41*/ 99319,
882    /*TargetOpcode::G_UMAX*//*Label 42*/ 99830,
883    /*TargetOpcode::G_BR*//*Label 43*/ 100341, 0, 0, 0, 0, 0, 0,
884    /*TargetOpcode::G_CTLZ*//*Label 44*/ 100405, 0,
885    /*TargetOpcode::G_CTPOP*//*Label 45*/ 100900,
886    /*TargetOpcode::G_BSWAP*//*Label 46*/ 100992,
887    /*TargetOpcode::G_BITREVERSE*//*Label 47*/ 101231,
888    /*TargetOpcode::G_FCEIL*//*Label 48*/ 101582, 0, 0,
889    /*TargetOpcode::G_FSQRT*//*Label 49*/ 101781,
890    /*TargetOpcode::G_FFLOOR*//*Label 50*/ 101911,
891    /*TargetOpcode::G_FRINT*//*Label 51*/ 102110,
892    /*TargetOpcode::G_FNEARBYINT*//*Label 52*/ 102357,
893    // Label 0: @141
894    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 63*/ 7398,
895    /*GILLT_s32*//*Label 54*/ 161,
896    /*GILLT_s64*//*Label 55*/ 2144,
897    /*GILLT_v2s32*//*Label 56*/ 2196,
898    /*GILLT_v2s64*//*Label 57*/ 2663, 0,
899    /*GILLT_v4s16*//*Label 58*/ 3392,
900    /*GILLT_v4s32*//*Label 59*/ 3859, 0, 0,
901    /*GILLT_v8s8*//*Label 60*/ 5121,
902    /*GILLT_v8s16*//*Label 61*/ 5588, 0, 0,
903    /*GILLT_v16s8*//*Label 62*/ 6850,
904    // Label 54: @161
905    GIM_Try, /*On fail goto*//*Label 64*/ 2143,
906      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
907      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
908      GIM_Try, /*On fail goto*//*Label 65*/ 238, // Rule ID 4388 //
909        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
911        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
912        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
913        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
914        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
915        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
916        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
918        GIM_CheckIsSafeToFold, /*InsnID*/1,
919        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
924        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
925        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
926        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
927        GIR_EraseFromParent, /*InsnID*/0,
928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
929        // GIR_Coverage, 4388,
930        GIR_Done,
931      // Label 65: @238
932      GIM_Try, /*On fail goto*//*Label 66*/ 305, // Rule ID 4389 //
933        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
935        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
936        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
937        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
938        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
939        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
940        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
942        GIM_CheckIsSafeToFold, /*InsnID*/1,
943        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
948        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
949        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
950        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
951        GIR_EraseFromParent, /*InsnID*/0,
952        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
953        // GIR_Coverage, 4389,
954        GIR_Done,
955      // Label 66: @305
956      GIM_Try, /*On fail goto*//*Label 67*/ 372, // Rule ID 4423 //
957        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
959        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
960        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
961        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
962        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
963        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
964        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
966        GIM_CheckIsSafeToFold, /*InsnID*/1,
967        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
968        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
972        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
973        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
974        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
975        GIR_EraseFromParent, /*InsnID*/0,
976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
977        // GIR_Coverage, 4423,
978        GIR_Done,
979      // Label 67: @372
980      GIM_Try, /*On fail goto*//*Label 68*/ 439, // Rule ID 4424 //
981        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
983        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
984        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
985        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
986        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
987        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
988        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
990        GIM_CheckIsSafeToFold, /*InsnID*/1,
991        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
996        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
997        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
998        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
999        GIR_EraseFromParent, /*InsnID*/0,
1000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1001        // GIR_Coverage, 4424,
1002        GIR_Done,
1003      // Label 68: @439
1004      GIM_Try, /*On fail goto*//*Label 69*/ 506, // Rule ID 1990 //
1005        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1008        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1009        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1010        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1011        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1012        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1013        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1014        GIM_CheckIsSafeToFold, /*InsnID*/1,
1015        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1020        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1021        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1022        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1023        GIR_EraseFromParent, /*InsnID*/0,
1024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1025        // GIR_Coverage, 1990,
1026        GIR_Done,
1027      // Label 69: @506
1028      GIM_Try, /*On fail goto*//*Label 70*/ 573, // Rule ID 1991 //
1029        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1032        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1033        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1034        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1035        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1036        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1037        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1038        GIM_CheckIsSafeToFold, /*InsnID*/1,
1039        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1044        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1046        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1047        GIR_EraseFromParent, /*InsnID*/0,
1048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1049        // GIR_Coverage, 1991,
1050        GIR_Done,
1051      // Label 70: @573
1052      GIM_Try, /*On fail goto*//*Label 71*/ 640, // Rule ID 2198 //
1053        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1056        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1057        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1058        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1059        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1060        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1061        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1062        GIM_CheckIsSafeToFold, /*InsnID*/1,
1063        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1064        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1068        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1069        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1070        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1071        GIR_EraseFromParent, /*InsnID*/0,
1072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1073        // GIR_Coverage, 2198,
1074        GIR_Done,
1075      // Label 71: @640
1076      GIM_Try, /*On fail goto*//*Label 72*/ 707, // Rule ID 2199 //
1077        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1080        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1081        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1082        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1083        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1084        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1085        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1086        GIM_CheckIsSafeToFold, /*InsnID*/1,
1087        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1092        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1093        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1094        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1095        GIR_EraseFromParent, /*InsnID*/0,
1096        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1097        // GIR_Coverage, 2199,
1098        GIR_Done,
1099      // Label 72: @707
1100      GIM_Try, /*On fail goto*//*Label 73*/ 817, // Rule ID 4170 //
1101        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1103        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1104        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1105        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1106        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1107        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1108        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1109        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1110        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1111        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1112        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1113        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1114        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1115        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1116        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1117        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1118        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1120        GIM_CheckIsSafeToFold, /*InsnID*/1,
1121        GIM_CheckIsSafeToFold, /*InsnID*/2,
1122        GIM_CheckIsSafeToFold, /*InsnID*/3,
1123        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1129        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1130        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1131        GIR_EraseFromParent, /*InsnID*/0,
1132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1133        // GIR_Coverage, 4170,
1134        GIR_Done,
1135      // Label 73: @817
1136      GIM_Try, /*On fail goto*//*Label 74*/ 927, // Rule ID 4207 //
1137        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1139        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1140        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1141        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1142        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1143        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1144        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1145        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1146        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1147        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1148        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1149        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1150        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1151        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1152        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1153        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1154        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1156        GIM_CheckIsSafeToFold, /*InsnID*/1,
1157        GIM_CheckIsSafeToFold, /*InsnID*/2,
1158        GIM_CheckIsSafeToFold, /*InsnID*/3,
1159        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1165        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1166        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1167        GIR_EraseFromParent, /*InsnID*/0,
1168        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1169        // GIR_Coverage, 4207,
1170        GIR_Done,
1171      // Label 74: @927
1172      GIM_Try, /*On fail goto*//*Label 75*/ 1037, // Rule ID 194 //
1173        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1176        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1177        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1178        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1179        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1180        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1181        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1182        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1183        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1184        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1185        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1186        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1187        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1188        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1189        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1190        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1191        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1192        GIM_CheckIsSafeToFold, /*InsnID*/1,
1193        GIM_CheckIsSafeToFold, /*InsnID*/2,
1194        GIM_CheckIsSafeToFold, /*InsnID*/3,
1195        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1196        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1201        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1202        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1203        GIR_EraseFromParent, /*InsnID*/0,
1204        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1205        // GIR_Coverage, 194,
1206        GIR_Done,
1207      // Label 75: @1037
1208      GIM_Try, /*On fail goto*//*Label 76*/ 1147, // Rule ID 527 //
1209        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1212        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1213        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1214        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1215        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1216        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1217        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1218        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1219        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1220        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1221        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1222        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1223        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1224        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1225        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1226        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1227        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1228        GIM_CheckIsSafeToFold, /*InsnID*/1,
1229        GIM_CheckIsSafeToFold, /*InsnID*/2,
1230        GIM_CheckIsSafeToFold, /*InsnID*/3,
1231        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1232        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1237        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1238        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1239        GIR_EraseFromParent, /*InsnID*/0,
1240        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1241        // GIR_Coverage, 527,
1242        GIR_Done,
1243      // Label 76: @1147
1244      GIM_Try, /*On fail goto*//*Label 77*/ 1201, // Rule ID 74 //
1245        GIM_CheckFeatures, GIFBS_IsARM,
1246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1248        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1249        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1250        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1251        // MIs[1] Operand 1
1252        // No operand predicates
1253        GIM_CheckIsSafeToFold, /*InsnID*/1,
1254        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1255        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1258        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1259        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1260        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1261        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1262        GIR_EraseFromParent, /*InsnID*/0,
1263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1264        // GIR_Coverage, 74,
1265        GIR_Done,
1266      // Label 77: @1201
1267      GIM_Try, /*On fail goto*//*Label 78*/ 1255, // Rule ID 413 //
1268        GIM_CheckFeatures, GIFBS_IsThumb2,
1269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1271        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1272        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1273        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1274        // MIs[1] Operand 1
1275        // No operand predicates
1276        GIM_CheckIsSafeToFold, /*InsnID*/1,
1277        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1278        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1281        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1282        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1283        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1284        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1285        GIR_EraseFromParent, /*InsnID*/0,
1286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287        // GIR_Coverage, 413,
1288        GIR_Done,
1289      // Label 78: @1255
1290      GIM_Try, /*On fail goto*//*Label 79*/ 1305, // Rule ID 414 //
1291        GIM_CheckFeatures, GIFBS_IsThumb2,
1292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1294        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1295        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1296        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1297        // MIs[1] Operand 1
1298        // No operand predicates
1299        GIM_CheckIsSafeToFold, /*InsnID*/1,
1300        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1304        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1305        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1306        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1307        GIR_EraseFromParent, /*InsnID*/0,
1308        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1309        // GIR_Coverage, 414,
1310        GIR_Done,
1311      // Label 79: @1305
1312      GIM_Try, /*On fail goto*//*Label 80*/ 1377, // Rule ID 173 //
1313        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1315        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1316        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1317        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1318        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1319        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1320        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1322        GIM_CheckIsSafeToFold, /*InsnID*/1,
1323        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1324        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1329        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1330        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1331        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1332        GIR_EraseFromParent, /*InsnID*/0,
1333        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334        // GIR_Coverage, 173,
1335        GIR_Done,
1336      // Label 80: @1377
1337      GIM_Try, /*On fail goto*//*Label 81*/ 1449, // Rule ID 174 //
1338        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1340        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1341        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1342        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1343        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1344        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1345        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1347        GIM_CheckIsSafeToFold, /*InsnID*/1,
1348        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1349        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1354        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1355        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1356        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1357        GIR_EraseFromParent, /*InsnID*/0,
1358        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1359        // GIR_Coverage, 174,
1360        GIR_Done,
1361      // Label 81: @1449
1362      GIM_Try, /*On fail goto*//*Label 82*/ 1517, // Rule ID 509 //
1363        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1365        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1366        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1367        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1368        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1369        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1370        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1372        GIM_CheckIsSafeToFold, /*InsnID*/1,
1373        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1374        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1379        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1380        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1381        GIR_EraseFromParent, /*InsnID*/0,
1382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1383        // GIR_Coverage, 509,
1384        GIR_Done,
1385      // Label 82: @1517
1386      GIM_Try, /*On fail goto*//*Label 83*/ 1585, // Rule ID 182 //
1387        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1389        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1390        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1391        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1392        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1393        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1394        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1396        GIM_CheckIsSafeToFold, /*InsnID*/1,
1397        // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra)  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1398        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1403        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1404        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1405        GIR_EraseFromParent, /*InsnID*/0,
1406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1407        // GIR_Coverage, 182,
1408        GIR_Done,
1409      // Label 83: @1585
1410      GIM_Try, /*On fail goto*//*Label 84*/ 1653, // Rule ID 515 //
1411        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1413        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1414        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1415        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1416        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1417        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1418        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1420        GIM_CheckIsSafeToFold, /*InsnID*/1,
1421        // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1422        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1427        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1428        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1429        GIR_EraseFromParent, /*InsnID*/0,
1430        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1431        // GIR_Coverage, 515,
1432        GIR_Done,
1433      // Label 84: @1653
1434      GIM_Try, /*On fail goto*//*Label 85*/ 1725, // Rule ID 4164 //
1435        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1438        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1439        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1440        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1441        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1442        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1443        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1444        GIM_CheckIsSafeToFold, /*InsnID*/1,
1445        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1446        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1451        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1452        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1453        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1454        GIR_EraseFromParent, /*InsnID*/0,
1455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1456        // GIR_Coverage, 4164,
1457        GIR_Done,
1458      // Label 85: @1725
1459      GIM_Try, /*On fail goto*//*Label 86*/ 1797, // Rule ID 4165 //
1460        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1463        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1464        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1465        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1466        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1467        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1468        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1469        GIM_CheckIsSafeToFold, /*InsnID*/1,
1470        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1471        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1476        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1477        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1478        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1479        GIR_EraseFromParent, /*InsnID*/0,
1480        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1481        // GIR_Coverage, 4165,
1482        GIR_Done,
1483      // Label 86: @1797
1484      GIM_Try, /*On fail goto*//*Label 87*/ 1865, // Rule ID 4202 //
1485        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1488        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1489        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1490        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1491        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1493        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1494        GIM_CheckIsSafeToFold, /*InsnID*/1,
1495        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1496        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1501        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1502        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1503        GIR_EraseFromParent, /*InsnID*/0,
1504        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1505        // GIR_Coverage, 4202,
1506        GIR_Done,
1507      // Label 87: @1865
1508      GIM_Try, /*On fail goto*//*Label 88*/ 1933, // Rule ID 4166 //
1509        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1512        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1513        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1514        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1515        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1516        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1517        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1518        GIM_CheckIsSafeToFold, /*InsnID*/1,
1519        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1526        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1527        GIR_EraseFromParent, /*InsnID*/0,
1528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1529        // GIR_Coverage, 4166,
1530        GIR_Done,
1531      // Label 88: @1933
1532      GIM_Try, /*On fail goto*//*Label 89*/ 2001, // Rule ID 4203 //
1533        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1536        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1537        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1538        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1539        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1540        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1541        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1542        GIM_CheckIsSafeToFold, /*InsnID*/1,
1543        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn))  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1544        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1549        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1550        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1551        GIR_EraseFromParent, /*InsnID*/0,
1552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1553        // GIR_Coverage, 4203,
1554        GIR_Done,
1555      // Label 89: @2001
1556      GIM_Try, /*On fail goto*//*Label 90*/ 2048, // Rule ID 75 //
1557        GIM_CheckFeatures, GIFBS_IsARM,
1558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1561        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1562        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1566        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1567        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1568        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1569        GIR_EraseFromParent, /*InsnID*/0,
1570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1571        // GIR_Coverage, 75,
1572        GIR_Done,
1573      // Label 90: @2048
1574      GIM_Try, /*On fail goto*//*Label 91*/ 2095, // Rule ID 415 //
1575        GIM_CheckFeatures, GIFBS_IsThumb2,
1576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1579        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1580        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1584        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1585        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1586        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1587        GIR_EraseFromParent, /*InsnID*/0,
1588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1589        // GIR_Coverage, 415,
1590        GIR_Done,
1591      // Label 91: @2095
1592      GIM_Try, /*On fail goto*//*Label 92*/ 2142, // Rule ID 4184 //
1593        GIM_CheckFeatures, GIFBS_IsThumb2,
1594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1597        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1602        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1603        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1604        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1605        GIR_EraseFromParent, /*InsnID*/0,
1606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1607        // GIR_Coverage, 4184,
1608        GIR_Done,
1609      // Label 92: @2142
1610      GIM_Reject,
1611    // Label 64: @2143
1612    GIM_Reject,
1613    // Label 55: @2144
1614    GIM_Try, /*On fail goto*//*Label 93*/ 2195, // Rule ID 777 //
1615      GIM_CheckFeatures, GIFBS_HasNEON,
1616      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1617      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1619      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1620      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1621      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1622      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1623      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1624      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1625      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1626      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1627      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1628      GIR_EraseFromParent, /*InsnID*/0,
1629      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1630      // GIR_Coverage, 777,
1631      GIR_Done,
1632    // Label 93: @2195
1633    GIM_Reject,
1634    // Label 56: @2196
1635    GIM_Try, /*On fail goto*//*Label 94*/ 2662,
1636      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1637      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1638      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1639      GIM_Try, /*On fail goto*//*Label 95*/ 2281, // Rule ID 4320 //
1640        GIM_CheckFeatures, GIFBS_HasNEON,
1641        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1642        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1643        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1644        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1645        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1646        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1647        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1648        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1650        GIM_CheckIsSafeToFold, /*InsnID*/1,
1651        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1652        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1657        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1658        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1659        GIR_EraseFromParent, /*InsnID*/0,
1660        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1661        // GIR_Coverage, 4320,
1662        GIR_Done,
1663      // Label 95: @2281
1664      GIM_Try, /*On fail goto*//*Label 96*/ 2352, // Rule ID 4326 //
1665        GIM_CheckFeatures, GIFBS_HasNEON,
1666        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1667        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1668        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1669        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1670        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1671        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1672        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1673        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1675        GIM_CheckIsSafeToFold, /*InsnID*/1,
1676        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1682        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1683        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1684        GIR_EraseFromParent, /*InsnID*/0,
1685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1686        // GIR_Coverage, 4326,
1687        GIR_Done,
1688      // Label 96: @2352
1689      GIM_Try, /*On fail goto*//*Label 97*/ 2423, // Rule ID 1169 //
1690        GIM_CheckFeatures, GIFBS_HasNEON,
1691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1692        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1693        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1694        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1695        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1696        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1697        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1698        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1699        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1700        GIM_CheckIsSafeToFold, /*InsnID*/1,
1701        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1702        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1707        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1708        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1709        GIR_EraseFromParent, /*InsnID*/0,
1710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1711        // GIR_Coverage, 1169,
1712        GIR_Done,
1713      // Label 97: @2423
1714      GIM_Try, /*On fail goto*//*Label 98*/ 2494, // Rule ID 1175 //
1715        GIM_CheckFeatures, GIFBS_HasNEON,
1716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1717        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1718        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1719        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1720        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1721        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1722        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1723        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1724        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1725        GIM_CheckIsSafeToFold, /*InsnID*/1,
1726        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1732        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1733        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1734        GIR_EraseFromParent, /*InsnID*/0,
1735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1736        // GIR_Coverage, 1175,
1737        GIR_Done,
1738      // Label 98: @2494
1739      GIM_Try, /*On fail goto*//*Label 99*/ 2558, // Rule ID 4250 //
1740        GIM_CheckFeatures, GIFBS_HasNEON,
1741        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1742        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1743        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1744        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1745        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1746        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1748        GIM_CheckIsSafeToFold, /*InsnID*/1,
1749        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1755        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1756        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1757        GIR_EraseFromParent, /*InsnID*/0,
1758        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1759        // GIR_Coverage, 4250,
1760        GIR_Done,
1761      // Label 99: @2558
1762      GIM_Try, /*On fail goto*//*Label 100*/ 2622, // Rule ID 892 //
1763        GIM_CheckFeatures, GIFBS_HasNEON,
1764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1765        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1766        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1767        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1768        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1769        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1770        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1771        GIM_CheckIsSafeToFold, /*InsnID*/1,
1772        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1778        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1779        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1780        GIR_EraseFromParent, /*InsnID*/0,
1781        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1782        // GIR_Coverage, 892,
1783        GIR_Done,
1784      // Label 100: @2622
1785      GIM_Try, /*On fail goto*//*Label 101*/ 2661, // Rule ID 773 //
1786        GIM_CheckFeatures, GIFBS_HasNEON,
1787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1789        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1794        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1795        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1796        GIR_EraseFromParent, /*InsnID*/0,
1797        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1798        // GIR_Coverage, 773,
1799        GIR_Done,
1800      // Label 101: @2661
1801      GIM_Reject,
1802    // Label 94: @2662
1803    GIM_Reject,
1804    // Label 57: @2663
1805    GIM_Try, /*On fail goto*//*Label 102*/ 3391,
1806      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1807      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1808      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1809      GIM_Try, /*On fail goto*//*Label 103*/ 2761, // Rule ID 4332 //
1810        GIM_CheckFeatures, GIFBS_HasNEON,
1811        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1812        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1813        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1814        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1815        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1816        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1817        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1818        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1819        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1820        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1821        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1823        GIM_CheckIsSafeToFold, /*InsnID*/1,
1824        GIM_CheckIsSafeToFold, /*InsnID*/2,
1825        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1831        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1832        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1833        GIR_EraseFromParent, /*InsnID*/0,
1834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1835        // GIR_Coverage, 4332,
1836        GIR_Done,
1837      // Label 103: @2761
1838      GIM_Try, /*On fail goto*//*Label 104*/ 2845, // Rule ID 4335 //
1839        GIM_CheckFeatures, GIFBS_HasNEON,
1840        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1841        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1842        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1843        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1844        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1845        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1846        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1847        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1848        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1849        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1850        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1852        GIM_CheckIsSafeToFold, /*InsnID*/1,
1853        GIM_CheckIsSafeToFold, /*InsnID*/2,
1854        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1860        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1861        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1862        GIR_EraseFromParent, /*InsnID*/0,
1863        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1864        // GIR_Coverage, 4335,
1865        GIR_Done,
1866      // Label 104: @2845
1867      GIM_Try, /*On fail goto*//*Label 105*/ 2929, // Rule ID 1181 //
1868        GIM_CheckFeatures, GIFBS_HasNEON,
1869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1870        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1871        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1872        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1873        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1874        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1875        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1876        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1877        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1878        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1879        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1880        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1881        GIM_CheckIsSafeToFold, /*InsnID*/1,
1882        GIM_CheckIsSafeToFold, /*InsnID*/2,
1883        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1884        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1889        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1890        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1891        GIR_EraseFromParent, /*InsnID*/0,
1892        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1893        // GIR_Coverage, 1181,
1894        GIR_Done,
1895      // Label 105: @2929
1896      GIM_Try, /*On fail goto*//*Label 106*/ 3013, // Rule ID 1184 //
1897        GIM_CheckFeatures, GIFBS_HasNEON,
1898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1899        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1900        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1901        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1902        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1903        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1904        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1905        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1906        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1907        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1908        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1909        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1910        GIM_CheckIsSafeToFold, /*InsnID*/1,
1911        GIM_CheckIsSafeToFold, /*InsnID*/2,
1912        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1918        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1919        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1920        GIR_EraseFromParent, /*InsnID*/0,
1921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1922        // GIR_Coverage, 1184,
1923        GIR_Done,
1924      // Label 106: @3013
1925      GIM_Try, /*On fail goto*//*Label 107*/ 3078, // Rule ID 785 //
1926        GIM_CheckFeatures, GIFBS_HasNEON,
1927        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1928        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1929        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1930        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1931        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1932        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1933        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1934        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1935        GIM_CheckIsSafeToFold, /*InsnID*/1,
1936        GIM_CheckIsSafeToFold, /*InsnID*/2,
1937        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1942        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1943        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1944        GIR_EraseFromParent, /*InsnID*/0,
1945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1946        // GIR_Coverage, 785,
1947        GIR_Done,
1948      // Label 107: @3078
1949      GIM_Try, /*On fail goto*//*Label 108*/ 3143, // Rule ID 788 //
1950        GIM_CheckFeatures, GIFBS_HasNEON,
1951        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1952        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1953        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1954        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1955        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1956        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1957        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1958        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1959        GIM_CheckIsSafeToFold, /*InsnID*/1,
1960        GIM_CheckIsSafeToFold, /*InsnID*/2,
1961        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1966        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1967        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1968        GIR_EraseFromParent, /*InsnID*/0,
1969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1970        // GIR_Coverage, 788,
1971        GIR_Done,
1972      // Label 108: @3143
1973      GIM_Try, /*On fail goto*//*Label 109*/ 3195, // Rule ID 4226 //
1974        GIM_CheckFeatures, GIFBS_HasNEON,
1975        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1976        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1977        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1978        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1980        GIM_CheckIsSafeToFold, /*InsnID*/1,
1981        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1986        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1987        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1988        GIR_EraseFromParent, /*InsnID*/0,
1989        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1990        // GIR_Coverage, 4226,
1991        GIR_Done,
1992      // Label 109: @3195
1993      GIM_Try, /*On fail goto*//*Label 110*/ 3247, // Rule ID 4229 //
1994        GIM_CheckFeatures, GIFBS_HasNEON,
1995        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1996        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1997        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1998        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2000        GIM_CheckIsSafeToFold, /*InsnID*/1,
2001        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2008        GIR_EraseFromParent, /*InsnID*/0,
2009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2010        // GIR_Coverage, 4229,
2011        GIR_Done,
2012      // Label 110: @3247
2013      GIM_Try, /*On fail goto*//*Label 111*/ 3299, // Rule ID 791 //
2014        GIM_CheckFeatures, GIFBS_HasNEON,
2015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2016        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2017        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2018        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2019        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2020        GIM_CheckIsSafeToFold, /*InsnID*/1,
2021        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2022        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2026        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2027        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2028        GIR_EraseFromParent, /*InsnID*/0,
2029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2030        // GIR_Coverage, 791,
2031        GIR_Done,
2032      // Label 111: @3299
2033      GIM_Try, /*On fail goto*//*Label 112*/ 3351, // Rule ID 794 //
2034        GIM_CheckFeatures, GIFBS_HasNEON,
2035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2036        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2037        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2038        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2039        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2040        GIM_CheckIsSafeToFold, /*InsnID*/1,
2041        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2046        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2047        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2048        GIR_EraseFromParent, /*InsnID*/0,
2049        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2050        // GIR_Coverage, 794,
2051        GIR_Done,
2052      // Label 112: @3351
2053      GIM_Try, /*On fail goto*//*Label 113*/ 3390, // Rule ID 778 //
2054        GIM_CheckFeatures, GIFBS_HasNEON,
2055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2057        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
2059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2062        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2063        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2064        GIR_EraseFromParent, /*InsnID*/0,
2065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2066        // GIR_Coverage, 778,
2067        GIR_Done,
2068      // Label 113: @3390
2069      GIM_Reject,
2070    // Label 102: @3391
2071    GIM_Reject,
2072    // Label 58: @3392
2073    GIM_Try, /*On fail goto*//*Label 114*/ 3858,
2074      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2075      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2077      GIM_Try, /*On fail goto*//*Label 115*/ 3477, // Rule ID 4319 //
2078        GIM_CheckFeatures, GIFBS_HasNEON,
2079        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2080        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2081        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2082        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2083        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2084        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2085        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2086        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2088        GIM_CheckIsSafeToFold, /*InsnID*/1,
2089        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2095        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2096        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2097        GIR_EraseFromParent, /*InsnID*/0,
2098        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2099        // GIR_Coverage, 4319,
2100        GIR_Done,
2101      // Label 115: @3477
2102      GIM_Try, /*On fail goto*//*Label 116*/ 3548, // Rule ID 4325 //
2103        GIM_CheckFeatures, GIFBS_HasNEON,
2104        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2105        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2106        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2107        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2108        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2109        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2110        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2111        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2113        GIM_CheckIsSafeToFold, /*InsnID*/1,
2114        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2120        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2121        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2122        GIR_EraseFromParent, /*InsnID*/0,
2123        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2124        // GIR_Coverage, 4325,
2125        GIR_Done,
2126      // Label 116: @3548
2127      GIM_Try, /*On fail goto*//*Label 117*/ 3619, // Rule ID 1168 //
2128        GIM_CheckFeatures, GIFBS_HasNEON,
2129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2130        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2131        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2132        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2133        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2134        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2135        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2136        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2137        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2138        GIM_CheckIsSafeToFold, /*InsnID*/1,
2139        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2140        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2145        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2146        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2147        GIR_EraseFromParent, /*InsnID*/0,
2148        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2149        // GIR_Coverage, 1168,
2150        GIR_Done,
2151      // Label 117: @3619
2152      GIM_Try, /*On fail goto*//*Label 118*/ 3690, // Rule ID 1174 //
2153        GIM_CheckFeatures, GIFBS_HasNEON,
2154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2155        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2156        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2157        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2158        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2159        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2160        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2161        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2162        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2163        GIM_CheckIsSafeToFold, /*InsnID*/1,
2164        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2170        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2171        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2172        GIR_EraseFromParent, /*InsnID*/0,
2173        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2174        // GIR_Coverage, 1174,
2175        GIR_Done,
2176      // Label 118: @3690
2177      GIM_Try, /*On fail goto*//*Label 119*/ 3754, // Rule ID 4249 //
2178        GIM_CheckFeatures, GIFBS_HasNEON,
2179        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2180        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2181        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2182        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2183        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2184        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2186        GIM_CheckIsSafeToFold, /*InsnID*/1,
2187        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2193        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2194        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2195        GIR_EraseFromParent, /*InsnID*/0,
2196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2197        // GIR_Coverage, 4249,
2198        GIR_Done,
2199      // Label 119: @3754
2200      GIM_Try, /*On fail goto*//*Label 120*/ 3818, // Rule ID 891 //
2201        GIM_CheckFeatures, GIFBS_HasNEON,
2202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2203        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2204        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2205        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2206        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2207        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2208        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2209        GIM_CheckIsSafeToFold, /*InsnID*/1,
2210        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2216        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2217        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2218        GIR_EraseFromParent, /*InsnID*/0,
2219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2220        // GIR_Coverage, 891,
2221        GIR_Done,
2222      // Label 120: @3818
2223      GIM_Try, /*On fail goto*//*Label 121*/ 3857, // Rule ID 772 //
2224        GIM_CheckFeatures, GIFBS_HasNEON,
2225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2227        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
2229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2232        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2233        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2234        GIR_EraseFromParent, /*InsnID*/0,
2235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2236        // GIR_Coverage, 772,
2237        GIR_Done,
2238      // Label 121: @3857
2239      GIM_Reject,
2240    // Label 114: @3858
2241    GIM_Reject,
2242    // Label 59: @3859
2243    GIM_Try, /*On fail goto*//*Label 122*/ 5120,
2244      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2245      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2246      GIM_Try, /*On fail goto*//*Label 123*/ 3957, // Rule ID 4331 //
2247        GIM_CheckFeatures, GIFBS_HasNEON,
2248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2249        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2250        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2251        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2252        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2253        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2254        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2255        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2256        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2257        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2258        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2259        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2261        GIM_CheckIsSafeToFold, /*InsnID*/1,
2262        GIM_CheckIsSafeToFold, /*InsnID*/2,
2263        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2269        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2270        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2271        GIR_EraseFromParent, /*InsnID*/0,
2272        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2273        // GIR_Coverage, 4331,
2274        GIR_Done,
2275      // Label 123: @3957
2276      GIM_Try, /*On fail goto*//*Label 124*/ 4045, // Rule ID 4334 //
2277        GIM_CheckFeatures, GIFBS_HasNEON,
2278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2279        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2280        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2281        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2282        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2283        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2284        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2285        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2286        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2287        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2288        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2289        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2291        GIM_CheckIsSafeToFold, /*InsnID*/1,
2292        GIM_CheckIsSafeToFold, /*InsnID*/2,
2293        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2294        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2299        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2300        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2301        GIR_EraseFromParent, /*InsnID*/0,
2302        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2303        // GIR_Coverage, 4334,
2304        GIR_Done,
2305      // Label 124: @4045
2306      GIM_Try, /*On fail goto*//*Label 125*/ 4133, // Rule ID 1180 //
2307        GIM_CheckFeatures, GIFBS_HasNEON,
2308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2310        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2311        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2312        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2313        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2314        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2315        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2316        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2317        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2318        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2319        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2320        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2321        GIM_CheckIsSafeToFold, /*InsnID*/1,
2322        GIM_CheckIsSafeToFold, /*InsnID*/2,
2323        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2324        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2329        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2330        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2331        GIR_EraseFromParent, /*InsnID*/0,
2332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2333        // GIR_Coverage, 1180,
2334        GIR_Done,
2335      // Label 125: @4133
2336      GIM_Try, /*On fail goto*//*Label 126*/ 4221, // Rule ID 1183 //
2337        GIM_CheckFeatures, GIFBS_HasNEON,
2338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2340        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2341        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2342        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2343        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2344        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2345        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2346        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2347        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2348        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2349        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2350        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2351        GIM_CheckIsSafeToFold, /*InsnID*/1,
2352        GIM_CheckIsSafeToFold, /*InsnID*/2,
2353        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2359        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2360        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2361        GIR_EraseFromParent, /*InsnID*/0,
2362        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2363        // GIR_Coverage, 1183,
2364        GIR_Done,
2365      // Label 126: @4221
2366      GIM_Try, /*On fail goto*//*Label 127*/ 4296, // Rule ID 4323 //
2367        GIM_CheckFeatures, GIFBS_HasNEON,
2368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2369        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2370        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2371        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2372        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2373        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2374        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2375        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2376        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2378        GIM_CheckIsSafeToFold, /*InsnID*/1,
2379        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2385        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2386        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2387        GIR_EraseFromParent, /*InsnID*/0,
2388        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2389        // GIR_Coverage, 4323,
2390        GIR_Done,
2391      // Label 127: @4296
2392      GIM_Try, /*On fail goto*//*Label 128*/ 4371, // Rule ID 4329 //
2393        GIM_CheckFeatures, GIFBS_HasNEON,
2394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2395        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2396        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2397        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2398        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2399        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2400        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2401        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2402        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2404        GIM_CheckIsSafeToFold, /*InsnID*/1,
2405        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2406        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2411        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2412        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2413        GIR_EraseFromParent, /*InsnID*/0,
2414        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2415        // GIR_Coverage, 4329,
2416        GIR_Done,
2417      // Label 128: @4371
2418      GIM_Try, /*On fail goto*//*Label 129*/ 4446, // Rule ID 1172 //
2419        GIM_CheckFeatures, GIFBS_HasNEON,
2420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2422        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2423        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2424        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2425        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2426        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2427        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2428        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2429        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2430        GIM_CheckIsSafeToFold, /*InsnID*/1,
2431        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2437        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2438        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2439        GIR_EraseFromParent, /*InsnID*/0,
2440        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2441        // GIR_Coverage, 1172,
2442        GIR_Done,
2443      // Label 129: @4446
2444      GIM_Try, /*On fail goto*//*Label 130*/ 4521, // Rule ID 1178 //
2445        GIM_CheckFeatures, GIFBS_HasNEON,
2446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2448        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2449        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2450        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2451        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2452        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2453        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2454        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2455        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2456        GIM_CheckIsSafeToFold, /*InsnID*/1,
2457        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2463        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2464        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2465        GIR_EraseFromParent, /*InsnID*/0,
2466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2467        // GIR_Coverage, 1178,
2468        GIR_Done,
2469      // Label 130: @4521
2470      GIM_Try, /*On fail goto*//*Label 131*/ 4590, // Rule ID 784 //
2471        GIM_CheckFeatures, GIFBS_HasNEON,
2472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2473        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2474        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2475        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2476        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2477        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2478        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2479        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2480        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2481        GIM_CheckIsSafeToFold, /*InsnID*/1,
2482        GIM_CheckIsSafeToFold, /*InsnID*/2,
2483        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2484        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2488        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2489        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2490        GIR_EraseFromParent, /*InsnID*/0,
2491        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2492        // GIR_Coverage, 784,
2493        GIR_Done,
2494      // Label 131: @4590
2495      GIM_Try, /*On fail goto*//*Label 132*/ 4659, // Rule ID 787 //
2496        GIM_CheckFeatures, GIFBS_HasNEON,
2497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2498        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2499        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2500        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2501        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2502        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2503        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2504        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2505        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2506        GIM_CheckIsSafeToFold, /*InsnID*/1,
2507        GIM_CheckIsSafeToFold, /*InsnID*/2,
2508        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2509        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2513        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2514        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2515        GIR_EraseFromParent, /*InsnID*/0,
2516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2517        // GIR_Coverage, 787,
2518        GIR_Done,
2519      // Label 132: @4659
2520      GIM_Try, /*On fail goto*//*Label 133*/ 4727, // Rule ID 4253 //
2521        GIM_CheckFeatures, GIFBS_HasNEON,
2522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2523        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2524        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2525        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2526        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2527        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2528        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2530        GIM_CheckIsSafeToFold, /*InsnID*/1,
2531        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2532        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2537        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2538        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2539        GIR_EraseFromParent, /*InsnID*/0,
2540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2541        // GIR_Coverage, 4253,
2542        GIR_Done,
2543      // Label 133: @4727
2544      GIM_Try, /*On fail goto*//*Label 134*/ 4783, // Rule ID 4225 //
2545        GIM_CheckFeatures, GIFBS_HasNEON,
2546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2547        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2548        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2549        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2550        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2552        GIM_CheckIsSafeToFold, /*InsnID*/1,
2553        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2554        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2558        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2559        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2560        GIR_EraseFromParent, /*InsnID*/0,
2561        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2562        // GIR_Coverage, 4225,
2563        GIR_Done,
2564      // Label 134: @4783
2565      GIM_Try, /*On fail goto*//*Label 135*/ 4839, // Rule ID 4228 //
2566        GIM_CheckFeatures, GIFBS_HasNEON,
2567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2568        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2569        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2570        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2571        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2573        GIM_CheckIsSafeToFold, /*InsnID*/1,
2574        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2575        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2579        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2580        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2581        GIR_EraseFromParent, /*InsnID*/0,
2582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2583        // GIR_Coverage, 4228,
2584        GIR_Done,
2585      // Label 135: @4839
2586      GIM_Try, /*On fail goto*//*Label 136*/ 4907, // Rule ID 895 //
2587        GIM_CheckFeatures, GIFBS_HasNEON,
2588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2590        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2591        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2592        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2593        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2594        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2595        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2596        GIM_CheckIsSafeToFold, /*InsnID*/1,
2597        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2603        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2604        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2605        GIR_EraseFromParent, /*InsnID*/0,
2606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2607        // GIR_Coverage, 895,
2608        GIR_Done,
2609      // Label 136: @4907
2610      GIM_Try, /*On fail goto*//*Label 137*/ 4963, // Rule ID 790 //
2611        GIM_CheckFeatures, GIFBS_HasNEON,
2612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2614        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2615        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2616        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2617        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2618        GIM_CheckIsSafeToFold, /*InsnID*/1,
2619        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2624        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2625        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2626        GIR_EraseFromParent, /*InsnID*/0,
2627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2628        // GIR_Coverage, 790,
2629        GIR_Done,
2630      // Label 137: @4963
2631      GIM_Try, /*On fail goto*//*Label 138*/ 5019, // Rule ID 793 //
2632        GIM_CheckFeatures, GIFBS_HasNEON,
2633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2635        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2636        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2637        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2638        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2639        GIM_CheckIsSafeToFold, /*InsnID*/1,
2640        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2645        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2646        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2647        GIR_EraseFromParent, /*InsnID*/0,
2648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2649        // GIR_Coverage, 793,
2650        GIR_Done,
2651      // Label 138: @5019
2652      GIM_Try, /*On fail goto*//*Label 139*/ 5062, // Rule ID 776 //
2653        GIM_CheckFeatures, GIFBS_HasNEON,
2654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2657        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2662        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2663        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2664        GIR_EraseFromParent, /*InsnID*/0,
2665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2666        // GIR_Coverage, 776,
2667        GIR_Done,
2668      // Label 139: @5062
2669      GIM_Try, /*On fail goto*//*Label 140*/ 5119, // Rule ID 3020 //
2670        GIM_CheckFeatures, GIFBS_HasMVEInt,
2671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
2672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
2673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
2674        // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
2675        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
2676        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
2677        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
2678        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi32,
2679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
2680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
2681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
2682        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2683        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2684        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2685        GIR_EraseFromParent, /*InsnID*/0,
2686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2687        // GIR_Coverage, 3020,
2688        GIR_Done,
2689      // Label 140: @5119
2690      GIM_Reject,
2691    // Label 122: @5120
2692    GIM_Reject,
2693    // Label 60: @5121
2694    GIM_Try, /*On fail goto*//*Label 141*/ 5587,
2695      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2696      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2698      GIM_Try, /*On fail goto*//*Label 142*/ 5206, // Rule ID 4318 //
2699        GIM_CheckFeatures, GIFBS_HasNEON,
2700        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2701        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2702        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2703        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2704        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2705        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2706        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2707        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2709        GIM_CheckIsSafeToFold, /*InsnID*/1,
2710        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2716        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2717        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2718        GIR_EraseFromParent, /*InsnID*/0,
2719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2720        // GIR_Coverage, 4318,
2721        GIR_Done,
2722      // Label 142: @5206
2723      GIM_Try, /*On fail goto*//*Label 143*/ 5277, // Rule ID 4324 //
2724        GIM_CheckFeatures, GIFBS_HasNEON,
2725        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2726        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2727        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2728        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2729        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2730        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2731        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2732        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2734        GIM_CheckIsSafeToFold, /*InsnID*/1,
2735        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2736        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2741        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2742        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2743        GIR_EraseFromParent, /*InsnID*/0,
2744        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2745        // GIR_Coverage, 4324,
2746        GIR_Done,
2747      // Label 143: @5277
2748      GIM_Try, /*On fail goto*//*Label 144*/ 5348, // Rule ID 1167 //
2749        GIM_CheckFeatures, GIFBS_HasNEON,
2750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2751        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2752        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2753        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2754        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2755        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2756        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2757        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2758        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2759        GIM_CheckIsSafeToFold, /*InsnID*/1,
2760        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2766        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2767        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2768        GIR_EraseFromParent, /*InsnID*/0,
2769        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2770        // GIR_Coverage, 1167,
2771        GIR_Done,
2772      // Label 144: @5348
2773      GIM_Try, /*On fail goto*//*Label 145*/ 5419, // Rule ID 1173 //
2774        GIM_CheckFeatures, GIFBS_HasNEON,
2775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2776        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2777        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2778        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2779        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2780        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2781        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2782        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2783        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2784        GIM_CheckIsSafeToFold, /*InsnID*/1,
2785        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2791        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2792        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2793        GIR_EraseFromParent, /*InsnID*/0,
2794        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2795        // GIR_Coverage, 1173,
2796        GIR_Done,
2797      // Label 145: @5419
2798      GIM_Try, /*On fail goto*//*Label 146*/ 5483, // Rule ID 4248 //
2799        GIM_CheckFeatures, GIFBS_HasNEON,
2800        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2801        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2802        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2803        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2804        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2805        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2807        GIM_CheckIsSafeToFold, /*InsnID*/1,
2808        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2815        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2816        GIR_EraseFromParent, /*InsnID*/0,
2817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2818        // GIR_Coverage, 4248,
2819        GIR_Done,
2820      // Label 146: @5483
2821      GIM_Try, /*On fail goto*//*Label 147*/ 5547, // Rule ID 890 //
2822        GIM_CheckFeatures, GIFBS_HasNEON,
2823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2824        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2825        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2826        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2827        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2828        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2829        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2830        GIM_CheckIsSafeToFold, /*InsnID*/1,
2831        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2837        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2838        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2839        GIR_EraseFromParent, /*InsnID*/0,
2840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2841        // GIR_Coverage, 890,
2842        GIR_Done,
2843      // Label 147: @5547
2844      GIM_Try, /*On fail goto*//*Label 148*/ 5586, // Rule ID 771 //
2845        GIM_CheckFeatures, GIFBS_HasNEON,
2846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2848        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2849        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2853        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2854        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2855        GIR_EraseFromParent, /*InsnID*/0,
2856        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2857        // GIR_Coverage, 771,
2858        GIR_Done,
2859      // Label 148: @5586
2860      GIM_Reject,
2861    // Label 141: @5587
2862    GIM_Reject,
2863    // Label 61: @5588
2864    GIM_Try, /*On fail goto*//*Label 149*/ 6849,
2865      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2866      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2867      GIM_Try, /*On fail goto*//*Label 150*/ 5686, // Rule ID 4330 //
2868        GIM_CheckFeatures, GIFBS_HasNEON,
2869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2870        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2871        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2872        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2873        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2874        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2875        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2876        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2877        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2878        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2879        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2880        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2882        GIM_CheckIsSafeToFold, /*InsnID*/1,
2883        GIM_CheckIsSafeToFold, /*InsnID*/2,
2884        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2885        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2891        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2892        GIR_EraseFromParent, /*InsnID*/0,
2893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2894        // GIR_Coverage, 4330,
2895        GIR_Done,
2896      // Label 150: @5686
2897      GIM_Try, /*On fail goto*//*Label 151*/ 5774, // Rule ID 4333 //
2898        GIM_CheckFeatures, GIFBS_HasNEON,
2899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2900        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2901        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2902        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2903        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2904        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2905        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2906        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2907        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2908        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2909        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2910        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2912        GIM_CheckIsSafeToFold, /*InsnID*/1,
2913        GIM_CheckIsSafeToFold, /*InsnID*/2,
2914        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2920        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2921        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2922        GIR_EraseFromParent, /*InsnID*/0,
2923        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2924        // GIR_Coverage, 4333,
2925        GIR_Done,
2926      // Label 151: @5774
2927      GIM_Try, /*On fail goto*//*Label 152*/ 5862, // Rule ID 1179 //
2928        GIM_CheckFeatures, GIFBS_HasNEON,
2929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2931        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2932        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2933        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2934        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2935        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2936        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2937        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2938        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2939        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2940        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2941        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2942        GIM_CheckIsSafeToFold, /*InsnID*/1,
2943        GIM_CheckIsSafeToFold, /*InsnID*/2,
2944        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2945        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2950        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2951        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2952        GIR_EraseFromParent, /*InsnID*/0,
2953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2954        // GIR_Coverage, 1179,
2955        GIR_Done,
2956      // Label 152: @5862
2957      GIM_Try, /*On fail goto*//*Label 153*/ 5950, // Rule ID 1182 //
2958        GIM_CheckFeatures, GIFBS_HasNEON,
2959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2961        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2962        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2963        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2964        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2965        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2966        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2967        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2968        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2969        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2970        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2971        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2972        GIM_CheckIsSafeToFold, /*InsnID*/1,
2973        GIM_CheckIsSafeToFold, /*InsnID*/2,
2974        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2980        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2981        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
2982        GIR_EraseFromParent, /*InsnID*/0,
2983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2984        // GIR_Coverage, 1182,
2985        GIR_Done,
2986      // Label 153: @5950
2987      GIM_Try, /*On fail goto*//*Label 154*/ 6025, // Rule ID 4322 //
2988        GIM_CheckFeatures, GIFBS_HasNEON,
2989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2990        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2991        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2992        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2993        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2994        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2995        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2996        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2997        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2999        GIM_CheckIsSafeToFold, /*InsnID*/1,
3000        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3008        GIR_EraseFromParent, /*InsnID*/0,
3009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3010        // GIR_Coverage, 4322,
3011        GIR_Done,
3012      // Label 154: @6025
3013      GIM_Try, /*On fail goto*//*Label 155*/ 6100, // Rule ID 4328 //
3014        GIM_CheckFeatures, GIFBS_HasNEON,
3015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3016        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3017        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3018        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3019        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3020        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3021        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3022        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3023        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3025        GIM_CheckIsSafeToFold, /*InsnID*/1,
3026        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3032        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3033        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3034        GIR_EraseFromParent, /*InsnID*/0,
3035        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3036        // GIR_Coverage, 4328,
3037        GIR_Done,
3038      // Label 155: @6100
3039      GIM_Try, /*On fail goto*//*Label 156*/ 6175, // Rule ID 1171 //
3040        GIM_CheckFeatures, GIFBS_HasNEON,
3041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3043        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3044        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3045        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3046        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3047        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3048        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3049        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3050        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3051        GIM_CheckIsSafeToFold, /*InsnID*/1,
3052        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3053        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3058        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3059        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3060        GIR_EraseFromParent, /*InsnID*/0,
3061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3062        // GIR_Coverage, 1171,
3063        GIR_Done,
3064      // Label 156: @6175
3065      GIM_Try, /*On fail goto*//*Label 157*/ 6250, // Rule ID 1177 //
3066        GIM_CheckFeatures, GIFBS_HasNEON,
3067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3069        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3070        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3071        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3072        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3073        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3074        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3075        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3076        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3077        GIM_CheckIsSafeToFold, /*InsnID*/1,
3078        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3079        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3084        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3085        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3086        GIR_EraseFromParent, /*InsnID*/0,
3087        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3088        // GIR_Coverage, 1177,
3089        GIR_Done,
3090      // Label 157: @6250
3091      GIM_Try, /*On fail goto*//*Label 158*/ 6319, // Rule ID 783 //
3092        GIM_CheckFeatures, GIFBS_HasNEON,
3093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3094        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3095        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3096        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3097        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3098        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3099        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3100        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3101        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3102        GIM_CheckIsSafeToFold, /*InsnID*/1,
3103        GIM_CheckIsSafeToFold, /*InsnID*/2,
3104        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
3106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3110        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3111        GIR_EraseFromParent, /*InsnID*/0,
3112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3113        // GIR_Coverage, 783,
3114        GIR_Done,
3115      // Label 158: @6319
3116      GIM_Try, /*On fail goto*//*Label 159*/ 6388, // Rule ID 786 //
3117        GIM_CheckFeatures, GIFBS_HasNEON,
3118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3119        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3120        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3121        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3122        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3123        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3124        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3125        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3126        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3127        GIM_CheckIsSafeToFold, /*InsnID*/1,
3128        GIM_CheckIsSafeToFold, /*InsnID*/2,
3129        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3134        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3135        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3136        GIR_EraseFromParent, /*InsnID*/0,
3137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3138        // GIR_Coverage, 786,
3139        GIR_Done,
3140      // Label 159: @6388
3141      GIM_Try, /*On fail goto*//*Label 160*/ 6456, // Rule ID 4252 //
3142        GIM_CheckFeatures, GIFBS_HasNEON,
3143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3144        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3145        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3146        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3147        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3148        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3149        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3151        GIM_CheckIsSafeToFold, /*InsnID*/1,
3152        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3158        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3159        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3160        GIR_EraseFromParent, /*InsnID*/0,
3161        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3162        // GIR_Coverage, 4252,
3163        GIR_Done,
3164      // Label 160: @6456
3165      GIM_Try, /*On fail goto*//*Label 161*/ 6512, // Rule ID 4224 //
3166        GIM_CheckFeatures, GIFBS_HasNEON,
3167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3168        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3169        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3170        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3171        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3173        GIM_CheckIsSafeToFold, /*InsnID*/1,
3174        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3175        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3179        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3180        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3181        GIR_EraseFromParent, /*InsnID*/0,
3182        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3183        // GIR_Coverage, 4224,
3184        GIR_Done,
3185      // Label 161: @6512
3186      GIM_Try, /*On fail goto*//*Label 162*/ 6568, // Rule ID 4227 //
3187        GIM_CheckFeatures, GIFBS_HasNEON,
3188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3189        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3190        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3191        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3192        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3194        GIM_CheckIsSafeToFold, /*InsnID*/1,
3195        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3196        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3200        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3201        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3202        GIR_EraseFromParent, /*InsnID*/0,
3203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3204        // GIR_Coverage, 4227,
3205        GIR_Done,
3206      // Label 162: @6568
3207      GIM_Try, /*On fail goto*//*Label 163*/ 6636, // Rule ID 894 //
3208        GIM_CheckFeatures, GIFBS_HasNEON,
3209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3211        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3212        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3213        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3214        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3215        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3216        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3217        GIM_CheckIsSafeToFold, /*InsnID*/1,
3218        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3219        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3224        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3225        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3226        GIR_EraseFromParent, /*InsnID*/0,
3227        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3228        // GIR_Coverage, 894,
3229        GIR_Done,
3230      // Label 163: @6636
3231      GIM_Try, /*On fail goto*//*Label 164*/ 6692, // Rule ID 789 //
3232        GIM_CheckFeatures, GIFBS_HasNEON,
3233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3235        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3236        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3237        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3238        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3239        GIM_CheckIsSafeToFold, /*InsnID*/1,
3240        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3245        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3246        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3247        GIR_EraseFromParent, /*InsnID*/0,
3248        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3249        // GIR_Coverage, 789,
3250        GIR_Done,
3251      // Label 164: @6692
3252      GIM_Try, /*On fail goto*//*Label 165*/ 6748, // Rule ID 792 //
3253        GIM_CheckFeatures, GIFBS_HasNEON,
3254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3256        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3257        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3258        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3259        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3260        GIM_CheckIsSafeToFold, /*InsnID*/1,
3261        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3266        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3267        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3268        GIR_EraseFromParent, /*InsnID*/0,
3269        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3270        // GIR_Coverage, 792,
3271        GIR_Done,
3272      // Label 165: @6748
3273      GIM_Try, /*On fail goto*//*Label 166*/ 6791, // Rule ID 775 //
3274        GIM_CheckFeatures, GIFBS_HasNEON,
3275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3278        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
3280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3283        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3284        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3285        GIR_EraseFromParent, /*InsnID*/0,
3286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3287        // GIR_Coverage, 775,
3288        GIR_Done,
3289      // Label 166: @6791
3290      GIM_Try, /*On fail goto*//*Label 167*/ 6848, // Rule ID 3018 //
3291        GIM_CheckFeatures, GIFBS_HasMVEInt,
3292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3295        // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3296        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3297        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3298        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi16,
3300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3303        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3304        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3305        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3306        GIR_EraseFromParent, /*InsnID*/0,
3307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3308        // GIR_Coverage, 3018,
3309        GIR_Done,
3310      // Label 167: @6848
3311      GIM_Reject,
3312    // Label 149: @6849
3313    GIM_Reject,
3314    // Label 62: @6850
3315    GIM_Try, /*On fail goto*//*Label 168*/ 7397,
3316      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3317      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3318      GIM_Try, /*On fail goto*//*Label 169*/ 6935, // Rule ID 4321 //
3319        GIM_CheckFeatures, GIFBS_HasNEON,
3320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3321        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3322        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3323        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3324        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3325        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3326        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3327        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3328        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3330        GIM_CheckIsSafeToFold, /*InsnID*/1,
3331        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3332        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3337        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3338        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3339        GIR_EraseFromParent, /*InsnID*/0,
3340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3341        // GIR_Coverage, 4321,
3342        GIR_Done,
3343      // Label 169: @6935
3344      GIM_Try, /*On fail goto*//*Label 170*/ 7010, // Rule ID 4327 //
3345        GIM_CheckFeatures, GIFBS_HasNEON,
3346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3347        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3348        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3349        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3350        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3351        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3352        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3353        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3354        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3356        GIM_CheckIsSafeToFold, /*InsnID*/1,
3357        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3358        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3363        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3364        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3365        GIR_EraseFromParent, /*InsnID*/0,
3366        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3367        // GIR_Coverage, 4327,
3368        GIR_Done,
3369      // Label 170: @7010
3370      GIM_Try, /*On fail goto*//*Label 171*/ 7085, // Rule ID 1170 //
3371        GIM_CheckFeatures, GIFBS_HasNEON,
3372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3374        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3375        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3376        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3377        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3378        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3379        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3380        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3381        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3382        GIM_CheckIsSafeToFold, /*InsnID*/1,
3383        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3389        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3390        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3391        GIR_EraseFromParent, /*InsnID*/0,
3392        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3393        // GIR_Coverage, 1170,
3394        GIR_Done,
3395      // Label 171: @7085
3396      GIM_Try, /*On fail goto*//*Label 172*/ 7160, // Rule ID 1176 //
3397        GIM_CheckFeatures, GIFBS_HasNEON,
3398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3400        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3401        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3402        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3403        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3404        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3405        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3406        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3407        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3408        GIM_CheckIsSafeToFold, /*InsnID*/1,
3409        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3416        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3417        GIR_EraseFromParent, /*InsnID*/0,
3418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3419        // GIR_Coverage, 1176,
3420        GIR_Done,
3421      // Label 172: @7160
3422      GIM_Try, /*On fail goto*//*Label 173*/ 7228, // Rule ID 4251 //
3423        GIM_CheckFeatures, GIFBS_HasNEON,
3424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3425        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3426        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3427        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3428        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3429        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3430        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3432        GIM_CheckIsSafeToFold, /*InsnID*/1,
3433        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3434        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3439        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3440        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3441        GIR_EraseFromParent, /*InsnID*/0,
3442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3443        // GIR_Coverage, 4251,
3444        GIR_Done,
3445      // Label 173: @7228
3446      GIM_Try, /*On fail goto*//*Label 174*/ 7296, // Rule ID 893 //
3447        GIM_CheckFeatures, GIFBS_HasNEON,
3448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3450        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3451        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3452        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3453        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3454        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3455        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3456        GIM_CheckIsSafeToFold, /*InsnID*/1,
3457        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3463        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3464        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3465        GIR_EraseFromParent, /*InsnID*/0,
3466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3467        // GIR_Coverage, 893,
3468        GIR_Done,
3469      // Label 174: @7296
3470      GIM_Try, /*On fail goto*//*Label 175*/ 7339, // Rule ID 774 //
3471        GIM_CheckFeatures, GIFBS_HasNEON,
3472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3475        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3476        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3480        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3481        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3482        GIR_EraseFromParent, /*InsnID*/0,
3483        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3484        // GIR_Coverage, 774,
3485        GIR_Done,
3486      // Label 175: @7339
3487      GIM_Try, /*On fail goto*//*Label 176*/ 7396, // Rule ID 3016 //
3488        GIM_CheckFeatures, GIFBS_HasMVEInt,
3489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3492        // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3493        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3494        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3495        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3496        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi8,
3497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3500        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3501        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3502        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3503        GIR_EraseFromParent, /*InsnID*/0,
3504        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3505        // GIR_Coverage, 3016,
3506        GIR_Done,
3507      // Label 176: @7396
3508      GIM_Reject,
3509    // Label 168: @7397
3510    GIM_Reject,
3511    // Label 63: @7398
3512    GIM_Reject,
3513    // Label 1: @7399
3514    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 186*/ 9653,
3515    /*GILLT_s32*//*Label 177*/ 7419,
3516    /*GILLT_s64*//*Label 178*/ 7927,
3517    /*GILLT_v2s32*//*Label 179*/ 7979,
3518    /*GILLT_v2s64*//*Label 180*/ 8094, 0,
3519    /*GILLT_v4s16*//*Label 181*/ 8383,
3520    /*GILLT_v4s32*//*Label 182*/ 8498, 0, 0,
3521    /*GILLT_v8s8*//*Label 183*/ 8928,
3522    /*GILLT_v8s16*//*Label 184*/ 9043, 0, 0,
3523    /*GILLT_v16s8*//*Label 185*/ 9473,
3524    // Label 177: @7419
3525    GIM_Try, /*On fail goto*//*Label 187*/ 7926,
3526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3527      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3528      GIM_Try, /*On fail goto*//*Label 188*/ 7483, // Rule ID 98 //
3529        GIM_CheckFeatures, GIFBS_IsARM,
3530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3531        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3532        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3533        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3534        // MIs[1] Operand 1
3535        // No operand predicates
3536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3537        GIM_CheckIsSafeToFold, /*InsnID*/1,
3538        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3539        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3542        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3543        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3544        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3545        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3546        GIR_EraseFromParent, /*InsnID*/0,
3547        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3548        // GIR_Coverage, 98,
3549        GIR_Done,
3550      // Label 188: @7483
3551      GIM_Try, /*On fail goto*//*Label 189*/ 7537, // Rule ID 433 //
3552        GIM_CheckFeatures, GIFBS_IsThumb2,
3553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3554        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3555        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3556        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3557        // MIs[1] Operand 1
3558        // No operand predicates
3559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3560        GIM_CheckIsSafeToFold, /*InsnID*/1,
3561        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3562        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3565        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3566        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3567        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3568        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3569        GIR_EraseFromParent, /*InsnID*/0,
3570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3571        // GIR_Coverage, 433,
3572        GIR_Done,
3573      // Label 189: @7537
3574      GIM_Try, /*On fail goto*//*Label 190*/ 7591, // Rule ID 78 //
3575        GIM_CheckFeatures, GIFBS_IsARM,
3576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3578        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3579        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3580        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3581        // MIs[1] Operand 1
3582        // No operand predicates
3583        GIM_CheckIsSafeToFold, /*InsnID*/1,
3584        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3588        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3589        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3590        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3591        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3592        GIR_EraseFromParent, /*InsnID*/0,
3593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3594        // GIR_Coverage, 78,
3595        GIR_Done,
3596      // Label 190: @7591
3597      GIM_Try, /*On fail goto*//*Label 191*/ 7645, // Rule ID 417 //
3598        GIM_CheckFeatures, GIFBS_IsThumb2,
3599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3601        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3602        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3603        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3604        // MIs[1] Operand 1
3605        // No operand predicates
3606        GIM_CheckIsSafeToFold, /*InsnID*/1,
3607        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3608        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3611        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3612        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3613        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3614        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3615        GIR_EraseFromParent, /*InsnID*/0,
3616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3617        // GIR_Coverage, 417,
3618        GIR_Done,
3619      // Label 191: @7645
3620      GIM_Try, /*On fail goto*//*Label 192*/ 7695, // Rule ID 418 //
3621        GIM_CheckFeatures, GIFBS_IsThumb2,
3622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3624        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3625        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3626        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
3627        // MIs[1] Operand 1
3628        // No operand predicates
3629        GIM_CheckIsSafeToFold, /*InsnID*/1,
3630        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3631        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3634        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3635        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3636        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3637        GIR_EraseFromParent, /*InsnID*/0,
3638        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3639        // GIR_Coverage, 418,
3640        GIR_Done,
3641      // Label 192: @7695
3642      GIM_Try, /*On fail goto*//*Label 193*/ 7763, // Rule ID 175 //
3643        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
3644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3646        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3647        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3648        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3649        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3650        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3651        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3652        GIM_CheckIsSafeToFold, /*InsnID*/1,
3653        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
3654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3659        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3660        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3661        GIR_EraseFromParent, /*InsnID*/0,
3662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3663        // GIR_Coverage, 175,
3664        GIR_Done,
3665      // Label 193: @7763
3666      GIM_Try, /*On fail goto*//*Label 194*/ 7831, // Rule ID 510 //
3667        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
3668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3670        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3671        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3672        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3673        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3674        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3675        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3676        GIM_CheckIsSafeToFold, /*InsnID*/1,
3677        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
3678        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3683        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3684        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3685        GIR_EraseFromParent, /*InsnID*/0,
3686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3687        // GIR_Coverage, 510,
3688        GIR_Done,
3689      // Label 194: @7831
3690      GIM_Try, /*On fail goto*//*Label 195*/ 7878, // Rule ID 79 //
3691        GIM_CheckFeatures, GIFBS_IsARM,
3692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3695        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
3696        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3700        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3701        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3702        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3703        GIR_EraseFromParent, /*InsnID*/0,
3704        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3705        // GIR_Coverage, 79,
3706        GIR_Done,
3707      // Label 195: @7878
3708      GIM_Try, /*On fail goto*//*Label 196*/ 7925, // Rule ID 419 //
3709        GIM_CheckFeatures, GIFBS_IsThumb2,
3710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3711        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3713        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
3714        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3719        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3720        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3721        GIR_EraseFromParent, /*InsnID*/0,
3722        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3723        // GIR_Coverage, 419,
3724        GIR_Done,
3725      // Label 196: @7925
3726      GIM_Reject,
3727    // Label 187: @7926
3728    GIM_Reject,
3729    // Label 178: @7927
3730    GIM_Try, /*On fail goto*//*Label 197*/ 7978, // Rule ID 964 //
3731      GIM_CheckFeatures, GIFBS_HasNEON,
3732      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3733      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3734      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3735      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3736      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3737      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
3738      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3739      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3740      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3741      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3742      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3743      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3744      GIR_EraseFromParent, /*InsnID*/0,
3745      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3746      // GIR_Coverage, 964,
3747      GIR_Done,
3748    // Label 197: @7978
3749    GIM_Reject,
3750    // Label 179: @7979
3751    GIM_Try, /*On fail goto*//*Label 198*/ 8093,
3752      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3753      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3756      GIM_Try, /*On fail goto*//*Label 199*/ 8057, // Rule ID 920 //
3757        GIM_CheckFeatures, GIFBS_HasNEON,
3758        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3759        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3760        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3761        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3762        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3763        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3764        GIM_CheckIsSafeToFold, /*InsnID*/1,
3765        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3766        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3771        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3772        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3773        GIR_EraseFromParent, /*InsnID*/0,
3774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3775        // GIR_Coverage, 920,
3776        GIR_Done,
3777      // Label 199: @8057
3778      GIM_Try, /*On fail goto*//*Label 200*/ 8092, // Rule ID 960 //
3779        GIM_CheckFeatures, GIFBS_HasNEON,
3780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3781        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3782        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3786        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3787        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3788        GIR_EraseFromParent, /*InsnID*/0,
3789        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3790        // GIR_Coverage, 960,
3791        GIR_Done,
3792      // Label 200: @8092
3793      GIM_Reject,
3794    // Label 198: @8093
3795    GIM_Reject,
3796    // Label 180: @8094
3797    GIM_Try, /*On fail goto*//*Label 201*/ 8382,
3798      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3799      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3800      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3801      GIM_Try, /*On fail goto*//*Label 202*/ 8173, // Rule ID 972 //
3802        GIM_CheckFeatures, GIFBS_HasNEON,
3803        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3804        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3805        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3806        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3807        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3808        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3809        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3810        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3811        GIM_CheckIsSafeToFold, /*InsnID*/1,
3812        GIM_CheckIsSafeToFold, /*InsnID*/2,
3813        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3814        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3818        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3819        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3820        GIR_EraseFromParent, /*InsnID*/0,
3821        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3822        // GIR_Coverage, 972,
3823        GIR_Done,
3824      // Label 202: @8173
3825      GIM_Try, /*On fail goto*//*Label 203*/ 8238, // Rule ID 975 //
3826        GIM_CheckFeatures, GIFBS_HasNEON,
3827        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3828        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3829        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3830        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3831        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3832        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3833        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3834        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3835        GIM_CheckIsSafeToFold, /*InsnID*/1,
3836        GIM_CheckIsSafeToFold, /*InsnID*/2,
3837        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3842        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3843        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3844        GIR_EraseFromParent, /*InsnID*/0,
3845        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3846        // GIR_Coverage, 975,
3847        GIR_Done,
3848      // Label 203: @8238
3849      GIM_Try, /*On fail goto*//*Label 204*/ 8290, // Rule ID 978 //
3850        GIM_CheckFeatures, GIFBS_HasNEON,
3851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3852        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3853        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3854        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3855        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3856        GIM_CheckIsSafeToFold, /*InsnID*/1,
3857        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3862        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3863        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3864        GIR_EraseFromParent, /*InsnID*/0,
3865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3866        // GIR_Coverage, 978,
3867        GIR_Done,
3868      // Label 204: @8290
3869      GIM_Try, /*On fail goto*//*Label 205*/ 8342, // Rule ID 981 //
3870        GIM_CheckFeatures, GIFBS_HasNEON,
3871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3872        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3873        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3874        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3875        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3876        GIM_CheckIsSafeToFold, /*InsnID*/1,
3877        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3882        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3883        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3884        GIR_EraseFromParent, /*InsnID*/0,
3885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3886        // GIR_Coverage, 981,
3887        GIR_Done,
3888      // Label 205: @8342
3889      GIM_Try, /*On fail goto*//*Label 206*/ 8381, // Rule ID 965 //
3890        GIM_CheckFeatures, GIFBS_HasNEON,
3891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3893        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3899        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3900        GIR_EraseFromParent, /*InsnID*/0,
3901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3902        // GIR_Coverage, 965,
3903        GIR_Done,
3904      // Label 206: @8381
3905      GIM_Reject,
3906    // Label 201: @8382
3907    GIM_Reject,
3908    // Label 181: @8383
3909    GIM_Try, /*On fail goto*//*Label 207*/ 8497,
3910      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
3911      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
3912      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3913      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3914      GIM_Try, /*On fail goto*//*Label 208*/ 8461, // Rule ID 919 //
3915        GIM_CheckFeatures, GIFBS_HasNEON,
3916        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3917        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3918        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3919        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3920        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3921        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3922        GIM_CheckIsSafeToFold, /*InsnID*/1,
3923        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3929        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3930        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3931        GIR_EraseFromParent, /*InsnID*/0,
3932        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3933        // GIR_Coverage, 919,
3934        GIR_Done,
3935      // Label 208: @8461
3936      GIM_Try, /*On fail goto*//*Label 209*/ 8496, // Rule ID 959 //
3937        GIM_CheckFeatures, GIFBS_HasNEON,
3938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3939        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3944        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3945        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3946        GIR_EraseFromParent, /*InsnID*/0,
3947        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3948        // GIR_Coverage, 959,
3949        GIR_Done,
3950      // Label 209: @8496
3951      GIM_Reject,
3952    // Label 207: @8497
3953    GIM_Reject,
3954    // Label 182: @8498
3955    GIM_Try, /*On fail goto*//*Label 210*/ 8927,
3956      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3957      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3958      GIM_Try, /*On fail goto*//*Label 211*/ 8577, // Rule ID 971 //
3959        GIM_CheckFeatures, GIFBS_HasNEON,
3960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3961        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3962        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3963        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3964        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3965        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3966        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3967        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3968        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3969        GIM_CheckIsSafeToFold, /*InsnID*/1,
3970        GIM_CheckIsSafeToFold, /*InsnID*/2,
3971        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3972        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3976        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3977        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
3978        GIR_EraseFromParent, /*InsnID*/0,
3979        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3980        // GIR_Coverage, 971,
3981        GIR_Done,
3982      // Label 211: @8577
3983      GIM_Try, /*On fail goto*//*Label 212*/ 8646, // Rule ID 974 //
3984        GIM_CheckFeatures, GIFBS_HasNEON,
3985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3986        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3987        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3988        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3989        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3990        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3991        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3992        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3993        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3994        GIM_CheckIsSafeToFold, /*InsnID*/1,
3995        GIM_CheckIsSafeToFold, /*InsnID*/2,
3996        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
3998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4001        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4002        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4003        GIR_EraseFromParent, /*InsnID*/0,
4004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4005        // GIR_Coverage, 974,
4006        GIR_Done,
4007      // Label 212: @8646
4008      GIM_Try, /*On fail goto*//*Label 213*/ 8714, // Rule ID 923 //
4009        GIM_CheckFeatures, GIFBS_HasNEON,
4010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4012        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4013        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4014        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4015        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4016        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4017        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4018        GIM_CheckIsSafeToFold, /*InsnID*/1,
4019        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
4021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4025        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4026        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4027        GIR_EraseFromParent, /*InsnID*/0,
4028        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4029        // GIR_Coverage, 923,
4030        GIR_Done,
4031      // Label 213: @8714
4032      GIM_Try, /*On fail goto*//*Label 214*/ 8770, // Rule ID 977 //
4033        GIM_CheckFeatures, GIFBS_HasNEON,
4034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4036        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4037        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4038        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4039        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4040        GIM_CheckIsSafeToFold, /*InsnID*/1,
4041        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
4043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4046        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4047        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4048        GIR_EraseFromParent, /*InsnID*/0,
4049        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4050        // GIR_Coverage, 977,
4051        GIR_Done,
4052      // Label 214: @8770
4053      GIM_Try, /*On fail goto*//*Label 215*/ 8826, // Rule ID 980 //
4054        GIM_CheckFeatures, GIFBS_HasNEON,
4055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4057        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4058        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4059        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4060        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4061        GIM_CheckIsSafeToFold, /*InsnID*/1,
4062        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4063        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4067        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4068        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4069        GIR_EraseFromParent, /*InsnID*/0,
4070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4071        // GIR_Coverage, 980,
4072        GIR_Done,
4073      // Label 215: @8826
4074      GIM_Try, /*On fail goto*//*Label 216*/ 8869, // Rule ID 963 //
4075        GIM_CheckFeatures, GIFBS_HasNEON,
4076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4079        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
4081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4084        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4085        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4086        GIR_EraseFromParent, /*InsnID*/0,
4087        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4088        // GIR_Coverage, 963,
4089        GIR_Done,
4090      // Label 216: @8869
4091      GIM_Try, /*On fail goto*//*Label 217*/ 8926, // Rule ID 3026 //
4092        GIM_CheckFeatures, GIFBS_HasMVEInt,
4093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4096        // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4097        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4098        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4099        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4100        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi32,
4101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4104        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4105        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4106        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4107        GIR_EraseFromParent, /*InsnID*/0,
4108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4109        // GIR_Coverage, 3026,
4110        GIR_Done,
4111      // Label 217: @8926
4112      GIM_Reject,
4113    // Label 210: @8927
4114    GIM_Reject,
4115    // Label 183: @8928
4116    GIM_Try, /*On fail goto*//*Label 218*/ 9042,
4117      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4118      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4119      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4121      GIM_Try, /*On fail goto*//*Label 219*/ 9006, // Rule ID 918 //
4122        GIM_CheckFeatures, GIFBS_HasNEON,
4123        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4124        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4125        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4126        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4127        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4128        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4129        GIM_CheckIsSafeToFold, /*InsnID*/1,
4130        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4131        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
4132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4136        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4137        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4138        GIR_EraseFromParent, /*InsnID*/0,
4139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4140        // GIR_Coverage, 918,
4141        GIR_Done,
4142      // Label 219: @9006
4143      GIM_Try, /*On fail goto*//*Label 220*/ 9041, // Rule ID 958 //
4144        GIM_CheckFeatures, GIFBS_HasNEON,
4145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4146        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
4148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4151        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4152        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4153        GIR_EraseFromParent, /*InsnID*/0,
4154        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4155        // GIR_Coverage, 958,
4156        GIR_Done,
4157      // Label 220: @9041
4158      GIM_Reject,
4159    // Label 218: @9042
4160    GIM_Reject,
4161    // Label 184: @9043
4162    GIM_Try, /*On fail goto*//*Label 221*/ 9472,
4163      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4164      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4165      GIM_Try, /*On fail goto*//*Label 222*/ 9122, // Rule ID 970 //
4166        GIM_CheckFeatures, GIFBS_HasNEON,
4167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4168        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4169        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4170        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4171        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4172        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4173        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4174        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4175        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4176        GIM_CheckIsSafeToFold, /*InsnID*/1,
4177        GIM_CheckIsSafeToFold, /*InsnID*/2,
4178        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4179        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
4180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4183        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4184        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4185        GIR_EraseFromParent, /*InsnID*/0,
4186        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4187        // GIR_Coverage, 970,
4188        GIR_Done,
4189      // Label 222: @9122
4190      GIM_Try, /*On fail goto*//*Label 223*/ 9191, // Rule ID 973 //
4191        GIM_CheckFeatures, GIFBS_HasNEON,
4192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4193        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4194        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4195        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4196        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4197        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4198        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4199        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4200        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4201        GIM_CheckIsSafeToFold, /*InsnID*/1,
4202        GIM_CheckIsSafeToFold, /*InsnID*/2,
4203        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4204        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4208        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4209        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4210        GIR_EraseFromParent, /*InsnID*/0,
4211        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4212        // GIR_Coverage, 973,
4213        GIR_Done,
4214      // Label 223: @9191
4215      GIM_Try, /*On fail goto*//*Label 224*/ 9259, // Rule ID 922 //
4216        GIM_CheckFeatures, GIFBS_HasNEON,
4217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4219        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4220        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4221        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4222        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4223        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4224        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4225        GIM_CheckIsSafeToFold, /*InsnID*/1,
4226        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4227        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
4228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4232        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4233        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4234        GIR_EraseFromParent, /*InsnID*/0,
4235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4236        // GIR_Coverage, 922,
4237        GIR_Done,
4238      // Label 224: @9259
4239      GIM_Try, /*On fail goto*//*Label 225*/ 9315, // Rule ID 976 //
4240        GIM_CheckFeatures, GIFBS_HasNEON,
4241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4242        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4243        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4244        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4245        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4246        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4247        GIM_CheckIsSafeToFold, /*InsnID*/1,
4248        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
4250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4253        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4254        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4255        GIR_EraseFromParent, /*InsnID*/0,
4256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4257        // GIR_Coverage, 976,
4258        GIR_Done,
4259      // Label 225: @9315
4260      GIM_Try, /*On fail goto*//*Label 226*/ 9371, // Rule ID 979 //
4261        GIM_CheckFeatures, GIFBS_HasNEON,
4262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4264        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4265        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4266        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4267        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4268        GIM_CheckIsSafeToFold, /*InsnID*/1,
4269        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4270        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
4271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4274        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4275        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4276        GIR_EraseFromParent, /*InsnID*/0,
4277        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4278        // GIR_Coverage, 979,
4279        GIR_Done,
4280      // Label 226: @9371
4281      GIM_Try, /*On fail goto*//*Label 227*/ 9414, // Rule ID 962 //
4282        GIM_CheckFeatures, GIFBS_HasNEON,
4283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4286        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
4288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4291        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4292        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4293        GIR_EraseFromParent, /*InsnID*/0,
4294        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4295        // GIR_Coverage, 962,
4296        GIR_Done,
4297      // Label 227: @9414
4298      GIM_Try, /*On fail goto*//*Label 228*/ 9471, // Rule ID 3024 //
4299        GIM_CheckFeatures, GIFBS_HasMVEInt,
4300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4303        // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
4304        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4305        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4306        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi16,
4308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4311        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4312        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4313        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4314        GIR_EraseFromParent, /*InsnID*/0,
4315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4316        // GIR_Coverage, 3024,
4317        GIR_Done,
4318      // Label 228: @9471
4319      GIM_Reject,
4320    // Label 221: @9472
4321    GIM_Reject,
4322    // Label 185: @9473
4323    GIM_Try, /*On fail goto*//*Label 229*/ 9652,
4324      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4325      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4326      GIM_Try, /*On fail goto*//*Label 230*/ 9551, // Rule ID 921 //
4327        GIM_CheckFeatures, GIFBS_HasNEON,
4328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4330        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4331        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4332        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4333        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4334        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4335        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4336        GIM_CheckIsSafeToFold, /*InsnID*/1,
4337        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
4339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4343        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4344        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4345        GIR_EraseFromParent, /*InsnID*/0,
4346        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4347        // GIR_Coverage, 921,
4348        GIR_Done,
4349      // Label 230: @9551
4350      GIM_Try, /*On fail goto*//*Label 231*/ 9594, // Rule ID 961 //
4351        GIM_CheckFeatures, GIFBS_HasNEON,
4352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4355        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
4357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4360        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4361        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4362        GIR_EraseFromParent, /*InsnID*/0,
4363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4364        // GIR_Coverage, 961,
4365        GIR_Done,
4366      // Label 231: @9594
4367      GIM_Try, /*On fail goto*//*Label 232*/ 9651, // Rule ID 3022 //
4368        GIM_CheckFeatures, GIFBS_HasMVEInt,
4369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4372        // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
4373        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4374        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4375        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi8,
4377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4380        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4381        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4382        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4383        GIR_EraseFromParent, /*InsnID*/0,
4384        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4385        // GIR_Coverage, 3022,
4386        GIR_Done,
4387      // Label 232: @9651
4388      GIM_Reject,
4389    // Label 229: @9652
4390    GIM_Reject,
4391    // Label 186: @9653
4392    GIM_Reject,
4393    // Label 2: @9654
4394    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 240*/ 10485,
4395    /*GILLT_s32*//*Label 233*/ 9674, 0,
4396    /*GILLT_v2s32*//*Label 234*/ 9993, 0, 0,
4397    /*GILLT_v4s16*//*Label 235*/ 10045,
4398    /*GILLT_v4s32*//*Label 236*/ 10097, 0, 0,
4399    /*GILLT_v8s8*//*Label 237*/ 10209,
4400    /*GILLT_v8s16*//*Label 238*/ 10261, 0, 0,
4401    /*GILLT_v16s8*//*Label 239*/ 10373,
4402    // Label 233: @9674
4403    GIM_Try, /*On fail goto*//*Label 241*/ 9992,
4404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4405      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4406      GIM_Try, /*On fail goto*//*Label 242*/ 9769, // Rule ID 188 //
4407        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
4408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4409        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4410        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4411        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4412        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4413        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4414        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4415        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4416        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4417        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4418        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4419        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4420        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4421        GIM_CheckIsSafeToFold, /*InsnID*/1,
4422        GIM_CheckIsSafeToFold, /*InsnID*/2,
4423        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4429        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4430        GIR_EraseFromParent, /*InsnID*/0,
4431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4432        // GIR_Coverage, 188,
4433        GIR_Done,
4434      // Label 242: @9769
4435      GIM_Try, /*On fail goto*//*Label 243*/ 9854, // Rule ID 521 //
4436        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4438        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4439        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4440        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4441        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4442        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4443        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4444        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4445        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4446        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4447        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4448        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4449        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4450        GIM_CheckIsSafeToFold, /*InsnID*/1,
4451        GIM_CheckIsSafeToFold, /*InsnID*/2,
4452        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4457        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4458        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4459        GIR_EraseFromParent, /*InsnID*/0,
4460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4461        // GIR_Coverage, 521,
4462        GIR_Done,
4463      // Label 243: @9854
4464      GIM_Try, /*On fail goto*//*Label 244*/ 9901, // Rule ID 171 //
4465        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4469        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4474        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4475        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4476        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4477        GIR_EraseFromParent, /*InsnID*/0,
4478        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4479        // GIR_Coverage, 171,
4480        GIR_Done,
4481      // Label 244: @9901
4482      GIM_Try, /*On fail goto*//*Label 245*/ 9948, // Rule ID 172 //
4483        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
4484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4487        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4492        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4493        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4494        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4495        GIR_EraseFromParent, /*InsnID*/0,
4496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4497        // GIR_Coverage, 172,
4498        GIR_Done,
4499      // Label 245: @9948
4500      GIM_Try, /*On fail goto*//*Label 246*/ 9991, // Rule ID 508 //
4501        GIM_CheckFeatures, GIFBS_IsThumb2,
4502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4505        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4506        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4510        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4511        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4512        GIR_EraseFromParent, /*InsnID*/0,
4513        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4514        // GIR_Coverage, 508,
4515        GIR_Done,
4516      // Label 246: @9991
4517      GIM_Reject,
4518    // Label 241: @9992
4519    GIM_Reject,
4520    // Label 234: @9993
4521    GIM_Try, /*On fail goto*//*Label 247*/ 10044, // Rule ID 840 //
4522      GIM_CheckFeatures, GIFBS_HasNEON,
4523      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4524      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4525      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4528      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4529      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4530      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4533      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4534      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4535      GIR_EraseFromParent, /*InsnID*/0,
4536      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4537      // GIR_Coverage, 840,
4538      GIR_Done,
4539    // Label 247: @10044
4540    GIM_Reject,
4541    // Label 235: @10045
4542    GIM_Try, /*On fail goto*//*Label 248*/ 10096, // Rule ID 839 //
4543      GIM_CheckFeatures, GIFBS_HasNEON,
4544      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4545      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4546      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4547      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4548      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4549      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4550      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4551      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4552      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4553      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4554      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4555      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4556      GIR_EraseFromParent, /*InsnID*/0,
4557      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4558      // GIR_Coverage, 839,
4559      GIR_Done,
4560    // Label 248: @10096
4561    GIM_Reject,
4562    // Label 236: @10097
4563    GIM_Try, /*On fail goto*//*Label 249*/ 10208,
4564      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4565      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4566      GIM_Try, /*On fail goto*//*Label 250*/ 10150, // Rule ID 843 //
4567        GIM_CheckFeatures, GIFBS_HasNEON,
4568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4571        // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4572        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4576        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4577        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4578        GIR_EraseFromParent, /*InsnID*/0,
4579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4580        // GIR_Coverage, 843,
4581        GIR_Done,
4582      // Label 250: @10150
4583      GIM_Try, /*On fail goto*//*Label 251*/ 10207, // Rule ID 3002 //
4584        GIM_CheckFeatures, GIFBS_HasMVEInt,
4585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4588        // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4589        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4590        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4591        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi32,
4593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4596        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4597        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4598        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4599        GIR_EraseFromParent, /*InsnID*/0,
4600        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4601        // GIR_Coverage, 3002,
4602        GIR_Done,
4603      // Label 251: @10207
4604      GIM_Reject,
4605    // Label 249: @10208
4606    GIM_Reject,
4607    // Label 237: @10209
4608    GIM_Try, /*On fail goto*//*Label 252*/ 10260, // Rule ID 838 //
4609      GIM_CheckFeatures, GIFBS_HasNEON,
4610      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4611      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4614      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4615      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4616      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4619      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4620      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4621      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4622      GIR_EraseFromParent, /*InsnID*/0,
4623      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4624      // GIR_Coverage, 838,
4625      GIR_Done,
4626    // Label 252: @10260
4627    GIM_Reject,
4628    // Label 238: @10261
4629    GIM_Try, /*On fail goto*//*Label 253*/ 10372,
4630      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4631      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4632      GIM_Try, /*On fail goto*//*Label 254*/ 10314, // Rule ID 842 //
4633        GIM_CheckFeatures, GIFBS_HasNEON,
4634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4637        // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4642        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4643        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4644        GIR_EraseFromParent, /*InsnID*/0,
4645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4646        // GIR_Coverage, 842,
4647        GIR_Done,
4648      // Label 254: @10314
4649      GIM_Try, /*On fail goto*//*Label 255*/ 10371, // Rule ID 3000 //
4650        GIM_CheckFeatures, GIFBS_HasMVEInt,
4651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4654        // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
4655        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4656        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4657        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi16,
4659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4662        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4663        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4664        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4665        GIR_EraseFromParent, /*InsnID*/0,
4666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4667        // GIR_Coverage, 3000,
4668        GIR_Done,
4669      // Label 255: @10371
4670      GIM_Reject,
4671    // Label 253: @10372
4672    GIM_Reject,
4673    // Label 239: @10373
4674    GIM_Try, /*On fail goto*//*Label 256*/ 10484,
4675      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4676      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4677      GIM_Try, /*On fail goto*//*Label 257*/ 10426, // Rule ID 841 //
4678        GIM_CheckFeatures, GIFBS_HasNEON,
4679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4682        // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4683        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4687        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4688        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4689        GIR_EraseFromParent, /*InsnID*/0,
4690        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4691        // GIR_Coverage, 841,
4692        GIR_Done,
4693      // Label 257: @10426
4694      GIM_Try, /*On fail goto*//*Label 258*/ 10483, // Rule ID 2998 //
4695        GIM_CheckFeatures, GIFBS_HasMVEInt,
4696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4699        // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
4700        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4701        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4702        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi8,
4704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4707        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4708        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4709        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4710        GIR_EraseFromParent, /*InsnID*/0,
4711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4712        // GIR_Coverage, 2998,
4713        GIR_Done,
4714      // Label 258: @10483
4715      GIM_Reject,
4716    // Label 256: @10484
4717    GIM_Reject,
4718    // Label 240: @10485
4719    GIM_Reject,
4720    // Label 3: @10486
4721    GIM_Try, /*On fail goto*//*Label 259*/ 10587,
4722      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4723      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4724      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4725      GIM_Try, /*On fail goto*//*Label 260*/ 10543, // Rule ID 197 //
4726        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4730        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4735        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4736        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4737        GIR_EraseFromParent, /*InsnID*/0,
4738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4739        // GIR_Coverage, 197,
4740        GIR_Done,
4741      // Label 260: @10543
4742      GIM_Try, /*On fail goto*//*Label 261*/ 10586, // Rule ID 538 //
4743        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4747        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4748        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4752        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4753        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4754        GIR_EraseFromParent, /*InsnID*/0,
4755        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4756        // GIR_Coverage, 538,
4757        GIR_Done,
4758      // Label 261: @10586
4759      GIM_Reject,
4760    // Label 259: @10587
4761    GIM_Reject,
4762    // Label 4: @10588
4763    GIM_Try, /*On fail goto*//*Label 262*/ 10689,
4764      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4765      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4766      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4767      GIM_Try, /*On fail goto*//*Label 263*/ 10645, // Rule ID 198 //
4768        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4772        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4778        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4779        GIR_EraseFromParent, /*InsnID*/0,
4780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4781        // GIR_Coverage, 198,
4782        GIR_Done,
4783      // Label 263: @10645
4784      GIM_Try, /*On fail goto*//*Label 264*/ 10688, // Rule ID 539 //
4785        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4789        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4794        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4795        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4796        GIR_EraseFromParent, /*InsnID*/0,
4797        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4798        // GIR_Coverage, 539,
4799        GIR_Done,
4800      // Label 264: @10688
4801      GIM_Reject,
4802    // Label 262: @10689
4803    GIM_Reject,
4804    // Label 5: @10690
4805    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 274*/ 13032,
4806    /*GILLT_s32*//*Label 265*/ 10710, 0,
4807    /*GILLT_v2s32*//*Label 266*/ 12352,
4808    /*GILLT_v2s64*//*Label 267*/ 12404,
4809    /*GILLT_v4s1*//*Label 268*/ 12470, 0,
4810    /*GILLT_v4s32*//*Label 269*/ 12576, 0,
4811    /*GILLT_v8s1*//*Label 270*/ 12688, 0,
4812    /*GILLT_v8s16*//*Label 271*/ 12794, 0,
4813    /*GILLT_v16s1*//*Label 272*/ 12860,
4814    /*GILLT_v16s8*//*Label 273*/ 12966,
4815    // Label 265: @10710
4816    GIM_Try, /*On fail goto*//*Label 275*/ 12351,
4817      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4818      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4819      GIM_Try, /*On fail goto*//*Label 276*/ 10783, // Rule ID 1868 //
4820        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4822        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4823        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4824        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4825        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4826        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4827        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4828        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4829        GIM_CheckIsSafeToFold, /*InsnID*/1,
4830        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4834        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4836        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4837        GIR_EraseFromParent, /*InsnID*/0,
4838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4839        // GIR_Coverage, 1868,
4840        GIR_Done,
4841      // Label 276: @10783
4842      GIM_Try, /*On fail goto*//*Label 277*/ 10846, // Rule ID 2094 //
4843        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4847        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4848        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4849        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4850        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4851        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4852        GIM_CheckIsSafeToFold, /*InsnID*/1,
4853        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4857        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4858        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4859        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4860        GIR_EraseFromParent, /*InsnID*/0,
4861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4862        // GIR_Coverage, 2094,
4863        GIR_Done,
4864      // Label 277: @10846
4865      GIM_Try, /*On fail goto*//*Label 278*/ 10888, // Rule ID 1987 //
4866        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4869        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4870        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4874        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4875        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4876        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4877        GIR_EraseFromParent, /*InsnID*/0,
4878        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4879        // GIR_Coverage, 1987,
4880        GIR_Done,
4881      // Label 278: @10888
4882      GIM_Try, /*On fail goto*//*Label 279*/ 10930, // Rule ID 1988 //
4883        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4886        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4887        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4891        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4892        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4893        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4894        GIR_EraseFromParent, /*InsnID*/0,
4895        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4896        // GIR_Coverage, 1988,
4897        GIR_Done,
4898      // Label 279: @10930
4899      GIM_Try, /*On fail goto*//*Label 280*/ 10972, // Rule ID 1989 //
4900        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4903        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4904        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4905        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4908        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4909        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4910        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4911        GIR_EraseFromParent, /*InsnID*/0,
4912        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4913        // GIR_Coverage, 1989,
4914        GIR_Done,
4915      // Label 280: @10972
4916      GIM_Try, /*On fail goto*//*Label 281*/ 11014, // Rule ID 2195 //
4917        GIM_CheckFeatures, GIFBS_IsThumb2,
4918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4920        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4921        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4922        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4925        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4926        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4927        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4928        GIR_EraseFromParent, /*InsnID*/0,
4929        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4930        // GIR_Coverage, 2195,
4931        GIR_Done,
4932      // Label 281: @11014
4933      GIM_Try, /*On fail goto*//*Label 282*/ 11056, // Rule ID 2196 //
4934        GIM_CheckFeatures, GIFBS_IsThumb2,
4935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4937        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4938        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4942        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4943        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4944        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4945        GIR_EraseFromParent, /*InsnID*/0,
4946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4947        // GIR_Coverage, 2196,
4948        GIR_Done,
4949      // Label 282: @11056
4950      GIM_Try, /*On fail goto*//*Label 283*/ 11098, // Rule ID 2197 //
4951        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4954        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4955        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4959        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4960        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4961        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4962        GIR_EraseFromParent, /*InsnID*/0,
4963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4964        // GIR_Coverage, 2197,
4965        GIR_Done,
4966      // Label 283: @11098
4967      GIM_Try, /*On fail goto*//*Label 284*/ 11173, // Rule ID 4160 //
4968        GIM_CheckFeatures, GIFBS_IsARM,
4969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4970        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4971        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4972        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4973        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4974        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4975        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4976        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4977        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4978        // MIs[2] Operand 1
4979        // No operand predicates
4980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4981        GIM_CheckIsSafeToFold, /*InsnID*/1,
4982        GIM_CheckIsSafeToFold, /*InsnID*/2,
4983        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4984        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4987        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4988        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4989        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4990        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
4991        GIR_EraseFromParent, /*InsnID*/0,
4992        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4993        // GIR_Coverage, 4160,
4994        GIR_Done,
4995      // Label 284: @11173
4996      GIM_Try, /*On fail goto*//*Label 285*/ 11248, // Rule ID 4193 //
4997        GIM_CheckFeatures, GIFBS_IsThumb2,
4998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4999        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5000        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5001        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5002        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5003        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5004        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5005        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5006        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5007        // MIs[2] Operand 1
5008        // No operand predicates
5009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5010        GIM_CheckIsSafeToFold, /*InsnID*/1,
5011        GIM_CheckIsSafeToFold, /*InsnID*/2,
5012        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5013        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5016        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5017        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5018        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5019        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5020        GIR_EraseFromParent, /*InsnID*/0,
5021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5022        // GIR_Coverage, 4193,
5023        GIR_Done,
5024      // Label 285: @11248
5025      GIM_Try, /*On fail goto*//*Label 286*/ 11323, // Rule ID 4159 //
5026        GIM_CheckFeatures, GIFBS_IsARM,
5027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5028        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5029        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5030        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5031        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5032        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5033        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5034        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5035        // MIs[2] Operand 1
5036        // No operand predicates
5037        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5039        GIM_CheckIsSafeToFold, /*InsnID*/1,
5040        GIM_CheckIsSafeToFold, /*InsnID*/2,
5041        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5045        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5046        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5047        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5048        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5049        GIR_EraseFromParent, /*InsnID*/0,
5050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5051        // GIR_Coverage, 4159,
5052        GIR_Done,
5053      // Label 286: @11323
5054      GIM_Try, /*On fail goto*//*Label 287*/ 11398, // Rule ID 4192 //
5055        GIM_CheckFeatures, GIFBS_IsThumb2,
5056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5057        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5058        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5059        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5060        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5061        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5062        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5063        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5064        // MIs[2] Operand 1
5065        // No operand predicates
5066        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5068        GIM_CheckIsSafeToFold, /*InsnID*/1,
5069        GIM_CheckIsSafeToFold, /*InsnID*/2,
5070        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5071        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5074        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5075        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5076        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5077        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5078        GIR_EraseFromParent, /*InsnID*/0,
5079        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5080        // GIR_Coverage, 4192,
5081        GIR_Done,
5082      // Label 287: @11398
5083      GIM_Try, /*On fail goto*//*Label 288*/ 11473, // Rule ID 4158 //
5084        GIM_CheckFeatures, GIFBS_IsARM,
5085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5087        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5088        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5089        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5090        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5091        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5092        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5093        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5094        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5095        // MIs[2] Operand 1
5096        // No operand predicates
5097        GIM_CheckIsSafeToFold, /*InsnID*/1,
5098        GIM_CheckIsSafeToFold, /*InsnID*/2,
5099        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5100        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5103        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5104        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5105        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5106        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5107        GIR_EraseFromParent, /*InsnID*/0,
5108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5109        // GIR_Coverage, 4158,
5110        GIR_Done,
5111      // Label 288: @11473
5112      GIM_Try, /*On fail goto*//*Label 289*/ 11548, // Rule ID 4191 //
5113        GIM_CheckFeatures, GIFBS_IsThumb2,
5114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5116        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5117        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5118        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5119        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5120        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5121        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5122        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5123        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5124        // MIs[2] Operand 1
5125        // No operand predicates
5126        GIM_CheckIsSafeToFold, /*InsnID*/1,
5127        GIM_CheckIsSafeToFold, /*InsnID*/2,
5128        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5132        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5133        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5134        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5135        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5136        GIR_EraseFromParent, /*InsnID*/0,
5137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5138        // GIR_Coverage, 4191,
5139        GIR_Done,
5140      // Label 289: @11548
5141      GIM_Try, /*On fail goto*//*Label 290*/ 11623, // Rule ID 161 //
5142        GIM_CheckFeatures, GIFBS_IsARM,
5143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5145        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5146        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5147        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5148        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5149        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5150        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5151        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5152        // MIs[2] Operand 1
5153        // No operand predicates
5154        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5155        GIM_CheckIsSafeToFold, /*InsnID*/1,
5156        GIM_CheckIsSafeToFold, /*InsnID*/2,
5157        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5158        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5161        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5162        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5163        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5164        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5165        GIR_EraseFromParent, /*InsnID*/0,
5166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5167        // GIR_Coverage, 161,
5168        GIR_Done,
5169      // Label 290: @11623
5170      GIM_Try, /*On fail goto*//*Label 291*/ 11698, // Rule ID 496 //
5171        GIM_CheckFeatures, GIFBS_IsThumb2,
5172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5174        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5175        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5176        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5177        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5178        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5179        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5180        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5181        // MIs[2] Operand 1
5182        // No operand predicates
5183        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5184        GIM_CheckIsSafeToFold, /*InsnID*/1,
5185        GIM_CheckIsSafeToFold, /*InsnID*/2,
5186        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5190        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5191        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5192        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5193        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5194        GIR_EraseFromParent, /*InsnID*/0,
5195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5196        // GIR_Coverage, 496,
5197        GIR_Done,
5198      // Label 291: @11698
5199      GIM_Try, /*On fail goto*//*Label 292*/ 11766, // Rule ID 4161 //
5200        GIM_CheckFeatures, GIFBS_IsARM,
5201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5202        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5203        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5204        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5205        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5206        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5207        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5209        GIM_CheckIsSafeToFold, /*InsnID*/1,
5210        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5215        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5216        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5217        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5218        GIR_EraseFromParent, /*InsnID*/0,
5219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5220        // GIR_Coverage, 4161,
5221        GIR_Done,
5222      // Label 292: @11766
5223      GIM_Try, /*On fail goto*//*Label 293*/ 11834, // Rule ID 4194 //
5224        GIM_CheckFeatures, GIFBS_IsThumb2,
5225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5226        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5227        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5228        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5229        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5230        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5231        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5233        GIM_CheckIsSafeToFold, /*InsnID*/1,
5234        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5239        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5240        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5241        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5242        GIR_EraseFromParent, /*InsnID*/0,
5243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5244        // GIR_Coverage, 4194,
5245        GIR_Done,
5246      // Label 293: @11834
5247      GIM_Try, /*On fail goto*//*Label 294*/ 11902, // Rule ID 162 //
5248        GIM_CheckFeatures, GIFBS_IsARM,
5249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5251        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5252        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5253        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5254        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5255        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5256        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5257        GIM_CheckIsSafeToFold, /*InsnID*/1,
5258        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5263        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5264        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5265        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5266        GIR_EraseFromParent, /*InsnID*/0,
5267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5268        // GIR_Coverage, 162,
5269        GIR_Done,
5270      // Label 294: @11902
5271      GIM_Try, /*On fail goto*//*Label 295*/ 11970, // Rule ID 497 //
5272        GIM_CheckFeatures, GIFBS_IsThumb2,
5273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5275        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5276        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5277        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5278        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5279        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5280        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5281        GIM_CheckIsSafeToFold, /*InsnID*/1,
5282        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5287        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5288        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5289        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5290        GIR_EraseFromParent, /*InsnID*/0,
5291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5292        // GIR_Coverage, 497,
5293        GIR_Done,
5294      // Label 295: @11970
5295      GIM_Try, /*On fail goto*//*Label 296*/ 12009, // Rule ID 353 //
5296        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
5297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
5298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
5299        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
5300        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
5301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB,
5302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5304        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5305        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5306        GIR_EraseFromParent, /*InsnID*/0,
5307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5308        // GIR_Coverage, 353,
5309        GIR_Done,
5310      // Label 296: @12009
5311      GIM_Try, /*On fail goto*//*Label 297*/ 12048, // Rule ID 354 //
5312        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
5313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
5314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
5315        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
5316        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
5317        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH,
5318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5320        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5321        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5322        GIR_EraseFromParent, /*InsnID*/0,
5323        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5324        // GIR_Coverage, 354,
5325        GIR_Done,
5326      // Label 297: @12048
5327      GIM_Try, /*On fail goto*//*Label 298*/ 12102, // Rule ID 149 //
5328        GIM_CheckFeatures, GIFBS_IsARM,
5329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5331        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5332        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5333        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5334        // MIs[1] Operand 1
5335        // No operand predicates
5336        GIM_CheckIsSafeToFold, /*InsnID*/1,
5337        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
5339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5341        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5342        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5343        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5344        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5345        GIR_EraseFromParent, /*InsnID*/0,
5346        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5347        // GIR_Coverage, 149,
5348        GIR_Done,
5349      // Label 298: @12102
5350      GIM_Try, /*On fail goto*//*Label 299*/ 12156, // Rule ID 487 //
5351        GIM_CheckFeatures, GIFBS_IsThumb2,
5352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5354        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5355        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5356        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5357        // MIs[1] Operand 1
5358        // No operand predicates
5359        GIM_CheckIsSafeToFold, /*InsnID*/1,
5360        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5361        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri,
5362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5364        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5365        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5366        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5367        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5368        GIR_EraseFromParent, /*InsnID*/0,
5369        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5370        // GIR_Coverage, 487,
5371        GIR_Done,
5372      // Label 299: @12156
5373      GIM_Try, /*On fail goto*//*Label 300*/ 12206, // Rule ID 165 //
5374        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
5375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5377        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5378        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5379        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
5380        // MIs[1] Operand 1
5381        // No operand predicates
5382        GIM_CheckIsSafeToFold, /*InsnID*/1,
5383        // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
5384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC,
5385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
5387        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5388        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5389        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5390        GIR_EraseFromParent, /*InsnID*/0,
5391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5392        // GIR_Coverage, 165,
5393        GIR_Done,
5394      // Label 300: @12206
5395      GIM_Try, /*On fail goto*//*Label 301*/ 12256, // Rule ID 499 //
5396        GIM_CheckFeatures, GIFBS_IsThumb2,
5397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5399        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5400        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5401        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
5402        // MIs[1] Operand 1
5403        // No operand predicates
5404        GIM_CheckIsSafeToFold, /*InsnID*/1,
5405        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
5406        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC,
5407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
5409        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5410        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5411        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5412        GIR_EraseFromParent, /*InsnID*/0,
5413        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5414        // GIR_Coverage, 499,
5415        GIR_Done,
5416      // Label 301: @12256
5417      GIM_Try, /*On fail goto*//*Label 302*/ 12303, // Rule ID 150 //
5418        GIM_CheckFeatures, GIFBS_IsARM,
5419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5422        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5423        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr,
5424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5427        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5428        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5429        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5430        GIR_EraseFromParent, /*InsnID*/0,
5431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5432        // GIR_Coverage, 150,
5433        GIR_Done,
5434      // Label 302: @12303
5435      GIM_Try, /*On fail goto*//*Label 303*/ 12350, // Rule ID 488 //
5436        GIM_CheckFeatures, GIFBS_IsThumb2,
5437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5440        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5441        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
5442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5445        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5446        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5447        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5448        GIR_EraseFromParent, /*InsnID*/0,
5449        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5450        // GIR_Coverage, 488,
5451        GIR_Done,
5452      // Label 303: @12350
5453      GIM_Reject,
5454    // Label 275: @12351
5455    GIM_Reject,
5456    // Label 266: @12352
5457    GIM_Try, /*On fail goto*//*Label 304*/ 12403, // Rule ID 1119 //
5458      GIM_CheckFeatures, GIFBS_HasNEON,
5459      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
5460      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
5461      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5464      // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5465      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
5466      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5467      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5468      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5469      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5470      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5471      GIR_EraseFromParent, /*InsnID*/0,
5472      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5473      // GIR_Coverage, 1119,
5474      GIR_Done,
5475    // Label 304: @12403
5476    GIM_Reject,
5477    // Label 267: @12404
5478    GIM_Try, /*On fail goto*//*Label 305*/ 12469, // Rule ID 2942 //
5479      GIM_CheckFeatures, GIFBS_HasMVEInt,
5480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
5481      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5483      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5484      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5485      // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
5486      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5487      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5488      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5489      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5492      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5493      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5494      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5495      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5496      GIR_EraseFromParent, /*InsnID*/0,
5497      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5498      // GIR_Coverage, 2942,
5499      GIR_Done,
5500    // Label 305: @12469
5501    GIM_Reject,
5502    // Label 268: @12470
5503    GIM_Try, /*On fail goto*//*Label 306*/ 12575, // Rule ID 1847 //
5504      GIM_CheckFeatures, GIFBS_HasMVEInt,
5505      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
5506      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
5507      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
5508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
5509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
5510      // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
5511      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5512      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
5513      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
5514      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5515      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
5516      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
5517      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
5518      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5519      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
5520      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
5521      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
5522      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5523      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
5524      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
5525      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
5526      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
5527      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5528      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5529      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
5532      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5533      GIR_EraseFromParent, /*InsnID*/0,
5534      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
5535      // GIR_Coverage, 1847,
5536      GIR_Done,
5537    // Label 306: @12575
5538    GIM_Reject,
5539    // Label 269: @12576
5540    GIM_Try, /*On fail goto*//*Label 307*/ 12687,
5541      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
5542      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5543      GIM_Try, /*On fail goto*//*Label 308*/ 12629, // Rule ID 1120 //
5544        GIM_CheckFeatures, GIFBS_HasNEON,
5545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5548        // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5549        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
5550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5553        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5554        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5555        GIR_EraseFromParent, /*InsnID*/0,
5556        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5557        // GIR_Coverage, 1120,
5558        GIR_Done,
5559      // Label 308: @12629
5560      GIM_Try, /*On fail goto*//*Label 309*/ 12686, // Rule ID 2940 //
5561        GIM_CheckFeatures, GIFBS_HasMVEInt,
5562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5565        // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5566        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5567        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5568        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5569        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5573        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5574        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5575        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5576        GIR_EraseFromParent, /*InsnID*/0,
5577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5578        // GIR_Coverage, 2940,
5579        GIR_Done,
5580      // Label 309: @12686
5581      GIM_Reject,
5582    // Label 307: @12687
5583    GIM_Reject,
5584    // Label 270: @12688
5585    GIM_Try, /*On fail goto*//*Label 310*/ 12793, // Rule ID 1848 //
5586      GIM_CheckFeatures, GIFBS_HasMVEInt,
5587      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
5588      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
5589      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
5590      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
5591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
5592      // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
5593      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5594      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
5595      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
5596      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5597      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
5598      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
5599      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
5600      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5601      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
5602      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
5603      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
5604      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5605      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
5606      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
5607      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
5608      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
5609      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5610      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5611      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5612      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5613      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
5614      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5615      GIR_EraseFromParent, /*InsnID*/0,
5616      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
5617      // GIR_Coverage, 1848,
5618      GIR_Done,
5619    // Label 310: @12793
5620    GIM_Reject,
5621    // Label 271: @12794
5622    GIM_Try, /*On fail goto*//*Label 311*/ 12859, // Rule ID 2938 //
5623      GIM_CheckFeatures, GIFBS_HasMVEInt,
5624      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
5625      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5628      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5629      // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5630      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5631      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5632      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5633      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5634      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5635      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5636      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5637      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5638      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5639      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5640      GIR_EraseFromParent, /*InsnID*/0,
5641      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5642      // GIR_Coverage, 2938,
5643      GIR_Done,
5644    // Label 311: @12859
5645    GIM_Reject,
5646    // Label 272: @12860
5647    GIM_Try, /*On fail goto*//*Label 312*/ 12965, // Rule ID 1846 //
5648      GIM_CheckFeatures, GIFBS_HasMVEInt,
5649      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
5650      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
5651      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
5652      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
5653      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
5654      // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
5655      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5656      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
5657      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
5658      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5659      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
5660      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
5661      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
5662      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5663      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
5664      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
5665      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
5666      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5667      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
5668      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
5669      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
5670      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
5671      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5672      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
5673      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5674      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5675      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
5676      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5677      GIR_EraseFromParent, /*InsnID*/0,
5678      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
5679      // GIR_Coverage, 1846,
5680      GIR_Done,
5681    // Label 312: @12965
5682    GIM_Reject,
5683    // Label 273: @12966
5684    GIM_Try, /*On fail goto*//*Label 313*/ 13031, // Rule ID 2936 //
5685      GIM_CheckFeatures, GIFBS_HasMVEInt,
5686      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5687      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5688      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5689      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5690      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5691      // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5692      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5693      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5694      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5695      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5696      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5698      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5699      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5700      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5701      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5702      GIR_EraseFromParent, /*InsnID*/0,
5703      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5704      // GIR_Coverage, 2936,
5705      GIR_Done,
5706    // Label 313: @13031
5707    GIM_Reject,
5708    // Label 274: @13032
5709    GIM_Reject,
5710    // Label 6: @13033
5711    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 323*/ 17855,
5712    /*GILLT_s32*//*Label 314*/ 13053, 0,
5713    /*GILLT_v2s32*//*Label 315*/ 17175,
5714    /*GILLT_v2s64*//*Label 316*/ 17227,
5715    /*GILLT_v4s1*//*Label 317*/ 17293, 0,
5716    /*GILLT_v4s32*//*Label 318*/ 17399, 0,
5717    /*GILLT_v8s1*//*Label 319*/ 17511, 0,
5718    /*GILLT_v8s16*//*Label 320*/ 17617, 0,
5719    /*GILLT_v16s1*//*Label 321*/ 17683,
5720    /*GILLT_v16s8*//*Label 322*/ 17789,
5721    // Label 314: @13053
5722    GIM_Try, /*On fail goto*//*Label 324*/ 17174,
5723      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5724      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5725      GIM_Try, /*On fail goto*//*Label 325*/ 13183, // Rule ID 4373 //
5726        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5728        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5729        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5730        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5731        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5732        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5733        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5734        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5735        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5736        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5737        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
5738        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
5739        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5740        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5741        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5742        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5743        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5744        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5745        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5746        // MIs[4] Rm
5747        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5748        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
5749        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
5750        GIM_CheckIsSafeToFold, /*InsnID*/1,
5751        GIM_CheckIsSafeToFold, /*InsnID*/2,
5752        GIM_CheckIsSafeToFold, /*InsnID*/3,
5753        GIM_CheckIsSafeToFold, /*InsnID*/4,
5754        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
5755        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5758        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5759        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5760        GIR_EraseFromParent, /*InsnID*/0,
5761        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5762        // GIR_Coverage, 4373,
5763        GIR_Done,
5764      // Label 325: @13183
5765      GIM_Try, /*On fail goto*//*Label 326*/ 13303, // Rule ID 4415 //
5766        GIM_CheckFeatures, GIFBS_IsThumb2,
5767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5768        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5769        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5770        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5771        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5772        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5773        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5774        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5775        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5776        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5777        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
5778        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
5779        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5780        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5781        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5782        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5783        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5784        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5785        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5786        // MIs[4] Rm
5787        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5788        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
5789        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
5790        GIM_CheckIsSafeToFold, /*InsnID*/1,
5791        GIM_CheckIsSafeToFold, /*InsnID*/2,
5792        GIM_CheckIsSafeToFold, /*InsnID*/3,
5793        GIM_CheckIsSafeToFold, /*InsnID*/4,
5794        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
5795        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5798        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5799        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5800        GIR_EraseFromParent, /*InsnID*/0,
5801        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5802        // GIR_Coverage, 4415,
5803        GIR_Done,
5804      // Label 326: @13303
5805      GIM_Try, /*On fail goto*//*Label 327*/ 13423, // Rule ID 1918 //
5806        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5808        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5809        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5810        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5811        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5812        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5813        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5814        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5815        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5816        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5817        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
5818        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5819        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5820        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
5821        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5822        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5823        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5824        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
5825        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5826        // MIs[4] Rm
5827        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5828        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
5829        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
5830        GIM_CheckIsSafeToFold, /*InsnID*/1,
5831        GIM_CheckIsSafeToFold, /*InsnID*/2,
5832        GIM_CheckIsSafeToFold, /*InsnID*/3,
5833        GIM_CheckIsSafeToFold, /*InsnID*/4,
5834        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
5835        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5839        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5840        GIR_EraseFromParent, /*InsnID*/0,
5841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5842        // GIR_Coverage, 1918,
5843        GIR_Done,
5844      // Label 327: @13423
5845      GIM_Try, /*On fail goto*//*Label 328*/ 13543, // Rule ID 2168 //
5846        GIM_CheckFeatures, GIFBS_IsThumb2,
5847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5848        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5849        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5850        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5851        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5852        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5853        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5854        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5855        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5856        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5857        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
5858        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5859        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5860        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
5861        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5862        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5863        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5864        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
5865        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5866        // MIs[4] Rm
5867        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5868        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
5869        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
5870        GIM_CheckIsSafeToFold, /*InsnID*/1,
5871        GIM_CheckIsSafeToFold, /*InsnID*/2,
5872        GIM_CheckIsSafeToFold, /*InsnID*/3,
5873        GIM_CheckIsSafeToFold, /*InsnID*/4,
5874        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
5875        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5878        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5879        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5880        GIR_EraseFromParent, /*InsnID*/0,
5881        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5882        // GIR_Coverage, 2168,
5883        GIR_Done,
5884      // Label 328: @13543
5885      GIM_Try, /*On fail goto*//*Label 329*/ 13660, // Rule ID 4174 //
5886        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5888        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5889        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5890        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5891        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5892        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5893        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5894        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5895        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5896        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5897        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5898        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5899        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5900        // MIs[3] Operand 1
5901        // No operand predicates
5902        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5903        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5904        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5905        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5906        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5907        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5908        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5909        GIM_CheckIsSafeToFold, /*InsnID*/1,
5910        GIM_CheckIsSafeToFold, /*InsnID*/2,
5911        GIM_CheckIsSafeToFold, /*InsnID*/3,
5912        GIM_CheckIsSafeToFold, /*InsnID*/4,
5913        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5918        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5920        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5921        GIR_EraseFromParent, /*InsnID*/0,
5922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5923        // GIR_Coverage, 4174,
5924        GIR_Done,
5925      // Label 329: @13660
5926      GIM_Try, /*On fail goto*//*Label 330*/ 13777, // Rule ID 4211 //
5927        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5929        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5930        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5931        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5932        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5933        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5934        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5935        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5936        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5937        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5938        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5939        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5940        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5941        // MIs[3] Operand 1
5942        // No operand predicates
5943        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5944        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5945        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5946        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5947        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5948        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5949        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5950        GIM_CheckIsSafeToFold, /*InsnID*/1,
5951        GIM_CheckIsSafeToFold, /*InsnID*/2,
5952        GIM_CheckIsSafeToFold, /*InsnID*/3,
5953        GIM_CheckIsSafeToFold, /*InsnID*/4,
5954        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5955        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5959        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5960        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5961        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
5962        GIR_EraseFromParent, /*InsnID*/0,
5963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5964        // GIR_Coverage, 4211,
5965        GIR_Done,
5966      // Label 330: @13777
5967      GIM_Try, /*On fail goto*//*Label 331*/ 13894, // Rule ID 4378 //
5968        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5970        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5971        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5972        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5973        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5974        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5975        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5976        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5977        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5978        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5979        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5980        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5981        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
5982        // MIs[3] Operand 1
5983        // No operand predicates
5984        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5985        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5986        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5987        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5988        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5989        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5990        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5991        GIM_CheckIsSafeToFold, /*InsnID*/1,
5992        GIM_CheckIsSafeToFold, /*InsnID*/2,
5993        GIM_CheckIsSafeToFold, /*InsnID*/3,
5994        GIM_CheckIsSafeToFold, /*InsnID*/4,
5995        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
5996        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
5999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6000        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6001        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6002        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6003        GIR_EraseFromParent, /*InsnID*/0,
6004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6005        // GIR_Coverage, 4378,
6006        GIR_Done,
6007      // Label 331: @13894
6008      GIM_Try, /*On fail goto*//*Label 332*/ 14011, // Rule ID 4420 //
6009        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6011        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6012        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6013        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6014        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6015        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6016        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6017        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6018        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6019        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6020        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6021        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6022        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6023        // MIs[3] Operand 1
6024        // No operand predicates
6025        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6026        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6027        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6028        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6029        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6030        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6031        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6032        GIM_CheckIsSafeToFold, /*InsnID*/1,
6033        GIM_CheckIsSafeToFold, /*InsnID*/2,
6034        GIM_CheckIsSafeToFold, /*InsnID*/3,
6035        GIM_CheckIsSafeToFold, /*InsnID*/4,
6036        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6037        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6039        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6041        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6042        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6043        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6044        GIR_EraseFromParent, /*InsnID*/0,
6045        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6046        // GIR_Coverage, 4420,
6047        GIR_Done,
6048      // Label 332: @14011
6049      GIM_Try, /*On fail goto*//*Label 333*/ 14128, // Rule ID 4173 //
6050        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6052        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6053        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6054        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6055        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6056        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6057        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6058        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6059        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6060        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6061        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6062        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6063        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6064        // MIs[3] Operand 1
6065        // No operand predicates
6066        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6067        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6068        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6069        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6070        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6071        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6072        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
6073        GIM_CheckIsSafeToFold, /*InsnID*/1,
6074        GIM_CheckIsSafeToFold, /*InsnID*/2,
6075        GIM_CheckIsSafeToFold, /*InsnID*/3,
6076        GIM_CheckIsSafeToFold, /*InsnID*/4,
6077        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6082        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6083        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6084        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6085        GIR_EraseFromParent, /*InsnID*/0,
6086        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6087        // GIR_Coverage, 4173,
6088        GIR_Done,
6089      // Label 333: @14128
6090      GIM_Try, /*On fail goto*//*Label 334*/ 14245, // Rule ID 4210 //
6091        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6093        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6094        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6095        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6096        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6097        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6098        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6099        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6100        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6101        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6102        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6103        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6104        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6105        // MIs[3] Operand 1
6106        // No operand predicates
6107        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6108        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6109        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6110        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6111        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6112        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6113        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
6114        GIM_CheckIsSafeToFold, /*InsnID*/1,
6115        GIM_CheckIsSafeToFold, /*InsnID*/2,
6116        GIM_CheckIsSafeToFold, /*InsnID*/3,
6117        GIM_CheckIsSafeToFold, /*InsnID*/4,
6118        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6123        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6124        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6125        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6126        GIR_EraseFromParent, /*InsnID*/0,
6127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6128        // GIR_Coverage, 4210,
6129        GIR_Done,
6130      // Label 334: @14245
6131      GIM_Try, /*On fail goto*//*Label 335*/ 14362, // Rule ID 205 //
6132        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6134        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6135        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6136        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6137        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6138        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6139        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6140        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6141        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6142        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6143        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6144        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6145        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6146        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6147        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6148        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6149        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6150        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6151        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6152        // MIs[4] Operand 1
6153        // No operand predicates
6154        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6155        GIM_CheckIsSafeToFold, /*InsnID*/1,
6156        GIM_CheckIsSafeToFold, /*InsnID*/2,
6157        GIM_CheckIsSafeToFold, /*InsnID*/3,
6158        GIM_CheckIsSafeToFold, /*InsnID*/4,
6159        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6164        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6165        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6166        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6167        GIR_EraseFromParent, /*InsnID*/0,
6168        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6169        // GIR_Coverage, 205,
6170        GIR_Done,
6171      // Label 335: @14362
6172      GIM_Try, /*On fail goto*//*Label 336*/ 14479, // Rule ID 546 //
6173        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6175        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6176        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6177        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6178        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6179        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6180        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6181        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6182        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6183        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6184        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6185        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6186        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6187        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6188        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6189        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6190        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6191        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6192        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6193        // MIs[4] Operand 1
6194        // No operand predicates
6195        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6196        GIM_CheckIsSafeToFold, /*InsnID*/1,
6197        GIM_CheckIsSafeToFold, /*InsnID*/2,
6198        GIM_CheckIsSafeToFold, /*InsnID*/3,
6199        GIM_CheckIsSafeToFold, /*InsnID*/4,
6200        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6201        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6205        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6206        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6207        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6208        GIR_EraseFromParent, /*InsnID*/0,
6209        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6210        // GIR_Coverage, 546,
6211        GIR_Done,
6212      // Label 336: @14479
6213      GIM_Try, /*On fail goto*//*Label 337*/ 14596, // Rule ID 1923 //
6214        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6216        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6217        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6218        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6219        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6220        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6221        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6222        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6223        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6224        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6225        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6226        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6227        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
6228        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6229        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6230        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6231        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6232        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6233        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6234        // MIs[4] Operand 1
6235        // No operand predicates
6236        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6237        GIM_CheckIsSafeToFold, /*InsnID*/1,
6238        GIM_CheckIsSafeToFold, /*InsnID*/2,
6239        GIM_CheckIsSafeToFold, /*InsnID*/3,
6240        GIM_CheckIsSafeToFold, /*InsnID*/4,
6241        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
6246        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6247        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6248        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6249        GIR_EraseFromParent, /*InsnID*/0,
6250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6251        // GIR_Coverage, 1923,
6252        GIR_Done,
6253      // Label 337: @14596
6254      GIM_Try, /*On fail goto*//*Label 338*/ 14713, // Rule ID 2173 //
6255        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6257        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6258        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6259        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6260        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6261        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6262        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6263        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6264        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6265        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6266        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6267        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6268        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
6269        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6270        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6271        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6272        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6273        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6274        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6275        // MIs[4] Operand 1
6276        // No operand predicates
6277        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6278        GIM_CheckIsSafeToFold, /*InsnID*/1,
6279        GIM_CheckIsSafeToFold, /*InsnID*/2,
6280        GIM_CheckIsSafeToFold, /*InsnID*/3,
6281        GIM_CheckIsSafeToFold, /*InsnID*/4,
6282        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
6287        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6288        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6289        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6290        GIR_EraseFromParent, /*InsnID*/0,
6291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6292        // GIR_Coverage, 2173,
6293        GIR_Done,
6294      // Label 338: @14713
6295      GIM_Try, /*On fail goto*//*Label 339*/ 14830, // Rule ID 204 //
6296        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6298        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6299        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6300        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6301        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6302        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6303        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6304        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6305        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6306        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6307        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6308        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6309        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
6310        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6311        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6312        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6313        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6314        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6315        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6316        // MIs[4] Operand 1
6317        // No operand predicates
6318        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
6319        GIM_CheckIsSafeToFold, /*InsnID*/1,
6320        GIM_CheckIsSafeToFold, /*InsnID*/2,
6321        GIM_CheckIsSafeToFold, /*InsnID*/3,
6322        GIM_CheckIsSafeToFold, /*InsnID*/4,
6323        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6324        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6328        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6329        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6330        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6331        GIR_EraseFromParent, /*InsnID*/0,
6332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6333        // GIR_Coverage, 204,
6334        GIR_Done,
6335      // Label 339: @14830
6336      GIM_Try, /*On fail goto*//*Label 340*/ 14947, // Rule ID 545 //
6337        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6339        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6340        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6341        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6342        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6343        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6344        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6345        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6346        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6347        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6348        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6349        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6350        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
6351        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6352        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6353        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6354        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6355        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6356        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6357        // MIs[4] Operand 1
6358        // No operand predicates
6359        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
6360        GIM_CheckIsSafeToFold, /*InsnID*/1,
6361        GIM_CheckIsSafeToFold, /*InsnID*/2,
6362        GIM_CheckIsSafeToFold, /*InsnID*/3,
6363        GIM_CheckIsSafeToFold, /*InsnID*/4,
6364        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6365        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6369        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6370        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6371        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6372        GIR_EraseFromParent, /*InsnID*/0,
6373        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6374        // GIR_Coverage, 545,
6375        GIR_Done,
6376      // Label 340: @14947
6377      GIM_Try, /*On fail goto*//*Label 341*/ 15035, // Rule ID 1919 //
6378        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6380        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6381        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6382        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6383        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6384        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6385        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6386        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6387        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6388        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6389        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6390        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6391        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
6392        GIM_CheckIsSafeToFold, /*InsnID*/1,
6393        GIM_CheckIsSafeToFold, /*InsnID*/2,
6394        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6395        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6399        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6400        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6401        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6402        GIR_EraseFromParent, /*InsnID*/0,
6403        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6404        // GIR_Coverage, 1919,
6405        GIR_Done,
6406      // Label 341: @15035
6407      GIM_Try, /*On fail goto*//*Label 342*/ 15123, // Rule ID 2169 //
6408        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6410        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6411        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6412        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6413        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6414        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6415        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6416        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6417        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6418        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6419        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6420        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6421        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
6422        GIM_CheckIsSafeToFold, /*InsnID*/1,
6423        GIM_CheckIsSafeToFold, /*InsnID*/2,
6424        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
6425        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6429        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6430        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6431        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6432        GIR_EraseFromParent, /*InsnID*/0,
6433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6434        // GIR_Coverage, 2169,
6435        GIR_Done,
6436      // Label 342: @15123
6437      GIM_Try, /*On fail goto*//*Label 343*/ 15211, // Rule ID 4374 //
6438        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6440        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6441        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6442        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6443        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6444        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6445        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6446        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6447        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6448        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6449        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6450        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6451        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6452        GIM_CheckIsSafeToFold, /*InsnID*/1,
6453        GIM_CheckIsSafeToFold, /*InsnID*/2,
6454        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6455        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
6458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6459        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6460        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6461        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6462        GIR_EraseFromParent, /*InsnID*/0,
6463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6464        // GIR_Coverage, 4374,
6465        GIR_Done,
6466      // Label 343: @15211
6467      GIM_Try, /*On fail goto*//*Label 344*/ 15299, // Rule ID 4416 //
6468        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6470        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6471        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6472        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6473        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6474        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6475        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6476        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6477        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6478        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6479        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6480        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6481        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6482        GIM_CheckIsSafeToFold, /*InsnID*/1,
6483        GIM_CheckIsSafeToFold, /*InsnID*/2,
6484        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
6485        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
6488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6489        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6490        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6491        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6492        GIR_EraseFromParent, /*InsnID*/0,
6493        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6494        // GIR_Coverage, 4416,
6495        GIR_Done,
6496      // Label 344: @15299
6497      GIM_Try, /*On fail goto*//*Label 345*/ 15395, // Rule ID 1922 //
6498        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6500        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6501        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6502        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6503        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6504        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6505        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6506        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6507        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6508        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6509        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6510        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6511        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6512        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6513        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6514        // MIs[3] Operand 1
6515        // No operand predicates
6516        GIM_CheckIsSafeToFold, /*InsnID*/1,
6517        GIM_CheckIsSafeToFold, /*InsnID*/2,
6518        GIM_CheckIsSafeToFold, /*InsnID*/3,
6519        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6524        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6526        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6527        GIR_EraseFromParent, /*InsnID*/0,
6528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6529        // GIR_Coverage, 1922,
6530        GIR_Done,
6531      // Label 345: @15395
6532      GIM_Try, /*On fail goto*//*Label 346*/ 15491, // Rule ID 2172 //
6533        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6535        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6536        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6537        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6538        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6539        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6540        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6541        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6542        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6543        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6544        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6545        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6546        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6547        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6548        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6549        // MIs[3] Operand 1
6550        // No operand predicates
6551        GIM_CheckIsSafeToFold, /*InsnID*/1,
6552        GIM_CheckIsSafeToFold, /*InsnID*/2,
6553        GIM_CheckIsSafeToFold, /*InsnID*/3,
6554        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6555        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6559        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6560        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6561        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6562        GIR_EraseFromParent, /*InsnID*/0,
6563        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6564        // GIR_Coverage, 2172,
6565        GIR_Done,
6566      // Label 346: @15491
6567      GIM_Try, /*On fail goto*//*Label 347*/ 15587, // Rule ID 1921 //
6568        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6570        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6571        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6572        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6573        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6574        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6575        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6576        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6577        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6578        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6579        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6580        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6581        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6582        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6583        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
6584        // MIs[3] Operand 1
6585        // No operand predicates
6586        GIM_CheckIsSafeToFold, /*InsnID*/1,
6587        GIM_CheckIsSafeToFold, /*InsnID*/2,
6588        GIM_CheckIsSafeToFold, /*InsnID*/3,
6589        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6590        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6594        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6595        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6596        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6597        GIR_EraseFromParent, /*InsnID*/0,
6598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6599        // GIR_Coverage, 1921,
6600        GIR_Done,
6601      // Label 347: @15587
6602      GIM_Try, /*On fail goto*//*Label 348*/ 15683, // Rule ID 2171 //
6603        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6605        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6606        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6607        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6608        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6609        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6610        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6611        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6612        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6613        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6614        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6615        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6616        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6617        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6618        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
6619        // MIs[3] Operand 1
6620        // No operand predicates
6621        GIM_CheckIsSafeToFold, /*InsnID*/1,
6622        GIM_CheckIsSafeToFold, /*InsnID*/2,
6623        GIM_CheckIsSafeToFold, /*InsnID*/3,
6624        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6625        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6629        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6630        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6631        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6632        GIR_EraseFromParent, /*InsnID*/0,
6633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6634        // GIR_Coverage, 2171,
6635        GIR_Done,
6636      // Label 348: @15683
6637      GIM_Try, /*On fail goto*//*Label 349*/ 15779, // Rule ID 1920 //
6638        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6640        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6641        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6642        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6643        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6644        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6645        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6646        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6647        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6648        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6649        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6650        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6651        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6652        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6653        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6654        // MIs[3] Operand 1
6655        // No operand predicates
6656        GIM_CheckIsSafeToFold, /*InsnID*/1,
6657        GIM_CheckIsSafeToFold, /*InsnID*/2,
6658        GIM_CheckIsSafeToFold, /*InsnID*/3,
6659        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6664        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6665        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6666        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6667        GIR_EraseFromParent, /*InsnID*/0,
6668        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6669        // GIR_Coverage, 1920,
6670        GIR_Done,
6671      // Label 349: @15779
6672      GIM_Try, /*On fail goto*//*Label 350*/ 15875, // Rule ID 2170 //
6673        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6675        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6676        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6677        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6678        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6679        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6680        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6681        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6682        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6683        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6684        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6685        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6686        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6687        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6688        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6689        // MIs[3] Operand 1
6690        // No operand predicates
6691        GIM_CheckIsSafeToFold, /*InsnID*/1,
6692        GIM_CheckIsSafeToFold, /*InsnID*/2,
6693        GIM_CheckIsSafeToFold, /*InsnID*/3,
6694        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6695        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6699        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6700        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6701        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6702        GIR_EraseFromParent, /*InsnID*/0,
6703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6704        // GIR_Coverage, 2170,
6705        GIR_Done,
6706      // Label 350: @15875
6707      GIM_Try, /*On fail goto*//*Label 351*/ 15971, // Rule ID 4377 //
6708        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6710        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6711        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6712        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6713        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6714        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6715        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6716        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6717        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6718        // MIs[2] Operand 1
6719        // No operand predicates
6720        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6721        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6722        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6723        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6724        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6725        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6726        GIM_CheckIsSafeToFold, /*InsnID*/1,
6727        GIM_CheckIsSafeToFold, /*InsnID*/2,
6728        GIM_CheckIsSafeToFold, /*InsnID*/3,
6729        // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6734        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6735        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6736        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6737        GIR_EraseFromParent, /*InsnID*/0,
6738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6739        // GIR_Coverage, 4377,
6740        GIR_Done,
6741      // Label 351: @15971
6742      GIM_Try, /*On fail goto*//*Label 352*/ 16067, // Rule ID 4419 //
6743        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6745        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6746        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6747        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6748        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6749        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6750        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6751        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6752        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6753        // MIs[2] Operand 1
6754        // No operand predicates
6755        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6756        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6757        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6758        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6759        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6760        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6761        GIM_CheckIsSafeToFold, /*InsnID*/1,
6762        GIM_CheckIsSafeToFold, /*InsnID*/2,
6763        GIM_CheckIsSafeToFold, /*InsnID*/3,
6764        // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6765        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6769        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6770        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6771        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6772        GIR_EraseFromParent, /*InsnID*/0,
6773        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6774        // GIR_Coverage, 4419,
6775        GIR_Done,
6776      // Label 352: @16067
6777      GIM_Try, /*On fail goto*//*Label 353*/ 16163, // Rule ID 4376 //
6778        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6780        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6781        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
6782        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6783        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6784        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6785        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6786        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6787        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
6788        // MIs[2] Operand 1
6789        // No operand predicates
6790        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6791        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6792        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6793        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6794        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6795        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6796        GIM_CheckIsSafeToFold, /*InsnID*/1,
6797        GIM_CheckIsSafeToFold, /*InsnID*/2,
6798        GIM_CheckIsSafeToFold, /*InsnID*/3,
6799        // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6800        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6804        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6805        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6806        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6807        GIR_EraseFromParent, /*InsnID*/0,
6808        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6809        // GIR_Coverage, 4376,
6810        GIR_Done,
6811      // Label 353: @16163
6812      GIM_Try, /*On fail goto*//*Label 354*/ 16259, // Rule ID 4418 //
6813        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6815        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6816        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
6817        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6818        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6819        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6820        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6821        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6822        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
6823        // MIs[2] Operand 1
6824        // No operand predicates
6825        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6826        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6827        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6828        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6829        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6830        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6831        GIM_CheckIsSafeToFold, /*InsnID*/1,
6832        GIM_CheckIsSafeToFold, /*InsnID*/2,
6833        GIM_CheckIsSafeToFold, /*InsnID*/3,
6834        // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6835        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6839        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6840        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6841        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6842        GIR_EraseFromParent, /*InsnID*/0,
6843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6844        // GIR_Coverage, 4418,
6845        GIR_Done,
6846      // Label 354: @16259
6847      GIM_Try, /*On fail goto*//*Label 355*/ 16355, // Rule ID 4375 //
6848        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6850        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6851        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6852        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6853        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6854        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6855        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6856        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6857        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6858        // MIs[2] Operand 1
6859        // No operand predicates
6860        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6861        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6862        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6863        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6864        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6865        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
6866        GIM_CheckIsSafeToFold, /*InsnID*/1,
6867        GIM_CheckIsSafeToFold, /*InsnID*/2,
6868        GIM_CheckIsSafeToFold, /*InsnID*/3,
6869        // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6870        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
6873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6874        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6875        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6876        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6877        GIR_EraseFromParent, /*InsnID*/0,
6878        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6879        // GIR_Coverage, 4375,
6880        GIR_Done,
6881      // Label 355: @16355
6882      GIM_Try, /*On fail goto*//*Label 356*/ 16451, // Rule ID 4417 //
6883        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6885        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6886        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6887        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6888        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6889        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6890        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6891        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6892        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6893        // MIs[2] Operand 1
6894        // No operand predicates
6895        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6896        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6897        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6898        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6899        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6900        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
6901        GIM_CheckIsSafeToFold, /*InsnID*/1,
6902        GIM_CheckIsSafeToFold, /*InsnID*/2,
6903        GIM_CheckIsSafeToFold, /*InsnID*/3,
6904        // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6905        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6909        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6910        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6911        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6912        GIR_EraseFromParent, /*InsnID*/0,
6913        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6914        // GIR_Coverage, 4417,
6915        GIR_Done,
6916      // Label 356: @16451
6917      GIM_Try, /*On fail goto*//*Label 357*/ 16526, // Rule ID 4198 //
6918        GIM_CheckFeatures, GIFBS_IsThumb2,
6919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6920        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6921        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6922        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6923        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6924        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
6925        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6926        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6927        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6928        // MIs[2] Operand 1
6929        // No operand predicates
6930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6931        GIM_CheckIsSafeToFold, /*InsnID*/1,
6932        GIM_CheckIsSafeToFold, /*InsnID*/2,
6933        // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
6937        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6938        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6939        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6940        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6941        GIR_EraseFromParent, /*InsnID*/0,
6942        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6943        // GIR_Coverage, 4198,
6944        GIR_Done,
6945      // Label 357: @16526
6946      GIM_Try, /*On fail goto*//*Label 358*/ 16601, // Rule ID 4197 //
6947        GIM_CheckFeatures, GIFBS_IsThumb2,
6948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6949        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6950        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6951        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6952        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6953        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6954        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6955        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6956        // MIs[2] Operand 1
6957        // No operand predicates
6958        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6960        GIM_CheckIsSafeToFold, /*InsnID*/1,
6961        GIM_CheckIsSafeToFold, /*InsnID*/2,
6962        // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
6966        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6967        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6968        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6969        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6970        GIR_EraseFromParent, /*InsnID*/0,
6971        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6972        // GIR_Coverage, 4197,
6973        GIR_Done,
6974      // Label 358: @16601
6975      GIM_Try, /*On fail goto*//*Label 359*/ 16676, // Rule ID 4196 //
6976        GIM_CheckFeatures, GIFBS_IsThumb2,
6977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6979        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6980        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6981        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6982        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6983        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
6984        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6985        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6986        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6987        // MIs[2] Operand 1
6988        // No operand predicates
6989        GIM_CheckIsSafeToFold, /*InsnID*/1,
6990        GIM_CheckIsSafeToFold, /*InsnID*/2,
6991        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6995        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6996        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6997        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6998        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
6999        GIR_EraseFromParent, /*InsnID*/0,
7000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7001        // GIR_Coverage, 4196,
7002        GIR_Done,
7003      // Label 359: @16676
7004      GIM_Try, /*On fail goto*//*Label 360*/ 16751, // Rule ID 502 //
7005        GIM_CheckFeatures, GIFBS_IsThumb2,
7006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7008        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7009        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7010        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7011        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7012        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7013        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7014        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7015        // MIs[2] Operand 1
7016        // No operand predicates
7017        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7018        GIM_CheckIsSafeToFold, /*InsnID*/1,
7019        GIM_CheckIsSafeToFold, /*InsnID*/2,
7020        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7024        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7025        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7026        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7027        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7028        GIR_EraseFromParent, /*InsnID*/0,
7029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7030        // GIR_Coverage, 502,
7031        GIR_Done,
7032      // Label 360: @16751
7033      GIM_Try, /*On fail goto*//*Label 361*/ 16819, // Rule ID 4199 //
7034        GIM_CheckFeatures, GIFBS_IsThumb2,
7035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7036        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7037        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7038        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7039        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7040        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7041        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7043        GIM_CheckIsSafeToFold, /*InsnID*/1,
7044        // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7045        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7049        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7050        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7051        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7052        GIR_EraseFromParent, /*InsnID*/0,
7053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7054        // GIR_Coverage, 4199,
7055        GIR_Done,
7056      // Label 361: @16819
7057      GIM_Try, /*On fail goto*//*Label 362*/ 16887, // Rule ID 503 //
7058        GIM_CheckFeatures, GIFBS_IsThumb2,
7059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7061        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7062        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7063        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7064        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7065        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7066        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7067        GIM_CheckIsSafeToFold, /*InsnID*/1,
7068        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7073        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7074        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7075        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7076        GIR_EraseFromParent, /*InsnID*/0,
7077        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7078        // GIR_Coverage, 503,
7079        GIR_Done,
7080      // Label 362: @16887
7081      GIM_Try, /*On fail goto*//*Label 363*/ 16929, // Rule ID 1861 //
7082        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
7083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7085        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
7086        // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16,
7088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7090        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
7091        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7092        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7093        GIR_EraseFromParent, /*InsnID*/0,
7094        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7095        // GIR_Coverage, 1861,
7096        GIR_Done,
7097      // Label 363: @16929
7098      GIM_Try, /*On fail goto*//*Label 364*/ 16971, // Rule ID 2076 //
7099        GIM_CheckFeatures, GIFBS_IsThumb2,
7100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7102        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
7103        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16,
7105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7107        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
7108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7109        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7110        GIR_EraseFromParent, /*InsnID*/0,
7111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7112        // GIR_Coverage, 2076,
7113        GIR_Done,
7114      // Label 364: @16971
7115      GIM_Try, /*On fail goto*//*Label 365*/ 17025, // Rule ID 153 //
7116        GIM_CheckFeatures, GIFBS_IsARM,
7117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7119        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7120        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7121        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
7122        // MIs[1] Operand 1
7123        // No operand predicates
7124        GIM_CheckIsSafeToFold, /*InsnID*/1,
7125        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri,
7127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7129        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7130        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7131        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7132        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7133        GIR_EraseFromParent, /*InsnID*/0,
7134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7135        // GIR_Coverage, 153,
7136        GIR_Done,
7137      // Label 365: @17025
7138      GIM_Try, /*On fail goto*//*Label 366*/ 17079, // Rule ID 490 //
7139        GIM_CheckFeatures, GIFBS_IsThumb2,
7140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7142        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7143        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7144        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7145        // MIs[1] Operand 1
7146        // No operand predicates
7147        GIM_CheckIsSafeToFold, /*InsnID*/1,
7148        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri,
7150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7152        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7153        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7154        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7155        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7156        GIR_EraseFromParent, /*InsnID*/0,
7157        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7158        // GIR_Coverage, 490,
7159        GIR_Done,
7160      // Label 366: @17079
7161      GIM_Try, /*On fail goto*//*Label 367*/ 17126, // Rule ID 154 //
7162        GIM_CheckFeatures, GIFBS_IsARM,
7163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
7166        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr,
7168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7171        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7172        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7173        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7174        GIR_EraseFromParent, /*InsnID*/0,
7175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7176        // GIR_Coverage, 154,
7177        GIR_Done,
7178      // Label 367: @17126
7179      GIM_Try, /*On fail goto*//*Label 368*/ 17173, // Rule ID 491 //
7180        GIM_CheckFeatures, GIFBS_IsThumb2,
7181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7184        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7185        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
7186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7189        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7190        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7191        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7192        GIR_EraseFromParent, /*InsnID*/0,
7193        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7194        // GIR_Coverage, 491,
7195        GIR_Done,
7196      // Label 368: @17173
7197      GIM_Reject,
7198    // Label 324: @17174
7199    GIM_Reject,
7200    // Label 315: @17175
7201    GIM_Try, /*On fail goto*//*Label 369*/ 17226, // Rule ID 1123 //
7202      GIM_CheckFeatures, GIFBS_HasNEON,
7203      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7204      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
7205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7206      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7208      // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7209      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
7210      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7211      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
7212      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
7213      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7214      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7215      GIR_EraseFromParent, /*InsnID*/0,
7216      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7217      // GIR_Coverage, 1123,
7218      GIR_Done,
7219    // Label 369: @17226
7220    GIM_Reject,
7221    // Label 316: @17227
7222    GIM_Try, /*On fail goto*//*Label 370*/ 17292, // Rule ID 2950 //
7223      GIM_CheckFeatures, GIFBS_HasMVEInt,
7224      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7225      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7226      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7227      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7228      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7229      // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7230      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7231      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7232      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7233      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7234      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7235      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7236      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7237      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7238      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7239      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7240      GIR_EraseFromParent, /*InsnID*/0,
7241      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7242      // GIR_Coverage, 2950,
7243      GIR_Done,
7244    // Label 370: @17292
7245    GIM_Reject,
7246    // Label 317: @17293
7247    GIM_Try, /*On fail goto*//*Label 371*/ 17398, // Rule ID 1853 //
7248      GIM_CheckFeatures, GIFBS_HasMVEInt,
7249      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
7250      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
7251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7253      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7254      // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7255      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7256      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7257      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7258      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7259      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7260      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7261      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7262      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7263      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7264      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7265      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7266      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7267      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7268      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7269      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7270      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7271      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7272      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7273      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7274      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7275      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7276      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7277      GIR_EraseFromParent, /*InsnID*/0,
7278      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7279      // GIR_Coverage, 1853,
7280      GIR_Done,
7281    // Label 371: @17398
7282    GIM_Reject,
7283    // Label 318: @17399
7284    GIM_Try, /*On fail goto*//*Label 372*/ 17510,
7285      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7286      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7287      GIM_Try, /*On fail goto*//*Label 373*/ 17452, // Rule ID 1124 //
7288        GIM_CheckFeatures, GIFBS_HasNEON,
7289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
7292        // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
7294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
7296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
7297        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7298        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7299        GIR_EraseFromParent, /*InsnID*/0,
7300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7301        // GIR_Coverage, 1124,
7302        GIR_Done,
7303      // Label 373: @17452
7304      GIM_Try, /*On fail goto*//*Label 374*/ 17509, // Rule ID 2948 //
7305        GIM_CheckFeatures, GIFBS_HasMVEInt,
7306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7309        // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7310        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7311        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7312        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7313        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7317        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7318        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7319        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7320        GIR_EraseFromParent, /*InsnID*/0,
7321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7322        // GIR_Coverage, 2948,
7323        GIR_Done,
7324      // Label 374: @17509
7325      GIM_Reject,
7326    // Label 372: @17510
7327    GIM_Reject,
7328    // Label 319: @17511
7329    GIM_Try, /*On fail goto*//*Label 375*/ 17616, // Rule ID 1854 //
7330      GIM_CheckFeatures, GIFBS_HasMVEInt,
7331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
7332      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
7333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7334      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7335      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7336      // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7337      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7338      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7339      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7340      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7341      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7342      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7343      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7344      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7345      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7346      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7347      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7348      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7349      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7350      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7351      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7352      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7353      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7354      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7355      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7356      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7357      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7358      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7359      GIR_EraseFromParent, /*InsnID*/0,
7360      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7361      // GIR_Coverage, 1854,
7362      GIR_Done,
7363    // Label 375: @17616
7364    GIM_Reject,
7365    // Label 320: @17617
7366    GIM_Try, /*On fail goto*//*Label 376*/ 17682, // Rule ID 2946 //
7367      GIM_CheckFeatures, GIFBS_HasMVEInt,
7368      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7369      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7370      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7371      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7373      // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7374      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7375      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7376      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7377      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7378      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7381      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7382      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7383      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7384      GIR_EraseFromParent, /*InsnID*/0,
7385      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7386      // GIR_Coverage, 2946,
7387      GIR_Done,
7388    // Label 376: @17682
7389    GIM_Reject,
7390    // Label 321: @17683
7391    GIM_Try, /*On fail goto*//*Label 377*/ 17788, // Rule ID 1852 //
7392      GIM_CheckFeatures, GIFBS_HasMVEInt,
7393      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
7394      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
7395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7396      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7397      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7398      // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7399      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7400      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7401      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7402      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7403      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7404      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7405      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7406      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7407      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7408      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7409      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7410      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7411      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7412      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7413      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7414      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7415      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7416      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7417      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7418      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7420      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7421      GIR_EraseFromParent, /*InsnID*/0,
7422      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7423      // GIR_Coverage, 1852,
7424      GIR_Done,
7425    // Label 377: @17788
7426    GIM_Reject,
7427    // Label 322: @17789
7428    GIM_Try, /*On fail goto*//*Label 378*/ 17854, // Rule ID 2944 //
7429      GIM_CheckFeatures, GIFBS_HasMVEInt,
7430      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7431      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7432      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7434      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7435      // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7436      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7437      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7438      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7439      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7440      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7441      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7442      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7443      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7444      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7445      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7446      GIR_EraseFromParent, /*InsnID*/0,
7447      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7448      // GIR_Coverage, 2944,
7449      GIR_Done,
7450    // Label 378: @17854
7451    GIM_Reject,
7452    // Label 323: @17855
7453    GIM_Reject,
7454    // Label 7: @17856
7455    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 388*/ 18956,
7456    /*GILLT_s32*//*Label 379*/ 17876, 0,
7457    /*GILLT_v2s32*//*Label 380*/ 18276,
7458    /*GILLT_v2s64*//*Label 381*/ 18328,
7459    /*GILLT_v4s1*//*Label 382*/ 18394, 0,
7460    /*GILLT_v4s32*//*Label 383*/ 18500, 0,
7461    /*GILLT_v8s1*//*Label 384*/ 18612, 0,
7462    /*GILLT_v8s16*//*Label 385*/ 18718, 0,
7463    /*GILLT_v16s1*//*Label 386*/ 18784,
7464    /*GILLT_v16s8*//*Label 387*/ 18890,
7465    // Label 379: @17876
7466    GIM_Try, /*On fail goto*//*Label 389*/ 18275,
7467      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
7468      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
7469      GIM_Try, /*On fail goto*//*Label 390*/ 17936, // Rule ID 4201 //
7470        GIM_CheckFeatures, GIFBS_IsThumb2,
7471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7472        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, -1,
7473        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7474        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7475        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7476        // MIs[1] Operand 1
7477        // No operand predicates
7478        GIM_CheckIsSafeToFold, /*InsnID*/1,
7479        // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
7480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
7481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7482        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7483        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7484        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7485        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7486        GIR_EraseFromParent, /*InsnID*/0,
7487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7488        // GIR_Coverage, 4201,
7489        GIR_Done,
7490      // Label 390: @17936
7491      GIM_Try, /*On fail goto*//*Label 391*/ 17986, // Rule ID 505 //
7492        GIM_CheckFeatures, GIFBS_IsThumb2,
7493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7494        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7495        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7496        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7497        // MIs[1] Operand 1
7498        // No operand predicates
7499        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
7500        GIM_CheckIsSafeToFold, /*InsnID*/1,
7501        // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
7502        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
7503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7504        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7505        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7506        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7507        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7508        GIR_EraseFromParent, /*InsnID*/0,
7509        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7510        // GIR_Coverage, 505,
7511        GIR_Done,
7512      // Label 391: @17986
7513      GIM_Try, /*On fail goto*//*Label 392*/ 18029, // Rule ID 506 //
7514        GIM_CheckFeatures, GIFBS_IsThumb2,
7515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7516        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7517        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
7518        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7519        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr,
7520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
7522        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7523        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7524        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7525        GIR_EraseFromParent, /*InsnID*/0,
7526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7527        // GIR_Coverage, 506,
7528        GIR_Done,
7529      // Label 392: @18029
7530      GIM_Try, /*On fail goto*//*Label 393*/ 18072, // Rule ID 167 //
7531        GIM_CheckFeatures, GIFBS_IsARM,
7532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7534        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
7535        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr,
7537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
7539        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7540        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7541        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7542        GIR_EraseFromParent, /*InsnID*/0,
7543        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7544        // GIR_Coverage, 167,
7545        GIR_Done,
7546      // Label 393: @18072
7547      GIM_Try, /*On fail goto*//*Label 394*/ 18126, // Rule ID 157 //
7548        GIM_CheckFeatures, GIFBS_IsARM,
7549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7551        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7552        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7553        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
7554        // MIs[1] Operand 1
7555        // No operand predicates
7556        GIM_CheckIsSafeToFold, /*InsnID*/1,
7557        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri,
7559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7561        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7562        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7563        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7564        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7565        GIR_EraseFromParent, /*InsnID*/0,
7566        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7567        // GIR_Coverage, 157,
7568        GIR_Done,
7569      // Label 394: @18126
7570      GIM_Try, /*On fail goto*//*Label 395*/ 18180, // Rule ID 493 //
7571        GIM_CheckFeatures, GIFBS_IsThumb2,
7572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7574        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7575        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7576        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7577        // MIs[1] Operand 1
7578        // No operand predicates
7579        GIM_CheckIsSafeToFold, /*InsnID*/1,
7580        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri,
7582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7584        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7585        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7586        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7587        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7588        GIR_EraseFromParent, /*InsnID*/0,
7589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7590        // GIR_Coverage, 493,
7591        GIR_Done,
7592      // Label 395: @18180
7593      GIM_Try, /*On fail goto*//*Label 396*/ 18227, // Rule ID 158 //
7594        GIM_CheckFeatures, GIFBS_IsARM,
7595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
7598        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr,
7600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7603        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7604        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7605        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7606        GIR_EraseFromParent, /*InsnID*/0,
7607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7608        // GIR_Coverage, 158,
7609        GIR_Done,
7610      // Label 396: @18227
7611      GIM_Try, /*On fail goto*//*Label 397*/ 18274, // Rule ID 494 //
7612        GIM_CheckFeatures, GIFBS_IsThumb2,
7613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7616        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr,
7618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7621        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7622        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7623        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7624        GIR_EraseFromParent, /*InsnID*/0,
7625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7626        // GIR_Coverage, 494,
7627        GIR_Done,
7628      // Label 397: @18274
7629      GIM_Reject,
7630    // Label 389: @18275
7631    GIM_Reject,
7632    // Label 380: @18276
7633    GIM_Try, /*On fail goto*//*Label 398*/ 18327, // Rule ID 1121 //
7634      GIM_CheckFeatures, GIFBS_HasNEON,
7635      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7636      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
7637      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7638      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7639      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7640      // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7641      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
7642      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7643      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
7644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
7645      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7646      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7647      GIR_EraseFromParent, /*InsnID*/0,
7648      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7649      // GIR_Coverage, 1121,
7650      GIR_Done,
7651    // Label 398: @18327
7652    GIM_Reject,
7653    // Label 381: @18328
7654    GIM_Try, /*On fail goto*//*Label 399*/ 18393, // Rule ID 2958 //
7655      GIM_CheckFeatures, GIFBS_HasMVEInt,
7656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7657      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7659      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7660      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7661      // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7662      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7663      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7664      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7665      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7666      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7667      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7668      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7669      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7670      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7671      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7672      GIR_EraseFromParent, /*InsnID*/0,
7673      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7674      // GIR_Coverage, 2958,
7675      GIR_Done,
7676    // Label 399: @18393
7677    GIM_Reject,
7678    // Label 382: @18394
7679    GIM_Try, /*On fail goto*//*Label 400*/ 18499, // Rule ID 1850 //
7680      GIM_CheckFeatures, GIFBS_HasMVEInt,
7681      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
7682      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
7683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7684      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7685      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7686      // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7687      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7688      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7689      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7690      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7691      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7692      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7693      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7694      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7695      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7696      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7697      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7698      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7699      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7700      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7701      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7702      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7703      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7704      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7705      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7706      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7707      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7708      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7709      GIR_EraseFromParent, /*InsnID*/0,
7710      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7711      // GIR_Coverage, 1850,
7712      GIR_Done,
7713    // Label 400: @18499
7714    GIM_Reject,
7715    // Label 383: @18500
7716    GIM_Try, /*On fail goto*//*Label 401*/ 18611,
7717      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7718      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7719      GIM_Try, /*On fail goto*//*Label 402*/ 18553, // Rule ID 1122 //
7720        GIM_CheckFeatures, GIFBS_HasNEON,
7721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
7724        // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
7726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
7728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
7729        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7730        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7731        GIR_EraseFromParent, /*InsnID*/0,
7732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7733        // GIR_Coverage, 1122,
7734        GIR_Done,
7735      // Label 402: @18553
7736      GIM_Try, /*On fail goto*//*Label 403*/ 18610, // Rule ID 2956 //
7737        GIM_CheckFeatures, GIFBS_HasMVEInt,
7738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7741        // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7742        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7743        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7744        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7745        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7749        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7750        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7751        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7752        GIR_EraseFromParent, /*InsnID*/0,
7753        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7754        // GIR_Coverage, 2956,
7755        GIR_Done,
7756      // Label 403: @18610
7757      GIM_Reject,
7758    // Label 401: @18611
7759    GIM_Reject,
7760    // Label 384: @18612
7761    GIM_Try, /*On fail goto*//*Label 404*/ 18717, // Rule ID 1851 //
7762      GIM_CheckFeatures, GIFBS_HasMVEInt,
7763      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
7764      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
7765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7766      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7767      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7768      // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7769      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7770      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7771      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7772      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7773      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7774      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7775      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7776      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7777      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7778      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7779      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7780      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7781      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7782      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7783      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7784      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7785      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7786      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7787      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7788      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7789      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7790      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7791      GIR_EraseFromParent, /*InsnID*/0,
7792      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7793      // GIR_Coverage, 1851,
7794      GIR_Done,
7795    // Label 404: @18717
7796    GIM_Reject,
7797    // Label 385: @18718
7798    GIM_Try, /*On fail goto*//*Label 405*/ 18783, // Rule ID 2954 //
7799      GIM_CheckFeatures, GIFBS_HasMVEInt,
7800      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7801      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7802      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7803      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7805      // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7806      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7807      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7808      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7809      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7810      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7811      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7812      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7813      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7814      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7815      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7816      GIR_EraseFromParent, /*InsnID*/0,
7817      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7818      // GIR_Coverage, 2954,
7819      GIR_Done,
7820    // Label 405: @18783
7821    GIM_Reject,
7822    // Label 386: @18784
7823    GIM_Try, /*On fail goto*//*Label 406*/ 18889, // Rule ID 1849 //
7824      GIM_CheckFeatures, GIFBS_HasMVEInt,
7825      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
7826      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
7827      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7828      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7829      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7830      // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7831      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7832      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7833      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7834      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7835      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7836      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7837      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7838      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7839      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7840      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7841      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7842      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7843      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7844      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7845      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7846      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
7847      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7848      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
7849      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7850      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7851      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7852      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7853      GIR_EraseFromParent, /*InsnID*/0,
7854      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32,
7855      // GIR_Coverage, 1849,
7856      GIR_Done,
7857    // Label 406: @18889
7858    GIM_Reject,
7859    // Label 387: @18890
7860    GIM_Try, /*On fail goto*//*Label 407*/ 18955, // Rule ID 2952 //
7861      GIM_CheckFeatures, GIFBS_HasMVEInt,
7862      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7863      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7865      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7866      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7867      // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7868      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7869      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7870      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7871      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7873      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7874      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7875      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7876      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
7877      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7878      GIR_EraseFromParent, /*InsnID*/0,
7879      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7880      // GIR_Coverage, 2952,
7881      GIR_Done,
7882    // Label 407: @18955
7883    GIM_Reject,
7884    // Label 388: @18956
7885    GIM_Reject,
7886    // Label 8: @18957
7887    GIM_Try, /*On fail goto*//*Label 408*/ 19250,
7888      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7889      GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 15, /*)*//*default:*//*Label 413*/ 19249,
7890      /*GILLT_v2s64*//*Label 409*/ 18979, 0, 0,
7891      /*GILLT_v4s32*//*Label 410*/ 19030, 0, 0, 0,
7892      /*GILLT_v8s16*//*Label 411*/ 19114, 0, 0,
7893      /*GILLT_v16s8*//*Label 412*/ 19198,
7894      // Label 409: @18979
7895      GIM_Try, /*On fail goto*//*Label 414*/ 19029, // Rule ID 2793 //
7896        GIM_CheckFeatures, GIFBS_HasNEON,
7897        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7898        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
7899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7902        // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
7903        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
7906        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
7907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
7908        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
7909        GIR_EraseFromParent, /*InsnID*/0,
7910        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7911        // GIR_Coverage, 2793,
7912        GIR_Done,
7913      // Label 414: @19029
7914      GIM_Reject,
7915      // Label 410: @19030
7916      GIM_Try, /*On fail goto*//*Label 415*/ 19113,
7917        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7918        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
7919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7921        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7922        GIM_Try, /*On fail goto*//*Label 416*/ 19082, // Rule ID 2794 //
7923          GIM_CheckFeatures, GIFBS_HasNEON,
7924          // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
7925          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7926          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7927          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
7928          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
7929          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
7930          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
7931          GIR_EraseFromParent, /*InsnID*/0,
7932          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7933          // GIR_Coverage, 2794,
7934          GIR_Done,
7935        // Label 416: @19082
7936        GIM_Try, /*On fail goto*//*Label 417*/ 19112, // Rule ID 2797 //
7937          GIM_CheckFeatures, GIFBS_HasNEON,
7938          // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
7939          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7940          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7941          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
7942          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
7943          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
7944          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
7945          GIR_EraseFromParent, /*InsnID*/0,
7946          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7947          // GIR_Coverage, 2797,
7948          GIR_Done,
7949        // Label 417: @19112
7950        GIM_Reject,
7951      // Label 415: @19113
7952      GIM_Reject,
7953      // Label 411: @19114
7954      GIM_Try, /*On fail goto*//*Label 418*/ 19197,
7955        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7956        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
7957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7960        GIM_Try, /*On fail goto*//*Label 419*/ 19166, // Rule ID 2795 //
7961          GIM_CheckFeatures, GIFBS_HasNEON,
7962          // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
7963          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7964          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7965          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
7966          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
7967          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
7968          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
7969          GIR_EraseFromParent, /*InsnID*/0,
7970          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7971          // GIR_Coverage, 2795,
7972          GIR_Done,
7973        // Label 419: @19166
7974        GIM_Try, /*On fail goto*//*Label 420*/ 19196, // Rule ID 2798 //
7975          GIM_CheckFeatures, GIFBS_HasNEON,
7976          // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
7977          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7978          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7979          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
7980          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
7981          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
7982          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
7983          GIR_EraseFromParent, /*InsnID*/0,
7984          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7985          // GIR_Coverage, 2798,
7986          GIR_Done,
7987        // Label 420: @19196
7988        GIM_Reject,
7989      // Label 418: @19197
7990      GIM_Reject,
7991      // Label 412: @19198
7992      GIM_Try, /*On fail goto*//*Label 421*/ 19248, // Rule ID 2796 //
7993        GIM_CheckFeatures, GIFBS_HasNEON,
7994        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
7996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7999        // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
8000        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8003        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8005        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8006        GIR_EraseFromParent, /*InsnID*/0,
8007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8008        // GIR_Coverage, 2796,
8009        GIR_Done,
8010      // Label 421: @19248
8011      GIM_Reject,
8012      // Label 413: @19249
8013      GIM_Reject,
8014    // Label 408: @19250
8015    GIM_Reject,
8016    // Label 9: @19251
8017    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 431*/ 28357,
8018    /*GILLT_s32*//*Label 422*/ 19271,
8019    /*GILLT_s64*//*Label 423*/ 19349,
8020    /*GILLT_v2s32*//*Label 424*/ 20148,
8021    /*GILLT_v2s64*//*Label 425*/ 20947, 0,
8022    /*GILLT_v4s16*//*Label 426*/ 22684,
8023    /*GILLT_v4s32*//*Label 427*/ 23483, 0, 0,
8024    /*GILLT_v8s8*//*Label 428*/ 25220,
8025    /*GILLT_v8s16*//*Label 429*/ 25659, 0, 0,
8026    /*GILLT_v16s8*//*Label 430*/ 27396,
8027    // Label 422: @19271
8028    GIM_Try, /*On fail goto*//*Label 432*/ 19348,
8029      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
8030      GIM_Try, /*On fail goto*//*Label 433*/ 19312, // Rule ID 702 //
8031        GIM_CheckFeatures, GIFBS_HasFPRegs,
8032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
8034        // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn)  =>  (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
8035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS,
8036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
8037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
8038        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8039        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8040        GIR_EraseFromParent, /*InsnID*/0,
8041        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8042        // GIR_Coverage, 702,
8043        GIR_Done,
8044      // Label 433: @19312
8045      GIM_Try, /*On fail goto*//*Label 434*/ 19347, // Rule ID 703 //
8046        GIM_CheckFeatures, GIFBS_HasFPRegs_UseVMOVSR,
8047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8049        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt)  =>  (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
8050        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR,
8051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sn
8052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
8053        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8054        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8055        GIR_EraseFromParent, /*InsnID*/0,
8056        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8057        // GIR_Coverage, 703,
8058        GIR_Done,
8059      // Label 434: @19347
8060      GIM_Reject,
8061    // Label 432: @19348
8062    GIM_Reject,
8063    // Label 423: @19349
8064    GIM_Try, /*On fail goto*//*Label 435*/ 19383, // Rule ID 2587 //
8065      GIM_CheckFeatures, GIFBS_HasNEON,
8066      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8067      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8068      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8069      // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[f64] }:$src
8070      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8071      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8072      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8073      GIR_EraseFromParent, /*InsnID*/0,
8074      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8075      // GIR_Coverage, 2587,
8076      GIR_Done,
8077    // Label 435: @19383
8078    GIM_Try, /*On fail goto*//*Label 436*/ 19417, // Rule ID 2588 //
8079      GIM_CheckFeatures, GIFBS_HasNEON,
8080      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8081      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8082      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8083      // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8084      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8085      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8086      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8087      GIR_EraseFromParent, /*InsnID*/0,
8088      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8089      // GIR_Coverage, 2588,
8090      GIR_Done,
8091    // Label 436: @19417
8092    GIM_Try, /*On fail goto*//*Label 437*/ 19451, // Rule ID 2599 //
8093      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8094      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8095      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8096      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8097      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[f64] }:$src
8098      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8099      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8100      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8101      GIR_EraseFromParent, /*InsnID*/0,
8102      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8103      // GIR_Coverage, 2599,
8104      GIR_Done,
8105    // Label 437: @19451
8106    GIM_Try, /*On fail goto*//*Label 438*/ 19485, // Rule ID 2600 //
8107      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8108      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8109      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8110      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8111      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[f64] }:$src
8112      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8113      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8114      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8115      GIR_EraseFromParent, /*InsnID*/0,
8116      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8117      // GIR_Coverage, 2600,
8118      GIR_Done,
8119    // Label 438: @19485
8120    GIM_Try, /*On fail goto*//*Label 439*/ 19519, // Rule ID 2601 //
8121      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8122      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8124      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8125      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[f64] }:$src
8126      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8127      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8128      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8129      GIR_EraseFromParent, /*InsnID*/0,
8130      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8131      // GIR_Coverage, 2601,
8132      GIR_Done,
8133    // Label 439: @19519
8134    GIM_Try, /*On fail goto*//*Label 440*/ 19553, // Rule ID 2602 //
8135      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8136      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8139      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[f64] }:$src
8140      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8142      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8143      GIR_EraseFromParent, /*InsnID*/0,
8144      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8145      // GIR_Coverage, 2602,
8146      GIR_Done,
8147    // Label 440: @19553
8148    GIM_Try, /*On fail goto*//*Label 441*/ 19587, // Rule ID 2603 //
8149      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8150      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8153      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[f64] }:$src
8154      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8156      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8157      GIR_EraseFromParent, /*InsnID*/0,
8158      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8159      // GIR_Coverage, 2603,
8160      GIR_Done,
8161    // Label 441: @19587
8162    GIM_Try, /*On fail goto*//*Label 442*/ 19621, // Rule ID 2604 //
8163      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8164      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8165      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8167      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8168      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8169      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8170      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8171      GIR_EraseFromParent, /*InsnID*/0,
8172      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8173      // GIR_Coverage, 2604,
8174      GIR_Done,
8175    // Label 442: @19621
8176    GIM_Try, /*On fail goto*//*Label 443*/ 19655, // Rule ID 2605 //
8177      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8178      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8179      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8181      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8182      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8183      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8184      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8185      GIR_EraseFromParent, /*InsnID*/0,
8186      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8187      // GIR_Coverage, 2605,
8188      GIR_Done,
8189    // Label 443: @19655
8190    GIM_Try, /*On fail goto*//*Label 444*/ 19689, // Rule ID 2606 //
8191      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8192      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8194      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8195      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8196      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8197      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8198      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8199      GIR_EraseFromParent, /*InsnID*/0,
8200      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8201      // GIR_Coverage, 2606,
8202      GIR_Done,
8203    // Label 444: @19689
8204    GIM_Try, /*On fail goto*//*Label 445*/ 19723, // Rule ID 2607 //
8205      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8206      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8208      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8209      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8210      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8211      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8212      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8213      GIR_EraseFromParent, /*InsnID*/0,
8214      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8215      // GIR_Coverage, 2607,
8216      GIR_Done,
8217    // Label 445: @19723
8218    GIM_Try, /*On fail goto*//*Label 446*/ 19757, // Rule ID 2608 //
8219      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8220      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8221      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8222      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8223      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v1i64] }:$src
8224      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8225      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8226      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8227      GIR_EraseFromParent, /*InsnID*/0,
8228      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8229      // GIR_Coverage, 2608,
8230      GIR_Done,
8231    // Label 446: @19757
8232    GIM_Try, /*On fail goto*//*Label 447*/ 19796, // Rule ID 2671 //
8233      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8234      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8235      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8237      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
8238      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8239      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8240      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8241      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8242      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8243      GIR_EraseFromParent, /*InsnID*/0,
8244      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8245      // GIR_Coverage, 2671,
8246      GIR_Done,
8247    // Label 447: @19796
8248    GIM_Try, /*On fail goto*//*Label 448*/ 19835, // Rule ID 2672 //
8249      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8250      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8253      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
8254      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8255      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8257      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8258      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8259      GIR_EraseFromParent, /*InsnID*/0,
8260      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8261      // GIR_Coverage, 2672,
8262      GIR_Done,
8263    // Label 448: @19835
8264    GIM_Try, /*On fail goto*//*Label 449*/ 19874, // Rule ID 2673 //
8265      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8266      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8267      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8269      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
8270      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8271      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8272      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8273      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8274      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8275      GIR_EraseFromParent, /*InsnID*/0,
8276      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8277      // GIR_Coverage, 2673,
8278      GIR_Done,
8279    // Label 449: @19874
8280    GIM_Try, /*On fail goto*//*Label 450*/ 19913, // Rule ID 2674 //
8281      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8282      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8284      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8285      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
8286      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8287      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8288      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8289      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8290      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8291      GIR_EraseFromParent, /*InsnID*/0,
8292      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8293      // GIR_Coverage, 2674,
8294      GIR_Done,
8295    // Label 450: @19913
8296    GIM_Try, /*On fail goto*//*Label 451*/ 19952, // Rule ID 2675 //
8297      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8298      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8299      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8300      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8301      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
8302      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8303      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8304      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8305      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8306      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8307      GIR_EraseFromParent, /*InsnID*/0,
8308      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8309      // GIR_Coverage, 2675,
8310      GIR_Done,
8311    // Label 451: @19952
8312    GIM_Try, /*On fail goto*//*Label 452*/ 19991, // Rule ID 2676 //
8313      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8314      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8315      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8317      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
8318      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8319      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8320      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8321      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8322      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8323      GIR_EraseFromParent, /*InsnID*/0,
8324      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8325      // GIR_Coverage, 2676,
8326      GIR_Done,
8327    // Label 452: @19991
8328    GIM_Try, /*On fail goto*//*Label 453*/ 20030, // Rule ID 2677 //
8329      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8330      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8333      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
8334      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8335      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8337      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8338      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8339      GIR_EraseFromParent, /*InsnID*/0,
8340      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8341      // GIR_Coverage, 2677,
8342      GIR_Done,
8343    // Label 453: @20030
8344    GIM_Try, /*On fail goto*//*Label 454*/ 20069, // Rule ID 2678 //
8345      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8346      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8349      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
8350      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8351      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8353      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8354      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8355      GIR_EraseFromParent, /*InsnID*/0,
8356      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8357      // GIR_Coverage, 2678,
8358      GIR_Done,
8359    // Label 454: @20069
8360    GIM_Try, /*On fail goto*//*Label 455*/ 20108, // Rule ID 2679 //
8361      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8362      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8363      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8364      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8365      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
8366      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8367      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8368      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8369      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8370      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8371      GIR_EraseFromParent, /*InsnID*/0,
8372      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8373      // GIR_Coverage, 2679,
8374      GIR_Done,
8375    // Label 455: @20108
8376    GIM_Try, /*On fail goto*//*Label 456*/ 20147, // Rule ID 2680 //
8377      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8378      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8379      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8381      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
8382      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8383      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8384      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8385      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8386      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8387      GIR_EraseFromParent, /*InsnID*/0,
8388      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8389      // GIR_Coverage, 2680,
8390      GIR_Done,
8391    // Label 456: @20147
8392    GIM_Reject,
8393    // Label 424: @20148
8394    GIM_Try, /*On fail goto*//*Label 457*/ 20182, // Rule ID 2589 //
8395      GIM_CheckFeatures, GIFBS_HasNEON,
8396      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8397      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8398      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8399      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8400      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8401      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8402      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8403      GIR_EraseFromParent, /*InsnID*/0,
8404      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8405      // GIR_Coverage, 2589,
8406      GIR_Done,
8407    // Label 457: @20182
8408    GIM_Try, /*On fail goto*//*Label 458*/ 20216, // Rule ID 2590 //
8409      GIM_CheckFeatures, GIFBS_HasNEON,
8410      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8411      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8412      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8413      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8414      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8415      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8416      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8417      GIR_EraseFromParent, /*InsnID*/0,
8418      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8419      // GIR_Coverage, 2590,
8420      GIR_Done,
8421    // Label 458: @20216
8422    GIM_Try, /*On fail goto*//*Label 459*/ 20250, // Rule ID 2609 //
8423      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8424      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8426      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8427      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8428      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8429      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8430      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8431      GIR_EraseFromParent, /*InsnID*/0,
8432      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8433      // GIR_Coverage, 2609,
8434      GIR_Done,
8435    // Label 459: @20250
8436    GIM_Try, /*On fail goto*//*Label 460*/ 20284, // Rule ID 2610 //
8437      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8438      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8439      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8441      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8442      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8444      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8445      GIR_EraseFromParent, /*InsnID*/0,
8446      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8447      // GIR_Coverage, 2610,
8448      GIR_Done,
8449    // Label 460: @20284
8450    GIM_Try, /*On fail goto*//*Label 461*/ 20318, // Rule ID 2611 //
8451      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8455      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8459      GIR_EraseFromParent, /*InsnID*/0,
8460      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8461      // GIR_Coverage, 2611,
8462      GIR_Done,
8463    // Label 461: @20318
8464    GIM_Try, /*On fail goto*//*Label 462*/ 20352, // Rule ID 2612 //
8465      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8466      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8469      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8470      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8471      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8472      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8473      GIR_EraseFromParent, /*InsnID*/0,
8474      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8475      // GIR_Coverage, 2612,
8476      GIR_Done,
8477    // Label 462: @20352
8478    GIM_Try, /*On fail goto*//*Label 463*/ 20386, // Rule ID 2613 //
8479      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8483      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2f32] }:$src
8484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8487      GIR_EraseFromParent, /*InsnID*/0,
8488      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8489      // GIR_Coverage, 2613,
8490      GIR_Done,
8491    // Label 463: @20386
8492    GIM_Try, /*On fail goto*//*Label 464*/ 20420, // Rule ID 2614 //
8493      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8494      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8497      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8498      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8501      GIR_EraseFromParent, /*InsnID*/0,
8502      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8503      // GIR_Coverage, 2614,
8504      GIR_Done,
8505    // Label 464: @20420
8506    GIM_Try, /*On fail goto*//*Label 465*/ 20454, // Rule ID 2615 //
8507      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8508      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8510      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8511      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8512      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8513      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8515      GIR_EraseFromParent, /*InsnID*/0,
8516      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8517      // GIR_Coverage, 2615,
8518      GIR_Done,
8519    // Label 465: @20454
8520    GIM_Try, /*On fail goto*//*Label 466*/ 20488, // Rule ID 2616 //
8521      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8525      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8526      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8527      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8528      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8529      GIR_EraseFromParent, /*InsnID*/0,
8530      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8531      // GIR_Coverage, 2616,
8532      GIR_Done,
8533    // Label 466: @20488
8534    GIM_Try, /*On fail goto*//*Label 467*/ 20522, // Rule ID 2617 //
8535      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8536      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8539      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8540      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8543      GIR_EraseFromParent, /*InsnID*/0,
8544      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8545      // GIR_Coverage, 2617,
8546      GIR_Done,
8547    // Label 467: @20522
8548    GIM_Try, /*On fail goto*//*Label 468*/ 20556, // Rule ID 2618 //
8549      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8550      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8553      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2i32] }:$src
8554      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8555      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8556      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8557      GIR_EraseFromParent, /*InsnID*/0,
8558      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
8559      // GIR_Coverage, 2618,
8560      GIR_Done,
8561    // Label 468: @20556
8562    GIM_Try, /*On fail goto*//*Label 469*/ 20595, // Rule ID 2681 //
8563      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8564      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8565      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8566      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8567      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
8568      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8569      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8570      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8571      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8572      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8573      GIR_EraseFromParent, /*InsnID*/0,
8574      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8575      // GIR_Coverage, 2681,
8576      GIR_Done,
8577    // Label 469: @20595
8578    GIM_Try, /*On fail goto*//*Label 470*/ 20634, // Rule ID 2682 //
8579      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8580      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8581      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8582      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8583      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
8584      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8585      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8586      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8587      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8588      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8589      GIR_EraseFromParent, /*InsnID*/0,
8590      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8591      // GIR_Coverage, 2682,
8592      GIR_Done,
8593    // Label 470: @20634
8594    GIM_Try, /*On fail goto*//*Label 471*/ 20673, // Rule ID 2683 //
8595      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8596      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8597      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8599      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
8600      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8601      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8603      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8604      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8605      GIR_EraseFromParent, /*InsnID*/0,
8606      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8607      // GIR_Coverage, 2683,
8608      GIR_Done,
8609    // Label 471: @20673
8610    GIM_Try, /*On fail goto*//*Label 472*/ 20712, // Rule ID 2684 //
8611      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8612      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8614      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8615      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
8616      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8619      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8620      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8621      GIR_EraseFromParent, /*InsnID*/0,
8622      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8623      // GIR_Coverage, 2684,
8624      GIR_Done,
8625    // Label 472: @20712
8626    GIM_Try, /*On fail goto*//*Label 473*/ 20751, // Rule ID 2685 //
8627      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8628      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8629      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8630      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8631      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
8632      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8633      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8634      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8635      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8636      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8637      GIR_EraseFromParent, /*InsnID*/0,
8638      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8639      // GIR_Coverage, 2685,
8640      GIR_Done,
8641    // Label 473: @20751
8642    GIM_Try, /*On fail goto*//*Label 474*/ 20790, // Rule ID 2686 //
8643      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8644      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8645      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8646      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8647      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
8648      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8649      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8650      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8651      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8652      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8653      GIR_EraseFromParent, /*InsnID*/0,
8654      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8655      // GIR_Coverage, 2686,
8656      GIR_Done,
8657    // Label 474: @20790
8658    GIM_Try, /*On fail goto*//*Label 475*/ 20829, // Rule ID 2687 //
8659      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8660      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8661      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8662      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8663      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
8664      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8665      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8666      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8667      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8668      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8669      GIR_EraseFromParent, /*InsnID*/0,
8670      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8671      // GIR_Coverage, 2687,
8672      GIR_Done,
8673    // Label 475: @20829
8674    GIM_Try, /*On fail goto*//*Label 476*/ 20868, // Rule ID 2688 //
8675      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8676      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8677      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8678      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8679      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
8680      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8682      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8683      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8684      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8685      GIR_EraseFromParent, /*InsnID*/0,
8686      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8687      // GIR_Coverage, 2688,
8688      GIR_Done,
8689    // Label 476: @20868
8690    GIM_Try, /*On fail goto*//*Label 477*/ 20907, // Rule ID 2689 //
8691      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8692      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8694      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8695      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
8696      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8698      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8699      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8700      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8701      GIR_EraseFromParent, /*InsnID*/0,
8702      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8703      // GIR_Coverage, 2689,
8704      GIR_Done,
8705    // Label 477: @20907
8706    GIM_Try, /*On fail goto*//*Label 478*/ 20946, // Rule ID 2690 //
8707      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8708      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8709      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8710      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8711      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
8712      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8713      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8714      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8715      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8716      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8717      GIR_EraseFromParent, /*InsnID*/0,
8718      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8719      // GIR_Coverage, 2690,
8720      GIR_Done,
8721    // Label 478: @20946
8722    GIM_Reject,
8723    // Label 425: @20947
8724    GIM_Try, /*On fail goto*//*Label 479*/ 20981, // Rule ID 2593 //
8725      GIM_CheckFeatures, GIFBS_HasNEON,
8726      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8729      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8730      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8733      GIR_EraseFromParent, /*InsnID*/0,
8734      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8735      // GIR_Coverage, 2593,
8736      GIR_Done,
8737    // Label 479: @20981
8738    GIM_Try, /*On fail goto*//*Label 480*/ 21015, // Rule ID 2594 //
8739      GIM_CheckFeatures, GIFBS_HasNEON,
8740      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8743      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8744      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8745      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8746      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8747      GIR_EraseFromParent, /*InsnID*/0,
8748      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8749      // GIR_Coverage, 2594,
8750      GIR_Done,
8751    // Label 480: @21015
8752    GIM_Try, /*On fail goto*//*Label 481*/ 21049, // Rule ID 2635 //
8753      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8754      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8757      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8758      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8761      GIR_EraseFromParent, /*InsnID*/0,
8762      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8763      // GIR_Coverage, 2635,
8764      GIR_Done,
8765    // Label 481: @21049
8766    GIM_Try, /*On fail goto*//*Label 482*/ 21083, // Rule ID 2636 //
8767      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8768      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8769      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8771      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8772      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8773      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8774      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8775      GIR_EraseFromParent, /*InsnID*/0,
8776      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8777      // GIR_Coverage, 2636,
8778      GIR_Done,
8779    // Label 482: @21083
8780    GIM_Try, /*On fail goto*//*Label 483*/ 21117, // Rule ID 2637 //
8781      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8782      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8783      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8784      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8785      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8786      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8787      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8788      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8789      GIR_EraseFromParent, /*InsnID*/0,
8790      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8791      // GIR_Coverage, 2637,
8792      GIR_Done,
8793    // Label 483: @21117
8794    GIM_Try, /*On fail goto*//*Label 484*/ 21151, // Rule ID 2638 //
8795      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8797      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8799      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8803      GIR_EraseFromParent, /*InsnID*/0,
8804      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8805      // GIR_Coverage, 2638,
8806      GIR_Done,
8807    // Label 484: @21151
8808    GIM_Try, /*On fail goto*//*Label 485*/ 21185, // Rule ID 2639 //
8809      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8810      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8811      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8812      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8813      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2f64] }:$src
8814      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8815      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8816      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8817      GIR_EraseFromParent, /*InsnID*/0,
8818      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8819      // GIR_Coverage, 2639,
8820      GIR_Done,
8821    // Label 485: @21185
8822    GIM_Try, /*On fail goto*//*Label 486*/ 21219, // Rule ID 2640 //
8823      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8824      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8825      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8826      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8827      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8828      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8829      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8830      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8831      GIR_EraseFromParent, /*InsnID*/0,
8832      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8833      // GIR_Coverage, 2640,
8834      GIR_Done,
8835    // Label 486: @21219
8836    GIM_Try, /*On fail goto*//*Label 487*/ 21253, // Rule ID 2641 //
8837      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8838      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8840      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8841      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8842      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8845      GIR_EraseFromParent, /*InsnID*/0,
8846      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8847      // GIR_Coverage, 2641,
8848      GIR_Done,
8849    // Label 487: @21253
8850    GIM_Try, /*On fail goto*//*Label 488*/ 21287, // Rule ID 2642 //
8851      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8852      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8854      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8855      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8856      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8858      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8859      GIR_EraseFromParent, /*InsnID*/0,
8860      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8861      // GIR_Coverage, 2642,
8862      GIR_Done,
8863    // Label 488: @21287
8864    GIM_Try, /*On fail goto*//*Label 489*/ 21321, // Rule ID 2643 //
8865      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8866      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8869      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8870      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8873      GIR_EraseFromParent, /*InsnID*/0,
8874      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8875      // GIR_Coverage, 2643,
8876      GIR_Done,
8877    // Label 489: @21321
8878    GIM_Try, /*On fail goto*//*Label 490*/ 21355, // Rule ID 2644 //
8879      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8880      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8883      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2i64] }:$src
8884      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8885      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8886      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8887      GIR_EraseFromParent, /*InsnID*/0,
8888      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
8889      // GIR_Coverage, 2644,
8890      GIR_Done,
8891    // Label 490: @21355
8892    GIM_Try, /*On fail goto*//*Label 491*/ 21394, // Rule ID 2707 //
8893      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8894      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8897      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
8898      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8899      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8900      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8901      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8902      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8903      GIR_EraseFromParent, /*InsnID*/0,
8904      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8905      // GIR_Coverage, 2707,
8906      GIR_Done,
8907    // Label 491: @21394
8908    GIM_Try, /*On fail goto*//*Label 492*/ 21433, // Rule ID 2708 //
8909      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8910      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8912      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8913      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
8914      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8915      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8916      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8917      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8918      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8919      GIR_EraseFromParent, /*InsnID*/0,
8920      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8921      // GIR_Coverage, 2708,
8922      GIR_Done,
8923    // Label 492: @21433
8924    GIM_Try, /*On fail goto*//*Label 493*/ 21472, // Rule ID 2709 //
8925      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8926      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8927      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8928      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8929      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
8930      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8931      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8932      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8933      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8934      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8935      GIR_EraseFromParent, /*InsnID*/0,
8936      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8937      // GIR_Coverage, 2709,
8938      GIR_Done,
8939    // Label 493: @21472
8940    GIM_Try, /*On fail goto*//*Label 494*/ 21511, // Rule ID 2710 //
8941      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8942      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8943      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8944      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8945      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
8946      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8947      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8948      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8949      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8950      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8951      GIR_EraseFromParent, /*InsnID*/0,
8952      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8953      // GIR_Coverage, 2710,
8954      GIR_Done,
8955    // Label 494: @21511
8956    GIM_Try, /*On fail goto*//*Label 495*/ 21550, // Rule ID 2711 //
8957      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8958      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8961      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
8962      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
8963      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8964      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8965      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8966      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8967      GIR_EraseFromParent, /*InsnID*/0,
8968      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8969      // GIR_Coverage, 2711,
8970      GIR_Done,
8971    // Label 495: @21550
8972    GIM_Try, /*On fail goto*//*Label 496*/ 21589, // Rule ID 2712 //
8973      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8974      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8975      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8976      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8977      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
8978      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8979      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8980      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8981      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8982      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8983      GIR_EraseFromParent, /*InsnID*/0,
8984      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8985      // GIR_Coverage, 2712,
8986      GIR_Done,
8987    // Label 496: @21589
8988    GIM_Try, /*On fail goto*//*Label 497*/ 21628, // Rule ID 2713 //
8989      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
8990      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8993      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
8994      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8995      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8996      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8997      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8998      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
8999      GIR_EraseFromParent, /*InsnID*/0,
9000      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9001      // GIR_Coverage, 2713,
9002      GIR_Done,
9003    // Label 497: @21628
9004    GIM_Try, /*On fail goto*//*Label 498*/ 21667, // Rule ID 2714 //
9005      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9006      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9009      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
9010      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9011      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9012      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9013      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9014      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9015      GIR_EraseFromParent, /*InsnID*/0,
9016      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9017      // GIR_Coverage, 2714,
9018      GIR_Done,
9019    // Label 498: @21667
9020    GIM_Try, /*On fail goto*//*Label 499*/ 21706, // Rule ID 2715 //
9021      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9022      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9023      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9024      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9025      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
9026      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9027      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9028      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9029      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9030      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9031      GIR_EraseFromParent, /*InsnID*/0,
9032      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9033      // GIR_Coverage, 2715,
9034      GIR_Done,
9035    // Label 499: @21706
9036    GIM_Try, /*On fail goto*//*Label 500*/ 21745, // Rule ID 2716 //
9037      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9038      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9039      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9040      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9041      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
9042      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
9043      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9044      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9045      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9046      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9047      GIR_EraseFromParent, /*InsnID*/0,
9048      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9049      // GIR_Coverage, 2716,
9050      GIR_Done,
9051    // Label 500: @21745
9052    GIM_Try, /*On fail goto*//*Label 501*/ 21779, // Rule ID 4065 //
9053      GIM_CheckFeatures, GIFBS_HasMVEInt,
9054      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9055      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9056      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9057      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9058      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9059      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9061      GIR_EraseFromParent, /*InsnID*/0,
9062      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9063      // GIR_Coverage, 4065,
9064      GIR_Done,
9065    // Label 501: @21779
9066    GIM_Try, /*On fail goto*//*Label 502*/ 21813, // Rule ID 4066 //
9067      GIM_CheckFeatures, GIFBS_HasMVEInt,
9068      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9069      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9070      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9071      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9072      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9073      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9074      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9075      GIR_EraseFromParent, /*InsnID*/0,
9076      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9077      // GIR_Coverage, 4066,
9078      GIR_Done,
9079    // Label 502: @21813
9080    GIM_Try, /*On fail goto*//*Label 503*/ 21847, // Rule ID 4071 //
9081      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9085      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9086      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9087      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9088      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9089      GIR_EraseFromParent, /*InsnID*/0,
9090      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9091      // GIR_Coverage, 4071,
9092      GIR_Done,
9093    // Label 503: @21847
9094    GIM_Try, /*On fail goto*//*Label 504*/ 21881, // Rule ID 4072 //
9095      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9096      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9097      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9098      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9099      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9100      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9101      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9102      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9103      GIR_EraseFromParent, /*InsnID*/0,
9104      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9105      // GIR_Coverage, 4072,
9106      GIR_Done,
9107    // Label 504: @21881
9108    GIM_Try, /*On fail goto*//*Label 505*/ 21915, // Rule ID 4073 //
9109      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9110      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9111      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9112      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9113      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9114      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9115      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9116      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9117      GIR_EraseFromParent, /*InsnID*/0,
9118      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9119      // GIR_Coverage, 4073,
9120      GIR_Done,
9121    // Label 505: @21915
9122    GIM_Try, /*On fail goto*//*Label 506*/ 21949, // Rule ID 4074 //
9123      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9124      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9126      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9127      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9128      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9129      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9130      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9131      GIR_EraseFromParent, /*InsnID*/0,
9132      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9133      // GIR_Coverage, 4074,
9134      GIR_Done,
9135    // Label 506: @21949
9136    GIM_Try, /*On fail goto*//*Label 507*/ 21983, // Rule ID 4075 //
9137      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9138      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9141      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
9142      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9145      GIR_EraseFromParent, /*InsnID*/0,
9146      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9147      // GIR_Coverage, 4075,
9148      GIR_Done,
9149    // Label 507: @21983
9150    GIM_Try, /*On fail goto*//*Label 508*/ 22017, // Rule ID 4076 //
9151      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9152      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9153      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9155      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9156      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9157      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9159      GIR_EraseFromParent, /*InsnID*/0,
9160      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9161      // GIR_Coverage, 4076,
9162      GIR_Done,
9163    // Label 508: @22017
9164    GIM_Try, /*On fail goto*//*Label 509*/ 22051, // Rule ID 4077 //
9165      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9166      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9167      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9169      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9170      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9171      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9172      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9173      GIR_EraseFromParent, /*InsnID*/0,
9174      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9175      // GIR_Coverage, 4077,
9176      GIR_Done,
9177    // Label 509: @22051
9178    GIM_Try, /*On fail goto*//*Label 510*/ 22085, // Rule ID 4078 //
9179      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9180      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9183      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9184      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9185      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9187      GIR_EraseFromParent, /*InsnID*/0,
9188      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9189      // GIR_Coverage, 4078,
9190      GIR_Done,
9191    // Label 510: @22085
9192    GIM_Try, /*On fail goto*//*Label 511*/ 22119, // Rule ID 4079 //
9193      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9194      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9196      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9197      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9198      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9199      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9200      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9201      GIR_EraseFromParent, /*InsnID*/0,
9202      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9203      // GIR_Coverage, 4079,
9204      GIR_Done,
9205    // Label 511: @22119
9206    GIM_Try, /*On fail goto*//*Label 512*/ 22153, // Rule ID 4080 //
9207      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
9208      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9209      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9211      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
9212      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9213      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9214      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9215      GIR_EraseFromParent, /*InsnID*/0,
9216      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
9217      // GIR_Coverage, 4080,
9218      GIR_Done,
9219    // Label 512: @22153
9220    GIM_Try, /*On fail goto*//*Label 513*/ 22206, // Rule ID 4107 //
9221      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9222      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9224      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9225      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
9226      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9227      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9228      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9229      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9230      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9231      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9232      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9233      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9234      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9235      GIR_EraseFromParent, /*InsnID*/0,
9236      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9237      // GIR_Coverage, 4107,
9238      GIR_Done,
9239    // Label 513: @22206
9240    GIM_Try, /*On fail goto*//*Label 514*/ 22259, // Rule ID 4108 //
9241      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9242      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9243      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9245      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
9246      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9247      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9248      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9249      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9250      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9251      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9252      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9253      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9254      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9255      GIR_EraseFromParent, /*InsnID*/0,
9256      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9257      // GIR_Coverage, 4108,
9258      GIR_Done,
9259    // Label 514: @22259
9260    GIM_Try, /*On fail goto*//*Label 515*/ 22312, // Rule ID 4109 //
9261      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9262      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9264      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9265      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
9266      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9267      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9268      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9269      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9270      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9271      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9272      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9273      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9274      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9275      GIR_EraseFromParent, /*InsnID*/0,
9276      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9277      // GIR_Coverage, 4109,
9278      GIR_Done,
9279    // Label 515: @22312
9280    GIM_Try, /*On fail goto*//*Label 516*/ 22365, // Rule ID 4110 //
9281      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9282      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9284      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9285      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
9286      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9287      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9288      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9289      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9290      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9291      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9292      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9293      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9294      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9295      GIR_EraseFromParent, /*InsnID*/0,
9296      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9297      // GIR_Coverage, 4110,
9298      GIR_Done,
9299    // Label 516: @22365
9300    GIM_Try, /*On fail goto*//*Label 517*/ 22418, // Rule ID 4111 //
9301      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9302      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9303      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9304      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9305      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
9306      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9307      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9308      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9309      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
9310      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9311      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9312      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9313      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9314      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9315      GIR_EraseFromParent, /*InsnID*/0,
9316      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9317      // GIR_Coverage, 4111,
9318      GIR_Done,
9319    // Label 517: @22418
9320    GIM_Try, /*On fail goto*//*Label 518*/ 22471, // Rule ID 4112 //
9321      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9322      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9323      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9324      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9325      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
9326      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9327      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9328      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9329      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9330      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9331      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9332      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9333      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9334      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9335      GIR_EraseFromParent, /*InsnID*/0,
9336      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9337      // GIR_Coverage, 4112,
9338      GIR_Done,
9339    // Label 518: @22471
9340    GIM_Try, /*On fail goto*//*Label 519*/ 22524, // Rule ID 4113 //
9341      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9342      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9343      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9344      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9345      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
9346      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9347      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9348      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9349      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9350      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9351      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9352      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9353      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9354      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9355      GIR_EraseFromParent, /*InsnID*/0,
9356      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9357      // GIR_Coverage, 4113,
9358      GIR_Done,
9359    // Label 519: @22524
9360    GIM_Try, /*On fail goto*//*Label 520*/ 22577, // Rule ID 4114 //
9361      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9362      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9363      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9364      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9365      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
9366      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9367      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9368      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9369      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9370      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9371      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9372      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9373      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9374      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9375      GIR_EraseFromParent, /*InsnID*/0,
9376      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9377      // GIR_Coverage, 4114,
9378      GIR_Done,
9379    // Label 520: @22577
9380    GIM_Try, /*On fail goto*//*Label 521*/ 22630, // Rule ID 4115 //
9381      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9382      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9383      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9384      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9385      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
9386      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9387      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9388      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9389      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9390      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9391      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9392      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9393      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9394      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9395      GIR_EraseFromParent, /*InsnID*/0,
9396      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9397      // GIR_Coverage, 4115,
9398      GIR_Done,
9399    // Label 521: @22630
9400    GIM_Try, /*On fail goto*//*Label 522*/ 22683, // Rule ID 4116 //
9401      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
9402      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9404      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9405      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
9406      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9407      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9408      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9409      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
9410      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9411      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9412      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9413      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9414      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9415      GIR_EraseFromParent, /*InsnID*/0,
9416      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9417      // GIR_Coverage, 4116,
9418      GIR_Done,
9419    // Label 522: @22683
9420    GIM_Reject,
9421    // Label 426: @22684
9422    GIM_Try, /*On fail goto*//*Label 523*/ 22718, // Rule ID 2591 //
9423      GIM_CheckFeatures, GIFBS_HasNEON,
9424      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9426      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9427      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9428      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9429      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9430      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9431      GIR_EraseFromParent, /*InsnID*/0,
9432      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9433      // GIR_Coverage, 2591,
9434      GIR_Done,
9435    // Label 523: @22718
9436    GIM_Try, /*On fail goto*//*Label 524*/ 22752, // Rule ID 2592 //
9437      GIM_CheckFeatures, GIFBS_HasNEON,
9438      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9439      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9441      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9442      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9444      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9445      GIR_EraseFromParent, /*InsnID*/0,
9446      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9447      // GIR_Coverage, 2592,
9448      GIR_Done,
9449    // Label 524: @22752
9450    GIM_Try, /*On fail goto*//*Label 525*/ 22786, // Rule ID 2619 //
9451      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9455      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9459      GIR_EraseFromParent, /*InsnID*/0,
9460      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9461      // GIR_Coverage, 2619,
9462      GIR_Done,
9463    // Label 525: @22786
9464    GIM_Try, /*On fail goto*//*Label 526*/ 22820, // Rule ID 2620 //
9465      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9466      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9469      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9470      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9471      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9472      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9473      GIR_EraseFromParent, /*InsnID*/0,
9474      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9475      // GIR_Coverage, 2620,
9476      GIR_Done,
9477    // Label 526: @22820
9478    GIM_Try, /*On fail goto*//*Label 527*/ 22854, // Rule ID 2621 //
9479      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9483      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9487      GIR_EraseFromParent, /*InsnID*/0,
9488      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9489      // GIR_Coverage, 2621,
9490      GIR_Done,
9491    // Label 527: @22854
9492    GIM_Try, /*On fail goto*//*Label 528*/ 22888, // Rule ID 2622 //
9493      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9494      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9497      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9498      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9501      GIR_EraseFromParent, /*InsnID*/0,
9502      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9503      // GIR_Coverage, 2622,
9504      GIR_Done,
9505    // Label 528: @22888
9506    GIM_Try, /*On fail goto*//*Label 529*/ 22922, // Rule ID 2623 //
9507      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9508      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9510      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9511      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4f16] }:$src
9512      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9513      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9515      GIR_EraseFromParent, /*InsnID*/0,
9516      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9517      // GIR_Coverage, 2623,
9518      GIR_Done,
9519    // Label 529: @22922
9520    GIM_Try, /*On fail goto*//*Label 530*/ 22956, // Rule ID 2624 //
9521      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9525      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9526      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9527      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9528      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9529      GIR_EraseFromParent, /*InsnID*/0,
9530      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9531      // GIR_Coverage, 2624,
9532      GIR_Done,
9533    // Label 530: @22956
9534    GIM_Try, /*On fail goto*//*Label 531*/ 22990, // Rule ID 2625 //
9535      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9536      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9539      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9540      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9543      GIR_EraseFromParent, /*InsnID*/0,
9544      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9545      // GIR_Coverage, 2625,
9546      GIR_Done,
9547    // Label 531: @22990
9548    GIM_Try, /*On fail goto*//*Label 532*/ 23024, // Rule ID 2626 //
9549      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9550      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9553      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9554      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9555      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9556      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9557      GIR_EraseFromParent, /*InsnID*/0,
9558      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9559      // GIR_Coverage, 2626,
9560      GIR_Done,
9561    // Label 532: @23024
9562    GIM_Try, /*On fail goto*//*Label 533*/ 23058, // Rule ID 2627 //
9563      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9564      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9565      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9566      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9567      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9568      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9569      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9570      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9571      GIR_EraseFromParent, /*InsnID*/0,
9572      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9573      // GIR_Coverage, 2627,
9574      GIR_Done,
9575    // Label 533: @23058
9576    GIM_Try, /*On fail goto*//*Label 534*/ 23092, // Rule ID 2628 //
9577      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9578      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9579      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9580      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9581      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4i16] }:$src
9582      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9583      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9584      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9585      GIR_EraseFromParent, /*InsnID*/0,
9586      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
9587      // GIR_Coverage, 2628,
9588      GIR_Done,
9589    // Label 534: @23092
9590    GIM_Try, /*On fail goto*//*Label 535*/ 23131, // Rule ID 2691 //
9591      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9592      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9593      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9594      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9595      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
9596      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9597      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9598      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9599      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9600      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9601      GIR_EraseFromParent, /*InsnID*/0,
9602      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9603      // GIR_Coverage, 2691,
9604      GIR_Done,
9605    // Label 535: @23131
9606    GIM_Try, /*On fail goto*//*Label 536*/ 23170, // Rule ID 2692 //
9607      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9608      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9609      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9610      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9611      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
9612      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9613      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9614      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9615      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9616      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9617      GIR_EraseFromParent, /*InsnID*/0,
9618      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9619      // GIR_Coverage, 2692,
9620      GIR_Done,
9621    // Label 536: @23170
9622    GIM_Try, /*On fail goto*//*Label 537*/ 23209, // Rule ID 2693 //
9623      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9624      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9625      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9627      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
9628      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9629      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9630      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9631      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9632      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9633      GIR_EraseFromParent, /*InsnID*/0,
9634      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9635      // GIR_Coverage, 2693,
9636      GIR_Done,
9637    // Label 537: @23209
9638    GIM_Try, /*On fail goto*//*Label 538*/ 23248, // Rule ID 2694 //
9639      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9640      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9641      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9642      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9643      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
9644      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9645      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9646      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9647      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9648      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9649      GIR_EraseFromParent, /*InsnID*/0,
9650      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9651      // GIR_Coverage, 2694,
9652      GIR_Done,
9653    // Label 538: @23248
9654    GIM_Try, /*On fail goto*//*Label 539*/ 23287, // Rule ID 2695 //
9655      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9657      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9659      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
9660      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
9661      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9662      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9663      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9664      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9665      GIR_EraseFromParent, /*InsnID*/0,
9666      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9667      // GIR_Coverage, 2695,
9668      GIR_Done,
9669    // Label 539: @23287
9670    GIM_Try, /*On fail goto*//*Label 540*/ 23326, // Rule ID 2696 //
9671      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9672      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9675      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
9676      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9677      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9678      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9679      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9680      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9681      GIR_EraseFromParent, /*InsnID*/0,
9682      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9683      // GIR_Coverage, 2696,
9684      GIR_Done,
9685    // Label 540: @23326
9686    GIM_Try, /*On fail goto*//*Label 541*/ 23365, // Rule ID 2697 //
9687      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9688      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9689      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9690      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9691      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
9692      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9693      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9694      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9695      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9696      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9697      GIR_EraseFromParent, /*InsnID*/0,
9698      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9699      // GIR_Coverage, 2697,
9700      GIR_Done,
9701    // Label 541: @23365
9702    GIM_Try, /*On fail goto*//*Label 542*/ 23404, // Rule ID 2698 //
9703      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9704      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9705      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9706      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9707      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
9708      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9709      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9710      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9711      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9712      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9713      GIR_EraseFromParent, /*InsnID*/0,
9714      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9715      // GIR_Coverage, 2698,
9716      GIR_Done,
9717    // Label 542: @23404
9718    GIM_Try, /*On fail goto*//*Label 543*/ 23443, // Rule ID 2699 //
9719      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9720      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9722      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9723      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
9724      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9725      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9726      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9727      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9728      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9729      GIR_EraseFromParent, /*InsnID*/0,
9730      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9731      // GIR_Coverage, 2699,
9732      GIR_Done,
9733    // Label 543: @23443
9734    GIM_Try, /*On fail goto*//*Label 544*/ 23482, // Rule ID 2700 //
9735      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9736      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9737      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9738      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9739      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
9740      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
9741      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9742      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9743      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9744      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9745      GIR_EraseFromParent, /*InsnID*/0,
9746      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9747      // GIR_Coverage, 2700,
9748      GIR_Done,
9749    // Label 544: @23482
9750    GIM_Reject,
9751    // Label 427: @23483
9752    GIM_Try, /*On fail goto*//*Label 545*/ 23517, // Rule ID 2595 //
9753      GIM_CheckFeatures, GIFBS_HasNEON,
9754      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9757      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9758      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9761      GIR_EraseFromParent, /*InsnID*/0,
9762      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9763      // GIR_Coverage, 2595,
9764      GIR_Done,
9765    // Label 545: @23517
9766    GIM_Try, /*On fail goto*//*Label 546*/ 23551, // Rule ID 2596 //
9767      GIM_CheckFeatures, GIFBS_HasNEON,
9768      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9769      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9771      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9772      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9773      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9774      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9775      GIR_EraseFromParent, /*InsnID*/0,
9776      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9777      // GIR_Coverage, 2596,
9778      GIR_Done,
9779    // Label 546: @23551
9780    GIM_Try, /*On fail goto*//*Label 547*/ 23585, // Rule ID 2645 //
9781      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9782      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9783      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9784      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9785      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9786      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9787      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9788      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9789      GIR_EraseFromParent, /*InsnID*/0,
9790      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9791      // GIR_Coverage, 2645,
9792      GIR_Done,
9793    // Label 547: @23585
9794    GIM_Try, /*On fail goto*//*Label 548*/ 23619, // Rule ID 2646 //
9795      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9797      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9799      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9803      GIR_EraseFromParent, /*InsnID*/0,
9804      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9805      // GIR_Coverage, 2646,
9806      GIR_Done,
9807    // Label 548: @23619
9808    GIM_Try, /*On fail goto*//*Label 549*/ 23653, // Rule ID 2647 //
9809      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9810      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9811      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9812      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9813      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9814      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9815      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9816      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9817      GIR_EraseFromParent, /*InsnID*/0,
9818      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9819      // GIR_Coverage, 2647,
9820      GIR_Done,
9821    // Label 549: @23653
9822    GIM_Try, /*On fail goto*//*Label 550*/ 23687, // Rule ID 2648 //
9823      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9824      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9825      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9826      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9827      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9828      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9829      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9830      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9831      GIR_EraseFromParent, /*InsnID*/0,
9832      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9833      // GIR_Coverage, 2648,
9834      GIR_Done,
9835    // Label 550: @23687
9836    GIM_Try, /*On fail goto*//*Label 551*/ 23721, // Rule ID 2649 //
9837      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9838      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9840      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9841      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4f32] }:$src
9842      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9845      GIR_EraseFromParent, /*InsnID*/0,
9846      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9847      // GIR_Coverage, 2649,
9848      GIR_Done,
9849    // Label 551: @23721
9850    GIM_Try, /*On fail goto*//*Label 552*/ 23755, // Rule ID 2650 //
9851      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9852      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9854      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9855      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9856      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9858      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9859      GIR_EraseFromParent, /*InsnID*/0,
9860      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9861      // GIR_Coverage, 2650,
9862      GIR_Done,
9863    // Label 552: @23755
9864    GIM_Try, /*On fail goto*//*Label 553*/ 23789, // Rule ID 2651 //
9865      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9866      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9869      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9870      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9873      GIR_EraseFromParent, /*InsnID*/0,
9874      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9875      // GIR_Coverage, 2651,
9876      GIR_Done,
9877    // Label 553: @23789
9878    GIM_Try, /*On fail goto*//*Label 554*/ 23823, // Rule ID 2652 //
9879      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9880      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9883      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9884      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9885      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9886      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9887      GIR_EraseFromParent, /*InsnID*/0,
9888      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9889      // GIR_Coverage, 2652,
9890      GIR_Done,
9891    // Label 554: @23823
9892    GIM_Try, /*On fail goto*//*Label 555*/ 23857, // Rule ID 2653 //
9893      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9894      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9897      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9898      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9899      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9900      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9901      GIR_EraseFromParent, /*InsnID*/0,
9902      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9903      // GIR_Coverage, 2653,
9904      GIR_Done,
9905    // Label 555: @23857
9906    GIM_Try, /*On fail goto*//*Label 556*/ 23891, // Rule ID 2654 //
9907      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9908      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9909      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9910      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9911      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4i32] }:$src
9912      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9913      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9914      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9915      GIR_EraseFromParent, /*InsnID*/0,
9916      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
9917      // GIR_Coverage, 2654,
9918      GIR_Done,
9919    // Label 556: @23891
9920    GIM_Try, /*On fail goto*//*Label 557*/ 23930, // Rule ID 2717 //
9921      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9922      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9923      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9925      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
9926      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9927      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9928      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9929      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9930      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9931      GIR_EraseFromParent, /*InsnID*/0,
9932      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9933      // GIR_Coverage, 2717,
9934      GIR_Done,
9935    // Label 557: @23930
9936    GIM_Try, /*On fail goto*//*Label 558*/ 23969, // Rule ID 2718 //
9937      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9938      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9939      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9940      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9941      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
9942      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9943      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9944      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9945      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9946      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9947      GIR_EraseFromParent, /*InsnID*/0,
9948      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9949      // GIR_Coverage, 2718,
9950      GIR_Done,
9951    // Label 558: @23969
9952    GIM_Try, /*On fail goto*//*Label 559*/ 24008, // Rule ID 2719 //
9953      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9954      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9955      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9956      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9957      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
9958      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
9959      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9960      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9961      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9962      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9963      GIR_EraseFromParent, /*InsnID*/0,
9964      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9965      // GIR_Coverage, 2719,
9966      GIR_Done,
9967    // Label 559: @24008
9968    GIM_Try, /*On fail goto*//*Label 560*/ 24047, // Rule ID 2720 //
9969      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9970      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9971      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9972      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9973      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
9974      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
9975      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9976      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9977      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9978      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9979      GIR_EraseFromParent, /*InsnID*/0,
9980      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9981      // GIR_Coverage, 2720,
9982      GIR_Done,
9983    // Label 560: @24047
9984    GIM_Try, /*On fail goto*//*Label 561*/ 24086, // Rule ID 2721 //
9985      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9986      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9987      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9988      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9989      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
9990      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
9991      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9992      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9993      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9994      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
9995      GIR_EraseFromParent, /*InsnID*/0,
9996      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9997      // GIR_Coverage, 2721,
9998      GIR_Done,
9999    // Label 561: @24086
10000    GIM_Try, /*On fail goto*//*Label 562*/ 24125, // Rule ID 2722 //
10001      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10002      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10003      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10004      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10005      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
10006      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10007      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10008      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10009      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10010      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10011      GIR_EraseFromParent, /*InsnID*/0,
10012      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10013      // GIR_Coverage, 2722,
10014      GIR_Done,
10015    // Label 562: @24125
10016    GIM_Try, /*On fail goto*//*Label 563*/ 24164, // Rule ID 2723 //
10017      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10021      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
10022      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10025      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10026      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10027      GIR_EraseFromParent, /*InsnID*/0,
10028      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10029      // GIR_Coverage, 2723,
10030      GIR_Done,
10031    // Label 563: @24164
10032    GIM_Try, /*On fail goto*//*Label 564*/ 24203, // Rule ID 2724 //
10033      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10034      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10036      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10037      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
10038      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10039      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10040      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10041      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10042      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10043      GIR_EraseFromParent, /*InsnID*/0,
10044      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10045      // GIR_Coverage, 2724,
10046      GIR_Done,
10047    // Label 564: @24203
10048    GIM_Try, /*On fail goto*//*Label 565*/ 24242, // Rule ID 2725 //
10049      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10050      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10051      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10052      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10053      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
10054      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10055      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10056      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10057      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10058      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10059      GIR_EraseFromParent, /*InsnID*/0,
10060      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10061      // GIR_Coverage, 2725,
10062      GIR_Done,
10063    // Label 565: @24242
10064    GIM_Try, /*On fail goto*//*Label 566*/ 24281, // Rule ID 2726 //
10065      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10066      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10067      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10068      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10069      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
10070      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
10071      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10072      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10073      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10074      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10075      GIR_EraseFromParent, /*InsnID*/0,
10076      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10077      // GIR_Coverage, 2726,
10078      GIR_Done,
10079    // Label 566: @24281
10080    GIM_Try, /*On fail goto*//*Label 567*/ 24315, // Rule ID 4067 //
10081      GIM_CheckFeatures, GIFBS_HasMVEInt,
10082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10085      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10086      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10087      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10088      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10089      GIR_EraseFromParent, /*InsnID*/0,
10090      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10091      // GIR_Coverage, 4067,
10092      GIR_Done,
10093    // Label 567: @24315
10094    GIM_Try, /*On fail goto*//*Label 568*/ 24349, // Rule ID 4068 //
10095      GIM_CheckFeatures, GIFBS_HasMVEInt,
10096      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10097      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10098      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10099      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10100      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10101      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10102      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10103      GIR_EraseFromParent, /*InsnID*/0,
10104      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10105      // GIR_Coverage, 4068,
10106      GIR_Done,
10107    // Label 568: @24349
10108    GIM_Try, /*On fail goto*//*Label 569*/ 24383, // Rule ID 4081 //
10109      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10110      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10111      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10112      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10113      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10114      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10115      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10116      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10117      GIR_EraseFromParent, /*InsnID*/0,
10118      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10119      // GIR_Coverage, 4081,
10120      GIR_Done,
10121    // Label 569: @24383
10122    GIM_Try, /*On fail goto*//*Label 570*/ 24417, // Rule ID 4082 //
10123      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10124      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10126      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10127      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10128      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10129      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10130      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10131      GIR_EraseFromParent, /*InsnID*/0,
10132      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10133      // GIR_Coverage, 4082,
10134      GIR_Done,
10135    // Label 570: @24417
10136    GIM_Try, /*On fail goto*//*Label 571*/ 24451, // Rule ID 4083 //
10137      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10138      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10141      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10142      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10145      GIR_EraseFromParent, /*InsnID*/0,
10146      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10147      // GIR_Coverage, 4083,
10148      GIR_Done,
10149    // Label 571: @24451
10150    GIM_Try, /*On fail goto*//*Label 572*/ 24485, // Rule ID 4084 //
10151      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10152      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10153      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10155      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10156      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10157      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10159      GIR_EraseFromParent, /*InsnID*/0,
10160      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10161      // GIR_Coverage, 4084,
10162      GIR_Done,
10163    // Label 572: @24485
10164    GIM_Try, /*On fail goto*//*Label 573*/ 24519, // Rule ID 4085 //
10165      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10166      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10167      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10169      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
10170      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10171      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10172      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10173      GIR_EraseFromParent, /*InsnID*/0,
10174      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10175      // GIR_Coverage, 4085,
10176      GIR_Done,
10177    // Label 573: @24519
10178    GIM_Try, /*On fail goto*//*Label 574*/ 24553, // Rule ID 4086 //
10179      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10180      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10183      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10184      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10185      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10187      GIR_EraseFromParent, /*InsnID*/0,
10188      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10189      // GIR_Coverage, 4086,
10190      GIR_Done,
10191    // Label 574: @24553
10192    GIM_Try, /*On fail goto*//*Label 575*/ 24587, // Rule ID 4087 //
10193      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10194      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10196      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10197      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10198      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10199      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10200      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10201      GIR_EraseFromParent, /*InsnID*/0,
10202      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10203      // GIR_Coverage, 4087,
10204      GIR_Done,
10205    // Label 575: @24587
10206    GIM_Try, /*On fail goto*//*Label 576*/ 24621, // Rule ID 4088 //
10207      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10208      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10209      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10211      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10212      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10213      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10214      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10215      GIR_EraseFromParent, /*InsnID*/0,
10216      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10217      // GIR_Coverage, 4088,
10218      GIR_Done,
10219    // Label 576: @24621
10220    GIM_Try, /*On fail goto*//*Label 577*/ 24655, // Rule ID 4089 //
10221      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10222      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10224      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10225      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10226      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10227      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10228      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10229      GIR_EraseFromParent, /*InsnID*/0,
10230      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10231      // GIR_Coverage, 4089,
10232      GIR_Done,
10233    // Label 577: @24655
10234    GIM_Try, /*On fail goto*//*Label 578*/ 24689, // Rule ID 4090 //
10235      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10236      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10237      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10239      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
10240      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10241      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10242      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10243      GIR_EraseFromParent, /*InsnID*/0,
10244      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10245      // GIR_Coverage, 4090,
10246      GIR_Done,
10247    // Label 578: @24689
10248    GIM_Try, /*On fail goto*//*Label 579*/ 24742, // Rule ID 4117 //
10249      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10250      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10253      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
10254      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10255      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10256      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10257      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10258      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10260      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10261      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10262      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10263      GIR_EraseFromParent, /*InsnID*/0,
10264      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10265      // GIR_Coverage, 4117,
10266      GIR_Done,
10267    // Label 579: @24742
10268    GIM_Try, /*On fail goto*//*Label 580*/ 24795, // Rule ID 4118 //
10269      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10273      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
10274      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10275      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10276      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10277      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10278      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10280      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10281      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10282      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10283      GIR_EraseFromParent, /*InsnID*/0,
10284      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10285      // GIR_Coverage, 4118,
10286      GIR_Done,
10287    // Label 580: @24795
10288    GIM_Try, /*On fail goto*//*Label 581*/ 24848, // Rule ID 4119 //
10289      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10290      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10291      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10292      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10293      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
10294      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10295      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10296      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10297      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10299      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10300      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10301      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10302      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10303      GIR_EraseFromParent, /*InsnID*/0,
10304      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10305      // GIR_Coverage, 4119,
10306      GIR_Done,
10307    // Label 581: @24848
10308    GIM_Try, /*On fail goto*//*Label 582*/ 24901, // Rule ID 4120 //
10309      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10310      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10311      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10313      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
10314      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10315      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10316      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10317      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10318      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10319      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10320      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10321      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10322      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10323      GIR_EraseFromParent, /*InsnID*/0,
10324      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10325      // GIR_Coverage, 4120,
10326      GIR_Done,
10327    // Label 582: @24901
10328    GIM_Try, /*On fail goto*//*Label 583*/ 24954, // Rule ID 4121 //
10329      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10330      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10333      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
10334      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10335      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10336      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10337      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
10338      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10339      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10340      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10341      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10342      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10343      GIR_EraseFromParent, /*InsnID*/0,
10344      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10345      // GIR_Coverage, 4121,
10346      GIR_Done,
10347    // Label 583: @24954
10348    GIM_Try, /*On fail goto*//*Label 584*/ 25007, // Rule ID 4122 //
10349      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10350      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10351      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10353      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
10354      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10355      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10356      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10357      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10358      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10359      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10360      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10361      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10362      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10363      GIR_EraseFromParent, /*InsnID*/0,
10364      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10365      // GIR_Coverage, 4122,
10366      GIR_Done,
10367    // Label 584: @25007
10368    GIM_Try, /*On fail goto*//*Label 585*/ 25060, // Rule ID 4123 //
10369      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10370      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10371      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10373      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
10374      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10375      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10376      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10377      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10378      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10380      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10381      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10382      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10383      GIR_EraseFromParent, /*InsnID*/0,
10384      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10385      // GIR_Coverage, 4123,
10386      GIR_Done,
10387    // Label 585: @25060
10388    GIM_Try, /*On fail goto*//*Label 586*/ 25113, // Rule ID 4124 //
10389      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10390      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10391      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10393      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
10394      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10395      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10396      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10397      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10398      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10399      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10400      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10401      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10402      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10403      GIR_EraseFromParent, /*InsnID*/0,
10404      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10405      // GIR_Coverage, 4124,
10406      GIR_Done,
10407    // Label 586: @25113
10408    GIM_Try, /*On fail goto*//*Label 587*/ 25166, // Rule ID 4125 //
10409      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10410      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10411      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10412      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10413      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
10414      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10415      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10416      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10417      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10418      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10420      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10421      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10422      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10423      GIR_EraseFromParent, /*InsnID*/0,
10424      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10425      // GIR_Coverage, 4125,
10426      GIR_Done,
10427    // Label 587: @25166
10428    GIM_Try, /*On fail goto*//*Label 588*/ 25219, // Rule ID 4126 //
10429      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10430      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10432      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10433      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
10434      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10435      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10436      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10437      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
10438      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10439      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10440      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10441      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10442      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10443      GIR_EraseFromParent, /*InsnID*/0,
10444      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10445      // GIR_Coverage, 4126,
10446      GIR_Done,
10447    // Label 588: @25219
10448    GIM_Reject,
10449    // Label 428: @25220
10450    GIM_Try, /*On fail goto*//*Label 589*/ 25254, // Rule ID 2629 //
10451      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10455      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10459      GIR_EraseFromParent, /*InsnID*/0,
10460      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10461      // GIR_Coverage, 2629,
10462      GIR_Done,
10463    // Label 589: @25254
10464    GIM_Try, /*On fail goto*//*Label 590*/ 25288, // Rule ID 2630 //
10465      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10466      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10469      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10470      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10471      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10472      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10473      GIR_EraseFromParent, /*InsnID*/0,
10474      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10475      // GIR_Coverage, 2630,
10476      GIR_Done,
10477    // Label 590: @25288
10478    GIM_Try, /*On fail goto*//*Label 591*/ 25322, // Rule ID 2631 //
10479      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10483      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10487      GIR_EraseFromParent, /*InsnID*/0,
10488      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10489      // GIR_Coverage, 2631,
10490      GIR_Done,
10491    // Label 591: @25322
10492    GIM_Try, /*On fail goto*//*Label 592*/ 25356, // Rule ID 2632 //
10493      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10494      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10497      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10498      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10501      GIR_EraseFromParent, /*InsnID*/0,
10502      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10503      // GIR_Coverage, 2632,
10504      GIR_Done,
10505    // Label 592: @25356
10506    GIM_Try, /*On fail goto*//*Label 593*/ 25390, // Rule ID 2633 //
10507      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10508      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10510      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10511      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10512      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10513      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10515      GIR_EraseFromParent, /*InsnID*/0,
10516      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10517      // GIR_Coverage, 2633,
10518      GIR_Done,
10519    // Label 593: @25390
10520    GIM_Try, /*On fail goto*//*Label 594*/ 25424, // Rule ID 2634 //
10521      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10525      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
10526      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10527      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10528      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10529      GIR_EraseFromParent, /*InsnID*/0,
10530      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36,
10531      // GIR_Coverage, 2634,
10532      GIR_Done,
10533    // Label 594: @25424
10534    GIM_Try, /*On fail goto*//*Label 595*/ 25463, // Rule ID 2701 //
10535      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10536      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10539      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
10540      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
10541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10543      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10544      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10545      GIR_EraseFromParent, /*InsnID*/0,
10546      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10547      // GIR_Coverage, 2701,
10548      GIR_Done,
10549    // Label 595: @25463
10550    GIM_Try, /*On fail goto*//*Label 596*/ 25502, // Rule ID 2702 //
10551      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10552      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10553      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10554      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10555      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
10556      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
10557      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10558      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10559      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10560      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10561      GIR_EraseFromParent, /*InsnID*/0,
10562      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10563      // GIR_Coverage, 2702,
10564      GIR_Done,
10565    // Label 596: @25502
10566    GIM_Try, /*On fail goto*//*Label 597*/ 25541, // Rule ID 2703 //
10567      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10568      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10569      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10571      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
10572      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10573      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10575      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10576      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10577      GIR_EraseFromParent, /*InsnID*/0,
10578      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10579      // GIR_Coverage, 2703,
10580      GIR_Done,
10581    // Label 597: @25541
10582    GIM_Try, /*On fail goto*//*Label 598*/ 25580, // Rule ID 2704 //
10583      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10584      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10585      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10586      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10587      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
10588      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10590      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10591      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10592      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10593      GIR_EraseFromParent, /*InsnID*/0,
10594      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10595      // GIR_Coverage, 2704,
10596      GIR_Done,
10597    // Label 598: @25580
10598    GIM_Try, /*On fail goto*//*Label 599*/ 25619, // Rule ID 2705 //
10599      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10600      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10601      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10602      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10603      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
10604      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10605      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10606      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10607      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10608      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10609      GIR_EraseFromParent, /*InsnID*/0,
10610      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10611      // GIR_Coverage, 2705,
10612      GIR_Done,
10613    // Label 599: @25619
10614    GIM_Try, /*On fail goto*//*Label 600*/ 25658, // Rule ID 2706 //
10615      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10616      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10617      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10619      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
10620      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10621      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10622      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10623      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10624      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10625      GIR_EraseFromParent, /*InsnID*/0,
10626      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10627      // GIR_Coverage, 2706,
10628      GIR_Done,
10629    // Label 600: @25658
10630    GIM_Reject,
10631    // Label 429: @25659
10632    GIM_Try, /*On fail goto*//*Label 601*/ 25693, // Rule ID 2597 //
10633      GIM_CheckFeatures, GIFBS_HasNEON,
10634      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10635      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10636      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10637      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10638      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10640      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10641      GIR_EraseFromParent, /*InsnID*/0,
10642      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10643      // GIR_Coverage, 2597,
10644      GIR_Done,
10645    // Label 601: @25693
10646    GIM_Try, /*On fail goto*//*Label 602*/ 25727, // Rule ID 2598 //
10647      GIM_CheckFeatures, GIFBS_HasNEON,
10648      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10649      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10650      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10651      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10652      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10653      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10654      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10655      GIR_EraseFromParent, /*InsnID*/0,
10656      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10657      // GIR_Coverage, 2598,
10658      GIR_Done,
10659    // Label 602: @25727
10660    GIM_Try, /*On fail goto*//*Label 603*/ 25761, // Rule ID 2655 //
10661      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10662      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10663      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10664      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10665      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10666      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10667      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10668      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10669      GIR_EraseFromParent, /*InsnID*/0,
10670      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10671      // GIR_Coverage, 2655,
10672      GIR_Done,
10673    // Label 603: @25761
10674    GIM_Try, /*On fail goto*//*Label 604*/ 25795, // Rule ID 2656 //
10675      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10676      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10677      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10678      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10679      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10680      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10682      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10683      GIR_EraseFromParent, /*InsnID*/0,
10684      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10685      // GIR_Coverage, 2656,
10686      GIR_Done,
10687    // Label 604: @25795
10688    GIM_Try, /*On fail goto*//*Label 605*/ 25829, // Rule ID 2657 //
10689      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10690      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10691      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10692      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10693      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10694      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10695      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10696      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10697      GIR_EraseFromParent, /*InsnID*/0,
10698      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10699      // GIR_Coverage, 2657,
10700      GIR_Done,
10701    // Label 605: @25829
10702    GIM_Try, /*On fail goto*//*Label 606*/ 25863, // Rule ID 2658 //
10703      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10704      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10705      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10706      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10707      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10708      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10709      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10710      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10711      GIR_EraseFromParent, /*InsnID*/0,
10712      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10713      // GIR_Coverage, 2658,
10714      GIR_Done,
10715    // Label 606: @25863
10716    GIM_Try, /*On fail goto*//*Label 607*/ 25897, // Rule ID 2659 //
10717      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10718      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10719      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10720      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10721      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8f16] }:$src
10722      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10723      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10724      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10725      GIR_EraseFromParent, /*InsnID*/0,
10726      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10727      // GIR_Coverage, 2659,
10728      GIR_Done,
10729    // Label 607: @25897
10730    GIM_Try, /*On fail goto*//*Label 608*/ 25931, // Rule ID 2660 //
10731      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10732      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10733      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10734      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10735      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10736      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10737      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10739      GIR_EraseFromParent, /*InsnID*/0,
10740      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10741      // GIR_Coverage, 2660,
10742      GIR_Done,
10743    // Label 608: @25931
10744    GIM_Try, /*On fail goto*//*Label 609*/ 25965, // Rule ID 2661 //
10745      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10746      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10747      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10748      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10749      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10750      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10751      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10752      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10753      GIR_EraseFromParent, /*InsnID*/0,
10754      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10755      // GIR_Coverage, 2661,
10756      GIR_Done,
10757    // Label 609: @25965
10758    GIM_Try, /*On fail goto*//*Label 610*/ 25999, // Rule ID 2662 //
10759      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10760      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10762      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10763      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10764      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10765      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10766      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10767      GIR_EraseFromParent, /*InsnID*/0,
10768      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10769      // GIR_Coverage, 2662,
10770      GIR_Done,
10771    // Label 610: @25999
10772    GIM_Try, /*On fail goto*//*Label 611*/ 26033, // Rule ID 2663 //
10773      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10774      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10775      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10776      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10777      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10778      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10779      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10780      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10781      GIR_EraseFromParent, /*InsnID*/0,
10782      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10783      // GIR_Coverage, 2663,
10784      GIR_Done,
10785    // Label 611: @26033
10786    GIM_Try, /*On fail goto*//*Label 612*/ 26067, // Rule ID 2664 //
10787      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10788      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10790      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10791      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8i16] }:$src
10792      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10793      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10794      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10795      GIR_EraseFromParent, /*InsnID*/0,
10796      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
10797      // GIR_Coverage, 2664,
10798      GIR_Done,
10799    // Label 612: @26067
10800    GIM_Try, /*On fail goto*//*Label 613*/ 26106, // Rule ID 2727 //
10801      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10802      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10803      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10805      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
10806      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10807      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10808      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10809      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10810      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10811      GIR_EraseFromParent, /*InsnID*/0,
10812      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10813      // GIR_Coverage, 2727,
10814      GIR_Done,
10815    // Label 613: @26106
10816    GIM_Try, /*On fail goto*//*Label 614*/ 26145, // Rule ID 2728 //
10817      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10818      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10820      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10821      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
10822      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10823      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10824      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10825      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10826      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10827      GIR_EraseFromParent, /*InsnID*/0,
10828      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10829      // GIR_Coverage, 2728,
10830      GIR_Done,
10831    // Label 614: @26145
10832    GIM_Try, /*On fail goto*//*Label 615*/ 26184, // Rule ID 2729 //
10833      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10834      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10835      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10837      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
10838      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10839      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10841      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10842      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10843      GIR_EraseFromParent, /*InsnID*/0,
10844      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10845      // GIR_Coverage, 2729,
10846      GIR_Done,
10847    // Label 615: @26184
10848    GIM_Try, /*On fail goto*//*Label 616*/ 26223, // Rule ID 2730 //
10849      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10850      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10851      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10852      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10853      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
10854      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10855      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10856      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10857      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10858      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10859      GIR_EraseFromParent, /*InsnID*/0,
10860      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10861      // GIR_Coverage, 2730,
10862      GIR_Done,
10863    // Label 616: @26223
10864    GIM_Try, /*On fail goto*//*Label 617*/ 26262, // Rule ID 2731 //
10865      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10866      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10869      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
10870      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
10871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10873      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10874      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10875      GIR_EraseFromParent, /*InsnID*/0,
10876      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10877      // GIR_Coverage, 2731,
10878      GIR_Done,
10879    // Label 617: @26262
10880    GIM_Try, /*On fail goto*//*Label 618*/ 26301, // Rule ID 2732 //
10881      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10882      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10883      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10884      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10885      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
10886      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10887      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10888      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10889      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10890      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10891      GIR_EraseFromParent, /*InsnID*/0,
10892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10893      // GIR_Coverage, 2732,
10894      GIR_Done,
10895    // Label 618: @26301
10896    GIM_Try, /*On fail goto*//*Label 619*/ 26340, // Rule ID 2733 //
10897      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10899      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10901      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
10902      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10904      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10905      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10906      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10907      GIR_EraseFromParent, /*InsnID*/0,
10908      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10909      // GIR_Coverage, 2733,
10910      GIR_Done,
10911    // Label 619: @26340
10912    GIM_Try, /*On fail goto*//*Label 620*/ 26379, // Rule ID 2734 //
10913      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10914      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10915      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10917      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
10918      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10919      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10920      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10921      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10922      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10923      GIR_EraseFromParent, /*InsnID*/0,
10924      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10925      // GIR_Coverage, 2734,
10926      GIR_Done,
10927    // Label 620: @26379
10928    GIM_Try, /*On fail goto*//*Label 621*/ 26418, // Rule ID 2735 //
10929      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10930      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10932      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10933      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
10934      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10935      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10936      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10937      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10938      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10939      GIR_EraseFromParent, /*InsnID*/0,
10940      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10941      // GIR_Coverage, 2735,
10942      GIR_Done,
10943    // Label 621: @26418
10944    GIM_Try, /*On fail goto*//*Label 622*/ 26457, // Rule ID 2736 //
10945      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10946      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10948      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10949      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
10950      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
10951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10952      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10953      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10954      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
10955      GIR_EraseFromParent, /*InsnID*/0,
10956      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10957      // GIR_Coverage, 2736,
10958      GIR_Done,
10959    // Label 622: @26457
10960    GIM_Try, /*On fail goto*//*Label 623*/ 26491, // Rule ID 4069 //
10961      GIM_CheckFeatures, GIFBS_HasMVEInt,
10962      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10963      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10965      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
10966      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10967      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10968      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10969      GIR_EraseFromParent, /*InsnID*/0,
10970      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10971      // GIR_Coverage, 4069,
10972      GIR_Done,
10973    // Label 623: @26491
10974    GIM_Try, /*On fail goto*//*Label 624*/ 26525, // Rule ID 4070 //
10975      GIM_CheckFeatures, GIFBS_HasMVEInt,
10976      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10978      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10979      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
10980      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10983      GIR_EraseFromParent, /*InsnID*/0,
10984      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10985      // GIR_Coverage, 4070,
10986      GIR_Done,
10987    // Label 624: @26525
10988    GIM_Try, /*On fail goto*//*Label 625*/ 26559, // Rule ID 4091 //
10989      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10990      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10993      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
10994      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10995      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10996      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10997      GIR_EraseFromParent, /*InsnID*/0,
10998      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
10999      // GIR_Coverage, 4091,
11000      GIR_Done,
11001    // Label 625: @26559
11002    GIM_Try, /*On fail goto*//*Label 626*/ 26593, // Rule ID 4092 //
11003      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11004      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11005      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11006      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11007      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
11008      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11009      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11010      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11011      GIR_EraseFromParent, /*InsnID*/0,
11012      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11013      // GIR_Coverage, 4092,
11014      GIR_Done,
11015    // Label 626: @26593
11016    GIM_Try, /*On fail goto*//*Label 627*/ 26627, // Rule ID 4093 //
11017      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11021      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
11022      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11025      GIR_EraseFromParent, /*InsnID*/0,
11026      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11027      // GIR_Coverage, 4093,
11028      GIR_Done,
11029    // Label 627: @26627
11030    GIM_Try, /*On fail goto*//*Label 628*/ 26661, // Rule ID 4094 //
11031      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11032      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11033      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11034      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11035      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
11036      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11037      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11038      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11039      GIR_EraseFromParent, /*InsnID*/0,
11040      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11041      // GIR_Coverage, 4094,
11042      GIR_Done,
11043    // Label 628: @26661
11044    GIM_Try, /*On fail goto*//*Label 629*/ 26695, // Rule ID 4095 //
11045      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11046      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11047      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11048      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11049      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
11050      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11051      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11052      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11053      GIR_EraseFromParent, /*InsnID*/0,
11054      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11055      // GIR_Coverage, 4095,
11056      GIR_Done,
11057    // Label 629: @26695
11058    GIM_Try, /*On fail goto*//*Label 630*/ 26729, // Rule ID 4096 //
11059      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11060      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11061      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11062      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11063      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
11064      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11065      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11066      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11067      GIR_EraseFromParent, /*InsnID*/0,
11068      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11069      // GIR_Coverage, 4096,
11070      GIR_Done,
11071    // Label 630: @26729
11072    GIM_Try, /*On fail goto*//*Label 631*/ 26763, // Rule ID 4097 //
11073      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11074      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11077      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
11078      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11079      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11080      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11081      GIR_EraseFromParent, /*InsnID*/0,
11082      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11083      // GIR_Coverage, 4097,
11084      GIR_Done,
11085    // Label 631: @26763
11086    GIM_Try, /*On fail goto*//*Label 632*/ 26797, // Rule ID 4098 //
11087      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11088      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11090      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11091      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
11092      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11093      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11094      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11095      GIR_EraseFromParent, /*InsnID*/0,
11096      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11097      // GIR_Coverage, 4098,
11098      GIR_Done,
11099    // Label 632: @26797
11100    GIM_Try, /*On fail goto*//*Label 633*/ 26831, // Rule ID 4099 //
11101      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11102      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11104      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11105      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
11106      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11107      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11108      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11109      GIR_EraseFromParent, /*InsnID*/0,
11110      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11111      // GIR_Coverage, 4099,
11112      GIR_Done,
11113    // Label 633: @26831
11114    GIM_Try, /*On fail goto*//*Label 634*/ 26865, // Rule ID 4100 //
11115      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11116      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11117      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11119      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
11120      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11121      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11122      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11123      GIR_EraseFromParent, /*InsnID*/0,
11124      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11125      // GIR_Coverage, 4100,
11126      GIR_Done,
11127    // Label 634: @26865
11128    GIM_Try, /*On fail goto*//*Label 635*/ 26918, // Rule ID 4127 //
11129      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11130      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11131      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11133      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
11134      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11135      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11136      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11137      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11138      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11139      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11140      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11141      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11142      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11143      GIR_EraseFromParent, /*InsnID*/0,
11144      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11145      // GIR_Coverage, 4127,
11146      GIR_Done,
11147    // Label 635: @26918
11148    GIM_Try, /*On fail goto*//*Label 636*/ 26971, // Rule ID 4128 //
11149      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11150      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11153      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
11154      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11155      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11156      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11157      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11159      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11160      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11161      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11162      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11163      GIR_EraseFromParent, /*InsnID*/0,
11164      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11165      // GIR_Coverage, 4128,
11166      GIR_Done,
11167    // Label 636: @26971
11168    GIM_Try, /*On fail goto*//*Label 637*/ 27024, // Rule ID 4129 //
11169      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11170      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11171      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11172      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11173      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
11174      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11175      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11176      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11177      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11178      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11179      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11180      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11181      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11182      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11183      GIR_EraseFromParent, /*InsnID*/0,
11184      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11185      // GIR_Coverage, 4129,
11186      GIR_Done,
11187    // Label 637: @27024
11188    GIM_Try, /*On fail goto*//*Label 638*/ 27077, // Rule ID 4130 //
11189      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11190      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11191      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11192      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11193      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
11194      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11195      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11196      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11197      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11198      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11199      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11200      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11201      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11202      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11203      GIR_EraseFromParent, /*InsnID*/0,
11204      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11205      // GIR_Coverage, 4130,
11206      GIR_Done,
11207    // Label 638: @27077
11208    GIM_Try, /*On fail goto*//*Label 639*/ 27130, // Rule ID 4131 //
11209      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11210      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11211      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11212      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11213      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
11214      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11215      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11216      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11217      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11218      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11219      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11220      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11221      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11222      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11223      GIR_EraseFromParent, /*InsnID*/0,
11224      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11225      // GIR_Coverage, 4131,
11226      GIR_Done,
11227    // Label 639: @27130
11228    GIM_Try, /*On fail goto*//*Label 640*/ 27183, // Rule ID 4132 //
11229      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11231      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11233      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
11234      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11235      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11236      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11237      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11238      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11239      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11240      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11241      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11242      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11243      GIR_EraseFromParent, /*InsnID*/0,
11244      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11245      // GIR_Coverage, 4132,
11246      GIR_Done,
11247    // Label 640: @27183
11248    GIM_Try, /*On fail goto*//*Label 641*/ 27236, // Rule ID 4133 //
11249      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11250      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11253      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
11254      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11255      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11256      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11257      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11258      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11260      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11261      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11262      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11263      GIR_EraseFromParent, /*InsnID*/0,
11264      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11265      // GIR_Coverage, 4133,
11266      GIR_Done,
11267    // Label 641: @27236
11268    GIM_Try, /*On fail goto*//*Label 642*/ 27289, // Rule ID 4134 //
11269      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11273      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
11274      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11275      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11276      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11277      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11278      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11280      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11281      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11282      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11283      GIR_EraseFromParent, /*InsnID*/0,
11284      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11285      // GIR_Coverage, 4134,
11286      GIR_Done,
11287    // Label 642: @27289
11288    GIM_Try, /*On fail goto*//*Label 643*/ 27342, // Rule ID 4135 //
11289      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11290      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11291      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11292      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11293      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
11294      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11295      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11296      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11297      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11299      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11300      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11301      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11302      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11303      GIR_EraseFromParent, /*InsnID*/0,
11304      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11305      // GIR_Coverage, 4135,
11306      GIR_Done,
11307    // Label 643: @27342
11308    GIM_Try, /*On fail goto*//*Label 644*/ 27395, // Rule ID 4136 //
11309      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11310      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11311      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11313      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
11314      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11315      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11316      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11317      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11318      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11319      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11320      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11321      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11322      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11323      GIR_EraseFromParent, /*InsnID*/0,
11324      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11325      // GIR_Coverage, 4136,
11326      GIR_Done,
11327    // Label 644: @27395
11328    GIM_Reject,
11329    // Label 430: @27396
11330    GIM_Try, /*On fail goto*//*Label 645*/ 27430, // Rule ID 2665 //
11331      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11332      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11334      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11335      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11336      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11337      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11338      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11339      GIR_EraseFromParent, /*InsnID*/0,
11340      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11341      // GIR_Coverage, 2665,
11342      GIR_Done,
11343    // Label 645: @27430
11344    GIM_Try, /*On fail goto*//*Label 646*/ 27464, // Rule ID 2666 //
11345      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11346      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11349      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11350      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11351      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11353      GIR_EraseFromParent, /*InsnID*/0,
11354      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11355      // GIR_Coverage, 2666,
11356      GIR_Done,
11357    // Label 646: @27464
11358    GIM_Try, /*On fail goto*//*Label 647*/ 27498, // Rule ID 2667 //
11359      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11360      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11362      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11363      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11364      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11365      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11366      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11367      GIR_EraseFromParent, /*InsnID*/0,
11368      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11369      // GIR_Coverage, 2667,
11370      GIR_Done,
11371    // Label 647: @27498
11372    GIM_Try, /*On fail goto*//*Label 648*/ 27532, // Rule ID 2668 //
11373      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11377      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11378      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11381      GIR_EraseFromParent, /*InsnID*/0,
11382      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11383      // GIR_Coverage, 2668,
11384      GIR_Done,
11385    // Label 648: @27532
11386    GIM_Try, /*On fail goto*//*Label 649*/ 27566, // Rule ID 2669 //
11387      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11388      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11389      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11390      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11391      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11392      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11394      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11395      GIR_EraseFromParent, /*InsnID*/0,
11396      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11397      // GIR_Coverage, 2669,
11398      GIR_Done,
11399    // Label 649: @27566
11400    GIM_Try, /*On fail goto*//*Label 650*/ 27600, // Rule ID 2670 //
11401      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11402      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11404      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11405      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
11406      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11407      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11408      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11409      GIR_EraseFromParent, /*InsnID*/0,
11410      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54,
11411      // GIR_Coverage, 2670,
11412      GIR_Done,
11413    // Label 650: @27600
11414    GIM_Try, /*On fail goto*//*Label 651*/ 27639, // Rule ID 2737 //
11415      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11416      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11419      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
11420      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
11421      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11422      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11423      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11424      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11425      GIR_EraseFromParent, /*InsnID*/0,
11426      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11427      // GIR_Coverage, 2737,
11428      GIR_Done,
11429    // Label 651: @27639
11430    GIM_Try, /*On fail goto*//*Label 652*/ 27678, // Rule ID 2738 //
11431      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11432      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11434      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11435      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
11436      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
11437      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11438      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11439      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11440      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11441      GIR_EraseFromParent, /*InsnID*/0,
11442      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11443      // GIR_Coverage, 2738,
11444      GIR_Done,
11445    // Label 652: @27678
11446    GIM_Try, /*On fail goto*//*Label 653*/ 27717, // Rule ID 2739 //
11447      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11448      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11449      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11450      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11451      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
11452      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11453      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11454      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11455      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11456      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11457      GIR_EraseFromParent, /*InsnID*/0,
11458      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11459      // GIR_Coverage, 2739,
11460      GIR_Done,
11461    // Label 653: @27717
11462    GIM_Try, /*On fail goto*//*Label 654*/ 27756, // Rule ID 2740 //
11463      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11464      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11466      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11467      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
11468      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11469      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11470      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11471      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11472      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11473      GIR_EraseFromParent, /*InsnID*/0,
11474      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11475      // GIR_Coverage, 2740,
11476      GIR_Done,
11477    // Label 654: @27756
11478    GIM_Try, /*On fail goto*//*Label 655*/ 27795, // Rule ID 2741 //
11479      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11483      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
11484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
11485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11487      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11488      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11489      GIR_EraseFromParent, /*InsnID*/0,
11490      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11491      // GIR_Coverage, 2741,
11492      GIR_Done,
11493    // Label 655: @27795
11494    GIM_Try, /*On fail goto*//*Label 656*/ 27834, // Rule ID 2742 //
11495      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11496      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11497      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11498      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11499      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
11500      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
11501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11502      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11503      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11504      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11505      GIR_EraseFromParent, /*InsnID*/0,
11506      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11507      // GIR_Coverage, 2742,
11508      GIR_Done,
11509    // Label 656: @27834
11510    GIM_Try, /*On fail goto*//*Label 657*/ 27868, // Rule ID 4101 //
11511      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11512      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11515      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11516      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11519      GIR_EraseFromParent, /*InsnID*/0,
11520      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11521      // GIR_Coverage, 4101,
11522      GIR_Done,
11523    // Label 657: @27868
11524    GIM_Try, /*On fail goto*//*Label 658*/ 27902, // Rule ID 4102 //
11525      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11529      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11533      GIR_EraseFromParent, /*InsnID*/0,
11534      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11535      // GIR_Coverage, 4102,
11536      GIR_Done,
11537    // Label 658: @27902
11538    GIM_Try, /*On fail goto*//*Label 659*/ 27936, // Rule ID 4103 //
11539      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11540      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11541      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11542      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11543      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11544      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11545      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11547      GIR_EraseFromParent, /*InsnID*/0,
11548      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11549      // GIR_Coverage, 4103,
11550      GIR_Done,
11551    // Label 659: @27936
11552    GIM_Try, /*On fail goto*//*Label 660*/ 27970, // Rule ID 4104 //
11553      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11554      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11557      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11558      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11559      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11561      GIR_EraseFromParent, /*InsnID*/0,
11562      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11563      // GIR_Coverage, 4104,
11564      GIR_Done,
11565    // Label 660: @27970
11566    GIM_Try, /*On fail goto*//*Label 661*/ 28004, // Rule ID 4105 //
11567      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11568      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11569      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11571      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11572      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11573      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11575      GIR_EraseFromParent, /*InsnID*/0,
11576      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11577      // GIR_Coverage, 4105,
11578      GIR_Done,
11579    // Label 661: @28004
11580    GIM_Try, /*On fail goto*//*Label 662*/ 28038, // Rule ID 4106 //
11581      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11582      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11583      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11584      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11585      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
11586      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11587      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11589      GIR_EraseFromParent, /*InsnID*/0,
11590      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57,
11591      // GIR_Coverage, 4106,
11592      GIR_Done,
11593    // Label 662: @28038
11594    GIM_Try, /*On fail goto*//*Label 663*/ 28091, // Rule ID 4137 //
11595      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11596      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11597      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11599      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
11600      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11601      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11602      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11603      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
11604      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11605      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11606      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11607      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11608      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11609      GIR_EraseFromParent, /*InsnID*/0,
11610      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11611      // GIR_Coverage, 4137,
11612      GIR_Done,
11613    // Label 663: @28091
11614    GIM_Try, /*On fail goto*//*Label 664*/ 28144, // Rule ID 4138 //
11615      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11616      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11617      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11619      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
11620      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11621      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11622      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11623      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
11624      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11625      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11626      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11627      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11628      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11629      GIR_EraseFromParent, /*InsnID*/0,
11630      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11631      // GIR_Coverage, 4138,
11632      GIR_Done,
11633    // Label 664: @28144
11634    GIM_Try, /*On fail goto*//*Label 665*/ 28197, // Rule ID 4139 //
11635      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11636      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11637      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11638      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11639      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
11640      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11641      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11642      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11643      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11645      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11646      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11647      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11648      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11649      GIR_EraseFromParent, /*InsnID*/0,
11650      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11651      // GIR_Coverage, 4139,
11652      GIR_Done,
11653    // Label 665: @28197
11654    GIM_Try, /*On fail goto*//*Label 666*/ 28250, // Rule ID 4140 //
11655      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11657      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11659      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
11660      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11661      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11662      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11663      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11664      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11665      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11666      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11667      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11668      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11669      GIR_EraseFromParent, /*InsnID*/0,
11670      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11671      // GIR_Coverage, 4140,
11672      GIR_Done,
11673    // Label 666: @28250
11674    GIM_Try, /*On fail goto*//*Label 667*/ 28303, // Rule ID 4141 //
11675      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11676      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11677      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11678      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11679      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
11680      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11681      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11682      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11683      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11684      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11685      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11686      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11687      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11688      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11689      GIR_EraseFromParent, /*InsnID*/0,
11690      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11691      // GIR_Coverage, 4141,
11692      GIR_Done,
11693    // Label 667: @28303
11694    GIM_Try, /*On fail goto*//*Label 668*/ 28356, // Rule ID 4142 //
11695      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11696      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11699      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
11700      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11701      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11702      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11703      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11704      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11705      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11706      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11707      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11708      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11709      GIR_EraseFromParent, /*InsnID*/0,
11710      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11711      // GIR_Coverage, 4142,
11712      GIR_Done,
11713    // Label 668: @28356
11714    GIM_Reject,
11715    // Label 431: @28357
11716    GIM_Reject,
11717    // Label 10: @28358
11718    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 674*/ 28604,
11719    /*GILLT_s16*//*Label 669*/ 28376,
11720    /*GILLT_s32*//*Label 670*/ 28416,
11721    /*GILLT_s64*//*Label 671*/ 28456, 0, 0, 0, 0,
11722    /*GILLT_v4s32*//*Label 672*/ 28496, 0, 0, 0,
11723    /*GILLT_v8s16*//*Label 673*/ 28550,
11724    // Label 669: @28376
11725    GIM_Try, /*On fail goto*//*Label 675*/ 28415, // Rule ID 678 //
11726      GIM_CheckFeatures, GIFBS_HasFullFP16,
11727      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
11728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
11729      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
11730      // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
11731      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZH,
11732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
11733      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
11734      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11735      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11736      GIR_EraseFromParent, /*InsnID*/0,
11737      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11738      // GIR_Coverage, 678,
11739      GIR_Done,
11740    // Label 675: @28415
11741    GIM_Reject,
11742    // Label 670: @28416
11743    GIM_Try, /*On fail goto*//*Label 676*/ 28455, // Rule ID 679 //
11744      GIM_CheckFeatures, GIFBS_HasFPARMv8,
11745      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
11746      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
11747      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
11748      // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
11749      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZS,
11750      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
11751      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
11752      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11753      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11754      GIR_EraseFromParent, /*InsnID*/0,
11755      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11756      // GIR_Coverage, 679,
11757      GIR_Done,
11758    // Label 676: @28455
11759    GIM_Reject,
11760    // Label 671: @28456
11761    GIM_Try, /*On fail goto*//*Label 677*/ 28495, // Rule ID 680 //
11762      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
11763      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11766      // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
11767      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZD,
11768      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
11769      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
11770      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11771      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11772      GIR_EraseFromParent, /*InsnID*/0,
11773      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11774      // GIR_Coverage, 680,
11775      GIR_Done,
11776    // Label 677: @28495
11777    GIM_Reject,
11778    // Label 672: @28496
11779    GIM_Try, /*On fail goto*//*Label 678*/ 28549, // Rule ID 3366 //
11780      GIM_CheckFeatures, GIFBS_HasMVEFloat,
11781      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11782      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11783      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11784      // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)  =>  (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)
11785      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11786      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11787      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11788      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32Z,
11789      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11790      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
11791      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11792      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11793      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11794      GIR_EraseFromParent, /*InsnID*/0,
11795      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11796      // GIR_Coverage, 3366,
11797      GIR_Done,
11798    // Label 678: @28549
11799    GIM_Reject,
11800    // Label 673: @28550
11801    GIM_Try, /*On fail goto*//*Label 679*/ 28603, // Rule ID 3367 //
11802      GIM_CheckFeatures, GIFBS_HasMVEFloat,
11803      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11805      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11806      // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)  =>  (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)
11807      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11808      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11809      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11810      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16Z,
11811      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11812      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
11813      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11814      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11815      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11816      GIR_EraseFromParent, /*InsnID*/0,
11817      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11818      // GIR_Coverage, 3367,
11819      GIR_Done,
11820    // Label 679: @28603
11821    GIM_Reject,
11822    // Label 674: @28604
11823    GIM_Reject,
11824    // Label 11: @28605
11825    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 685*/ 28803,
11826    /*GILLT_s16*//*Label 680*/ 28623,
11827    /*GILLT_s32*//*Label 681*/ 28647,
11828    /*GILLT_s64*//*Label 682*/ 28671, 0, 0, 0, 0,
11829    /*GILLT_v4s32*//*Label 683*/ 28695, 0, 0, 0,
11830    /*GILLT_v8s16*//*Label 684*/ 28749,
11831    // Label 680: @28623
11832    GIM_Try, /*On fail goto*//*Label 686*/ 28646, // Rule ID 687 //
11833      GIM_CheckFeatures, GIFBS_HasFullFP16,
11834      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
11835      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
11836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
11837      // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
11838      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAH,
11839      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11840      // GIR_Coverage, 687,
11841      GIR_Done,
11842    // Label 686: @28646
11843    GIM_Reject,
11844    // Label 681: @28647
11845    GIM_Try, /*On fail goto*//*Label 687*/ 28670, // Rule ID 688 //
11846      GIM_CheckFeatures, GIFBS_HasFPARMv8,
11847      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
11848      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
11849      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
11850      // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
11851      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAS,
11852      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11853      // GIR_Coverage, 688,
11854      GIR_Done,
11855    // Label 687: @28670
11856    GIM_Reject,
11857    // Label 682: @28671
11858    GIM_Try, /*On fail goto*//*Label 688*/ 28694, // Rule ID 689 //
11859      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
11860      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11861      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11863      // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
11864      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAD,
11865      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11866      // GIR_Coverage, 689,
11867      GIR_Done,
11868    // Label 688: @28694
11869    GIM_Reject,
11870    // Label 683: @28695
11871    GIM_Try, /*On fail goto*//*Label 689*/ 28748, // Rule ID 3364 //
11872      GIM_CheckFeatures, GIFBS_HasMVEFloat,
11873      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11874      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11875      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11876      // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)  =>  (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)
11877      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11878      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11879      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11880      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32A,
11881      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11882      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
11883      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11884      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11885      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11886      GIR_EraseFromParent, /*InsnID*/0,
11887      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11888      // GIR_Coverage, 3364,
11889      GIR_Done,
11890    // Label 689: @28748
11891    GIM_Reject,
11892    // Label 684: @28749
11893    GIM_Try, /*On fail goto*//*Label 690*/ 28802, // Rule ID 3365 //
11894      GIM_CheckFeatures, GIFBS_HasMVEFloat,
11895      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11897      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11898      // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)  =>  (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)
11899      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11900      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11901      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11902      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16A,
11903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11904      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
11905      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11906      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11907      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11908      GIR_EraseFromParent, /*InsnID*/0,
11909      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11910      // GIR_Coverage, 3365,
11911      GIR_Done,
11912    // Label 690: @28802
11913    GIM_Reject,
11914    // Label 685: @28803
11915    GIM_Reject,
11916    // Label 12: @28804
11917    GIM_Try, /*On fail goto*//*Label 691*/ 34505,
11918      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
11919      GIM_Try, /*On fail goto*//*Label 692*/ 28859, // Rule ID 1869 //
11920        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
11921        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
11922        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11923        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
11926        // (intrinsic_wo_chain:{ *:[i32] } 1861:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
11927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
11928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
11930        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11931        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11932        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11933        GIR_EraseFromParent, /*InsnID*/0,
11934        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11935        // GIR_Coverage, 1869,
11936        GIR_Done,
11937      // Label 692: @28859
11938      GIM_Try, /*On fail goto*//*Label 693*/ 28909, // Rule ID 2092 //
11939        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
11940        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
11941        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11942        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11945        // (intrinsic_wo_chain:{ *:[i32] } 1861:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
11946        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
11947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
11949        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11950        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11951        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
11952        GIR_EraseFromParent, /*InsnID*/0,
11953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11954        // GIR_Coverage, 2092,
11955        GIR_Done,
11956      // Label 693: @28909
11957      GIM_Try, /*On fail goto*//*Label 694*/ 28949, // Rule ID 690 //
11958        GIM_CheckFeatures, GIFBS_HasFullFP16,
11959        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
11960        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
11961        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
11962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
11963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
11964        // (intrinsic_wo_chain:{ *:[f16] } 1747:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm)  =>  (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
11965        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNH,
11966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
11967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
11968        GIR_EraseFromParent, /*InsnID*/0,
11969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11970        // GIR_Coverage, 690,
11971        GIR_Done,
11972      // Label 694: @28949
11973      GIM_Try, /*On fail goto*//*Label 695*/ 28989, // Rule ID 691 //
11974        GIM_CheckFeatures, GIFBS_HasFPARMv8,
11975        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
11976        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11977        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
11979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
11980        // (intrinsic_wo_chain:{ *:[f32] } 1747:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
11981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS,
11982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
11983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
11984        GIR_EraseFromParent, /*InsnID*/0,
11985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11986        // GIR_Coverage, 691,
11987        GIR_Done,
11988      // Label 695: @28989
11989      GIM_Try, /*On fail goto*//*Label 696*/ 29029, // Rule ID 692 //
11990        GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
11991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
11992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
11993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
11994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11996        // (intrinsic_wo_chain:{ *:[f64] } 1747:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
11997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND,
11998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
11999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
12000        GIR_EraseFromParent, /*InsnID*/0,
12001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12002        // GIR_Coverage, 692,
12003        GIR_Done,
12004      // Label 696: @29029
12005      GIM_Try, /*On fail goto*//*Label 697*/ 29076, // Rule ID 708 //
12006        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
12007        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
12008        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12009        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
12010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
12011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12012        // (intrinsic_wo_chain:{ *:[f32] } 1862:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
12013        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD,
12014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
12015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
12016        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12017        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12018        GIR_EraseFromParent, /*InsnID*/0,
12019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12020        // GIR_Coverage, 708,
12021        GIR_Done,
12022      // Label 697: @29076
12023      GIM_Try, /*On fail goto*//*Label 698*/ 29123, // Rule ID 709 //
12024        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
12025        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
12026        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12027        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
12029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
12030        // (intrinsic_wo_chain:{ *:[f32] } 1862:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
12031        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS,
12032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
12033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
12034        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12035        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12036        GIR_EraseFromParent, /*InsnID*/0,
12037        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12038        // GIR_Coverage, 709,
12039        GIR_Done,
12040      // Label 698: @29123
12041      GIM_Try, /*On fail goto*//*Label 699*/ 29170, // Rule ID 710 //
12042        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
12043        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
12044        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12045        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
12046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
12047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12048        // (intrinsic_wo_chain:{ *:[f32] } 1863:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
12049        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD,
12050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
12051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
12052        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12053        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12054        GIR_EraseFromParent, /*InsnID*/0,
12055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12056        // GIR_Coverage, 710,
12057        GIR_Done,
12058      // Label 699: @29170
12059      GIM_Try, /*On fail goto*//*Label 700*/ 29217, // Rule ID 711 //
12060        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
12061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
12062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
12065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
12066        // (intrinsic_wo_chain:{ *:[f32] } 1863:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
12067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS,
12068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
12069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
12070        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12071        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12072        GIR_EraseFromParent, /*InsnID*/0,
12073        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12074        // GIR_Coverage, 711,
12075        GIR_Done,
12076      // Label 700: @29217
12077      GIM_Try, /*On fail goto*//*Label 701*/ 29264, // Rule ID 1230 //
12078        GIM_CheckFeatures, GIFBS_HasNEON,
12079        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12080        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12081        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
12082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12084        // (intrinsic_wo_chain:{ *:[v4i16] } 1715:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
12085        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8,
12086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12088        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12089        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12090        GIR_EraseFromParent, /*InsnID*/0,
12091        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12092        // GIR_Coverage, 1230,
12093        GIR_Done,
12094      // Label 701: @29264
12095      GIM_Try, /*On fail goto*//*Label 702*/ 29311, // Rule ID 1231 //
12096        GIM_CheckFeatures, GIFBS_HasNEON,
12097        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12098        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12099        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12102        // (intrinsic_wo_chain:{ *:[v2i32] } 1715:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
12103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16,
12104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12106        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12107        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12108        GIR_EraseFromParent, /*InsnID*/0,
12109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12110        // GIR_Coverage, 1231,
12111        GIR_Done,
12112      // Label 702: @29311
12113      GIM_Try, /*On fail goto*//*Label 703*/ 29358, // Rule ID 1232 //
12114        GIM_CheckFeatures, GIFBS_HasNEON,
12115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12120        // (intrinsic_wo_chain:{ *:[v1i64] } 1715:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
12121        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32,
12122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12124        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12125        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12126        GIR_EraseFromParent, /*InsnID*/0,
12127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12128        // GIR_Coverage, 1232,
12129        GIR_Done,
12130      // Label 703: @29358
12131      GIM_Try, /*On fail goto*//*Label 704*/ 29405, // Rule ID 1233 //
12132        GIM_CheckFeatures, GIFBS_HasNEON,
12133        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12134        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12135        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12138        // (intrinsic_wo_chain:{ *:[v8i16] } 1715:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
12139        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8,
12140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12142        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12143        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12144        GIR_EraseFromParent, /*InsnID*/0,
12145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12146        // GIR_Coverage, 1233,
12147        GIR_Done,
12148      // Label 704: @29405
12149      GIM_Try, /*On fail goto*//*Label 705*/ 29452, // Rule ID 1234 //
12150        GIM_CheckFeatures, GIFBS_HasNEON,
12151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12156        // (intrinsic_wo_chain:{ *:[v4i32] } 1715:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
12157        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16,
12158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12160        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12161        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12162        GIR_EraseFromParent, /*InsnID*/0,
12163        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12164        // GIR_Coverage, 1234,
12165        GIR_Done,
12166      // Label 705: @29452
12167      GIM_Try, /*On fail goto*//*Label 706*/ 29499, // Rule ID 1235 //
12168        GIM_CheckFeatures, GIFBS_HasNEON,
12169        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
12170        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
12171        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12174        // (intrinsic_wo_chain:{ *:[v2i64] } 1715:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
12175        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32,
12176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12178        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12179        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12180        GIR_EraseFromParent, /*InsnID*/0,
12181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12182        // GIR_Coverage, 1235,
12183        GIR_Done,
12184      // Label 706: @29499
12185      GIM_Try, /*On fail goto*//*Label 707*/ 29546, // Rule ID 1236 //
12186        GIM_CheckFeatures, GIFBS_HasNEON,
12187        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12188        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12189        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
12190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12192        // (intrinsic_wo_chain:{ *:[v4i16] } 1716:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
12193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8,
12194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12196        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12197        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12198        GIR_EraseFromParent, /*InsnID*/0,
12199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12200        // GIR_Coverage, 1236,
12201        GIR_Done,
12202      // Label 707: @29546
12203      GIM_Try, /*On fail goto*//*Label 708*/ 29593, // Rule ID 1237 //
12204        GIM_CheckFeatures, GIFBS_HasNEON,
12205        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12206        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12210        // (intrinsic_wo_chain:{ *:[v2i32] } 1716:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
12211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16,
12212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12214        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12215        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12216        GIR_EraseFromParent, /*InsnID*/0,
12217        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12218        // GIR_Coverage, 1237,
12219        GIR_Done,
12220      // Label 708: @29593
12221      GIM_Try, /*On fail goto*//*Label 709*/ 29640, // Rule ID 1238 //
12222        GIM_CheckFeatures, GIFBS_HasNEON,
12223        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12224        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12225        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12228        // (intrinsic_wo_chain:{ *:[v1i64] } 1716:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
12229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32,
12230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12232        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12233        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12234        GIR_EraseFromParent, /*InsnID*/0,
12235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12236        // GIR_Coverage, 1238,
12237        GIR_Done,
12238      // Label 709: @29640
12239      GIM_Try, /*On fail goto*//*Label 710*/ 29687, // Rule ID 1239 //
12240        GIM_CheckFeatures, GIFBS_HasNEON,
12241        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12242        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12243        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12246        // (intrinsic_wo_chain:{ *:[v8i16] } 1716:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
12247        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8,
12248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12250        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12251        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12252        GIR_EraseFromParent, /*InsnID*/0,
12253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12254        // GIR_Coverage, 1239,
12255        GIR_Done,
12256      // Label 710: @29687
12257      GIM_Try, /*On fail goto*//*Label 711*/ 29734, // Rule ID 1240 //
12258        GIM_CheckFeatures, GIFBS_HasNEON,
12259        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12260        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12261        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12264        // (intrinsic_wo_chain:{ *:[v4i32] } 1716:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
12265        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16,
12266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12268        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12269        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12270        GIR_EraseFromParent, /*InsnID*/0,
12271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12272        // GIR_Coverage, 1240,
12273        GIR_Done,
12274      // Label 711: @29734
12275      GIM_Try, /*On fail goto*//*Label 712*/ 29781, // Rule ID 1241 //
12276        GIM_CheckFeatures, GIFBS_HasNEON,
12277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
12278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
12279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12282        // (intrinsic_wo_chain:{ *:[v2i64] } 1716:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
12283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32,
12284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12286        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12287        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12288        GIR_EraseFromParent, /*InsnID*/0,
12289        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12290        // GIR_Coverage, 1241,
12291        GIR_Done,
12292      // Label 712: @29781
12293      GIM_Try, /*On fail goto*//*Label 713*/ 29828, // Rule ID 1270 //
12294        GIM_CheckFeatures, GIFBS_HasNEON,
12295        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12296        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12297        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12300        // (intrinsic_wo_chain:{ *:[v2i32] } 1741:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
12301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd,
12302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12304        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12305        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12306        GIR_EraseFromParent, /*InsnID*/0,
12307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12308        // GIR_Coverage, 1270,
12309        GIR_Done,
12310      // Label 713: @29828
12311      GIM_Try, /*On fail goto*//*Label 714*/ 29875, // Rule ID 1271 //
12312        GIM_CheckFeatures, GIFBS_HasNEON,
12313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12318        // (intrinsic_wo_chain:{ *:[v4i32] } 1741:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
12319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq,
12320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12322        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12323        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12324        GIR_EraseFromParent, /*InsnID*/0,
12325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12326        // GIR_Coverage, 1271,
12327        GIR_Done,
12328      // Label 714: @29875
12329      GIM_Try, /*On fail goto*//*Label 715*/ 29922, // Rule ID 1272 //
12330        GIM_CheckFeatures, GIFBS_HasNEON,
12331        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12336        // (intrinsic_wo_chain:{ *:[v2f32] } 1741:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
12337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd,
12338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12340        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12341        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12342        GIR_EraseFromParent, /*InsnID*/0,
12343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12344        // GIR_Coverage, 1272,
12345        GIR_Done,
12346      // Label 715: @29922
12347      GIM_Try, /*On fail goto*//*Label 716*/ 29969, // Rule ID 1273 //
12348        GIM_CheckFeatures, GIFBS_HasNEON,
12349        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12350        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12354        // (intrinsic_wo_chain:{ *:[v4f32] } 1741:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
12355        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq,
12356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12358        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12359        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12360        GIR_EraseFromParent, /*InsnID*/0,
12361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12362        // GIR_Coverage, 1273,
12363        GIR_Done,
12364      // Label 716: @29969
12365      GIM_Try, /*On fail goto*//*Label 717*/ 30016, // Rule ID 1274 //
12366        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
12367        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12368        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12369        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12372        // (intrinsic_wo_chain:{ *:[v4f16] } 1741:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
12373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd,
12374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12376        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12377        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12378        GIR_EraseFromParent, /*InsnID*/0,
12379        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12380        // GIR_Coverage, 1274,
12381        GIR_Done,
12382      // Label 717: @30016
12383      GIM_Try, /*On fail goto*//*Label 718*/ 30063, // Rule ID 1275 //
12384        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
12385        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
12386        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12387        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12390        // (intrinsic_wo_chain:{ *:[v8f16] } 1741:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
12391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq,
12392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12394        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12395        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12396        GIR_EraseFromParent, /*InsnID*/0,
12397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12398        // GIR_Coverage, 1275,
12399        GIR_Done,
12400      // Label 718: @30063
12401      GIM_Try, /*On fail goto*//*Label 719*/ 30110, // Rule ID 1280 //
12402        GIM_CheckFeatures, GIFBS_HasNEON,
12403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12408        // (intrinsic_wo_chain:{ *:[v2i32] } 1754:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
12409        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd,
12410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12412        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12413        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12414        GIR_EraseFromParent, /*InsnID*/0,
12415        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12416        // GIR_Coverage, 1280,
12417        GIR_Done,
12418      // Label 719: @30110
12419      GIM_Try, /*On fail goto*//*Label 720*/ 30157, // Rule ID 1281 //
12420        GIM_CheckFeatures, GIFBS_HasNEON,
12421        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12422        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12423        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12425        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12426        // (intrinsic_wo_chain:{ *:[v4i32] } 1754:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
12427        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq,
12428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12430        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12431        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12432        GIR_EraseFromParent, /*InsnID*/0,
12433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12434        // GIR_Coverage, 1281,
12435        GIR_Done,
12436      // Label 720: @30157
12437      GIM_Try, /*On fail goto*//*Label 721*/ 30204, // Rule ID 1282 //
12438        GIM_CheckFeatures, GIFBS_HasNEON,
12439        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12440        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12441        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12444        // (intrinsic_wo_chain:{ *:[v2f32] } 1754:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
12445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd,
12446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12448        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12449        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12450        GIR_EraseFromParent, /*InsnID*/0,
12451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12452        // GIR_Coverage, 1282,
12453        GIR_Done,
12454      // Label 721: @30204
12455      GIM_Try, /*On fail goto*//*Label 722*/ 30251, // Rule ID 1283 //
12456        GIM_CheckFeatures, GIFBS_HasNEON,
12457        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12458        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12459        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12462        // (intrinsic_wo_chain:{ *:[v4f32] } 1754:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
12463        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq,
12464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12466        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12467        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12468        GIR_EraseFromParent, /*InsnID*/0,
12469        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12470        // GIR_Coverage, 1283,
12471        GIR_Done,
12472      // Label 722: @30251
12473      GIM_Try, /*On fail goto*//*Label 723*/ 30298, // Rule ID 1284 //
12474        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
12475        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12476        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12477        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12480        // (intrinsic_wo_chain:{ *:[v4f16] } 1754:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
12481        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd,
12482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12484        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12485        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12486        GIR_EraseFromParent, /*InsnID*/0,
12487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12488        // GIR_Coverage, 1284,
12489        GIR_Done,
12490      // Label 723: @30298
12491      GIM_Try, /*On fail goto*//*Label 724*/ 30345, // Rule ID 1285 //
12492        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
12493        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
12494        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12498        // (intrinsic_wo_chain:{ *:[v8f16] } 1754:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
12499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq,
12500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12502        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12503        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12504        GIR_EraseFromParent, /*InsnID*/0,
12505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12506        // GIR_Coverage, 1285,
12507        GIR_Done,
12508      // Label 724: @30345
12509      GIM_Try, /*On fail goto*//*Label 725*/ 30392, // Rule ID 1506 //
12510        GIM_CheckFeatures, GIFBS_HasNEON,
12511        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12512        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12513        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
12514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12516        // (intrinsic_wo_chain:{ *:[v8i8] } 1721:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
12517        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8,
12518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12520        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12521        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12522        GIR_EraseFromParent, /*InsnID*/0,
12523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12524        // GIR_Coverage, 1506,
12525        GIR_Done,
12526      // Label 725: @30392
12527      GIM_Try, /*On fail goto*//*Label 726*/ 30439, // Rule ID 1507 //
12528        GIM_CheckFeatures, GIFBS_HasNEON,
12529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12534        // (intrinsic_wo_chain:{ *:[v4i16] } 1721:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
12535        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16,
12536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12538        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12539        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12540        GIR_EraseFromParent, /*InsnID*/0,
12541        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12542        // GIR_Coverage, 1507,
12543        GIR_Done,
12544      // Label 726: @30439
12545      GIM_Try, /*On fail goto*//*Label 727*/ 30486, // Rule ID 1508 //
12546        GIM_CheckFeatures, GIFBS_HasNEON,
12547        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12548        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12549        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12552        // (intrinsic_wo_chain:{ *:[v2i32] } 1721:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
12553        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32,
12554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12556        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12557        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12558        GIR_EraseFromParent, /*InsnID*/0,
12559        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12560        // GIR_Coverage, 1508,
12561        GIR_Done,
12562      // Label 727: @30486
12563      GIM_Try, /*On fail goto*//*Label 728*/ 30533, // Rule ID 1509 //
12564        GIM_CheckFeatures, GIFBS_HasNEON,
12565        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12566        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
12567        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12570        // (intrinsic_wo_chain:{ *:[v16i8] } 1721:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
12571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8,
12572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12574        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12575        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12576        GIR_EraseFromParent, /*InsnID*/0,
12577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12578        // GIR_Coverage, 1509,
12579        GIR_Done,
12580      // Label 728: @30533
12581      GIM_Try, /*On fail goto*//*Label 729*/ 30580, // Rule ID 1510 //
12582        GIM_CheckFeatures, GIFBS_HasNEON,
12583        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12584        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12585        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12588        // (intrinsic_wo_chain:{ *:[v8i16] } 1721:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
12589        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16,
12590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12592        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12593        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12594        GIR_EraseFromParent, /*InsnID*/0,
12595        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12596        // GIR_Coverage, 1510,
12597        GIR_Done,
12598      // Label 729: @30580
12599      GIM_Try, /*On fail goto*//*Label 730*/ 30627, // Rule ID 1511 //
12600        GIM_CheckFeatures, GIFBS_HasNEON,
12601        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
12602        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12603        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12606        // (intrinsic_wo_chain:{ *:[v4i32] } 1721:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
12607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32,
12608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12610        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12611        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12612        GIR_EraseFromParent, /*InsnID*/0,
12613        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12614        // GIR_Coverage, 1511,
12615        GIR_Done,
12616      // Label 730: @30627
12617      GIM_Try, /*On fail goto*//*Label 731*/ 30674, // Rule ID 1522 //
12618        GIM_CheckFeatures, GIFBS_HasNEON,
12619        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12620        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12621        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
12622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12624        // (intrinsic_wo_chain:{ *:[v8i8] } 1727:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
12625        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8,
12626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12628        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12629        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12630        GIR_EraseFromParent, /*InsnID*/0,
12631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12632        // GIR_Coverage, 1522,
12633        GIR_Done,
12634      // Label 731: @30674
12635      GIM_Try, /*On fail goto*//*Label 732*/ 30721, // Rule ID 1523 //
12636        GIM_CheckFeatures, GIFBS_HasNEON,
12637        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12638        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12639        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12642        // (intrinsic_wo_chain:{ *:[v4i16] } 1727:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
12643        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16,
12644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12647        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12648        GIR_EraseFromParent, /*InsnID*/0,
12649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12650        // GIR_Coverage, 1523,
12651        GIR_Done,
12652      // Label 732: @30721
12653      GIM_Try, /*On fail goto*//*Label 733*/ 30768, // Rule ID 1524 //
12654        GIM_CheckFeatures, GIFBS_HasNEON,
12655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12660        // (intrinsic_wo_chain:{ *:[v2i32] } 1727:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
12661        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32,
12662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12664        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12665        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12666        GIR_EraseFromParent, /*InsnID*/0,
12667        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12668        // GIR_Coverage, 1524,
12669        GIR_Done,
12670      // Label 733: @30768
12671      GIM_Try, /*On fail goto*//*Label 734*/ 30815, // Rule ID 1525 //
12672        GIM_CheckFeatures, GIFBS_HasNEON,
12673        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12674        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
12675        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12678        // (intrinsic_wo_chain:{ *:[v16i8] } 1727:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
12679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8,
12680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12682        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12683        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12684        GIR_EraseFromParent, /*InsnID*/0,
12685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12686        // GIR_Coverage, 1525,
12687        GIR_Done,
12688      // Label 734: @30815
12689      GIM_Try, /*On fail goto*//*Label 735*/ 30862, // Rule ID 1526 //
12690        GIM_CheckFeatures, GIFBS_HasNEON,
12691        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12692        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12693        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12696        // (intrinsic_wo_chain:{ *:[v8i16] } 1727:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
12697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16,
12698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12700        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12701        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12702        GIR_EraseFromParent, /*InsnID*/0,
12703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12704        // GIR_Coverage, 1526,
12705        GIR_Done,
12706      // Label 735: @30862
12707      GIM_Try, /*On fail goto*//*Label 736*/ 30909, // Rule ID 1527 //
12708        GIM_CheckFeatures, GIFBS_HasNEON,
12709        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
12710        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12711        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12714        // (intrinsic_wo_chain:{ *:[v4i32] } 1727:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
12715        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32,
12716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12719        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12720        GIR_EraseFromParent, /*InsnID*/0,
12721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12722        // GIR_Coverage, 1527,
12723        GIR_Done,
12724      // Label 736: @30909
12725      GIM_Try, /*On fail goto*//*Label 737*/ 30956, // Rule ID 1528 //
12726        GIM_CheckFeatures, GIFBS_HasNEON,
12727        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12728        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12729        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
12730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12732        // (intrinsic_wo_chain:{ *:[v8i8] } 1670:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
12733        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8,
12734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12736        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12737        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12738        GIR_EraseFromParent, /*InsnID*/0,
12739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12740        // GIR_Coverage, 1528,
12741        GIR_Done,
12742      // Label 737: @30956
12743      GIM_Try, /*On fail goto*//*Label 738*/ 31003, // Rule ID 1529 //
12744        GIM_CheckFeatures, GIFBS_HasNEON,
12745        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12746        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12747        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
12748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12750        // (intrinsic_wo_chain:{ *:[v4i16] } 1670:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
12751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16,
12752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12754        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12755        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12756        GIR_EraseFromParent, /*InsnID*/0,
12757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12758        // GIR_Coverage, 1529,
12759        GIR_Done,
12760      // Label 738: @31003
12761      GIM_Try, /*On fail goto*//*Label 739*/ 31050, // Rule ID 1530 //
12762        GIM_CheckFeatures, GIFBS_HasNEON,
12763        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12764        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12765        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
12766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
12768        // (intrinsic_wo_chain:{ *:[v2i32] } 1670:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
12769        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32,
12770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12772        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12773        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12774        GIR_EraseFromParent, /*InsnID*/0,
12775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12776        // GIR_Coverage, 1530,
12777        GIR_Done,
12778      // Label 739: @31050
12779      GIM_Try, /*On fail goto*//*Label 740*/ 31097, // Rule ID 1531 //
12780        GIM_CheckFeatures, GIFBS_HasNEON,
12781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
12783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12786        // (intrinsic_wo_chain:{ *:[v16i8] } 1670:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
12787        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8,
12788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12790        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12791        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12792        GIR_EraseFromParent, /*InsnID*/0,
12793        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12794        // GIR_Coverage, 1531,
12795        GIR_Done,
12796      // Label 740: @31097
12797      GIM_Try, /*On fail goto*//*Label 741*/ 31144, // Rule ID 1532 //
12798        GIM_CheckFeatures, GIFBS_HasNEON,
12799        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
12801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12804        // (intrinsic_wo_chain:{ *:[v8i16] } 1670:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
12805        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16,
12806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12808        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12809        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12810        GIR_EraseFromParent, /*InsnID*/0,
12811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12812        // GIR_Coverage, 1532,
12813        GIR_Done,
12814      // Label 741: @31144
12815      GIM_Try, /*On fail goto*//*Label 742*/ 31191, // Rule ID 1533 //
12816        GIM_CheckFeatures, GIFBS_HasNEON,
12817        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
12818        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
12819        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12822        // (intrinsic_wo_chain:{ *:[v4i32] } 1670:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
12823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32,
12824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12826        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12827        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12828        GIR_EraseFromParent, /*InsnID*/0,
12829        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12830        // GIR_Coverage, 1533,
12831        GIR_Done,
12832      // Label 742: @31191
12833      GIM_Try, /*On fail goto*//*Label 743*/ 31238, // Rule ID 1577 //
12834        GIM_CheckFeatures, GIFBS_HasNEON,
12835        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
12836        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12837        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12839        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12840        // (intrinsic_wo_chain:{ *:[v8i8] } 1724:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
12841        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8,
12842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12844        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12845        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12846        GIR_EraseFromParent, /*InsnID*/0,
12847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12848        // GIR_Coverage, 1577,
12849        GIR_Done,
12850      // Label 743: @31238
12851      GIM_Try, /*On fail goto*//*Label 744*/ 31285, // Rule ID 1578 //
12852        GIM_CheckFeatures, GIFBS_HasNEON,
12853        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
12854        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12855        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12858        // (intrinsic_wo_chain:{ *:[v4i16] } 1724:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
12859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16,
12860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12862        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12863        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12864        GIR_EraseFromParent, /*InsnID*/0,
12865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12866        // GIR_Coverage, 1578,
12867        GIR_Done,
12868      // Label 744: @31285
12869      GIM_Try, /*On fail goto*//*Label 745*/ 31332, // Rule ID 1579 //
12870        GIM_CheckFeatures, GIFBS_HasNEON,
12871        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
12872        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12873        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
12874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12876        // (intrinsic_wo_chain:{ *:[v2i32] } 1724:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
12877        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32,
12878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12880        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12881        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12882        GIR_EraseFromParent, /*InsnID*/0,
12883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12884        // GIR_Coverage, 1579,
12885        GIR_Done,
12886      // Label 745: @31332
12887      GIM_Try, /*On fail goto*//*Label 746*/ 31379, // Rule ID 1580 //
12888        GIM_CheckFeatures, GIFBS_HasNEON,
12889        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
12890        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12891        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12894        // (intrinsic_wo_chain:{ *:[v8i8] } 1726:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
12895        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8,
12896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12899        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12900        GIR_EraseFromParent, /*InsnID*/0,
12901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12902        // GIR_Coverage, 1580,
12903        GIR_Done,
12904      // Label 746: @31379
12905      GIM_Try, /*On fail goto*//*Label 747*/ 31426, // Rule ID 1581 //
12906        GIM_CheckFeatures, GIFBS_HasNEON,
12907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
12908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12912        // (intrinsic_wo_chain:{ *:[v4i16] } 1726:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
12913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16,
12914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12916        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12917        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12918        GIR_EraseFromParent, /*InsnID*/0,
12919        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12920        // GIR_Coverage, 1581,
12921        GIR_Done,
12922      // Label 747: @31426
12923      GIM_Try, /*On fail goto*//*Label 748*/ 31473, // Rule ID 1582 //
12924        GIM_CheckFeatures, GIFBS_HasNEON,
12925        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
12926        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12927        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
12928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12930        // (intrinsic_wo_chain:{ *:[v2i32] } 1726:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
12931        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32,
12932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12934        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12935        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12936        GIR_EraseFromParent, /*InsnID*/0,
12937        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12938        // GIR_Coverage, 1582,
12939        GIR_Done,
12940      // Label 748: @31473
12941      GIM_Try, /*On fail goto*//*Label 749*/ 31520, // Rule ID 1583 //
12942        GIM_CheckFeatures, GIFBS_HasNEON,
12943        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
12944        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
12945        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12948        // (intrinsic_wo_chain:{ *:[v8i8] } 1725:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
12949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8,
12950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12952        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12953        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12954        GIR_EraseFromParent, /*InsnID*/0,
12955        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12956        // GIR_Coverage, 1583,
12957        GIR_Done,
12958      // Label 749: @31520
12959      GIM_Try, /*On fail goto*//*Label 750*/ 31567, // Rule ID 1584 //
12960        GIM_CheckFeatures, GIFBS_HasNEON,
12961        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
12962        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
12963        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12966        // (intrinsic_wo_chain:{ *:[v4i16] } 1725:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
12967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16,
12968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12970        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12971        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12972        GIR_EraseFromParent, /*InsnID*/0,
12973        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12974        // GIR_Coverage, 1584,
12975        GIR_Done,
12976      // Label 750: @31567
12977      GIM_Try, /*On fail goto*//*Label 751*/ 31614, // Rule ID 1585 //
12978        GIM_CheckFeatures, GIFBS_HasNEON,
12979        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
12980        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12981        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
12982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
12984        // (intrinsic_wo_chain:{ *:[v2i32] } 1725:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
12985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32,
12986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
12988        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12989        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
12990        GIR_EraseFromParent, /*InsnID*/0,
12991        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12992        // GIR_Coverage, 1585,
12993        GIR_Done,
12994      // Label 751: @31614
12995      GIM_Try, /*On fail goto*//*Label 752*/ 31654, // Rule ID 1608 //
12996        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
12997        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
12998        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
12999        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13002        // (intrinsic_wo_chain:{ *:[v2i32] } 1671:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13003        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf,
13004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13006        GIR_EraseFromParent, /*InsnID*/0,
13007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13008        // GIR_Coverage, 1608,
13009        GIR_Done,
13010      // Label 752: @31654
13011      GIM_Try, /*On fail goto*//*Label 753*/ 31694, // Rule ID 1609 //
13012        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13013        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
13014        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13015        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13018        // (intrinsic_wo_chain:{ *:[v4i32] } 1671:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13019        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf,
13020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13022        GIR_EraseFromParent, /*InsnID*/0,
13023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13024        // GIR_Coverage, 1609,
13025        GIR_Done,
13026      // Label 753: @31694
13027      GIM_Try, /*On fail goto*//*Label 754*/ 31734, // Rule ID 1610 //
13028        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13029        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
13030        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13031        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13034        // (intrinsic_wo_chain:{ *:[v2i32] } 1672:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf,
13036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13038        GIR_EraseFromParent, /*InsnID*/0,
13039        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13040        // GIR_Coverage, 1610,
13041        GIR_Done,
13042      // Label 754: @31734
13043      GIM_Try, /*On fail goto*//*Label 755*/ 31774, // Rule ID 1611 //
13044        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13045        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
13046        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13047        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13050        // (intrinsic_wo_chain:{ *:[v4i32] } 1672:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13051        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf,
13052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13054        GIR_EraseFromParent, /*InsnID*/0,
13055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13056        // GIR_Coverage, 1611,
13057        GIR_Done,
13058      // Label 755: @31774
13059      GIM_Try, /*On fail goto*//*Label 756*/ 31814, // Rule ID 1612 //
13060        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
13062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13066        // (intrinsic_wo_chain:{ *:[v4i16] } 1671:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh,
13068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13070        GIR_EraseFromParent, /*InsnID*/0,
13071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13072        // GIR_Coverage, 1612,
13073        GIR_Done,
13074      // Label 756: @31814
13075      GIM_Try, /*On fail goto*//*Label 757*/ 31854, // Rule ID 1613 //
13076        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13077        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
13078        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13079        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13082        // (intrinsic_wo_chain:{ *:[v8i16] } 1671:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh,
13084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13086        GIR_EraseFromParent, /*InsnID*/0,
13087        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13088        // GIR_Coverage, 1613,
13089        GIR_Done,
13090      // Label 757: @31854
13091      GIM_Try, /*On fail goto*//*Label 758*/ 31894, // Rule ID 1614 //
13092        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13093        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
13094        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13095        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13098        // (intrinsic_wo_chain:{ *:[v4i16] } 1672:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13099        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh,
13100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13102        GIR_EraseFromParent, /*InsnID*/0,
13103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13104        // GIR_Coverage, 1614,
13105        GIR_Done,
13106      // Label 758: @31894
13107      GIM_Try, /*On fail goto*//*Label 759*/ 31934, // Rule ID 1615 //
13108        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
13110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13114        // (intrinsic_wo_chain:{ *:[v8i16] } 1672:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh,
13116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13118        GIR_EraseFromParent, /*InsnID*/0,
13119        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13120        // GIR_Coverage, 1615,
13121        GIR_Done,
13122      // Label 759: @31934
13123      GIM_Try, /*On fail goto*//*Label 760*/ 31974, // Rule ID 1616 //
13124        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13125        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
13126        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13127        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13130        // (intrinsic_wo_chain:{ *:[v2i32] } 1681:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13131        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf,
13132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13134        GIR_EraseFromParent, /*InsnID*/0,
13135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13136        // GIR_Coverage, 1616,
13137        GIR_Done,
13138      // Label 760: @31974
13139      GIM_Try, /*On fail goto*//*Label 761*/ 32014, // Rule ID 1617 //
13140        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13141        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
13142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13146        // (intrinsic_wo_chain:{ *:[v4i32] } 1681:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf,
13148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13150        GIR_EraseFromParent, /*InsnID*/0,
13151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13152        // GIR_Coverage, 1617,
13153        GIR_Done,
13154      // Label 761: @32014
13155      GIM_Try, /*On fail goto*//*Label 762*/ 32054, // Rule ID 1618 //
13156        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13157        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
13158        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13159        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13160        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13161        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13162        // (intrinsic_wo_chain:{ *:[v2i32] } 1682:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13163        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf,
13164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13166        GIR_EraseFromParent, /*InsnID*/0,
13167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13168        // GIR_Coverage, 1618,
13169        GIR_Done,
13170      // Label 762: @32054
13171      GIM_Try, /*On fail goto*//*Label 763*/ 32094, // Rule ID 1619 //
13172        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13173        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
13174        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13175        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13178        // (intrinsic_wo_chain:{ *:[v4i32] } 1682:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13179        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf,
13180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13182        GIR_EraseFromParent, /*InsnID*/0,
13183        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13184        // GIR_Coverage, 1619,
13185        GIR_Done,
13186      // Label 763: @32094
13187      GIM_Try, /*On fail goto*//*Label 764*/ 32134, // Rule ID 1620 //
13188        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13189        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
13190        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13191        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13194        // (intrinsic_wo_chain:{ *:[v4i16] } 1681:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh,
13196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13198        GIR_EraseFromParent, /*InsnID*/0,
13199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13200        // GIR_Coverage, 1620,
13201        GIR_Done,
13202      // Label 764: @32134
13203      GIM_Try, /*On fail goto*//*Label 765*/ 32174, // Rule ID 1621 //
13204        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13205        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
13206        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13210        // (intrinsic_wo_chain:{ *:[v8i16] } 1681:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh,
13212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13214        GIR_EraseFromParent, /*InsnID*/0,
13215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13216        // GIR_Coverage, 1621,
13217        GIR_Done,
13218      // Label 765: @32174
13219      GIM_Try, /*On fail goto*//*Label 766*/ 32214, // Rule ID 1622 //
13220        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
13222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13224        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13226        // (intrinsic_wo_chain:{ *:[v4i16] } 1682:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13227        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh,
13228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13230        GIR_EraseFromParent, /*InsnID*/0,
13231        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13232        // GIR_Coverage, 1622,
13233        GIR_Done,
13234      // Label 766: @32214
13235      GIM_Try, /*On fail goto*//*Label 767*/ 32254, // Rule ID 1623 //
13236        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13237        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
13238        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13239        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13242        // (intrinsic_wo_chain:{ *:[v8i16] } 1682:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh,
13244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13246        GIR_EraseFromParent, /*InsnID*/0,
13247        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13248        // GIR_Coverage, 1623,
13249        GIR_Done,
13250      // Label 767: @32254
13251      GIM_Try, /*On fail goto*//*Label 768*/ 32294, // Rule ID 1624 //
13252        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13253        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
13254        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13255        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13258        // (intrinsic_wo_chain:{ *:[v2i32] } 1683:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf,
13260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13262        GIR_EraseFromParent, /*InsnID*/0,
13263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13264        // GIR_Coverage, 1624,
13265        GIR_Done,
13266      // Label 768: @32294
13267      GIM_Try, /*On fail goto*//*Label 769*/ 32334, // Rule ID 1625 //
13268        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
13270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13274        // (intrinsic_wo_chain:{ *:[v4i32] } 1683:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf,
13276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13278        GIR_EraseFromParent, /*InsnID*/0,
13279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13280        // GIR_Coverage, 1625,
13281        GIR_Done,
13282      // Label 769: @32334
13283      GIM_Try, /*On fail goto*//*Label 770*/ 32374, // Rule ID 1626 //
13284        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
13286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13290        // (intrinsic_wo_chain:{ *:[v2i32] } 1684:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf,
13292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13294        GIR_EraseFromParent, /*InsnID*/0,
13295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13296        // GIR_Coverage, 1626,
13297        GIR_Done,
13298      // Label 770: @32374
13299      GIM_Try, /*On fail goto*//*Label 771*/ 32414, // Rule ID 1627 //
13300        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13301        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
13302        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13303        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13306        // (intrinsic_wo_chain:{ *:[v4i32] } 1684:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf,
13308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13310        GIR_EraseFromParent, /*InsnID*/0,
13311        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13312        // GIR_Coverage, 1627,
13313        GIR_Done,
13314      // Label 771: @32414
13315      GIM_Try, /*On fail goto*//*Label 772*/ 32454, // Rule ID 1628 //
13316        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13317        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
13318        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13319        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13322        // (intrinsic_wo_chain:{ *:[v4i16] } 1683:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13323        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh,
13324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13326        GIR_EraseFromParent, /*InsnID*/0,
13327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13328        // GIR_Coverage, 1628,
13329        GIR_Done,
13330      // Label 772: @32454
13331      GIM_Try, /*On fail goto*//*Label 773*/ 32494, // Rule ID 1629 //
13332        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13333        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
13334        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13335        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13338        // (intrinsic_wo_chain:{ *:[v8i16] } 1683:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh,
13340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13342        GIR_EraseFromParent, /*InsnID*/0,
13343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13344        // GIR_Coverage, 1629,
13345        GIR_Done,
13346      // Label 773: @32494
13347      GIM_Try, /*On fail goto*//*Label 774*/ 32534, // Rule ID 1630 //
13348        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13349        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
13350        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13354        // (intrinsic_wo_chain:{ *:[v4i16] } 1684:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13355        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh,
13356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13358        GIR_EraseFromParent, /*InsnID*/0,
13359        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13360        // GIR_Coverage, 1630,
13361        GIR_Done,
13362      // Label 774: @32534
13363      GIM_Try, /*On fail goto*//*Label 775*/ 32574, // Rule ID 1631 //
13364        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13365        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
13366        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13367        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13370        // (intrinsic_wo_chain:{ *:[v8i16] } 1684:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13371        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh,
13372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13374        GIR_EraseFromParent, /*InsnID*/0,
13375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13376        // GIR_Coverage, 1631,
13377        GIR_Done,
13378      // Label 775: @32574
13379      GIM_Try, /*On fail goto*//*Label 776*/ 32614, // Rule ID 1632 //
13380        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
13382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13386        // (intrinsic_wo_chain:{ *:[v2i32] } 1679:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13387        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf,
13388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13390        GIR_EraseFromParent, /*InsnID*/0,
13391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13392        // GIR_Coverage, 1632,
13393        GIR_Done,
13394      // Label 776: @32614
13395      GIM_Try, /*On fail goto*//*Label 777*/ 32654, // Rule ID 1633 //
13396        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
13398        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13402        // (intrinsic_wo_chain:{ *:[v4i32] } 1679:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf,
13404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13406        GIR_EraseFromParent, /*InsnID*/0,
13407        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13408        // GIR_Coverage, 1633,
13409        GIR_Done,
13410      // Label 777: @32654
13411      GIM_Try, /*On fail goto*//*Label 778*/ 32694, // Rule ID 1634 //
13412        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13413        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
13414        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13415        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13418        // (intrinsic_wo_chain:{ *:[v2i32] } 1680:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
13419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf,
13420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13422        GIR_EraseFromParent, /*InsnID*/0,
13423        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13424        // GIR_Coverage, 1634,
13425        GIR_Done,
13426      // Label 778: @32694
13427      GIM_Try, /*On fail goto*//*Label 779*/ 32734, // Rule ID 1635 //
13428        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13429        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
13430        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13431        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13434        // (intrinsic_wo_chain:{ *:[v4i32] } 1680:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
13435        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf,
13436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13438        GIR_EraseFromParent, /*InsnID*/0,
13439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13440        // GIR_Coverage, 1635,
13441        GIR_Done,
13442      // Label 779: @32734
13443      GIM_Try, /*On fail goto*//*Label 780*/ 32774, // Rule ID 1636 //
13444        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
13446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13450        // (intrinsic_wo_chain:{ *:[v4i16] } 1679:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13451        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh,
13452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13454        GIR_EraseFromParent, /*InsnID*/0,
13455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13456        // GIR_Coverage, 1636,
13457        GIR_Done,
13458      // Label 780: @32774
13459      GIM_Try, /*On fail goto*//*Label 781*/ 32814, // Rule ID 1637 //
13460        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13461        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
13462        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13463        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13466        // (intrinsic_wo_chain:{ *:[v8i16] } 1679:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13467        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh,
13468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13470        GIR_EraseFromParent, /*InsnID*/0,
13471        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13472        // GIR_Coverage, 1637,
13473        GIR_Done,
13474      // Label 781: @32814
13475      GIM_Try, /*On fail goto*//*Label 782*/ 32854, // Rule ID 1638 //
13476        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13477        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
13478        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13479        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13482        // (intrinsic_wo_chain:{ *:[v4i16] } 1680:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
13483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh,
13484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13486        GIR_EraseFromParent, /*InsnID*/0,
13487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13488        // GIR_Coverage, 1638,
13489        GIR_Done,
13490      // Label 782: @32854
13491      GIM_Try, /*On fail goto*//*Label 783*/ 32894, // Rule ID 1639 //
13492        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13493        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
13494        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13498        // (intrinsic_wo_chain:{ *:[v8i16] } 1680:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
13499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh,
13500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13502        GIR_EraseFromParent, /*InsnID*/0,
13503        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13504        // GIR_Coverage, 1639,
13505        GIR_Done,
13506      // Label 783: @32894
13507      GIM_Try, /*On fail goto*//*Label 784*/ 32941, // Rule ID 1656 //
13508        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
13509        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2hf,
13510        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13511        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13514        // (intrinsic_wo_chain:{ *:[v4i16] } 1675:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
13515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
13516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13518        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13519        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
13520        GIR_EraseFromParent, /*InsnID*/0,
13521        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13522        // GIR_Coverage, 1656,
13523        GIR_Done,
13524      // Label 784: @32941
13525      GIM_Try, /*On fail goto*//*Label 785*/ 32988, // Rule ID 1657 //
13526        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
13527        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvthf2fp,
13528        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13529        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13532        // (intrinsic_wo_chain:{ *:[v4f32] } 1678:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
13533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
13534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13536        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13537        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
13538        GIR_EraseFromParent, /*InsnID*/0,
13539        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13540        // GIR_Coverage, 1657,
13541        GIR_Done,
13542      // Label 785: @32988
13543      GIM_Try, /*On fail goto*//*Label 786*/ 33028, // Rule ID 1679 //
13544        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13545        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13546        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13547        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13550        // (intrinsic_wo_chain:{ *:[v2f32] } 1747:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13551        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf,
13552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13554        GIR_EraseFromParent, /*InsnID*/0,
13555        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13556        // GIR_Coverage, 1679,
13557        GIR_Done,
13558      // Label 786: @33028
13559      GIM_Try, /*On fail goto*//*Label 787*/ 33068, // Rule ID 1680 //
13560        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13561        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13562        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13563        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13566        // (intrinsic_wo_chain:{ *:[v4f32] } 1747:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13567        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf,
13568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13570        GIR_EraseFromParent, /*InsnID*/0,
13571        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13572        // GIR_Coverage, 1680,
13573        GIR_Done,
13574      // Label 787: @33068
13575      GIM_Try, /*On fail goto*//*Label 788*/ 33108, // Rule ID 1681 //
13576        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13577        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13578        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13579        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13582        // (intrinsic_wo_chain:{ *:[v4f16] } 1747:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13583        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh,
13584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13586        GIR_EraseFromParent, /*InsnID*/0,
13587        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13588        // GIR_Coverage, 1681,
13589        GIR_Done,
13590      // Label 788: @33108
13591      GIM_Try, /*On fail goto*//*Label 789*/ 33148, // Rule ID 1682 //
13592        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13593        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13594        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13595        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13598        // (intrinsic_wo_chain:{ *:[v8f16] } 1747:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh,
13600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13602        GIR_EraseFromParent, /*InsnID*/0,
13603        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13604        // GIR_Coverage, 1682,
13605        GIR_Done,
13606      // Label 789: @33148
13607      GIM_Try, /*On fail goto*//*Label 790*/ 33188, // Rule ID 1683 //
13608        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13609        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
13610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13614        // (intrinsic_wo_chain:{ *:[v2f32] } 1749:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf,
13616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13618        GIR_EraseFromParent, /*InsnID*/0,
13619        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13620        // GIR_Coverage, 1683,
13621        GIR_Done,
13622      // Label 790: @33188
13623      GIM_Try, /*On fail goto*//*Label 791*/ 33228, // Rule ID 1684 //
13624        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13625        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
13626        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13627        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13630        // (intrinsic_wo_chain:{ *:[v4f32] } 1749:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13631        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf,
13632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13634        GIR_EraseFromParent, /*InsnID*/0,
13635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13636        // GIR_Coverage, 1684,
13637        GIR_Done,
13638      // Label 791: @33228
13639      GIM_Try, /*On fail goto*//*Label 792*/ 33268, // Rule ID 1685 //
13640        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13641        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
13642        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13643        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13646        // (intrinsic_wo_chain:{ *:[v4f16] } 1749:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13647        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh,
13648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13650        GIR_EraseFromParent, /*InsnID*/0,
13651        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13652        // GIR_Coverage, 1685,
13653        GIR_Done,
13654      // Label 792: @33268
13655      GIM_Try, /*On fail goto*//*Label 793*/ 33308, // Rule ID 1686 //
13656        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13657        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
13658        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13659        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13662        // (intrinsic_wo_chain:{ *:[v8f16] } 1749:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh,
13664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13666        GIR_EraseFromParent, /*InsnID*/0,
13667        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13668        // GIR_Coverage, 1686,
13669        GIR_Done,
13670      // Label 793: @33308
13671      GIM_Try, /*On fail goto*//*Label 794*/ 33348, // Rule ID 1687 //
13672        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13673        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
13674        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13675        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13678        // (intrinsic_wo_chain:{ *:[v2f32] } 1745:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf,
13680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13682        GIR_EraseFromParent, /*InsnID*/0,
13683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13684        // GIR_Coverage, 1687,
13685        GIR_Done,
13686      // Label 794: @33348
13687      GIM_Try, /*On fail goto*//*Label 795*/ 33388, // Rule ID 1688 //
13688        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
13690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13694        // (intrinsic_wo_chain:{ *:[v4f32] } 1745:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13695        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf,
13696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13698        GIR_EraseFromParent, /*InsnID*/0,
13699        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13700        // GIR_Coverage, 1688,
13701        GIR_Done,
13702      // Label 795: @33388
13703      GIM_Try, /*On fail goto*//*Label 796*/ 33428, // Rule ID 1689 //
13704        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13705        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
13706        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13707        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13710        // (intrinsic_wo_chain:{ *:[v4f16] } 1745:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh,
13712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13714        GIR_EraseFromParent, /*InsnID*/0,
13715        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13716        // GIR_Coverage, 1689,
13717        GIR_Done,
13718      // Label 796: @33428
13719      GIM_Try, /*On fail goto*//*Label 797*/ 33468, // Rule ID 1690 //
13720        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13721        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
13722        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13723        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13726        // (intrinsic_wo_chain:{ *:[v8f16] } 1745:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh,
13728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13730        GIR_EraseFromParent, /*InsnID*/0,
13731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13732        // GIR_Coverage, 1690,
13733        GIR_Done,
13734      // Label 797: @33468
13735      GIM_Try, /*On fail goto*//*Label 798*/ 33508, // Rule ID 1691 //
13736        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13737        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
13738        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13739        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13742        // (intrinsic_wo_chain:{ *:[v2f32] } 1750:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13743        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf,
13744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13746        GIR_EraseFromParent, /*InsnID*/0,
13747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13748        // GIR_Coverage, 1691,
13749        GIR_Done,
13750      // Label 798: @33508
13751      GIM_Try, /*On fail goto*//*Label 799*/ 33548, // Rule ID 1692 //
13752        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13753        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
13754        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13755        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13758        // (intrinsic_wo_chain:{ *:[v4f32] } 1750:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf,
13760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13762        GIR_EraseFromParent, /*InsnID*/0,
13763        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13764        // GIR_Coverage, 1692,
13765        GIR_Done,
13766      // Label 799: @33548
13767      GIM_Try, /*On fail goto*//*Label 800*/ 33588, // Rule ID 1693 //
13768        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13769        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
13770        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13771        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13774        // (intrinsic_wo_chain:{ *:[v4f16] } 1750:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13775        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh,
13776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13778        GIR_EraseFromParent, /*InsnID*/0,
13779        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13780        // GIR_Coverage, 1693,
13781        GIR_Done,
13782      // Label 800: @33588
13783      GIM_Try, /*On fail goto*//*Label 801*/ 33628, // Rule ID 1694 //
13784        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13785        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
13786        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13787        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13790        // (intrinsic_wo_chain:{ *:[v8f16] } 1750:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh,
13792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13794        GIR_EraseFromParent, /*InsnID*/0,
13795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13796        // GIR_Coverage, 1694,
13797        GIR_Done,
13798      // Label 801: @33628
13799      GIM_Try, /*On fail goto*//*Label 802*/ 33668, // Rule ID 1695 //
13800        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13801        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
13802        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13803        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13806        // (intrinsic_wo_chain:{ *:[v2f32] } 1746:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13807        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf,
13808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13810        GIR_EraseFromParent, /*InsnID*/0,
13811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13812        // GIR_Coverage, 1695,
13813        GIR_Done,
13814      // Label 802: @33668
13815      GIM_Try, /*On fail goto*//*Label 803*/ 33708, // Rule ID 1696 //
13816        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13817        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
13818        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13819        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13822        // (intrinsic_wo_chain:{ *:[v4f32] } 1746:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf,
13824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13826        GIR_EraseFromParent, /*InsnID*/0,
13827        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13828        // GIR_Coverage, 1696,
13829        GIR_Done,
13830      // Label 803: @33708
13831      GIM_Try, /*On fail goto*//*Label 804*/ 33748, // Rule ID 1697 //
13832        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13833        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
13834        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13835        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13838        // (intrinsic_wo_chain:{ *:[v4f16] } 1746:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh,
13840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13842        GIR_EraseFromParent, /*InsnID*/0,
13843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13844        // GIR_Coverage, 1697,
13845        GIR_Done,
13846      // Label 804: @33748
13847      GIM_Try, /*On fail goto*//*Label 805*/ 33788, // Rule ID 1698 //
13848        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13849        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
13850        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13851        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13854        // (intrinsic_wo_chain:{ *:[v8f16] } 1746:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh,
13856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13858        GIR_EraseFromParent, /*InsnID*/0,
13859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13860        // GIR_Coverage, 1698,
13861        GIR_Done,
13862      // Label 805: @33788
13863      GIM_Try, /*On fail goto*//*Label 806*/ 33828, // Rule ID 1699 //
13864        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
13866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13870        // (intrinsic_wo_chain:{ *:[v2f32] } 1748:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf,
13872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13874        GIR_EraseFromParent, /*InsnID*/0,
13875        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13876        // GIR_Coverage, 1699,
13877        GIR_Done,
13878      // Label 806: @33828
13879      GIM_Try, /*On fail goto*//*Label 807*/ 33868, // Rule ID 1700 //
13880        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
13881        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
13882        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13883        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13886        // (intrinsic_wo_chain:{ *:[v4f32] } 1748:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13887        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf,
13888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13890        GIR_EraseFromParent, /*InsnID*/0,
13891        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13892        // GIR_Coverage, 1700,
13893        GIR_Done,
13894      // Label 807: @33868
13895      GIM_Try, /*On fail goto*//*Label 808*/ 33908, // Rule ID 1701 //
13896        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13897        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
13898        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13899        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13902        // (intrinsic_wo_chain:{ *:[v4f16] } 1748:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13903        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh,
13904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13906        GIR_EraseFromParent, /*InsnID*/0,
13907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13908        // GIR_Coverage, 1701,
13909        GIR_Done,
13910      // Label 808: @33908
13911      GIM_Try, /*On fail goto*//*Label 809*/ 33948, // Rule ID 1702 //
13912        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
13913        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
13914        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13915        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13918        // (intrinsic_wo_chain:{ *:[v8f16] } 1748:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13919        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh,
13920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13922        GIR_EraseFromParent, /*InsnID*/0,
13923        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13924        // GIR_Coverage, 1702,
13925        GIR_Done,
13926      // Label 809: @33948
13927      GIM_Try, /*On fail goto*//*Label 810*/ 33988, // Rule ID 1705 //
13928        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
13929        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesimc,
13930        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13931        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13934        // (intrinsic_wo_chain:{ *:[v16i8] } 1648:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
13935        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC,
13936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13938        GIR_EraseFromParent, /*InsnID*/0,
13939        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13940        // GIR_Coverage, 1705,
13941        GIR_Done,
13942      // Label 810: @33988
13943      GIM_Try, /*On fail goto*//*Label 811*/ 34028, // Rule ID 1706 //
13944        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
13945        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesmc,
13946        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13947        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13950        // (intrinsic_wo_chain:{ *:[v16i8] } 1649:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
13951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC,
13952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13954        GIR_EraseFromParent, /*InsnID*/0,
13955        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13956        // GIR_Coverage, 1706,
13957        GIR_Done,
13958      // Label 811: @34028
13959      GIM_Try, /*On fail goto*//*Label 812*/ 34078, // Rule ID 1864 //
13960        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
13961        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
13962        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13963        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
13965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
13966        // (intrinsic_wo_chain:{ *:[i32] } 1836:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
13967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16,
13968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
13970        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13971        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13972        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
13973        GIR_EraseFromParent, /*InsnID*/0,
13974        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13975        // GIR_Coverage, 1864,
13976        GIR_Done,
13977      // Label 812: @34078
13978      GIM_Try, /*On fail goto*//*Label 813*/ 34128, // Rule ID 2081 //
13979        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13980        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
13981        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13982        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13984        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13985        // (intrinsic_wo_chain:{ *:[i32] } 1836:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
13986        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16,
13987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13989        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13990        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13991        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
13992        GIR_EraseFromParent, /*InsnID*/0,
13993        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13994        // GIR_Coverage, 2081,
13995        GIR_Done,
13996      // Label 813: @34128
13997      GIM_Try, /*On fail goto*//*Label 814*/ 34175, // Rule ID 3684 //
13998        GIM_CheckFeatures, GIFBS_HasMVEInt,
13999        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp8,
14000        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s1,
14001        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
14003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14004        // (intrinsic_wo_chain:{ *:[v16i1] } 1594:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
14005        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP8,
14006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
14007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14008        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14009        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14010        GIR_EraseFromParent, /*InsnID*/0,
14011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14012        // GIR_Coverage, 3684,
14013        GIR_Done,
14014      // Label 814: @34175
14015      GIM_Try, /*On fail goto*//*Label 815*/ 34222, // Rule ID 3686 //
14016        GIM_CheckFeatures, GIFBS_HasMVEInt,
14017        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp16,
14018        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s1,
14019        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
14021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14022        // (intrinsic_wo_chain:{ *:[v8i1] } 1591:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
14023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP16,
14024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
14025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14026        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14027        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14028        GIR_EraseFromParent, /*InsnID*/0,
14029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14030        // GIR_Coverage, 3686,
14031        GIR_Done,
14032      // Label 815: @34222
14033      GIM_Try, /*On fail goto*//*Label 816*/ 34269, // Rule ID 3688 //
14034        GIM_CheckFeatures, GIFBS_HasMVEInt,
14035        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp32,
14036        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
14037        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
14039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14040        // (intrinsic_wo_chain:{ *:[v4i1] } 1592:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
14041        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP32,
14042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
14043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14044        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14045        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14046        GIR_EraseFromParent, /*InsnID*/0,
14047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14048        // GIR_Coverage, 3688,
14049        GIR_Done,
14050      // Label 816: @34269
14051      GIM_Try, /*On fail goto*//*Label 817*/ 34316, // Rule ID 3690 //
14052        GIM_CheckFeatures, GIFBS_HasMVEInt,
14053        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp64,
14054        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
14055        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
14057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14058        // (intrinsic_wo_chain:{ *:[v4i1] } 1593:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP64:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
14059        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP64,
14060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
14061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14062        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14063        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14064        GIR_EraseFromParent, /*InsnID*/0,
14065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14066        // GIR_Coverage, 3690,
14067        GIR_Done,
14068      // Label 817: @34316
14069      GIM_Try, /*On fail goto*//*Label 818*/ 34363, // Rule ID 614 //
14070        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
14071        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tt,
14072        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14074        // MIs[0] Rn
14075        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
14076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14077        // (intrinsic_wo_chain:{ *:[i32] } 1503:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
14078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TT,
14079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
14080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14081        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14082        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14083        GIR_EraseFromParent, /*InsnID*/0,
14084        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14085        // GIR_Coverage, 614,
14086        GIR_Done,
14087      // Label 818: @34363
14088      GIM_Try, /*On fail goto*//*Label 819*/ 34410, // Rule ID 615 //
14089        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
14090        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttt,
14091        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14093        // MIs[0] Rn
14094        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
14095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14096        // (intrinsic_wo_chain:{ *:[i32] } 1506:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
14097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTT,
14098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
14099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14100        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14101        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14102        GIR_EraseFromParent, /*InsnID*/0,
14103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14104        // GIR_Coverage, 615,
14105        GIR_Done,
14106      // Label 819: @34410
14107      GIM_Try, /*On fail goto*//*Label 820*/ 34457, // Rule ID 616 //
14108        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
14109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tta,
14110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14112        // MIs[0] Rn
14113        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
14114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14115        // (intrinsic_wo_chain:{ *:[i32] } 1504:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
14116        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTA,
14117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
14118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14119        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14120        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14121        GIR_EraseFromParent, /*InsnID*/0,
14122        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14123        // GIR_Coverage, 616,
14124        GIR_Done,
14125      // Label 820: @34457
14126      GIM_Try, /*On fail goto*//*Label 821*/ 34504, // Rule ID 617 //
14127        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
14128        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttat,
14129        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14131        // MIs[0] Rn
14132        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
14133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14134        // (intrinsic_wo_chain:{ *:[i32] } 1505:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
14135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTAT,
14136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
14137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14138        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14139        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14140        GIR_EraseFromParent, /*InsnID*/0,
14141        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14142        // GIR_Coverage, 617,
14143        GIR_Done,
14144      // Label 821: @34504
14145      GIM_Reject,
14146    // Label 691: @34505
14147    GIM_Try, /*On fail goto*//*Label 822*/ 54837,
14148      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
14149      GIM_Try, /*On fail goto*//*Label 823*/ 34572, // Rule ID 2099 //
14150        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
14151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
14152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
14158        // (intrinsic_wo_chain:{ *:[i32] } 1860:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
14159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16,
14160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
14163        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14164        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14165        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14166        GIR_EraseFromParent, /*InsnID*/0,
14167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14168        // GIR_Coverage, 2099,
14169        GIR_Done,
14170      // Label 823: @34572
14171      GIM_Try, /*On fail goto*//*Label 824*/ 34656, // Rule ID 111 //
14172        GIM_CheckFeatures, GIFBS_IsARM,
14173        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
14174        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14175        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14176        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14178        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14179        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14180        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14181        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14182        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14183        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14184        // MIs[1] Rm
14185        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
14187        GIM_CheckIsSafeToFold, /*InsnID*/1,
14188        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Rn)  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
14189        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
14190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
14192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
14193        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14194        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14195        GIR_EraseFromParent, /*InsnID*/0,
14196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14197        // GIR_Coverage, 111,
14198        GIR_Done,
14199      // Label 824: @34656
14200      GIM_Try, /*On fail goto*//*Label 825*/ 34740, // Rule ID 2117 //
14201        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
14202        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
14203        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14204        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14205        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14207        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14208        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14209        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14210        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14211        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14212        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14213        // MIs[1] Rm
14214        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
14216        GIM_CheckIsSafeToFold, /*InsnID*/1,
14217        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Rn)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
14218        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
14219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
14221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
14222        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14223        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14224        GIR_EraseFromParent, /*InsnID*/0,
14225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14226        // GIR_Coverage, 2117,
14227        GIR_Done,
14228      // Label 825: @34740
14229      GIM_Try, /*On fail goto*//*Label 826*/ 34824, // Rule ID 112 //
14230        GIM_CheckFeatures, GIFBS_IsARM,
14231        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
14232        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14233        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14234        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14237        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14238        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14239        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14240        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14241        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14242        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14243        // MIs[1] Rn
14244        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14245        GIM_CheckIsSafeToFold, /*InsnID*/1,
14246        // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
14247        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
14248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
14250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
14251        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14252        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14253        GIR_EraseFromParent, /*InsnID*/0,
14254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14255        // GIR_Coverage, 112,
14256        GIR_Done,
14257      // Label 826: @34824
14258      GIM_Try, /*On fail goto*//*Label 827*/ 34908, // Rule ID 2118 //
14259        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
14260        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
14261        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14262        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14263        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14266        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14267        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14268        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14269        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14270        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14271        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14272        // MIs[1] Rn
14273        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14274        GIM_CheckIsSafeToFold, /*InsnID*/1,
14275        // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
14276        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
14277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
14279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
14280        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14281        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14282        GIR_EraseFromParent, /*InsnID*/0,
14283        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14284        // GIR_Coverage, 2118,
14285        GIR_Done,
14286      // Label 827: @34908
14287      GIM_Try, /*On fail goto*//*Label 828*/ 34992, // Rule ID 4151 //
14288        GIM_CheckFeatures, GIFBS_IsARM,
14289        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
14290        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14291        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14292        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14295        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14296        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14297        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14298        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14299        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14300        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14301        // MIs[1] Rm
14302        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14303        GIM_CheckIsSafeToFold, /*InsnID*/1,
14304        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm))  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
14305        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
14306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
14308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14309        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14310        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14311        GIR_EraseFromParent, /*InsnID*/0,
14312        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14313        // GIR_Coverage, 4151,
14314        GIR_Done,
14315      // Label 828: @34992
14316      GIM_Try, /*On fail goto*//*Label 829*/ 35076, // Rule ID 4405 //
14317        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
14318        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
14319        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14320        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14321        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14324        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14325        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
14326        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
14327        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
14328        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14329        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14330        // MIs[1] Rm
14331        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
14332        GIM_CheckIsSafeToFold, /*InsnID*/1,
14333        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
14334        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
14335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
14337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
14338        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14339        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14340        GIR_EraseFromParent, /*InsnID*/0,
14341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14342        // GIR_Coverage, 4405,
14343        GIR_Done,
14344      // Label 829: @35076
14345      GIM_Try, /*On fail goto*//*Label 830*/ 35145, // Rule ID 1894 //
14346        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
14347        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
14348        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14349        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14350        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14353        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14354        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14355        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
14356        // MIs[1] Operand 1
14357        // No operand predicates
14358        GIM_CheckIsSafeToFold, /*InsnID*/1,
14359        // (intrinsic_wo_chain:{ *:[i32] } 1855:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
14360        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
14361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14362        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
14363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
14364        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14365        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14366        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14367        GIR_EraseFromParent, /*InsnID*/0,
14368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14369        // GIR_Coverage, 1894,
14370        GIR_Done,
14371      // Label 830: @35145
14372      GIM_Try, /*On fail goto*//*Label 831*/ 35211, // Rule ID 1898 //
14373        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
14374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
14375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14376        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14377        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14380        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14381        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14382        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
14383        // MIs[1] Operand 1
14384        // No operand predicates
14385        GIM_CheckIsSafeToFold, /*InsnID*/1,
14386        // (intrinsic_wo_chain:{ *:[i32] } 1856:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
14387        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
14388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14389        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
14390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
14391        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14392        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14393        GIR_EraseFromParent, /*InsnID*/0,
14394        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14395        // GIR_Coverage, 1898,
14396        GIR_Done,
14397      // Label 831: @35211
14398      GIM_Try, /*On fail goto*//*Label 832*/ 35280, // Rule ID 2130 //
14399        GIM_CheckFeatures, GIFBS_IsThumb2,
14400        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
14401        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14402        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14403        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
14406        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14407        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14408        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
14409        // MIs[1] Operand 1
14410        // No operand predicates
14411        GIM_CheckIsSafeToFold, /*InsnID*/1,
14412        // (intrinsic_wo_chain:{ *:[i32] } 1855:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
14413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
14414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14415        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
14416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
14417        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14418        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14419        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14420        GIR_EraseFromParent, /*InsnID*/0,
14421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14422        // GIR_Coverage, 2130,
14423        GIR_Done,
14424      // Label 832: @35280
14425      GIM_Try, /*On fail goto*//*Label 833*/ 35346, // Rule ID 2132 //
14426        GIM_CheckFeatures, GIFBS_IsThumb2,
14427        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
14428        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14429        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14430        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
14433        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14434        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14435        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
14436        // MIs[1] Operand 1
14437        // No operand predicates
14438        GIM_CheckIsSafeToFold, /*InsnID*/1,
14439        // (intrinsic_wo_chain:{ *:[i32] } 1856:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
14440        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
14441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14442        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
14443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
14444        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14445        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14446        GIR_EraseFromParent, /*InsnID*/0,
14447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14448        // GIR_Coverage, 2132,
14449        GIR_Done,
14450      // Label 833: @35346
14451      GIM_Try, /*On fail goto*//*Label 834*/ 35424, // Rule ID 3326 //
14452        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
14453        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14454        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14455        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
14457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
14458        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14459        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14460        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
14461        // MIs[1] Operand 1
14462        // No operand predicates
14463        GIM_CheckIsSafeToFold, /*InsnID*/1,
14464        // (intrinsic_wo_chain:{ *:[v16i8] } 1618:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
14465        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14466        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14467        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
14468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms8,
14469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
14470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
14471        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14472        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14473        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14474        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14475        GIR_EraseFromParent, /*InsnID*/0,
14476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14477        // GIR_Coverage, 3326,
14478        GIR_Done,
14479      // Label 834: @35424
14480      GIM_Try, /*On fail goto*//*Label 835*/ 35502, // Rule ID 3328 //
14481        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
14482        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14483        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14484        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
14486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
14487        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14488        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14489        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
14490        // MIs[1] Operand 1
14491        // No operand predicates
14492        GIM_CheckIsSafeToFold, /*InsnID*/1,
14493        // (intrinsic_wo_chain:{ *:[v8i16] } 1618:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
14494        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14495        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14496        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
14497        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms16,
14498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
14499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
14500        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14501        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14502        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14503        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14504        GIR_EraseFromParent, /*InsnID*/0,
14505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14506        // GIR_Coverage, 3328,
14507        GIR_Done,
14508      // Label 835: @35502
14509      GIM_Try, /*On fail goto*//*Label 836*/ 35580, // Rule ID 3330 //
14510        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
14511        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14512        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14513        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
14515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
14516        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14517        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14518        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
14519        // MIs[1] Operand 1
14520        // No operand predicates
14521        GIM_CheckIsSafeToFold, /*InsnID*/1,
14522        // (intrinsic_wo_chain:{ *:[v4i32] } 1618:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
14523        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14524        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14525        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
14526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms32,
14527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
14528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
14529        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14530        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14531        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14532        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14533        GIR_EraseFromParent, /*InsnID*/0,
14534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14535        // GIR_Coverage, 3330,
14536        GIR_Done,
14537      // Label 836: @35580
14538      GIM_Try, /*On fail goto*//*Label 837*/ 35643, // Rule ID 1640 //
14539        GIM_CheckFeatures, GIFBS_HasNEON,
14540        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
14541        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14542        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14543        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14546        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14547        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14548        // MIs[1] Operand 1
14549        // No operand predicates
14550        GIM_CheckIsSafeToFold, /*InsnID*/1,
14551        // (intrinsic_wo_chain:{ *:[v2i32] } 1673:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
14553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14555        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14556        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14557        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14558        GIR_EraseFromParent, /*InsnID*/0,
14559        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14560        // GIR_Coverage, 1640,
14561        GIR_Done,
14562      // Label 837: @35643
14563      GIM_Try, /*On fail goto*//*Label 838*/ 35706, // Rule ID 1641 //
14564        GIM_CheckFeatures, GIFBS_HasNEON,
14565        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
14566        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14567        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14568        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14571        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14572        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14573        // MIs[1] Operand 1
14574        // No operand predicates
14575        GIM_CheckIsSafeToFold, /*InsnID*/1,
14576        // (intrinsic_wo_chain:{ *:[v2i32] } 1674:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
14578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14580        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14581        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14582        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14583        GIR_EraseFromParent, /*InsnID*/0,
14584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14585        // GIR_Coverage, 1641,
14586        GIR_Done,
14587      // Label 838: @35706
14588      GIM_Try, /*On fail goto*//*Label 839*/ 35769, // Rule ID 1642 //
14589        GIM_CheckFeatures, GIFBS_HasNEON,
14590        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
14591        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14592        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14593        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14596        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14597        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14598        // MIs[1] Operand 1
14599        // No operand predicates
14600        GIM_CheckIsSafeToFold, /*InsnID*/1,
14601        // (intrinsic_wo_chain:{ *:[v2f32] } 1676:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14602        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
14603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14605        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14606        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14607        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14608        GIR_EraseFromParent, /*InsnID*/0,
14609        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14610        // GIR_Coverage, 1642,
14611        GIR_Done,
14612      // Label 839: @35769
14613      GIM_Try, /*On fail goto*//*Label 840*/ 35832, // Rule ID 1643 //
14614        GIM_CheckFeatures, GIFBS_HasNEON,
14615        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
14616        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14617        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14618        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14621        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14622        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14623        // MIs[1] Operand 1
14624        // No operand predicates
14625        GIM_CheckIsSafeToFold, /*InsnID*/1,
14626        // (intrinsic_wo_chain:{ *:[v2f32] } 1677:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
14628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14630        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14631        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14632        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14633        GIR_EraseFromParent, /*InsnID*/0,
14634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14635        // GIR_Coverage, 1643,
14636        GIR_Done,
14637      // Label 840: @35832
14638      GIM_Try, /*On fail goto*//*Label 841*/ 35895, // Rule ID 1644 //
14639        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
14641        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14642        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14643        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14646        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14647        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14648        // MIs[1] Operand 1
14649        // No operand predicates
14650        GIM_CheckIsSafeToFold, /*InsnID*/1,
14651        // (intrinsic_wo_chain:{ *:[v4i16] } 1673:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14652        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
14653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14655        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14656        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14657        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14658        GIR_EraseFromParent, /*InsnID*/0,
14659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14660        // GIR_Coverage, 1644,
14661        GIR_Done,
14662      // Label 841: @35895
14663      GIM_Try, /*On fail goto*//*Label 842*/ 35958, // Rule ID 1645 //
14664        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14665        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
14666        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14667        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14668        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14671        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14672        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14673        // MIs[1] Operand 1
14674        // No operand predicates
14675        GIM_CheckIsSafeToFold, /*InsnID*/1,
14676        // (intrinsic_wo_chain:{ *:[v4i16] } 1674:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
14678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14680        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14681        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14682        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14683        GIR_EraseFromParent, /*InsnID*/0,
14684        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14685        // GIR_Coverage, 1645,
14686        GIR_Done,
14687      // Label 842: @35958
14688      GIM_Try, /*On fail goto*//*Label 843*/ 36021, // Rule ID 1646 //
14689        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14690        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
14691        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14692        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14693        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14696        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14697        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14698        // MIs[1] Operand 1
14699        // No operand predicates
14700        GIM_CheckIsSafeToFold, /*InsnID*/1,
14701        // (intrinsic_wo_chain:{ *:[v4f16] } 1676:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14702        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
14703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14705        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14706        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14707        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14708        GIR_EraseFromParent, /*InsnID*/0,
14709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14710        // GIR_Coverage, 1646,
14711        GIR_Done,
14712      // Label 843: @36021
14713      GIM_Try, /*On fail goto*//*Label 844*/ 36084, // Rule ID 1647 //
14714        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14715        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
14716        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14717        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14718        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14721        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14722        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14723        // MIs[1] Operand 1
14724        // No operand predicates
14725        GIM_CheckIsSafeToFold, /*InsnID*/1,
14726        // (intrinsic_wo_chain:{ *:[v4f16] } 1677:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
14728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14730        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14731        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14732        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14733        GIR_EraseFromParent, /*InsnID*/0,
14734        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14735        // GIR_Coverage, 1647,
14736        GIR_Done,
14737      // Label 844: @36084
14738      GIM_Try, /*On fail goto*//*Label 845*/ 36147, // Rule ID 1648 //
14739        GIM_CheckFeatures, GIFBS_HasNEON,
14740        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
14741        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14742        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14743        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14746        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14747        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14748        // MIs[1] Operand 1
14749        // No operand predicates
14750        GIM_CheckIsSafeToFold, /*InsnID*/1,
14751        // (intrinsic_wo_chain:{ *:[v4i32] } 1673:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14752        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
14753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14755        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14756        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14757        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14758        GIR_EraseFromParent, /*InsnID*/0,
14759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14760        // GIR_Coverage, 1648,
14761        GIR_Done,
14762      // Label 845: @36147
14763      GIM_Try, /*On fail goto*//*Label 846*/ 36210, // Rule ID 1649 //
14764        GIM_CheckFeatures, GIFBS_HasNEON,
14765        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
14766        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14767        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14771        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14772        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14773        // MIs[1] Operand 1
14774        // No operand predicates
14775        GIM_CheckIsSafeToFold, /*InsnID*/1,
14776        // (intrinsic_wo_chain:{ *:[v4i32] } 1674:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14777        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
14778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14780        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14781        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14782        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14783        GIR_EraseFromParent, /*InsnID*/0,
14784        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14785        // GIR_Coverage, 1649,
14786        GIR_Done,
14787      // Label 846: @36210
14788      GIM_Try, /*On fail goto*//*Label 847*/ 36273, // Rule ID 1650 //
14789        GIM_CheckFeatures, GIFBS_HasNEON,
14790        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
14791        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14792        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14793        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14796        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14797        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14798        // MIs[1] Operand 1
14799        // No operand predicates
14800        GIM_CheckIsSafeToFold, /*InsnID*/1,
14801        // (intrinsic_wo_chain:{ *:[v4f32] } 1676:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
14803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14805        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14806        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14807        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14808        GIR_EraseFromParent, /*InsnID*/0,
14809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14810        // GIR_Coverage, 1650,
14811        GIR_Done,
14812      // Label 847: @36273
14813      GIM_Try, /*On fail goto*//*Label 848*/ 36336, // Rule ID 1651 //
14814        GIM_CheckFeatures, GIFBS_HasNEON,
14815        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
14816        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14817        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14821        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14822        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14823        // MIs[1] Operand 1
14824        // No operand predicates
14825        GIM_CheckIsSafeToFold, /*InsnID*/1,
14826        // (intrinsic_wo_chain:{ *:[v4f32] } 1677:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14827        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
14828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14830        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14831        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14832        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14833        GIR_EraseFromParent, /*InsnID*/0,
14834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14835        // GIR_Coverage, 1651,
14836        GIR_Done,
14837      // Label 848: @36336
14838      GIM_Try, /*On fail goto*//*Label 849*/ 36399, // Rule ID 1652 //
14839        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14840        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
14841        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14842        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14843        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14846        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14847        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14848        // MIs[1] Operand 1
14849        // No operand predicates
14850        GIM_CheckIsSafeToFold, /*InsnID*/1,
14851        // (intrinsic_wo_chain:{ *:[v8i16] } 1673:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
14853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14855        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14857        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14858        GIR_EraseFromParent, /*InsnID*/0,
14859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14860        // GIR_Coverage, 1652,
14861        GIR_Done,
14862      // Label 849: @36399
14863      GIM_Try, /*On fail goto*//*Label 850*/ 36462, // Rule ID 1653 //
14864        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
14866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14871        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14872        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14873        // MIs[1] Operand 1
14874        // No operand predicates
14875        GIM_CheckIsSafeToFold, /*InsnID*/1,
14876        // (intrinsic_wo_chain:{ *:[v8i16] } 1674:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14877        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
14878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14880        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14881        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14882        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14883        GIR_EraseFromParent, /*InsnID*/0,
14884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14885        // GIR_Coverage, 1653,
14886        GIR_Done,
14887      // Label 850: @36462
14888      GIM_Try, /*On fail goto*//*Label 851*/ 36525, // Rule ID 1654 //
14889        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14890        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
14891        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14892        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14893        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14896        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14897        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14898        // MIs[1] Operand 1
14899        // No operand predicates
14900        GIM_CheckIsSafeToFold, /*InsnID*/1,
14901        // (intrinsic_wo_chain:{ *:[v8f16] } 1676:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14902        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
14903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14905        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14906        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14907        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14908        GIR_EraseFromParent, /*InsnID*/0,
14909        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14910        // GIR_Coverage, 1654,
14911        GIR_Done,
14912      // Label 851: @36525
14913      GIM_Try, /*On fail goto*//*Label 852*/ 36588, // Rule ID 1655 //
14914        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14915        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
14916        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14917        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14918        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14921        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14922        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14923        // MIs[1] Operand 1
14924        // No operand predicates
14925        GIM_CheckIsSafeToFold, /*InsnID*/1,
14926        // (intrinsic_wo_chain:{ *:[v8f16] } 1677:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
14927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
14928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14930        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
14931        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14932        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14933        GIR_EraseFromParent, /*InsnID*/0,
14934        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14935        // GIR_Coverage, 1655,
14936        GIR_Done,
14937      // Label 852: @36588
14938      GIM_Try, /*On fail goto*//*Label 853*/ 36651, // Rule ID 1713 //
14939        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
14940        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqshl,
14941        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14942        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14943        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14946        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14947        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14948        // MIs[1] Operand 1
14949        // No operand predicates
14950        GIM_CheckIsSafeToFold, /*InsnID*/1,
14951        // (intrinsic_wo_chain:{ *:[i32] } 1569:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
14952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQSHL,
14953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
14954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
14955        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14956        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14957        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14958        GIR_EraseFromParent, /*InsnID*/0,
14959        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14960        // GIR_Coverage, 1713,
14961        GIR_Done,
14962      // Label 853: @36651
14963      GIM_Try, /*On fail goto*//*Label 854*/ 36714, // Rule ID 1714 //
14964        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
14965        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_srshr,
14966        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14967        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14968        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14971        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14972        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14973        // MIs[1] Operand 1
14974        // No operand predicates
14975        GIM_CheckIsSafeToFold, /*InsnID*/1,
14976        // (intrinsic_wo_chain:{ *:[i32] } 1571:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
14977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SRSHR,
14978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
14979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
14980        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14981        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14982        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
14983        GIR_EraseFromParent, /*InsnID*/0,
14984        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14985        // GIR_Coverage, 1714,
14986        GIR_Done,
14987      // Label 854: @36714
14988      GIM_Try, /*On fail goto*//*Label 855*/ 36777, // Rule ID 1715 //
14989        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
14990        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqshl,
14991        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14992        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14993        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
14994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14996        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14997        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14998        // MIs[1] Operand 1
14999        // No operand predicates
15000        GIM_CheckIsSafeToFold, /*InsnID*/1,
15001        // (intrinsic_wo_chain:{ *:[i32] } 1576:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
15002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQSHL,
15003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
15004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
15005        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15008        GIR_EraseFromParent, /*InsnID*/0,
15009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15010        // GIR_Coverage, 1715,
15011        GIR_Done,
15012      // Label 855: @36777
15013      GIM_Try, /*On fail goto*//*Label 856*/ 36840, // Rule ID 1716 //
15014        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
15015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_urshr,
15016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15021        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
15022        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
15023        // MIs[1] Operand 1
15024        // No operand predicates
15025        GIM_CheckIsSafeToFold, /*InsnID*/1,
15026        // (intrinsic_wo_chain:{ *:[i32] } 1578:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
15027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_URSHR,
15028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
15029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
15030        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15031        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15032        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15033        GIR_EraseFromParent, /*InsnID*/0,
15034        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15035        // GIR_Coverage, 1716,
15036        GIR_Done,
15037      // Label 856: @36840
15038      GIM_Try, /*On fail goto*//*Label 857*/ 36899, // Rule ID 107 //
15039        GIM_CheckFeatures, GIFBS_IsARM,
15040        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
15041        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15042        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15043        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15047        // (intrinsic_wo_chain:{ *:[i32] } 1780:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
15049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15052        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15053        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15054        GIR_EraseFromParent, /*InsnID*/0,
15055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15056        // GIR_Coverage, 107,
15057        GIR_Done,
15058      // Label 857: @36899
15059      GIM_Try, /*On fail goto*//*Label 858*/ 36958, // Rule ID 108 //
15060        GIM_CheckFeatures, GIFBS_IsARM,
15061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
15062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15068        // (intrinsic_wo_chain:{ *:[i32] } 1779:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
15070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15073        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15074        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15075        GIR_EraseFromParent, /*InsnID*/0,
15076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15077        // GIR_Coverage, 108,
15078        GIR_Done,
15079      // Label 858: @36958
15080      GIM_Try, /*On fail goto*//*Label 859*/ 37017, // Rule ID 109 //
15081        GIM_CheckFeatures, GIFBS_IsARM,
15082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
15083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15085        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15089        // (intrinsic_wo_chain:{ *:[i32] } 1784:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
15091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15094        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15095        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15096        GIR_EraseFromParent, /*InsnID*/0,
15097        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15098        // GIR_Coverage, 109,
15099        GIR_Done,
15100      // Label 859: @37017
15101      GIM_Try, /*On fail goto*//*Label 860*/ 37076, // Rule ID 110 //
15102        GIM_CheckFeatures, GIFBS_IsARM,
15103        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
15104        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15105        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15110        // (intrinsic_wo_chain:{ *:[i32] } 1785:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
15112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15115        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15116        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15117        GIR_EraseFromParent, /*InsnID*/0,
15118        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15119        // GIR_Coverage, 110,
15120        GIR_Done,
15121      // Label 860: @37076
15122      GIM_Try, /*On fail goto*//*Label 861*/ 37135, // Rule ID 113 //
15123        GIM_CheckFeatures, GIFBS_IsARM,
15124        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
15125        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15126        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15127        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15131        // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
15132        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
15133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
15136        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15137        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15138        GIR_EraseFromParent, /*InsnID*/0,
15139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15140        // GIR_Coverage, 113,
15141        GIR_Done,
15142      // Label 861: @37135
15143      GIM_Try, /*On fail goto*//*Label 862*/ 37194, // Rule ID 114 //
15144        GIM_CheckFeatures, GIFBS_IsARM,
15145        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
15146        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15147        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15148        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15152        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
15153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
15154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
15157        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15158        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15159        GIR_EraseFromParent, /*InsnID*/0,
15160        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15161        // GIR_Coverage, 114,
15162        GIR_Done,
15163      // Label 862: @37194
15164      GIM_Try, /*On fail goto*//*Label 863*/ 37253, // Rule ID 115 //
15165        GIM_CheckFeatures, GIFBS_IsARM,
15166        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
15167        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15168        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15169        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15173        // (intrinsic_wo_chain:{ *:[i32] } 1847:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
15175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15178        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15179        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15180        GIR_EraseFromParent, /*InsnID*/0,
15181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15182        // GIR_Coverage, 115,
15183        GIR_Done,
15184      // Label 863: @37253
15185      GIM_Try, /*On fail goto*//*Label 864*/ 37312, // Rule ID 116 //
15186        GIM_CheckFeatures, GIFBS_IsARM,
15187        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
15188        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15189        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15190        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15194        // (intrinsic_wo_chain:{ *:[i32] } 1848:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
15196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15199        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15200        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15201        GIR_EraseFromParent, /*InsnID*/0,
15202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15203        // GIR_Coverage, 116,
15204        GIR_Done,
15205      // Label 864: @37312
15206      GIM_Try, /*On fail goto*//*Label 865*/ 37371, // Rule ID 117 //
15207        GIM_CheckFeatures, GIFBS_IsARM,
15208        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
15209        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15210        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15211        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15215        // (intrinsic_wo_chain:{ *:[i32] } 1851:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
15217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15220        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15221        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15222        GIR_EraseFromParent, /*InsnID*/0,
15223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15224        // GIR_Coverage, 117,
15225        GIR_Done,
15226      // Label 865: @37371
15227      GIM_Try, /*On fail goto*//*Label 866*/ 37430, // Rule ID 118 //
15228        GIM_CheckFeatures, GIFBS_IsARM,
15229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
15230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15236        // (intrinsic_wo_chain:{ *:[i32] } 1852:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
15238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15241        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15242        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15243        GIR_EraseFromParent, /*InsnID*/0,
15244        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15245        // GIR_Coverage, 118,
15246        GIR_Done,
15247      // Label 866: @37430
15248      GIM_Try, /*On fail goto*//*Label 867*/ 37489, // Rule ID 119 //
15249        GIM_CheckFeatures, GIFBS_IsARM,
15250        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
15251        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15252        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15253        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15257        // (intrinsic_wo_chain:{ *:[i32] } 1781:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15258        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
15259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15262        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15263        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15264        GIR_EraseFromParent, /*InsnID*/0,
15265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15266        // GIR_Coverage, 119,
15267        GIR_Done,
15268      // Label 867: @37489
15269      GIM_Try, /*On fail goto*//*Label 868*/ 37548, // Rule ID 120 //
15270        GIM_CheckFeatures, GIFBS_IsARM,
15271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
15272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15278        // (intrinsic_wo_chain:{ *:[i32] } 1782:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
15280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15283        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15284        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15285        GIR_EraseFromParent, /*InsnID*/0,
15286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15287        // GIR_Coverage, 120,
15288        GIR_Done,
15289      // Label 868: @37548
15290      GIM_Try, /*On fail goto*//*Label 869*/ 37607, // Rule ID 121 //
15291        GIM_CheckFeatures, GIFBS_IsARM,
15292        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
15293        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15294        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15295        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15299        // (intrinsic_wo_chain:{ *:[i32] } 1849:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15300        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
15301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15304        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15305        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15306        GIR_EraseFromParent, /*InsnID*/0,
15307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15308        // GIR_Coverage, 121,
15309        GIR_Done,
15310      // Label 869: @37607
15311      GIM_Try, /*On fail goto*//*Label 870*/ 37666, // Rule ID 122 //
15312        GIM_CheckFeatures, GIFBS_IsARM,
15313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
15314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15316        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15320        // (intrinsic_wo_chain:{ *:[i32] } 1850:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
15322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15325        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15326        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15327        GIR_EraseFromParent, /*InsnID*/0,
15328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15329        // GIR_Coverage, 122,
15330        GIR_Done,
15331      // Label 870: @37666
15332      GIM_Try, /*On fail goto*//*Label 871*/ 37725, // Rule ID 135 //
15333        GIM_CheckFeatures, GIFBS_IsARM,
15334        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
15335        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15336        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15337        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15341        // (intrinsic_wo_chain:{ *:[i32] } 1793:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15342        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
15343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15346        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15347        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15348        GIR_EraseFromParent, /*InsnID*/0,
15349        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15350        // GIR_Coverage, 135,
15351        GIR_Done,
15352      // Label 871: @37725
15353      GIM_Try, /*On fail goto*//*Label 872*/ 37784, // Rule ID 136 //
15354        GIM_CheckFeatures, GIFBS_IsARM,
15355        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
15356        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15357        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15358        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15362        // (intrinsic_wo_chain:{ *:[i32] } 1791:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
15364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15367        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15368        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15369        GIR_EraseFromParent, /*InsnID*/0,
15370        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15371        // GIR_Coverage, 136,
15372        GIR_Done,
15373      // Label 872: @37784
15374      GIM_Try, /*On fail goto*//*Label 873*/ 37843, // Rule ID 137 //
15375        GIM_CheckFeatures, GIFBS_IsARM,
15376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
15377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15378        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15379        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15383        // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
15385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15388        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15389        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15390        GIR_EraseFromParent, /*InsnID*/0,
15391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15392        // GIR_Coverage, 137,
15393        GIR_Done,
15394      // Label 873: @37843
15395      GIM_Try, /*On fail goto*//*Label 874*/ 37902, // Rule ID 138 //
15396        GIM_CheckFeatures, GIFBS_IsARM,
15397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
15398        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15400        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15404        // (intrinsic_wo_chain:{ *:[i32] } 1794:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15405        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
15406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15409        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15410        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15411        GIR_EraseFromParent, /*InsnID*/0,
15412        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15413        // GIR_Coverage, 138,
15414        GIR_Done,
15415      // Label 874: @37902
15416      GIM_Try, /*On fail goto*//*Label 875*/ 37961, // Rule ID 139 //
15417        GIM_CheckFeatures, GIFBS_IsARM,
15418        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
15419        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15420        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15421        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15425        // (intrinsic_wo_chain:{ *:[i32] } 1795:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
15427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15430        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15431        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15432        GIR_EraseFromParent, /*InsnID*/0,
15433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15434        // GIR_Coverage, 139,
15435        GIR_Done,
15436      // Label 875: @37961
15437      GIM_Try, /*On fail goto*//*Label 876*/ 38020, // Rule ID 140 //
15438        GIM_CheckFeatures, GIFBS_IsARM,
15439        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
15440        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15441        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15442        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15446        // (intrinsic_wo_chain:{ *:[i32] } 1796:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15447        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
15448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15451        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15452        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15453        GIR_EraseFromParent, /*InsnID*/0,
15454        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15455        // GIR_Coverage, 140,
15456        GIR_Done,
15457      // Label 876: @38020
15458      GIM_Try, /*On fail goto*//*Label 877*/ 38079, // Rule ID 141 //
15459        GIM_CheckFeatures, GIFBS_IsARM,
15460        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
15461        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15462        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15463        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15467        // (intrinsic_wo_chain:{ *:[i32] } 1842:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
15469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15472        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15473        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15474        GIR_EraseFromParent, /*InsnID*/0,
15475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15476        // GIR_Coverage, 141,
15477        GIR_Done,
15478      // Label 877: @38079
15479      GIM_Try, /*On fail goto*//*Label 878*/ 38138, // Rule ID 142 //
15480        GIM_CheckFeatures, GIFBS_IsARM,
15481        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
15482        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15483        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15484        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15488        // (intrinsic_wo_chain:{ *:[i32] } 1840:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15489        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
15490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15493        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15494        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15495        GIR_EraseFromParent, /*InsnID*/0,
15496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15497        // GIR_Coverage, 142,
15498        GIR_Done,
15499      // Label 878: @38138
15500      GIM_Try, /*On fail goto*//*Label 879*/ 38197, // Rule ID 143 //
15501        GIM_CheckFeatures, GIFBS_IsARM,
15502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
15503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15509        // (intrinsic_wo_chain:{ *:[i32] } 1841:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
15511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15514        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15515        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15516        GIR_EraseFromParent, /*InsnID*/0,
15517        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15518        // GIR_Coverage, 143,
15519        GIR_Done,
15520      // Label 879: @38197
15521      GIM_Try, /*On fail goto*//*Label 880*/ 38256, // Rule ID 144 //
15522        GIM_CheckFeatures, GIFBS_IsARM,
15523        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
15524        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15525        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15526        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15530        // (intrinsic_wo_chain:{ *:[i32] } 1843:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15531        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
15532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15535        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15536        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15537        GIR_EraseFromParent, /*InsnID*/0,
15538        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15539        // GIR_Coverage, 144,
15540        GIR_Done,
15541      // Label 880: @38256
15542      GIM_Try, /*On fail goto*//*Label 881*/ 38315, // Rule ID 145 //
15543        GIM_CheckFeatures, GIFBS_IsARM,
15544        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
15545        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15546        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15547        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15551        // (intrinsic_wo_chain:{ *:[i32] } 1844:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
15553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15556        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15557        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15558        GIR_EraseFromParent, /*InsnID*/0,
15559        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15560        // GIR_Coverage, 145,
15561        GIR_Done,
15562      // Label 881: @38315
15563      GIM_Try, /*On fail goto*//*Label 882*/ 38374, // Rule ID 146 //
15564        GIM_CheckFeatures, GIFBS_IsARM,
15565        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
15566        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15567        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15568        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15572        // (intrinsic_wo_chain:{ *:[i32] } 1845:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15573        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
15574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15577        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15578        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15579        GIR_EraseFromParent, /*InsnID*/0,
15580        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15581        // GIR_Coverage, 146,
15582        GIR_Done,
15583      // Label 882: @38374
15584      GIM_Try, /*On fail goto*//*Label 883*/ 38433, // Rule ID 147 //
15585        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
15586        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
15587        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15588        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15589        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
15591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
15592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
15593        // (intrinsic_wo_chain:{ *:[i32] } 1853:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
15594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
15595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15599        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15600        GIR_EraseFromParent, /*InsnID*/0,
15601        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15602        // GIR_Coverage, 147,
15603        GIR_Done,
15604      // Label 883: @38433
15605      GIM_Try, /*On fail goto*//*Label 884*/ 38485, // Rule ID 206 //
15606        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15607        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
15608        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15609        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15610        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15614        // (intrinsic_wo_chain:{ *:[i32] } 1507:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
15616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15619        GIR_EraseFromParent, /*InsnID*/0,
15620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15621        // GIR_Coverage, 206,
15622        GIR_Done,
15623      // Label 884: @38485
15624      GIM_Try, /*On fail goto*//*Label 885*/ 38537, // Rule ID 207 //
15625        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15626        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
15627        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15628        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15629        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15633        // (intrinsic_wo_chain:{ *:[i32] } 1508:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
15635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15638        GIR_EraseFromParent, /*InsnID*/0,
15639        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15640        // GIR_Coverage, 207,
15641        GIR_Done,
15642      // Label 885: @38537
15643      GIM_Try, /*On fail goto*//*Label 886*/ 38589, // Rule ID 208 //
15644        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15645        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
15646        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15647        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15648        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15652        // (intrinsic_wo_chain:{ *:[i32] } 1511:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15653        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
15654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15657        GIR_EraseFromParent, /*InsnID*/0,
15658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15659        // GIR_Coverage, 208,
15660        GIR_Done,
15661      // Label 886: @38589
15662      GIM_Try, /*On fail goto*//*Label 887*/ 38641, // Rule ID 209 //
15663        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15664        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
15665        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15666        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15667        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15671        // (intrinsic_wo_chain:{ *:[i32] } 1509:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
15673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15676        GIR_EraseFromParent, /*InsnID*/0,
15677        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15678        // GIR_Coverage, 209,
15679        GIR_Done,
15680      // Label 887: @38641
15681      GIM_Try, /*On fail goto*//*Label 888*/ 38693, // Rule ID 210 //
15682        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15683        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
15684        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15685        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15686        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15690        // (intrinsic_wo_chain:{ *:[i32] } 1512:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15691        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
15692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15695        GIR_EraseFromParent, /*InsnID*/0,
15696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15697        // GIR_Coverage, 210,
15698        GIR_Done,
15699      // Label 888: @38693
15700      GIM_Try, /*On fail goto*//*Label 889*/ 38745, // Rule ID 211 //
15701        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
15702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
15703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15709        // (intrinsic_wo_chain:{ *:[i32] } 1510:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
15710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
15711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15714        GIR_EraseFromParent, /*InsnID*/0,
15715        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15716        // GIR_Coverage, 211,
15717        GIR_Done,
15718      // Label 889: @38745
15719      GIM_Try, /*On fail goto*//*Label 890*/ 38804, // Rule ID 438 //
15720        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15721        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
15722        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15723        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15724        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15728        // (intrinsic_wo_chain:{ *:[i32] } 1779:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15729        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
15730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15733        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15734        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15735        GIR_EraseFromParent, /*InsnID*/0,
15736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15737        // GIR_Coverage, 438,
15738        GIR_Done,
15739      // Label 890: @38804
15740      GIM_Try, /*On fail goto*//*Label 891*/ 38863, // Rule ID 439 //
15741        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15742        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
15743        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15744        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15745        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15749        // (intrinsic_wo_chain:{ *:[i32] } 1780:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
15751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15754        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15755        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15756        GIR_EraseFromParent, /*InsnID*/0,
15757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15758        // GIR_Coverage, 439,
15759        GIR_Done,
15760      // Label 891: @38863
15761      GIM_Try, /*On fail goto*//*Label 892*/ 38922, // Rule ID 440 //
15762        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15763        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
15764        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15765        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15766        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15770        // (intrinsic_wo_chain:{ *:[i32] } 1781:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15771        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
15772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15775        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15776        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15777        GIR_EraseFromParent, /*InsnID*/0,
15778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15779        // GIR_Coverage, 440,
15780        GIR_Done,
15781      // Label 892: @38922
15782      GIM_Try, /*On fail goto*//*Label 893*/ 38981, // Rule ID 441 //
15783        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
15785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15787        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15791        // (intrinsic_wo_chain:{ *:[i32] } 1852:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
15793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15796        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15797        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15798        GIR_EraseFromParent, /*InsnID*/0,
15799        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15800        // GIR_Coverage, 441,
15801        GIR_Done,
15802      // Label 893: @38981
15803      GIM_Try, /*On fail goto*//*Label 894*/ 39040, // Rule ID 442 //
15804        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15805        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
15806        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15807        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15808        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15812        // (intrinsic_wo_chain:{ *:[i32] } 1782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15813        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
15814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15817        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15818        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15819        GIR_EraseFromParent, /*InsnID*/0,
15820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15821        // GIR_Coverage, 442,
15822        GIR_Done,
15823      // Label 894: @39040
15824      GIM_Try, /*On fail goto*//*Label 895*/ 39099, // Rule ID 443 //
15825        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
15827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15829        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15833        // (intrinsic_wo_chain:{ *:[i32] } 1784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15834        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
15835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15839        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15840        GIR_EraseFromParent, /*InsnID*/0,
15841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15842        // GIR_Coverage, 443,
15843        GIR_Done,
15844      // Label 895: @39099
15845      GIM_Try, /*On fail goto*//*Label 896*/ 39158, // Rule ID 444 //
15846        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15847        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
15848        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15849        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15850        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15854        // (intrinsic_wo_chain:{ *:[i32] } 1785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
15856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15859        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15860        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15861        GIR_EraseFromParent, /*InsnID*/0,
15862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15863        // GIR_Coverage, 444,
15864        GIR_Done,
15865      // Label 896: @39158
15866      GIM_Try, /*On fail goto*//*Label 897*/ 39217, // Rule ID 445 //
15867        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15868        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
15869        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15870        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15871        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15875        // (intrinsic_wo_chain:{ *:[i32] } 1847:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
15877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15880        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15881        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15882        GIR_EraseFromParent, /*InsnID*/0,
15883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15884        // GIR_Coverage, 445,
15885        GIR_Done,
15886      // Label 897: @39217
15887      GIM_Try, /*On fail goto*//*Label 898*/ 39276, // Rule ID 446 //
15888        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15889        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
15890        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15891        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15892        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15896        // (intrinsic_wo_chain:{ *:[i32] } 1848:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15897        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
15898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15902        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15903        GIR_EraseFromParent, /*InsnID*/0,
15904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15905        // GIR_Coverage, 446,
15906        GIR_Done,
15907      // Label 898: @39276
15908      GIM_Try, /*On fail goto*//*Label 899*/ 39335, // Rule ID 447 //
15909        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15910        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
15911        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15912        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15913        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15917        // (intrinsic_wo_chain:{ *:[i32] } 1849:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15918        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
15919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15922        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15923        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15924        GIR_EraseFromParent, /*InsnID*/0,
15925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15926        // GIR_Coverage, 447,
15927        GIR_Done,
15928      // Label 899: @39335
15929      GIM_Try, /*On fail goto*//*Label 900*/ 39394, // Rule ID 448 //
15930        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15931        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
15932        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15933        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15938        // (intrinsic_wo_chain:{ *:[i32] } 1850:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
15940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15943        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15944        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15945        GIR_EraseFromParent, /*InsnID*/0,
15946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15947        // GIR_Coverage, 448,
15948        GIR_Done,
15949      // Label 900: @39394
15950      GIM_Try, /*On fail goto*//*Label 901*/ 39453, // Rule ID 449 //
15951        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15952        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
15953        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15954        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15955        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15959        // (intrinsic_wo_chain:{ *:[i32] } 1851:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
15961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15964        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15965        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15966        GIR_EraseFromParent, /*InsnID*/0,
15967        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15968        // GIR_Coverage, 449,
15969        GIR_Done,
15970      // Label 901: @39453
15971      GIM_Try, /*On fail goto*//*Label 902*/ 39512, // Rule ID 462 //
15972        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15973        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
15974        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15975        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15976        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15980        // (intrinsic_wo_chain:{ *:[i32] } 1793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
15981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
15982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15985        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15986        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
15987        GIR_EraseFromParent, /*InsnID*/0,
15988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15989        // GIR_Coverage, 462,
15990        GIR_Done,
15991      // Label 902: @39512
15992      GIM_Try, /*On fail goto*//*Label 903*/ 39571, // Rule ID 463 //
15993        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
15995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15997        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16001        // (intrinsic_wo_chain:{ *:[i32] } 1791:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
16003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16008        GIR_EraseFromParent, /*InsnID*/0,
16009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16010        // GIR_Coverage, 463,
16011        GIR_Done,
16012      // Label 903: @39571
16013      GIM_Try, /*On fail goto*//*Label 904*/ 39630, // Rule ID 464 //
16014        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
16016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16022        // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
16024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16028        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16029        GIR_EraseFromParent, /*InsnID*/0,
16030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16031        // GIR_Coverage, 464,
16032        GIR_Done,
16033      // Label 904: @39630
16034      GIM_Try, /*On fail goto*//*Label 905*/ 39689, // Rule ID 465 //
16035        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
16037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16039        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16043        // (intrinsic_wo_chain:{ *:[i32] } 1794:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16044        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
16045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16048        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16049        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16050        GIR_EraseFromParent, /*InsnID*/0,
16051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16052        // GIR_Coverage, 465,
16053        GIR_Done,
16054      // Label 905: @39689
16055      GIM_Try, /*On fail goto*//*Label 906*/ 39748, // Rule ID 466 //
16056        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16057        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
16058        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16059        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16060        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16064        // (intrinsic_wo_chain:{ *:[i32] } 1795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16065        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
16066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16069        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16070        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16071        GIR_EraseFromParent, /*InsnID*/0,
16072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16073        // GIR_Coverage, 466,
16074        GIR_Done,
16075      // Label 906: @39748
16076      GIM_Try, /*On fail goto*//*Label 907*/ 39807, // Rule ID 467 //
16077        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16078        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
16079        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16080        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16081        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16085        // (intrinsic_wo_chain:{ *:[i32] } 1796:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16086        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
16087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16090        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16091        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16092        GIR_EraseFromParent, /*InsnID*/0,
16093        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16094        // GIR_Coverage, 467,
16095        GIR_Done,
16096      // Label 907: @39807
16097      GIM_Try, /*On fail goto*//*Label 908*/ 39866, // Rule ID 468 //
16098        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16099        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
16100        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16101        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16102        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16106        // (intrinsic_wo_chain:{ *:[i32] } 1842:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16107        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
16108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16111        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16112        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16113        GIR_EraseFromParent, /*InsnID*/0,
16114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16115        // GIR_Coverage, 468,
16116        GIR_Done,
16117      // Label 908: @39866
16118      GIM_Try, /*On fail goto*//*Label 909*/ 39925, // Rule ID 469 //
16119        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
16121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16123        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16127        // (intrinsic_wo_chain:{ *:[i32] } 1840:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
16129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16132        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16133        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16134        GIR_EraseFromParent, /*InsnID*/0,
16135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16136        // GIR_Coverage, 469,
16137        GIR_Done,
16138      // Label 909: @39925
16139      GIM_Try, /*On fail goto*//*Label 910*/ 39984, // Rule ID 470 //
16140        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16141        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
16142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16148        // (intrinsic_wo_chain:{ *:[i32] } 1841:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
16150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16153        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16154        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16155        GIR_EraseFromParent, /*InsnID*/0,
16156        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16157        // GIR_Coverage, 470,
16158        GIR_Done,
16159      // Label 910: @39984
16160      GIM_Try, /*On fail goto*//*Label 911*/ 40043, // Rule ID 471 //
16161        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16162        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
16163        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16164        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16165        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16169        // (intrinsic_wo_chain:{ *:[i32] } 1843:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16170        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
16171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16174        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16175        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16176        GIR_EraseFromParent, /*InsnID*/0,
16177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16178        // GIR_Coverage, 471,
16179        GIR_Done,
16180      // Label 911: @40043
16181      GIM_Try, /*On fail goto*//*Label 912*/ 40102, // Rule ID 472 //
16182        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16183        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
16184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16190        // (intrinsic_wo_chain:{ *:[i32] } 1844:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
16192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16195        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16196        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16197        GIR_EraseFromParent, /*InsnID*/0,
16198        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16199        // GIR_Coverage, 472,
16200        GIR_Done,
16201      // Label 912: @40102
16202      GIM_Try, /*On fail goto*//*Label 913*/ 40161, // Rule ID 473 //
16203        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16204        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
16205        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16206        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16207        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16211        // (intrinsic_wo_chain:{ *:[i32] } 1845:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16212        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
16213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16216        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16217        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16218        GIR_EraseFromParent, /*InsnID*/0,
16219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16220        // GIR_Coverage, 473,
16221        GIR_Done,
16222      // Label 913: @40161
16223      GIM_Try, /*On fail goto*//*Label 914*/ 40220, // Rule ID 474 //
16224        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
16226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16232        // (intrinsic_wo_chain:{ *:[i32] } 1853:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16233        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
16234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16237        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16238        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16239        GIR_EraseFromParent, /*InsnID*/0,
16240        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16241        // GIR_Coverage, 474,
16242        GIR_Done,
16243      // Label 914: @40220
16244      GIM_Try, /*On fail goto*//*Label 915*/ 40279, // Rule ID 530 //
16245        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16246        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
16247        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16248        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16249        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16253        // (intrinsic_wo_chain:{ *:[i32] } 1811:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16254        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
16255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16258        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16259        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16260        GIR_EraseFromParent, /*InsnID*/0,
16261        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16262        // GIR_Coverage, 530,
16263        GIR_Done,
16264      // Label 915: @40279
16265      GIM_Try, /*On fail goto*//*Label 916*/ 40338, // Rule ID 531 //
16266        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16267        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
16268        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16269        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16270        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16274        // (intrinsic_wo_chain:{ *:[i32] } 1812:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
16276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16279        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16280        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16281        GIR_EraseFromParent, /*InsnID*/0,
16282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16283        // GIR_Coverage, 531,
16284        GIR_Done,
16285      // Label 916: @40338
16286      GIM_Try, /*On fail goto*//*Label 917*/ 40397, // Rule ID 532 //
16287        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16288        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
16289        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16290        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16291        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16295        // (intrinsic_wo_chain:{ *:[i32] } 1819:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
16297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16300        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16301        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16302        GIR_EraseFromParent, /*InsnID*/0,
16303        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16304        // GIR_Coverage, 532,
16305        GIR_Done,
16306      // Label 917: @40397
16307      GIM_Try, /*On fail goto*//*Label 918*/ 40456, // Rule ID 533 //
16308        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16309        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
16310        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16311        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16312        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16316        // (intrinsic_wo_chain:{ *:[i32] } 1820:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16317        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
16318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16322        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16323        GIR_EraseFromParent, /*InsnID*/0,
16324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16325        // GIR_Coverage, 533,
16326        GIR_Done,
16327      // Label 918: @40456
16328      GIM_Try, /*On fail goto*//*Label 919*/ 40508, // Rule ID 547 //
16329        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
16331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16333        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16337        // (intrinsic_wo_chain:{ *:[i32] } 1507:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
16339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16342        GIR_EraseFromParent, /*InsnID*/0,
16343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16344        // GIR_Coverage, 547,
16345        GIR_Done,
16346      // Label 919: @40508
16347      GIM_Try, /*On fail goto*//*Label 920*/ 40560, // Rule ID 548 //
16348        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16349        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
16350        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16352        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16356        // (intrinsic_wo_chain:{ *:[i32] } 1508:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16357        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
16358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16361        GIR_EraseFromParent, /*InsnID*/0,
16362        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16363        // GIR_Coverage, 548,
16364        GIR_Done,
16365      // Label 920: @40560
16366      GIM_Try, /*On fail goto*//*Label 921*/ 40612, // Rule ID 549 //
16367        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16368        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
16369        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16370        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16371        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16375        // (intrinsic_wo_chain:{ *:[i32] } 1511:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
16377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16380        GIR_EraseFromParent, /*InsnID*/0,
16381        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16382        // GIR_Coverage, 549,
16383        GIR_Done,
16384      // Label 921: @40612
16385      GIM_Try, /*On fail goto*//*Label 922*/ 40664, // Rule ID 550 //
16386        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16387        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
16388        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16389        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16390        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16394        // (intrinsic_wo_chain:{ *:[i32] } 1509:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16395        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
16396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16399        GIR_EraseFromParent, /*InsnID*/0,
16400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16401        // GIR_Coverage, 550,
16402        GIR_Done,
16403      // Label 922: @40664
16404      GIM_Try, /*On fail goto*//*Label 923*/ 40716, // Rule ID 551 //
16405        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16406        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
16407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16409        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16413        // (intrinsic_wo_chain:{ *:[i32] } 1512:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16414        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
16415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16418        GIR_EraseFromParent, /*InsnID*/0,
16419        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16420        // GIR_Coverage, 551,
16421        GIR_Done,
16422      // Label 923: @40716
16423      GIM_Try, /*On fail goto*//*Label 924*/ 40768, // Rule ID 552 //
16424        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
16425        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
16426        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16427        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16432        // (intrinsic_wo_chain:{ *:[i32] } 1510:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
16433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
16434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16437        GIR_EraseFromParent, /*InsnID*/0,
16438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16439        // GIR_Coverage, 552,
16440        GIR_Done,
16441      // Label 924: @40768
16442      GIM_Try, /*On fail goto*//*Label 925*/ 40827, // Rule ID 795 //
16443        GIM_CheckFeatures, GIFBS_HasNEON,
16444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16445        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16446        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16447        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16451        // (intrinsic_wo_chain:{ *:[v4i16] } 1685:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16452        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
16453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16456        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16457        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16458        GIR_EraseFromParent, /*InsnID*/0,
16459        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16460        // GIR_Coverage, 795,
16461        GIR_Done,
16462      // Label 925: @40827
16463      GIM_Try, /*On fail goto*//*Label 926*/ 40886, // Rule ID 796 //
16464        GIM_CheckFeatures, GIFBS_HasNEON,
16465        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16466        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16467        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16468        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16472        // (intrinsic_wo_chain:{ *:[v2i32] } 1685:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16473        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
16474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16477        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16478        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16479        GIR_EraseFromParent, /*InsnID*/0,
16480        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16481        // GIR_Coverage, 796,
16482        GIR_Done,
16483      // Label 926: @40886
16484      GIM_Try, /*On fail goto*//*Label 927*/ 40945, // Rule ID 797 //
16485        GIM_CheckFeatures, GIFBS_HasNEON,
16486        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16487        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16488        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16489        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16493        // (intrinsic_wo_chain:{ *:[v8i16] } 1685:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
16494        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
16495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16498        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16499        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16500        GIR_EraseFromParent, /*InsnID*/0,
16501        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16502        // GIR_Coverage, 797,
16503        GIR_Done,
16504      // Label 927: @40945
16505      GIM_Try, /*On fail goto*//*Label 928*/ 41004, // Rule ID 798 //
16506        GIM_CheckFeatures, GIFBS_HasNEON,
16507        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16508        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16509        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16510        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16514        // (intrinsic_wo_chain:{ *:[v4i32] } 1685:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
16515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
16516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16519        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16520        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16521        GIR_EraseFromParent, /*InsnID*/0,
16522        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16523        // GIR_Coverage, 798,
16524        GIR_Done,
16525      // Label 928: @41004
16526      GIM_Try, /*On fail goto*//*Label 929*/ 41063, // Rule ID 799 //
16527        GIM_CheckFeatures, GIFBS_HasNEON,
16528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16529        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16530        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16531        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16535        // (intrinsic_wo_chain:{ *:[v8i8] } 1685:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
16537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16540        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16541        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16542        GIR_EraseFromParent, /*InsnID*/0,
16543        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16544        // GIR_Coverage, 799,
16545        GIR_Done,
16546      // Label 929: @41063
16547      GIM_Try, /*On fail goto*//*Label 930*/ 41122, // Rule ID 800 //
16548        GIM_CheckFeatures, GIFBS_HasNEON,
16549        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
16550        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16551        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16552        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16556        // (intrinsic_wo_chain:{ *:[v16i8] } 1685:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
16557        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
16558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16561        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16562        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16563        GIR_EraseFromParent, /*InsnID*/0,
16564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16565        // GIR_Coverage, 800,
16566        GIR_Done,
16567      // Label 930: @41122
16568      GIM_Try, /*On fail goto*//*Label 931*/ 41181, // Rule ID 801 //
16569        GIM_CheckFeatures, GIFBS_HasNEON,
16570        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16571        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16572        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16573        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16577        // (intrinsic_wo_chain:{ *:[v4i16] } 1686:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
16579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16582        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16583        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16584        GIR_EraseFromParent, /*InsnID*/0,
16585        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16586        // GIR_Coverage, 801,
16587        GIR_Done,
16588      // Label 931: @41181
16589      GIM_Try, /*On fail goto*//*Label 932*/ 41240, // Rule ID 802 //
16590        GIM_CheckFeatures, GIFBS_HasNEON,
16591        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16592        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16593        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16594        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16598        // (intrinsic_wo_chain:{ *:[v2i32] } 1686:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
16600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16603        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16604        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16605        GIR_EraseFromParent, /*InsnID*/0,
16606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16607        // GIR_Coverage, 802,
16608        GIR_Done,
16609      // Label 932: @41240
16610      GIM_Try, /*On fail goto*//*Label 933*/ 41299, // Rule ID 803 //
16611        GIM_CheckFeatures, GIFBS_HasNEON,
16612        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16613        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16614        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16615        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16619        // (intrinsic_wo_chain:{ *:[v8i16] } 1686:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
16620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
16621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16624        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16625        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16626        GIR_EraseFromParent, /*InsnID*/0,
16627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16628        // GIR_Coverage, 803,
16629        GIR_Done,
16630      // Label 933: @41299
16631      GIM_Try, /*On fail goto*//*Label 934*/ 41358, // Rule ID 804 //
16632        GIM_CheckFeatures, GIFBS_HasNEON,
16633        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16634        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16635        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16636        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16640        // (intrinsic_wo_chain:{ *:[v4i32] } 1686:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
16641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
16642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16645        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16646        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16647        GIR_EraseFromParent, /*InsnID*/0,
16648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16649        // GIR_Coverage, 804,
16650        GIR_Done,
16651      // Label 934: @41358
16652      GIM_Try, /*On fail goto*//*Label 935*/ 41417, // Rule ID 805 //
16653        GIM_CheckFeatures, GIFBS_HasNEON,
16654        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16655        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16656        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16657        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16661        // (intrinsic_wo_chain:{ *:[v8i8] } 1686:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16662        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
16663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16666        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16667        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16668        GIR_EraseFromParent, /*InsnID*/0,
16669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16670        // GIR_Coverage, 805,
16671        GIR_Done,
16672      // Label 935: @41417
16673      GIM_Try, /*On fail goto*//*Label 936*/ 41476, // Rule ID 806 //
16674        GIM_CheckFeatures, GIFBS_HasNEON,
16675        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
16676        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16677        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16678        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16682        // (intrinsic_wo_chain:{ *:[v16i8] } 1686:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
16683        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
16684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16687        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16688        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16689        GIR_EraseFromParent, /*InsnID*/0,
16690        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16691        // GIR_Coverage, 806,
16692        GIR_Done,
16693      // Label 936: @41476
16694      GIM_Try, /*On fail goto*//*Label 937*/ 41535, // Rule ID 807 //
16695        GIM_CheckFeatures, GIFBS_HasNEON,
16696        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16697        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16698        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16699        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16703        // (intrinsic_wo_chain:{ *:[v4i16] } 1743:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
16705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16708        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16709        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16710        GIR_EraseFromParent, /*InsnID*/0,
16711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16712        // GIR_Coverage, 807,
16713        GIR_Done,
16714      // Label 937: @41535
16715      GIM_Try, /*On fail goto*//*Label 938*/ 41594, // Rule ID 808 //
16716        GIM_CheckFeatures, GIFBS_HasNEON,
16717        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16718        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16719        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16720        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16724        // (intrinsic_wo_chain:{ *:[v2i32] } 1743:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
16726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16729        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16730        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16731        GIR_EraseFromParent, /*InsnID*/0,
16732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16733        // GIR_Coverage, 808,
16734        GIR_Done,
16735      // Label 938: @41594
16736      GIM_Try, /*On fail goto*//*Label 939*/ 41653, // Rule ID 809 //
16737        GIM_CheckFeatures, GIFBS_HasNEON,
16738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16740        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16741        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16745        // (intrinsic_wo_chain:{ *:[v8i16] } 1743:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
16746        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
16747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16750        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16751        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16752        GIR_EraseFromParent, /*InsnID*/0,
16753        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16754        // GIR_Coverage, 809,
16755        GIR_Done,
16756      // Label 939: @41653
16757      GIM_Try, /*On fail goto*//*Label 940*/ 41712, // Rule ID 810 //
16758        GIM_CheckFeatures, GIFBS_HasNEON,
16759        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16760        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16761        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16762        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16766        // (intrinsic_wo_chain:{ *:[v4i32] } 1743:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
16767        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
16768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16771        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16772        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16773        GIR_EraseFromParent, /*InsnID*/0,
16774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16775        // GIR_Coverage, 810,
16776        GIR_Done,
16777      // Label 940: @41712
16778      GIM_Try, /*On fail goto*//*Label 941*/ 41771, // Rule ID 811 //
16779        GIM_CheckFeatures, GIFBS_HasNEON,
16780        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16781        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16782        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16783        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16787        // (intrinsic_wo_chain:{ *:[v8i8] } 1743:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16788        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
16789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16792        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16793        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16794        GIR_EraseFromParent, /*InsnID*/0,
16795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16796        // GIR_Coverage, 811,
16797        GIR_Done,
16798      // Label 941: @41771
16799      GIM_Try, /*On fail goto*//*Label 942*/ 41830, // Rule ID 812 //
16800        GIM_CheckFeatures, GIFBS_HasNEON,
16801        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
16802        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16803        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16804        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16808        // (intrinsic_wo_chain:{ *:[v16i8] } 1743:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
16809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
16810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16813        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16814        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16815        GIR_EraseFromParent, /*InsnID*/0,
16816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16817        // GIR_Coverage, 812,
16818        GIR_Done,
16819      // Label 942: @41830
16820      GIM_Try, /*On fail goto*//*Label 943*/ 41889, // Rule ID 813 //
16821        GIM_CheckFeatures, GIFBS_HasNEON,
16822        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16823        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16824        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16825        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16829        // (intrinsic_wo_chain:{ *:[v4i16] } 1744:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16830        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
16831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16834        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16835        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16836        GIR_EraseFromParent, /*InsnID*/0,
16837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16838        // GIR_Coverage, 813,
16839        GIR_Done,
16840      // Label 943: @41889
16841      GIM_Try, /*On fail goto*//*Label 944*/ 41948, // Rule ID 814 //
16842        GIM_CheckFeatures, GIFBS_HasNEON,
16843        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16844        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16845        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16846        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16850        // (intrinsic_wo_chain:{ *:[v2i32] } 1744:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16851        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
16852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16855        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16856        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16857        GIR_EraseFromParent, /*InsnID*/0,
16858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16859        // GIR_Coverage, 814,
16860        GIR_Done,
16861      // Label 944: @41948
16862      GIM_Try, /*On fail goto*//*Label 945*/ 42007, // Rule ID 815 //
16863        GIM_CheckFeatures, GIFBS_HasNEON,
16864        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16865        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16866        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16867        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16871        // (intrinsic_wo_chain:{ *:[v8i16] } 1744:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
16872        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
16873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16876        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16877        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16878        GIR_EraseFromParent, /*InsnID*/0,
16879        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16880        // GIR_Coverage, 815,
16881        GIR_Done,
16882      // Label 945: @42007
16883      GIM_Try, /*On fail goto*//*Label 946*/ 42066, // Rule ID 816 //
16884        GIM_CheckFeatures, GIFBS_HasNEON,
16885        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16886        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16887        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16888        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16892        // (intrinsic_wo_chain:{ *:[v4i32] } 1744:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
16893        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
16894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16897        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16898        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16899        GIR_EraseFromParent, /*InsnID*/0,
16900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16901        // GIR_Coverage, 816,
16902        GIR_Done,
16903      // Label 946: @42066
16904      GIM_Try, /*On fail goto*//*Label 947*/ 42125, // Rule ID 817 //
16905        GIM_CheckFeatures, GIFBS_HasNEON,
16906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16909        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16913        // (intrinsic_wo_chain:{ *:[v8i8] } 1744:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
16915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16918        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16919        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16920        GIR_EraseFromParent, /*InsnID*/0,
16921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16922        // GIR_Coverage, 817,
16923        GIR_Done,
16924      // Label 947: @42125
16925      GIM_Try, /*On fail goto*//*Label 948*/ 42184, // Rule ID 818 //
16926        GIM_CheckFeatures, GIFBS_HasNEON,
16927        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
16928        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16929        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16930        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16934        // (intrinsic_wo_chain:{ *:[v16i8] } 1744:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
16935        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
16936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16939        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16940        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16941        GIR_EraseFromParent, /*InsnID*/0,
16942        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16943        // GIR_Coverage, 818,
16944        GIR_Done,
16945      // Label 948: @42184
16946      GIM_Try, /*On fail goto*//*Label 949*/ 42243, // Rule ID 835 //
16947        GIM_CheckFeatures, GIFBS_HasNEON,
16948        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
16949        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16950        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16951        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16955        // (intrinsic_wo_chain:{ *:[v8i8] } 1740:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
16956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
16957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16960        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16961        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16962        GIR_EraseFromParent, /*InsnID*/0,
16963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16964        // GIR_Coverage, 835,
16965        GIR_Done,
16966      // Label 949: @42243
16967      GIM_Try, /*On fail goto*//*Label 950*/ 42302, // Rule ID 836 //
16968        GIM_CheckFeatures, GIFBS_HasNEON,
16969        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
16970        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16971        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16972        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16976        // (intrinsic_wo_chain:{ *:[v4i16] } 1740:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
16977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
16978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16981        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16982        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
16983        GIR_EraseFromParent, /*InsnID*/0,
16984        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16985        // GIR_Coverage, 836,
16986        GIR_Done,
16987      // Label 950: @42302
16988      GIM_Try, /*On fail goto*//*Label 951*/ 42361, // Rule ID 837 //
16989        GIM_CheckFeatures, GIFBS_HasNEON,
16990        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
16991        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16992        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
16993        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
16994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16997        // (intrinsic_wo_chain:{ *:[v2i32] } 1740:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
16998        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
16999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17002        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17003        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17004        GIR_EraseFromParent, /*InsnID*/0,
17005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17006        // GIR_Coverage, 837,
17007        GIR_Done,
17008      // Label 951: @42361
17009      GIM_Try, /*On fail goto*//*Label 952*/ 42420, // Rule ID 844 //
17010        GIM_CheckFeatures, GIFBS_HasNEON,
17011        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
17012        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17013        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17014        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17018        // (intrinsic_wo_chain:{ *:[v8i8] } 1711:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
17019        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
17020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17023        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17024        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17025        GIR_EraseFromParent, /*InsnID*/0,
17026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17027        // GIR_Coverage, 844,
17028        GIR_Done,
17029      // Label 952: @42420
17030      GIM_Try, /*On fail goto*//*Label 953*/ 42479, // Rule ID 845 //
17031        GIM_CheckFeatures, GIFBS_HasNEON,
17032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
17033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17039        // (intrinsic_wo_chain:{ *:[v16i8] } 1711:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
17040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
17041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17045        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17046        GIR_EraseFromParent, /*InsnID*/0,
17047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17048        // GIR_Coverage, 845,
17049        GIR_Done,
17050      // Label 953: @42479
17051      GIM_Try, /*On fail goto*//*Label 954*/ 42538, // Rule ID 858 //
17052        GIM_CheckFeatures, GIFBS_HasNEON,
17053        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
17054        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17055        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17056        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17060        // (intrinsic_wo_chain:{ *:[v4i16] } 1722:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
17062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17066        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17067        GIR_EraseFromParent, /*InsnID*/0,
17068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17069        // GIR_Coverage, 858,
17070        GIR_Done,
17071      // Label 954: @42538
17072      GIM_Try, /*On fail goto*//*Label 955*/ 42597, // Rule ID 859 //
17073        GIM_CheckFeatures, GIFBS_HasNEON,
17074        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
17075        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17076        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17077        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17081        // (intrinsic_wo_chain:{ *:[v2i32] } 1722:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17082        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
17083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17086        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17087        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17088        GIR_EraseFromParent, /*InsnID*/0,
17089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17090        // GIR_Coverage, 859,
17091        GIR_Done,
17092      // Label 955: @42597
17093      GIM_Try, /*On fail goto*//*Label 956*/ 42656, // Rule ID 860 //
17094        GIM_CheckFeatures, GIFBS_HasNEON,
17095        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
17096        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17097        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17098        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17102        // (intrinsic_wo_chain:{ *:[v8i16] } 1722:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
17104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17107        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17108        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17109        GIR_EraseFromParent, /*InsnID*/0,
17110        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17111        // GIR_Coverage, 860,
17112        GIR_Done,
17113      // Label 956: @42656
17114      GIM_Try, /*On fail goto*//*Label 957*/ 42715, // Rule ID 861 //
17115        GIM_CheckFeatures, GIFBS_HasNEON,
17116        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
17117        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17118        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17119        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17123        // (intrinsic_wo_chain:{ *:[v4i32] } 1722:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
17125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17128        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17129        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17130        GIR_EraseFromParent, /*InsnID*/0,
17131        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17132        // GIR_Coverage, 861,
17133        GIR_Done,
17134      // Label 957: @42715
17135      GIM_Try, /*On fail goto*//*Label 958*/ 42774, // Rule ID 866 //
17136        GIM_CheckFeatures, GIFBS_HasNEON,
17137        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
17138        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17139        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17140        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17144        // (intrinsic_wo_chain:{ *:[v4i16] } 1728:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17145        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
17146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17149        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17150        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17151        GIR_EraseFromParent, /*InsnID*/0,
17152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17153        // GIR_Coverage, 866,
17154        GIR_Done,
17155      // Label 958: @42774
17156      GIM_Try, /*On fail goto*//*Label 959*/ 42833, // Rule ID 867 //
17157        GIM_CheckFeatures, GIFBS_HasNEON,
17158        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
17159        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17160        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17161        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17165        // (intrinsic_wo_chain:{ *:[v2i32] } 1728:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17166        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
17167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17170        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17171        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17172        GIR_EraseFromParent, /*InsnID*/0,
17173        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17174        // GIR_Coverage, 867,
17175        GIR_Done,
17176      // Label 959: @42833
17177      GIM_Try, /*On fail goto*//*Label 960*/ 42892, // Rule ID 868 //
17178        GIM_CheckFeatures, GIFBS_HasNEON,
17179        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
17180        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17181        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17182        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17186        // (intrinsic_wo_chain:{ *:[v8i16] } 1728:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
17188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17191        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17192        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17193        GIR_EraseFromParent, /*InsnID*/0,
17194        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17195        // GIR_Coverage, 868,
17196        GIR_Done,
17197      // Label 960: @42892
17198      GIM_Try, /*On fail goto*//*Label 961*/ 42951, // Rule ID 869 //
17199        GIM_CheckFeatures, GIFBS_HasNEON,
17200        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
17201        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17202        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17203        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17207        // (intrinsic_wo_chain:{ *:[v4i32] } 1728:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
17209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17212        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17213        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17214        GIR_EraseFromParent, /*InsnID*/0,
17215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17216        // GIR_Coverage, 869,
17217        GIR_Done,
17218      // Label 961: @42951
17219      GIM_Try, /*On fail goto*//*Label 962*/ 43010, // Rule ID 880 //
17220        GIM_CheckFeatures, GIFBS_HasNEON,
17221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
17222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17228        // (intrinsic_wo_chain:{ *:[v8i16] } 1708:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
17229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
17230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17233        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17234        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17235        GIR_EraseFromParent, /*InsnID*/0,
17236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17237        // GIR_Coverage, 880,
17238        GIR_Done,
17239      // Label 962: @43010
17240      GIM_Try, /*On fail goto*//*Label 963*/ 43062, // Rule ID 881 //
17241        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
17242        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
17243        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17244        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17245        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17249        // (intrinsic_wo_chain:{ *:[v2i64] } 1708:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
17250        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
17251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17254        GIR_EraseFromParent, /*InsnID*/0,
17255        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17256        // GIR_Coverage, 881,
17257        GIR_Done,
17258      // Label 963: @43062
17259      GIM_Try, /*On fail goto*//*Label 964*/ 43121, // Rule ID 886 //
17260        GIM_CheckFeatures, GIFBS_HasNEON,
17261        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
17262        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17263        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17264        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17268        // (intrinsic_wo_chain:{ *:[v4i32] } 1723:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
17270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17273        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17274        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17275        GIR_EraseFromParent, /*InsnID*/0,
17276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17277        // GIR_Coverage, 886,
17278        GIR_Done,
17279      // Label 964: @43121
17280      GIM_Try, /*On fail goto*//*Label 965*/ 43180, // Rule ID 887 //
17281        GIM_CheckFeatures, GIFBS_HasNEON,
17282        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
17283        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17284        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17285        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17289        // (intrinsic_wo_chain:{ *:[v2i64] } 1723:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
17291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17294        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17295        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17296        GIR_EraseFromParent, /*InsnID*/0,
17297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17298        // GIR_Coverage, 887,
17299        GIR_Done,
17300      // Label 965: @43180
17301      GIM_Try, /*On fail goto*//*Label 966*/ 43239, // Rule ID 982 //
17302        GIM_CheckFeatures, GIFBS_HasNEON,
17303        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17304        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17305        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17306        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17310        // (intrinsic_wo_chain:{ *:[v4i16] } 1687:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17311        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
17312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17315        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17316        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17317        GIR_EraseFromParent, /*InsnID*/0,
17318        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17319        // GIR_Coverage, 982,
17320        GIR_Done,
17321      // Label 966: @43239
17322      GIM_Try, /*On fail goto*//*Label 967*/ 43298, // Rule ID 983 //
17323        GIM_CheckFeatures, GIFBS_HasNEON,
17324        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17325        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17326        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17327        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17331        // (intrinsic_wo_chain:{ *:[v2i32] } 1687:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17332        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
17333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17336        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17337        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17338        GIR_EraseFromParent, /*InsnID*/0,
17339        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17340        // GIR_Coverage, 983,
17341        GIR_Done,
17342      // Label 967: @43298
17343      GIM_Try, /*On fail goto*//*Label 968*/ 43357, // Rule ID 984 //
17344        GIM_CheckFeatures, GIFBS_HasNEON,
17345        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17346        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17347        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17348        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17352        // (intrinsic_wo_chain:{ *:[v8i16] } 1687:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17353        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
17354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17357        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17358        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17359        GIR_EraseFromParent, /*InsnID*/0,
17360        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17361        // GIR_Coverage, 984,
17362        GIR_Done,
17363      // Label 968: @43357
17364      GIM_Try, /*On fail goto*//*Label 969*/ 43416, // Rule ID 985 //
17365        GIM_CheckFeatures, GIFBS_HasNEON,
17366        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17367        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17368        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17369        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17373        // (intrinsic_wo_chain:{ *:[v4i32] } 1687:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17374        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
17375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17378        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17379        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17380        GIR_EraseFromParent, /*InsnID*/0,
17381        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17382        // GIR_Coverage, 985,
17383        GIR_Done,
17384      // Label 969: @43416
17385      GIM_Try, /*On fail goto*//*Label 970*/ 43475, // Rule ID 986 //
17386        GIM_CheckFeatures, GIFBS_HasNEON,
17387        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17388        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17389        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17390        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17394        // (intrinsic_wo_chain:{ *:[v8i8] } 1687:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
17395        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
17396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17399        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17400        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17401        GIR_EraseFromParent, /*InsnID*/0,
17402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17403        // GIR_Coverage, 986,
17404        GIR_Done,
17405      // Label 970: @43475
17406      GIM_Try, /*On fail goto*//*Label 971*/ 43534, // Rule ID 987 //
17407        GIM_CheckFeatures, GIFBS_HasNEON,
17408        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
17409        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17410        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17411        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17415        // (intrinsic_wo_chain:{ *:[v16i8] } 1687:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
17416        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
17417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17420        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17421        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17422        GIR_EraseFromParent, /*InsnID*/0,
17423        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17424        // GIR_Coverage, 987,
17425        GIR_Done,
17426      // Label 971: @43534
17427      GIM_Try, /*On fail goto*//*Label 972*/ 43593, // Rule ID 988 //
17428        GIM_CheckFeatures, GIFBS_HasNEON,
17429        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17430        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17431        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17432        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17436        // (intrinsic_wo_chain:{ *:[v4i16] } 1688:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17437        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
17438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17441        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17442        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17443        GIR_EraseFromParent, /*InsnID*/0,
17444        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17445        // GIR_Coverage, 988,
17446        GIR_Done,
17447      // Label 972: @43593
17448      GIM_Try, /*On fail goto*//*Label 973*/ 43652, // Rule ID 989 //
17449        GIM_CheckFeatures, GIFBS_HasNEON,
17450        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17451        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17452        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17453        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17457        // (intrinsic_wo_chain:{ *:[v2i32] } 1688:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
17459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17462        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17463        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17464        GIR_EraseFromParent, /*InsnID*/0,
17465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17466        // GIR_Coverage, 989,
17467        GIR_Done,
17468      // Label 973: @43652
17469      GIM_Try, /*On fail goto*//*Label 974*/ 43711, // Rule ID 990 //
17470        GIM_CheckFeatures, GIFBS_HasNEON,
17471        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17472        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17473        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17474        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17478        // (intrinsic_wo_chain:{ *:[v8i16] } 1688:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
17480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17483        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17484        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17485        GIR_EraseFromParent, /*InsnID*/0,
17486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17487        // GIR_Coverage, 990,
17488        GIR_Done,
17489      // Label 974: @43711
17490      GIM_Try, /*On fail goto*//*Label 975*/ 43770, // Rule ID 991 //
17491        GIM_CheckFeatures, GIFBS_HasNEON,
17492        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17493        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17494        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17495        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17499        // (intrinsic_wo_chain:{ *:[v4i32] } 1688:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17500        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
17501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17504        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17505        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17506        GIR_EraseFromParent, /*InsnID*/0,
17507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17508        // GIR_Coverage, 991,
17509        GIR_Done,
17510      // Label 975: @43770
17511      GIM_Try, /*On fail goto*//*Label 976*/ 43829, // Rule ID 992 //
17512        GIM_CheckFeatures, GIFBS_HasNEON,
17513        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17514        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17515        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17516        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17520        // (intrinsic_wo_chain:{ *:[v8i8] } 1688:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
17521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
17522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17526        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17527        GIR_EraseFromParent, /*InsnID*/0,
17528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17529        // GIR_Coverage, 992,
17530        GIR_Done,
17531      // Label 976: @43829
17532      GIM_Try, /*On fail goto*//*Label 977*/ 43888, // Rule ID 993 //
17533        GIM_CheckFeatures, GIFBS_HasNEON,
17534        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
17535        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17536        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17537        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17541        // (intrinsic_wo_chain:{ *:[v16i8] } 1688:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
17542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
17543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17546        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17547        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17548        GIR_EraseFromParent, /*InsnID*/0,
17549        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17550        // GIR_Coverage, 993,
17551        GIR_Done,
17552      // Label 977: @43888
17553      GIM_Try, /*On fail goto*//*Label 978*/ 43947, // Rule ID 1010 //
17554        GIM_CheckFeatures, GIFBS_HasNEON,
17555        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
17556        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17557        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17558        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17562        // (intrinsic_wo_chain:{ *:[v8i8] } 1756:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17563        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
17564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17567        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17568        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17569        GIR_EraseFromParent, /*InsnID*/0,
17570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17571        // GIR_Coverage, 1010,
17572        GIR_Done,
17573      // Label 978: @43947
17574      GIM_Try, /*On fail goto*//*Label 979*/ 44006, // Rule ID 1011 //
17575        GIM_CheckFeatures, GIFBS_HasNEON,
17576        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
17577        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17578        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17579        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17583        // (intrinsic_wo_chain:{ *:[v4i16] } 1756:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
17585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17588        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17589        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17590        GIR_EraseFromParent, /*InsnID*/0,
17591        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17592        // GIR_Coverage, 1011,
17593        GIR_Done,
17594      // Label 979: @44006
17595      GIM_Try, /*On fail goto*//*Label 980*/ 44065, // Rule ID 1012 //
17596        GIM_CheckFeatures, GIFBS_HasNEON,
17597        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
17598        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17599        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17600        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17604        // (intrinsic_wo_chain:{ *:[v2i32] } 1756:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
17605        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
17606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17609        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17610        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17611        GIR_EraseFromParent, /*InsnID*/0,
17612        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17613        // GIR_Coverage, 1012,
17614        GIR_Done,
17615      // Label 980: @44065
17616      GIM_Try, /*On fail goto*//*Label 981*/ 44124, // Rule ID 1105 //
17617        GIM_CheckFeatures, GIFBS_HasNEON,
17618        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
17619        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17620        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17621        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17625        // (intrinsic_wo_chain:{ *:[v2i32] } 1665:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
17626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
17627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17630        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17631        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17632        GIR_EraseFromParent, /*InsnID*/0,
17633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17634        // GIR_Coverage, 1105,
17635        GIR_Done,
17636      // Label 981: @44124
17637      GIM_Try, /*On fail goto*//*Label 982*/ 44183, // Rule ID 1106 //
17638        GIM_CheckFeatures, GIFBS_HasNEON,
17639        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
17640        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17646        // (intrinsic_wo_chain:{ *:[v4i32] } 1665:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
17647        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
17648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17651        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17652        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17653        GIR_EraseFromParent, /*InsnID*/0,
17654        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17655        // GIR_Coverage, 1106,
17656        GIR_Done,
17657      // Label 982: @44183
17658      GIM_Try, /*On fail goto*//*Label 983*/ 44242, // Rule ID 1107 //
17659        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17660        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
17661        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17662        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17663        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17667        // (intrinsic_wo_chain:{ *:[v4i16] } 1665:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
17668        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
17669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17672        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17673        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17674        GIR_EraseFromParent, /*InsnID*/0,
17675        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17676        // GIR_Coverage, 1107,
17677        GIR_Done,
17678      // Label 983: @44242
17679      GIM_Try, /*On fail goto*//*Label 984*/ 44301, // Rule ID 1108 //
17680        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17681        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
17682        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17683        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17684        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17688        // (intrinsic_wo_chain:{ *:[v8i16] } 1665:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
17689        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
17690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17693        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17694        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17695        GIR_EraseFromParent, /*InsnID*/0,
17696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17697        // GIR_Coverage, 1108,
17698        GIR_Done,
17699      // Label 984: @44301
17700      GIM_Try, /*On fail goto*//*Label 985*/ 44360, // Rule ID 1109 //
17701        GIM_CheckFeatures, GIFBS_HasNEON,
17702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
17703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17709        // (intrinsic_wo_chain:{ *:[v2i32] } 1666:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
17710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
17711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17715        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17716        GIR_EraseFromParent, /*InsnID*/0,
17717        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17718        // GIR_Coverage, 1109,
17719        GIR_Done,
17720      // Label 985: @44360
17721      GIM_Try, /*On fail goto*//*Label 986*/ 44419, // Rule ID 1110 //
17722        GIM_CheckFeatures, GIFBS_HasNEON,
17723        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
17724        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17725        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17726        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17730        // (intrinsic_wo_chain:{ *:[v4i32] } 1666:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
17731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
17732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17735        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17736        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17737        GIR_EraseFromParent, /*InsnID*/0,
17738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17739        // GIR_Coverage, 1110,
17740        GIR_Done,
17741      // Label 986: @44419
17742      GIM_Try, /*On fail goto*//*Label 987*/ 44478, // Rule ID 1111 //
17743        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17744        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
17745        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17746        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17747        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17751        // (intrinsic_wo_chain:{ *:[v4i16] } 1666:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
17752        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
17753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17756        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17757        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17758        GIR_EraseFromParent, /*InsnID*/0,
17759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17760        // GIR_Coverage, 1111,
17761        GIR_Done,
17762      // Label 987: @44478
17763      GIM_Try, /*On fail goto*//*Label 988*/ 44537, // Rule ID 1112 //
17764        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17765        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
17766        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17767        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17772        // (intrinsic_wo_chain:{ *:[v8i16] } 1666:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
17773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
17774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17778        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17779        GIR_EraseFromParent, /*InsnID*/0,
17780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17781        // GIR_Coverage, 1112,
17782        GIR_Done,
17783      // Label 988: @44537
17784      GIM_Try, /*On fail goto*//*Label 989*/ 44596, // Rule ID 1145 //
17785        GIM_CheckFeatures, GIFBS_HasNEON,
17786        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17787        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17788        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17789        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17793        // (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
17795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17798        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17799        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17800        GIR_EraseFromParent, /*InsnID*/0,
17801        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17802        // GIR_Coverage, 1145,
17803        GIR_Done,
17804      // Label 989: @44596
17805      GIM_Try, /*On fail goto*//*Label 990*/ 44655, // Rule ID 1146 //
17806        GIM_CheckFeatures, GIFBS_HasNEON,
17807        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17808        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17809        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17810        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17814        // (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
17816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17819        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17820        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17821        GIR_EraseFromParent, /*InsnID*/0,
17822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17823        // GIR_Coverage, 1146,
17824        GIR_Done,
17825      // Label 990: @44655
17826      GIM_Try, /*On fail goto*//*Label 991*/ 44714, // Rule ID 1147 //
17827        GIM_CheckFeatures, GIFBS_HasNEON,
17828        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17829        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17830        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17831        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17835        // (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17836        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
17837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17840        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17841        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17842        GIR_EraseFromParent, /*InsnID*/0,
17843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17844        // GIR_Coverage, 1147,
17845        GIR_Done,
17846      // Label 991: @44714
17847      GIM_Try, /*On fail goto*//*Label 992*/ 44773, // Rule ID 1148 //
17848        GIM_CheckFeatures, GIFBS_HasNEON,
17849        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17850        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17851        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17852        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17856        // (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
17858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17861        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17862        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17863        GIR_EraseFromParent, /*InsnID*/0,
17864        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17865        // GIR_Coverage, 1148,
17866        GIR_Done,
17867      // Label 992: @44773
17868      GIM_Try, /*On fail goto*//*Label 993*/ 44832, // Rule ID 1149 //
17869        GIM_CheckFeatures, GIFBS_HasNEON,
17870        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17871        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17872        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17873        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17877        // (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
17878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
17879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17882        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17883        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17884        GIR_EraseFromParent, /*InsnID*/0,
17885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17886        // GIR_Coverage, 1149,
17887        GIR_Done,
17888      // Label 993: @44832
17889      GIM_Try, /*On fail goto*//*Label 994*/ 44891, // Rule ID 1150 //
17890        GIM_CheckFeatures, GIFBS_HasNEON,
17891        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
17892        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17893        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17894        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17898        // (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
17899        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
17900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17903        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17904        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17905        GIR_EraseFromParent, /*InsnID*/0,
17906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17907        // GIR_Coverage, 1150,
17908        GIR_Done,
17909      // Label 994: @44891
17910      GIM_Try, /*On fail goto*//*Label 995*/ 44950, // Rule ID 1151 //
17911        GIM_CheckFeatures, GIFBS_HasNEON,
17912        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
17913        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17914        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17915        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17919        // (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
17920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
17921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17924        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17925        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17926        GIR_EraseFromParent, /*InsnID*/0,
17927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17928        // GIR_Coverage, 1151,
17929        GIR_Done,
17930      // Label 995: @44950
17931      GIM_Try, /*On fail goto*//*Label 996*/ 45009, // Rule ID 1152 //
17932        GIM_CheckFeatures, GIFBS_HasNEON,
17933        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
17934        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17935        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17936        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17940        // (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
17941        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
17942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17945        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17946        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17947        GIR_EraseFromParent, /*InsnID*/0,
17948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17949        // GIR_Coverage, 1152,
17950        GIR_Done,
17951      // Label 996: @45009
17952      GIM_Try, /*On fail goto*//*Label 997*/ 45068, // Rule ID 1153 //
17953        GIM_CheckFeatures, GIFBS_HasNEON,
17954        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
17955        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17956        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17957        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17961        // (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
17962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
17963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17966        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17967        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17968        GIR_EraseFromParent, /*InsnID*/0,
17969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17970        // GIR_Coverage, 1153,
17971        GIR_Done,
17972      // Label 997: @45068
17973      GIM_Try, /*On fail goto*//*Label 998*/ 45127, // Rule ID 1154 //
17974        GIM_CheckFeatures, GIFBS_HasNEON,
17975        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
17976        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17977        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17978        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17982        // (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
17983        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
17984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
17986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17987        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17988        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
17989        GIR_EraseFromParent, /*InsnID*/0,
17990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17991        // GIR_Coverage, 1154,
17992        GIR_Done,
17993      // Label 998: @45127
17994      GIM_Try, /*On fail goto*//*Label 999*/ 45186, // Rule ID 1155 //
17995        GIM_CheckFeatures, GIFBS_HasNEON,
17996        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
17997        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17998        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17999        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18003        // (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18004        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
18005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18008        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18009        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18010        GIR_EraseFromParent, /*InsnID*/0,
18011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18012        // GIR_Coverage, 1155,
18013        GIR_Done,
18014      // Label 999: @45186
18015      GIM_Try, /*On fail goto*//*Label 1000*/ 45245, // Rule ID 1156 //
18016        GIM_CheckFeatures, GIFBS_HasNEON,
18017        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
18018        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
18019        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
18020        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18024        // (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
18026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18029        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18030        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18031        GIR_EraseFromParent, /*InsnID*/0,
18032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18033        // GIR_Coverage, 1156,
18034        GIR_Done,
18035      // Label 1000: @45245
18036      GIM_Try, /*On fail goto*//*Label 1001*/ 45304, // Rule ID 1157 //
18037        GIM_CheckFeatures, GIFBS_HasNEON,
18038        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
18039        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18040        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18041        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18045        // (intrinsic_wo_chain:{ *:[v2f32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
18047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18050        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18051        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18052        GIR_EraseFromParent, /*InsnID*/0,
18053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18054        // GIR_Coverage, 1157,
18055        GIR_Done,
18056      // Label 1001: @45304
18057      GIM_Try, /*On fail goto*//*Label 1002*/ 45363, // Rule ID 1158 //
18058        GIM_CheckFeatures, GIFBS_HasNEON,
18059        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
18060        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18061        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18062        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18066        // (intrinsic_wo_chain:{ *:[v4f32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
18067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
18068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18071        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18072        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18073        GIR_EraseFromParent, /*InsnID*/0,
18074        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18075        // GIR_Coverage, 1158,
18076        GIR_Done,
18077      // Label 1002: @45363
18078      GIM_Try, /*On fail goto*//*Label 1003*/ 45422, // Rule ID 1159 //
18079        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18080        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
18081        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18082        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18083        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18087        // (intrinsic_wo_chain:{ *:[v4f16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
18089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18092        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18093        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18094        GIR_EraseFromParent, /*InsnID*/0,
18095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18096        // GIR_Coverage, 1159,
18097        GIR_Done,
18098      // Label 1003: @45422
18099      GIM_Try, /*On fail goto*//*Label 1004*/ 45481, // Rule ID 1160 //
18100        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18101        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
18102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18108        // (intrinsic_wo_chain:{ *:[v8f16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
18109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
18110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18113        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18114        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18115        GIR_EraseFromParent, /*InsnID*/0,
18116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18117        // GIR_Coverage, 1160,
18118        GIR_Done,
18119      // Label 1004: @45481
18120      GIM_Try, /*On fail goto*//*Label 1005*/ 45540, // Rule ID 1225 //
18121        GIM_CheckFeatures, GIFBS_HasNEON,
18122        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
18123        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18124        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18125        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18129        // (intrinsic_wo_chain:{ *:[v8i8] } 1714:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
18131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18134        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18135        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18136        GIR_EraseFromParent, /*InsnID*/0,
18137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18138        // GIR_Coverage, 1225,
18139        GIR_Done,
18140      // Label 1005: @45540
18141      GIM_Try, /*On fail goto*//*Label 1006*/ 45599, // Rule ID 1226 //
18142        GIM_CheckFeatures, GIFBS_HasNEON,
18143        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
18144        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18145        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18146        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18150        // (intrinsic_wo_chain:{ *:[v4i16] } 1714:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18151        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
18152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18155        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18156        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18157        GIR_EraseFromParent, /*InsnID*/0,
18158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18159        // GIR_Coverage, 1226,
18160        GIR_Done,
18161      // Label 1006: @45599
18162      GIM_Try, /*On fail goto*//*Label 1007*/ 45658, // Rule ID 1227 //
18163        GIM_CheckFeatures, GIFBS_HasNEON,
18164        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
18165        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18166        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18167        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18171        // (intrinsic_wo_chain:{ *:[v2i32] } 1714:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18172        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
18173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18176        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18177        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18178        GIR_EraseFromParent, /*InsnID*/0,
18179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18180        // GIR_Coverage, 1227,
18181        GIR_Done,
18182      // Label 1007: @45658
18183      GIM_Try, /*On fail goto*//*Label 1008*/ 45717, // Rule ID 1228 //
18184        GIM_CheckFeatures, GIFBS_HasNEON,
18185        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
18186        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18187        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18188        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18192        // (intrinsic_wo_chain:{ *:[v2f32] } 1714:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
18194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18197        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18198        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18199        GIR_EraseFromParent, /*InsnID*/0,
18200        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18201        // GIR_Coverage, 1228,
18202        GIR_Done,
18203      // Label 1008: @45717
18204      GIM_Try, /*On fail goto*//*Label 1009*/ 45776, // Rule ID 1229 //
18205        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18206        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
18207        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18208        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18209        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18213        // (intrinsic_wo_chain:{ *:[v4f16] } 1714:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
18215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18219        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18220        GIR_EraseFromParent, /*InsnID*/0,
18221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18222        // GIR_Coverage, 1229,
18223        GIR_Done,
18224      // Label 1009: @45776
18225      GIM_Try, /*On fail goto*//*Label 1010*/ 45835, // Rule ID 1242 //
18226        GIM_CheckFeatures, GIFBS_HasNEON,
18227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18228        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18229        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18230        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18234        // (intrinsic_wo_chain:{ *:[v4i16] } 1712:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
18235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
18236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18239        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18240        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18241        GIR_EraseFromParent, /*InsnID*/0,
18242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18243        // GIR_Coverage, 1242,
18244        GIR_Done,
18245      // Label 1010: @45835
18246      GIM_Try, /*On fail goto*//*Label 1011*/ 45894, // Rule ID 1243 //
18247        GIM_CheckFeatures, GIFBS_HasNEON,
18248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18249        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18250        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18251        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18255        // (intrinsic_wo_chain:{ *:[v2i32] } 1712:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
18256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
18257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18260        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18261        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18262        GIR_EraseFromParent, /*InsnID*/0,
18263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18264        // GIR_Coverage, 1243,
18265        GIR_Done,
18266      // Label 1011: @45894
18267      GIM_Try, /*On fail goto*//*Label 1012*/ 45953, // Rule ID 1244 //
18268        GIM_CheckFeatures, GIFBS_HasNEON,
18269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
18271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
18272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18276        // (intrinsic_wo_chain:{ *:[v1i64] } 1712:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
18277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
18278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18281        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18282        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18283        GIR_EraseFromParent, /*InsnID*/0,
18284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18285        // GIR_Coverage, 1244,
18286        GIR_Done,
18287      // Label 1012: @45953
18288      GIM_Try, /*On fail goto*//*Label 1013*/ 46012, // Rule ID 1245 //
18289        GIM_CheckFeatures, GIFBS_HasNEON,
18290        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18291        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18292        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18293        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18297        // (intrinsic_wo_chain:{ *:[v8i16] } 1712:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
18298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
18299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18302        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18303        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18304        GIR_EraseFromParent, /*InsnID*/0,
18305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18306        // GIR_Coverage, 1245,
18307        GIR_Done,
18308      // Label 1013: @46012
18309      GIM_Try, /*On fail goto*//*Label 1014*/ 46071, // Rule ID 1246 //
18310        GIM_CheckFeatures, GIFBS_HasNEON,
18311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18318        // (intrinsic_wo_chain:{ *:[v4i32] } 1712:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
18319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
18320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18324        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18325        GIR_EraseFromParent, /*InsnID*/0,
18326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18327        // GIR_Coverage, 1246,
18328        GIR_Done,
18329      // Label 1014: @46071
18330      GIM_Try, /*On fail goto*//*Label 1015*/ 46130, // Rule ID 1247 //
18331        GIM_CheckFeatures, GIFBS_HasNEON,
18332        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
18333        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
18334        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
18335        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18339        // (intrinsic_wo_chain:{ *:[v2i64] } 1712:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
18340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
18341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18344        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18345        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18346        GIR_EraseFromParent, /*InsnID*/0,
18347        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18348        // GIR_Coverage, 1247,
18349        GIR_Done,
18350      // Label 1015: @46130
18351      GIM_Try, /*On fail goto*//*Label 1016*/ 46189, // Rule ID 1248 //
18352        GIM_CheckFeatures, GIFBS_HasNEON,
18353        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18354        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18355        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18356        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18360        // (intrinsic_wo_chain:{ *:[v4i16] } 1713:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
18361        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
18362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18365        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18366        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18367        GIR_EraseFromParent, /*InsnID*/0,
18368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18369        // GIR_Coverage, 1248,
18370        GIR_Done,
18371      // Label 1016: @46189
18372      GIM_Try, /*On fail goto*//*Label 1017*/ 46248, // Rule ID 1249 //
18373        GIM_CheckFeatures, GIFBS_HasNEON,
18374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18376        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18377        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18381        // (intrinsic_wo_chain:{ *:[v2i32] } 1713:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
18382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
18383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18386        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18387        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18388        GIR_EraseFromParent, /*InsnID*/0,
18389        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18390        // GIR_Coverage, 1249,
18391        GIR_Done,
18392      // Label 1017: @46248
18393      GIM_Try, /*On fail goto*//*Label 1018*/ 46307, // Rule ID 1250 //
18394        GIM_CheckFeatures, GIFBS_HasNEON,
18395        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18396        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
18397        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
18398        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18402        // (intrinsic_wo_chain:{ *:[v1i64] } 1713:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
18403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
18404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18407        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18408        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18409        GIR_EraseFromParent, /*InsnID*/0,
18410        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18411        // GIR_Coverage, 1250,
18412        GIR_Done,
18413      // Label 1018: @46307
18414      GIM_Try, /*On fail goto*//*Label 1019*/ 46366, // Rule ID 1251 //
18415        GIM_CheckFeatures, GIFBS_HasNEON,
18416        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18417        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18418        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18419        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18423        // (intrinsic_wo_chain:{ *:[v8i16] } 1713:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
18424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
18425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18429        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18430        GIR_EraseFromParent, /*InsnID*/0,
18431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18432        // GIR_Coverage, 1251,
18433        GIR_Done,
18434      // Label 1019: @46366
18435      GIM_Try, /*On fail goto*//*Label 1020*/ 46425, // Rule ID 1252 //
18436        GIM_CheckFeatures, GIFBS_HasNEON,
18437        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18438        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18439        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18440        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18444        // (intrinsic_wo_chain:{ *:[v4i32] } 1713:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
18445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
18446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18449        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18450        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18451        GIR_EraseFromParent, /*InsnID*/0,
18452        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18453        // GIR_Coverage, 1252,
18454        GIR_Done,
18455      // Label 1020: @46425
18456      GIM_Try, /*On fail goto*//*Label 1021*/ 46484, // Rule ID 1253 //
18457        GIM_CheckFeatures, GIFBS_HasNEON,
18458        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
18459        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
18460        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
18461        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18465        // (intrinsic_wo_chain:{ *:[v2i64] } 1713:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
18466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
18467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
18469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18470        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18471        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18472        GIR_EraseFromParent, /*InsnID*/0,
18473        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18474        // GIR_Coverage, 1253,
18475        GIR_Done,
18476      // Label 1021: @46484
18477      GIM_Try, /*On fail goto*//*Label 1022*/ 46543, // Rule ID 1254 //
18478        GIM_CheckFeatures, GIFBS_HasNEON,
18479        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
18480        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18481        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18482        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18486        // (intrinsic_wo_chain:{ *:[v8i8] } 1717:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18487        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
18488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18491        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18492        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18493        GIR_EraseFromParent, /*InsnID*/0,
18494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18495        // GIR_Coverage, 1254,
18496        GIR_Done,
18497      // Label 1022: @46543
18498      GIM_Try, /*On fail goto*//*Label 1023*/ 46602, // Rule ID 1255 //
18499        GIM_CheckFeatures, GIFBS_HasNEON,
18500        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
18501        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18502        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18503        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18507        // (intrinsic_wo_chain:{ *:[v4i16] } 1717:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
18509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18512        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18513        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18514        GIR_EraseFromParent, /*InsnID*/0,
18515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18516        // GIR_Coverage, 1255,
18517        GIR_Done,
18518      // Label 1023: @46602
18519      GIM_Try, /*On fail goto*//*Label 1024*/ 46661, // Rule ID 1256 //
18520        GIM_CheckFeatures, GIFBS_HasNEON,
18521        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
18522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18528        // (intrinsic_wo_chain:{ *:[v2i32] } 1717:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18529        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
18530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18533        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18534        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18535        GIR_EraseFromParent, /*InsnID*/0,
18536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18537        // GIR_Coverage, 1256,
18538        GIR_Done,
18539      // Label 1024: @46661
18540      GIM_Try, /*On fail goto*//*Label 1025*/ 46720, // Rule ID 1257 //
18541        GIM_CheckFeatures, GIFBS_HasNEON,
18542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
18543        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18544        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18545        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18549        // (intrinsic_wo_chain:{ *:[v8i8] } 1718:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
18551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18554        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18555        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18556        GIR_EraseFromParent, /*InsnID*/0,
18557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18558        // GIR_Coverage, 1257,
18559        GIR_Done,
18560      // Label 1025: @46720
18561      GIM_Try, /*On fail goto*//*Label 1026*/ 46779, // Rule ID 1258 //
18562        GIM_CheckFeatures, GIFBS_HasNEON,
18563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
18564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18570        // (intrinsic_wo_chain:{ *:[v4i16] } 1718:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
18572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18575        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18576        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18577        GIR_EraseFromParent, /*InsnID*/0,
18578        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18579        // GIR_Coverage, 1258,
18580        GIR_Done,
18581      // Label 1026: @46779
18582      GIM_Try, /*On fail goto*//*Label 1027*/ 46838, // Rule ID 1259 //
18583        GIM_CheckFeatures, GIFBS_HasNEON,
18584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
18585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18586        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18587        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18591        // (intrinsic_wo_chain:{ *:[v2i32] } 1718:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
18593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18596        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18597        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18598        GIR_EraseFromParent, /*InsnID*/0,
18599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18600        // GIR_Coverage, 1259,
18601        GIR_Done,
18602      // Label 1027: @46838
18603      GIM_Try, /*On fail goto*//*Label 1028*/ 46897, // Rule ID 1260 //
18604        GIM_CheckFeatures, GIFBS_HasNEON,
18605        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
18606        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18607        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18608        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18612        // (intrinsic_wo_chain:{ *:[v2f32] } 1717:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18613        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
18614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18617        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18618        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18619        GIR_EraseFromParent, /*InsnID*/0,
18620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18621        // GIR_Coverage, 1260,
18622        GIR_Done,
18623      // Label 1028: @46897
18624      GIM_Try, /*On fail goto*//*Label 1029*/ 46956, // Rule ID 1261 //
18625        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18626        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
18627        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18628        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18629        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18633        // (intrinsic_wo_chain:{ *:[v4f16] } 1717:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
18635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18638        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18639        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18640        GIR_EraseFromParent, /*InsnID*/0,
18641        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18642        // GIR_Coverage, 1261,
18643        GIR_Done,
18644      // Label 1029: @46956
18645      GIM_Try, /*On fail goto*//*Label 1030*/ 47015, // Rule ID 1262 //
18646        GIM_CheckFeatures, GIFBS_HasNEON,
18647        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
18648        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18649        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18654        // (intrinsic_wo_chain:{ *:[v8i8] } 1719:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
18656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18659        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18660        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18661        GIR_EraseFromParent, /*InsnID*/0,
18662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18663        // GIR_Coverage, 1262,
18664        GIR_Done,
18665      // Label 1030: @47015
18666      GIM_Try, /*On fail goto*//*Label 1031*/ 47074, // Rule ID 1263 //
18667        GIM_CheckFeatures, GIFBS_HasNEON,
18668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
18669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18671        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18675        // (intrinsic_wo_chain:{ *:[v4i16] } 1719:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
18677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18681        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18682        GIR_EraseFromParent, /*InsnID*/0,
18683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18684        // GIR_Coverage, 1263,
18685        GIR_Done,
18686      // Label 1031: @47074
18687      GIM_Try, /*On fail goto*//*Label 1032*/ 47133, // Rule ID 1264 //
18688        GIM_CheckFeatures, GIFBS_HasNEON,
18689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
18690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18692        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18696        // (intrinsic_wo_chain:{ *:[v2i32] } 1719:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
18698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18701        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18702        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18703        GIR_EraseFromParent, /*InsnID*/0,
18704        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18705        // GIR_Coverage, 1264,
18706        GIR_Done,
18707      // Label 1032: @47133
18708      GIM_Try, /*On fail goto*//*Label 1033*/ 47192, // Rule ID 1265 //
18709        GIM_CheckFeatures, GIFBS_HasNEON,
18710        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
18711        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18712        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18713        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18717        // (intrinsic_wo_chain:{ *:[v8i8] } 1720:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
18719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18722        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18723        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18724        GIR_EraseFromParent, /*InsnID*/0,
18725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18726        // GIR_Coverage, 1265,
18727        GIR_Done,
18728      // Label 1033: @47192
18729      GIM_Try, /*On fail goto*//*Label 1034*/ 47251, // Rule ID 1266 //
18730        GIM_CheckFeatures, GIFBS_HasNEON,
18731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
18732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18738        // (intrinsic_wo_chain:{ *:[v4i16] } 1720:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
18740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18743        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18744        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18745        GIR_EraseFromParent, /*InsnID*/0,
18746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18747        // GIR_Coverage, 1266,
18748        GIR_Done,
18749      // Label 1034: @47251
18750      GIM_Try, /*On fail goto*//*Label 1035*/ 47310, // Rule ID 1267 //
18751        GIM_CheckFeatures, GIFBS_HasNEON,
18752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
18753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18759        // (intrinsic_wo_chain:{ *:[v2i32] } 1720:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
18761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18764        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18765        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18766        GIR_EraseFromParent, /*InsnID*/0,
18767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18768        // GIR_Coverage, 1267,
18769        GIR_Done,
18770      // Label 1035: @47310
18771      GIM_Try, /*On fail goto*//*Label 1036*/ 47369, // Rule ID 1268 //
18772        GIM_CheckFeatures, GIFBS_HasNEON,
18773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
18774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18780        // (intrinsic_wo_chain:{ *:[v2f32] } 1719:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
18782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18785        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18786        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18787        GIR_EraseFromParent, /*InsnID*/0,
18788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18789        // GIR_Coverage, 1268,
18790        GIR_Done,
18791      // Label 1036: @47369
18792      GIM_Try, /*On fail goto*//*Label 1037*/ 47428, // Rule ID 1269 //
18793        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18794        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
18795        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18796        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18797        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18801        // (intrinsic_wo_chain:{ *:[v4f16] } 1719:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
18803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18806        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18807        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18808        GIR_EraseFromParent, /*InsnID*/0,
18809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18810        // GIR_Coverage, 1269,
18811        GIR_Done,
18812      // Label 1037: @47428
18813      GIM_Try, /*On fail goto*//*Label 1038*/ 47487, // Rule ID 1276 //
18814        GIM_CheckFeatures, GIFBS_HasNEON,
18815        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
18816        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18817        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18822        // (intrinsic_wo_chain:{ *:[v2f32] } 1742:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
18824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18827        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18828        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18829        GIR_EraseFromParent, /*InsnID*/0,
18830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18831        // GIR_Coverage, 1276,
18832        GIR_Done,
18833      // Label 1038: @47487
18834      GIM_Try, /*On fail goto*//*Label 1039*/ 47546, // Rule ID 1277 //
18835        GIM_CheckFeatures, GIFBS_HasNEON,
18836        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
18837        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18838        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18839        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18843        // (intrinsic_wo_chain:{ *:[v4f32] } 1742:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
18844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
18845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18848        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18849        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18850        GIR_EraseFromParent, /*InsnID*/0,
18851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18852        // GIR_Coverage, 1277,
18853        GIR_Done,
18854      // Label 1039: @47546
18855      GIM_Try, /*On fail goto*//*Label 1040*/ 47605, // Rule ID 1278 //
18856        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18857        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
18858        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18859        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18860        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18864        // (intrinsic_wo_chain:{ *:[v4f16] } 1742:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18865        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
18866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18869        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18870        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18871        GIR_EraseFromParent, /*InsnID*/0,
18872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18873        // GIR_Coverage, 1278,
18874        GIR_Done,
18875      // Label 1040: @47605
18876      GIM_Try, /*On fail goto*//*Label 1041*/ 47664, // Rule ID 1279 //
18877        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18878        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
18879        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18880        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18881        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18885        // (intrinsic_wo_chain:{ *:[v8f16] } 1742:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
18886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
18887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18891        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18892        GIR_EraseFromParent, /*InsnID*/0,
18893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18894        // GIR_Coverage, 1279,
18895        GIR_Done,
18896      // Label 1041: @47664
18897      GIM_Try, /*On fail goto*//*Label 1042*/ 47723, // Rule ID 1286 //
18898        GIM_CheckFeatures, GIFBS_HasNEON,
18899        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
18900        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18901        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18902        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18906        // (intrinsic_wo_chain:{ *:[v2f32] } 1755:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
18907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
18908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18911        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18912        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18913        GIR_EraseFromParent, /*InsnID*/0,
18914        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18915        // GIR_Coverage, 1286,
18916        GIR_Done,
18917      // Label 1042: @47723
18918      GIM_Try, /*On fail goto*//*Label 1043*/ 47782, // Rule ID 1287 //
18919        GIM_CheckFeatures, GIFBS_HasNEON,
18920        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
18921        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18922        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18923        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18927        // (intrinsic_wo_chain:{ *:[v4f32] } 1755:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
18928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
18929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18932        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18933        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18934        GIR_EraseFromParent, /*InsnID*/0,
18935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18936        // GIR_Coverage, 1287,
18937        GIR_Done,
18938      // Label 1043: @47782
18939      GIM_Try, /*On fail goto*//*Label 1044*/ 47841, // Rule ID 1288 //
18940        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18941        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
18942        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18943        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18944        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18948        // (intrinsic_wo_chain:{ *:[v4f16] } 1755:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
18949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
18950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18953        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18954        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18955        GIR_EraseFromParent, /*InsnID*/0,
18956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18957        // GIR_Coverage, 1288,
18958        GIR_Done,
18959      // Label 1044: @47841
18960      GIM_Try, /*On fail goto*//*Label 1045*/ 47900, // Rule ID 1289 //
18961        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
18962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
18963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18969        // (intrinsic_wo_chain:{ *:[v8f16] } 1755:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
18970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
18971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18974        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18975        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18976        GIR_EraseFromParent, /*InsnID*/0,
18977        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18978        // GIR_Coverage, 1289,
18979        GIR_Done,
18980      // Label 1045: @47900
18981      GIM_Try, /*On fail goto*//*Label 1046*/ 47959, // Rule ID 1290 //
18982        GIM_CheckFeatures, GIFBS_HasNEON,
18983        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
18984        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18985        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18986        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18990        // (intrinsic_wo_chain:{ *:[v4i16] } 1758:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
18991        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
18992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
18994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18995        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18996        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
18997        GIR_EraseFromParent, /*InsnID*/0,
18998        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18999        // GIR_Coverage, 1290,
19000        GIR_Done,
19001      // Label 1046: @47959
19002      GIM_Try, /*On fail goto*//*Label 1047*/ 48018, // Rule ID 1291 //
19003        GIM_CheckFeatures, GIFBS_HasNEON,
19004        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19005        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19006        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19007        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19011        // (intrinsic_wo_chain:{ *:[v2i32] } 1758:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
19013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19016        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19017        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19018        GIR_EraseFromParent, /*InsnID*/0,
19019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19020        // GIR_Coverage, 1291,
19021        GIR_Done,
19022      // Label 1047: @48018
19023      GIM_Try, /*On fail goto*//*Label 1048*/ 48077, // Rule ID 1292 //
19024        GIM_CheckFeatures, GIFBS_HasNEON,
19025        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19026        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19027        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19028        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19032        // (intrinsic_wo_chain:{ *:[v8i16] } 1758:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19033        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
19034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19037        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19038        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19039        GIR_EraseFromParent, /*InsnID*/0,
19040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19041        // GIR_Coverage, 1292,
19042        GIR_Done,
19043      // Label 1048: @48077
19044      GIM_Try, /*On fail goto*//*Label 1049*/ 48136, // Rule ID 1293 //
19045        GIM_CheckFeatures, GIFBS_HasNEON,
19046        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19047        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19048        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19049        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19053        // (intrinsic_wo_chain:{ *:[v4i32] } 1758:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19054        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
19055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19058        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19059        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19060        GIR_EraseFromParent, /*InsnID*/0,
19061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19062        // GIR_Coverage, 1293,
19063        GIR_Done,
19064      // Label 1049: @48136
19065      GIM_Try, /*On fail goto*//*Label 1050*/ 48195, // Rule ID 1294 //
19066        GIM_CheckFeatures, GIFBS_HasNEON,
19067        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19068        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19069        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19070        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19074        // (intrinsic_wo_chain:{ *:[v8i8] } 1758:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19075        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
19076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19079        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19080        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19081        GIR_EraseFromParent, /*InsnID*/0,
19082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19083        // GIR_Coverage, 1294,
19084        GIR_Done,
19085      // Label 1050: @48195
19086      GIM_Try, /*On fail goto*//*Label 1051*/ 48254, // Rule ID 1295 //
19087        GIM_CheckFeatures, GIFBS_HasNEON,
19088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19091        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19095        // (intrinsic_wo_chain:{ *:[v16i8] } 1758:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
19097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19100        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19101        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19102        GIR_EraseFromParent, /*InsnID*/0,
19103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19104        // GIR_Coverage, 1295,
19105        GIR_Done,
19106      // Label 1051: @48254
19107      GIM_Try, /*On fail goto*//*Label 1052*/ 48313, // Rule ID 1296 //
19108        GIM_CheckFeatures, GIFBS_HasNEON,
19109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19112        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19116        // (intrinsic_wo_chain:{ *:[v1i64] } 1758:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19117        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
19118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19121        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19122        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19123        GIR_EraseFromParent, /*InsnID*/0,
19124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19125        // GIR_Coverage, 1296,
19126        GIR_Done,
19127      // Label 1052: @48313
19128      GIM_Try, /*On fail goto*//*Label 1053*/ 48372, // Rule ID 1297 //
19129        GIM_CheckFeatures, GIFBS_HasNEON,
19130        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
19131        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19132        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19133        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19137        // (intrinsic_wo_chain:{ *:[v2i64] } 1758:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
19139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19142        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19143        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19144        GIR_EraseFromParent, /*InsnID*/0,
19145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19146        // GIR_Coverage, 1297,
19147        GIR_Done,
19148      // Label 1053: @48372
19149      GIM_Try, /*On fail goto*//*Label 1054*/ 48431, // Rule ID 1298 //
19150        GIM_CheckFeatures, GIFBS_HasNEON,
19151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19158        // (intrinsic_wo_chain:{ *:[v4i16] } 1759:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
19160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19163        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19164        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19165        GIR_EraseFromParent, /*InsnID*/0,
19166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19167        // GIR_Coverage, 1298,
19168        GIR_Done,
19169      // Label 1054: @48431
19170      GIM_Try, /*On fail goto*//*Label 1055*/ 48490, // Rule ID 1299 //
19171        GIM_CheckFeatures, GIFBS_HasNEON,
19172        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19173        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19174        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19175        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19179        // (intrinsic_wo_chain:{ *:[v2i32] } 1759:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19180        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
19181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19184        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19185        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19186        GIR_EraseFromParent, /*InsnID*/0,
19187        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19188        // GIR_Coverage, 1299,
19189        GIR_Done,
19190      // Label 1055: @48490
19191      GIM_Try, /*On fail goto*//*Label 1056*/ 48549, // Rule ID 1300 //
19192        GIM_CheckFeatures, GIFBS_HasNEON,
19193        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19194        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19195        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19196        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19200        // (intrinsic_wo_chain:{ *:[v8i16] } 1759:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19201        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
19202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19205        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19206        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19207        GIR_EraseFromParent, /*InsnID*/0,
19208        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19209        // GIR_Coverage, 1300,
19210        GIR_Done,
19211      // Label 1056: @48549
19212      GIM_Try, /*On fail goto*//*Label 1057*/ 48608, // Rule ID 1301 //
19213        GIM_CheckFeatures, GIFBS_HasNEON,
19214        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19215        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19216        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19217        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19221        // (intrinsic_wo_chain:{ *:[v4i32] } 1759:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
19223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19226        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19227        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19228        GIR_EraseFromParent, /*InsnID*/0,
19229        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19230        // GIR_Coverage, 1301,
19231        GIR_Done,
19232      // Label 1057: @48608
19233      GIM_Try, /*On fail goto*//*Label 1058*/ 48667, // Rule ID 1302 //
19234        GIM_CheckFeatures, GIFBS_HasNEON,
19235        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19236        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19237        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19238        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19242        // (intrinsic_wo_chain:{ *:[v8i8] } 1759:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
19244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19247        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19248        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19249        GIR_EraseFromParent, /*InsnID*/0,
19250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19251        // GIR_Coverage, 1302,
19252        GIR_Done,
19253      // Label 1058: @48667
19254      GIM_Try, /*On fail goto*//*Label 1059*/ 48726, // Rule ID 1303 //
19255        GIM_CheckFeatures, GIFBS_HasNEON,
19256        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19257        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19258        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19259        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19263        // (intrinsic_wo_chain:{ *:[v16i8] } 1759:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
19265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19268        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19269        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19270        GIR_EraseFromParent, /*InsnID*/0,
19271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19272        // GIR_Coverage, 1303,
19273        GIR_Done,
19274      // Label 1059: @48726
19275      GIM_Try, /*On fail goto*//*Label 1060*/ 48785, // Rule ID 1304 //
19276        GIM_CheckFeatures, GIFBS_HasNEON,
19277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19284        // (intrinsic_wo_chain:{ *:[v1i64] } 1759:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19285        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
19286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19289        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19290        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19291        GIR_EraseFromParent, /*InsnID*/0,
19292        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19293        // GIR_Coverage, 1304,
19294        GIR_Done,
19295      // Label 1060: @48785
19296      GIM_Try, /*On fail goto*//*Label 1061*/ 48844, // Rule ID 1305 //
19297        GIM_CheckFeatures, GIFBS_HasNEON,
19298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
19299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19300        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19301        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19305        // (intrinsic_wo_chain:{ *:[v2i64] } 1759:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
19307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19310        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19311        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19312        GIR_EraseFromParent, /*InsnID*/0,
19313        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19314        // GIR_Coverage, 1305,
19315        GIR_Done,
19316      // Label 1061: @48844
19317      GIM_Try, /*On fail goto*//*Label 1062*/ 48903, // Rule ID 1339 //
19318        GIM_CheckFeatures, GIFBS_HasNEON,
19319        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19320        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19321        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19322        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19326        // (intrinsic_wo_chain:{ *:[v4i16] } 1752:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19327        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
19328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19331        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19332        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19333        GIR_EraseFromParent, /*InsnID*/0,
19334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19335        // GIR_Coverage, 1339,
19336        GIR_Done,
19337      // Label 1062: @48903
19338      GIM_Try, /*On fail goto*//*Label 1063*/ 48962, // Rule ID 1340 //
19339        GIM_CheckFeatures, GIFBS_HasNEON,
19340        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19341        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19342        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19343        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19347        // (intrinsic_wo_chain:{ *:[v2i32] } 1752:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19348        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
19349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19352        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19353        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19354        GIR_EraseFromParent, /*InsnID*/0,
19355        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19356        // GIR_Coverage, 1340,
19357        GIR_Done,
19358      // Label 1063: @48962
19359      GIM_Try, /*On fail goto*//*Label 1064*/ 49021, // Rule ID 1341 //
19360        GIM_CheckFeatures, GIFBS_HasNEON,
19361        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19362        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19363        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19364        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19368        // (intrinsic_wo_chain:{ *:[v8i16] } 1752:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
19370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19373        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19374        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19375        GIR_EraseFromParent, /*InsnID*/0,
19376        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19377        // GIR_Coverage, 1341,
19378        GIR_Done,
19379      // Label 1064: @49021
19380      GIM_Try, /*On fail goto*//*Label 1065*/ 49080, // Rule ID 1342 //
19381        GIM_CheckFeatures, GIFBS_HasNEON,
19382        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19383        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19384        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19385        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19389        // (intrinsic_wo_chain:{ *:[v4i32] } 1752:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
19391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19394        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19395        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19396        GIR_EraseFromParent, /*InsnID*/0,
19397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19398        // GIR_Coverage, 1342,
19399        GIR_Done,
19400      // Label 1065: @49080
19401      GIM_Try, /*On fail goto*//*Label 1066*/ 49139, // Rule ID 1343 //
19402        GIM_CheckFeatures, GIFBS_HasNEON,
19403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19406        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19410        // (intrinsic_wo_chain:{ *:[v8i8] } 1752:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
19412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19416        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19417        GIR_EraseFromParent, /*InsnID*/0,
19418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19419        // GIR_Coverage, 1343,
19420        GIR_Done,
19421      // Label 1066: @49139
19422      GIM_Try, /*On fail goto*//*Label 1067*/ 49198, // Rule ID 1344 //
19423        GIM_CheckFeatures, GIFBS_HasNEON,
19424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19427        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19431        // (intrinsic_wo_chain:{ *:[v16i8] } 1752:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
19433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19436        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19437        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19438        GIR_EraseFromParent, /*InsnID*/0,
19439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19440        // GIR_Coverage, 1344,
19441        GIR_Done,
19442      // Label 1067: @49198
19443      GIM_Try, /*On fail goto*//*Label 1068*/ 49257, // Rule ID 1345 //
19444        GIM_CheckFeatures, GIFBS_HasNEON,
19445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19452        // (intrinsic_wo_chain:{ *:[v1i64] } 1752:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
19454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19457        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19458        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19459        GIR_EraseFromParent, /*InsnID*/0,
19460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19461        // GIR_Coverage, 1345,
19462        GIR_Done,
19463      // Label 1068: @49257
19464      GIM_Try, /*On fail goto*//*Label 1069*/ 49316, // Rule ID 1346 //
19465        GIM_CheckFeatures, GIFBS_HasNEON,
19466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
19467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19469        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19473        // (intrinsic_wo_chain:{ *:[v2i64] } 1752:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
19475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19478        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19479        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19480        GIR_EraseFromParent, /*InsnID*/0,
19481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19482        // GIR_Coverage, 1346,
19483        GIR_Done,
19484      // Label 1069: @49316
19485      GIM_Try, /*On fail goto*//*Label 1070*/ 49375, // Rule ID 1347 //
19486        GIM_CheckFeatures, GIFBS_HasNEON,
19487        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19488        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19489        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19490        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19494        // (intrinsic_wo_chain:{ *:[v4i16] } 1753:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16,
19496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19499        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19500        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19501        GIR_EraseFromParent, /*InsnID*/0,
19502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19503        // GIR_Coverage, 1347,
19504        GIR_Done,
19505      // Label 1070: @49375
19506      GIM_Try, /*On fail goto*//*Label 1071*/ 49434, // Rule ID 1348 //
19507        GIM_CheckFeatures, GIFBS_HasNEON,
19508        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19509        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19510        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19511        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19515        // (intrinsic_wo_chain:{ *:[v2i32] } 1753:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19516        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32,
19517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19520        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19521        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19522        GIR_EraseFromParent, /*InsnID*/0,
19523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19524        // GIR_Coverage, 1348,
19525        GIR_Done,
19526      // Label 1071: @49434
19527      GIM_Try, /*On fail goto*//*Label 1072*/ 49493, // Rule ID 1349 //
19528        GIM_CheckFeatures, GIFBS_HasNEON,
19529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19536        // (intrinsic_wo_chain:{ *:[v8i16] } 1753:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19537        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16,
19538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19541        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19542        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19543        GIR_EraseFromParent, /*InsnID*/0,
19544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19545        // GIR_Coverage, 1349,
19546        GIR_Done,
19547      // Label 1072: @49493
19548      GIM_Try, /*On fail goto*//*Label 1073*/ 49552, // Rule ID 1350 //
19549        GIM_CheckFeatures, GIFBS_HasNEON,
19550        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19551        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19552        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19553        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19557        // (intrinsic_wo_chain:{ *:[v4i32] } 1753:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32,
19559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19562        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19563        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19564        GIR_EraseFromParent, /*InsnID*/0,
19565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19566        // GIR_Coverage, 1350,
19567        GIR_Done,
19568      // Label 1073: @49552
19569      GIM_Try, /*On fail goto*//*Label 1074*/ 49611, // Rule ID 1351 //
19570        GIM_CheckFeatures, GIFBS_HasNEON,
19571        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19578        // (intrinsic_wo_chain:{ *:[v8i8] } 1753:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8,
19580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19583        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19584        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19585        GIR_EraseFromParent, /*InsnID*/0,
19586        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19587        // GIR_Coverage, 1351,
19588        GIR_Done,
19589      // Label 1074: @49611
19590      GIM_Try, /*On fail goto*//*Label 1075*/ 49670, // Rule ID 1352 //
19591        GIM_CheckFeatures, GIFBS_HasNEON,
19592        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19593        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19594        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19595        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19599        // (intrinsic_wo_chain:{ *:[v16i8] } 1753:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19600        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8,
19601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19604        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19605        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19606        GIR_EraseFromParent, /*InsnID*/0,
19607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19608        // GIR_Coverage, 1352,
19609        GIR_Done,
19610      // Label 1075: @49670
19611      GIM_Try, /*On fail goto*//*Label 1076*/ 49729, // Rule ID 1353 //
19612        GIM_CheckFeatures, GIFBS_HasNEON,
19613        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19614        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19615        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19616        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19620        // (intrinsic_wo_chain:{ *:[v1i64] } 1753:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64,
19622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19625        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19626        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19627        GIR_EraseFromParent, /*InsnID*/0,
19628        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19629        // GIR_Coverage, 1353,
19630        GIR_Done,
19631      // Label 1076: @49729
19632      GIM_Try, /*On fail goto*//*Label 1077*/ 49788, // Rule ID 1354 //
19633        GIM_CheckFeatures, GIFBS_HasNEON,
19634        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
19635        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19636        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19637        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19641        // (intrinsic_wo_chain:{ *:[v2i64] } 1753:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64,
19643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19647        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19648        GIR_EraseFromParent, /*InsnID*/0,
19649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19650        // GIR_Coverage, 1354,
19651        GIR_Done,
19652      // Label 1077: @49788
19653      GIM_Try, /*On fail goto*//*Label 1078*/ 49847, // Rule ID 1374 //
19654        GIM_CheckFeatures, GIFBS_HasNEON,
19655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19658        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19662        // (intrinsic_wo_chain:{ *:[v4i16] } 1737:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16,
19664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19668        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19669        GIR_EraseFromParent, /*InsnID*/0,
19670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19671        // GIR_Coverage, 1374,
19672        GIR_Done,
19673      // Label 1078: @49847
19674      GIM_Try, /*On fail goto*//*Label 1079*/ 49906, // Rule ID 1375 //
19675        GIM_CheckFeatures, GIFBS_HasNEON,
19676        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19677        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19678        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19679        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19683        // (intrinsic_wo_chain:{ *:[v2i32] } 1737:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19684        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32,
19685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19688        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19689        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19690        GIR_EraseFromParent, /*InsnID*/0,
19691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19692        // GIR_Coverage, 1375,
19693        GIR_Done,
19694      // Label 1079: @49906
19695      GIM_Try, /*On fail goto*//*Label 1080*/ 49965, // Rule ID 1376 //
19696        GIM_CheckFeatures, GIFBS_HasNEON,
19697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19704        // (intrinsic_wo_chain:{ *:[v8i16] } 1737:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16,
19706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19709        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19710        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19711        GIR_EraseFromParent, /*InsnID*/0,
19712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19713        // GIR_Coverage, 1376,
19714        GIR_Done,
19715      // Label 1080: @49965
19716      GIM_Try, /*On fail goto*//*Label 1081*/ 50024, // Rule ID 1377 //
19717        GIM_CheckFeatures, GIFBS_HasNEON,
19718        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19719        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19720        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19721        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19725        // (intrinsic_wo_chain:{ *:[v4i32] } 1737:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32,
19727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19730        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19731        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19732        GIR_EraseFromParent, /*InsnID*/0,
19733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19734        // GIR_Coverage, 1377,
19735        GIR_Done,
19736      // Label 1081: @50024
19737      GIM_Try, /*On fail goto*//*Label 1082*/ 50083, // Rule ID 1378 //
19738        GIM_CheckFeatures, GIFBS_HasNEON,
19739        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19740        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19741        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19742        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19746        // (intrinsic_wo_chain:{ *:[v8i8] } 1737:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19747        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8,
19748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19751        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19752        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19753        GIR_EraseFromParent, /*InsnID*/0,
19754        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19755        // GIR_Coverage, 1378,
19756        GIR_Done,
19757      // Label 1082: @50083
19758      GIM_Try, /*On fail goto*//*Label 1083*/ 50142, // Rule ID 1379 //
19759        GIM_CheckFeatures, GIFBS_HasNEON,
19760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19761        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19762        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19763        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19767        // (intrinsic_wo_chain:{ *:[v16i8] } 1737:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19768        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8,
19769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19772        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19773        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19774        GIR_EraseFromParent, /*InsnID*/0,
19775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19776        // GIR_Coverage, 1379,
19777        GIR_Done,
19778      // Label 1083: @50142
19779      GIM_Try, /*On fail goto*//*Label 1084*/ 50201, // Rule ID 1380 //
19780        GIM_CheckFeatures, GIFBS_HasNEON,
19781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19784        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19788        // (intrinsic_wo_chain:{ *:[v1i64] } 1737:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19789        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64,
19790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19793        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19794        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19795        GIR_EraseFromParent, /*InsnID*/0,
19796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19797        // GIR_Coverage, 1380,
19798        GIR_Done,
19799      // Label 1084: @50201
19800      GIM_Try, /*On fail goto*//*Label 1085*/ 50260, // Rule ID 1381 //
19801        GIM_CheckFeatures, GIFBS_HasNEON,
19802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
19803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19805        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19809        // (intrinsic_wo_chain:{ *:[v2i64] } 1737:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64,
19811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19815        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19816        GIR_EraseFromParent, /*InsnID*/0,
19817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19818        // GIR_Coverage, 1381,
19819        GIR_Done,
19820      // Label 1085: @50260
19821      GIM_Try, /*On fail goto*//*Label 1086*/ 50319, // Rule ID 1382 //
19822        GIM_CheckFeatures, GIFBS_HasNEON,
19823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19826        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19830        // (intrinsic_wo_chain:{ *:[v4i16] } 1739:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16,
19832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19836        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19837        GIR_EraseFromParent, /*InsnID*/0,
19838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19839        // GIR_Coverage, 1382,
19840        GIR_Done,
19841      // Label 1086: @50319
19842      GIM_Try, /*On fail goto*//*Label 1087*/ 50378, // Rule ID 1383 //
19843        GIM_CheckFeatures, GIFBS_HasNEON,
19844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19847        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19851        // (intrinsic_wo_chain:{ *:[v2i32] } 1739:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
19852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32,
19853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19857        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19858        GIR_EraseFromParent, /*InsnID*/0,
19859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19860        // GIR_Coverage, 1383,
19861        GIR_Done,
19862      // Label 1087: @50378
19863      GIM_Try, /*On fail goto*//*Label 1088*/ 50437, // Rule ID 1384 //
19864        GIM_CheckFeatures, GIFBS_HasNEON,
19865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19872        // (intrinsic_wo_chain:{ *:[v8i16] } 1739:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
19873        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16,
19874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19877        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19878        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19879        GIR_EraseFromParent, /*InsnID*/0,
19880        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19881        // GIR_Coverage, 1384,
19882        GIR_Done,
19883      // Label 1088: @50437
19884      GIM_Try, /*On fail goto*//*Label 1089*/ 50496, // Rule ID 1385 //
19885        GIM_CheckFeatures, GIFBS_HasNEON,
19886        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19887        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19888        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19889        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19893        // (intrinsic_wo_chain:{ *:[v4i32] } 1739:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
19894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32,
19895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19899        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19900        GIR_EraseFromParent, /*InsnID*/0,
19901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19902        // GIR_Coverage, 1385,
19903        GIR_Done,
19904      // Label 1089: @50496
19905      GIM_Try, /*On fail goto*//*Label 1090*/ 50555, // Rule ID 1386 //
19906        GIM_CheckFeatures, GIFBS_HasNEON,
19907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19914        // (intrinsic_wo_chain:{ *:[v8i8] } 1739:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
19915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8,
19916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19920        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19921        GIR_EraseFromParent, /*InsnID*/0,
19922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19923        // GIR_Coverage, 1386,
19924        GIR_Done,
19925      // Label 1090: @50555
19926      GIM_Try, /*On fail goto*//*Label 1091*/ 50614, // Rule ID 1387 //
19927        GIM_CheckFeatures, GIFBS_HasNEON,
19928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19931        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19935        // (intrinsic_wo_chain:{ *:[v16i8] } 1739:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
19936        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8,
19937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19940        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19941        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19942        GIR_EraseFromParent, /*InsnID*/0,
19943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19944        // GIR_Coverage, 1387,
19945        GIR_Done,
19946      // Label 1091: @50614
19947      GIM_Try, /*On fail goto*//*Label 1092*/ 50673, // Rule ID 1388 //
19948        GIM_CheckFeatures, GIFBS_HasNEON,
19949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19956        // (intrinsic_wo_chain:{ *:[v1i64] } 1739:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
19957        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64,
19958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19962        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19963        GIR_EraseFromParent, /*InsnID*/0,
19964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19965        // GIR_Coverage, 1388,
19966        GIR_Done,
19967      // Label 1092: @50673
19968      GIM_Try, /*On fail goto*//*Label 1093*/ 50732, // Rule ID 1389 //
19969        GIM_CheckFeatures, GIFBS_HasNEON,
19970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
19971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19973        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19977        // (intrinsic_wo_chain:{ *:[v2i64] } 1739:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
19978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64,
19979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
19981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19982        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19983        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
19984        GIR_EraseFromParent, /*InsnID*/0,
19985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19986        // GIR_Coverage, 1389,
19987        GIR_Done,
19988      // Label 1093: @50732
19989      GIM_Try, /*On fail goto*//*Label 1094*/ 50791, // Rule ID 1423 //
19990        GIM_CheckFeatures, GIFBS_HasNEON,
19991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
19992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19994        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19998        // (intrinsic_wo_chain:{ *:[v4i16] } 1732:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
19999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16,
20000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20003        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20004        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20005        GIR_EraseFromParent, /*InsnID*/0,
20006        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20007        // GIR_Coverage, 1423,
20008        GIR_Done,
20009      // Label 1094: @50791
20010      GIM_Try, /*On fail goto*//*Label 1095*/ 50850, // Rule ID 1424 //
20011        GIM_CheckFeatures, GIFBS_HasNEON,
20012        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20013        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20014        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20015        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20019        // (intrinsic_wo_chain:{ *:[v2i32] } 1732:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
20020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32,
20021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20024        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20025        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20026        GIR_EraseFromParent, /*InsnID*/0,
20027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20028        // GIR_Coverage, 1424,
20029        GIR_Done,
20030      // Label 1095: @50850
20031      GIM_Try, /*On fail goto*//*Label 1096*/ 50909, // Rule ID 1425 //
20032        GIM_CheckFeatures, GIFBS_HasNEON,
20033        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20034        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20035        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20036        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20040        // (intrinsic_wo_chain:{ *:[v8i16] } 1732:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
20041        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16,
20042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20046        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20047        GIR_EraseFromParent, /*InsnID*/0,
20048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20049        // GIR_Coverage, 1425,
20050        GIR_Done,
20051      // Label 1096: @50909
20052      GIM_Try, /*On fail goto*//*Label 1097*/ 50968, // Rule ID 1426 //
20053        GIM_CheckFeatures, GIFBS_HasNEON,
20054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20057        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20061        // (intrinsic_wo_chain:{ *:[v4i32] } 1732:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
20062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32,
20063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20067        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20068        GIR_EraseFromParent, /*InsnID*/0,
20069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20070        // GIR_Coverage, 1426,
20071        GIR_Done,
20072      // Label 1097: @50968
20073      GIM_Try, /*On fail goto*//*Label 1098*/ 51027, // Rule ID 1427 //
20074        GIM_CheckFeatures, GIFBS_HasNEON,
20075        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20076        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20077        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20078        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20082        // (intrinsic_wo_chain:{ *:[v8i8] } 1732:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
20083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8,
20084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20088        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20089        GIR_EraseFromParent, /*InsnID*/0,
20090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20091        // GIR_Coverage, 1427,
20092        GIR_Done,
20093      // Label 1098: @51027
20094      GIM_Try, /*On fail goto*//*Label 1099*/ 51086, // Rule ID 1428 //
20095        GIM_CheckFeatures, GIFBS_HasNEON,
20096        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20097        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20098        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20099        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20103        // (intrinsic_wo_chain:{ *:[v16i8] } 1732:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
20104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8,
20105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20109        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20110        GIR_EraseFromParent, /*InsnID*/0,
20111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20112        // GIR_Coverage, 1428,
20113        GIR_Done,
20114      // Label 1099: @51086
20115      GIM_Try, /*On fail goto*//*Label 1100*/ 51145, // Rule ID 1429 //
20116        GIM_CheckFeatures, GIFBS_HasNEON,
20117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
20119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20124        // (intrinsic_wo_chain:{ *:[v1i64] } 1732:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
20125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64,
20126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20129        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20130        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20131        GIR_EraseFromParent, /*InsnID*/0,
20132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20133        // GIR_Coverage, 1429,
20134        GIR_Done,
20135      // Label 1100: @51145
20136      GIM_Try, /*On fail goto*//*Label 1101*/ 51204, // Rule ID 1430 //
20137        GIM_CheckFeatures, GIFBS_HasNEON,
20138        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
20139        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20140        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20141        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
20142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20145        // (intrinsic_wo_chain:{ *:[v2i64] } 1732:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
20146        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64,
20147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20150        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20151        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20152        GIR_EraseFromParent, /*InsnID*/0,
20153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20154        // GIR_Coverage, 1430,
20155        GIR_Done,
20156      // Label 1101: @51204
20157      GIM_Try, /*On fail goto*//*Label 1102*/ 51263, // Rule ID 1431 //
20158        GIM_CheckFeatures, GIFBS_HasNEON,
20159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20166        // (intrinsic_wo_chain:{ *:[v4i16] } 1733:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
20167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16,
20168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20171        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20172        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20173        GIR_EraseFromParent, /*InsnID*/0,
20174        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20175        // GIR_Coverage, 1431,
20176        GIR_Done,
20177      // Label 1102: @51263
20178      GIM_Try, /*On fail goto*//*Label 1103*/ 51322, // Rule ID 1432 //
20179        GIM_CheckFeatures, GIFBS_HasNEON,
20180        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20181        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20182        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20183        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20187        // (intrinsic_wo_chain:{ *:[v2i32] } 1733:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
20188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32,
20189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20192        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20193        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20194        GIR_EraseFromParent, /*InsnID*/0,
20195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20196        // GIR_Coverage, 1432,
20197        GIR_Done,
20198      // Label 1103: @51322
20199      GIM_Try, /*On fail goto*//*Label 1104*/ 51381, // Rule ID 1433 //
20200        GIM_CheckFeatures, GIFBS_HasNEON,
20201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20208        // (intrinsic_wo_chain:{ *:[v8i16] } 1733:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
20209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16,
20210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20214        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20215        GIR_EraseFromParent, /*InsnID*/0,
20216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20217        // GIR_Coverage, 1433,
20218        GIR_Done,
20219      // Label 1104: @51381
20220      GIM_Try, /*On fail goto*//*Label 1105*/ 51440, // Rule ID 1434 //
20221        GIM_CheckFeatures, GIFBS_HasNEON,
20222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20229        // (intrinsic_wo_chain:{ *:[v4i32] } 1733:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
20230        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32,
20231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20234        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20235        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20236        GIR_EraseFromParent, /*InsnID*/0,
20237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20238        // GIR_Coverage, 1434,
20239        GIR_Done,
20240      // Label 1105: @51440
20241      GIM_Try, /*On fail goto*//*Label 1106*/ 51499, // Rule ID 1435 //
20242        GIM_CheckFeatures, GIFBS_HasNEON,
20243        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20244        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20245        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20246        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20250        // (intrinsic_wo_chain:{ *:[v8i8] } 1733:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
20251        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8,
20252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20255        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20256        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20257        GIR_EraseFromParent, /*InsnID*/0,
20258        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20259        // GIR_Coverage, 1435,
20260        GIR_Done,
20261      // Label 1106: @51499
20262      GIM_Try, /*On fail goto*//*Label 1107*/ 51558, // Rule ID 1436 //
20263        GIM_CheckFeatures, GIFBS_HasNEON,
20264        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20265        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20266        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20267        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20271        // (intrinsic_wo_chain:{ *:[v16i8] } 1733:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
20272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8,
20273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20276        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20277        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20278        GIR_EraseFromParent, /*InsnID*/0,
20279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20280        // GIR_Coverage, 1436,
20281        GIR_Done,
20282      // Label 1107: @51558
20283      GIM_Try, /*On fail goto*//*Label 1108*/ 51617, // Rule ID 1437 //
20284        GIM_CheckFeatures, GIFBS_HasNEON,
20285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
20287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20292        // (intrinsic_wo_chain:{ *:[v1i64] } 1733:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
20293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64,
20294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20297        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20298        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20299        GIR_EraseFromParent, /*InsnID*/0,
20300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20301        // GIR_Coverage, 1437,
20302        GIR_Done,
20303      // Label 1108: @51617
20304      GIM_Try, /*On fail goto*//*Label 1109*/ 51676, // Rule ID 1438 //
20305        GIM_CheckFeatures, GIFBS_HasNEON,
20306        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
20307        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20308        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20309        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
20310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20313        // (intrinsic_wo_chain:{ *:[v2i64] } 1733:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
20314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64,
20315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
20317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
20318        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20319        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20320        GIR_EraseFromParent, /*InsnID*/0,
20321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20322        // GIR_Coverage, 1438,
20323        GIR_Done,
20324      // Label 1109: @51676
20325      GIM_Try, /*On fail goto*//*Label 1110*/ 51728, // Rule ID 1703 //
20326        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
20327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesd,
20328        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20334        // (intrinsic_wo_chain:{ *:[v16i8] } 1646:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
20335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD,
20336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
20338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20339        GIR_EraseFromParent, /*InsnID*/0,
20340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20341        // GIR_Coverage, 1703,
20342        GIR_Done,
20343      // Label 1110: @51728
20344      GIM_Try, /*On fail goto*//*Label 1111*/ 51780, // Rule ID 1704 //
20345        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
20346        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aese,
20347        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20348        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20349        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20353        // (intrinsic_wo_chain:{ *:[v16i8] } 1647:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
20354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE,
20355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
20357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20358        GIR_EraseFromParent, /*InsnID*/0,
20359        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20360        // GIR_Coverage, 1704,
20361        GIR_Done,
20362      // Label 1111: @51780
20363      GIM_Try, /*On fail goto*//*Label 1112*/ 51832, // Rule ID 1707 //
20364        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
20365        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su1,
20366        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20367        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20368        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20372        // (intrinsic_wo_chain:{ *:[v4i32] } 1656:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
20373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1,
20374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
20376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20377        GIR_EraseFromParent, /*InsnID*/0,
20378        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20379        // GIR_Coverage, 1707,
20380        GIR_Done,
20381      // Label 1112: @51832
20382      GIM_Try, /*On fail goto*//*Label 1113*/ 51884, // Rule ID 1708 //
20383        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
20384        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su0,
20385        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20386        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20387        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20391        // (intrinsic_wo_chain:{ *:[v4i32] } 1659:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
20392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0,
20393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
20395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20396        GIR_EraseFromParent, /*InsnID*/0,
20397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20398        // GIR_Coverage, 1708,
20399        GIR_Done,
20400      // Label 1113: @51884
20401      GIM_Try, /*On fail goto*//*Label 1114*/ 51943, // Rule ID 1717 //
20402        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
20403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqrshr,
20404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20406        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20410        // (intrinsic_wo_chain:{ *:[i32] } 1567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
20411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQRSHR,
20412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
20414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20416        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20417        GIR_EraseFromParent, /*InsnID*/0,
20418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20419        // GIR_Coverage, 1717,
20420        GIR_Done,
20421      // Label 1114: @51943
20422      GIM_Try, /*On fail goto*//*Label 1115*/ 52002, // Rule ID 1718 //
20423        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
20424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqrshl,
20425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20427        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20431        // (intrinsic_wo_chain:{ *:[i32] } 1574:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
20432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQRSHL,
20433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
20435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20436        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20437        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20438        GIR_EraseFromParent, /*InsnID*/0,
20439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20440        // GIR_Coverage, 1718,
20441        GIR_Done,
20442      // Label 1115: @52002
20443      GIM_Try, /*On fail goto*//*Label 1116*/ 52061, // Rule ID 1834 //
20444        GIM_CheckFeatures, GIFBS_HasMVEInt,
20445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s,
20446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20452        // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
20453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs16,
20454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20457        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20458        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20459        GIR_EraseFromParent, /*InsnID*/0,
20460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20461        // GIR_Coverage, 1834,
20462        GIR_Done,
20463      // Label 1116: @52061
20464      GIM_Try, /*On fail goto*//*Label 1117*/ 52120, // Rule ID 1835 //
20465        GIM_CheckFeatures, GIFBS_HasMVEInt,
20466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s,
20467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20469        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20473        // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
20474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs32,
20475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20478        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20479        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20480        GIR_EraseFromParent, /*InsnID*/0,
20481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20482        // GIR_Coverage, 1835,
20483        GIR_Done,
20484      // Label 1117: @52120
20485      GIM_Try, /*On fail goto*//*Label 1118*/ 52179, // Rule ID 1836 //
20486        GIM_CheckFeatures, GIFBS_HasMVEInt,
20487        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s,
20488        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20489        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20490        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20494        // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
20495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs8,
20496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20499        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20500        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20501        GIR_EraseFromParent, /*InsnID*/0,
20502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20503        // GIR_Coverage, 1836,
20504        GIR_Done,
20505      // Label 1118: @52179
20506      GIM_Try, /*On fail goto*//*Label 1119*/ 52238, // Rule ID 1837 //
20507        GIM_CheckFeatures, GIFBS_HasMVEInt,
20508        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u,
20509        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20510        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20511        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20515        // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
20516        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu16,
20517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20520        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20521        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20522        GIR_EraseFromParent, /*InsnID*/0,
20523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20524        // GIR_Coverage, 1837,
20525        GIR_Done,
20526      // Label 1119: @52238
20527      GIM_Try, /*On fail goto*//*Label 1120*/ 52297, // Rule ID 1838 //
20528        GIM_CheckFeatures, GIFBS_HasMVEInt,
20529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u,
20530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20536        // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
20537        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu32,
20538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20541        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20542        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20543        GIR_EraseFromParent, /*InsnID*/0,
20544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20545        // GIR_Coverage, 1838,
20546        GIR_Done,
20547      // Label 1120: @52297
20548      GIM_Try, /*On fail goto*//*Label 1121*/ 52356, // Rule ID 1839 //
20549        GIM_CheckFeatures, GIFBS_HasMVEInt,
20550        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u,
20551        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20552        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20553        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20557        // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
20558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu8,
20559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20562        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20563        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20564        GIR_EraseFromParent, /*InsnID*/0,
20565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20566        // GIR_Coverage, 1839,
20567        GIR_Done,
20568      // Label 1121: @52356
20569      GIM_Try, /*On fail goto*//*Label 1122*/ 52415, // Rule ID 1840 //
20570        GIM_CheckFeatures, GIFBS_HasMVEInt,
20571        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s,
20572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20578        // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
20579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs16,
20580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20583        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20584        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20585        GIR_EraseFromParent, /*InsnID*/0,
20586        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20587        // GIR_Coverage, 1840,
20588        GIR_Done,
20589      // Label 1122: @52415
20590      GIM_Try, /*On fail goto*//*Label 1123*/ 52474, // Rule ID 1841 //
20591        GIM_CheckFeatures, GIFBS_HasMVEInt,
20592        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s,
20593        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20594        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20595        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20599        // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
20600        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs32,
20601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20604        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20605        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20606        GIR_EraseFromParent, /*InsnID*/0,
20607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20608        // GIR_Coverage, 1841,
20609        GIR_Done,
20610      // Label 1123: @52474
20611      GIM_Try, /*On fail goto*//*Label 1124*/ 52533, // Rule ID 1842 //
20612        GIM_CheckFeatures, GIFBS_HasMVEInt,
20613        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s,
20614        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20615        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20616        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20620        // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
20621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs8,
20622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20625        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20626        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20627        GIR_EraseFromParent, /*InsnID*/0,
20628        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20629        // GIR_Coverage, 1842,
20630        GIR_Done,
20631      // Label 1124: @52533
20632      GIM_Try, /*On fail goto*//*Label 1125*/ 52592, // Rule ID 1843 //
20633        GIM_CheckFeatures, GIFBS_HasMVEInt,
20634        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u,
20635        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20636        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20637        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20641        // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
20642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu16,
20643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20646        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20647        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20648        GIR_EraseFromParent, /*InsnID*/0,
20649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20650        // GIR_Coverage, 1843,
20651        GIR_Done,
20652      // Label 1125: @52592
20653      GIM_Try, /*On fail goto*//*Label 1126*/ 52651, // Rule ID 1844 //
20654        GIM_CheckFeatures, GIFBS_HasMVEInt,
20655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u,
20656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20658        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20662        // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
20663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu32,
20664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20667        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20668        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20669        GIR_EraseFromParent, /*InsnID*/0,
20670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20671        // GIR_Coverage, 1844,
20672        GIR_Done,
20673      // Label 1126: @52651
20674      GIM_Try, /*On fail goto*//*Label 1127*/ 52710, // Rule ID 1845 //
20675        GIM_CheckFeatures, GIFBS_HasMVEInt,
20676        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u,
20677        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20678        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20679        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
20683        // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
20684        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu8,
20685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
20686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
20687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
20688        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20689        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20690        GIR_EraseFromParent, /*InsnID*/0,
20691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20692        // GIR_Coverage, 1845,
20693        GIR_Done,
20694      // Label 1127: @52710
20695      GIM_Try, /*On fail goto*//*Label 1128*/ 52772, // Rule ID 1866 //
20696        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
20698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20704        // (intrinsic_wo_chain:{ *:[i32] } 1835:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
20705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16,
20706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
20708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
20709        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20710        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20711        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20712        GIR_EraseFromParent, /*InsnID*/0,
20713        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20714        // GIR_Coverage, 1866,
20715        GIR_Done,
20716      // Label 1128: @52772
20717      GIM_Try, /*On fail goto*//*Label 1129*/ 52834, // Rule ID 1873 //
20718        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20719        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
20720        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20721        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20722        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20726        // (intrinsic_wo_chain:{ *:[i32] } 1860:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
20727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16,
20728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
20730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
20731        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20732        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20733        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20734        GIR_EraseFromParent, /*InsnID*/0,
20735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20736        // GIR_Coverage, 1873,
20737        GIR_Done,
20738      // Label 1129: @52834
20739      GIM_Try, /*On fail goto*//*Label 1130*/ 52893, // Rule ID 1912 //
20740        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20741        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
20742        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20743        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20744        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
20747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20748        // (intrinsic_wo_chain:{ *:[i32] } 1811:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20749        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD,
20750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20753        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20754        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20755        GIR_EraseFromParent, /*InsnID*/0,
20756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20757        // GIR_Coverage, 1912,
20758        GIR_Done,
20759      // Label 1130: @52893
20760      GIM_Try, /*On fail goto*//*Label 1131*/ 52952, // Rule ID 1913 //
20761        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20762        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
20763        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20764        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20765        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
20768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20769        // (intrinsic_wo_chain:{ *:[i32] } 1812:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX,
20771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20774        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20775        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20776        GIR_EraseFromParent, /*InsnID*/0,
20777        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20778        // GIR_Coverage, 1913,
20779        GIR_Done,
20780      // Label 1131: @52952
20781      GIM_Try, /*On fail goto*//*Label 1132*/ 53011, // Rule ID 1914 //
20782        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20783        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
20784        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20785        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20786        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
20789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20790        // (intrinsic_wo_chain:{ *:[i32] } 1819:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD,
20792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20795        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20796        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20797        GIR_EraseFromParent, /*InsnID*/0,
20798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20799        // GIR_Coverage, 1914,
20800        GIR_Done,
20801      // Label 1132: @53011
20802      GIM_Try, /*On fail goto*//*Label 1133*/ 53070, // Rule ID 1915 //
20803        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
20804        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
20805        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20806        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20807        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
20810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20811        // (intrinsic_wo_chain:{ *:[i32] } 1820:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20812        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX,
20813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20816        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20817        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20818        GIR_EraseFromParent, /*InsnID*/0,
20819        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20820        // GIR_Coverage, 1915,
20821        GIR_Done,
20822      // Label 1133: @53070
20823      GIM_Try, /*On fail goto*//*Label 1134*/ 53129, // Rule ID 1974 //
20824        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20825        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
20826        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20827        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20828        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20832        // (intrinsic_wo_chain:{ *:[i32] } 1813:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20833        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB,
20834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20837        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20838        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20839        GIR_EraseFromParent, /*InsnID*/0,
20840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20841        // GIR_Coverage, 1974,
20842        GIR_Done,
20843      // Label 1134: @53129
20844      GIM_Try, /*On fail goto*//*Label 1135*/ 53188, // Rule ID 1975 //
20845        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20846        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
20847        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20848        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20849        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20853        // (intrinsic_wo_chain:{ *:[i32] } 1814:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT,
20855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20858        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20859        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20860        GIR_EraseFromParent, /*InsnID*/0,
20861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20862        // GIR_Coverage, 1975,
20863        GIR_Done,
20864      // Label 1135: @53188
20865      GIM_Try, /*On fail goto*//*Label 1136*/ 53247, // Rule ID 1976 //
20866        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20867        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
20868        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20869        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20870        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20874        // (intrinsic_wo_chain:{ *:[i32] } 1815:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20875        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB,
20876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20879        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20880        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20881        GIR_EraseFromParent, /*InsnID*/0,
20882        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20883        // GIR_Coverage, 1976,
20884        GIR_Done,
20885      // Label 1136: @53247
20886      GIM_Try, /*On fail goto*//*Label 1137*/ 53306, // Rule ID 1977 //
20887        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20888        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
20889        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20890        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20891        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20895        // (intrinsic_wo_chain:{ *:[i32] } 1816:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20896        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
20897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20900        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20901        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20902        GIR_EraseFromParent, /*InsnID*/0,
20903        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20904        // GIR_Coverage, 1977,
20905        GIR_Done,
20906      // Label 1137: @53306
20907      GIM_Try, /*On fail goto*//*Label 1138*/ 53365, // Rule ID 1978 //
20908        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20909        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
20910        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20911        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20912        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20916        // (intrinsic_wo_chain:{ *:[i32] } 1817:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20917        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB,
20918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20921        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20922        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20923        GIR_EraseFromParent, /*InsnID*/0,
20924        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20925        // GIR_Coverage, 1978,
20926        GIR_Done,
20927      // Label 1138: @53365
20928      GIM_Try, /*On fail goto*//*Label 1139*/ 53424, // Rule ID 1979 //
20929        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
20930        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
20931        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20932        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20933        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20937        // (intrinsic_wo_chain:{ *:[i32] } 1818:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
20938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT,
20939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
20941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
20942        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20943        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20944        GIR_EraseFromParent, /*InsnID*/0,
20945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20946        // GIR_Coverage, 1979,
20947        GIR_Done,
20948      // Label 1139: @53424
20949      GIM_Try, /*On fail goto*//*Label 1140*/ 53486, // Rule ID 2082 //
20950        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20951        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
20952        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20953        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20954        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20958        // (intrinsic_wo_chain:{ *:[i32] } 1835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
20959        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16,
20960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20963        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
20964        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20965        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20966        GIR_EraseFromParent, /*InsnID*/0,
20967        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20968        // GIR_Coverage, 2082,
20969        GIR_Done,
20970      // Label 1140: @53486
20971      GIM_Try, /*On fail goto*//*Label 1141*/ 53545, // Rule ID 2115 //
20972        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20973        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
20974        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20975        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20976        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20980        // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
20981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
20982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
20984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
20985        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20986        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
20987        GIR_EraseFromParent, /*InsnID*/0,
20988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20989        // GIR_Coverage, 2115,
20990        GIR_Done,
20991      // Label 1141: @53545
20992      GIM_Try, /*On fail goto*//*Label 1142*/ 53604, // Rule ID 2116 //
20993        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
20995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20997        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21001        // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
21002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
21003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
21005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
21006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21008        GIR_EraseFromParent, /*InsnID*/0,
21009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21010        // GIR_Coverage, 2116,
21011        GIR_Done,
21012      // Label 1142: @53604
21013      GIM_Try, /*On fail goto*//*Label 1143*/ 53663, // Rule ID 2144 //
21014        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
21016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21022        // (intrinsic_wo_chain:{ *:[i32] } 1813:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB,
21024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21028        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21029        GIR_EraseFromParent, /*InsnID*/0,
21030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21031        // GIR_Coverage, 2144,
21032        GIR_Done,
21033      // Label 1143: @53663
21034      GIM_Try, /*On fail goto*//*Label 1144*/ 53722, // Rule ID 2145 //
21035        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
21037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21039        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21043        // (intrinsic_wo_chain:{ *:[i32] } 1814:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21044        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT,
21045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21048        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21049        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21050        GIR_EraseFromParent, /*InsnID*/0,
21051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21052        // GIR_Coverage, 2145,
21053        GIR_Done,
21054      // Label 1144: @53722
21055      GIM_Try, /*On fail goto*//*Label 1145*/ 53781, // Rule ID 2146 //
21056        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21057        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
21058        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21059        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21060        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21064        // (intrinsic_wo_chain:{ *:[i32] } 1815:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21065        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB,
21066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21069        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21070        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21071        GIR_EraseFromParent, /*InsnID*/0,
21072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21073        // GIR_Coverage, 2146,
21074        GIR_Done,
21075      // Label 1145: @53781
21076      GIM_Try, /*On fail goto*//*Label 1146*/ 53840, // Rule ID 2147 //
21077        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21078        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
21079        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21080        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21081        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21085        // (intrinsic_wo_chain:{ *:[i32] } 1816:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21086        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
21087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21090        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21091        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21092        GIR_EraseFromParent, /*InsnID*/0,
21093        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21094        // GIR_Coverage, 2147,
21095        GIR_Done,
21096      // Label 1146: @53840
21097      GIM_Try, /*On fail goto*//*Label 1147*/ 53899, // Rule ID 2148 //
21098        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21099        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
21100        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21101        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21102        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21106        // (intrinsic_wo_chain:{ *:[i32] } 1817:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21107        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB,
21108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21111        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21112        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21113        GIR_EraseFromParent, /*InsnID*/0,
21114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21115        // GIR_Coverage, 2148,
21116        GIR_Done,
21117      // Label 1147: @53899
21118      GIM_Try, /*On fail goto*//*Label 1148*/ 53958, // Rule ID 2149 //
21119        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
21120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
21121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21123        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21127        // (intrinsic_wo_chain:{ *:[i32] } 1818:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT,
21129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21132        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21133        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21134        GIR_EraseFromParent, /*InsnID*/0,
21135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21136        // GIR_Coverage, 2149,
21137        GIR_Done,
21138      // Label 1148: @53958
21139      GIM_Try, /*On fail goto*//*Label 1149*/ 54013, // Rule ID 2424 //
21140        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
21141        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
21142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21148        // (intrinsic_wo_chain:{ *:[v4f16] } 1669:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
21149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
21150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21153        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21154        GIR_EraseFromParent, /*InsnID*/0,
21155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21156        // GIR_Coverage, 2424,
21157        GIR_Done,
21158      // Label 1149: @54013
21159      GIM_Try, /*On fail goto*//*Label 1150*/ 54068, // Rule ID 2425 //
21160        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
21161        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
21162        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21163        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21164        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21168        // (intrinsic_wo_chain:{ *:[v4f16] } 1668:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
21169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
21170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21173        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
21174        GIR_EraseFromParent, /*InsnID*/0,
21175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21176        // GIR_Coverage, 2425,
21177        GIR_Done,
21178      // Label 1150: @54068
21179      GIM_Try, /*On fail goto*//*Label 1151*/ 54123, // Rule ID 2426 //
21180        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
21181        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
21182        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21183        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21184        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21188        // (intrinsic_wo_chain:{ *:[v8f16] } 1669:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
21189        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
21190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21193        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21194        GIR_EraseFromParent, /*InsnID*/0,
21195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21196        // GIR_Coverage, 2426,
21197        GIR_Done,
21198      // Label 1151: @54123
21199      GIM_Try, /*On fail goto*//*Label 1152*/ 54178, // Rule ID 2427 //
21200        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
21201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
21202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21208        // (intrinsic_wo_chain:{ *:[v8f16] } 1668:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
21209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
21210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21213        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
21214        GIR_EraseFromParent, /*InsnID*/0,
21215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21216        // GIR_Coverage, 2427,
21217        GIR_Done,
21218      // Label 1152: @54178
21219      GIM_Try, /*On fail goto*//*Label 1153*/ 54233, // Rule ID 2428 //
21220        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
21221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
21222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21228        // (intrinsic_wo_chain:{ *:[v2f32] } 1669:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
21229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
21230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21233        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21234        GIR_EraseFromParent, /*InsnID*/0,
21235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21236        // GIR_Coverage, 2428,
21237        GIR_Done,
21238      // Label 1153: @54233
21239      GIM_Try, /*On fail goto*//*Label 1154*/ 54288, // Rule ID 2429 //
21240        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
21241        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
21242        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21243        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21244        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21248        // (intrinsic_wo_chain:{ *:[v2f32] } 1668:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
21249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
21250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21253        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
21254        GIR_EraseFromParent, /*InsnID*/0,
21255        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21256        // GIR_Coverage, 2429,
21257        GIR_Done,
21258      // Label 1154: @54288
21259      GIM_Try, /*On fail goto*//*Label 1155*/ 54343, // Rule ID 2430 //
21260        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
21261        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
21262        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21263        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21264        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21268        // (intrinsic_wo_chain:{ *:[v4f32] } 1669:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
21269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
21270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21273        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21274        GIR_EraseFromParent, /*InsnID*/0,
21275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21276        // GIR_Coverage, 2430,
21277        GIR_Done,
21278      // Label 1155: @54343
21279      GIM_Try, /*On fail goto*//*Label 1156*/ 54398, // Rule ID 2431 //
21280        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
21281        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
21282        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21283        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21284        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21288        // (intrinsic_wo_chain:{ *:[v4f32] } 1668:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
21289        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
21290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
21293        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
21294        GIR_EraseFromParent, /*InsnID*/0,
21295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21296        // GIR_Coverage, 2431,
21297        GIR_Done,
21298      // Label 1156: @54398
21299      GIM_Try, /*On fail goto*//*Label 1157*/ 54471, // Rule ID 3004 //
21300        GIM_CheckFeatures, GIFBS_HasMVEInt,
21301        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
21302        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21303        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21304        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21308        // (intrinsic_wo_chain:{ *:[v16i8] } 1614:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
21309        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21310        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21311        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi8,
21313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21316        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21317        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21318        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21319        GIR_EraseFromParent, /*InsnID*/0,
21320        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21321        // GIR_Coverage, 3004,
21322        GIR_Done,
21323      // Label 1157: @54471
21324      GIM_Try, /*On fail goto*//*Label 1158*/ 54544, // Rule ID 3006 //
21325        GIM_CheckFeatures, GIFBS_HasMVEInt,
21326        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
21327        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21328        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21329        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21333        // (intrinsic_wo_chain:{ *:[v8i16] } 1614:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
21334        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21335        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21336        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi16,
21338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21341        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21342        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21343        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21344        GIR_EraseFromParent, /*InsnID*/0,
21345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21346        // GIR_Coverage, 3006,
21347        GIR_Done,
21348      // Label 1158: @54544
21349      GIM_Try, /*On fail goto*//*Label 1159*/ 54617, // Rule ID 3008 //
21350        GIM_CheckFeatures, GIFBS_HasMVEInt,
21351        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
21352        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21353        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21354        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21358        // (intrinsic_wo_chain:{ *:[v4i32] } 1614:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
21359        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21360        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21361        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21362        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi32,
21363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21366        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21367        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21368        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21369        GIR_EraseFromParent, /*InsnID*/0,
21370        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21371        // GIR_Coverage, 3008,
21372        GIR_Done,
21373      // Label 1159: @54617
21374      GIM_Try, /*On fail goto*//*Label 1160*/ 54690, // Rule ID 3010 //
21375        GIM_CheckFeatures, GIFBS_HasMVEInt,
21376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
21377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21378        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21379        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21383        // (intrinsic_wo_chain:{ *:[v16i8] } 1615:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
21384        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21385        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21386        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21387        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi8,
21388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21391        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21392        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21393        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21394        GIR_EraseFromParent, /*InsnID*/0,
21395        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21396        // GIR_Coverage, 3010,
21397        GIR_Done,
21398      // Label 1160: @54690
21399      GIM_Try, /*On fail goto*//*Label 1161*/ 54763, // Rule ID 3012 //
21400        GIM_CheckFeatures, GIFBS_HasMVEInt,
21401        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
21402        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21403        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21404        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21408        // (intrinsic_wo_chain:{ *:[v8i16] } 1615:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
21409        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21410        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21411        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21412        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi16,
21413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21416        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21417        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21418        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21419        GIR_EraseFromParent, /*InsnID*/0,
21420        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21421        // GIR_Coverage, 3012,
21422        GIR_Done,
21423      // Label 1161: @54763
21424      GIM_Try, /*On fail goto*//*Label 1162*/ 54836, // Rule ID 3014 //
21425        GIM_CheckFeatures, GIFBS_HasMVEInt,
21426        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
21427        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21428        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21429        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21433        // (intrinsic_wo_chain:{ *:[v4i32] } 1615:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
21434        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21435        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21436        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21437        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi32,
21438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21441        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21442        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21443        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21444        GIR_EraseFromParent, /*InsnID*/0,
21445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21446        // GIR_Coverage, 3014,
21447        GIR_Done,
21448      // Label 1162: @54836
21449      GIM_Reject,
21450    // Label 822: @54837
21451    GIM_Try, /*On fail goto*//*Label 1163*/ 63188,
21452      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
21453      GIM_Try, /*On fail goto*//*Label 1164*/ 54928, // Rule ID 3314 //
21454        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21455        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21456        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21457        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21458        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21461        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21462        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21463        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
21464        // MIs[1] Operand 1
21465        // No operand predicates
21466        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21467        GIM_CheckIsSafeToFold, /*InsnID*/1,
21468        // (intrinsic_wo_chain:{ *:[v16i8] } 1616:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
21469        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21470        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21471        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms8,
21473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21475        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21476        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21477        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21478        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21479        GIR_EraseFromParent, /*InsnID*/0,
21480        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21481        // GIR_Coverage, 3314,
21482        GIR_Done,
21483      // Label 1164: @54928
21484      GIM_Try, /*On fail goto*//*Label 1165*/ 55014, // Rule ID 3316 //
21485        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21486        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21487        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21488        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21489        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21492        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21493        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21494        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
21495        // MIs[1] Operand 1
21496        // No operand predicates
21497        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21498        GIM_CheckIsSafeToFold, /*InsnID*/1,
21499        // (intrinsic_wo_chain:{ *:[v16i8] } 1616:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
21500        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21501        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21502        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu8,
21504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21506        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21507        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21508        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21509        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21510        GIR_EraseFromParent, /*InsnID*/0,
21511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21512        // GIR_Coverage, 3316,
21513        GIR_Done,
21514      // Label 1165: @55014
21515      GIM_Try, /*On fail goto*//*Label 1166*/ 55100, // Rule ID 3318 //
21516        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21517        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21518        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21519        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21520        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21521        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21523        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21524        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21525        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
21526        // MIs[1] Operand 1
21527        // No operand predicates
21528        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21529        GIM_CheckIsSafeToFold, /*InsnID*/1,
21530        // (intrinsic_wo_chain:{ *:[v8i16] } 1616:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
21531        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21532        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21533        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms16,
21535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21537        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21538        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21539        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21540        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21541        GIR_EraseFromParent, /*InsnID*/0,
21542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21543        // GIR_Coverage, 3318,
21544        GIR_Done,
21545      // Label 1166: @55100
21546      GIM_Try, /*On fail goto*//*Label 1167*/ 55186, // Rule ID 3320 //
21547        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21548        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21549        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21550        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21551        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21554        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21555        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21556        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
21557        // MIs[1] Operand 1
21558        // No operand predicates
21559        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21560        GIM_CheckIsSafeToFold, /*InsnID*/1,
21561        // (intrinsic_wo_chain:{ *:[v8i16] } 1616:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
21562        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21563        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21564        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21565        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu16,
21566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21568        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21569        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21570        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21571        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21572        GIR_EraseFromParent, /*InsnID*/0,
21573        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21574        // GIR_Coverage, 3320,
21575        GIR_Done,
21576      // Label 1167: @55186
21577      GIM_Try, /*On fail goto*//*Label 1168*/ 55272, // Rule ID 3322 //
21578        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21579        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21580        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21581        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21582        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21584        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21585        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21586        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21587        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
21588        // MIs[1] Operand 1
21589        // No operand predicates
21590        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21591        GIM_CheckIsSafeToFold, /*InsnID*/1,
21592        // (intrinsic_wo_chain:{ *:[v4i32] } 1616:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
21593        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21594        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21595        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms32,
21597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21599        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21600        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21601        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21602        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21603        GIR_EraseFromParent, /*InsnID*/0,
21604        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21605        // GIR_Coverage, 3322,
21606        GIR_Done,
21607      // Label 1168: @55272
21608      GIM_Try, /*On fail goto*//*Label 1169*/ 55358, // Rule ID 3324 //
21609        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
21610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21613        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21616        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21617        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21618        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
21619        // MIs[1] Operand 1
21620        // No operand predicates
21621        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21622        GIM_CheckIsSafeToFold, /*InsnID*/1,
21623        // (intrinsic_wo_chain:{ *:[v4i32] } 1616:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
21624        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21625        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21626        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu32,
21628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21630        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21631        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21632        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21633        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21634        GIR_EraseFromParent, /*InsnID*/0,
21635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21636        // GIR_Coverage, 3324,
21637        GIR_Done,
21638      // Label 1169: @55358
21639      GIM_Try, /*On fail goto*//*Label 1170*/ 55444, // Rule ID 3332 //
21640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21641        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21642        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21643        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21644        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21647        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21648        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21649        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
21650        // MIs[1] Operand 1
21651        // No operand predicates
21652        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21653        GIM_CheckIsSafeToFold, /*InsnID*/1,
21654        // (intrinsic_wo_chain:{ *:[v16i8] } 1624:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
21655        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21656        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21657        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms8,
21659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21661        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21662        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21663        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21664        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21665        GIR_EraseFromParent, /*InsnID*/0,
21666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21667        // GIR_Coverage, 3332,
21668        GIR_Done,
21669      // Label 1170: @55444
21670      GIM_Try, /*On fail goto*//*Label 1171*/ 55530, // Rule ID 3334 //
21671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21675        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21678        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21679        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21680        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
21681        // MIs[1] Operand 1
21682        // No operand predicates
21683        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21684        GIM_CheckIsSafeToFold, /*InsnID*/1,
21685        // (intrinsic_wo_chain:{ *:[v16i8] } 1624:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
21686        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21687        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21688        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21689        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu8,
21690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21692        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21693        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21694        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21695        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21696        GIR_EraseFromParent, /*InsnID*/0,
21697        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21698        // GIR_Coverage, 3334,
21699        GIR_Done,
21700      // Label 1171: @55530
21701      GIM_Try, /*On fail goto*//*Label 1172*/ 55616, // Rule ID 3336 //
21702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21706        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21709        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21710        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21711        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
21712        // MIs[1] Operand 1
21713        // No operand predicates
21714        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21715        GIM_CheckIsSafeToFold, /*InsnID*/1,
21716        // (intrinsic_wo_chain:{ *:[v8i16] } 1624:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
21717        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21718        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21719        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21720        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms16,
21721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21722        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21723        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21724        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21725        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21726        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21727        GIR_EraseFromParent, /*InsnID*/0,
21728        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21729        // GIR_Coverage, 3336,
21730        GIR_Done,
21731      // Label 1172: @55616
21732      GIM_Try, /*On fail goto*//*Label 1173*/ 55702, // Rule ID 3338 //
21733        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21734        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21735        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21736        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21737        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21740        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21741        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21742        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
21743        // MIs[1] Operand 1
21744        // No operand predicates
21745        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21746        GIM_CheckIsSafeToFold, /*InsnID*/1,
21747        // (intrinsic_wo_chain:{ *:[v8i16] } 1624:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
21748        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21749        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21750        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu16,
21752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21754        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21755        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21756        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21757        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21758        GIR_EraseFromParent, /*InsnID*/0,
21759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21760        // GIR_Coverage, 3338,
21761        GIR_Done,
21762      // Label 1173: @55702
21763      GIM_Try, /*On fail goto*//*Label 1174*/ 55788, // Rule ID 3340 //
21764        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21765        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21766        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21767        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21768        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21771        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21772        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21773        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
21774        // MIs[1] Operand 1
21775        // No operand predicates
21776        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21777        GIM_CheckIsSafeToFold, /*InsnID*/1,
21778        // (intrinsic_wo_chain:{ *:[v4i32] } 1624:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
21779        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21780        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21781        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21782        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms32,
21783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21785        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21786        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21787        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21788        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21789        GIR_EraseFromParent, /*InsnID*/0,
21790        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21791        // GIR_Coverage, 3340,
21792        GIR_Done,
21793      // Label 1174: @55788
21794      GIM_Try, /*On fail goto*//*Label 1175*/ 55874, // Rule ID 3342 //
21795        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
21796        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21797        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21798        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21799        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21801        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21802        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21803        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21804        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
21805        // MIs[1] Operand 1
21806        // No operand predicates
21807        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21808        GIM_CheckIsSafeToFold, /*InsnID*/1,
21809        // (intrinsic_wo_chain:{ *:[v4i32] } 1624:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
21810        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21811        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21812        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21813        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu32,
21814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
21816        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21817        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21818        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21819        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21820        GIR_EraseFromParent, /*InsnID*/0,
21821        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21822        // GIR_Coverage, 3342,
21823        GIR_Done,
21824      // Label 1175: @55874
21825      GIM_Try, /*On fail goto*//*Label 1176*/ 55955, // Rule ID 3052 //
21826        GIM_CheckFeatures, GIFBS_HasMVEInt,
21827        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21828        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21829        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21830        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21831        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21835        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21836        // (intrinsic_wo_chain:{ *:[v16i8] } 1582:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
21837        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21838        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21839        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21840        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs8,
21841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21844        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21845        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21846        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21847        GIR_EraseFromParent, /*InsnID*/0,
21848        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21849        // GIR_Coverage, 3052,
21850        GIR_Done,
21851      // Label 1176: @55955
21852      GIM_Try, /*On fail goto*//*Label 1177*/ 56036, // Rule ID 3054 //
21853        GIM_CheckFeatures, GIFBS_HasMVEInt,
21854        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21855        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21856        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21857        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21858        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21862        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21863        // (intrinsic_wo_chain:{ *:[v8i16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
21864        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21865        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21866        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21867        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs16,
21868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21871        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21872        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21873        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21874        GIR_EraseFromParent, /*InsnID*/0,
21875        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21876        // GIR_Coverage, 3054,
21877        GIR_Done,
21878      // Label 1177: @56036
21879      GIM_Try, /*On fail goto*//*Label 1178*/ 56117, // Rule ID 3056 //
21880        GIM_CheckFeatures, GIFBS_HasMVEInt,
21881        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21882        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21883        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21884        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21885        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21889        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21890        // (intrinsic_wo_chain:{ *:[v4i32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
21891        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21892        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21893        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs32,
21895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21898        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21899        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21900        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21901        GIR_EraseFromParent, /*InsnID*/0,
21902        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21903        // GIR_Coverage, 3056,
21904        GIR_Done,
21905      // Label 1178: @56117
21906      GIM_Try, /*On fail goto*//*Label 1179*/ 56198, // Rule ID 3058 //
21907        GIM_CheckFeatures, GIFBS_HasMVEInt,
21908        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21909        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21910        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21911        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21912        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21916        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21917        // (intrinsic_wo_chain:{ *:[v16i8] } 1582:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
21918        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21919        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21920        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu8,
21922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21925        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21926        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21927        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21928        GIR_EraseFromParent, /*InsnID*/0,
21929        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21930        // GIR_Coverage, 3058,
21931        GIR_Done,
21932      // Label 1179: @56198
21933      GIM_Try, /*On fail goto*//*Label 1180*/ 56279, // Rule ID 3060 //
21934        GIM_CheckFeatures, GIFBS_HasMVEInt,
21935        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21936        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21937        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21938        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21939        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21943        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21944        // (intrinsic_wo_chain:{ *:[v8i16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
21945        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21946        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21947        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21948        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu16,
21949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21952        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21953        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21954        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21955        GIR_EraseFromParent, /*InsnID*/0,
21956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21957        // GIR_Coverage, 3060,
21958        GIR_Done,
21959      // Label 1180: @56279
21960      GIM_Try, /*On fail goto*//*Label 1181*/ 56360, // Rule ID 3062 //
21961        GIM_CheckFeatures, GIFBS_HasMVEInt,
21962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
21963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21966        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21970        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
21971        // (intrinsic_wo_chain:{ *:[v4i32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
21972        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21973        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21974        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
21975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu32,
21976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
21977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
21978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
21979        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
21980        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
21981        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21982        GIR_EraseFromParent, /*InsnID*/0,
21983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21984        // GIR_Coverage, 3062,
21985        GIR_Done,
21986      // Label 1181: @56360
21987      GIM_Try, /*On fail goto*//*Label 1182*/ 56441, // Rule ID 3064 //
21988        GIM_CheckFeatures, GIFBS_HasMVEInt,
21989        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
21990        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21991        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21992        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21993        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21997        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
21998        // (intrinsic_wo_chain:{ *:[v16i8] } 1620:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
21999        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22000        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22001        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs8,
22003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22006        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22008        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22009        GIR_EraseFromParent, /*InsnID*/0,
22010        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22011        // GIR_Coverage, 3064,
22012        GIR_Done,
22013      // Label 1182: @56441
22014      GIM_Try, /*On fail goto*//*Label 1183*/ 56522, // Rule ID 3066 //
22015        GIM_CheckFeatures, GIFBS_HasMVEInt,
22016        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
22017        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22018        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22019        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22020        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22024        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22025        // (intrinsic_wo_chain:{ *:[v8i16] } 1620:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22026        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22027        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22028        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22029        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs16,
22030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22033        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22034        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22035        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22036        GIR_EraseFromParent, /*InsnID*/0,
22037        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22038        // GIR_Coverage, 3066,
22039        GIR_Done,
22040      // Label 1183: @56522
22041      GIM_Try, /*On fail goto*//*Label 1184*/ 56603, // Rule ID 3068 //
22042        GIM_CheckFeatures, GIFBS_HasMVEInt,
22043        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
22044        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22045        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22046        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22047        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22051        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22052        // (intrinsic_wo_chain:{ *:[v4i32] } 1620:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22053        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22054        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22055        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22056        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs32,
22057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22060        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22061        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22062        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22063        GIR_EraseFromParent, /*InsnID*/0,
22064        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22065        // GIR_Coverage, 3068,
22066        GIR_Done,
22067      // Label 1184: @56603
22068      GIM_Try, /*On fail goto*//*Label 1185*/ 56684, // Rule ID 3070 //
22069        GIM_CheckFeatures, GIFBS_HasMVEInt,
22070        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
22071        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22072        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22073        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22074        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22078        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22079        // (intrinsic_wo_chain:{ *:[v16i8] } 1620:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22080        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22081        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22082        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu8,
22084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22087        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22088        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22089        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22090        GIR_EraseFromParent, /*InsnID*/0,
22091        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22092        // GIR_Coverage, 3070,
22093        GIR_Done,
22094      // Label 1185: @56684
22095      GIM_Try, /*On fail goto*//*Label 1186*/ 56765, // Rule ID 3072 //
22096        GIM_CheckFeatures, GIFBS_HasMVEInt,
22097        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
22098        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22099        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22100        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22101        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22105        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22106        // (intrinsic_wo_chain:{ *:[v8i16] } 1620:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22107        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22108        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22109        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu16,
22111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22114        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22115        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22116        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22117        GIR_EraseFromParent, /*InsnID*/0,
22118        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22119        // GIR_Coverage, 3072,
22120        GIR_Done,
22121      // Label 1186: @56765
22122      GIM_Try, /*On fail goto*//*Label 1187*/ 56846, // Rule ID 3074 //
22123        GIM_CheckFeatures, GIFBS_HasMVEInt,
22124        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
22125        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22126        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22127        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22128        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22132        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22133        // (intrinsic_wo_chain:{ *:[v4i32] } 1620:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22134        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22135        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22136        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22137        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu32,
22138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22141        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22142        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22143        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22144        GIR_EraseFromParent, /*InsnID*/0,
22145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22146        // GIR_Coverage, 3074,
22147        GIR_Done,
22148      // Label 1187: @56846
22149      GIM_Try, /*On fail goto*//*Label 1188*/ 56927, // Rule ID 3076 //
22150        GIM_CheckFeatures, GIFBS_HasMVEInt,
22151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22155        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22159        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22160        // (intrinsic_wo_chain:{ *:[v16i8] } 1597:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22161        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22162        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22163        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22164        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs8,
22165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22168        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22169        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22170        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22171        GIR_EraseFromParent, /*InsnID*/0,
22172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22173        // GIR_Coverage, 3076,
22174        GIR_Done,
22175      // Label 1188: @56927
22176      GIM_Try, /*On fail goto*//*Label 1189*/ 57008, // Rule ID 3078 //
22177        GIM_CheckFeatures, GIFBS_HasMVEInt,
22178        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22179        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22180        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22181        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22182        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22186        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22187        // (intrinsic_wo_chain:{ *:[v8i16] } 1597:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22188        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22189        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22190        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs16,
22192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22195        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22196        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22197        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22198        GIR_EraseFromParent, /*InsnID*/0,
22199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22200        // GIR_Coverage, 3078,
22201        GIR_Done,
22202      // Label 1189: @57008
22203      GIM_Try, /*On fail goto*//*Label 1190*/ 57089, // Rule ID 3080 //
22204        GIM_CheckFeatures, GIFBS_HasMVEInt,
22205        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22206        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22208        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22209        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22213        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22214        // (intrinsic_wo_chain:{ *:[v4i32] } 1597:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22215        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22216        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22217        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22218        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs32,
22219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22222        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22223        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22224        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22225        GIR_EraseFromParent, /*InsnID*/0,
22226        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22227        // GIR_Coverage, 3080,
22228        GIR_Done,
22229      // Label 1190: @57089
22230      GIM_Try, /*On fail goto*//*Label 1191*/ 57170, // Rule ID 3082 //
22231        GIM_CheckFeatures, GIFBS_HasMVEInt,
22232        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22233        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22234        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22235        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22236        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22240        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22241        // (intrinsic_wo_chain:{ *:[v16i8] } 1597:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22242        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22243        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22244        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22245        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu8,
22246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22249        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22250        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22251        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22252        GIR_EraseFromParent, /*InsnID*/0,
22253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22254        // GIR_Coverage, 3082,
22255        GIR_Done,
22256      // Label 1191: @57170
22257      GIM_Try, /*On fail goto*//*Label 1192*/ 57251, // Rule ID 3084 //
22258        GIM_CheckFeatures, GIFBS_HasMVEInt,
22259        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22260        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22261        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22262        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22263        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22267        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22268        // (intrinsic_wo_chain:{ *:[v8i16] } 1597:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22269        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22270        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22271        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu16,
22273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22276        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22277        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22278        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22279        GIR_EraseFromParent, /*InsnID*/0,
22280        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22281        // GIR_Coverage, 3084,
22282        GIR_Done,
22283      // Label 1192: @57251
22284      GIM_Try, /*On fail goto*//*Label 1193*/ 57332, // Rule ID 3086 //
22285        GIM_CheckFeatures, GIFBS_HasMVEInt,
22286        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
22287        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22288        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22289        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22290        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22294        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22295        // (intrinsic_wo_chain:{ *:[v4i32] } 1597:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22296        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22297        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22298        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu32,
22300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22303        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22304        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22305        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22306        GIR_EraseFromParent, /*InsnID*/0,
22307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22308        // GIR_Coverage, 3086,
22309        GIR_Done,
22310      // Label 1193: @57332
22311      GIM_Try, /*On fail goto*//*Label 1194*/ 57413, // Rule ID 3088 //
22312        GIM_CheckFeatures, GIFBS_HasMVEInt,
22313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22316        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22317        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22321        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22322        // (intrinsic_wo_chain:{ *:[v16i8] } 1598:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22323        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22324        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22325        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22326        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs8,
22327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22330        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22331        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22332        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22333        GIR_EraseFromParent, /*InsnID*/0,
22334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22335        // GIR_Coverage, 3088,
22336        GIR_Done,
22337      // Label 1194: @57413
22338      GIM_Try, /*On fail goto*//*Label 1195*/ 57494, // Rule ID 3090 //
22339        GIM_CheckFeatures, GIFBS_HasMVEInt,
22340        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22341        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22342        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22343        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22344        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22348        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22349        // (intrinsic_wo_chain:{ *:[v8i16] } 1598:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22350        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22351        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22352        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22353        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs16,
22354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22357        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22358        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22359        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22360        GIR_EraseFromParent, /*InsnID*/0,
22361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22362        // GIR_Coverage, 3090,
22363        GIR_Done,
22364      // Label 1195: @57494
22365      GIM_Try, /*On fail goto*//*Label 1196*/ 57575, // Rule ID 3092 //
22366        GIM_CheckFeatures, GIFBS_HasMVEInt,
22367        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22368        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22369        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22370        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22371        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22375        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22376        // (intrinsic_wo_chain:{ *:[v4i32] } 1598:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22377        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22378        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22379        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs32,
22381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22384        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22385        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22386        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22387        GIR_EraseFromParent, /*InsnID*/0,
22388        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22389        // GIR_Coverage, 3092,
22390        GIR_Done,
22391      // Label 1196: @57575
22392      GIM_Try, /*On fail goto*//*Label 1197*/ 57656, // Rule ID 3094 //
22393        GIM_CheckFeatures, GIFBS_HasMVEInt,
22394        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22395        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22396        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22397        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22398        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22402        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22403        // (intrinsic_wo_chain:{ *:[v16i8] } 1598:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22404        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22405        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22406        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22407        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu8,
22408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22411        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22412        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22413        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22414        GIR_EraseFromParent, /*InsnID*/0,
22415        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22416        // GIR_Coverage, 3094,
22417        GIR_Done,
22418      // Label 1197: @57656
22419      GIM_Try, /*On fail goto*//*Label 1198*/ 57737, // Rule ID 3096 //
22420        GIM_CheckFeatures, GIFBS_HasMVEInt,
22421        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22422        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22423        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22424        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22425        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22429        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22430        // (intrinsic_wo_chain:{ *:[v8i16] } 1598:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22431        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22432        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22433        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22434        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu16,
22435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22438        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22439        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22440        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22441        GIR_EraseFromParent, /*InsnID*/0,
22442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22443        // GIR_Coverage, 3096,
22444        GIR_Done,
22445      // Label 1198: @57737
22446      GIM_Try, /*On fail goto*//*Label 1199*/ 57818, // Rule ID 3098 //
22447        GIM_CheckFeatures, GIFBS_HasMVEInt,
22448        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
22449        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22450        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22451        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22452        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22456        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22457        // (intrinsic_wo_chain:{ *:[v4i32] } 1598:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22458        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22459        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22460        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22461        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu32,
22462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22465        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22466        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22467        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22468        GIR_EraseFromParent, /*InsnID*/0,
22469        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22470        // GIR_Coverage, 3098,
22471        GIR_Done,
22472      // Label 1199: @57818
22473      GIM_Try, /*On fail goto*//*Label 1200*/ 57899, // Rule ID 3396 //
22474        GIM_CheckFeatures, GIFBS_HasMVEFloat,
22475        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
22476        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22477        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22478        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22479        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22483        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22484        // (intrinsic_wo_chain:{ *:[v4f32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
22485        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22486        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22487        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32,
22489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22492        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22493        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22494        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22495        GIR_EraseFromParent, /*InsnID*/0,
22496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22497        // GIR_Coverage, 3396,
22498        GIR_Done,
22499      // Label 1200: @57899
22500      GIM_Try, /*On fail goto*//*Label 1201*/ 57980, // Rule ID 3398 //
22501        GIM_CheckFeatures, GIFBS_HasMVEFloat,
22502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
22503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22506        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22510        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22511        // (intrinsic_wo_chain:{ *:[v8f16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
22512        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22513        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22514        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16,
22516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22519        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22520        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22521        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22522        GIR_EraseFromParent, /*InsnID*/0,
22523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22524        // GIR_Coverage, 3398,
22525        GIR_Done,
22526      // Label 1201: @57980
22527      GIM_Try, /*On fail goto*//*Label 1202*/ 58061, // Rule ID 3563 //
22528        GIM_CheckFeatures, GIFBS_HasMVEInt,
22529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
22530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22533        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22537        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22538        // (intrinsic_wo_chain:{ *:[v8i16] } 1613:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22539        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22540        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22541        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp8,
22543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22546        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22547        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22548        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22549        GIR_EraseFromParent, /*InsnID*/0,
22550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22551        // GIR_Coverage, 3563,
22552        GIR_Done,
22553      // Label 1202: @58061
22554      GIM_Try, /*On fail goto*//*Label 1203*/ 58142, // Rule ID 3565 //
22555        GIM_CheckFeatures, GIFBS_HasMVEInt,
22556        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
22557        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22558        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22559        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22560        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22564        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22565        // (intrinsic_wo_chain:{ *:[v8i16] } 1613:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22566        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22567        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22568        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22569        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp8,
22570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22573        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22574        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22575        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22576        GIR_EraseFromParent, /*InsnID*/0,
22577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22578        // GIR_Coverage, 3565,
22579        GIR_Done,
22580      // Label 1203: @58142
22581      GIM_Try, /*On fail goto*//*Label 1204*/ 58223, // Rule ID 3567 //
22582        GIM_CheckFeatures, GIFBS_HasMVEInt,
22583        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
22584        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22585        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22586        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22587        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22591        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22592        // (intrinsic_wo_chain:{ *:[v4i32] } 1613:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22593        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22594        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22595        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp16,
22597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22600        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22601        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22602        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22603        GIR_EraseFromParent, /*InsnID*/0,
22604        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22605        // GIR_Coverage, 3567,
22606        GIR_Done,
22607      // Label 1204: @58223
22608      GIM_Try, /*On fail goto*//*Label 1205*/ 58304, // Rule ID 3569 //
22609        GIM_CheckFeatures, GIFBS_HasMVEInt,
22610        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
22611        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22612        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22613        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22614        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22618        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22619        // (intrinsic_wo_chain:{ *:[v4i32] } 1613:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22620        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22621        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22622        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22623        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp16,
22624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22627        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22628        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22629        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22630        GIR_EraseFromParent, /*InsnID*/0,
22631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22632        // GIR_Coverage, 3569,
22633        GIR_Done,
22634      // Label 1205: @58304
22635      GIM_Try, /*On fail goto*//*Label 1206*/ 58385, // Rule ID 3571 //
22636        GIM_CheckFeatures, GIFBS_HasMVEInt,
22637        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22638        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22639        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22640        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22641        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22645        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22646        // (intrinsic_wo_chain:{ *:[v16i8] } 1611:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22647        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22648        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22649        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22650        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs8,
22651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22654        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22655        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22656        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22657        GIR_EraseFromParent, /*InsnID*/0,
22658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22659        // GIR_Coverage, 3571,
22660        GIR_Done,
22661      // Label 1206: @58385
22662      GIM_Try, /*On fail goto*//*Label 1207*/ 58466, // Rule ID 3573 //
22663        GIM_CheckFeatures, GIFBS_HasMVEInt,
22664        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22665        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22666        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22667        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22668        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22672        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22673        // (intrinsic_wo_chain:{ *:[v8i16] } 1611:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22674        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22675        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22676        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs16,
22678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22681        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22682        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22683        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22684        GIR_EraseFromParent, /*InsnID*/0,
22685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22686        // GIR_Coverage, 3573,
22687        GIR_Done,
22688      // Label 1207: @58466
22689      GIM_Try, /*On fail goto*//*Label 1208*/ 58547, // Rule ID 3575 //
22690        GIM_CheckFeatures, GIFBS_HasMVEInt,
22691        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22692        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22693        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22694        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22695        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22699        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22700        // (intrinsic_wo_chain:{ *:[v4i32] } 1611:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22701        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22702        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22703        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs32,
22705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22708        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22709        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22710        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22711        GIR_EraseFromParent, /*InsnID*/0,
22712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22713        // GIR_Coverage, 3575,
22714        GIR_Done,
22715      // Label 1208: @58547
22716      GIM_Try, /*On fail goto*//*Label 1209*/ 58628, // Rule ID 3577 //
22717        GIM_CheckFeatures, GIFBS_HasMVEInt,
22718        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22719        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22720        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22721        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22722        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22726        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22727        // (intrinsic_wo_chain:{ *:[v16i8] } 1611:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22728        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22729        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22730        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu8,
22732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22735        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22736        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22737        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22738        GIR_EraseFromParent, /*InsnID*/0,
22739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22740        // GIR_Coverage, 3577,
22741        GIR_Done,
22742      // Label 1209: @58628
22743      GIM_Try, /*On fail goto*//*Label 1210*/ 58709, // Rule ID 3579 //
22744        GIM_CheckFeatures, GIFBS_HasMVEInt,
22745        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22746        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22747        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22748        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22749        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22753        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22754        // (intrinsic_wo_chain:{ *:[v8i16] } 1611:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22755        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22756        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22757        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22758        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu16,
22759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22762        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22763        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22764        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22765        GIR_EraseFromParent, /*InsnID*/0,
22766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22767        // GIR_Coverage, 3579,
22768        GIR_Done,
22769      // Label 1210: @58709
22770      GIM_Try, /*On fail goto*//*Label 1211*/ 58790, // Rule ID 3581 //
22771        GIM_CheckFeatures, GIFBS_HasMVEInt,
22772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
22773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22775        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22776        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22780        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22781        // (intrinsic_wo_chain:{ *:[v4i32] } 1611:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22782        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22783        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22784        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu32,
22786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22789        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22790        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22791        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22792        GIR_EraseFromParent, /*InsnID*/0,
22793        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22794        // GIR_Coverage, 3581,
22795        GIR_Done,
22796      // Label 1211: @58790
22797      GIM_Try, /*On fail goto*//*Label 1212*/ 58871, // Rule ID 3583 //
22798        GIM_CheckFeatures, GIFBS_HasMVEInt,
22799        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22802        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22803        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22807        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22808        // (intrinsic_wo_chain:{ *:[v16i8] } 1623:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22809        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22810        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22811        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22812        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs8,
22813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22816        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22817        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22818        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22819        GIR_EraseFromParent, /*InsnID*/0,
22820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22821        // GIR_Coverage, 3583,
22822        GIR_Done,
22823      // Label 1212: @58871
22824      GIM_Try, /*On fail goto*//*Label 1213*/ 58952, // Rule ID 3585 //
22825        GIM_CheckFeatures, GIFBS_HasMVEInt,
22826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22829        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22830        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22834        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22835        // (intrinsic_wo_chain:{ *:[v8i16] } 1623:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22836        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22837        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22838        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs16,
22840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22843        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22844        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22845        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22846        GIR_EraseFromParent, /*InsnID*/0,
22847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22848        // GIR_Coverage, 3585,
22849        GIR_Done,
22850      // Label 1213: @58952
22851      GIM_Try, /*On fail goto*//*Label 1214*/ 59033, // Rule ID 3587 //
22852        GIM_CheckFeatures, GIFBS_HasMVEInt,
22853        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22854        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22855        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22856        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22857        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22861        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22862        // (intrinsic_wo_chain:{ *:[v4i32] } 1623:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22863        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22864        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22865        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22866        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs32,
22867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22870        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22871        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22872        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22873        GIR_EraseFromParent, /*InsnID*/0,
22874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22875        // GIR_Coverage, 3587,
22876        GIR_Done,
22877      // Label 1214: @59033
22878      GIM_Try, /*On fail goto*//*Label 1215*/ 59114, // Rule ID 3589 //
22879        GIM_CheckFeatures, GIFBS_HasMVEInt,
22880        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22881        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22882        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22883        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22884        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22888        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22889        // (intrinsic_wo_chain:{ *:[v16i8] } 1623:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
22890        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22891        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22892        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22893        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu8,
22894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22897        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22898        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22899        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22900        GIR_EraseFromParent, /*InsnID*/0,
22901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22902        // GIR_Coverage, 3589,
22903        GIR_Done,
22904      // Label 1215: @59114
22905      GIM_Try, /*On fail goto*//*Label 1216*/ 59195, // Rule ID 3591 //
22906        GIM_CheckFeatures, GIFBS_HasMVEInt,
22907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22911        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22915        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22916        // (intrinsic_wo_chain:{ *:[v8i16] } 1623:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
22917        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22918        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22919        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu16,
22921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22924        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22925        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22926        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22927        GIR_EraseFromParent, /*InsnID*/0,
22928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22929        // GIR_Coverage, 3591,
22930        GIR_Done,
22931      // Label 1216: @59195
22932      GIM_Try, /*On fail goto*//*Label 1217*/ 59276, // Rule ID 3593 //
22933        GIM_CheckFeatures, GIFBS_HasMVEInt,
22934        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
22935        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22936        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22937        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22938        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22942        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22943        // (intrinsic_wo_chain:{ *:[v4i32] } 1623:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
22944        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22945        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22946        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
22947        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu32,
22948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
22950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
22951        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22952        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22953        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
22954        GIR_EraseFromParent, /*InsnID*/0,
22955        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22956        // GIR_Coverage, 3593,
22957        GIR_Done,
22958      // Label 1217: @59276
22959      GIM_Try, /*On fail goto*//*Label 1218*/ 59343, // Rule ID 3599 //
22960        GIM_CheckFeatures, GIFBS_HasMVEFloat,
22961        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
22962        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22963        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22964        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22965        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22969        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
22970        // (intrinsic_wo_chain:{ *:[v8f16] } 1595:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] })  =>  (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
22971        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32bh,
22972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
22974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
22975        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22976        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
22977        GIR_EraseFromParent, /*InsnID*/0,
22978        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22979        // GIR_Coverage, 3599,
22980        GIR_Done,
22981      // Label 1218: @59343
22982      GIM_Try, /*On fail goto*//*Label 1219*/ 59410, // Rule ID 3601 //
22983        GIM_CheckFeatures, GIFBS_HasMVEFloat,
22984        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
22985        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22986        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22987        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22988        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
22989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
22990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
22991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
22992        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
22993        // (intrinsic_wo_chain:{ *:[v8f16] } 1595:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] })  =>  (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
22994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32th,
22995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
22996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
22997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
22998        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22999        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23000        GIR_EraseFromParent, /*InsnID*/0,
23001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23002        // GIR_Coverage, 3601,
23003        GIR_Done,
23004      // Label 1219: @59410
23005      GIM_Try, /*On fail goto*//*Label 1220*/ 59486, // Rule ID 3302 //
23006        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
23007        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23008        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23009        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23010        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23014        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23015        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23016        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
23017        // MIs[1] Operand 1
23018        // No operand predicates
23019        GIM_CheckIsSafeToFold, /*InsnID*/1,
23020        // (intrinsic_wo_chain:{ *:[v16i8] } 1634:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
23021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm8,
23022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23025        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23026        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23027        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23028        GIR_EraseFromParent, /*InsnID*/0,
23029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23030        // GIR_Coverage, 3302,
23031        GIR_Done,
23032      // Label 1220: @59486
23033      GIM_Try, /*On fail goto*//*Label 1221*/ 59562, // Rule ID 3304 //
23034        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
23035        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23036        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23037        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23038        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23042        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23043        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23044        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
23045        // MIs[1] Operand 1
23046        // No operand predicates
23047        GIM_CheckIsSafeToFold, /*InsnID*/1,
23048        // (intrinsic_wo_chain:{ *:[v8i16] } 1634:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
23049        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm16,
23050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23053        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23054        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23055        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23056        GIR_EraseFromParent, /*InsnID*/0,
23057        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23058        // GIR_Coverage, 3304,
23059        GIR_Done,
23060      // Label 1221: @59562
23061      GIM_Try, /*On fail goto*//*Label 1222*/ 59638, // Rule ID 3306 //
23062        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
23063        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23064        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23065        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23066        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23070        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23071        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23072        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
23073        // MIs[1] Operand 1
23074        // No operand predicates
23075        GIM_CheckIsSafeToFold, /*InsnID*/1,
23076        // (intrinsic_wo_chain:{ *:[v4i32] } 1634:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
23077        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm32,
23078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23081        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23082        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23083        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23084        GIR_EraseFromParent, /*InsnID*/0,
23085        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23086        // GIR_Coverage, 3306,
23087        GIR_Done,
23088      // Label 1222: @59638
23089      GIM_Try, /*On fail goto*//*Label 1223*/ 59714, // Rule ID 3308 //
23090        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
23091        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23092        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23093        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23094        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23098        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23099        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23100        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
23101        // MIs[1] Operand 1
23102        // No operand predicates
23103        GIM_CheckIsSafeToFold, /*InsnID*/1,
23104        // (intrinsic_wo_chain:{ *:[v16i8] } 1636:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)  =>  (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
23105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm8,
23106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23109        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23110        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23111        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23112        GIR_EraseFromParent, /*InsnID*/0,
23113        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23114        // GIR_Coverage, 3308,
23115        GIR_Done,
23116      // Label 1223: @59714
23117      GIM_Try, /*On fail goto*//*Label 1224*/ 59790, // Rule ID 3310 //
23118        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
23119        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23120        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23121        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23122        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23126        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23127        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23128        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
23129        // MIs[1] Operand 1
23130        // No operand predicates
23131        GIM_CheckIsSafeToFold, /*InsnID*/1,
23132        // (intrinsic_wo_chain:{ *:[v8i16] } 1636:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)  =>  (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
23133        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm16,
23134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23137        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23138        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23139        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23140        GIR_EraseFromParent, /*InsnID*/0,
23141        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23142        // GIR_Coverage, 3310,
23143        GIR_Done,
23144      // Label 1224: @59790
23145      GIM_Try, /*On fail goto*//*Label 1225*/ 59866, // Rule ID 3312 //
23146        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
23147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23149        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23150        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23154        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
23155        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23156        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
23157        // MIs[1] Operand 1
23158        // No operand predicates
23159        GIM_CheckIsSafeToFold, /*InsnID*/1,
23160        // (intrinsic_wo_chain:{ *:[v4i32] } 1636:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)  =>  (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
23161        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm32,
23162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
23164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
23165        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23166        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23167        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23168        GIR_EraseFromParent, /*InsnID*/0,
23169        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23170        // GIR_Coverage, 3312,
23171        GIR_Done,
23172      // Label 1225: @59866
23173      GIM_Try, /*On fail goto*//*Label 1226*/ 59955, // Rule ID 3535 //
23174        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23175        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
23176        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23177        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23178        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23179        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
23180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23181        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23182        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23183        // MIs[1] Operand 1
23184        // No operand predicates
23185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
23187        GIM_CheckIsSafeToFold, /*InsnID*/1,
23188        // (intrinsic_wo_chain:{ *:[v8f16] } 1589:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
23189        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23190        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23191        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23192        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf16,
23193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
23196        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
23197        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23198        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23199        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23200        GIR_EraseFromParent, /*InsnID*/0,
23201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23202        // GIR_Coverage, 3535,
23203        GIR_Done,
23204      // Label 1226: @59955
23205      GIM_Try, /*On fail goto*//*Label 1227*/ 60044, // Rule ID 3537 //
23206        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23207        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
23208        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23209        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23211        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
23212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23213        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23214        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23215        // MIs[1] Operand 1
23216        // No operand predicates
23217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
23219        GIM_CheckIsSafeToFold, /*InsnID*/1,
23220        // (intrinsic_wo_chain:{ *:[v4f32] } 1589:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
23221        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23222        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23223        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf32,
23225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
23228        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
23229        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23230        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23231        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23232        GIR_EraseFromParent, /*InsnID*/0,
23233        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23234        // GIR_Coverage, 3537,
23235        GIR_Done,
23236      // Label 1227: @60044
23237      GIM_Try, /*On fail goto*//*Label 1228*/ 60115, // Rule ID 148 //
23238        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23239        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
23240        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23241        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23242        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23243        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23248        // (intrinsic_wo_chain:{ *:[i32] } 1854:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
23249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
23250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23254        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23255        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23256        GIR_EraseFromParent, /*InsnID*/0,
23257        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23258        // GIR_Coverage, 148,
23259        GIR_Done,
23260      // Label 1228: @60115
23261      GIM_Try, /*On fail goto*//*Label 1229*/ 60186, // Rule ID 475 //
23262        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23263        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
23264        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23265        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23266        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23267        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
23272        // (intrinsic_wo_chain:{ *:[i32] } 1854:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
23273        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
23274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23278        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23279        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23280        GIR_EraseFromParent, /*InsnID*/0,
23281        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23282        // GIR_Coverage, 475,
23283        GIR_Done,
23284      // Label 1229: @60186
23285      GIM_Try, /*On fail goto*//*Label 1230*/ 60257, // Rule ID 534 //
23286        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23287        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
23288        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23289        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23290        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23291        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
23296        // (intrinsic_wo_chain:{ *:[i32] } 1799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
23297        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
23298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23302        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23303        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23304        GIR_EraseFromParent, /*InsnID*/0,
23305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23306        // GIR_Coverage, 534,
23307        GIR_Done,
23308      // Label 1230: @60257
23309      GIM_Try, /*On fail goto*//*Label 1231*/ 60328, // Rule ID 535 //
23310        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
23312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23315        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
23320        // (intrinsic_wo_chain:{ *:[i32] } 1800:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
23321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
23322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23326        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23327        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23328        GIR_EraseFromParent, /*InsnID*/0,
23329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23330        // GIR_Coverage, 535,
23331        GIR_Done,
23332      // Label 1231: @60328
23333      GIM_Try, /*On fail goto*//*Label 1232*/ 60399, // Rule ID 536 //
23334        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23335        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
23336        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23337        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23338        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23339        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
23344        // (intrinsic_wo_chain:{ *:[i32] } 1807:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
23345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
23346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23350        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23351        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23352        GIR_EraseFromParent, /*InsnID*/0,
23353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23354        // GIR_Coverage, 536,
23355        GIR_Done,
23356      // Label 1232: @60399
23357      GIM_Try, /*On fail goto*//*Label 1233*/ 60470, // Rule ID 537 //
23358        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23359        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
23360        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23361        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23362        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23363        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
23368        // (intrinsic_wo_chain:{ *:[i32] } 1808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
23369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
23370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23374        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23375        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23376        GIR_EraseFromParent, /*InsnID*/0,
23377        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23378        // GIR_Coverage, 537,
23379        GIR_Done,
23380      // Label 1233: @60470
23381      GIM_Try, /*On fail goto*//*Label 1234*/ 60534, // Rule ID 954 //
23382        GIM_CheckFeatures, GIFBS_HasDotProd,
23383        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
23384        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23385        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23386        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
23387        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
23388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
23392        // (intrinsic_wo_chain:{ *:[v2i32] } 1661:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
23393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD,
23394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
23396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23398        GIR_EraseFromParent, /*InsnID*/0,
23399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23400        // GIR_Coverage, 954,
23401        GIR_Done,
23402      // Label 1234: @60534
23403      GIM_Try, /*On fail goto*//*Label 1235*/ 60598, // Rule ID 955 //
23404        GIM_CheckFeatures, GIFBS_HasDotProd,
23405        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
23406        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23407        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23408        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
23409        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
23410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
23414        // (intrinsic_wo_chain:{ *:[v2i32] } 1650:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
23415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD,
23416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
23418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23420        GIR_EraseFromParent, /*InsnID*/0,
23421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23422        // GIR_Coverage, 955,
23423        GIR_Done,
23424      // Label 1235: @60598
23425      GIM_Try, /*On fail goto*//*Label 1236*/ 60662, // Rule ID 956 //
23426        GIM_CheckFeatures, GIFBS_HasDotProd,
23427        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
23428        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23429        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23430        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23431        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
23432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23436        // (intrinsic_wo_chain:{ *:[v4i32] } 1661:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
23437        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ,
23438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
23440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23442        GIR_EraseFromParent, /*InsnID*/0,
23443        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23444        // GIR_Coverage, 956,
23445        GIR_Done,
23446      // Label 1236: @60662
23447      GIM_Try, /*On fail goto*//*Label 1237*/ 60726, // Rule ID 957 //
23448        GIM_CheckFeatures, GIFBS_HasDotProd,
23449        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
23450        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23451        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23452        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23453        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
23454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23458        // (intrinsic_wo_chain:{ *:[v4i32] } 1650:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
23459        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ,
23460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
23462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23464        GIR_EraseFromParent, /*InsnID*/0,
23465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23466        // GIR_Coverage, 957,
23467        GIR_Done,
23468      // Label 1237: @60726
23469      GIM_Try, /*On fail goto*//*Label 1238*/ 60797, // Rule ID 1678 //
23470        GIM_CheckFeatures, GIFBS_HasNEON,
23471        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1,
23472        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
23473        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
23474        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
23475        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
23476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
23480        // (intrinsic_wo_chain:{ *:[v8i8] } 1774:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
23481        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
23482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
23484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23486        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23487        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23488        GIR_EraseFromParent, /*InsnID*/0,
23489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23490        // GIR_Coverage, 1678,
23491        GIR_Done,
23492      // Label 1238: @60797
23493      GIM_Try, /*On fail goto*//*Label 1239*/ 60861, // Rule ID 1709 //
23494        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
23495        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0,
23496        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23497        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23498        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23499        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
23500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23504        // (intrinsic_wo_chain:{ *:[v4i32] } 1655:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
23505        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
23506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23510        GIR_EraseFromParent, /*InsnID*/0,
23511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23512        // GIR_Coverage, 1709,
23513        GIR_Done,
23514      // Label 1239: @60861
23515      GIM_Try, /*On fail goto*//*Label 1240*/ 60925, // Rule ID 1710 //
23516        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
23517        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h,
23518        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23519        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23520        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23521        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
23522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23526        // (intrinsic_wo_chain:{ *:[v4i32] } 1657:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
23527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
23528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23532        GIR_EraseFromParent, /*InsnID*/0,
23533        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23534        // GIR_Coverage, 1710,
23535        GIR_Done,
23536      // Label 1240: @60925
23537      GIM_Try, /*On fail goto*//*Label 1241*/ 60989, // Rule ID 1711 //
23538        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
23539        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2,
23540        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23541        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23542        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23543        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
23544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23548        // (intrinsic_wo_chain:{ *:[v4i32] } 1658:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
23549        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
23550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23554        GIR_EraseFromParent, /*InsnID*/0,
23555        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23556        // GIR_Coverage, 1711,
23557        GIR_Done,
23558      // Label 1241: @60989
23559      GIM_Try, /*On fail goto*//*Label 1242*/ 61053, // Rule ID 1712 //
23560        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
23561        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1,
23562        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23563        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23564        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23565        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
23566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
23570        // (intrinsic_wo_chain:{ *:[v4i32] } 1660:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
23571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
23572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23576        GIR_EraseFromParent, /*InsnID*/0,
23577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23578        // GIR_Coverage, 1712,
23579        GIR_Done,
23580      // Label 1242: @61053
23581      GIM_Try, /*On fail goto*//*Label 1243*/ 61124, // Rule ID 1904 //
23582        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23583        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
23584        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23585        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23586        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23587        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23592        // (intrinsic_wo_chain:{ *:[i32] } 1799:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
23593        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
23594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23599        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23600        GIR_EraseFromParent, /*InsnID*/0,
23601        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23602        // GIR_Coverage, 1904,
23603        GIR_Done,
23604      // Label 1243: @61124
23605      GIM_Try, /*On fail goto*//*Label 1244*/ 61195, // Rule ID 1905 //
23606        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23607        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
23608        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23609        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23610        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23611        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23616        // (intrinsic_wo_chain:{ *:[i32] } 1800:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
23617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
23618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23622        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23623        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23624        GIR_EraseFromParent, /*InsnID*/0,
23625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23626        // GIR_Coverage, 1905,
23627        GIR_Done,
23628      // Label 1244: @61195
23629      GIM_Try, /*On fail goto*//*Label 1245*/ 61266, // Rule ID 1906 //
23630        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23631        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
23632        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23633        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23634        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23635        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23640        // (intrinsic_wo_chain:{ *:[i32] } 1807:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
23641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
23642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23647        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23648        GIR_EraseFromParent, /*InsnID*/0,
23649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23650        // GIR_Coverage, 1906,
23651        GIR_Done,
23652      // Label 1245: @61266
23653      GIM_Try, /*On fail goto*//*Label 1246*/ 61337, // Rule ID 1907 //
23654        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
23656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23658        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23659        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23664        // (intrinsic_wo_chain:{ *:[i32] } 1808:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
23665        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
23666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
23670        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23671        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23672        GIR_EraseFromParent, /*InsnID*/0,
23673        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23674        // GIR_Coverage, 1907,
23675        GIR_Done,
23676      // Label 1246: @61337
23677      GIM_Try, /*On fail goto*//*Label 1247*/ 61408, // Rule ID 1980 //
23678        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23679        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
23680        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23681        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23682        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23683        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23688        // (intrinsic_wo_chain:{ *:[i32] } 1797:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23689        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
23690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23694        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23695        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23696        GIR_EraseFromParent, /*InsnID*/0,
23697        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23698        // GIR_Coverage, 1980,
23699        GIR_Done,
23700      // Label 1247: @61408
23701      GIM_Try, /*On fail goto*//*Label 1248*/ 61479, // Rule ID 1981 //
23702        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23703        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
23704        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23705        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23706        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23707        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23711        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23712        // (intrinsic_wo_chain:{ *:[i32] } 1798:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
23714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23719        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23720        GIR_EraseFromParent, /*InsnID*/0,
23721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23722        // GIR_Coverage, 1981,
23723        GIR_Done,
23724      // Label 1248: @61479
23725      GIM_Try, /*On fail goto*//*Label 1249*/ 61550, // Rule ID 1982 //
23726        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23727        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
23728        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23729        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23730        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23731        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23736        // (intrinsic_wo_chain:{ *:[i32] } 1803:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23737        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
23738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23742        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23743        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23744        GIR_EraseFromParent, /*InsnID*/0,
23745        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23746        // GIR_Coverage, 1982,
23747        GIR_Done,
23748      // Label 1249: @61550
23749      GIM_Try, /*On fail goto*//*Label 1250*/ 61621, // Rule ID 1983 //
23750        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23751        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
23752        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23753        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23754        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23755        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23760        // (intrinsic_wo_chain:{ *:[i32] } 1804:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
23762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23766        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23767        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23768        GIR_EraseFromParent, /*InsnID*/0,
23769        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23770        // GIR_Coverage, 1983,
23771        GIR_Done,
23772      // Label 1250: @61621
23773      GIM_Try, /*On fail goto*//*Label 1251*/ 61692, // Rule ID 1984 //
23774        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23775        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
23776        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23777        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23778        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23779        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23784        // (intrinsic_wo_chain:{ *:[i32] } 1805:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
23786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23790        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23791        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23792        GIR_EraseFromParent, /*InsnID*/0,
23793        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23794        // GIR_Coverage, 1984,
23795        GIR_Done,
23796      // Label 1251: @61692
23797      GIM_Try, /*On fail goto*//*Label 1252*/ 61763, // Rule ID 1985 //
23798        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23799        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
23800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23802        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23803        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23808        // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
23810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23815        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23816        GIR_EraseFromParent, /*InsnID*/0,
23817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23818        // GIR_Coverage, 1985,
23819        GIR_Done,
23820      // Label 1252: @61763
23821      GIM_Try, /*On fail goto*//*Label 1253*/ 61834, // Rule ID 2154 //
23822        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
23824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23826        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23827        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23832        // (intrinsic_wo_chain:{ *:[i32] } 1797:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23833        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
23834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23839        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23840        GIR_EraseFromParent, /*InsnID*/0,
23841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23842        // GIR_Coverage, 2154,
23843        GIR_Done,
23844      // Label 1253: @61834
23845      GIM_Try, /*On fail goto*//*Label 1254*/ 61905, // Rule ID 2155 //
23846        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23847        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
23848        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23849        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23850        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23851        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23856        // (intrinsic_wo_chain:{ *:[i32] } 1798:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
23858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23862        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23863        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23864        GIR_EraseFromParent, /*InsnID*/0,
23865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23866        // GIR_Coverage, 2155,
23867        GIR_Done,
23868      // Label 1254: @61905
23869      GIM_Try, /*On fail goto*//*Label 1255*/ 61976, // Rule ID 2156 //
23870        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23871        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
23872        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23873        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23874        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23875        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23880        // (intrinsic_wo_chain:{ *:[i32] } 1803:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
23882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23886        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23887        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23888        GIR_EraseFromParent, /*InsnID*/0,
23889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23890        // GIR_Coverage, 2156,
23891        GIR_Done,
23892      // Label 1255: @61976
23893      GIM_Try, /*On fail goto*//*Label 1256*/ 62047, // Rule ID 2157 //
23894        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23895        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
23896        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23897        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23898        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23899        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23904        // (intrinsic_wo_chain:{ *:[i32] } 1804:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23905        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
23906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23910        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23911        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23912        GIR_EraseFromParent, /*InsnID*/0,
23913        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23914        // GIR_Coverage, 2157,
23915        GIR_Done,
23916      // Label 1256: @62047
23917      GIM_Try, /*On fail goto*//*Label 1257*/ 62118, // Rule ID 2158 //
23918        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23919        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
23920        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23921        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23922        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23923        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23928        // (intrinsic_wo_chain:{ *:[i32] } 1805:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23929        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
23930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23934        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23935        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23936        GIR_EraseFromParent, /*InsnID*/0,
23937        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23938        // GIR_Coverage, 2158,
23939        GIR_Done,
23940      // Label 1257: @62118
23941      GIM_Try, /*On fail goto*//*Label 1258*/ 62189, // Rule ID 2159 //
23942        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23943        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
23944        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23945        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23946        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23947        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
23952        // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
23953        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
23954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
23958        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23959        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23960        GIR_EraseFromParent, /*InsnID*/0,
23961        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23962        // GIR_Coverage, 2159,
23963        GIR_Done,
23964      // Label 1258: @62189
23965      GIM_Try, /*On fail goto*//*Label 1259*/ 62260, // Rule ID 2437 //
23966        GIM_CheckFeatures, GIFBS_HasNEON,
23967        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
23968        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
23969        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
23970        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
23971        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
23972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
23976        // (intrinsic_wo_chain:{ *:[v8i8] } 1667:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VBSLd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
23977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
23978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
23980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
23982        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23983        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
23984        GIR_EraseFromParent, /*InsnID*/0,
23985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23986        // GIR_Coverage, 2437,
23987        GIR_Done,
23988      // Label 1259: @62260
23989      GIM_Try, /*On fail goto*//*Label 1260*/ 62331, // Rule ID 2438 //
23990        GIM_CheckFeatures, GIFBS_HasNEON,
23991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
23992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23994        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23995        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
23996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
24000        // (intrinsic_wo_chain:{ *:[v4i16] } 1667:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VBSLd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
24001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
24002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24008        GIR_EraseFromParent, /*InsnID*/0,
24009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24010        // GIR_Coverage, 2438,
24011        GIR_Done,
24012      // Label 1260: @62331
24013      GIM_Try, /*On fail goto*//*Label 1261*/ 62402, // Rule ID 2439 //
24014        GIM_CheckFeatures, GIFBS_HasNEON,
24015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
24017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
24018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
24019        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
24020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
24021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
24022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
24023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
24024        // (intrinsic_wo_chain:{ *:[v2i32] } 1667:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
24025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
24026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24030        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24031        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24032        GIR_EraseFromParent, /*InsnID*/0,
24033        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24034        // GIR_Coverage, 2439,
24035        GIR_Done,
24036      // Label 1261: @62402
24037      GIM_Try, /*On fail goto*//*Label 1262*/ 62473, // Rule ID 2440 //
24038        GIM_CheckFeatures, GIFBS_HasNEON,
24039        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24040        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
24041        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
24042        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
24043        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
24044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
24045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
24046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
24047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
24048        // (intrinsic_wo_chain:{ *:[v2f32] } 1667:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VBSLd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
24049        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
24050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24054        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24055        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24056        GIR_EraseFromParent, /*InsnID*/0,
24057        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24058        // GIR_Coverage, 2440,
24059        GIR_Done,
24060      // Label 1262: @62473
24061      GIM_Try, /*On fail goto*//*Label 1263*/ 62544, // Rule ID 2441 //
24062        GIM_CheckFeatures, GIFBS_HasNEON,
24063        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24064        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
24065        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
24066        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
24067        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
24068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
24069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
24070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
24071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
24072        // (intrinsic_wo_chain:{ *:[v1i64] } 1667:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
24073        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
24074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24078        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24079        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24080        GIR_EraseFromParent, /*InsnID*/0,
24081        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24082        // GIR_Coverage, 2441,
24083        GIR_Done,
24084      // Label 1263: @62544
24085      GIM_Try, /*On fail goto*//*Label 1264*/ 62615, // Rule ID 2444 //
24086        GIM_CheckFeatures, GIFBS_HasNEON,
24087        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24088        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24089        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24090        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24091        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
24092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
24094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
24095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
24096        // (intrinsic_wo_chain:{ *:[v16i8] } 1667:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VBSLq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
24097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
24098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24102        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24103        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24104        GIR_EraseFromParent, /*InsnID*/0,
24105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24106        // GIR_Coverage, 2444,
24107        GIR_Done,
24108      // Label 1264: @62615
24109      GIM_Try, /*On fail goto*//*Label 1265*/ 62686, // Rule ID 2445 //
24110        GIM_CheckFeatures, GIFBS_HasNEON,
24111        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24112        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24113        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24114        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24115        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
24116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
24118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
24119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
24120        // (intrinsic_wo_chain:{ *:[v8i16] } 1667:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VBSLq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
24121        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
24122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24126        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24127        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24128        GIR_EraseFromParent, /*InsnID*/0,
24129        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24130        // GIR_Coverage, 2445,
24131        GIR_Done,
24132      // Label 1265: @62686
24133      GIM_Try, /*On fail goto*//*Label 1266*/ 62757, // Rule ID 2446 //
24134        GIM_CheckFeatures, GIFBS_HasNEON,
24135        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24136        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24137        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24138        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24139        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
24142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
24143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
24144        // (intrinsic_wo_chain:{ *:[v4i32] } 1667:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
24145        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
24146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24150        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24151        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24152        GIR_EraseFromParent, /*InsnID*/0,
24153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24154        // GIR_Coverage, 2446,
24155        GIR_Done,
24156      // Label 1266: @62757
24157      GIM_Try, /*On fail goto*//*Label 1267*/ 62828, // Rule ID 2447 //
24158        GIM_CheckFeatures, GIFBS_HasNEON,
24159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24163        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
24166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
24167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
24168        // (intrinsic_wo_chain:{ *:[v4f32] } 1667:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VBSLq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
24169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
24170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24174        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24175        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24176        GIR_EraseFromParent, /*InsnID*/0,
24177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24178        // GIR_Coverage, 2447,
24179        GIR_Done,
24180      // Label 1267: @62828
24181      GIM_Try, /*On fail goto*//*Label 1268*/ 62899, // Rule ID 2448 //
24182        GIM_CheckFeatures, GIFBS_HasNEON,
24183        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
24184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
24185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
24186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
24187        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
24188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
24190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
24191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
24192        // (intrinsic_wo_chain:{ *:[v2i64] } 1667:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
24193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
24194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
24196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
24197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
24198        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24199        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24200        GIR_EraseFromParent, /*InsnID*/0,
24201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24202        // GIR_Coverage, 2448,
24203        GIR_Done,
24204      // Label 1268: @62899
24205      GIM_Try, /*On fail goto*//*Label 1269*/ 62995, // Rule ID 2561 //
24206        GIM_CheckFeatures, GIFBS_HasNEON,
24207        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1c,
24208        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24209        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24211        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24213        // (intrinsic_wo_chain:{ *:[v4i32] } 1651:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
24214        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
24215        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24216        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
24217        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
24218        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
24219        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24220        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
24221        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24222        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
24223        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
24224        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
24225        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53,
24226        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2,
24227        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1C,
24228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
24230        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
24232        GIR_EraseFromParent, /*InsnID*/0,
24233        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24234        // GIR_Coverage, 2561,
24235        GIR_Done,
24236      // Label 1269: @62995
24237      GIM_Try, /*On fail goto*//*Label 1270*/ 63091, // Rule ID 2562 //
24238        GIM_CheckFeatures, GIFBS_HasNEON,
24239        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1m,
24240        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24241        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24242        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24243        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24245        // (intrinsic_wo_chain:{ *:[v4i32] } 1653:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
24246        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
24247        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24248        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
24249        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
24250        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
24251        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24252        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
24253        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24254        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
24255        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
24256        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
24257        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53,
24258        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2,
24259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1M,
24260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
24262        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
24264        GIR_EraseFromParent, /*InsnID*/0,
24265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24266        // GIR_Coverage, 2562,
24267        GIR_Done,
24268      // Label 1270: @63091
24269      GIM_Try, /*On fail goto*//*Label 1271*/ 63187, // Rule ID 2563 //
24270        GIM_CheckFeatures, GIFBS_HasNEON,
24271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1p,
24272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24275        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24277        // (intrinsic_wo_chain:{ *:[v4i32] } 1654:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
24278        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
24279        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24280        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
24281        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
24282        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
24283        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24284        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
24285        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24286        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
24287        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
24288        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
24289        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53,
24290        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2,
24291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1P,
24292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
24294        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
24296        GIR_EraseFromParent, /*InsnID*/0,
24297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24298        // GIR_Coverage, 2563,
24299        GIR_Done,
24300      // Label 1271: @63187
24301      GIM_Reject,
24302    // Label 1163: @63188
24303    GIM_Try, /*On fail goto*//*Label 1272*/ 66550,
24304      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
24305      GIM_Try, /*On fail goto*//*Label 1273*/ 63276, // Rule ID 3137 //
24306        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24307        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24308        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24309        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24310        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24311        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24314        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
24315        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24316        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24317        // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
24318        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24319        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24320        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8bh,
24322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24324        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24325        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24326        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24327        GIR_EraseFromParent, /*InsnID*/0,
24328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24329        // GIR_Coverage, 3137,
24330        GIR_Done,
24331      // Label 1273: @63276
24332      GIM_Try, /*On fail goto*//*Label 1274*/ 63359, // Rule ID 3141 //
24333        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24334        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24335        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24336        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24337        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24338        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24341        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
24342        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24343        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24344        // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
24345        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24346        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24347        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24348        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8th,
24349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24351        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24352        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24353        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24354        GIR_EraseFromParent, /*InsnID*/0,
24355        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24356        // GIR_Coverage, 3141,
24357        GIR_Done,
24358      // Label 1274: @63359
24359      GIM_Try, /*On fail goto*//*Label 1275*/ 63442, // Rule ID 3145 //
24360        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24361        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24362        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24363        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24364        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24365        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24368        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
24369        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24370        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24371        // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
24372        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24373        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24374        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24375        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16bh,
24376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24378        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24379        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24380        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24381        GIR_EraseFromParent, /*InsnID*/0,
24382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24383        // GIR_Coverage, 3145,
24384        GIR_Done,
24385      // Label 1275: @63442
24386      GIM_Try, /*On fail goto*//*Label 1276*/ 63525, // Rule ID 3149 //
24387        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24388        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24389        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24390        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24391        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24392        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24395        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
24396        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24397        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24398        // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
24399        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24400        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24401        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16th,
24403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24405        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24406        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24407        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24408        GIR_EraseFromParent, /*InsnID*/0,
24409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24410        // GIR_Coverage, 3149,
24411        GIR_Done,
24412      // Label 1276: @63525
24413      GIM_Try, /*On fail goto*//*Label 1277*/ 63608, // Rule ID 3153 //
24414        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24415        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24416        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24417        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24418        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24419        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24422        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
24423        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24424        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24425        // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
24426        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24427        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24428        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24429        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8bh,
24430        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24432        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24433        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24434        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24435        GIR_EraseFromParent, /*InsnID*/0,
24436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24437        // GIR_Coverage, 3153,
24438        GIR_Done,
24439      // Label 1277: @63608
24440      GIM_Try, /*On fail goto*//*Label 1278*/ 63691, // Rule ID 3157 //
24441        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24442        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24443        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24444        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24445        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24446        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24449        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
24450        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24451        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24452        // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
24453        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24454        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24455        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24456        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8th,
24457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24459        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24460        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24461        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24462        GIR_EraseFromParent, /*InsnID*/0,
24463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24464        // GIR_Coverage, 3157,
24465        GIR_Done,
24466      // Label 1278: @63691
24467      GIM_Try, /*On fail goto*//*Label 1279*/ 63774, // Rule ID 3161 //
24468        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24469        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24470        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24471        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24472        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24473        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24476        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
24477        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24478        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24479        // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
24480        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24481        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24482        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16bh,
24484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24486        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24487        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24488        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24489        GIR_EraseFromParent, /*InsnID*/0,
24490        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24491        // GIR_Coverage, 3161,
24492        GIR_Done,
24493      // Label 1279: @63774
24494      GIM_Try, /*On fail goto*//*Label 1280*/ 63857, // Rule ID 3165 //
24495        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
24496        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24497        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24498        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24499        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24500        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24503        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
24504        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24505        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24506        // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
24507        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24508        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24509        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16th,
24511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24513        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24514        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24515        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24516        GIR_EraseFromParent, /*InsnID*/0,
24517        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24518        // GIR_Coverage, 3165,
24519        GIR_Done,
24520      // Label 1280: @63857
24521      GIM_Try, /*On fail goto*//*Label 1281*/ 63946, // Rule ID 3539 //
24522        GIM_CheckFeatures, GIFBS_HasMVEInt,
24523        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24524        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24525        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24526        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24527        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24528        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24532        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24533        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24534        // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24535        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24536        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24537        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24538        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs8,
24539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24542        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24543        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24544        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24545        GIR_EraseFromParent, /*InsnID*/0,
24546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24547        // GIR_Coverage, 3539,
24548        GIR_Done,
24549      // Label 1281: @63946
24550      GIM_Try, /*On fail goto*//*Label 1282*/ 64035, // Rule ID 3541 //
24551        GIM_CheckFeatures, GIFBS_HasMVEInt,
24552        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24553        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24554        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24555        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24556        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24557        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24561        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24562        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24563        // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24564        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24565        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24566        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24567        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs8,
24568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24571        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24572        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24573        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24574        GIR_EraseFromParent, /*InsnID*/0,
24575        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24576        // GIR_Coverage, 3541,
24577        GIR_Done,
24578      // Label 1282: @64035
24579      GIM_Try, /*On fail goto*//*Label 1283*/ 64124, // Rule ID 3543 //
24580        GIM_CheckFeatures, GIFBS_HasMVEInt,
24581        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24582        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24583        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24584        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24585        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24586        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24590        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24591        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24592        // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24593        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24594        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24595        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs16,
24597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24600        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24601        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24602        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24603        GIR_EraseFromParent, /*InsnID*/0,
24604        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24605        // GIR_Coverage, 3543,
24606        GIR_Done,
24607      // Label 1283: @64124
24608      GIM_Try, /*On fail goto*//*Label 1284*/ 64213, // Rule ID 3545 //
24609        GIM_CheckFeatures, GIFBS_HasMVEInt,
24610        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24611        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24612        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24613        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24614        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24615        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24619        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24620        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24621        // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24622        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24623        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24624        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24625        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs16,
24626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24629        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24630        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24631        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24632        GIR_EraseFromParent, /*InsnID*/0,
24633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24634        // GIR_Coverage, 3545,
24635        GIR_Done,
24636      // Label 1284: @64213
24637      GIM_Try, /*On fail goto*//*Label 1285*/ 64302, // Rule ID 3547 //
24638        GIM_CheckFeatures, GIFBS_HasMVEInt,
24639        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24640        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
24641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24643        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24644        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24648        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24649        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24650        // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24651        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24652        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24653        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs32,
24655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24658        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24659        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24660        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24661        GIR_EraseFromParent, /*InsnID*/0,
24662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24663        // GIR_Coverage, 3547,
24664        GIR_Done,
24665      // Label 1285: @64302
24666      GIM_Try, /*On fail goto*//*Label 1286*/ 64391, // Rule ID 3549 //
24667        GIM_CheckFeatures, GIFBS_HasMVEInt,
24668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
24670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24671        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24672        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24673        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24677        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24678        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24679        // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24680        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24681        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24682        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24683        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs32,
24684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24687        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24688        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24689        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24690        GIR_EraseFromParent, /*InsnID*/0,
24691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24692        // GIR_Coverage, 3549,
24693        GIR_Done,
24694      // Label 1286: @64391
24695      GIM_Try, /*On fail goto*//*Label 1287*/ 64480, // Rule ID 3551 //
24696        GIM_CheckFeatures, GIFBS_HasMVEInt,
24697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24701        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24702        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24706        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24707        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24708        // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24709        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24710        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24711        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24712        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu8,
24713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24716        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24717        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24718        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24719        GIR_EraseFromParent, /*InsnID*/0,
24720        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24721        // GIR_Coverage, 3551,
24722        GIR_Done,
24723      // Label 1287: @64480
24724      GIM_Try, /*On fail goto*//*Label 1288*/ 64569, // Rule ID 3553 //
24725        GIM_CheckFeatures, GIFBS_HasMVEInt,
24726        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24727        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24728        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24729        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24730        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24731        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24735        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24736        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24737        // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24738        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24739        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24740        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24741        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu8,
24742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24745        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24746        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24747        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24748        GIR_EraseFromParent, /*InsnID*/0,
24749        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24750        // GIR_Coverage, 3553,
24751        GIR_Done,
24752      // Label 1288: @64569
24753      GIM_Try, /*On fail goto*//*Label 1289*/ 64658, // Rule ID 3555 //
24754        GIM_CheckFeatures, GIFBS_HasMVEInt,
24755        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24756        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24757        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24758        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24759        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24760        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24761        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24764        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24765        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24766        // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24767        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24768        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24769        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu16,
24771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24774        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24775        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24776        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24777        GIR_EraseFromParent, /*InsnID*/0,
24778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24779        // GIR_Coverage, 3555,
24780        GIR_Done,
24781      // Label 1289: @64658
24782      GIM_Try, /*On fail goto*//*Label 1290*/ 64747, // Rule ID 3557 //
24783        GIM_CheckFeatures, GIFBS_HasMVEInt,
24784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24787        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24788        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24789        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24793        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24794        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24795        // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24796        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24797        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24798        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu16,
24800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24803        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24804        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24805        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24806        GIR_EraseFromParent, /*InsnID*/0,
24807        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24808        // GIR_Coverage, 3557,
24809        GIR_Done,
24810      // Label 1290: @64747
24811      GIM_Try, /*On fail goto*//*Label 1291*/ 64836, // Rule ID 3559 //
24812        GIM_CheckFeatures, GIFBS_HasMVEInt,
24813        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24814        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
24815        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24816        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24817        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24818        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24822        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24823        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
24824        // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24825        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24826        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24827        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24828        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu32,
24829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24832        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24833        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24834        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24835        GIR_EraseFromParent, /*InsnID*/0,
24836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24837        // GIR_Coverage, 3559,
24838        GIR_Done,
24839      // Label 1291: @64836
24840      GIM_Try, /*On fail goto*//*Label 1292*/ 64925, // Rule ID 3561 //
24841        GIM_CheckFeatures, GIFBS_HasMVEInt,
24842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
24843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
24844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24845        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24846        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24847        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
24848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24851        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24852        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
24853        // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24854        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24855        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24856        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu32,
24858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24861        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24862        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24863        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24864        GIR_EraseFromParent, /*InsnID*/0,
24865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24866        // GIR_Coverage, 3561,
24867        GIR_Done,
24868      // Label 1292: @64925
24869      GIM_Try, /*On fail goto*//*Label 1293*/ 65022, // Rule ID 3392 //
24870        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24871        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
24872        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24873        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24874        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24875        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
24876        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
24877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24878        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24879        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24880        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24881        // MIs[1] Operand 1
24882        // No operand predicates
24883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
24884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
24885        GIM_CheckIsSafeToFold, /*InsnID*/1,
24886        // (intrinsic_wo_chain:{ *:[v8f16] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
24887        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24888        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24889        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24890        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf16,
24891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
24893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
24894        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
24895        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24896        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24897        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24898        GIR_EraseFromParent, /*InsnID*/0,
24899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24900        // GIR_Coverage, 3392,
24901        GIR_Done,
24902      // Label 1293: @65022
24903      GIM_Try, /*On fail goto*//*Label 1294*/ 65119, // Rule ID 3394 //
24904        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24905        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
24906        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24907        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24909        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
24910        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
24911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24912        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24913        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24914        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24915        // MIs[1] Operand 1
24916        // No operand predicates
24917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
24918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
24919        GIM_CheckIsSafeToFold, /*InsnID*/1,
24920        // (intrinsic_wo_chain:{ *:[v4f32] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
24921        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24922        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24923        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf32,
24925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
24927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
24928        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
24929        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24930        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24931        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24932        GIR_EraseFromParent, /*InsnID*/0,
24933        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24934        // GIR_Coverage, 3394,
24935        GIR_Done,
24936      // Label 1294: @65119
24937      GIM_Try, /*On fail goto*//*Label 1295*/ 65216, // Rule ID 3603 //
24938        GIM_CheckFeatures, GIFBS_HasMVEInt,
24939        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
24940        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24941        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24942        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24943        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
24944        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
24945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24946        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24947        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24948        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24949        // MIs[1] Operand 1
24950        // No operand predicates
24951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
24952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
24953        GIM_CheckIsSafeToFold, /*InsnID*/1,
24954        // (intrinsic_wo_chain:{ *:[v16i8] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
24955        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24956        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24957        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi8,
24959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
24961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
24962        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
24963        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24964        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24965        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24966        GIR_EraseFromParent, /*InsnID*/0,
24967        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24968        // GIR_Coverage, 3603,
24969        GIR_Done,
24970      // Label 1295: @65216
24971      GIM_Try, /*On fail goto*//*Label 1296*/ 65313, // Rule ID 3605 //
24972        GIM_CheckFeatures, GIFBS_HasMVEInt,
24973        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
24974        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24975        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24976        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24977        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
24978        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
24979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24980        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24981        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24982        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24983        // MIs[1] Operand 1
24984        // No operand predicates
24985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
24986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
24987        GIM_CheckIsSafeToFold, /*InsnID*/1,
24988        // (intrinsic_wo_chain:{ *:[v8i16] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
24989        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24990        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24991        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi16,
24993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
24995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
24996        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
24997        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24998        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
24999        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25000        GIR_EraseFromParent, /*InsnID*/0,
25001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25002        // GIR_Coverage, 3605,
25003        GIR_Done,
25004      // Label 1296: @65313
25005      GIM_Try, /*On fail goto*//*Label 1297*/ 65410, // Rule ID 3607 //
25006        GIM_CheckFeatures, GIFBS_HasMVEInt,
25007        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
25008        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25009        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25010        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25011        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
25012        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
25013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25014        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25015        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25016        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25017        // MIs[1] Operand 1
25018        // No operand predicates
25019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25021        GIM_CheckIsSafeToFold, /*InsnID*/1,
25022        // (intrinsic_wo_chain:{ *:[v4i32] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
25023        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25024        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25025        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25026        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi32,
25027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25030        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25031        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25032        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25033        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25034        GIR_EraseFromParent, /*InsnID*/0,
25035        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25036        // GIR_Coverage, 3607,
25037        GIR_Done,
25038      // Label 1297: @65410
25039      GIM_Try, /*On fail goto*//*Label 1298*/ 65507, // Rule ID 3609 //
25040        GIM_CheckFeatures, GIFBS_HasMVEInt,
25041        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
25042        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25043        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25044        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25045        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
25046        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
25047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25048        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25049        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25050        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25051        // MIs[1] Operand 1
25052        // No operand predicates
25053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25055        GIM_CheckIsSafeToFold, /*InsnID*/1,
25056        // (intrinsic_wo_chain:{ *:[v16i8] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
25057        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25058        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25059        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs8,
25061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25064        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25065        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25066        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25067        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25068        GIR_EraseFromParent, /*InsnID*/0,
25069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25070        // GIR_Coverage, 3609,
25071        GIR_Done,
25072      // Label 1298: @65507
25073      GIM_Try, /*On fail goto*//*Label 1299*/ 65604, // Rule ID 3611 //
25074        GIM_CheckFeatures, GIFBS_HasMVEInt,
25075        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
25076        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25077        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25078        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25079        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
25080        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
25081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25082        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25083        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25084        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25085        // MIs[1] Operand 1
25086        // No operand predicates
25087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25089        GIM_CheckIsSafeToFold, /*InsnID*/1,
25090        // (intrinsic_wo_chain:{ *:[v8i16] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
25091        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25092        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25093        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs16,
25095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25098        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25099        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25100        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25101        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25102        GIR_EraseFromParent, /*InsnID*/0,
25103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25104        // GIR_Coverage, 3611,
25105        GIR_Done,
25106      // Label 1299: @65604
25107      GIM_Try, /*On fail goto*//*Label 1300*/ 65701, // Rule ID 3613 //
25108        GIM_CheckFeatures, GIFBS_HasMVEInt,
25109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
25110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25112        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25113        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
25114        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
25115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25116        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25117        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25118        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25119        // MIs[1] Operand 1
25120        // No operand predicates
25121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25123        GIM_CheckIsSafeToFold, /*InsnID*/1,
25124        // (intrinsic_wo_chain:{ *:[v4i32] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
25125        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25126        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25127        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs32,
25129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25132        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25133        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25134        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25135        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25136        GIR_EraseFromParent, /*InsnID*/0,
25137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25138        // GIR_Coverage, 3613,
25139        GIR_Done,
25140      // Label 1300: @65701
25141      GIM_Try, /*On fail goto*//*Label 1301*/ 65780, // Rule ID 2799 //
25142        GIM_CheckFeatures, GIFBS_HasMVEInt,
25143        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25144        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25145        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25146        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25147        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
25148        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
25149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25150        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25154        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
25155        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs8,
25156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25160        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25161        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25162        GIR_EraseFromParent, /*InsnID*/0,
25163        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25164        // GIR_Coverage, 2799,
25165        GIR_Done,
25166      // Label 1301: @65780
25167      GIM_Try, /*On fail goto*//*Label 1302*/ 65859, // Rule ID 2801 //
25168        GIM_CheckFeatures, GIFBS_HasMVEInt,
25169        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25170        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25171        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25172        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25173        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
25174        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
25175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25176        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25180        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
25181        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs16,
25182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25186        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25187        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25188        GIR_EraseFromParent, /*InsnID*/0,
25189        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25190        // GIR_Coverage, 2801,
25191        GIR_Done,
25192      // Label 1302: @65859
25193      GIM_Try, /*On fail goto*//*Label 1303*/ 65938, // Rule ID 2803 //
25194        GIM_CheckFeatures, GIFBS_HasMVEInt,
25195        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25196        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25197        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25198        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25199        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
25200        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
25201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25202        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25206        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
25207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs32,
25208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25212        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25213        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25214        GIR_EraseFromParent, /*InsnID*/0,
25215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25216        // GIR_Coverage, 2803,
25217        GIR_Done,
25218      // Label 1303: @65938
25219      GIM_Try, /*On fail goto*//*Label 1304*/ 66017, // Rule ID 2805 //
25220        GIM_CheckFeatures, GIFBS_HasMVEInt,
25221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25225        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
25226        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
25227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25228        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25232        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
25233        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu8,
25234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25238        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25239        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25240        GIR_EraseFromParent, /*InsnID*/0,
25241        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25242        // GIR_Coverage, 2805,
25243        GIR_Done,
25244      // Label 1304: @66017
25245      GIM_Try, /*On fail goto*//*Label 1305*/ 66096, // Rule ID 2807 //
25246        GIM_CheckFeatures, GIFBS_HasMVEInt,
25247        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25248        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25249        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25250        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25251        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
25252        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
25253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25254        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25258        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
25259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu16,
25260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25264        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25265        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25266        GIR_EraseFromParent, /*InsnID*/0,
25267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25268        // GIR_Coverage, 2807,
25269        GIR_Done,
25270      // Label 1305: @66096
25271      GIM_Try, /*On fail goto*//*Label 1306*/ 66175, // Rule ID 2809 //
25272        GIM_CheckFeatures, GIFBS_HasMVEInt,
25273        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
25274        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25275        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25276        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
25277        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
25278        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
25279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25280        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
25282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25284        // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
25285        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu32,
25286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
25287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
25288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25290        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25291        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25292        GIR_EraseFromParent, /*InsnID*/0,
25293        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25294        // GIR_Coverage, 2809,
25295        GIR_Done,
25296      // Label 1306: @66175
25297      GIM_Try, /*On fail goto*//*Label 1307*/ 66262, // Rule ID 3376 //
25298        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25299        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
25300        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25301        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25302        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25303        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
25304        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
25305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25306        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25307        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25308        // MIs[1] Operand 1
25309        // No operand predicates
25310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25313        GIM_CheckIsSafeToFold, /*InsnID*/1,
25314        // (intrinsic_wo_chain:{ *:[v8f16] } 1587:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
25315        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf16,
25316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
25318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25320        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25321        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25322        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25323        GIR_EraseFromParent, /*InsnID*/0,
25324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25325        // GIR_Coverage, 3376,
25326        GIR_Done,
25327      // Label 1307: @66262
25328      GIM_Try, /*On fail goto*//*Label 1308*/ 66349, // Rule ID 3378 //
25329        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
25331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25333        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25334        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
25335        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
25336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25337        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25338        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25339        // MIs[1] Operand 1
25340        // No operand predicates
25341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
25343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
25344        GIM_CheckIsSafeToFold, /*InsnID*/1,
25345        // (intrinsic_wo_chain:{ *:[v4f32] } 1587:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
25346        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf32,
25347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
25349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
25350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
25351        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
25352        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25353        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25354        GIR_EraseFromParent, /*InsnID*/0,
25355        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25356        // GIR_Coverage, 3378,
25357        GIR_Done,
25358      // Label 1308: @66349
25359      GIM_Try, /*On fail goto*//*Label 1309*/ 66438, // Rule ID 2555 //
25360        GIM_CheckFeatures, GIFBS_HasNEON,
25361        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx2,
25362        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
25363        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
25364        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
25365        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
25366        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
25367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
25368        // (intrinsic_wo_chain:{ *:[v8i8] } 1775:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
25369        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
25370        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
25371        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
25372        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
25373        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
25374        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
25375        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
25376        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25377        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX2,
25378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
25379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
25380        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
25382        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
25383        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25384        GIR_EraseFromParent, /*InsnID*/0,
25385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25386        // GIR_Coverage, 2555,
25387        GIR_Done,
25388      // Label 1309: @66438
25389      GIM_Try, /*On fail goto*//*Label 1310*/ 66549, // Rule ID 2556 //
25390        GIM_CheckFeatures, GIFBS_HasNEON,
25391        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl3,
25392        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
25393        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
25394        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
25395        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
25396        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
25397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
25398        // (intrinsic_wo_chain:{ *:[v8i8] } 1772:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
25399        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
25400        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
25401        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25402        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
25403        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
25404        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
25405        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
25406        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
25407        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
25408        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
25409        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
25410        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
25411        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
25412        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
25413        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
25414        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL3Pseudo,
25416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
25417        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
25419        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
25420        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25421        GIR_EraseFromParent, /*InsnID*/0,
25422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25423        // GIR_Coverage, 2556,
25424        GIR_Done,
25425      // Label 1310: @66549
25426      GIM_Reject,
25427    // Label 1272: @66550
25428    GIM_Try, /*On fail goto*//*Label 1311*/ 71002,
25429      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
25430      GIM_Try, /*On fail goto*//*Label 1312*/ 66650, // Rule ID 3248 //
25431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25432        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25433        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25434        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25435        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25436        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25437        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25440        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25441        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25442        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25443        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25444        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25445        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25446        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25447        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25448        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs8,
25449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25452        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25453        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25454        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25455        GIR_EraseFromParent, /*InsnID*/0,
25456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25457        // GIR_Coverage, 3248,
25458        GIR_Done,
25459      // Label 1312: @66650
25460      GIM_Try, /*On fail goto*//*Label 1313*/ 66745, // Rule ID 3250 //
25461        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25462        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25463        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25464        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25465        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25466        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25467        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25471        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25472        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25473        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25474        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25475        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25476        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25477        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25478        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs16,
25479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25482        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25483        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25484        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25485        GIR_EraseFromParent, /*InsnID*/0,
25486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25487        // GIR_Coverage, 3250,
25488        GIR_Done,
25489      // Label 1313: @66745
25490      GIM_Try, /*On fail goto*//*Label 1314*/ 66840, // Rule ID 3252 //
25491        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25492        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25493        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25494        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25495        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25496        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25497        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25501        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25502        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25503        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25504        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25505        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25506        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25507        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs32,
25509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25512        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25513        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25514        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25515        GIR_EraseFromParent, /*InsnID*/0,
25516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25517        // GIR_Coverage, 3252,
25518        GIR_Done,
25519      // Label 1314: @66840
25520      GIM_Try, /*On fail goto*//*Label 1315*/ 66935, // Rule ID 3254 //
25521        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25525        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25526        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25527        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25531        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25532        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25533        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25534        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25535        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25536        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25537        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25538        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu8,
25539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25542        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25543        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25544        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25545        GIR_EraseFromParent, /*InsnID*/0,
25546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25547        // GIR_Coverage, 3254,
25548        GIR_Done,
25549      // Label 1315: @66935
25550      GIM_Try, /*On fail goto*//*Label 1316*/ 67030, // Rule ID 3256 //
25551        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25552        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25553        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25554        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25555        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25556        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25557        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25561        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25562        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25563        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25564        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25565        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25566        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25567        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25568        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu16,
25569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25572        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25573        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25574        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25575        GIR_EraseFromParent, /*InsnID*/0,
25576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25577        // GIR_Coverage, 3256,
25578        GIR_Done,
25579      // Label 1316: @67030
25580      GIM_Try, /*On fail goto*//*Label 1317*/ 67125, // Rule ID 3258 //
25581        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25582        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25583        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25584        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25585        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25586        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25587        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25591        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25592        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25593        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25594        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25595        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25596        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25597        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu32,
25599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25602        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25603        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25604        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25605        GIR_EraseFromParent, /*InsnID*/0,
25606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25607        // GIR_Coverage, 3258,
25608        GIR_Done,
25609      // Label 1317: @67125
25610      GIM_Try, /*On fail goto*//*Label 1318*/ 67220, // Rule ID 3260 //
25611        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25612        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25613        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25614        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25615        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25616        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25617        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25621        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25622        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25623        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25624        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25625        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25626        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25627        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25628        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs8,
25629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25632        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25633        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25634        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25635        GIR_EraseFromParent, /*InsnID*/0,
25636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25637        // GIR_Coverage, 3260,
25638        GIR_Done,
25639      // Label 1318: @67220
25640      GIM_Try, /*On fail goto*//*Label 1319*/ 67315, // Rule ID 3262 //
25641        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25642        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25643        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25644        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25645        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25646        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25647        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25651        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25652        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25653        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25654        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25655        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25656        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25657        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs16,
25659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25662        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25663        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25664        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25665        GIR_EraseFromParent, /*InsnID*/0,
25666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25667        // GIR_Coverage, 3262,
25668        GIR_Done,
25669      // Label 1319: @67315
25670      GIM_Try, /*On fail goto*//*Label 1320*/ 67410, // Rule ID 3264 //
25671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25675        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25676        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25677        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25681        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25682        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25683        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25684        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25685        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25686        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25687        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25688        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs32,
25689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25692        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25693        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25694        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25695        GIR_EraseFromParent, /*InsnID*/0,
25696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25697        // GIR_Coverage, 3264,
25698        GIR_Done,
25699      // Label 1320: @67410
25700      GIM_Try, /*On fail goto*//*Label 1321*/ 67505, // Rule ID 3266 //
25701        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25702        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25703        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25704        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25705        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25706        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25707        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25711        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25712        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25713        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25714        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25715        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25716        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25717        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu8,
25719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25722        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25723        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25724        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25725        GIR_EraseFromParent, /*InsnID*/0,
25726        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25727        // GIR_Coverage, 3266,
25728        GIR_Done,
25729      // Label 1321: @67505
25730      GIM_Try, /*On fail goto*//*Label 1322*/ 67600, // Rule ID 3268 //
25731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25735        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25736        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25737        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25741        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25742        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25743        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25744        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25745        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25746        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25747        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25748        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu16,
25749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25752        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25753        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25754        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25755        GIR_EraseFromParent, /*InsnID*/0,
25756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25757        // GIR_Coverage, 3268,
25758        GIR_Done,
25759      // Label 1322: @67600
25760      GIM_Try, /*On fail goto*//*Label 1323*/ 67695, // Rule ID 3270 //
25761        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25762        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25763        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25764        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25765        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25766        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25767        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25771        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25772        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
25773        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25774        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25775        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25776        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25777        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25778        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu32,
25779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25782        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25783        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25784        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25785        GIR_EraseFromParent, /*InsnID*/0,
25786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25787        // GIR_Coverage, 3270,
25788        GIR_Done,
25789      // Label 1323: @67695
25790      GIM_Try, /*On fail goto*//*Label 1324*/ 67790, // Rule ID 3272 //
25791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25792        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25793        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25795        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25796        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25797        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25801        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25802        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25803        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25804        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25805        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25806        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25807        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs8,
25809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25812        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25813        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25814        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25815        GIR_EraseFromParent, /*InsnID*/0,
25816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25817        // GIR_Coverage, 3272,
25818        GIR_Done,
25819      // Label 1324: @67790
25820      GIM_Try, /*On fail goto*//*Label 1325*/ 67885, // Rule ID 3274 //
25821        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25822        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25823        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25824        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25825        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25826        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25827        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25831        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25832        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25833        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25834        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25835        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25836        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25837        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs16,
25839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25842        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25843        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25844        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25845        GIR_EraseFromParent, /*InsnID*/0,
25846        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25847        // GIR_Coverage, 3274,
25848        GIR_Done,
25849      // Label 1325: @67885
25850      GIM_Try, /*On fail goto*//*Label 1326*/ 67980, // Rule ID 3276 //
25851        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25852        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25853        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25854        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25855        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25856        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25857        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25861        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25862        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25863        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25864        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25865        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25866        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25867        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25868        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs32,
25869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25872        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25873        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25874        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25875        GIR_EraseFromParent, /*InsnID*/0,
25876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25877        // GIR_Coverage, 3276,
25878        GIR_Done,
25879      // Label 1326: @67980
25880      GIM_Try, /*On fail goto*//*Label 1327*/ 68075, // Rule ID 3278 //
25881        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25882        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25883        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25884        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25885        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25886        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25887        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25891        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25892        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25893        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25894        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25895        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25896        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25897        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu8,
25899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25902        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25903        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25904        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25905        GIR_EraseFromParent, /*InsnID*/0,
25906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25907        // GIR_Coverage, 3278,
25908        GIR_Done,
25909      // Label 1327: @68075
25910      GIM_Try, /*On fail goto*//*Label 1328*/ 68170, // Rule ID 3280 //
25911        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25912        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25913        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25914        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25915        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25916        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25917        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25921        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25922        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25923        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25924        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
25925        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25926        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25927        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu16,
25929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25932        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25933        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25934        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25935        GIR_EraseFromParent, /*InsnID*/0,
25936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25937        // GIR_Coverage, 3280,
25938        GIR_Done,
25939      // Label 1328: @68170
25940      GIM_Try, /*On fail goto*//*Label 1329*/ 68265, // Rule ID 3282 //
25941        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25942        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25943        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25944        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25945        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25946        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25947        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25951        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25952        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25953        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
25954        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
25955        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25956        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25957        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu32,
25959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25962        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25963        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25964        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25965        GIR_EraseFromParent, /*InsnID*/0,
25966        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25967        // GIR_Coverage, 3282,
25968        GIR_Done,
25969      // Label 1329: @68265
25970      GIM_Try, /*On fail goto*//*Label 1330*/ 68360, // Rule ID 3284 //
25971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
25972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25974        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25975        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25976        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
25977        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
25978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25981        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25982        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
25983        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
25984        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
25985        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25986        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25987        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25988        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs8,
25989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
25991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
25992        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25993        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
25994        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25995        GIR_EraseFromParent, /*InsnID*/0,
25996        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25997        // GIR_Coverage, 3284,
25998        GIR_Done,
25999      // Label 1330: @68360
26000      GIM_Try, /*On fail goto*//*Label 1331*/ 68455, // Rule ID 3286 //
26001        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
26002        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26003        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26004        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26005        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26006        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26007        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26011        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26012        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26013        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26014        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
26015        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26016        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26017        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs16,
26019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26022        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26023        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26024        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26025        GIR_EraseFromParent, /*InsnID*/0,
26026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26027        // GIR_Coverage, 3286,
26028        GIR_Done,
26029      // Label 1331: @68455
26030      GIM_Try, /*On fail goto*//*Label 1332*/ 68550, // Rule ID 3288 //
26031        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
26032        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26033        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26034        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26035        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26036        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26037        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26041        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26042        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26043        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26044        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
26045        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26046        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26047        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs32,
26049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26052        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26053        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26054        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26055        GIR_EraseFromParent, /*InsnID*/0,
26056        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26057        // GIR_Coverage, 3288,
26058        GIR_Done,
26059      // Label 1332: @68550
26060      GIM_Try, /*On fail goto*//*Label 1333*/ 68645, // Rule ID 3290 //
26061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
26062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26065        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26066        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26067        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26071        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26072        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26073        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26074        // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
26075        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26076        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26077        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu8,
26079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26082        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26083        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26084        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26085        GIR_EraseFromParent, /*InsnID*/0,
26086        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26087        // GIR_Coverage, 3290,
26088        GIR_Done,
26089      // Label 1333: @68645
26090      GIM_Try, /*On fail goto*//*Label 1334*/ 68740, // Rule ID 3292 //
26091        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
26092        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26093        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26094        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26095        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26096        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26097        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26101        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26102        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26103        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26104        // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
26105        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26106        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26107        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26108        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu16,
26109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26112        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26113        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26114        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26115        GIR_EraseFromParent, /*InsnID*/0,
26116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26117        // GIR_Coverage, 3292,
26118        GIR_Done,
26119      // Label 1334: @68740
26120      GIM_Try, /*On fail goto*//*Label 1335*/ 68835, // Rule ID 3294 //
26121        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
26122        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26123        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26124        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26125        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26126        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26127        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26131        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26132        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26133        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26134        // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
26135        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26136        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26137        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu32,
26139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26142        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26143        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26144        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26145        GIR_EraseFromParent, /*InsnID*/0,
26146        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26147        // GIR_Coverage, 3294,
26148        GIR_Done,
26149      // Label 1335: @68835
26150      GIM_Try, /*On fail goto*//*Label 1336*/ 68916, // Rule ID 3621 //
26151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26155        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26156        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26157        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26160        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26161        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26162        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26163        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26164        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs8,
26166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26169        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26170        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26171        GIR_EraseFromParent, /*InsnID*/0,
26172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26173        // GIR_Coverage, 3621,
26174        GIR_Done,
26175      // Label 1336: @68916
26176      GIM_Try, /*On fail goto*//*Label 1337*/ 68997, // Rule ID 3623 //
26177        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26178        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26179        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26180        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26181        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26182        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26183        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26187        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26188        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26189        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26190        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs16,
26192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26195        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26196        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26197        GIR_EraseFromParent, /*InsnID*/0,
26198        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26199        // GIR_Coverage, 3623,
26200        GIR_Done,
26201      // Label 1337: @68997
26202      GIM_Try, /*On fail goto*//*Label 1338*/ 69078, // Rule ID 3625 //
26203        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26204        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26205        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26206        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26207        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26208        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26209        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26213        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26214        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26215        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26216        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26217        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs32,
26218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26221        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26222        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26223        GIR_EraseFromParent, /*InsnID*/0,
26224        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26225        // GIR_Coverage, 3625,
26226        GIR_Done,
26227      // Label 1338: @69078
26228      GIM_Try, /*On fail goto*//*Label 1339*/ 69159, // Rule ID 3627 //
26229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26233        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26234        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26235        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26239        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26240        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26241        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26242        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru8,
26244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26247        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26248        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26249        GIR_EraseFromParent, /*InsnID*/0,
26250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26251        // GIR_Coverage, 3627,
26252        GIR_Done,
26253      // Label 1339: @69159
26254      GIM_Try, /*On fail goto*//*Label 1340*/ 69240, // Rule ID 3629 //
26255        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26256        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26257        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26258        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26259        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26260        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26261        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26265        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26266        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26267        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26268        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru16,
26270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26273        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26274        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26275        GIR_EraseFromParent, /*InsnID*/0,
26276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26277        // GIR_Coverage, 3629,
26278        GIR_Done,
26279      // Label 1340: @69240
26280      GIM_Try, /*On fail goto*//*Label 1341*/ 69321, // Rule ID 3631 //
26281        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26282        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26283        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26284        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26285        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26286        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26287        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26291        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26292        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26293        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26294        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26295        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru32,
26296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26299        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26300        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26301        GIR_EraseFromParent, /*InsnID*/0,
26302        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26303        // GIR_Coverage, 3631,
26304        GIR_Done,
26305      // Label 1341: @69321
26306      GIM_Try, /*On fail goto*//*Label 1342*/ 69402, // Rule ID 3633 //
26307        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26308        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26309        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26310        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26311        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26312        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26313        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26317        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26318        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26319        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26320        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs8,
26322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26325        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26326        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26327        GIR_EraseFromParent, /*InsnID*/0,
26328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26329        // GIR_Coverage, 3633,
26330        GIR_Done,
26331      // Label 1342: @69402
26332      GIM_Try, /*On fail goto*//*Label 1343*/ 69483, // Rule ID 3635 //
26333        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26334        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26335        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26336        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26337        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26338        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26339        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26343        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26344        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26345        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26346        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26347        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs16,
26348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26351        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26352        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26353        GIR_EraseFromParent, /*InsnID*/0,
26354        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26355        // GIR_Coverage, 3635,
26356        GIR_Done,
26357      // Label 1343: @69483
26358      GIM_Try, /*On fail goto*//*Label 1344*/ 69564, // Rule ID 3637 //
26359        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26360        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26361        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26362        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26363        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26364        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26365        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26369        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26370        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26371        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26372        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs32,
26374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26377        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26378        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26379        GIR_EraseFromParent, /*InsnID*/0,
26380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26381        // GIR_Coverage, 3637,
26382        GIR_Done,
26383      // Label 1344: @69564
26384      GIM_Try, /*On fail goto*//*Label 1345*/ 69645, // Rule ID 3639 //
26385        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26386        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26387        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26388        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26389        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26390        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26391        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26395        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26396        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26397        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26398        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26399        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru8,
26400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26403        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26404        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26405        GIR_EraseFromParent, /*InsnID*/0,
26406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26407        // GIR_Coverage, 3639,
26408        GIR_Done,
26409      // Label 1345: @69645
26410      GIM_Try, /*On fail goto*//*Label 1346*/ 69726, // Rule ID 3641 //
26411        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26412        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26413        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26414        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26415        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26416        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26417        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26421        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26422        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26423        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26424        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26425        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru16,
26426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26429        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26430        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26431        GIR_EraseFromParent, /*InsnID*/0,
26432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26433        // GIR_Coverage, 3641,
26434        GIR_Done,
26435      // Label 1346: @69726
26436      GIM_Try, /*On fail goto*//*Label 1347*/ 69807, // Rule ID 3643 //
26437        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26438        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26439        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26440        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26441        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26442        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26443        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26447        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26448        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26449        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26450        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26451        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru32,
26452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26455        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26456        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26457        GIR_EraseFromParent, /*InsnID*/0,
26458        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26459        // GIR_Coverage, 3643,
26460        GIR_Done,
26461      // Label 1347: @69807
26462      GIM_Try, /*On fail goto*//*Label 1348*/ 69888, // Rule ID 3645 //
26463        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26464        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26465        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26466        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26467        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26468        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26469        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26473        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26474        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26475        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26476        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26477        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs8,
26478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26481        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26482        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26483        GIR_EraseFromParent, /*InsnID*/0,
26484        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26485        // GIR_Coverage, 3645,
26486        GIR_Done,
26487      // Label 1348: @69888
26488      GIM_Try, /*On fail goto*//*Label 1349*/ 69969, // Rule ID 3647 //
26489        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26490        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26491        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26492        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26493        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26494        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26495        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26499        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26500        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26501        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26502        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs16,
26504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26507        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26508        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26509        GIR_EraseFromParent, /*InsnID*/0,
26510        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26511        // GIR_Coverage, 3647,
26512        GIR_Done,
26513      // Label 1349: @69969
26514      GIM_Try, /*On fail goto*//*Label 1350*/ 70050, // Rule ID 3649 //
26515        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26516        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26517        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26518        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26519        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26520        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26521        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26525        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26526        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26527        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26528        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26529        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs32,
26530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26533        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26534        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26535        GIR_EraseFromParent, /*InsnID*/0,
26536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26537        // GIR_Coverage, 3649,
26538        GIR_Done,
26539      // Label 1350: @70050
26540      GIM_Try, /*On fail goto*//*Label 1351*/ 70131, // Rule ID 3651 //
26541        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26542        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26543        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26544        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26545        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26546        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26547        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26551        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26552        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26553        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26554        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26555        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru8,
26556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26559        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26560        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26561        GIR_EraseFromParent, /*InsnID*/0,
26562        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26563        // GIR_Coverage, 3651,
26564        GIR_Done,
26565      // Label 1351: @70131
26566      GIM_Try, /*On fail goto*//*Label 1352*/ 70212, // Rule ID 3653 //
26567        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26568        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26569        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26570        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26571        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26572        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26573        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26577        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26578        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26579        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26580        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru16,
26582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26585        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26586        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26587        GIR_EraseFromParent, /*InsnID*/0,
26588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26589        // GIR_Coverage, 3653,
26590        GIR_Done,
26591      // Label 1352: @70212
26592      GIM_Try, /*On fail goto*//*Label 1353*/ 70293, // Rule ID 3655 //
26593        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26594        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26595        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26596        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26597        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26598        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26599        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26603        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26604        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26605        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26606        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru32,
26608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26611        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26612        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26613        GIR_EraseFromParent, /*InsnID*/0,
26614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26615        // GIR_Coverage, 3655,
26616        GIR_Done,
26617      // Label 1353: @70293
26618      GIM_Try, /*On fail goto*//*Label 1354*/ 70374, // Rule ID 3657 //
26619        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26620        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26621        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26622        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26623        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26624        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26625        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26629        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26630        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26631        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26632        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26633        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs8,
26634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26637        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26638        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26639        GIR_EraseFromParent, /*InsnID*/0,
26640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26641        // GIR_Coverage, 3657,
26642        GIR_Done,
26643      // Label 1354: @70374
26644      GIM_Try, /*On fail goto*//*Label 1355*/ 70455, // Rule ID 3659 //
26645        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26646        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26647        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26648        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26649        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26650        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26651        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26655        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26656        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26657        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26658        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs16,
26660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26663        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26664        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26665        GIR_EraseFromParent, /*InsnID*/0,
26666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26667        // GIR_Coverage, 3659,
26668        GIR_Done,
26669      // Label 1355: @70455
26670      GIM_Try, /*On fail goto*//*Label 1356*/ 70536, // Rule ID 3661 //
26671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26675        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26676        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26677        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26681        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26682        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26683        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
26684        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs32,
26686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26689        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26690        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26691        GIR_EraseFromParent, /*InsnID*/0,
26692        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26693        // GIR_Coverage, 3661,
26694        GIR_Done,
26695      // Label 1356: @70536
26696      GIM_Try, /*On fail goto*//*Label 1357*/ 70617, // Rule ID 3663 //
26697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26701        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26702        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26703        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26707        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26708        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26709        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26710        // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
26711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru8,
26712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26715        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26716        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26717        GIR_EraseFromParent, /*InsnID*/0,
26718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26719        // GIR_Coverage, 3663,
26720        GIR_Done,
26721      // Label 1357: @70617
26722      GIM_Try, /*On fail goto*//*Label 1358*/ 70698, // Rule ID 3665 //
26723        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26724        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26725        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26726        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26727        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26728        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26729        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26733        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26734        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26735        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26736        // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
26737        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru16,
26738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26741        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26742        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26743        GIR_EraseFromParent, /*InsnID*/0,
26744        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26745        // GIR_Coverage, 3665,
26746        GIR_Done,
26747      // Label 1358: @70698
26748      GIM_Try, /*On fail goto*//*Label 1359*/ 70779, // Rule ID 3667 //
26749        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
26750        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26751        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26752        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26753        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26754        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26755        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
26756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26759        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26760        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
26761        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
26762        // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
26763        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru32,
26764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
26766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
26767        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26768        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26769        GIR_EraseFromParent, /*InsnID*/0,
26770        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26771        // GIR_Coverage, 3667,
26772        GIR_Done,
26773      // Label 1359: @70779
26774      GIM_Try, /*On fail goto*//*Label 1360*/ 70898, // Rule ID 2557 //
26775        GIM_CheckFeatures, GIFBS_HasNEON,
26776        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx3,
26777        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
26778        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
26779        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26780        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26781        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
26782        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
26783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26784        // (intrinsic_wo_chain:{ *:[v8i8] } 1776:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
26785        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
26786        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
26787        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26788        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
26789        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26790        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
26791        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
26792        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
26793        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
26794        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
26795        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
26796        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
26797        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
26798        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
26799        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
26800        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26801        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX3Pseudo,
26802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
26804        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
26806        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26807        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26808        GIR_EraseFromParent, /*InsnID*/0,
26809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26810        // GIR_Coverage, 2557,
26811        GIR_Done,
26812      // Label 1360: @70898
26813      GIM_Try, /*On fail goto*//*Label 1361*/ 71001, // Rule ID 2558 //
26814        GIM_CheckFeatures, GIFBS_HasNEON,
26815        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl4,
26816        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
26817        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
26818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26819        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26820        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
26821        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
26822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26823        // (intrinsic_wo_chain:{ *:[v8i8] } 1773:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
26824        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
26825        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
26826        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
26827        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
26828        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
26829        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
26830        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
26831        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
26832        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
26833        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
26834        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
26835        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26836        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL4Pseudo,
26837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26838        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
26840        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26841        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26842        GIR_EraseFromParent, /*InsnID*/0,
26843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26844        // GIR_Coverage, 2558,
26845        GIR_Done,
26846      // Label 1361: @71001
26847      GIM_Reject,
26848    // Label 1311: @71002
26849    GIM_Try, /*On fail goto*//*Label 1362*/ 73909,
26850      GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
26851      GIM_Try, /*On fail goto*//*Label 1363*/ 71098, // Rule ID 2829 //
26852        GIM_CheckFeatures, GIFBS_HasMVEInt,
26853        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26854        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26855        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26856        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26857        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26858        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26859        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
26860        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
26861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
26862        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
26863        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
26864        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26865        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
26867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
26868        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
26869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs8,
26870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
26871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
26872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
26873        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26874        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26875        GIR_EraseFromParent, /*InsnID*/0,
26876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26877        // GIR_Coverage, 2829,
26878        GIR_Done,
26879      // Label 1363: @71098
26880      GIM_Try, /*On fail goto*//*Label 1364*/ 71189, // Rule ID 2833 //
26881        GIM_CheckFeatures, GIFBS_HasMVEInt,
26882        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26883        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26884        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26885        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26886        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26887        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26888        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
26889        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
26890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
26891        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
26892        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
26893        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26894        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
26896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
26897        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
26898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs8,
26899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
26900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
26901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
26902        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26903        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26904        GIR_EraseFromParent, /*InsnID*/0,
26905        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26906        // GIR_Coverage, 2833,
26907        GIR_Done,
26908      // Label 1364: @71189
26909      GIM_Try, /*On fail goto*//*Label 1365*/ 71280, // Rule ID 2837 //
26910        GIM_CheckFeatures, GIFBS_HasMVEInt,
26911        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26912        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26913        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26914        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26915        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26916        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26917        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
26918        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
26919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
26920        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
26921        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
26922        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26923        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
26925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
26926        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
26927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu8,
26928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
26929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
26930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
26931        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26932        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26933        GIR_EraseFromParent, /*InsnID*/0,
26934        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26935        // GIR_Coverage, 2837,
26936        GIR_Done,
26937      // Label 1365: @71280
26938      GIM_Try, /*On fail goto*//*Label 1366*/ 71371, // Rule ID 2841 //
26939        GIM_CheckFeatures, GIFBS_HasMVEInt,
26940        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26941        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26942        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26943        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26944        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26945        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26946        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
26947        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
26948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
26949        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
26950        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
26951        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26952        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
26954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
26955        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
26956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs16,
26957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
26958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
26959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
26960        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26961        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26962        GIR_EraseFromParent, /*InsnID*/0,
26963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26964        // GIR_Coverage, 2841,
26965        GIR_Done,
26966      // Label 1366: @71371
26967      GIM_Try, /*On fail goto*//*Label 1367*/ 71462, // Rule ID 2845 //
26968        GIM_CheckFeatures, GIFBS_HasMVEInt,
26969        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26970        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26971        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26972        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26973        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26974        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
26975        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
26976        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
26977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
26978        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
26979        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
26980        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26981        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
26982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
26983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
26984        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
26985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs16,
26986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
26987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
26988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
26989        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26990        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
26991        GIR_EraseFromParent, /*InsnID*/0,
26992        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26993        // GIR_Coverage, 2845,
26994        GIR_Done,
26995      // Label 1367: @71462
26996      GIM_Try, /*On fail goto*//*Label 1368*/ 71553, // Rule ID 2849 //
26997        GIM_CheckFeatures, GIFBS_HasMVEInt,
26998        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
26999        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27000        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27001        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27002        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27003        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27004        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27005        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27007        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
27008        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27009        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27010        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27013        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu16,
27015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27018        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27019        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27020        GIR_EraseFromParent, /*InsnID*/0,
27021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27022        // GIR_Coverage, 2849,
27023        GIR_Done,
27024      // Label 1368: @71553
27025      GIM_Try, /*On fail goto*//*Label 1369*/ 71644, // Rule ID 2853 //
27026        GIM_CheckFeatures, GIFBS_HasMVEInt,
27027        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27028        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27029        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27030        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27031        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27032        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27033        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27034        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27036        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27037        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27038        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27039        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27042        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27043        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs32,
27044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27047        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27048        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27049        GIR_EraseFromParent, /*InsnID*/0,
27050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27051        // GIR_Coverage, 2853,
27052        GIR_Done,
27053      // Label 1369: @71644
27054      GIM_Try, /*On fail goto*//*Label 1370*/ 71735, // Rule ID 2857 //
27055        GIM_CheckFeatures, GIFBS_HasMVEInt,
27056        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27057        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27058        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27059        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27060        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27061        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27062        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27063        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27065        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27066        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27067        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27068        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27071        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs32,
27073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27076        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27077        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27078        GIR_EraseFromParent, /*InsnID*/0,
27079        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27080        // GIR_Coverage, 2857,
27081        GIR_Done,
27082      // Label 1370: @71735
27083      GIM_Try, /*On fail goto*//*Label 1371*/ 71826, // Rule ID 2861 //
27084        GIM_CheckFeatures, GIFBS_HasMVEInt,
27085        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27086        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27087        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27088        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27089        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27090        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27091        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27092        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27094        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
27095        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27096        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27097        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27100        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27101        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu32,
27102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27105        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27106        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27107        GIR_EraseFromParent, /*InsnID*/0,
27108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27109        // GIR_Coverage, 2861,
27110        GIR_Done,
27111      // Label 1371: @71826
27112      GIM_Try, /*On fail goto*//*Label 1372*/ 71917, // Rule ID 2865 //
27113        GIM_CheckFeatures, GIFBS_HasMVEInt,
27114        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27115        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27116        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27117        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27118        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27119        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27120        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27121        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27123        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27124        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27125        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27126        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27129        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs8,
27131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27134        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27135        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27136        GIR_EraseFromParent, /*InsnID*/0,
27137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27138        // GIR_Coverage, 2865,
27139        GIR_Done,
27140      // Label 1372: @71917
27141      GIM_Try, /*On fail goto*//*Label 1373*/ 72008, // Rule ID 2869 //
27142        GIM_CheckFeatures, GIFBS_HasMVEInt,
27143        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27144        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27145        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27146        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27147        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27148        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27149        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27150        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27152        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27153        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27154        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27155        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27158        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs8,
27160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27163        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27164        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27165        GIR_EraseFromParent, /*InsnID*/0,
27166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27167        // GIR_Coverage, 2869,
27168        GIR_Done,
27169      // Label 1373: @72008
27170      GIM_Try, /*On fail goto*//*Label 1374*/ 72099, // Rule ID 2873 //
27171        GIM_CheckFeatures, GIFBS_HasMVEInt,
27172        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27173        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27174        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27175        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27176        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27177        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27178        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27179        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27181        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27182        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27183        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27184        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27187        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs16,
27189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27192        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27193        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27194        GIR_EraseFromParent, /*InsnID*/0,
27195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27196        // GIR_Coverage, 2873,
27197        GIR_Done,
27198      // Label 1374: @72099
27199      GIM_Try, /*On fail goto*//*Label 1375*/ 72190, // Rule ID 2877 //
27200        GIM_CheckFeatures, GIFBS_HasMVEInt,
27201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27205        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27206        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27207        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27208        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27210        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27211        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27212        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27213        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27216        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27217        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs16,
27218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27221        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27222        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27223        GIR_EraseFromParent, /*InsnID*/0,
27224        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27225        // GIR_Coverage, 2877,
27226        GIR_Done,
27227      // Label 1375: @72190
27228      GIM_Try, /*On fail goto*//*Label 1376*/ 72281, // Rule ID 2881 //
27229        GIM_CheckFeatures, GIFBS_HasMVEInt,
27230        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27231        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27232        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27233        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27234        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27235        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27236        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27237        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27239        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27240        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27241        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27242        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27245        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27246        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs32,
27247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27250        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27251        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27252        GIR_EraseFromParent, /*InsnID*/0,
27253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27254        // GIR_Coverage, 2881,
27255        GIR_Done,
27256      // Label 1376: @72281
27257      GIM_Try, /*On fail goto*//*Label 1377*/ 72372, // Rule ID 2885 //
27258        GIM_CheckFeatures, GIFBS_HasMVEInt,
27259        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27260        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27261        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27262        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27263        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27264        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27265        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27266        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27268        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27269        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27270        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27271        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27274        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs32,
27276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27279        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27280        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27281        GIR_EraseFromParent, /*InsnID*/0,
27282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27283        // GIR_Coverage, 2885,
27284        GIR_Done,
27285      // Label 1377: @72372
27286      GIM_Try, /*On fail goto*//*Label 1378*/ 72467, // Rule ID 2831 //
27287        GIM_CheckFeatures, GIFBS_HasMVEInt,
27288        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27289        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27290        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27291        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27292        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27293        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27294        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27295        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27297        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27298        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27299        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27303        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27304        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas8,
27305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27309        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27310        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27311        GIR_EraseFromParent, /*InsnID*/0,
27312        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27313        // GIR_Coverage, 2831,
27314        GIR_Done,
27315      // Label 1378: @72467
27316      GIM_Try, /*On fail goto*//*Label 1379*/ 72562, // Rule ID 2835 //
27317        GIM_CheckFeatures, GIFBS_HasMVEInt,
27318        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27319        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27320        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27321        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27322        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27323        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27324        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27325        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27327        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27328        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27329        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27333        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27334        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs8,
27335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27339        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27340        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27341        GIR_EraseFromParent, /*InsnID*/0,
27342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27343        // GIR_Coverage, 2835,
27344        GIR_Done,
27345      // Label 1379: @72562
27346      GIM_Try, /*On fail goto*//*Label 1380*/ 72657, // Rule ID 2839 //
27347        GIM_CheckFeatures, GIFBS_HasMVEInt,
27348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27351        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27352        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27353        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27354        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27355        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27357        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
27358        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27359        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27362        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27363        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27364        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau8,
27365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27369        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27370        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27371        GIR_EraseFromParent, /*InsnID*/0,
27372        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27373        // GIR_Coverage, 2839,
27374        GIR_Done,
27375      // Label 1380: @72657
27376      GIM_Try, /*On fail goto*//*Label 1381*/ 72752, // Rule ID 2843 //
27377        GIM_CheckFeatures, GIFBS_HasMVEInt,
27378        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27379        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27380        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27381        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27382        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27383        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27384        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27385        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27387        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27388        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27389        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27393        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas16,
27395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27399        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27400        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27401        GIR_EraseFromParent, /*InsnID*/0,
27402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27403        // GIR_Coverage, 2843,
27404        GIR_Done,
27405      // Label 1381: @72752
27406      GIM_Try, /*On fail goto*//*Label 1382*/ 72847, // Rule ID 2847 //
27407        GIM_CheckFeatures, GIFBS_HasMVEInt,
27408        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27409        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27410        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27411        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27412        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27413        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27414        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27415        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27417        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27418        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27419        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27423        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs16,
27425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27429        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27430        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27431        GIR_EraseFromParent, /*InsnID*/0,
27432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27433        // GIR_Coverage, 2847,
27434        GIR_Done,
27435      // Label 1382: @72847
27436      GIM_Try, /*On fail goto*//*Label 1383*/ 72942, // Rule ID 2851 //
27437        GIM_CheckFeatures, GIFBS_HasMVEInt,
27438        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27439        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27440        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27441        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27442        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27443        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27444        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27445        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27447        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
27448        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27449        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27453        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27454        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau16,
27455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27459        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27460        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27461        GIR_EraseFromParent, /*InsnID*/0,
27462        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27463        // GIR_Coverage, 2851,
27464        GIR_Done,
27465      // Label 1383: @72942
27466      GIM_Try, /*On fail goto*//*Label 1384*/ 73037, // Rule ID 2855 //
27467        GIM_CheckFeatures, GIFBS_HasMVEInt,
27468        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27469        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27470        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27471        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27472        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27473        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27474        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27475        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27477        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27478        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27479        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27483        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27484        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas32,
27485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27489        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27490        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27491        GIR_EraseFromParent, /*InsnID*/0,
27492        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27493        // GIR_Coverage, 2855,
27494        GIR_Done,
27495      // Label 1384: @73037
27496      GIM_Try, /*On fail goto*//*Label 1385*/ 73132, // Rule ID 2859 //
27497        GIM_CheckFeatures, GIFBS_HasMVEInt,
27498        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27499        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27500        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27501        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27502        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27503        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27504        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27505        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27507        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27508        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27509        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27513        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs32,
27515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27519        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27520        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27521        GIR_EraseFromParent, /*InsnID*/0,
27522        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27523        // GIR_Coverage, 2859,
27524        GIR_Done,
27525      // Label 1385: @73132
27526      GIM_Try, /*On fail goto*//*Label 1386*/ 73227, // Rule ID 2863 //
27527        GIM_CheckFeatures, GIFBS_HasMVEInt,
27528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27529        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27530        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27531        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27532        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27533        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27534        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27535        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27537        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
27538        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
27539        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27543        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27544        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau32,
27545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27549        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27550        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27551        GIR_EraseFromParent, /*InsnID*/0,
27552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27553        // GIR_Coverage, 2863,
27554        GIR_Done,
27555      // Label 1386: @73227
27556      GIM_Try, /*On fail goto*//*Label 1387*/ 73322, // Rule ID 2867 //
27557        GIM_CheckFeatures, GIFBS_HasMVEInt,
27558        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27559        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27560        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27561        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27562        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27563        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27564        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27565        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27567        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27568        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27569        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27573        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27574        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas8,
27575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27579        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27580        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27581        GIR_EraseFromParent, /*InsnID*/0,
27582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27583        // GIR_Coverage, 2867,
27584        GIR_Done,
27585      // Label 1387: @73322
27586      GIM_Try, /*On fail goto*//*Label 1388*/ 73417, // Rule ID 2871 //
27587        GIM_CheckFeatures, GIFBS_HasMVEInt,
27588        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27589        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27590        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27591        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27592        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27593        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27594        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
27595        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
27596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27597        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27598        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27599        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27603        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
27604        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs8,
27605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27609        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27610        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27611        GIR_EraseFromParent, /*InsnID*/0,
27612        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27613        // GIR_Coverage, 2871,
27614        GIR_Done,
27615      // Label 1388: @73417
27616      GIM_Try, /*On fail goto*//*Label 1389*/ 73512, // Rule ID 2875 //
27617        GIM_CheckFeatures, GIFBS_HasMVEInt,
27618        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27619        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27620        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27621        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27622        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27623        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27624        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27625        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27627        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27628        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27629        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27633        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas16,
27635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27639        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27640        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27641        GIR_EraseFromParent, /*InsnID*/0,
27642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27643        // GIR_Coverage, 2875,
27644        GIR_Done,
27645      // Label 1389: @73512
27646      GIM_Try, /*On fail goto*//*Label 1390*/ 73607, // Rule ID 2879 //
27647        GIM_CheckFeatures, GIFBS_HasMVEInt,
27648        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27649        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27650        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27651        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27652        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27653        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27654        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
27655        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
27656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27657        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27658        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27659        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27663        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
27664        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs16,
27665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27669        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27670        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27671        GIR_EraseFromParent, /*InsnID*/0,
27672        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27673        // GIR_Coverage, 2879,
27674        GIR_Done,
27675      // Label 1390: @73607
27676      GIM_Try, /*On fail goto*//*Label 1391*/ 73702, // Rule ID 2883 //
27677        GIM_CheckFeatures, GIFBS_HasMVEInt,
27678        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27679        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27680        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27681        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27682        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27683        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27684        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27685        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27687        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27688        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27689        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27693        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas32,
27695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27699        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27700        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27701        GIR_EraseFromParent, /*InsnID*/0,
27702        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27703        // GIR_Coverage, 2883,
27704        GIR_Done,
27705      // Label 1391: @73702
27706      GIM_Try, /*On fail goto*//*Label 1392*/ 73797, // Rule ID 2887 //
27707        GIM_CheckFeatures, GIFBS_HasMVEInt,
27708        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
27709        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27710        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27711        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27712        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27713        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27714        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
27715        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
27716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
27717        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
27718        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
27719        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
27721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
27722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
27723        // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
27724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs32,
27725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
27726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
27727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
27728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
27729        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27730        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27731        GIR_EraseFromParent, /*InsnID*/0,
27732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27733        // GIR_Coverage, 2887,
27734        GIR_Done,
27735      // Label 1392: @73797
27736      GIM_Try, /*On fail goto*//*Label 1393*/ 73908, // Rule ID 2559 //
27737        GIM_CheckFeatures, GIFBS_HasNEON,
27738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx4,
27739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
27740        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
27741        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27742        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27743        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
27744        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
27745        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s8,
27746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27747        // (intrinsic_wo_chain:{ *:[v8i8] } 1777:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
27748        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
27749        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
27750        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
27751        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
27752        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
27753        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
27754        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
27755        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
27756        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
27757        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
27758        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
27759        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX4Pseudo,
27761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
27763        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Vm
27765        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27766        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27767        GIR_EraseFromParent, /*InsnID*/0,
27768        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27769        // GIR_Coverage, 2559,
27770        GIR_Done,
27771      // Label 1393: @73908
27772      GIM_Reject,
27773    // Label 1362: @73909
27774    GIM_Try, /*On fail goto*//*Label 1394*/ 78399,
27775      GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
27776      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshrn,
27777      GIM_Try, /*On fail goto*//*Label 1395*/ 74030, // Rule ID 3168 //
27778        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27779        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27780        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27781        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27782        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27783        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27784        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27785        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27786        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27790        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27791        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27792        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
27793        // MIs[1] Operand 1
27794        // No operand predicates
27795        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27796        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27797        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
27798        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
27799        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
27800        GIM_CheckIsSafeToFold, /*InsnID*/1,
27801        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
27802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
27803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27806        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27807        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27808        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27809        GIR_EraseFromParent, /*InsnID*/0,
27810        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27811        // GIR_Coverage, 3168,
27812        GIR_Done,
27813      // Label 1395: @74030
27814      GIM_Try, /*On fail goto*//*Label 1396*/ 74142, // Rule ID 3170 //
27815        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27816        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27817        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27818        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27819        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27820        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27821        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27822        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27823        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27827        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27828        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27829        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
27830        // MIs[1] Operand 1
27831        // No operand predicates
27832        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27833        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27834        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
27835        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
27836        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
27837        GIM_CheckIsSafeToFold, /*InsnID*/1,
27838        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
27839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
27840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27843        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27844        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27845        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27846        GIR_EraseFromParent, /*InsnID*/0,
27847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27848        // GIR_Coverage, 3170,
27849        GIR_Done,
27850      // Label 1396: @74142
27851      GIM_Try, /*On fail goto*//*Label 1397*/ 74254, // Rule ID 3172 //
27852        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27853        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27854        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27855        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27856        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27857        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27858        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27859        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27860        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27864        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27865        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27866        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
27867        // MIs[1] Operand 1
27868        // No operand predicates
27869        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27870        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27871        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
27872        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
27873        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
27874        GIM_CheckIsSafeToFold, /*InsnID*/1,
27875        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
27876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
27877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27880        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27881        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27882        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27883        GIR_EraseFromParent, /*InsnID*/0,
27884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27885        // GIR_Coverage, 3172,
27886        GIR_Done,
27887      // Label 1397: @74254
27888      GIM_Try, /*On fail goto*//*Label 1398*/ 74366, // Rule ID 3174 //
27889        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27890        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27891        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27892        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27893        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27894        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27895        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27896        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27897        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27901        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27902        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27903        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
27904        // MIs[1] Operand 1
27905        // No operand predicates
27906        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27907        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27908        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
27909        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
27910        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
27911        GIM_CheckIsSafeToFold, /*InsnID*/1,
27912        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
27913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
27914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27917        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27918        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27919        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27920        GIR_EraseFromParent, /*InsnID*/0,
27921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27922        // GIR_Coverage, 3174,
27923        GIR_Done,
27924      // Label 1398: @74366
27925      GIM_Try, /*On fail goto*//*Label 1399*/ 74478, // Rule ID 3176 //
27926        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27927        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27928        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27929        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27930        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27931        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27932        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27933        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27934        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27938        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27939        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27940        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
27941        // MIs[1] Operand 1
27942        // No operand predicates
27943        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27944        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27945        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
27946        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
27947        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
27948        GIM_CheckIsSafeToFold, /*InsnID*/1,
27949        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
27950        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
27951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27954        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27955        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27956        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27957        GIR_EraseFromParent, /*InsnID*/0,
27958        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27959        // GIR_Coverage, 3176,
27960        GIR_Done,
27961      // Label 1399: @74478
27962      GIM_Try, /*On fail goto*//*Label 1400*/ 74590, // Rule ID 3178 //
27963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27966        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27967        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27968        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
27969        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
27970        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
27971        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
27972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27975        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27976        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
27977        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
27978        // MIs[1] Operand 1
27979        // No operand predicates
27980        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27981        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
27982        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
27983        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
27984        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
27985        GIM_CheckIsSafeToFold, /*InsnID*/1,
27986        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
27987        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
27988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
27990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
27991        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27992        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27993        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
27994        GIR_EraseFromParent, /*InsnID*/0,
27995        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27996        // GIR_Coverage, 3178,
27997        GIR_Done,
27998      // Label 1400: @74590
27999      GIM_Try, /*On fail goto*//*Label 1401*/ 74702, // Rule ID 3180 //
28000        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28001        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28002        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28003        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28004        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28005        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28006        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28007        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28008        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28012        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28013        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28014        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28015        // MIs[1] Operand 1
28016        // No operand predicates
28017        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28018        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28019        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28020        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28021        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28022        GIM_CheckIsSafeToFold, /*InsnID*/1,
28023        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
28025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28028        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28029        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28030        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28031        GIR_EraseFromParent, /*InsnID*/0,
28032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28033        // GIR_Coverage, 3180,
28034        GIR_Done,
28035      // Label 1401: @74702
28036      GIM_Try, /*On fail goto*//*Label 1402*/ 74814, // Rule ID 3182 //
28037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28039        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28040        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28041        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28042        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28043        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28044        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28045        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28049        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28050        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28051        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28052        // MIs[1] Operand 1
28053        // No operand predicates
28054        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28055        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28056        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28057        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28058        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28059        GIM_CheckIsSafeToFold, /*InsnID*/1,
28060        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
28062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28065        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28066        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28067        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28068        GIR_EraseFromParent, /*InsnID*/0,
28069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28070        // GIR_Coverage, 3182,
28071        GIR_Done,
28072      // Label 1402: @74814
28073      GIM_Try, /*On fail goto*//*Label 1403*/ 74926, // Rule ID 3184 //
28074        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28075        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28076        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28077        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28078        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28079        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28080        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28081        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28082        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28086        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28087        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28088        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28089        // MIs[1] Operand 1
28090        // No operand predicates
28091        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28092        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28093        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28094        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28095        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28096        GIM_CheckIsSafeToFold, /*InsnID*/1,
28097        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28098        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
28099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28102        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28103        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28104        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28105        GIR_EraseFromParent, /*InsnID*/0,
28106        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28107        // GIR_Coverage, 3184,
28108        GIR_Done,
28109      // Label 1403: @74926
28110      GIM_Try, /*On fail goto*//*Label 1404*/ 75038, // Rule ID 3186 //
28111        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28112        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28113        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28114        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28115        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28116        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28117        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28118        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28119        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28123        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28124        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28125        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28126        // MIs[1] Operand 1
28127        // No operand predicates
28128        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28129        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28130        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28131        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28132        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28133        GIM_CheckIsSafeToFold, /*InsnID*/1,
28134        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
28136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28139        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28140        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28141        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28142        GIR_EraseFromParent, /*InsnID*/0,
28143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28144        // GIR_Coverage, 3186,
28145        GIR_Done,
28146      // Label 1404: @75038
28147      GIM_Try, /*On fail goto*//*Label 1405*/ 75150, // Rule ID 3188 //
28148        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28149        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28150        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28151        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28152        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28153        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28154        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28155        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28156        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28160        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28161        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28162        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28163        // MIs[1] Operand 1
28164        // No operand predicates
28165        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28166        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28167        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28168        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28169        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28170        GIM_CheckIsSafeToFold, /*InsnID*/1,
28171        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28172        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
28173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28176        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28177        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28178        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28179        GIR_EraseFromParent, /*InsnID*/0,
28180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28181        // GIR_Coverage, 3188,
28182        GIR_Done,
28183      // Label 1405: @75150
28184      GIM_Try, /*On fail goto*//*Label 1406*/ 75262, // Rule ID 3190 //
28185        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28186        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28187        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28188        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28189        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28190        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28191        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28192        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28193        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28197        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28198        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28199        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28200        // MIs[1] Operand 1
28201        // No operand predicates
28202        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28203        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28204        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28205        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28206        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28207        GIM_CheckIsSafeToFold, /*InsnID*/1,
28208        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
28210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28213        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28214        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28215        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28216        GIR_EraseFromParent, /*InsnID*/0,
28217        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28218        // GIR_Coverage, 3190,
28219        GIR_Done,
28220      // Label 1406: @75262
28221      GIM_Try, /*On fail goto*//*Label 1407*/ 75374, // Rule ID 3192 //
28222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28225        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28226        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28227        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28228        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28229        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28230        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28234        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28235        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28236        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28237        // MIs[1] Operand 1
28238        // No operand predicates
28239        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28240        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28241        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28242        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28243        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28244        GIM_CheckIsSafeToFold, /*InsnID*/1,
28245        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28246        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
28247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28250        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28251        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28252        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28253        GIR_EraseFromParent, /*InsnID*/0,
28254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28255        // GIR_Coverage, 3192,
28256        GIR_Done,
28257      // Label 1407: @75374
28258      GIM_Try, /*On fail goto*//*Label 1408*/ 75486, // Rule ID 3194 //
28259        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28260        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28261        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28262        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28263        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28264        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28265        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28266        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28267        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28271        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28272        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28273        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28274        // MIs[1] Operand 1
28275        // No operand predicates
28276        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28277        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28278        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28279        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28280        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28281        GIM_CheckIsSafeToFold, /*InsnID*/1,
28282        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
28284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28287        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28288        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28289        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28290        GIR_EraseFromParent, /*InsnID*/0,
28291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28292        // GIR_Coverage, 3194,
28293        GIR_Done,
28294      // Label 1408: @75486
28295      GIM_Try, /*On fail goto*//*Label 1409*/ 75598, // Rule ID 3196 //
28296        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28297        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28298        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28299        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28300        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28301        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28302        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28303        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28304        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28308        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28309        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28310        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28311        // MIs[1] Operand 1
28312        // No operand predicates
28313        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28314        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28315        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28316        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28317        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28318        GIM_CheckIsSafeToFold, /*InsnID*/1,
28319        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
28321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28324        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28325        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28326        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28327        GIR_EraseFromParent, /*InsnID*/0,
28328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28329        // GIR_Coverage, 3196,
28330        GIR_Done,
28331      // Label 1409: @75598
28332      GIM_Try, /*On fail goto*//*Label 1410*/ 75710, // Rule ID 3198 //
28333        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28334        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28335        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28336        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28337        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28338        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28339        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28340        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28341        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28345        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28346        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28347        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28348        // MIs[1] Operand 1
28349        // No operand predicates
28350        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28351        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28352        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28353        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28354        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28355        GIM_CheckIsSafeToFold, /*InsnID*/1,
28356        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28357        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
28358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28361        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28362        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28363        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28364        GIR_EraseFromParent, /*InsnID*/0,
28365        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28366        // GIR_Coverage, 3198,
28367        GIR_Done,
28368      // Label 1410: @75710
28369      GIM_Try, /*On fail goto*//*Label 1411*/ 75822, // Rule ID 3200 //
28370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28373        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28374        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28375        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28376        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28377        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28378        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28382        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28383        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28384        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28385        // MIs[1] Operand 1
28386        // No operand predicates
28387        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28388        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28389        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28390        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28391        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28392        GIM_CheckIsSafeToFold, /*InsnID*/1,
28393        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs16,
28395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28398        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28399        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28400        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28401        GIR_EraseFromParent, /*InsnID*/0,
28402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28403        // GIR_Coverage, 3200,
28404        GIR_Done,
28405      // Label 1411: @75822
28406      GIM_Try, /*On fail goto*//*Label 1412*/ 75934, // Rule ID 3202 //
28407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28409        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28410        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28411        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28412        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28413        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28414        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28415        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28419        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28420        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28421        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28422        // MIs[1] Operand 1
28423        // No operand predicates
28424        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28425        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28426        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28427        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28428        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28429        GIM_CheckIsSafeToFold, /*InsnID*/1,
28430        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28431        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths16,
28432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28435        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28436        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28437        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28438        GIR_EraseFromParent, /*InsnID*/0,
28439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28440        // GIR_Coverage, 3202,
28441        GIR_Done,
28442      // Label 1412: @75934
28443      GIM_Try, /*On fail goto*//*Label 1413*/ 76046, // Rule ID 3204 //
28444        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28445        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28446        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28447        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28448        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28449        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28450        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28451        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28452        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28456        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28457        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28458        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28459        // MIs[1] Operand 1
28460        // No operand predicates
28461        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28462        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28463        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28464        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28465        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28466        GIM_CheckIsSafeToFold, /*InsnID*/1,
28467        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs32,
28469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28472        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28473        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28474        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28475        GIR_EraseFromParent, /*InsnID*/0,
28476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28477        // GIR_Coverage, 3204,
28478        GIR_Done,
28479      // Label 1413: @76046
28480      GIM_Try, /*On fail goto*//*Label 1414*/ 76158, // Rule ID 3206 //
28481        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28482        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28483        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28484        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28485        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28486        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28487        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28488        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28489        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28493        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28494        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28495        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28496        // MIs[1] Operand 1
28497        // No operand predicates
28498        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28499        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28500        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28501        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28502        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28503        GIM_CheckIsSafeToFold, /*InsnID*/1,
28504        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28505        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths32,
28506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28509        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28510        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28511        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28512        GIR_EraseFromParent, /*InsnID*/0,
28513        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28514        // GIR_Coverage, 3206,
28515        GIR_Done,
28516      // Label 1414: @76158
28517      GIM_Try, /*On fail goto*//*Label 1415*/ 76270, // Rule ID 3208 //
28518        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28519        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28520        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28521        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28522        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28523        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28524        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28525        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28526        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28530        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28531        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28532        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28533        // MIs[1] Operand 1
28534        // No operand predicates
28535        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28536        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28537        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28538        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28539        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28540        GIM_CheckIsSafeToFold, /*InsnID*/1,
28541        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu16,
28543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28546        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28547        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28548        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28549        GIR_EraseFromParent, /*InsnID*/0,
28550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28551        // GIR_Coverage, 3208,
28552        GIR_Done,
28553      // Label 1415: @76270
28554      GIM_Try, /*On fail goto*//*Label 1416*/ 76382, // Rule ID 3210 //
28555        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28556        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28557        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28558        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28559        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28560        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28561        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28562        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28563        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28567        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28568        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28569        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28570        // MIs[1] Operand 1
28571        // No operand predicates
28572        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28573        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28574        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28575        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28576        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28577        GIM_CheckIsSafeToFold, /*InsnID*/1,
28578        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu16,
28580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28583        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28584        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28585        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28586        GIR_EraseFromParent, /*InsnID*/0,
28587        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28588        // GIR_Coverage, 3210,
28589        GIR_Done,
28590      // Label 1416: @76382
28591      GIM_Try, /*On fail goto*//*Label 1417*/ 76494, // Rule ID 3212 //
28592        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28593        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28594        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28595        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28596        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28597        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28598        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28599        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28600        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28604        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28605        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28606        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28607        // MIs[1] Operand 1
28608        // No operand predicates
28609        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28610        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28611        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28612        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28613        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28614        GIM_CheckIsSafeToFold, /*InsnID*/1,
28615        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28616        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu32,
28617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28620        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28621        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28622        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28623        GIR_EraseFromParent, /*InsnID*/0,
28624        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28625        // GIR_Coverage, 3212,
28626        GIR_Done,
28627      // Label 1417: @76494
28628      GIM_Try, /*On fail goto*//*Label 1418*/ 76606, // Rule ID 3214 //
28629        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28630        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28631        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28632        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28633        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28634        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28635        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28636        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28637        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28641        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28642        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28643        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28644        // MIs[1] Operand 1
28645        // No operand predicates
28646        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28647        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28648        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28649        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28650        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28651        GIM_CheckIsSafeToFold, /*InsnID*/1,
28652        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28653        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu32,
28654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28657        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28658        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28659        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28660        GIR_EraseFromParent, /*InsnID*/0,
28661        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28662        // GIR_Coverage, 3214,
28663        GIR_Done,
28664      // Label 1418: @76606
28665      GIM_Try, /*On fail goto*//*Label 1419*/ 76718, // Rule ID 3216 //
28666        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28667        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28668        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28669        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28670        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28671        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28672        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28673        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28674        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28678        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28679        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28680        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28681        // MIs[1] Operand 1
28682        // No operand predicates
28683        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28684        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28685        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28686        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28687        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28688        GIM_CheckIsSafeToFold, /*InsnID*/1,
28689        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs16,
28691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28694        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28695        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28696        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28697        GIR_EraseFromParent, /*InsnID*/0,
28698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28699        // GIR_Coverage, 3216,
28700        GIR_Done,
28701      // Label 1419: @76718
28702      GIM_Try, /*On fail goto*//*Label 1420*/ 76830, // Rule ID 3218 //
28703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28706        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28707        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28708        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28709        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28710        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28711        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28715        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28716        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28717        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28718        // MIs[1] Operand 1
28719        // No operand predicates
28720        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28721        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28722        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28723        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28724        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28725        GIM_CheckIsSafeToFold, /*InsnID*/1,
28726        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths16,
28728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28731        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28732        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28733        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28734        GIR_EraseFromParent, /*InsnID*/0,
28735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28736        // GIR_Coverage, 3218,
28737        GIR_Done,
28738      // Label 1420: @76830
28739      GIM_Try, /*On fail goto*//*Label 1421*/ 76942, // Rule ID 3220 //
28740        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28741        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28742        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28743        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28744        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28745        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28746        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28747        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28748        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28752        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28753        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28754        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28755        // MIs[1] Operand 1
28756        // No operand predicates
28757        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28758        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28759        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28760        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28761        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28762        GIM_CheckIsSafeToFold, /*InsnID*/1,
28763        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28764        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs32,
28765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28768        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28769        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28770        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28771        GIR_EraseFromParent, /*InsnID*/0,
28772        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28773        // GIR_Coverage, 3220,
28774        GIR_Done,
28775      // Label 1421: @76942
28776      GIM_Try, /*On fail goto*//*Label 1422*/ 77054, // Rule ID 3222 //
28777        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28778        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28779        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28780        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28781        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28782        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28783        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28784        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28785        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28789        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28790        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28791        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28792        // MIs[1] Operand 1
28793        // No operand predicates
28794        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28795        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28796        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
28797        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28798        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28799        GIM_CheckIsSafeToFold, /*InsnID*/1,
28800        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28801        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths32,
28802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28805        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28806        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28807        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28808        GIR_EraseFromParent, /*InsnID*/0,
28809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28810        // GIR_Coverage, 3222,
28811        GIR_Done,
28812      // Label 1422: @77054
28813      GIM_Try, /*On fail goto*//*Label 1423*/ 77166, // Rule ID 3224 //
28814        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28815        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28816        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28817        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28818        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28819        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28820        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28821        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28822        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28826        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28827        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28828        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28829        // MIs[1] Operand 1
28830        // No operand predicates
28831        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28832        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28833        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28834        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28835        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28836        GIM_CheckIsSafeToFold, /*InsnID*/1,
28837        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu16,
28839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28842        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28843        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28844        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28845        GIR_EraseFromParent, /*InsnID*/0,
28846        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28847        // GIR_Coverage, 3224,
28848        GIR_Done,
28849      // Label 1423: @77166
28850      GIM_Try, /*On fail goto*//*Label 1424*/ 77278, // Rule ID 3226 //
28851        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28852        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28853        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28854        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28855        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28856        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28857        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28858        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28859        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28863        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28864        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28865        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28866        // MIs[1] Operand 1
28867        // No operand predicates
28868        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28869        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28870        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28871        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28872        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28873        GIM_CheckIsSafeToFold, /*InsnID*/1,
28874        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28875        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu16,
28876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28879        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28880        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28881        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28882        GIR_EraseFromParent, /*InsnID*/0,
28883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28884        // GIR_Coverage, 3226,
28885        GIR_Done,
28886      // Label 1424: @77278
28887      GIM_Try, /*On fail goto*//*Label 1425*/ 77390, // Rule ID 3228 //
28888        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28889        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28890        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28891        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28892        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28893        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28894        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28895        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28896        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28900        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28901        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28902        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28903        // MIs[1] Operand 1
28904        // No operand predicates
28905        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28906        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28907        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28908        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28909        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28910        GIM_CheckIsSafeToFold, /*InsnID*/1,
28911        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28912        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu32,
28913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28916        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28917        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28918        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28919        GIR_EraseFromParent, /*InsnID*/0,
28920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28921        // GIR_Coverage, 3228,
28922        GIR_Done,
28923      // Label 1425: @77390
28924      GIM_Try, /*On fail goto*//*Label 1426*/ 77502, // Rule ID 3230 //
28925        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28926        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28927        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28928        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28929        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28930        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28931        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28932        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28933        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28937        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28938        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28939        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
28940        // MIs[1] Operand 1
28941        // No operand predicates
28942        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28943        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
28944        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28945        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
28946        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
28947        GIM_CheckIsSafeToFold, /*InsnID*/1,
28948        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
28949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu32,
28950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28953        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28954        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28955        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28956        GIR_EraseFromParent, /*InsnID*/0,
28957        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28958        // GIR_Coverage, 3230,
28959        GIR_Done,
28960      // Label 1426: @77502
28961      GIM_Try, /*On fail goto*//*Label 1427*/ 77614, // Rule ID 3232 //
28962        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28963        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28964        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28965        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28966        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28967        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28968        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
28969        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
28970        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
28971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28974        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28975        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28976        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
28977        // MIs[1] Operand 1
28978        // No operand predicates
28979        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28980        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28981        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
28982        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
28983        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
28984        GIM_CheckIsSafeToFold, /*InsnID*/1,
28985        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
28986        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16bh,
28987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
28989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
28990        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
28991        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28992        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
28993        GIR_EraseFromParent, /*InsnID*/0,
28994        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28995        // GIR_Coverage, 3232,
28996        GIR_Done,
28997      // Label 1427: @77614
28998      GIM_Try, /*On fail goto*//*Label 1428*/ 77726, // Rule ID 3234 //
28999        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29000        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29001        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29002        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29003        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29004        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29005        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29006        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29007        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29011        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29012        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29013        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
29014        // MIs[1] Operand 1
29015        // No operand predicates
29016        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29017        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29018        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29019        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29020        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
29021        GIM_CheckIsSafeToFold, /*InsnID*/1,
29022        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
29023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16th,
29024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29027        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29028        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29029        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29030        GIR_EraseFromParent, /*InsnID*/0,
29031        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29032        // GIR_Coverage, 3234,
29033        GIR_Done,
29034      // Label 1428: @77726
29035      GIM_Try, /*On fail goto*//*Label 1429*/ 77838, // Rule ID 3236 //
29036        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29037        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29038        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29039        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29040        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29041        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29042        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29043        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29044        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29048        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29049        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29050        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
29051        // MIs[1] Operand 1
29052        // No operand predicates
29053        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29054        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29055        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29056        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29057        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
29058        GIM_CheckIsSafeToFold, /*InsnID*/1,
29059        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
29060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32bh,
29061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29064        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29065        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29066        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29067        GIR_EraseFromParent, /*InsnID*/0,
29068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29069        // GIR_Coverage, 3236,
29070        GIR_Done,
29071      // Label 1429: @77838
29072      GIM_Try, /*On fail goto*//*Label 1430*/ 77950, // Rule ID 3238 //
29073        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29074        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29075        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29076        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29077        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29078        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29079        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29080        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29081        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29085        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29086        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29087        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
29088        // MIs[1] Operand 1
29089        // No operand predicates
29090        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29091        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29092        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29093        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29094        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
29095        GIM_CheckIsSafeToFold, /*InsnID*/1,
29096        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
29097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32th,
29098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29101        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29102        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29103        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29104        GIR_EraseFromParent, /*InsnID*/0,
29105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29106        // GIR_Coverage, 3238,
29107        GIR_Done,
29108      // Label 1430: @77950
29109      GIM_Try, /*On fail goto*//*Label 1431*/ 78062, // Rule ID 3240 //
29110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29112        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29113        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29114        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29115        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29116        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29117        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29118        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29122        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29123        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29124        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
29125        // MIs[1] Operand 1
29126        // No operand predicates
29127        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29128        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29129        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29130        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29131        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
29132        GIM_CheckIsSafeToFold, /*InsnID*/1,
29133        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
29134        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16bh,
29135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29138        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29139        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29140        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29141        GIR_EraseFromParent, /*InsnID*/0,
29142        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29143        // GIR_Coverage, 3240,
29144        GIR_Done,
29145      // Label 1431: @78062
29146      GIM_Try, /*On fail goto*//*Label 1432*/ 78174, // Rule ID 3242 //
29147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29149        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29150        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29151        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29152        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29153        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29154        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29155        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29159        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29160        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29161        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
29162        // MIs[1] Operand 1
29163        // No operand predicates
29164        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29165        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29166        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29167        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29168        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
29169        GIM_CheckIsSafeToFold, /*InsnID*/1,
29170        // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
29171        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16th,
29172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29175        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29176        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29177        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29178        GIR_EraseFromParent, /*InsnID*/0,
29179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29180        // GIR_Coverage, 3242,
29181        GIR_Done,
29182      // Label 1432: @78174
29183      GIM_Try, /*On fail goto*//*Label 1433*/ 78286, // Rule ID 3244 //
29184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29187        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29188        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29189        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29190        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29191        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29192        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29196        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29197        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29198        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
29199        // MIs[1] Operand 1
29200        // No operand predicates
29201        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29202        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29203        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29204        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29205        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
29206        GIM_CheckIsSafeToFold, /*InsnID*/1,
29207        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
29208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32bh,
29209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29212        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29213        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29214        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29215        GIR_EraseFromParent, /*InsnID*/0,
29216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29217        // GIR_Coverage, 3244,
29218        GIR_Done,
29219      // Label 1433: @78286
29220      GIM_Try, /*On fail goto*//*Label 1434*/ 78398, // Rule ID 3246 //
29221        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29222        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29223        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29224        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29225        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29226        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29227        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
29228        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
29229        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
29230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29233        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
29234        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29235        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
29236        // MIs[1] Operand 1
29237        // No operand predicates
29238        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29239        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29240        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
29241        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
29242        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
29243        GIM_CheckIsSafeToFold, /*InsnID*/1,
29244        // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
29245        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32th,
29246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
29248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29249        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29250        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29251        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29252        GIR_EraseFromParent, /*InsnID*/0,
29253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29254        // GIR_Coverage, 3246,
29255        GIR_Done,
29256      // Label 1434: @78398
29257      GIM_Reject,
29258    // Label 1394: @78399
29259    GIM_Reject,
29260    // Label 13: @78400
29261    GIM_Try, /*On fail goto*//*Label 1435*/ 78449,
29262      GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
29263      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_clrex,
29264      GIM_Try, /*On fail goto*//*Label 1436*/ 78425, // Rule ID 254 //
29265        GIM_CheckFeatures, GIFBS_HasV6K_IsARM,
29266        // (intrinsic_void 1500:{ *:[iPTR] })  =>  (CLREX)
29267        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX,
29268        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29269        GIR_EraseFromParent, /*InsnID*/0,
29270        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29271        // GIR_Coverage, 254,
29272        GIR_Done,
29273      // Label 1436: @78425
29274      GIM_Try, /*On fail goto*//*Label 1437*/ 78448, // Rule ID 589 //
29275        GIM_CheckFeatures, GIFBS_HasV7Clrex_IsThumb,
29276        // (intrinsic_void 1500:{ *:[iPTR] })  =>  (t2CLREX)
29277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX,
29278        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29279        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29280        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29281        GIR_EraseFromParent, /*InsnID*/0,
29282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29283        // GIR_Coverage, 589,
29284        GIR_Done,
29285      // Label 1437: @78448
29286      GIM_Reject,
29287    // Label 1435: @78449
29288    GIM_Try, /*On fail goto*//*Label 1438*/ 79209,
29289      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
29290      GIM_Try, /*On fail goto*//*Label 1439*/ 78482, // Rule ID 352 //
29291        GIM_CheckFeatures, GIFBS_IsThumb_IsWindows,
29292        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
29293        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29294        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 249,
29295        // (intrinsic_void 1846:{ *:[iPTR] }, 249:{ *:[i32] })  =>  (t__brkdiv0)
29296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0,
29297        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29298        GIR_EraseFromParent, /*InsnID*/0,
29299        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29300        // GIR_Coverage, 352,
29301        GIR_Done,
29302      // Label 1439: @78482
29303      GIM_Try, /*On fail goto*//*Label 1440*/ 78529, // Rule ID 2 //
29304        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
29305        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
29306        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29307        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29308        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29309        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
29310        // MIs[1] Operand 1
29311        // No operand predicates
29312        GIM_CheckIsSafeToFold, /*InsnID*/1,
29313        // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
29314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT,
29315        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29316        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29317        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29318        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29319        GIR_EraseFromParent, /*InsnID*/0,
29320        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29321        // GIR_Coverage, 2,
29322        GIR_Done,
29323      // Label 1440: @78529
29324      GIM_Try, /*On fail goto*//*Label 1441*/ 78576, // Rule ID 10 //
29325        GIM_CheckFeatures, GIFBS_HasV7_IsARM,
29326        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
29327        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29328        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29329        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29330        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29331        // MIs[1] Operand 1
29332        // No operand predicates
29333        GIM_CheckIsSafeToFold, /*InsnID*/1,
29334        // (intrinsic_void 1513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DBG (imm:{ *:[i32] }):$opt)
29335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG,
29336        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29337        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29338        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29339        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29340        GIR_EraseFromParent, /*InsnID*/0,
29341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29342        // GIR_Coverage, 10,
29343        GIR_Done,
29344      // Label 1441: @78576
29345      GIM_Try, /*On fail goto*//*Label 1442*/ 78616, // Rule ID 11 //
29346        GIM_CheckFeatures, GIFBS_IsARM,
29347        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
29348        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29349        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29350        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29351        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
29352        // MIs[1] Operand 1
29353        // No operand predicates
29354        GIM_CheckIsSafeToFold, /*InsnID*/1,
29355        // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (UDF (imm:{ *:[i32] }):$imm16)
29356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF,
29357        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
29358        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29359        GIR_EraseFromParent, /*InsnID*/0,
29360        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29361        // GIR_Coverage, 11,
29362        GIR_Done,
29363      // Label 1442: @78616
29364      GIM_Try, /*On fail goto*//*Label 1443*/ 78656, // Rule ID 237 //
29365        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
29366        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
29367        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29368        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29369        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29370        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29371        // MIs[1] Operand 1
29372        // No operand predicates
29373        GIM_CheckIsSafeToFold, /*InsnID*/1,
29374        // (intrinsic_void 1514:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DMB (imm:{ *:[i32] }):$opt)
29375        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB,
29376        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29377        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29378        GIR_EraseFromParent, /*InsnID*/0,
29379        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29380        // GIR_Coverage, 237,
29381        GIR_Done,
29382      // Label 1443: @78656
29383      GIM_Try, /*On fail goto*//*Label 1444*/ 78696, // Rule ID 238 //
29384        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
29385        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
29386        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29387        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29388        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29389        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29390        // MIs[1] Operand 1
29391        // No operand predicates
29392        GIM_CheckIsSafeToFold, /*InsnID*/1,
29393        // (intrinsic_void 1515:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DSB (imm:{ *:[i32] }):$opt)
29394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB,
29395        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29396        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29397        GIR_EraseFromParent, /*InsnID*/0,
29398        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29399        // GIR_Coverage, 238,
29400        GIR_Done,
29401      // Label 1444: @78696
29402      GIM_Try, /*On fail goto*//*Label 1445*/ 78736, // Rule ID 239 //
29403        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
29404        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
29405        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29406        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29407        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29408        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29409        // MIs[1] Operand 1
29410        // No operand predicates
29411        GIM_CheckIsSafeToFold, /*InsnID*/1,
29412        // (intrinsic_void 1519:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (ISB (imm:{ *:[i32] }):$opt)
29413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB,
29414        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29415        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29416        GIR_EraseFromParent, /*InsnID*/0,
29417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29418        // GIR_Coverage, 239,
29419        GIR_Done,
29420      // Label 1445: @78736
29421      GIM_Try, /*On fail goto*//*Label 1446*/ 78783, // Rule ID 285 //
29422        GIM_CheckFeatures, GIFBS_HasV6M_IsThumb,
29423        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
29424        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29425        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29426        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29427        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29428        // MIs[1] Operand 1
29429        // No operand predicates
29430        GIM_CheckIsSafeToFold, /*InsnID*/1,
29431        // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (tHINT (imm:{ *:[i32] }):$imm)
29432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT,
29433        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29434        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29435        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29436        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29437        GIR_EraseFromParent, /*InsnID*/0,
29438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29439        // GIR_Coverage, 285,
29440        GIR_Done,
29441      // Label 1446: @78783
29442      GIM_Try, /*On fail goto*//*Label 1447*/ 78823, // Rule ID 351 //
29443        GIM_CheckFeatures, GIFBS_IsThumb,
29444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
29445        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29446        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29447        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29448        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_255,
29449        // MIs[1] Operand 1
29450        // No operand predicates
29451        GIM_CheckIsSafeToFold, /*InsnID*/1,
29452        // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8)  =>  (tUDF (imm:{ *:[i32] }):$imm8)
29453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF,
29454        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
29455        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29456        GIR_EraseFromParent, /*InsnID*/0,
29457        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29458        // GIR_Coverage, 351,
29459        GIR_Done,
29460      // Label 1447: @78823
29461      GIM_Try, /*On fail goto*//*Label 1448*/ 78863, // Rule ID 500 //
29462        GIM_CheckFeatures, GIFBS_IsThumb2,
29463        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
29464        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29465        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29466        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29467        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
29468        // MIs[1] Operand 1
29469        // No operand predicates
29470        GIM_CheckIsSafeToFold, /*InsnID*/1,
29471        // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (t2UDF (imm:{ *:[i32] }):$imm16)
29472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF,
29473        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
29474        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29475        GIR_EraseFromParent, /*InsnID*/0,
29476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29477        // GIR_Coverage, 500,
29478        GIR_Done,
29479      // Label 1448: @78863
29480      GIM_Try, /*On fail goto*//*Label 1449*/ 78910, // Rule ID 574 //
29481        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
29482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
29483        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29484        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29485        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29486        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29487        // MIs[1] Operand 1
29488        // No operand predicates
29489        GIM_CheckIsSafeToFold, /*InsnID*/1,
29490        // (intrinsic_void 1514:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DMB (imm:{ *:[i32] }):$opt)
29491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB,
29492        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29493        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29494        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29495        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29496        GIR_EraseFromParent, /*InsnID*/0,
29497        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29498        // GIR_Coverage, 574,
29499        GIR_Done,
29500      // Label 1449: @78910
29501      GIM_Try, /*On fail goto*//*Label 1450*/ 78957, // Rule ID 575 //
29502        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
29503        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
29504        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29505        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29506        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29507        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29508        // MIs[1] Operand 1
29509        // No operand predicates
29510        GIM_CheckIsSafeToFold, /*InsnID*/1,
29511        // (intrinsic_void 1515:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DSB (imm:{ *:[i32] }):$opt)
29512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB,
29513        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29514        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29515        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29516        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29517        GIR_EraseFromParent, /*InsnID*/0,
29518        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29519        // GIR_Coverage, 575,
29520        GIR_Done,
29521      // Label 1450: @78957
29522      GIM_Try, /*On fail goto*//*Label 1451*/ 79004, // Rule ID 576 //
29523        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
29524        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
29525        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29526        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29527        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29528        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29529        // MIs[1] Operand 1
29530        // No operand predicates
29531        GIM_CheckIsSafeToFold, /*InsnID*/1,
29532        // (intrinsic_void 1519:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2ISB (imm:{ *:[i32] }):$opt)
29533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB,
29534        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29535        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29536        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29537        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29538        GIR_EraseFromParent, /*InsnID*/0,
29539        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29540        // GIR_Coverage, 576,
29541        GIR_Done,
29542      // Label 1451: @79004
29543      GIM_Try, /*On fail goto*//*Label 1452*/ 79051, // Rule ID 594 //
29544        GIM_CheckFeatures, GIFBS_IsThumb2,
29545        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
29546        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29547        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29548        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29549        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
29550        // MIs[1] Operand 1
29551        // No operand predicates
29552        GIM_CheckIsSafeToFold, /*InsnID*/1,
29553        // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (t2HINT (imm:{ *:[i32] }):$imm)
29554        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT,
29555        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
29556        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29557        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29558        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29559        GIR_EraseFromParent, /*InsnID*/0,
29560        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29561        // GIR_Coverage, 594,
29562        GIR_Done,
29563      // Label 1452: @79051
29564      GIM_Try, /*On fail goto*//*Label 1453*/ 79098, // Rule ID 595 //
29565        GIM_CheckFeatures, GIFBS_IsThumb2,
29566        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
29567        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29568        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
29569        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29570        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
29571        // MIs[1] Operand 1
29572        // No operand predicates
29573        GIM_CheckIsSafeToFold, /*InsnID*/1,
29574        // (intrinsic_void 1513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DBG (imm:{ *:[i32] }):$opt)
29575        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG,
29576        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
29577        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29578        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29579        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29580        GIR_EraseFromParent, /*InsnID*/0,
29581        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29582        // GIR_Coverage, 595,
29583        GIR_Done,
29584      // Label 1453: @79098
29585      GIM_Try, /*On fail goto*//*Label 1454*/ 79137, // Rule ID 740 //
29586        GIM_CheckFeatures, GIFBS_HasFPRegs,
29587        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_get_fpscr,
29588        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29590        // (intrinsic_w_chain:{ *:[i32] } 1516:{ *:[iPTR] })  =>  (VMRS:{ *:[i32] })
29591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
29592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
29593        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29594        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29595        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29596        GIR_EraseFromParent, /*InsnID*/0,
29597        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29598        // GIR_Coverage, 740,
29599        GIR_Done,
29600      // Label 1454: @79137
29601      GIM_Try, /*On fail goto*//*Label 1455*/ 79169, // Rule ID 618 //
29602        GIM_CheckFeatures, GIFBS_IsThumb2,
29603        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::set_loop_iterations,
29604        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
29606        // (intrinsic_void 231:{ *:[iPTR] }, rGPR:{ *:[i32] }:$elts)  =>  (t2DoLoopStart rGPR:{ *:[i32] }:$elts)
29607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DoLoopStart,
29608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elts
29609        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29610        GIR_EraseFromParent, /*InsnID*/0,
29611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29612        // GIR_Coverage, 618,
29613        GIR_Done,
29614      // Label 1455: @79169
29615      GIM_Try, /*On fail goto*//*Label 1456*/ 79208, // Rule ID 741 //
29616        GIM_CheckFeatures, GIFBS_HasFPRegs,
29617        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_set_fpscr,
29618        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
29619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
29620        // (intrinsic_void 1790:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt)  =>  (VMSR GPRnopc:{ *:[i32] }:$Rt)
29621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR,
29622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
29623        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29624        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29625        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29626        GIR_EraseFromParent, /*InsnID*/0,
29627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29628        // GIR_Coverage, 741,
29629        GIR_Done,
29630      // Label 1456: @79208
29631      GIM_Reject,
29632    // Label 1438: @79209
29633    GIM_Try, /*On fail goto*//*Label 1457*/ 81374,
29634      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
29635      GIM_Try, /*On fail goto*//*Label 1458*/ 79273, // Rule ID 3836 //
29636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
29637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29638        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29639        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29642        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29643        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29644        // MIs[1] Operand 1
29645        // No operand predicates
29646        GIM_CheckIsSafeToFold, /*InsnID*/1,
29647        // (intrinsic_w_chain:{ *:[v4i32] } 1601:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
29648        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
29649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
29651        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29652        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29653        GIR_EraseFromParent, /*InsnID*/0,
29654        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29655        // GIR_Coverage, 3836,
29656        GIR_Done,
29657      // Label 1458: @79273
29658      GIM_Try, /*On fail goto*//*Label 1459*/ 79332, // Rule ID 3842 //
29659        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
29660        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29661        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29662        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29665        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29666        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29667        // MIs[1] Operand 1
29668        // No operand predicates
29669        GIM_CheckIsSafeToFold, /*InsnID*/1,
29670        // (intrinsic_w_chain:{ *:[v4f32] } 1601:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
29671        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
29672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
29674        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29675        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29676        GIR_EraseFromParent, /*InsnID*/0,
29677        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29678        // GIR_Coverage, 3842,
29679        GIR_Done,
29680      // Label 1459: @79332
29681      GIM_Try, /*On fail goto*//*Label 1460*/ 79391, // Rule ID 3844 //
29682        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
29683        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29684        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
29685        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29688        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29689        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29690        // MIs[1] Operand 1
29691        // No operand predicates
29692        GIM_CheckIsSafeToFold, /*InsnID*/1,
29693        // (intrinsic_w_chain:{ *:[v2i64] } 1601:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
29694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
29695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
29697        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29698        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29699        GIR_EraseFromParent, /*InsnID*/0,
29700        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29701        // GIR_Coverage, 3844,
29702        GIR_Done,
29703      // Label 1460: @79391
29704      GIM_Try, /*On fail goto*//*Label 1461*/ 79450, // Rule ID 3846 //
29705        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
29706        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29707        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
29708        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29711        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29712        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29713        // MIs[1] Operand 1
29714        // No operand predicates
29715        GIM_CheckIsSafeToFold, /*InsnID*/1,
29716        // (intrinsic_w_chain:{ *:[v2f64] } 1601:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
29717        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
29718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
29720        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29721        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29722        GIR_EraseFromParent, /*InsnID*/0,
29723        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29724        // GIR_Coverage, 3846,
29725        GIR_Done,
29726      // Label 1461: @79450
29727      GIM_Try, /*On fail goto*//*Label 1462*/ 79499, // Rule ID 1724 //
29728        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_space,
29729        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29730        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
29732        // MIs[0] size
29733        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
29734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
29735        // (intrinsic_w_chain:{ *:[i32] } 1821:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)  =>  (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
29736        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE,
29737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size
29739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
29740        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29741        GIR_EraseFromParent, /*InsnID*/0,
29742        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29743        // GIR_Coverage, 1724,
29744        GIR_Done,
29745      // Label 1462: @79499
29746      GIM_Try, /*On fail goto*//*Label 1463*/ 79558, // Rule ID 3838 //
29747        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
29748        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
29749        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29750        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29752        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29753        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29754        // MIs[1] Operand 1
29755        // No operand predicates
29756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29757        GIM_CheckIsSafeToFold, /*InsnID*/1,
29758        // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
29759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
29760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
29761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
29762        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29763        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29764        GIR_EraseFromParent, /*InsnID*/0,
29765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29766        // GIR_Coverage, 3838,
29767        GIR_Done,
29768      // Label 1463: @79558
29769      GIM_Try, /*On fail goto*//*Label 1464*/ 79617, // Rule ID 3848 //
29770        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
29771        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
29772        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29773        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29775        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29776        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29777        // MIs[1] Operand 1
29778        // No operand predicates
29779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29780        GIM_CheckIsSafeToFold, /*InsnID*/1,
29781        // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
29782        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
29783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
29784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
29785        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29786        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29787        GIR_EraseFromParent, /*InsnID*/0,
29788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29789        // GIR_Coverage, 3848,
29790        GIR_Done,
29791      // Label 1464: @79617
29792      GIM_Try, /*On fail goto*//*Label 1465*/ 79676, // Rule ID 3852 //
29793        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
29794        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
29795        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29796        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
29797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29798        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29799        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29800        // MIs[1] Operand 1
29801        // No operand predicates
29802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29803        GIM_CheckIsSafeToFold, /*InsnID*/1,
29804        // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
29805        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
29806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
29807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
29808        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29809        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29810        GIR_EraseFromParent, /*InsnID*/0,
29811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29812        // GIR_Coverage, 3852,
29813        GIR_Done,
29814      // Label 1465: @79676
29815      GIM_Try, /*On fail goto*//*Label 1466*/ 79735, // Rule ID 3856 //
29816        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
29817        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
29818        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29819        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
29820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29821        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29822        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29823        // MIs[1] Operand 1
29824        // No operand predicates
29825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29826        GIM_CheckIsSafeToFold, /*InsnID*/1,
29827        // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
29828        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
29829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
29830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
29831        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
29832        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
29833        GIR_EraseFromParent, /*InsnID*/0,
29834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29835        // GIR_Coverage, 3856,
29836        GIR_Done,
29837      // Label 1466: @79735
29838      GIM_Try, /*On fail goto*//*Label 1467*/ 79798, // Rule ID 3 //
29839        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
29840        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
29841        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29842        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29843        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
29845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
29846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
29847        // (intrinsic_w_chain:{ *:[i32] } 1789:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
29848        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL,
29849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29852        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29853        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29854        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29855        GIR_EraseFromParent, /*InsnID*/0,
29856        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29857        // GIR_Coverage, 3,
29858        GIR_Done,
29859      // Label 1467: @79798
29860      GIM_Try, /*On fail goto*//*Label 1468*/ 79861, // Rule ID 123 //
29861        GIM_CheckFeatures, GIFBS_IsARM,
29862        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
29863        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29864        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29865        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29869        // (intrinsic_w_chain:{ *:[i32] } 1788:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29870        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX,
29871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29874        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29875        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29876        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29877        GIR_EraseFromParent, /*InsnID*/0,
29878        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29879        // GIR_Coverage, 123,
29880        GIR_Done,
29881      // Label 1468: @79861
29882      GIM_Try, /*On fail goto*//*Label 1469*/ 79924, // Rule ID 124 //
29883        GIM_CheckFeatures, GIFBS_IsARM,
29884        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
29885        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29886        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29887        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29891        // (intrinsic_w_chain:{ *:[i32] } 1786:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29892        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16,
29893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29896        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29897        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29898        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29899        GIR_EraseFromParent, /*InsnID*/0,
29900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29901        // GIR_Coverage, 124,
29902        GIR_Done,
29903      // Label 1469: @79924
29904      GIM_Try, /*On fail goto*//*Label 1470*/ 79987, // Rule ID 125 //
29905        GIM_CheckFeatures, GIFBS_IsARM,
29906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
29907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29909        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29913        // (intrinsic_w_chain:{ *:[i32] } 1787:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8,
29915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29918        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29919        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29920        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29921        GIR_EraseFromParent, /*InsnID*/0,
29922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29923        // GIR_Coverage, 125,
29924        GIR_Done,
29925      // Label 1470: @79987
29926      GIM_Try, /*On fail goto*//*Label 1471*/ 80050, // Rule ID 126 //
29927        GIM_CheckFeatures, GIFBS_IsARM,
29928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
29929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29931        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29935        // (intrinsic_w_chain:{ *:[i32] } 1824:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29936        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX,
29937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29940        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29941        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29942        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29943        GIR_EraseFromParent, /*InsnID*/0,
29944        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29945        // GIR_Coverage, 126,
29946        GIR_Done,
29947      // Label 1471: @80050
29948      GIM_Try, /*On fail goto*//*Label 1472*/ 80113, // Rule ID 127 //
29949        GIM_CheckFeatures, GIFBS_IsARM,
29950        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
29951        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29952        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29953        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29957        // (intrinsic_w_chain:{ *:[i32] } 1825:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16,
29959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29962        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29963        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29964        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29965        GIR_EraseFromParent, /*InsnID*/0,
29966        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29967        // GIR_Coverage, 127,
29968        GIR_Done,
29969      // Label 1472: @80113
29970      GIM_Try, /*On fail goto*//*Label 1473*/ 80176, // Rule ID 128 //
29971        GIM_CheckFeatures, GIFBS_IsARM,
29972        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
29973        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29974        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29975        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
29978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
29979        // (intrinsic_w_chain:{ *:[i32] } 1826:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
29980        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8,
29981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
29982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
29983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
29984        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29985        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
29986        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
29987        GIR_EraseFromParent, /*InsnID*/0,
29988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29989        // GIR_Coverage, 128,
29990        GIR_Done,
29991      // Label 1473: @80176
29992      GIM_Try, /*On fail goto*//*Label 1474*/ 80239, // Rule ID 129 //
29993        GIM_CheckFeatures, GIFBS_IsARM,
29994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
29995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29997        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
29999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30001        // (intrinsic_w_chain:{ *:[i32] } 1839:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX,
30003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30007        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30008        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30009        GIR_EraseFromParent, /*InsnID*/0,
30010        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30011        // GIR_Coverage, 129,
30012        GIR_Done,
30013      // Label 1474: @80239
30014      GIM_Try, /*On fail goto*//*Label 1475*/ 80302, // Rule ID 130 //
30015        GIM_CheckFeatures, GIFBS_IsARM,
30016        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
30017        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30018        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30019        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
30021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30023        // (intrinsic_w_chain:{ *:[i32] } 1837:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16,
30025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30028        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30029        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30030        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30031        GIR_EraseFromParent, /*InsnID*/0,
30032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30033        // GIR_Coverage, 130,
30034        GIR_Done,
30035      // Label 1475: @80302
30036      GIM_Try, /*On fail goto*//*Label 1476*/ 80365, // Rule ID 131 //
30037        GIM_CheckFeatures, GIFBS_IsARM,
30038        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
30039        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30040        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30041        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
30043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30045        // (intrinsic_w_chain:{ *:[i32] } 1838:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8,
30047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30050        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30051        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30052        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30053        GIR_EraseFromParent, /*InsnID*/0,
30054        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30055        // GIR_Coverage, 131,
30056        GIR_Done,
30057      // Label 1476: @80365
30058      GIM_Try, /*On fail goto*//*Label 1477*/ 80428, // Rule ID 132 //
30059        GIM_CheckFeatures, GIFBS_IsARM,
30060        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
30061        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30062        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30063        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
30065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30067        // (intrinsic_w_chain:{ *:[i32] } 1857:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30068        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX,
30069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30072        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30073        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30074        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30075        GIR_EraseFromParent, /*InsnID*/0,
30076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30077        // GIR_Coverage, 132,
30078        GIR_Done,
30079      // Label 1477: @80428
30080      GIM_Try, /*On fail goto*//*Label 1478*/ 80491, // Rule ID 133 //
30081        GIM_CheckFeatures, GIFBS_IsARM,
30082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
30083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30085        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
30087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30089        // (intrinsic_w_chain:{ *:[i32] } 1858:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16,
30091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30094        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30095        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30096        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30097        GIR_EraseFromParent, /*InsnID*/0,
30098        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30099        // GIR_Coverage, 133,
30100        GIR_Done,
30101      // Label 1478: @80491
30102      GIM_Try, /*On fail goto*//*Label 1479*/ 80554, // Rule ID 134 //
30103        GIM_CheckFeatures, GIFBS_IsARM,
30104        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
30105        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30106        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30107        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
30109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
30110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30111        // (intrinsic_w_chain:{ *:[i32] } 1859:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
30112        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8,
30113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30115        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30116        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30117        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30118        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30119        GIR_EraseFromParent, /*InsnID*/0,
30120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30121        // GIR_Coverage, 134,
30122        GIR_Done,
30123      // Label 1479: @80554
30124      GIM_Try, /*On fail goto*//*Label 1480*/ 80617, // Rule ID 437 //
30125        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30126        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
30127        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30128        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30129        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
30131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
30132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
30133        // (intrinsic_w_chain:{ *:[i32] } 1789:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
30134        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL,
30135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30138        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30139        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30140        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30141        GIR_EraseFromParent, /*InsnID*/0,
30142        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30143        // GIR_Coverage, 437,
30144        GIR_Done,
30145      // Label 1480: @80617
30146      GIM_Try, /*On fail goto*//*Label 1481*/ 80680, // Rule ID 450 //
30147        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30148        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
30149        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30150        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30151        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30155        // (intrinsic_w_chain:{ *:[i32] } 1788:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30156        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX,
30157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30160        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30161        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30162        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30163        GIR_EraseFromParent, /*InsnID*/0,
30164        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30165        // GIR_Coverage, 450,
30166        GIR_Done,
30167      // Label 1481: @80680
30168      GIM_Try, /*On fail goto*//*Label 1482*/ 80743, // Rule ID 451 //
30169        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30170        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
30171        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30172        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30173        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30177        // (intrinsic_w_chain:{ *:[i32] } 1786:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30178        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16,
30179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30182        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30183        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30184        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30185        GIR_EraseFromParent, /*InsnID*/0,
30186        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30187        // GIR_Coverage, 451,
30188        GIR_Done,
30189      // Label 1482: @80743
30190      GIM_Try, /*On fail goto*//*Label 1483*/ 80806, // Rule ID 452 //
30191        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30192        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
30193        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30194        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30195        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30199        // (intrinsic_w_chain:{ *:[i32] } 1787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30200        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8,
30201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30204        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30205        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30206        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30207        GIR_EraseFromParent, /*InsnID*/0,
30208        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30209        // GIR_Coverage, 452,
30210        GIR_Done,
30211      // Label 1483: @80806
30212      GIM_Try, /*On fail goto*//*Label 1484*/ 80869, // Rule ID 453 //
30213        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30214        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
30215        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30216        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30217        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30221        // (intrinsic_w_chain:{ *:[i32] } 1824:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX,
30223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30226        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30227        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30228        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30229        GIR_EraseFromParent, /*InsnID*/0,
30230        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30231        // GIR_Coverage, 453,
30232        GIR_Done,
30233      // Label 1484: @80869
30234      GIM_Try, /*On fail goto*//*Label 1485*/ 80932, // Rule ID 454 //
30235        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30236        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
30237        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30238        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30239        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30242        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30243        // (intrinsic_w_chain:{ *:[i32] } 1825:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30244        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16,
30245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30248        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30249        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30250        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30251        GIR_EraseFromParent, /*InsnID*/0,
30252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30253        // GIR_Coverage, 454,
30254        GIR_Done,
30255      // Label 1485: @80932
30256      GIM_Try, /*On fail goto*//*Label 1486*/ 80995, // Rule ID 455 //
30257        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30258        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
30259        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30260        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30261        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30265        // (intrinsic_w_chain:{ *:[i32] } 1826:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30266        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8,
30267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30270        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30271        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30272        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30273        GIR_EraseFromParent, /*InsnID*/0,
30274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30275        // GIR_Coverage, 455,
30276        GIR_Done,
30277      // Label 1486: @80995
30278      GIM_Try, /*On fail goto*//*Label 1487*/ 81058, // Rule ID 456 //
30279        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30280        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
30281        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30282        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30283        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30287        // (intrinsic_w_chain:{ *:[i32] } 1839:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30288        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX,
30289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30292        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30293        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30294        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30295        GIR_EraseFromParent, /*InsnID*/0,
30296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30297        // GIR_Coverage, 456,
30298        GIR_Done,
30299      // Label 1487: @81058
30300      GIM_Try, /*On fail goto*//*Label 1488*/ 81121, // Rule ID 457 //
30301        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30302        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
30303        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30304        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30305        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30309        // (intrinsic_w_chain:{ *:[i32] } 1837:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16,
30311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30314        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30315        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30316        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30317        GIR_EraseFromParent, /*InsnID*/0,
30318        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30319        // GIR_Coverage, 457,
30320        GIR_Done,
30321      // Label 1488: @81121
30322      GIM_Try, /*On fail goto*//*Label 1489*/ 81184, // Rule ID 458 //
30323        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30324        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
30325        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30326        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30327        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30331        // (intrinsic_w_chain:{ *:[i32] } 1838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30332        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8,
30333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30336        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30337        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30338        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30339        GIR_EraseFromParent, /*InsnID*/0,
30340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30341        // GIR_Coverage, 458,
30342        GIR_Done,
30343      // Label 1489: @81184
30344      GIM_Try, /*On fail goto*//*Label 1490*/ 81247, // Rule ID 459 //
30345        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30346        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
30347        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30348        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30349        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30353        // (intrinsic_w_chain:{ *:[i32] } 1857:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX,
30355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30358        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30359        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30360        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30361        GIR_EraseFromParent, /*InsnID*/0,
30362        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30363        // GIR_Coverage, 459,
30364        GIR_Done,
30365      // Label 1490: @81247
30366      GIM_Try, /*On fail goto*//*Label 1491*/ 81310, // Rule ID 460 //
30367        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30368        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
30369        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30370        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30371        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30375        // (intrinsic_w_chain:{ *:[i32] } 1858:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16,
30377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30380        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30381        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30382        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30383        GIR_EraseFromParent, /*InsnID*/0,
30384        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30385        // GIR_Coverage, 460,
30386        GIR_Done,
30387      // Label 1491: @81310
30388      GIM_Try, /*On fail goto*//*Label 1492*/ 81373, // Rule ID 461 //
30389        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
30390        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
30391        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30392        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30393        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
30396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30397        // (intrinsic_w_chain:{ *:[i32] } 1859:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
30398        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8,
30399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
30400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
30401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
30402        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30403        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30404        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30405        GIR_EraseFromParent, /*InsnID*/0,
30406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30407        // GIR_Coverage, 461,
30408        GIR_Done,
30409      // Label 1492: @81373
30410      GIM_Reject,
30411    // Label 1457: @81374
30412    GIM_Try, /*On fail goto*//*Label 1493*/ 81652,
30413      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
30414      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vstr_scatter_base_wb,
30415      GIM_Try, /*On fail goto*//*Label 1494*/ 81450, // Rule ID 3840 //
30416        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30417        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30418        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30419        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
30420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30422        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30423        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
30424        // MIs[1] Operand 1
30425        // No operand predicates
30426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
30427        GIM_CheckIsSafeToFold, /*InsnID*/1,
30428        // (intrinsic_w_chain:{ *:[v4i32] } 1642:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
30429        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
30430        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
30431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
30432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
30433        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
30434        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
30435        GIR_EraseFromParent, /*InsnID*/0,
30436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30437        // GIR_Coverage, 3840,
30438        GIR_Done,
30439      // Label 1494: @81450
30440      GIM_Try, /*On fail goto*//*Label 1495*/ 81517, // Rule ID 3850 //
30441        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30442        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30443        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30444        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
30445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30447        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30448        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
30449        // MIs[1] Operand 1
30450        // No operand predicates
30451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
30452        GIM_CheckIsSafeToFold, /*InsnID*/1,
30453        // (intrinsic_w_chain:{ *:[v4i32] } 1642:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
30454        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
30455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
30456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
30457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
30458        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
30459        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
30460        GIR_EraseFromParent, /*InsnID*/0,
30461        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30462        // GIR_Coverage, 3850,
30463        GIR_Done,
30464      // Label 1495: @81517
30465      GIM_Try, /*On fail goto*//*Label 1496*/ 81584, // Rule ID 3854 //
30466        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
30467        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
30468        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30469        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
30470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30472        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30473        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
30474        // MIs[1] Operand 1
30475        // No operand predicates
30476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
30477        GIM_CheckIsSafeToFold, /*InsnID*/1,
30478        // (intrinsic_w_chain:{ *:[v2i64] } 1642:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
30479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
30480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
30481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
30482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
30483        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
30484        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
30485        GIR_EraseFromParent, /*InsnID*/0,
30486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30487        // GIR_Coverage, 3854,
30488        GIR_Done,
30489      // Label 1496: @81584
30490      GIM_Try, /*On fail goto*//*Label 1497*/ 81651, // Rule ID 3858 //
30491        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
30492        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
30493        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30494        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
30495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30497        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30498        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
30499        // MIs[1] Operand 1
30500        // No operand predicates
30501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
30502        GIM_CheckIsSafeToFold, /*InsnID*/1,
30503        // (intrinsic_w_chain:{ *:[v2i64] } 1642:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
30504        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
30505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
30506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
30507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
30508        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
30509        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
30510        GIR_EraseFromParent, /*InsnID*/0,
30511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30512        // GIR_Coverage, 3858,
30513        GIR_Done,
30514      // Label 1497: @81651
30515      GIM_Reject,
30516    // Label 1493: @81652
30517    GIM_Try, /*On fail goto*//*Label 1498*/ 82989,
30518      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
30519      GIM_Try, /*On fail goto*//*Label 1499*/ 81727, // Rule ID 3728 //
30520        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30521        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30522        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30523        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30524        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30525        // MIs[0] base
30526        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30530        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30531        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30532        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
30533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
30534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30537        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30538        GIR_EraseFromParent, /*InsnID*/0,
30539        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30540        // GIR_Coverage, 3728,
30541        GIR_Done,
30542      // Label 1499: @81727
30543      GIM_Try, /*On fail goto*//*Label 1500*/ 81797, // Rule ID 3729 //
30544        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30545        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30546        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30547        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30548        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30549        // MIs[0] base
30550        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30554        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30555        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30556        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
30557        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
30558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30561        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30562        GIR_EraseFromParent, /*InsnID*/0,
30563        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30564        // GIR_Coverage, 3729,
30565        GIR_Done,
30566      // Label 1500: @81797
30567      GIM_Try, /*On fail goto*//*Label 1501*/ 81867, // Rule ID 3732 //
30568        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30569        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30570        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30571        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30572        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30573        // MIs[0] base
30574        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30578        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
30579        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30580        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
30581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB8_rq,
30582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30585        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30586        GIR_EraseFromParent, /*InsnID*/0,
30587        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30588        // GIR_Coverage, 3732,
30589        GIR_Done,
30590      // Label 1501: @81867
30591      GIM_Try, /*On fail goto*//*Label 1502*/ 81937, // Rule ID 3812 //
30592        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30593        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30594        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30595        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30596        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30597        // MIs[0] base
30598        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30602        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
30603        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30604        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
30605        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB16_rq,
30606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30609        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30610        GIR_EraseFromParent, /*InsnID*/0,
30611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30612        // GIR_Coverage, 3812,
30613        GIR_Done,
30614      // Label 1502: @81937
30615      GIM_Try, /*On fail goto*//*Label 1503*/ 82007, // Rule ID 3814 //
30616        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30617        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30618        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30619        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30620        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30621        // MIs[0] base
30622        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30626        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
30627        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30628        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB32_rq,
30630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30633        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30634        GIR_EraseFromParent, /*InsnID*/0,
30635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30636        // GIR_Coverage, 3814,
30637        GIR_Done,
30638      // Label 1503: @82007
30639      GIM_Try, /*On fail goto*//*Label 1504*/ 82077, // Rule ID 3816 //
30640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30643        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30644        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30645        // MIs[0] base
30646        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30650        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30651        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30652        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
30653        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
30654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30657        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30658        GIR_EraseFromParent, /*InsnID*/0,
30659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30660        // GIR_Coverage, 3816,
30661        GIR_Done,
30662      // Label 1504: @82077
30663      GIM_Try, /*On fail goto*//*Label 1505*/ 82147, // Rule ID 3817 //
30664        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30665        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30666        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30667        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30668        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30669        // MIs[0] base
30670        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30674        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30675        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30676        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
30677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
30678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30681        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30682        GIR_EraseFromParent, /*InsnID*/0,
30683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30684        // GIR_Coverage, 3817,
30685        GIR_Done,
30686      // Label 1505: @82147
30687      GIM_Try, /*On fail goto*//*Label 1506*/ 82217, // Rule ID 3820 //
30688        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30689        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30690        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30691        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30692        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30693        // MIs[0] base
30694        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30698        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30699        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30700        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq_u,
30702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30705        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30706        GIR_EraseFromParent, /*InsnID*/0,
30707        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30708        // GIR_Coverage, 3820,
30709        GIR_Done,
30710      // Label 1506: @82217
30711      GIM_Try, /*On fail goto*//*Label 1507*/ 82287, // Rule ID 3821 //
30712        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30713        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30715        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30716        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30717        // MIs[0] base
30718        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30722        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
30723        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30724        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq,
30726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30729        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30730        GIR_EraseFromParent, /*InsnID*/0,
30731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30732        // GIR_Coverage, 3821,
30733        GIR_Done,
30734      // Label 1507: @82287
30735      GIM_Try, /*On fail goto*//*Label 1508*/ 82357, // Rule ID 3824 //
30736        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30737        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30738        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30739        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30740        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30741        // MIs[0] base
30742        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30746        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
30747        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30748        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30749        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
30750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30753        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30754        GIR_EraseFromParent, /*InsnID*/0,
30755        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30756        // GIR_Coverage, 3824,
30757        GIR_Done,
30758      // Label 1508: @82357
30759      GIM_Try, /*On fail goto*//*Label 1509*/ 82427, // Rule ID 3825 //
30760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30761        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30762        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30763        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30764        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30765        // MIs[0] base
30766        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30770        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
30771        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
30772        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
30774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30777        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30778        GIR_EraseFromParent, /*InsnID*/0,
30779        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30780        // GIR_Coverage, 3825,
30781        GIR_Done,
30782      // Label 1509: @82427
30783      GIM_Try, /*On fail goto*//*Label 1510*/ 82497, // Rule ID 3828 //
30784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30785        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30786        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30787        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30788        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30789        // MIs[0] base
30790        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30794        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
30795        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30796        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30797        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
30798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30801        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30802        GIR_EraseFromParent, /*InsnID*/0,
30803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30804        // GIR_Coverage, 3828,
30805        GIR_Done,
30806      // Label 1510: @82497
30807      GIM_Try, /*On fail goto*//*Label 1511*/ 82567, // Rule ID 3829 //
30808        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30809        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30810        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30811        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30812        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30813        // MIs[0] base
30814        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30818        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
30819        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
30820        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
30821        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
30822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30825        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30826        GIR_EraseFromParent, /*InsnID*/0,
30827        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30828        // GIR_Coverage, 3829,
30829        GIR_Done,
30830      // Label 1511: @82567
30831      GIM_Try, /*On fail goto*//*Label 1512*/ 82637, // Rule ID 3832 //
30832        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
30834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
30835        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30836        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30837        // MIs[0] base
30838        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30839        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30842        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
30843        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30844        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
30845        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq_u,
30846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30849        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30850        GIR_EraseFromParent, /*InsnID*/0,
30851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30852        // GIR_Coverage, 3832,
30853        GIR_Done,
30854      // Label 1512: @82637
30855      GIM_Try, /*On fail goto*//*Label 1513*/ 82707, // Rule ID 3833 //
30856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
30857        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
30858        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
30859        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30860        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30861        // MIs[0] base
30862        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
30863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
30864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30866        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
30867        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
30868        // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] })  =>  (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
30869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq,
30870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
30871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
30872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
30873        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30874        GIR_EraseFromParent, /*InsnID*/0,
30875        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30876        // GIR_Coverage, 3833,
30877        GIR_Done,
30878      // Label 1513: @82707
30879      GIM_Try, /*On fail goto*//*Label 1514*/ 82779, // Rule ID 267 //
30880        GIM_CheckFeatures, GIFBS_IsARM,
30881        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
30882        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30883        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30884        // MIs[0] cop
30885        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
30886        // MIs[0] opc1
30887        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
30888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
30890        // MIs[0] CRm
30891        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
30892        // (intrinsic_void 1530:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
30893        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR,
30894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
30895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
30896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
30897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
30898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30899        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30900        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30901        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30902        GIR_EraseFromParent, /*InsnID*/0,
30903        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30904        // GIR_Coverage, 267,
30905        GIR_Done,
30906      // Label 1514: @82779
30907      GIM_Try, /*On fail goto*//*Label 1515*/ 82844, // Rule ID 268 //
30908        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
30909        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
30910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30911        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30912        // MIs[0] cop
30913        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
30914        // MIs[0] opc1
30915        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
30916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
30917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
30918        // MIs[0] CRm
30919        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
30920        // (intrinsic_void 1531:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
30921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2,
30922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
30923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
30924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
30925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
30926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30927        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30928        GIR_EraseFromParent, /*InsnID*/0,
30929        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30930        // GIR_Coverage, 268,
30931        GIR_Done,
30932      // Label 1515: @82844
30933      GIM_Try, /*On fail goto*//*Label 1516*/ 82916, // Rule ID 610 //
30934        GIM_CheckFeatures, GIFBS_IsThumb2,
30935        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
30936        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30937        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30938        // MIs[0] cop
30939        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
30940        // MIs[0] opc1
30941        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
30942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
30943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
30944        // MIs[0] CRm
30945        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
30946        // (intrinsic_void 1530:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
30947        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR,
30948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
30949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
30950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
30951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
30952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30953        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30954        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30955        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30956        GIR_EraseFromParent, /*InsnID*/0,
30957        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30958        // GIR_Coverage, 610,
30959        GIR_Done,
30960      // Label 1516: @82916
30961      GIM_Try, /*On fail goto*//*Label 1517*/ 82988, // Rule ID 611 //
30962        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
30963        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
30964        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30965        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30966        // MIs[0] cop
30967        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
30968        // MIs[0] opc1
30969        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
30970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
30971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
30972        // MIs[0] CRm
30973        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
30974        // (intrinsic_void 1531:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
30975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2,
30976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
30977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
30978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
30979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
30980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30981        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30982        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
30983        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
30984        GIR_EraseFromParent, /*InsnID*/0,
30985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30986        // GIR_Coverage, 611,
30987        GIR_Done,
30988      // Label 1517: @82988
30989      GIM_Reject,
30990    // Label 1498: @82989
30991    GIM_Try, /*On fail goto*//*Label 1518*/ 86829,
30992      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
30993      GIM_Try, /*On fail goto*//*Label 1519*/ 83063, // Rule ID 255 //
30994        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
30995        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
30996        // MIs[0] cop
30997        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
30998        // MIs[0] opc1
30999        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31000        // MIs[0] CRd
31001        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
31002        // MIs[0] CRn
31003        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
31004        // MIs[0] CRm
31005        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
31006        // MIs[0] opc2
31007        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
31008        // (intrinsic_void 1498:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31009        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP,
31010        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
31011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
31012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
31013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
31014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
31015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31016        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
31017        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
31018        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31019        GIR_EraseFromParent, /*InsnID*/0,
31020        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31021        // GIR_Coverage, 255,
31022        GIR_Done,
31023      // Label 1519: @83063
31024      GIM_Try, /*On fail goto*//*Label 1520*/ 83125, // Rule ID 256 //
31025        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
31026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
31027        // MIs[0] cop
31028        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31029        // MIs[0] opc1
31030        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31031        // MIs[0] CRd
31032        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
31033        // MIs[0] CRn
31034        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
31035        // MIs[0] CRm
31036        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
31037        // MIs[0] opc2
31038        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
31039        // (intrinsic_void 1499:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2,
31041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
31042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
31043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
31044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
31045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
31046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31047        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31048        GIR_EraseFromParent, /*InsnID*/0,
31049        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31050        // GIR_Coverage, 256,
31051        GIR_Done,
31052      // Label 1520: @83125
31053      GIM_Try, /*On fail goto*//*Label 1521*/ 83194, // Rule ID 612 //
31054        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
31055        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
31056        // MIs[0] cop
31057        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31058        // MIs[0] opc1
31059        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31060        // MIs[0] CRd
31061        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
31062        // MIs[0] CRn
31063        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
31064        // MIs[0] CRm
31065        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
31066        // MIs[0] opc2
31067        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
31068        // (intrinsic_void 1498:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP,
31070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
31071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
31072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
31073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
31074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
31075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31076        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
31077        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
31078        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31079        GIR_EraseFromParent, /*InsnID*/0,
31080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31081        // GIR_Coverage, 612,
31082        GIR_Done,
31083      // Label 1521: @83194
31084      GIM_Try, /*On fail goto*//*Label 1522*/ 83263, // Rule ID 613 //
31085        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
31086        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
31087        // MIs[0] cop
31088        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31089        // MIs[0] opc1
31090        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31091        // MIs[0] CRd
31092        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
31093        // MIs[0] CRn
31094        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
31095        // MIs[0] CRm
31096        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
31097        // MIs[0] opc2
31098        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
31099        // (intrinsic_void 1499:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31100        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2,
31101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
31102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
31103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
31104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
31105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
31106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31107        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
31108        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
31109        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31110        GIR_EraseFromParent, /*InsnID*/0,
31111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31112        // GIR_Coverage, 613,
31113        GIR_Done,
31114      // Label 1522: @83263
31115      GIM_Try, /*On fail goto*//*Label 1523*/ 83341, // Rule ID 3722 //
31116        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31117        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31119        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31120        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31121        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31123        // MIs[0] base
31124        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31127        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31128        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31129        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31130        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31131        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31135        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31136        GIR_EraseFromParent, /*InsnID*/0,
31137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31138        // GIR_Coverage, 3722,
31139        GIR_Done,
31140      // Label 1523: @83341
31141      GIM_Try, /*On fail goto*//*Label 1524*/ 83419, // Rule ID 3723 //
31142        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31143        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31145        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31146        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31147        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31149        // MIs[0] base
31150        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31153        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31154        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31155        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31156        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31157        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31161        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31162        GIR_EraseFromParent, /*InsnID*/0,
31163        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31164        // GIR_Coverage, 3723,
31165        GIR_Done,
31166      // Label 1524: @83419
31167      GIM_Try, /*On fail goto*//*Label 1525*/ 83497, // Rule ID 3726 //
31168        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31169        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31170        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31171        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31172        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31173        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31175        // MIs[0] base
31176        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31179        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31180        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31181        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31182        // (intrinsic_w_chain:{ *:[v16i8] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
31183        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
31184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31187        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31188        GIR_EraseFromParent, /*InsnID*/0,
31189        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31190        // GIR_Coverage, 3726,
31191        GIR_Done,
31192      // Label 1525: @83497
31193      GIM_Try, /*On fail goto*//*Label 1526*/ 83575, // Rule ID 3734 //
31194        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31195        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31196        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31197        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31198        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31199        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31201        // MIs[0] base
31202        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31205        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31206        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31207        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31208        // (intrinsic_w_chain:{ *:[v16i8] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
31209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
31210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31213        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31214        GIR_EraseFromParent, /*InsnID*/0,
31215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31216        // GIR_Coverage, 3734,
31217        GIR_Done,
31218      // Label 1526: @83575
31219      GIM_Try, /*On fail goto*//*Label 1527*/ 83653, // Rule ID 3736 //
31220        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31221        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31222        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31223        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31224        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31225        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31227        // MIs[0] base
31228        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31231        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31232        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31233        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31234        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU16_rq,
31236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31239        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31240        GIR_EraseFromParent, /*InsnID*/0,
31241        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31242        // GIR_Coverage, 3736,
31243        GIR_Done,
31244      // Label 1527: @83653
31245      GIM_Try, /*On fail goto*//*Label 1528*/ 83731, // Rule ID 3738 //
31246        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31247        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31248        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31249        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31250        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31251        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31253        // MIs[0] base
31254        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31257        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31258        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31259        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31260        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31261        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS16_rq,
31262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31265        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31266        GIR_EraseFromParent, /*InsnID*/0,
31267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31268        // GIR_Coverage, 3738,
31269        GIR_Done,
31270      // Label 1528: @83731
31271      GIM_Try, /*On fail goto*//*Label 1529*/ 83809, // Rule ID 3740 //
31272        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31273        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31275        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31276        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31277        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31279        // MIs[0] base
31280        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31283        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31284        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31285        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31286        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU32_rq,
31288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31291        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31292        GIR_EraseFromParent, /*InsnID*/0,
31293        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31294        // GIR_Coverage, 3740,
31295        GIR_Done,
31296      // Label 1529: @83809
31297      GIM_Try, /*On fail goto*//*Label 1530*/ 83887, // Rule ID 3742 //
31298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31300        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31301        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31302        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31303        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31305        // MIs[0] base
31306        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31309        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
31310        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31311        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31312        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31313        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS32_rq,
31314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31317        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31318        GIR_EraseFromParent, /*InsnID*/0,
31319        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31320        // GIR_Coverage, 3742,
31321        GIR_Done,
31322      // Label 1530: @83887
31323      GIM_Try, /*On fail goto*//*Label 1531*/ 83965, // Rule ID 3744 //
31324        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31325        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31326        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31327        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31328        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31329        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31331        // MIs[0] base
31332        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31335        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31336        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31337        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31338        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31343        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31344        GIR_EraseFromParent, /*InsnID*/0,
31345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31346        // GIR_Coverage, 3744,
31347        GIR_Done,
31348      // Label 1531: @83965
31349      GIM_Try, /*On fail goto*//*Label 1532*/ 84043, // Rule ID 3745 //
31350        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31351        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31352        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31353        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31354        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31355        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31357        // MIs[0] base
31358        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31361        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31362        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31363        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31364        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31365        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31369        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31370        GIR_EraseFromParent, /*InsnID*/0,
31371        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31372        // GIR_Coverage, 3745,
31373        GIR_Done,
31374      // Label 1532: @84043
31375      GIM_Try, /*On fail goto*//*Label 1533*/ 84121, // Rule ID 3748 //
31376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31378        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31379        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31380        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31381        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31383        // MIs[0] base
31384        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31387        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31388        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31389        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31390        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31395        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31396        GIR_EraseFromParent, /*InsnID*/0,
31397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31398        // GIR_Coverage, 3748,
31399        GIR_Done,
31400      // Label 1533: @84121
31401      GIM_Try, /*On fail goto*//*Label 1534*/ 84199, // Rule ID 3749 //
31402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31404        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31405        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31406        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31407        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31409        // MIs[0] base
31410        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31413        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31414        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31415        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31416        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31417        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31421        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31422        GIR_EraseFromParent, /*InsnID*/0,
31423        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31424        // GIR_Coverage, 3749,
31425        GIR_Done,
31426      // Label 1534: @84199
31427      GIM_Try, /*On fail goto*//*Label 1535*/ 84277, // Rule ID 3752 //
31428        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31429        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31430        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31431        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31432        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31433        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31435        // MIs[0] base
31436        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31439        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31440        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31441        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31442        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31443        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31447        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31448        GIR_EraseFromParent, /*InsnID*/0,
31449        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31450        // GIR_Coverage, 3752,
31451        GIR_Done,
31452      // Label 1535: @84277
31453      GIM_Try, /*On fail goto*//*Label 1536*/ 84355, // Rule ID 3753 //
31454        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31455        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31456        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31457        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31458        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31459        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31461        // MIs[0] base
31462        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31465        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31466        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31467        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31468        // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31469        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31473        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31474        GIR_EraseFromParent, /*InsnID*/0,
31475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31476        // GIR_Coverage, 3753,
31477        GIR_Done,
31478      // Label 1536: @84355
31479      GIM_Try, /*On fail goto*//*Label 1537*/ 84433, // Rule ID 3756 //
31480        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31481        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31482        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31483        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31484        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31485        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31487        // MIs[0] base
31488        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31491        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31492        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31493        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31494        // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31499        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31500        GIR_EraseFromParent, /*InsnID*/0,
31501        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31502        // GIR_Coverage, 3756,
31503        GIR_Done,
31504      // Label 1537: @84433
31505      GIM_Try, /*On fail goto*//*Label 1538*/ 84511, // Rule ID 3757 //
31506        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31507        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31508        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31509        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31510        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31511        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31513        // MIs[0] base
31514        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31516        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31517        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31518        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31519        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31520        // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31525        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31526        GIR_EraseFromParent, /*InsnID*/0,
31527        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31528        // GIR_Coverage, 3757,
31529        GIR_Done,
31530      // Label 1538: @84511
31531      GIM_Try, /*On fail goto*//*Label 1539*/ 84589, // Rule ID 3760 //
31532        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31533        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31534        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31535        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31536        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31537        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31539        // MIs[0] base
31540        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31543        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31544        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31545        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31546        // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31547        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
31548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31551        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31552        GIR_EraseFromParent, /*InsnID*/0,
31553        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31554        // GIR_Coverage, 3760,
31555        GIR_Done,
31556      // Label 1539: @84589
31557      GIM_Try, /*On fail goto*//*Label 1540*/ 84667, // Rule ID 3761 //
31558        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31559        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31561        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31562        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31563        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31565        // MIs[0] base
31566        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31569        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31570        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31571        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31572        // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
31573        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
31574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31577        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31578        GIR_EraseFromParent, /*InsnID*/0,
31579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31580        // GIR_Coverage, 3761,
31581        GIR_Done,
31582      // Label 1540: @84667
31583      GIM_Try, /*On fail goto*//*Label 1541*/ 84745, // Rule ID 3764 //
31584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31586        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31587        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31588        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31589        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31591        // MIs[0] base
31592        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31595        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31596        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31597        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31598        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq_u,
31600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31603        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31604        GIR_EraseFromParent, /*InsnID*/0,
31605        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31606        // GIR_Coverage, 3764,
31607        GIR_Done,
31608      // Label 1541: @84745
31609      GIM_Try, /*On fail goto*//*Label 1542*/ 84823, // Rule ID 3765 //
31610        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31611        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31613        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31614        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31615        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31617        // MIs[0] base
31618        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31621        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31622        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31623        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31624        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31625        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq,
31626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31629        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31630        GIR_EraseFromParent, /*InsnID*/0,
31631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31632        // GIR_Coverage, 3765,
31633        GIR_Done,
31634      // Label 1542: @84823
31635      GIM_Try, /*On fail goto*//*Label 1543*/ 84901, // Rule ID 3768 //
31636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31638        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31639        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31640        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31641        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31643        // MIs[0] base
31644        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31647        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31648        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31649        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31650        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq_u,
31652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31655        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31656        GIR_EraseFromParent, /*InsnID*/0,
31657        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31658        // GIR_Coverage, 3768,
31659        GIR_Done,
31660      // Label 1543: @84901
31661      GIM_Try, /*On fail goto*//*Label 1544*/ 84979, // Rule ID 3769 //
31662        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31663        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31664        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31665        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31666        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31667        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31669        // MIs[0] base
31670        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31673        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
31674        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31675        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31676        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq,
31678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31681        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31682        GIR_EraseFromParent, /*InsnID*/0,
31683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31684        // GIR_Coverage, 3769,
31685        GIR_Done,
31686      // Label 1544: @84979
31687      GIM_Try, /*On fail goto*//*Label 1545*/ 85057, // Rule ID 3772 //
31688        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31689        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31690        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31691        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31692        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31693        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31695        // MIs[0] base
31696        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31699        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31700        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31701        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31702        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31707        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31708        GIR_EraseFromParent, /*InsnID*/0,
31709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31710        // GIR_Coverage, 3772,
31711        GIR_Done,
31712      // Label 1545: @85057
31713      GIM_Try, /*On fail goto*//*Label 1546*/ 85135, // Rule ID 3773 //
31714        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31715        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31716        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31717        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31718        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31719        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31721        // MIs[0] base
31722        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31725        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31726        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31727        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31728        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31729        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31733        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31734        GIR_EraseFromParent, /*InsnID*/0,
31735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31736        // GIR_Coverage, 3773,
31737        GIR_Done,
31738      // Label 1546: @85135
31739      GIM_Try, /*On fail goto*//*Label 1547*/ 85213, // Rule ID 3776 //
31740        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31741        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31742        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31743        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31744        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31745        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31747        // MIs[0] base
31748        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31751        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31752        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31753        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31754        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31755        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31759        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31760        GIR_EraseFromParent, /*InsnID*/0,
31761        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31762        // GIR_Coverage, 3776,
31763        GIR_Done,
31764      // Label 1547: @85213
31765      GIM_Try, /*On fail goto*//*Label 1548*/ 85291, // Rule ID 3777 //
31766        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31767        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31769        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31770        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31771        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31773        // MIs[0] base
31774        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31777        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31778        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31779        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31780        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31785        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31786        GIR_EraseFromParent, /*InsnID*/0,
31787        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31788        // GIR_Coverage, 3777,
31789        GIR_Done,
31790      // Label 1548: @85291
31791      GIM_Try, /*On fail goto*//*Label 1549*/ 85369, // Rule ID 3780 //
31792        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31793        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31795        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31796        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31797        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31799        // MIs[0] base
31800        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31801        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31803        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31804        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31805        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31806        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31807        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31811        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31812        GIR_EraseFromParent, /*InsnID*/0,
31813        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31814        // GIR_Coverage, 3780,
31815        GIR_Done,
31816      // Label 1549: @85369
31817      GIM_Try, /*On fail goto*//*Label 1550*/ 85447, // Rule ID 3781 //
31818        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31819        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31820        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31821        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31822        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31823        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31825        // MIs[0] base
31826        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31829        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31830        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31831        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31832        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31833        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31837        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31838        GIR_EraseFromParent, /*InsnID*/0,
31839        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31840        // GIR_Coverage, 3781,
31841        GIR_Done,
31842      // Label 1550: @85447
31843      GIM_Try, /*On fail goto*//*Label 1551*/ 85525, // Rule ID 3784 //
31844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31846        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31847        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31848        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31849        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31851        // MIs[0] base
31852        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31855        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31856        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31857        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31858        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31863        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31864        GIR_EraseFromParent, /*InsnID*/0,
31865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31866        // GIR_Coverage, 3784,
31867        GIR_Done,
31868      // Label 1551: @85525
31869      GIM_Try, /*On fail goto*//*Label 1552*/ 85603, // Rule ID 3785 //
31870        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31871        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31872        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31873        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31874        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31875        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31877        // MIs[0] base
31878        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31881        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31882        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31883        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31884        // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31885        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31889        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31890        GIR_EraseFromParent, /*InsnID*/0,
31891        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31892        // GIR_Coverage, 3785,
31893        GIR_Done,
31894      // Label 1552: @85603
31895      GIM_Try, /*On fail goto*//*Label 1553*/ 85681, // Rule ID 3788 //
31896        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31897        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31898        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31899        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31900        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31901        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31903        // MIs[0] base
31904        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31907        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31908        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31909        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31910        // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31911        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31915        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31916        GIR_EraseFromParent, /*InsnID*/0,
31917        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31918        // GIR_Coverage, 3788,
31919        GIR_Done,
31920      // Label 1553: @85681
31921      GIM_Try, /*On fail goto*//*Label 1554*/ 85759, // Rule ID 3789 //
31922        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31923        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31924        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31925        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31926        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31927        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31929        // MIs[0] base
31930        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31933        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31934        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31935        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31936        // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31937        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31941        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31942        GIR_EraseFromParent, /*InsnID*/0,
31943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31944        // GIR_Coverage, 3789,
31945        GIR_Done,
31946      // Label 1554: @85759
31947      GIM_Try, /*On fail goto*//*Label 1555*/ 85837, // Rule ID 3792 //
31948        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31949        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31950        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31951        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31952        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31953        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31955        // MIs[0] base
31956        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31959        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31960        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31961        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31962        // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
31964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31967        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31968        GIR_EraseFromParent, /*InsnID*/0,
31969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31970        // GIR_Coverage, 3792,
31971        GIR_Done,
31972      // Label 1555: @85837
31973      GIM_Try, /*On fail goto*//*Label 1556*/ 85915, // Rule ID 3793 //
31974        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
31975        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31976        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31977        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31978        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31979        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31981        // MIs[0] base
31982        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
31983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
31984        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31985        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
31986        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
31987        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31988        // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
31989        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
31990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
31992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
31993        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
31994        GIR_EraseFromParent, /*InsnID*/0,
31995        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31996        // GIR_Coverage, 3793,
31997        GIR_Done,
31998      // Label 1556: @85915
31999      GIM_Try, /*On fail goto*//*Label 1557*/ 85993, // Rule ID 3796 //
32000        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32001        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32002        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32003        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32004        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32005        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32007        // MIs[0] base
32008        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32011        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32012        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32013        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32014        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32015        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
32016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32019        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32020        GIR_EraseFromParent, /*InsnID*/0,
32021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32022        // GIR_Coverage, 3796,
32023        GIR_Done,
32024      // Label 1557: @85993
32025      GIM_Try, /*On fail goto*//*Label 1558*/ 86071, // Rule ID 3797 //
32026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32027        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32028        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32029        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32030        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32031        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32033        // MIs[0] base
32034        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32037        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32038        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
32039        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32040        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32041        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
32042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32045        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32046        GIR_EraseFromParent, /*InsnID*/0,
32047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32048        // GIR_Coverage, 3797,
32049        GIR_Done,
32050      // Label 1558: @86071
32051      GIM_Try, /*On fail goto*//*Label 1559*/ 86149, // Rule ID 3800 //
32052        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32053        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32054        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32055        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32056        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32057        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32059        // MIs[0] base
32060        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32063        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32064        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32065        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32066        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
32068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32071        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32072        GIR_EraseFromParent, /*InsnID*/0,
32073        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32074        // GIR_Coverage, 3800,
32075        GIR_Done,
32076      // Label 1559: @86149
32077      GIM_Try, /*On fail goto*//*Label 1560*/ 86227, // Rule ID 3801 //
32078        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32079        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32080        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32081        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32082        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32083        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32085        // MIs[0] base
32086        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32089        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32090        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
32091        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32092        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32093        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
32094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32097        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32098        GIR_EraseFromParent, /*InsnID*/0,
32099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32100        // GIR_Coverage, 3801,
32101        GIR_Done,
32102      // Label 1560: @86227
32103      GIM_Try, /*On fail goto*//*Label 1561*/ 86305, // Rule ID 3804 //
32104        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32105        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32107        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32108        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32109        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32111        // MIs[0] base
32112        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32115        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32116        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32117        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32118        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
32120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32123        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32124        GIR_EraseFromParent, /*InsnID*/0,
32125        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32126        // GIR_Coverage, 3804,
32127        GIR_Done,
32128      // Label 1561: @86305
32129      GIM_Try, /*On fail goto*//*Label 1562*/ 86383, // Rule ID 3805 //
32130        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32131        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32132        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32133        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32134        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32135        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32137        // MIs[0] base
32138        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32141        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32142        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
32143        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32144        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32145        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
32146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32149        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32150        GIR_EraseFromParent, /*InsnID*/0,
32151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32152        // GIR_Coverage, 3805,
32153        GIR_Done,
32154      // Label 1562: @86383
32155      GIM_Try, /*On fail goto*//*Label 1563*/ 86461, // Rule ID 3808 //
32156        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32157        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32158        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32159        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32160        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32161        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32163        // MIs[0] base
32164        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32167        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32168        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32169        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32170        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32171        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
32172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32175        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32176        GIR_EraseFromParent, /*InsnID*/0,
32177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32178        // GIR_Coverage, 3808,
32179        GIR_Done,
32180      // Label 1563: @86461
32181      GIM_Try, /*On fail goto*//*Label 1564*/ 86539, // Rule ID 3809 //
32182        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
32183        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
32184        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
32185        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32186        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32187        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32189        // MIs[0] base
32190        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
32191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
32192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32193        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
32194        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
32195        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32196        // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
32197        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
32198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
32200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
32201        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32202        GIR_EraseFromParent, /*InsnID*/0,
32203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32204        // GIR_Coverage, 3809,
32205        GIR_Done,
32206      // Label 1564: @86539
32207      GIM_Try, /*On fail goto*//*Label 1565*/ 86613, // Rule ID 265 //
32208        GIM_CheckFeatures, GIFBS_IsARM,
32209        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
32210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32211        // MIs[0] cop
32212        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
32213        // MIs[0] opc1
32214        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
32215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
32216        // MIs[0] CRn
32217        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
32218        // MIs[0] CRm
32219        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
32220        // MIs[0] opc2
32221        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
32222        // (intrinsic_void 1528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
32223        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
32224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
32225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
32226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
32227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
32228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
32229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
32230        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32231        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32232        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32233        GIR_EraseFromParent, /*InsnID*/0,
32234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32235        // GIR_Coverage, 265,
32236        GIR_Done,
32237      // Label 1565: @86613
32238      GIM_Try, /*On fail goto*//*Label 1566*/ 86680, // Rule ID 266 //
32239        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
32240        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
32241        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32242        // MIs[0] cop
32243        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
32244        // MIs[0] opc1
32245        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
32246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
32247        // MIs[0] CRn
32248        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
32249        // MIs[0] CRm
32250        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
32251        // MIs[0] opc2
32252        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
32253        // (intrinsic_void 1529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
32254        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2,
32255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
32256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
32257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
32258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
32259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
32260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
32261        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32262        GIR_EraseFromParent, /*InsnID*/0,
32263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32264        // GIR_Coverage, 266,
32265        GIR_Done,
32266      // Label 1566: @86680
32267      GIM_Try, /*On fail goto*//*Label 1567*/ 86754, // Rule ID 608 //
32268        GIM_CheckFeatures, GIFBS_IsThumb2,
32269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
32270        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32271        // MIs[0] cop
32272        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
32273        // MIs[0] opc1
32274        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
32275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
32276        // MIs[0] CRn
32277        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
32278        // MIs[0] CRm
32279        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
32280        // MIs[0] opc2
32281        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
32282        // (intrinsic_void 1528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
32283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR,
32284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
32285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
32286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
32287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
32288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
32289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
32290        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32291        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32292        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32293        GIR_EraseFromParent, /*InsnID*/0,
32294        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32295        // GIR_Coverage, 608,
32296        GIR_Done,
32297      // Label 1567: @86754
32298      GIM_Try, /*On fail goto*//*Label 1568*/ 86828, // Rule ID 609 //
32299        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
32300        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
32301        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32302        // MIs[0] cop
32303        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
32304        // MIs[0] opc1
32305        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
32306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
32307        // MIs[0] CRn
32308        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
32309        // MIs[0] CRm
32310        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
32311        // MIs[0] opc2
32312        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
32313        // (intrinsic_void 1529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
32314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2,
32315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
32316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
32317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
32318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
32319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
32320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
32321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32322        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32323        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
32324        GIR_EraseFromParent, /*InsnID*/0,
32325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32326        // GIR_Coverage, 609,
32327        GIR_Done,
32328      // Label 1568: @86828
32329      GIM_Reject,
32330    // Label 1518: @86829
32331    GIM_Reject,
32332    // Label 14: @86830
32333    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1572*/ 86964,
32334    /*GILLT_v2s64*//*Label 1569*/ 86844, 0, 0,
32335    /*GILLT_v4s32*//*Label 1570*/ 86884, 0, 0, 0,
32336    /*GILLT_v8s16*//*Label 1571*/ 86924,
32337    // Label 1569: @86844
32338    GIM_Try, /*On fail goto*//*Label 1573*/ 86883, // Rule ID 2537 //
32339      GIM_CheckFeatures, GIFBS_HasNEON,
32340      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
32341      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32342      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32343      // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
32344      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
32345      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32346      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32347      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32348      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32349      GIR_EraseFromParent, /*InsnID*/0,
32350      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32351      // GIR_Coverage, 2537,
32352      GIR_Done,
32353    // Label 1573: @86883
32354    GIM_Reject,
32355    // Label 1570: @86884
32356    GIM_Try, /*On fail goto*//*Label 1574*/ 86923, // Rule ID 2536 //
32357      GIM_CheckFeatures, GIFBS_HasNEON,
32358      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
32359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32360      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32361      // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
32362      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
32363      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32364      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32365      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32366      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32367      GIR_EraseFromParent, /*InsnID*/0,
32368      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32369      // GIR_Coverage, 2536,
32370      GIR_Done,
32371    // Label 1574: @86923
32372    GIM_Reject,
32373    // Label 1571: @86924
32374    GIM_Try, /*On fail goto*//*Label 1575*/ 86963, // Rule ID 2535 //
32375      GIM_CheckFeatures, GIFBS_HasNEON,
32376      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
32377      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32378      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32379      // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
32380      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
32381      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32382      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32383      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32384      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32385      GIR_EraseFromParent, /*InsnID*/0,
32386      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32387      // GIR_Coverage, 2535,
32388      GIR_Done,
32389    // Label 1575: @86963
32390    GIM_Reject,
32391    // Label 1572: @86964
32392    GIM_Reject,
32393    // Label 15: @86965
32394    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 14, /*)*//*default:*//*Label 1582*/ 87243,
32395    /*GILLT_v2s32*//*Label 1576*/ 86982, 0,
32396    /*GILLT_v4s1*//*Label 1577*/ 87022,
32397    /*GILLT_v4s16*//*Label 1578*/ 87069, 0, 0,
32398    /*GILLT_v8s1*//*Label 1579*/ 87109,
32399    /*GILLT_v8s8*//*Label 1580*/ 87156, 0, 0,
32400    /*GILLT_v16s1*//*Label 1581*/ 87196,
32401    // Label 1576: @86982
32402    GIM_Try, /*On fail goto*//*Label 1583*/ 87021, // Rule ID 1576 //
32403      GIM_CheckFeatures, GIFBS_HasNEON,
32404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
32405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
32406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
32407      // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)  =>  (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
32408      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32,
32409      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32410      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32411      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32412      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32413      GIR_EraseFromParent, /*InsnID*/0,
32414      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32415      // GIR_Coverage, 1576,
32416      GIR_Done,
32417    // Label 1583: @87021
32418    GIM_Reject,
32419    // Label 1577: @87022
32420    GIM_Try, /*On fail goto*//*Label 1584*/ 87068, // Rule ID 3881 //
32421      GIM_CheckFeatures, GIFBS_HasMVEInt,
32422      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
32423      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
32424      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
32425      // (trunc:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1)  =>  (MVE_VCMPi32r:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
32426      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
32427      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
32428      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
32429      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
32430      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
32431      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32432      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32433      GIR_EraseFromParent, /*InsnID*/0,
32434      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32435      // GIR_Coverage, 3881,
32436      GIR_Done,
32437    // Label 1584: @87068
32438    GIM_Reject,
32439    // Label 1578: @87069
32440    GIM_Try, /*On fail goto*//*Label 1585*/ 87108, // Rule ID 1575 //
32441      GIM_CheckFeatures, GIFBS_HasNEON,
32442      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
32443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
32444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
32445      // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)  =>  (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
32446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16,
32447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32449      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32450      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32451      GIR_EraseFromParent, /*InsnID*/0,
32452      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32453      // GIR_Coverage, 1575,
32454      GIR_Done,
32455    // Label 1585: @87108
32456    GIM_Reject,
32457    // Label 1579: @87109
32458    GIM_Try, /*On fail goto*//*Label 1586*/ 87155, // Rule ID 3880 //
32459      GIM_CheckFeatures, GIFBS_HasMVEInt,
32460      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
32461      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
32462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
32463      // (trunc:{ *:[v8i1] } MQPR:{ *:[v8i16] }:$v1)  =>  (MVE_VCMPi32r:{ *:[v8i1] } MQPR:{ *:[v8i16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
32464      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
32465      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
32466      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
32467      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
32468      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
32469      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32470      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32471      GIR_EraseFromParent, /*InsnID*/0,
32472      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32473      // GIR_Coverage, 3880,
32474      GIR_Done,
32475    // Label 1586: @87155
32476    GIM_Reject,
32477    // Label 1580: @87156
32478    GIM_Try, /*On fail goto*//*Label 1587*/ 87195, // Rule ID 1574 //
32479      GIM_CheckFeatures, GIFBS_HasNEON,
32480      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
32481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
32482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
32483      // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)  =>  (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
32484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8,
32485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32487      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32488      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32489      GIR_EraseFromParent, /*InsnID*/0,
32490      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32491      // GIR_Coverage, 1574,
32492      GIR_Done,
32493    // Label 1587: @87195
32494    GIM_Reject,
32495    // Label 1581: @87196
32496    GIM_Try, /*On fail goto*//*Label 1588*/ 87242, // Rule ID 3879 //
32497      GIM_CheckFeatures, GIFBS_HasMVEInt,
32498      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
32499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
32500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
32501      // (trunc:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1)  =>  (MVE_VCMPi32r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
32502      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
32503      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
32504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
32505      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
32506      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
32507      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32508      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32509      GIR_EraseFromParent, /*InsnID*/0,
32510      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32511      // GIR_Coverage, 3879,
32512      GIR_Done,
32513    // Label 1588: @87242
32514    GIM_Reject,
32515    // Label 1582: @87243
32516    GIM_Reject,
32517    // Label 16: @87244
32518    GIM_Try, /*On fail goto*//*Label 1589*/ 87440,
32519      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32520      GIM_Try, /*On fail goto*//*Label 1590*/ 87287, // Rule ID 410 //
32521        GIM_CheckFeatures, GIFBS_IsThumb2,
32522        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
32523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
32524        // MIs[0] Operand 1
32525        // No operand predicates
32526        // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm  =>  (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
32527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi,
32528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32529        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
32530        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32531        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32532        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32533        GIR_EraseFromParent, /*InsnID*/0,
32534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32535        // GIR_Coverage, 410,
32536        GIR_Done,
32537      // Label 1590: @87287
32538      GIM_Try, /*On fail goto*//*Label 1591*/ 87324, // Rule ID 59 //
32539        GIM_CheckFeatures, GIFBS_IsARM,
32540        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
32541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
32542        // MIs[0] Operand 1
32543        // No operand predicates
32544        // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm  =>  (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
32545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi,
32546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32547        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
32548        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32549        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32550        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32551        GIR_EraseFromParent, /*InsnID*/0,
32552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32553        // GIR_Coverage, 59,
32554        GIR_Done,
32555      // Label 1591: @87324
32556      GIM_Try, /*On fail goto*//*Label 1592*/ 87357, // Rule ID 60 //
32557        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
32558        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
32559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
32560        // MIs[0] Operand 1
32561        // No operand predicates
32562        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
32563        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16,
32564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32565        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
32566        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32567        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32568        GIR_EraseFromParent, /*InsnID*/0,
32569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32570        // GIR_Coverage, 60,
32571        GIR_Done,
32572      // Label 1592: @87357
32573      GIM_Try, /*On fail goto*//*Label 1593*/ 87383, // Rule ID 277 //
32574        GIM_CheckFeatures, GIFBS_IsARM,
32575        GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_arm_i32imm,
32576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
32577        // MIs[0] Operand 1
32578        // No operand predicates
32579        // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src  =>  (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
32580        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi32imm,
32581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
32582        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
32583        GIR_EraseFromParent, /*InsnID*/0,
32584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32585        // GIR_Coverage, 277,
32586        GIR_Done,
32587      // Label 1593: @87383
32588      GIM_Try, /*On fail goto*//*Label 1594*/ 87416, // Rule ID 411 //
32589        GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
32590        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
32591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
32592        // MIs[0] Operand 1
32593        // No operand predicates
32594        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
32595        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16,
32596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32597        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
32598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32599        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32600        GIR_EraseFromParent, /*InsnID*/0,
32601        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32602        // GIR_Coverage, 411,
32603        GIR_Done,
32604      // Label 1594: @87416
32605      GIM_Try, /*On fail goto*//*Label 1595*/ 87439, // Rule ID 597 //
32606        GIM_CheckFeatures, GIFBS_IsThumb_UseMovt,
32607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
32608        // MIs[0] Operand 1
32609        // No operand predicates
32610        // (imm:{ *:[i32] }):$src  =>  (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
32611        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm,
32612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
32613        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
32614        GIR_EraseFromParent, /*InsnID*/0,
32615        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32616        // GIR_Coverage, 597,
32617        GIR_Done,
32618      // Label 1595: @87439
32619      GIM_Reject,
32620    // Label 1589: @87440
32621    GIM_Reject,
32622    // Label 17: @87441
32623    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1598*/ 87519,
32624    /*GILLT_s32*//*Label 1596*/ 87449,
32625    /*GILLT_s64*//*Label 1597*/ 87484,
32626    // Label 1596: @87449
32627    GIM_Try, /*On fail goto*//*Label 1599*/ 87483, // Rule ID 743 //
32628      GIM_CheckFeatures, GIFBS_HasVFP3,
32629      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f32imm,
32630      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
32631      // MIs[0] Operand 1
32632      // No operand predicates
32633      // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm  =>  (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
32634      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTS,
32635      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
32636      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF32Imm, // imm
32637      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32638      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32639      GIR_EraseFromParent, /*InsnID*/0,
32640      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32641      // GIR_Coverage, 743,
32642      GIR_Done,
32643    // Label 1599: @87483
32644    GIM_Reject,
32645    // Label 1597: @87484
32646    GIM_Try, /*On fail goto*//*Label 1600*/ 87518, // Rule ID 742 //
32647      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP3,
32648      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f64imm,
32649      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
32650      // MIs[0] Operand 1
32651      // No operand predicates
32652      // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm  =>  (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
32653      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTD,
32654      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
32655      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF64Imm, // imm
32656      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32657      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32658      GIR_EraseFromParent, /*InsnID*/0,
32659      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32660      // GIR_Coverage, 742,
32661      GIR_Done,
32662    // Label 1600: @87518
32663    GIM_Reject,
32664    // Label 1598: @87519
32665    GIM_Reject,
32666    // Label 18: @87520
32667    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1604*/ 87654,
32668    /*GILLT_v2s64*//*Label 1601*/ 87534, 0, 0,
32669    /*GILLT_v4s32*//*Label 1602*/ 87574, 0, 0, 0,
32670    /*GILLT_v8s16*//*Label 1603*/ 87614,
32671    // Label 1601: @87534
32672    GIM_Try, /*On fail goto*//*Label 1605*/ 87573, // Rule ID 1588 //
32673      GIM_CheckFeatures, GIFBS_HasNEON,
32674      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
32675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32677      // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
32678      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64,
32679      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32680      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32681      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32682      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32683      GIR_EraseFromParent, /*InsnID*/0,
32684      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32685      // GIR_Coverage, 1588,
32686      GIR_Done,
32687    // Label 1605: @87573
32688    GIM_Reject,
32689    // Label 1602: @87574
32690    GIM_Try, /*On fail goto*//*Label 1606*/ 87613, // Rule ID 1587 //
32691      GIM_CheckFeatures, GIFBS_HasNEON,
32692      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
32693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32694      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32695      // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
32696      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32,
32697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32698      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32699      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32700      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32701      GIR_EraseFromParent, /*InsnID*/0,
32702      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32703      // GIR_Coverage, 1587,
32704      GIR_Done,
32705    // Label 1606: @87613
32706    GIM_Reject,
32707    // Label 1603: @87614
32708    GIM_Try, /*On fail goto*//*Label 1607*/ 87653, // Rule ID 1586 //
32709      GIM_CheckFeatures, GIFBS_HasNEON,
32710      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
32711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32712      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32713      // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
32714      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16,
32715      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32716      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32717      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32718      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32719      GIR_EraseFromParent, /*InsnID*/0,
32720      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32721      // GIR_Coverage, 1586,
32722      GIR_Done,
32723    // Label 1607: @87653
32724    GIM_Reject,
32725    // Label 1604: @87654
32726    GIM_Reject,
32727    // Label 19: @87655
32728    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1611*/ 88176,
32729    /*GILLT_v2s64*//*Label 1608*/ 87669, 0, 0,
32730    /*GILLT_v4s32*//*Label 1609*/ 87838, 0, 0, 0,
32731    /*GILLT_v8s16*//*Label 1610*/ 88007,
32732    // Label 1608: @87669
32733    GIM_Try, /*On fail goto*//*Label 1612*/ 87837,
32734      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
32735      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32736      GIM_Try, /*On fail goto*//*Label 1613*/ 87742, // Rule ID 1163 //
32737        GIM_CheckFeatures, GIFBS_HasNEON,
32738        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32739        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32740        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32741        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
32742        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
32743        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
32744        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32745        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32746        GIM_CheckIsSafeToFold, /*InsnID*/1,
32747        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
32748        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64,
32749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32752        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32753        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32754        GIR_EraseFromParent, /*InsnID*/0,
32755        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32756        // GIR_Coverage, 1163,
32757        GIR_Done,
32758      // Label 1613: @87742
32759      GIM_Try, /*On fail goto*//*Label 1614*/ 87805, // Rule ID 1166 //
32760        GIM_CheckFeatures, GIFBS_HasNEON,
32761        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32762        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32763        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32764        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
32765        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
32766        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
32767        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32768        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32769        GIM_CheckIsSafeToFold, /*InsnID*/1,
32770        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
32771        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64,
32772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32775        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32776        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32777        GIR_EraseFromParent, /*InsnID*/0,
32778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32779        // GIR_Coverage, 1166,
32780        GIR_Done,
32781      // Label 1614: @87805
32782      GIM_Try, /*On fail goto*//*Label 1615*/ 87836, // Rule ID 1591 //
32783        GIM_CheckFeatures, GIFBS_HasNEON,
32784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32785        // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
32786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
32787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32789        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32790        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32791        GIR_EraseFromParent, /*InsnID*/0,
32792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32793        // GIR_Coverage, 1591,
32794        GIR_Done,
32795      // Label 1615: @87836
32796      GIM_Reject,
32797    // Label 1612: @87837
32798    GIM_Reject,
32799    // Label 1609: @87838
32800    GIM_Try, /*On fail goto*//*Label 1616*/ 88006,
32801      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
32802      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32803      GIM_Try, /*On fail goto*//*Label 1617*/ 87911, // Rule ID 1162 //
32804        GIM_CheckFeatures, GIFBS_HasNEON,
32805        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32806        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32807        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32808        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
32809        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
32810        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
32811        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32812        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32813        GIM_CheckIsSafeToFold, /*InsnID*/1,
32814        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
32815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32,
32816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32819        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32820        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32821        GIR_EraseFromParent, /*InsnID*/0,
32822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32823        // GIR_Coverage, 1162,
32824        GIR_Done,
32825      // Label 1617: @87911
32826      GIM_Try, /*On fail goto*//*Label 1618*/ 87974, // Rule ID 1165 //
32827        GIM_CheckFeatures, GIFBS_HasNEON,
32828        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32829        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32830        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32831        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
32832        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
32833        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
32834        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32835        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32836        GIM_CheckIsSafeToFold, /*InsnID*/1,
32837        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
32838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
32839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32842        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32843        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32844        GIR_EraseFromParent, /*InsnID*/0,
32845        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32846        // GIR_Coverage, 1165,
32847        GIR_Done,
32848      // Label 1618: @87974
32849      GIM_Try, /*On fail goto*//*Label 1619*/ 88005, // Rule ID 1590 //
32850        GIM_CheckFeatures, GIFBS_HasNEON,
32851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32852        // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
32853        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
32854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32857        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32858        GIR_EraseFromParent, /*InsnID*/0,
32859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32860        // GIR_Coverage, 1590,
32861        GIR_Done,
32862      // Label 1619: @88005
32863      GIM_Reject,
32864    // Label 1616: @88006
32865    GIM_Reject,
32866    // Label 1610: @88007
32867    GIM_Try, /*On fail goto*//*Label 1620*/ 88175,
32868      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
32869      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
32870      GIM_Try, /*On fail goto*//*Label 1621*/ 88080, // Rule ID 1161 //
32871        GIM_CheckFeatures, GIFBS_HasNEON,
32872        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32873        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32874        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32875        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
32876        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
32877        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
32878        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32879        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32880        GIM_CheckIsSafeToFold, /*InsnID*/1,
32881        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
32882        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16,
32883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32886        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32887        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32888        GIR_EraseFromParent, /*InsnID*/0,
32889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32890        // GIR_Coverage, 1161,
32891        GIR_Done,
32892      // Label 1621: @88080
32893      GIM_Try, /*On fail goto*//*Label 1622*/ 88143, // Rule ID 1164 //
32894        GIM_CheckFeatures, GIFBS_HasNEON,
32895        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32896        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
32897        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
32898        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
32899        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
32900        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
32901        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
32902        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
32903        GIM_CheckIsSafeToFold, /*InsnID*/1,
32904        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
32905        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
32906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
32908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
32909        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32910        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32911        GIR_EraseFromParent, /*InsnID*/0,
32912        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32913        // GIR_Coverage, 1164,
32914        GIR_Done,
32915      // Label 1622: @88143
32916      GIM_Try, /*On fail goto*//*Label 1623*/ 88174, // Rule ID 1589 //
32917        GIM_CheckFeatures, GIFBS_HasNEON,
32918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
32919        // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
32920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
32921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
32922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
32923        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32924        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32925        GIR_EraseFromParent, /*InsnID*/0,
32926        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32927        // GIR_Coverage, 1589,
32928        GIR_Done,
32929      // Label 1623: @88174
32930      GIM_Reject,
32931    // Label 1620: @88175
32932    GIM_Reject,
32933    // Label 1611: @88176
32934    GIM_Reject,
32935    // Label 20: @88177
32936    GIM_Try, /*On fail goto*//*Label 1624*/ 88285,
32937      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32938      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
32939      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32940      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
32941      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
32942      GIM_Try, /*On fail goto*//*Label 1625*/ 88245, // Rule ID 476 //
32943        GIM_CheckFeatures, GIFBS_IsThumb2,
32944        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
32945        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32946        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31,
32947        // MIs[1] Operand 1
32948        // No operand predicates
32949        GIM_CheckIsSafeToFold, /*InsnID*/1,
32950        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
32951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri,
32952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
32954        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32955        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32956        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32957        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32958        GIR_EraseFromParent, /*InsnID*/0,
32959        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32960        // GIR_Coverage, 476,
32961        GIR_Done,
32962      // Label 1625: @88245
32963      GIM_Try, /*On fail goto*//*Label 1626*/ 88284, // Rule ID 477 //
32964        GIM_CheckFeatures, GIFBS_IsThumb2,
32965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
32966        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
32967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
32968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
32970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
32971        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32972        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32973        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32974        GIR_EraseFromParent, /*InsnID*/0,
32975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32976        // GIR_Coverage, 477,
32977        GIR_Done,
32978      // Label 1626: @88284
32979      GIM_Reject,
32980    // Label 1624: @88285
32981    GIM_Reject,
32982    // Label 21: @88286
32983    GIM_Try, /*On fail goto*//*Label 1627*/ 88345, // Rule ID 479 //
32984      GIM_CheckFeatures, GIFBS_IsThumb2,
32985      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32986      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
32987      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32988      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
32989      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
32990      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
32991      // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
32992      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr,
32993      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
32994      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
32995      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
32996      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32997      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32998      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
32999      GIR_EraseFromParent, /*InsnID*/0,
33000      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33001      // GIR_Coverage, 479,
33002      GIR_Done,
33003    // Label 1627: @88345
33004    GIM_Reject,
33005    // Label 22: @88346
33006    GIM_Try, /*On fail goto*//*Label 1628*/ 88563,
33007      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
33008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33009      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
33010      GIM_Try, /*On fail goto*//*Label 1629*/ 88412, // Rule ID 203 //
33011        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
33012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
33013        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33014        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
33015        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33016        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
33017        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
33018        GIM_CheckIsSafeToFold, /*InsnID*/1,
33019        // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
33020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
33021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
33023        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33024        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33025        GIR_EraseFromParent, /*InsnID*/0,
33026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33027        // GIR_Coverage, 203,
33028        GIR_Done,
33029      // Label 1629: @88412
33030      GIM_Try, /*On fail goto*//*Label 1630*/ 88464, // Rule ID 336 //
33031        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
33032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
33033        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33034        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
33035        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33036        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
33037        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
33038        GIM_CheckIsSafeToFold, /*InsnID*/1,
33039        // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
33040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH,
33041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
33043        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33044        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33045        GIR_EraseFromParent, /*InsnID*/0,
33046        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33047        // GIR_Coverage, 336,
33048        GIR_Done,
33049      // Label 1630: @88464
33050      GIM_Try, /*On fail goto*//*Label 1631*/ 88562,
33051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
33052        GIM_Try, /*On fail goto*//*Label 1632*/ 88518, // Rule ID 544 //
33053          GIM_CheckFeatures, GIFBS_IsThumb2,
33054          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33055          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
33056          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33057          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
33058          GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
33059          GIM_CheckIsSafeToFold, /*InsnID*/1,
33060          // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
33061          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
33062          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33063          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
33064          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33065          GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33066          GIR_EraseFromParent, /*InsnID*/0,
33067          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33068          // GIR_Coverage, 544,
33069          GIR_Done,
33070        // Label 1632: @88518
33071        GIM_Try, /*On fail goto*//*Label 1633*/ 88561, // Rule ID 481 //
33072          GIM_CheckFeatures, GIFBS_IsThumb2,
33073          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
33074          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
33075          // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33076          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr,
33077          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33078          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
33079          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
33080          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33081          GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33082          GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33083          GIR_EraseFromParent, /*InsnID*/0,
33084          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33085          // GIR_Coverage, 481,
33086          GIR_Done,
33087        // Label 1633: @88561
33088        GIM_Reject,
33089      // Label 1631: @88562
33090      GIM_Reject,
33091    // Label 1628: @88563
33092    GIM_Reject,
33093    // Label 23: @88564
33094    GIM_Try, /*On fail goto*//*Label 1634*/ 88665,
33095      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
33096      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33097      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
33098      GIM_Try, /*On fail goto*//*Label 1635*/ 88621, // Rule ID 180 //
33099        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
33100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
33101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
33102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
33103        // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
33104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMUL,
33105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
33107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
33108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33109        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33110        GIR_EraseFromParent, /*InsnID*/0,
33111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33112        // GIR_Coverage, 180,
33113        GIR_Done,
33114      // Label 1635: @88621
33115      GIM_Try, /*On fail goto*//*Label 1636*/ 88664, // Rule ID 513 //
33116        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
33117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
33118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
33119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
33120        // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33121        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMUL,
33122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
33123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
33124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
33125        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33126        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33127        GIR_EraseFromParent, /*InsnID*/0,
33128        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33129        // GIR_Coverage, 513,
33130        GIR_Done,
33131      // Label 1636: @88664
33132      GIM_Reject,
33133    // Label 1634: @88665
33134    GIM_Reject,
33135    // Label 24: @88666
33136    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1644*/ 89435,
33137    /*GILLT_s16*//*Label 1637*/ 88684,
33138    /*GILLT_s32*//*Label 1638*/ 88736,
33139    /*GILLT_s64*//*Label 1639*/ 88788,
33140    /*GILLT_v2s32*//*Label 1640*/ 88840, 0, 0,
33141    /*GILLT_v4s16*//*Label 1641*/ 88892,
33142    /*GILLT_v4s32*//*Label 1642*/ 89075, 0, 0, 0,
33143    /*GILLT_v8s16*//*Label 1643*/ 89187,
33144    // Label 1637: @88684
33145    GIM_Try, /*On fail goto*//*Label 1645*/ 88735, // Rule ID 627 //
33146      GIM_CheckFeatures, GIFBS_HasFullFP16,
33147      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
33148      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
33149      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
33150      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
33151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
33152      // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
33153      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH,
33154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33156      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33157      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33158      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33159      GIR_EraseFromParent, /*InsnID*/0,
33160      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33161      // GIR_Coverage, 627,
33162      GIR_Done,
33163    // Label 1645: @88735
33164    GIM_Reject,
33165    // Label 1638: @88736
33166    GIM_Try, /*On fail goto*//*Label 1646*/ 88787, // Rule ID 626 //
33167      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
33168      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33169      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
33170      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
33171      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33172      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
33173      // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
33174      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS,
33175      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33176      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33177      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33178      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33179      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33180      GIR_EraseFromParent, /*InsnID*/0,
33181      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33182      // GIR_Coverage, 626,
33183      GIR_Done,
33184    // Label 1646: @88787
33185    GIM_Reject,
33186    // Label 1639: @88788
33187    GIM_Try, /*On fail goto*//*Label 1647*/ 88839, // Rule ID 625 //
33188      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
33189      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
33190      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
33191      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33192      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33194      // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
33195      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
33196      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
33197      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
33198      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
33199      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33200      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33201      GIR_EraseFromParent, /*InsnID*/0,
33202      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33203      // GIR_Coverage, 625,
33204      GIR_Done,
33205    // Label 1647: @88839
33206    GIM_Reject,
33207    // Label 1640: @88840
33208    GIM_Try, /*On fail goto*//*Label 1648*/ 88891, // Rule ID 779 //
33209      GIM_CheckFeatures, GIFBS_HasNEON,
33210      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
33211      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
33212      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33213      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33215      // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
33216      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd,
33217      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33218      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33219      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33220      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33221      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33222      GIR_EraseFromParent, /*InsnID*/0,
33223      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33224      // GIR_Coverage, 779,
33225      GIR_Done,
33226    // Label 1648: @88891
33227    GIM_Reject,
33228    // Label 1641: @88892
33229    GIM_Try, /*On fail goto*//*Label 1649*/ 89074,
33230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
33231      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
33232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33233      GIM_Try, /*On fail goto*//*Label 1650*/ 88970, // Rule ID 4302 //
33234        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33235        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33236        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33237        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
33238        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
33239        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33240        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33242        GIM_CheckIsSafeToFold, /*InsnID*/1,
33243        // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33244        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
33245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
33247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33249        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33250        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33251        GIR_EraseFromParent, /*InsnID*/0,
33252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33253        // GIR_Coverage, 4302,
33254        GIR_Done,
33255      // Label 1650: @88970
33256      GIM_Try, /*On fail goto*//*Label 1651*/ 89034, // Rule ID 948 //
33257        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33259        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33260        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33261        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
33262        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
33263        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33264        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33265        GIM_CheckIsSafeToFold, /*InsnID*/1,
33266        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33267        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
33268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33272        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33273        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33274        GIR_EraseFromParent, /*InsnID*/0,
33275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33276        // GIR_Coverage, 948,
33277        GIR_Done,
33278      // Label 1651: @89034
33279      GIM_Try, /*On fail goto*//*Label 1652*/ 89073, // Rule ID 781 //
33280        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33283        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33284        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd,
33285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33288        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33289        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33290        GIR_EraseFromParent, /*InsnID*/0,
33291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33292        // GIR_Coverage, 781,
33293        GIR_Done,
33294      // Label 1652: @89073
33295      GIM_Reject,
33296    // Label 1649: @89074
33297    GIM_Reject,
33298    // Label 1642: @89075
33299    GIM_Try, /*On fail goto*//*Label 1653*/ 89186,
33300      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
33301      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33302      GIM_Try, /*On fail goto*//*Label 1654*/ 89128, // Rule ID 780 //
33303        GIM_CheckFeatures, GIFBS_HasNEON,
33304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33307        // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
33308        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq,
33309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33312        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33313        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33314        GIR_EraseFromParent, /*InsnID*/0,
33315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33316        // GIR_Coverage, 780,
33317        GIR_Done,
33318      // Label 1654: @89128
33319      GIM_Try, /*On fail goto*//*Label 1655*/ 89185, // Rule ID 3384 //
33320        GIM_CheckFeatures, GIFBS_HasMVEFloat,
33321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
33323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33324        // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
33325        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
33326        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
33327        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
33328        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf32,
33329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
33331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
33332        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33333        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33334        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33335        GIR_EraseFromParent, /*InsnID*/0,
33336        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33337        // GIR_Coverage, 3384,
33338        GIR_Done,
33339      // Label 1655: @89185
33340      GIM_Reject,
33341    // Label 1653: @89186
33342    GIM_Reject,
33343    // Label 1643: @89187
33344    GIM_Try, /*On fail goto*//*Label 1656*/ 89434,
33345      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
33346      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33347      GIM_Try, /*On fail goto*//*Label 1657*/ 89265, // Rule ID 4303 //
33348        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33350        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33351        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33352        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
33353        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
33354        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33355        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33357        GIM_CheckIsSafeToFold, /*InsnID*/1,
33358        // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
33360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
33362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33364        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33365        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33366        GIR_EraseFromParent, /*InsnID*/0,
33367        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33368        // GIR_Coverage, 4303,
33369        GIR_Done,
33370      // Label 1657: @89265
33371      GIM_Try, /*On fail goto*//*Label 1658*/ 89333, // Rule ID 949 //
33372        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33375        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33376        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33377        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
33378        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
33379        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33380        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33381        GIM_CheckIsSafeToFold, /*InsnID*/1,
33382        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33383        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
33384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33388        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33389        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33390        GIR_EraseFromParent, /*InsnID*/0,
33391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33392        // GIR_Coverage, 949,
33393        GIR_Done,
33394      // Label 1658: @89333
33395      GIM_Try, /*On fail goto*//*Label 1659*/ 89376, // Rule ID 782 //
33396        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33400        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33401        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq,
33402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33405        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33406        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33407        GIR_EraseFromParent, /*InsnID*/0,
33408        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33409        // GIR_Coverage, 782,
33410        GIR_Done,
33411      // Label 1659: @89376
33412      GIM_Try, /*On fail goto*//*Label 1660*/ 89433, // Rule ID 3386 //
33413        GIM_CheckFeatures, GIFBS_HasMVEFloat,
33414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
33416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33417        // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
33418        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
33419        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
33420        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
33421        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf16,
33422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
33424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
33425        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33426        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33427        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33428        GIR_EraseFromParent, /*InsnID*/0,
33429        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33430        // GIR_Coverage, 3386,
33431        GIR_Done,
33432      // Label 1660: @89433
33433      GIM_Reject,
33434    // Label 1656: @89434
33435    GIM_Reject,
33436    // Label 1644: @89435
33437    GIM_Reject,
33438    // Label 25: @89436
33439    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1668*/ 90197,
33440    /*GILLT_s16*//*Label 1661*/ 89454,
33441    /*GILLT_s32*//*Label 1662*/ 89506,
33442    /*GILLT_s64*//*Label 1663*/ 89558,
33443    /*GILLT_v2s32*//*Label 1664*/ 89610, 0, 0,
33444    /*GILLT_v4s16*//*Label 1665*/ 89662,
33445    /*GILLT_v4s32*//*Label 1666*/ 89837, 0, 0, 0,
33446    /*GILLT_v8s16*//*Label 1667*/ 89949,
33447    // Label 1661: @89454
33448    GIM_Try, /*On fail goto*//*Label 1669*/ 89505, // Rule ID 630 //
33449      GIM_CheckFeatures, GIFBS_HasFullFP16,
33450      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
33451      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
33452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
33453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
33454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
33455      // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
33456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH,
33457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33460      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33461      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33462      GIR_EraseFromParent, /*InsnID*/0,
33463      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33464      // GIR_Coverage, 630,
33465      GIR_Done,
33466    // Label 1669: @89505
33467    GIM_Reject,
33468    // Label 1662: @89506
33469    GIM_Try, /*On fail goto*//*Label 1670*/ 89557, // Rule ID 629 //
33470      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
33471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33472      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
33473      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
33474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
33476      // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
33477      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS,
33478      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33480      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33481      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33482      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33483      GIR_EraseFromParent, /*InsnID*/0,
33484      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33485      // GIR_Coverage, 629,
33486      GIR_Done,
33487    // Label 1670: @89557
33488    GIM_Reject,
33489    // Label 1663: @89558
33490    GIM_Try, /*On fail goto*//*Label 1671*/ 89609, // Rule ID 628 //
33491      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
33492      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
33493      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
33494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33497      // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
33498      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD,
33499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
33500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
33501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
33502      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33503      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33504      GIR_EraseFromParent, /*InsnID*/0,
33505      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33506      // GIR_Coverage, 628,
33507      GIR_Done,
33508    // Label 1671: @89609
33509    GIM_Reject,
33510    // Label 1664: @89610
33511    GIM_Try, /*On fail goto*//*Label 1672*/ 89661, // Rule ID 966 //
33512      GIM_CheckFeatures, GIFBS_HasNEON,
33513      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
33514      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
33515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33517      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33518      // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
33519      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd,
33520      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33521      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33522      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33523      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33524      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33525      GIR_EraseFromParent, /*InsnID*/0,
33526      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33527      // GIR_Coverage, 966,
33528      GIR_Done,
33529    // Label 1672: @89661
33530    GIM_Reject,
33531    // Label 1665: @89662
33532    GIM_Try, /*On fail goto*//*Label 1673*/ 89836,
33533      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
33534      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
33535      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33537      GIM_Try, /*On fail goto*//*Label 1674*/ 89740, // Rule ID 926 //
33538        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
33539        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33540        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33541        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
33542        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
33543        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33544        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33545        GIM_CheckIsSafeToFold, /*InsnID*/1,
33546        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33547        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd,
33548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33552        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33553        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33554        GIR_EraseFromParent, /*InsnID*/0,
33555        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33556        // GIR_Coverage, 926,
33557        GIR_Done,
33558      // Label 1674: @89740
33559      GIM_Try, /*On fail goto*//*Label 1675*/ 89800, // Rule ID 952 //
33560        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33561        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33562        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33563        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
33564        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
33565        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33566        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33567        GIM_CheckIsSafeToFold, /*InsnID*/1,
33568        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33569        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd,
33570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33574        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33575        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33576        GIR_EraseFromParent, /*InsnID*/0,
33577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33578        // GIR_Coverage, 952,
33579        GIR_Done,
33580      // Label 1675: @89800
33581      GIM_Try, /*On fail goto*//*Label 1676*/ 89835, // Rule ID 968 //
33582        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33584        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd,
33586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33589        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33590        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33591        GIR_EraseFromParent, /*InsnID*/0,
33592        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33593        // GIR_Coverage, 968,
33594        GIR_Done,
33595      // Label 1676: @89835
33596      GIM_Reject,
33597    // Label 1673: @89836
33598    GIM_Reject,
33599    // Label 1666: @89837
33600    GIM_Try, /*On fail goto*//*Label 1677*/ 89948,
33601      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
33602      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33603      GIM_Try, /*On fail goto*//*Label 1678*/ 89890, // Rule ID 967 //
33604        GIM_CheckFeatures, GIFBS_HasNEON,
33605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33608        // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
33609        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq,
33610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33613        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33614        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33615        GIR_EraseFromParent, /*InsnID*/0,
33616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33617        // GIR_Coverage, 967,
33618        GIR_Done,
33619      // Label 1678: @89890
33620      GIM_Try, /*On fail goto*//*Label 1679*/ 89947, // Rule ID 3388 //
33621        GIM_CheckFeatures, GIFBS_HasMVEFloat,
33622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
33624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33625        // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
33626        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
33627        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
33628        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
33629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf32,
33630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
33632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
33633        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33634        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33635        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33636        GIR_EraseFromParent, /*InsnID*/0,
33637        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33638        // GIR_Coverage, 3388,
33639        GIR_Done,
33640      // Label 1679: @89947
33641      GIM_Reject,
33642    // Label 1677: @89948
33643    GIM_Reject,
33644    // Label 1667: @89949
33645    GIM_Try, /*On fail goto*//*Label 1680*/ 90196,
33646      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
33647      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33648      GIM_Try, /*On fail goto*//*Label 1681*/ 90027, // Rule ID 927 //
33649        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
33650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33652        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33653        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33654        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
33655        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
33656        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33657        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33658        GIM_CheckIsSafeToFold, /*InsnID*/1,
33659        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq,
33661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33665        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33666        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33667        GIR_EraseFromParent, /*InsnID*/0,
33668        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33669        // GIR_Coverage, 927,
33670        GIR_Done,
33671      // Label 1681: @90027
33672      GIM_Try, /*On fail goto*//*Label 1682*/ 90095, // Rule ID 953 //
33673        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
33674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33676        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33677        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
33678        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
33679        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
33680        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33681        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33682        GIM_CheckIsSafeToFold, /*InsnID*/1,
33683        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33684        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq,
33685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
33687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
33688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
33689        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33690        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33691        GIR_EraseFromParent, /*InsnID*/0,
33692        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33693        // GIR_Coverage, 953,
33694        GIR_Done,
33695      // Label 1682: @90095
33696      GIM_Try, /*On fail goto*//*Label 1683*/ 90138, // Rule ID 969 //
33697        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33701        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33702        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq,
33703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33706        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33707        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33708        GIR_EraseFromParent, /*InsnID*/0,
33709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33710        // GIR_Coverage, 969,
33711        GIR_Done,
33712      // Label 1683: @90138
33713      GIM_Try, /*On fail goto*//*Label 1684*/ 90195, // Rule ID 3390 //
33714        GIM_CheckFeatures, GIFBS_HasMVEFloat,
33715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
33717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33718        // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
33719        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
33720        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
33721        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
33722        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf16,
33723        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
33725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
33726        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33727        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33728        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33729        GIR_EraseFromParent, /*InsnID*/0,
33730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33731        // GIR_Coverage, 3390,
33732        GIR_Done,
33733      // Label 1684: @90195
33734      GIM_Reject,
33735    // Label 1680: @90196
33736    GIM_Reject,
33737    // Label 1668: @90197
33738    GIM_Reject,
33739    // Label 26: @90198
33740    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1692*/ 90914,
33741    /*GILLT_s16*//*Label 1685*/ 90216,
33742    /*GILLT_s32*//*Label 1686*/ 90268,
33743    /*GILLT_s64*//*Label 1687*/ 90427,
33744    /*GILLT_v2s32*//*Label 1688*/ 90586, 0, 0,
33745    /*GILLT_v4s16*//*Label 1689*/ 90638,
33746    /*GILLT_v4s32*//*Label 1690*/ 90690, 0, 0, 0,
33747    /*GILLT_v8s16*//*Label 1691*/ 90802,
33748    // Label 1685: @90216
33749    GIM_Try, /*On fail goto*//*Label 1693*/ 90267, // Rule ID 636 //
33750      GIM_CheckFeatures, GIFBS_HasFullFP16,
33751      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
33752      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
33753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
33754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
33755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
33756      // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
33757      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH,
33758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33761      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33762      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33763      GIR_EraseFromParent, /*InsnID*/0,
33764      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33765      // GIR_Coverage, 636,
33766      GIR_Done,
33767    // Label 1693: @90267
33768    GIM_Reject,
33769    // Label 1686: @90268
33770    GIM_Try, /*On fail goto*//*Label 1694*/ 90426,
33771      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33772      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
33773      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
33774      GIM_Try, /*On fail goto*//*Label 1695*/ 90334, // Rule ID 2238 //
33775        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
33776        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33777        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
33778        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33779        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
33781        GIM_CheckIsSafeToFold, /*InsnID*/1,
33782        // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b)  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
33783        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
33784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
33786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
33787        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33788        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33789        GIR_EraseFromParent, /*InsnID*/0,
33790        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33791        // GIR_Coverage, 2238,
33792        GIR_Done,
33793      // Label 1695: @90334
33794      GIM_Try, /*On fail goto*//*Label 1696*/ 90386, // Rule ID 4428 //
33795        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
33796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33797        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33798        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
33799        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33800        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33801        GIM_CheckIsSafeToFold, /*InsnID*/1,
33802        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
33803        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
33804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
33806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
33807        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33808        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33809        GIR_EraseFromParent, /*InsnID*/0,
33810        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33811        // GIR_Coverage, 4428,
33812        GIR_Done,
33813      // Label 1696: @90386
33814      GIM_Try, /*On fail goto*//*Label 1697*/ 90425, // Rule ID 635 //
33815        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
33816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
33817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
33818        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
33819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS,
33820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
33821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
33822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
33823        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33824        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33825        GIR_EraseFromParent, /*InsnID*/0,
33826        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33827        // GIR_Coverage, 635,
33828        GIR_Done,
33829      // Label 1697: @90425
33830      GIM_Reject,
33831    // Label 1694: @90426
33832    GIM_Reject,
33833    // Label 1687: @90427
33834    GIM_Try, /*On fail goto*//*Label 1698*/ 90585,
33835      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
33836      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
33837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33838      GIM_Try, /*On fail goto*//*Label 1699*/ 90493, // Rule ID 2237 //
33839        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
33840        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33841        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
33842        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
33843        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33845        GIM_CheckIsSafeToFold, /*InsnID*/1,
33846        // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b)  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
33847        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
33848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
33849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
33850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
33851        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33852        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33853        GIR_EraseFromParent, /*InsnID*/0,
33854        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33855        // GIR_Coverage, 2237,
33856        GIR_Done,
33857      // Label 1699: @90493
33858      GIM_Try, /*On fail goto*//*Label 1700*/ 90545, // Rule ID 4427 //
33859        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
33860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33861        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33862        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
33863        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
33864        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33865        GIM_CheckIsSafeToFold, /*InsnID*/1,
33866        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
33867        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
33868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
33869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
33870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
33871        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33872        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33873        GIR_EraseFromParent, /*InsnID*/0,
33874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33875        // GIR_Coverage, 4427,
33876        GIR_Done,
33877      // Label 1700: @90545
33878      GIM_Try, /*On fail goto*//*Label 1701*/ 90584, // Rule ID 634 //
33879        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
33880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33882        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
33883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD,
33884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
33885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
33886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
33887        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33888        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33889        GIR_EraseFromParent, /*InsnID*/0,
33890        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33891        // GIR_Coverage, 634,
33892        GIR_Done,
33893      // Label 1701: @90584
33894      GIM_Reject,
33895    // Label 1698: @90585
33896    GIM_Reject,
33897    // Label 1688: @90586
33898    GIM_Try, /*On fail goto*//*Label 1702*/ 90637, // Rule ID 846 //
33899      GIM_CheckFeatures, GIFBS_HasNEON,
33900      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
33901      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
33902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33904      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33905      // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
33906      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd,
33907      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33908      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33909      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33910      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33911      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33912      GIR_EraseFromParent, /*InsnID*/0,
33913      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33914      // GIR_Coverage, 846,
33915      GIR_Done,
33916    // Label 1702: @90637
33917    GIM_Reject,
33918    // Label 1689: @90638
33919    GIM_Try, /*On fail goto*//*Label 1703*/ 90689, // Rule ID 848 //
33920      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33921      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
33922      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
33923      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
33925      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
33926      // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
33927      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd,
33928      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33929      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33930      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33931      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33932      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33933      GIR_EraseFromParent, /*InsnID*/0,
33934      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33935      // GIR_Coverage, 848,
33936      GIR_Done,
33937    // Label 1703: @90689
33938    GIM_Reject,
33939    // Label 1690: @90690
33940    GIM_Try, /*On fail goto*//*Label 1704*/ 90801,
33941      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
33942      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33943      GIM_Try, /*On fail goto*//*Label 1705*/ 90743, // Rule ID 847 //
33944        GIM_CheckFeatures, GIFBS_HasNEON,
33945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33948        // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
33949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq,
33950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33953        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33954        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33955        GIR_EraseFromParent, /*InsnID*/0,
33956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33957        // GIR_Coverage, 847,
33958        GIR_Done,
33959      // Label 1705: @90743
33960      GIM_Try, /*On fail goto*//*Label 1706*/ 90800, // Rule ID 3372 //
33961        GIM_CheckFeatures, GIFBS_HasMVEFloat,
33962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
33964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33965        // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
33966        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
33967        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
33968        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
33969        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf32,
33970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
33972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
33973        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33974        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
33975        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33976        GIR_EraseFromParent, /*InsnID*/0,
33977        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33978        // GIR_Coverage, 3372,
33979        GIR_Done,
33980      // Label 1706: @90800
33981      GIM_Reject,
33982    // Label 1704: @90801
33983    GIM_Reject,
33984    // Label 1691: @90802
33985    GIM_Try, /*On fail goto*//*Label 1707*/ 90913,
33986      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
33987      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33988      GIM_Try, /*On fail goto*//*Label 1708*/ 90855, // Rule ID 849 //
33989        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
33990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
33991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
33992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
33993        // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
33994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq,
33995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
33996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
33997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
33998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33999        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34000        GIR_EraseFromParent, /*InsnID*/0,
34001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34002        // GIR_Coverage, 849,
34003        GIR_Done,
34004      // Label 1708: @90855
34005      GIM_Try, /*On fail goto*//*Label 1709*/ 90912, // Rule ID 3374 //
34006        GIM_CheckFeatures, GIFBS_HasMVEFloat,
34007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
34009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34010        // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
34011        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
34012        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
34013        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
34014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf16,
34015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
34017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
34018        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34019        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34020        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
34021        GIR_EraseFromParent, /*InsnID*/0,
34022        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34023        // GIR_Coverage, 3374,
34024        GIR_Done,
34025      // Label 1709: @90912
34026      GIM_Reject,
34027    // Label 1707: @90913
34028    GIM_Reject,
34029    // Label 1692: @90914
34030    GIM_Reject,
34031    // Label 27: @90915
34032    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1717*/ 92275,
34033    /*GILLT_s16*//*Label 1710*/ 90933,
34034    /*GILLT_s32*//*Label 1711*/ 91253,
34035    /*GILLT_s64*//*Label 1712*/ 91573,
34036    /*GILLT_v2s32*//*Label 1713*/ 91893, 0, 0,
34037    /*GILLT_v4s16*//*Label 1714*/ 92020,
34038    /*GILLT_v4s32*//*Label 1715*/ 92084, 0, 0, 0,
34039    /*GILLT_v8s16*//*Label 1716*/ 92211,
34040    // Label 1710: @90933
34041    GIM_Try, /*On fail goto*//*Label 1718*/ 91252,
34042      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
34043      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
34044      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
34045      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
34046      GIM_Try, /*On fail goto*//*Label 1719*/ 91024, // Rule ID 2327 //
34047        GIM_CheckFeatures, GIFBS_HasFullFP16,
34048        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34049        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34050        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34051        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34053        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
34054        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34055        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
34056        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34057        GIM_CheckIsSafeToFold, /*InsnID*/1,
34058        GIM_CheckIsSafeToFold, /*InsnID*/2,
34059        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
34061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
34063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34066        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34067        GIR_EraseFromParent, /*InsnID*/0,
34068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34069        // GIR_Coverage, 2327,
34070        GIR_Done,
34071      // Label 1719: @91024
34072      GIM_Try, /*On fail goto*//*Label 1720*/ 91084, // Rule ID 2316 //
34073        GIM_CheckFeatures, GIFBS_HasFullFP16,
34074        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34075        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34076        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34077        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34080        GIM_CheckIsSafeToFold, /*InsnID*/1,
34081        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34082        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
34083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34088        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34089        GIR_EraseFromParent, /*InsnID*/0,
34090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34091        // GIR_Coverage, 2316,
34092        GIR_Done,
34093      // Label 1720: @91084
34094      GIM_Try, /*On fail goto*//*Label 1721*/ 91144, // Rule ID 2319 //
34095        GIM_CheckFeatures, GIFBS_HasFullFP16,
34096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34097        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34098        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34099        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34100        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34102        GIM_CheckIsSafeToFold, /*InsnID*/1,
34103        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm), HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
34105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
34109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34110        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34111        GIR_EraseFromParent, /*InsnID*/0,
34112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34113        // GIR_Coverage, 2319,
34114        GIR_Done,
34115      // Label 1721: @91144
34116      GIM_Try, /*On fail goto*//*Label 1722*/ 91204, // Rule ID 2332 //
34117        GIM_CheckFeatures, GIFBS_HasFullFP16,
34118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34120        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34121        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34122        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34123        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34124        GIM_CheckIsSafeToFold, /*InsnID*/1,
34125        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
34127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
34129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34131        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34132        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34133        GIR_EraseFromParent, /*InsnID*/0,
34134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34135        // GIR_Coverage, 2332,
34136        GIR_Done,
34137      // Label 1722: @91204
34138      GIM_Try, /*On fail goto*//*Label 1723*/ 91251, // Rule ID 2310 //
34139        GIM_CheckFeatures, GIFBS_HasFullFP16,
34140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34143        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34144        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAH,
34145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34149        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34150        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34151        GIR_EraseFromParent, /*InsnID*/0,
34152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34153        // GIR_Coverage, 2310,
34154        GIR_Done,
34155      // Label 1723: @91251
34156      GIM_Reject,
34157    // Label 1718: @91252
34158    GIM_Reject,
34159    // Label 1711: @91253
34160    GIM_Try, /*On fail goto*//*Label 1724*/ 91572,
34161      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34162      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34163      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34164      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
34165      GIM_Try, /*On fail goto*//*Label 1725*/ 91344, // Rule ID 2326 //
34166        GIM_CheckFeatures, GIFBS_HasVFP4,
34167        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34168        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34169        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34170        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34172        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
34173        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34174        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
34175        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34176        GIM_CheckIsSafeToFold, /*InsnID*/1,
34177        GIM_CheckIsSafeToFold, /*InsnID*/2,
34178        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34179        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
34180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
34182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34184        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34185        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34186        GIR_EraseFromParent, /*InsnID*/0,
34187        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34188        // GIR_Coverage, 2326,
34189        GIR_Done,
34190      // Label 1725: @91344
34191      GIM_Try, /*On fail goto*//*Label 1726*/ 91404, // Rule ID 2315 //
34192        GIM_CheckFeatures, GIFBS_HasVFP4,
34193        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34194        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34195        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34196        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34199        GIM_CheckIsSafeToFold, /*InsnID*/1,
34200        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34201        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
34202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34206        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34207        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34208        GIR_EraseFromParent, /*InsnID*/0,
34209        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34210        // GIR_Coverage, 2315,
34211        GIR_Done,
34212      // Label 1726: @91404
34213      GIM_Try, /*On fail goto*//*Label 1727*/ 91464, // Rule ID 2318 //
34214        GIM_CheckFeatures, GIFBS_HasVFP4,
34215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34216        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34217        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34218        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34219        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34221        GIM_CheckIsSafeToFold, /*InsnID*/1,
34222        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34223        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
34224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
34228        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34229        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34230        GIR_EraseFromParent, /*InsnID*/0,
34231        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34232        // GIR_Coverage, 2318,
34233        GIR_Done,
34234      // Label 1727: @91464
34235      GIM_Try, /*On fail goto*//*Label 1728*/ 91524, // Rule ID 2331 //
34236        GIM_CheckFeatures, GIFBS_HasVFP4,
34237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34239        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34240        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34241        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34242        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34243        GIM_CheckIsSafeToFold, /*InsnID*/1,
34244        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34245        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
34246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
34248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34250        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34251        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34252        GIR_EraseFromParent, /*InsnID*/0,
34253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34254        // GIR_Coverage, 2331,
34255        GIR_Done,
34256      // Label 1728: @91524
34257      GIM_Try, /*On fail goto*//*Label 1729*/ 91571, // Rule ID 2309 //
34258        GIM_CheckFeatures, GIFBS_HasVFP4,
34259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34262        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34263        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
34264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
34266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34268        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34269        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34270        GIR_EraseFromParent, /*InsnID*/0,
34271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34272        // GIR_Coverage, 2309,
34273        GIR_Done,
34274      // Label 1729: @91571
34275      GIM_Reject,
34276    // Label 1724: @91572
34277    GIM_Reject,
34278    // Label 1712: @91573
34279    GIM_Try, /*On fail goto*//*Label 1730*/ 91892,
34280      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
34281      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
34282      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
34283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34284      GIM_Try, /*On fail goto*//*Label 1731*/ 91664, // Rule ID 2325 //
34285        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34286        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34287        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34288        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34289        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34291        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
34292        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34293        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
34294        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34295        GIM_CheckIsSafeToFold, /*InsnID*/1,
34296        GIM_CheckIsSafeToFold, /*InsnID*/2,
34297        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
34299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
34301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
34302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
34303        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34304        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34305        GIR_EraseFromParent, /*InsnID*/0,
34306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34307        // GIR_Coverage, 2325,
34308        GIR_Done,
34309      // Label 1731: @91664
34310      GIM_Try, /*On fail goto*//*Label 1732*/ 91724, // Rule ID 2314 //
34311        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34312        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34313        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34314        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34315        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34318        GIM_CheckIsSafeToFold, /*InsnID*/1,
34319        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
34321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
34323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
34324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
34325        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34326        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34327        GIR_EraseFromParent, /*InsnID*/0,
34328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34329        // GIR_Coverage, 2314,
34330        GIR_Done,
34331      // Label 1732: @91724
34332      GIM_Try, /*On fail goto*//*Label 1733*/ 91784, // Rule ID 2317 //
34333        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34335        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34336        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34337        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34338        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34340        GIM_CheckIsSafeToFold, /*InsnID*/1,
34341        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34342        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
34343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
34345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
34346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
34347        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34348        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34349        GIR_EraseFromParent, /*InsnID*/0,
34350        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34351        // GIR_Coverage, 2317,
34352        GIR_Done,
34353      // Label 1733: @91784
34354      GIM_Try, /*On fail goto*//*Label 1734*/ 91844, // Rule ID 2330 //
34355        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34358        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34359        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34360        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34361        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34362        GIM_CheckIsSafeToFold, /*InsnID*/1,
34363        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34364        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
34365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
34367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
34368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
34369        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34370        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34371        GIR_EraseFromParent, /*InsnID*/0,
34372        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34373        // GIR_Coverage, 2330,
34374        GIR_Done,
34375      // Label 1734: @91844
34376      GIM_Try, /*On fail goto*//*Label 1735*/ 91891, // Rule ID 2308 //
34377        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34381        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
34383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
34385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
34386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
34387        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34388        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34389        GIR_EraseFromParent, /*InsnID*/0,
34390        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34391        // GIR_Coverage, 2308,
34392        GIR_Done,
34393      // Label 1735: @91891
34394      GIM_Reject,
34395    // Label 1730: @91892
34396    GIM_Reject,
34397    // Label 1713: @91893
34398    GIM_Try, /*On fail goto*//*Label 1736*/ 92019,
34399      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
34400      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
34401      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
34402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34403      GIM_Try, /*On fail goto*//*Label 1737*/ 91971, // Rule ID 2418 //
34404        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
34405        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34406        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34407        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
34408        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34411        GIM_CheckIsSafeToFold, /*InsnID*/1,
34412        // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
34413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
34414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
34417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34418        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34419        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34420        GIR_EraseFromParent, /*InsnID*/0,
34421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34422        // GIR_Coverage, 2418,
34423        GIR_Done,
34424      // Label 1737: @91971
34425      GIM_Try, /*On fail goto*//*Label 1738*/ 92018, // Rule ID 2416 //
34426        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
34427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34430        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
34431        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
34432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
34435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34436        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34437        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34438        GIR_EraseFromParent, /*InsnID*/0,
34439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34440        // GIR_Coverage, 2416,
34441        GIR_Done,
34442      // Label 1738: @92018
34443      GIM_Reject,
34444    // Label 1736: @92019
34445    GIM_Reject,
34446    // Label 1714: @92020
34447    GIM_Try, /*On fail goto*//*Label 1739*/ 92083, // Rule ID 2414 //
34448      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
34449      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
34450      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
34451      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
34452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34455      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34456      // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
34457      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
34458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34460      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
34461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34462      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34463      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34464      GIR_EraseFromParent, /*InsnID*/0,
34465      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34466      // GIR_Coverage, 2414,
34467      GIR_Done,
34468    // Label 1739: @92083
34469    GIM_Reject,
34470    // Label 1715: @92084
34471    GIM_Try, /*On fail goto*//*Label 1740*/ 92210,
34472      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
34473      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
34474      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
34476      GIM_Try, /*On fail goto*//*Label 1741*/ 92162, // Rule ID 2419 //
34477        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
34478        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34479        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
34480        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
34481        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
34482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
34483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
34484        GIM_CheckIsSafeToFold, /*InsnID*/1,
34485        // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
34486        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
34487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
34490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34491        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34492        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34493        GIR_EraseFromParent, /*InsnID*/0,
34494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34495        // GIR_Coverage, 2419,
34496        GIR_Done,
34497      // Label 1741: @92162
34498      GIM_Try, /*On fail goto*//*Label 1742*/ 92209, // Rule ID 2417 //
34499        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
34500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
34501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
34502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
34503        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
34504        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
34505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
34508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34509        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34510        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34511        GIR_EraseFromParent, /*InsnID*/0,
34512        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34513        // GIR_Coverage, 2417,
34514        GIR_Done,
34515      // Label 1742: @92209
34516      GIM_Reject,
34517    // Label 1740: @92210
34518    GIM_Reject,
34519    // Label 1716: @92211
34520    GIM_Try, /*On fail goto*//*Label 1743*/ 92274, // Rule ID 2415 //
34521      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
34522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
34523      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34524      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34525      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
34526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
34527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
34528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
34529      // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
34530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
34531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
34533      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
34534      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
34535      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34536      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34537      GIR_EraseFromParent, /*InsnID*/0,
34538      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34539      // GIR_Coverage, 2415,
34540      GIR_Done,
34541    // Label 1743: @92274
34542    GIM_Reject,
34543    // Label 1717: @92275
34544    GIM_Reject,
34545    // Label 28: @92276
34546    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 1747*/ 92441,
34547    /*GILLT_s16*//*Label 1744*/ 92285,
34548    /*GILLT_s32*//*Label 1745*/ 92337,
34549    /*GILLT_s64*//*Label 1746*/ 92389,
34550    // Label 1744: @92285
34551    GIM_Try, /*On fail goto*//*Label 1748*/ 92336, // Rule ID 633 //
34552      GIM_CheckFeatures, GIFBS_HasFullFP16,
34553      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
34554      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
34555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
34556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34558      // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH,
34560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34562      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34563      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34564      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34565      GIR_EraseFromParent, /*InsnID*/0,
34566      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34567      // GIR_Coverage, 633,
34568      GIR_Done,
34569    // Label 1748: @92336
34570    GIM_Reject,
34571    // Label 1745: @92337
34572    GIM_Try, /*On fail goto*//*Label 1749*/ 92388, // Rule ID 632 //
34573      GIM_CheckFeatures, GIFBS_HasVFP2,
34574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34575      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
34577      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34578      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34579      // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34580      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS,
34581      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34582      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
34583      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
34584      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34585      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34586      GIR_EraseFromParent, /*InsnID*/0,
34587      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34588      // GIR_Coverage, 632,
34589      GIR_Done,
34590    // Label 1749: @92388
34591    GIM_Reject,
34592    // Label 1746: @92389
34593    GIM_Try, /*On fail goto*//*Label 1750*/ 92440, // Rule ID 631 //
34594      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
34595      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
34596      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
34597      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34600      // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34601      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD,
34602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
34604      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
34605      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34606      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34607      GIR_EraseFromParent, /*InsnID*/0,
34608      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34609      // GIR_Coverage, 631,
34610      GIR_Done,
34611    // Label 1750: @92440
34612    GIM_Reject,
34613    // Label 1747: @92441
34614    GIM_Reject,
34615    // Label 29: @92442
34616    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1758*/ 93711,
34617    /*GILLT_s16*//*Label 1751*/ 92460,
34618    /*GILLT_s32*//*Label 1752*/ 92789,
34619    /*GILLT_s64*//*Label 1753*/ 93118,
34620    /*GILLT_v2s32*//*Label 1754*/ 93447, 0, 0,
34621    /*GILLT_v4s16*//*Label 1755*/ 93487,
34622    /*GILLT_v4s32*//*Label 1756*/ 93527, 0, 0, 0,
34623    /*GILLT_v8s16*//*Label 1757*/ 93619,
34624    // Label 1751: @92460
34625    GIM_Try, /*On fail goto*//*Label 1759*/ 92788,
34626      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
34627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
34628      GIM_Try, /*On fail goto*//*Label 1760*/ 92551, // Rule ID 2335 //
34629        GIM_CheckFeatures, GIFBS_HasFullFP16,
34630        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34631        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34632        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34633        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
34634        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
34635        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
34636        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34637        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
34638        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34639        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34640        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34641        GIM_CheckIsSafeToFold, /*InsnID*/1,
34642        GIM_CheckIsSafeToFold, /*InsnID*/2,
34643        // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34644        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
34645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
34648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34649        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34650        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34651        GIR_EraseFromParent, /*InsnID*/0,
34652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34653        // GIR_Coverage, 2335,
34654        GIR_Done,
34655      // Label 1760: @92551
34656      GIM_Try, /*On fail goto*//*Label 1761*/ 92632, // Rule ID 2338 //
34657        GIM_CheckFeatures, GIFBS_HasFullFP16,
34658        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34659        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34660        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34661        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
34662        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
34663        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34664        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34665        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34666        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
34667        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34668        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34669        GIM_CheckIsSafeToFold, /*InsnID*/1,
34670        GIM_CheckIsSafeToFold, /*InsnID*/2,
34671        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm), HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
34673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sm
34677        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34678        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34679        GIR_EraseFromParent, /*InsnID*/0,
34680        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34681        // GIR_Coverage, 2338,
34682        GIR_Done,
34683      // Label 1761: @92632
34684      GIM_Try, /*On fail goto*//*Label 1762*/ 92700, // Rule ID 2324 //
34685        GIM_CheckFeatures, GIFBS_HasFullFP16,
34686        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34687        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34688        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34689        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
34690        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
34691        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34692        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34693        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
34694        GIM_CheckIsSafeToFold, /*InsnID*/1,
34695        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34696        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
34697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34701        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34702        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34703        GIR_EraseFromParent, /*InsnID*/0,
34704        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34705        // GIR_Coverage, 2324,
34706        GIR_Done,
34707      // Label 1762: @92700
34708      GIM_Try, /*On fail goto*//*Label 1763*/ 92756, // Rule ID 639 //
34709        GIM_CheckFeatures, GIFBS_HasFullFP16,
34710        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34711        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
34712        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
34713        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
34714        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34715        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
34716        GIM_CheckIsSafeToFold, /*InsnID*/1,
34717        // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm))  =>  (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
34718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH,
34719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34722        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34723        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34724        GIR_EraseFromParent, /*InsnID*/0,
34725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34726        // GIR_Coverage, 639,
34727        GIR_Done,
34728      // Label 1763: @92756
34729      GIM_Try, /*On fail goto*//*Label 1764*/ 92787, // Rule ID 677 //
34730        GIM_CheckFeatures, GIFBS_HasFullFP16,
34731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
34732        // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
34733        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH,
34734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
34736        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34737        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34738        GIR_EraseFromParent, /*InsnID*/0,
34739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34740        // GIR_Coverage, 677,
34741        GIR_Done,
34742      // Label 1764: @92787
34743      GIM_Reject,
34744    // Label 1759: @92788
34745    GIM_Reject,
34746    // Label 1752: @92789
34747    GIM_Try, /*On fail goto*//*Label 1765*/ 93117,
34748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34749      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
34750      GIM_Try, /*On fail goto*//*Label 1766*/ 92880, // Rule ID 2334 //
34751        GIM_CheckFeatures, GIFBS_HasVFP4,
34752        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34753        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34754        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34755        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34756        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34757        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
34758        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34759        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
34760        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34761        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34762        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34763        GIM_CheckIsSafeToFold, /*InsnID*/1,
34764        GIM_CheckIsSafeToFold, /*InsnID*/2,
34765        // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34766        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
34767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
34770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34771        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34772        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34773        GIR_EraseFromParent, /*InsnID*/0,
34774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34775        // GIR_Coverage, 2334,
34776        GIR_Done,
34777      // Label 1766: @92880
34778      GIM_Try, /*On fail goto*//*Label 1767*/ 92961, // Rule ID 2337 //
34779        GIM_CheckFeatures, GIFBS_HasVFP4,
34780        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34781        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34782        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34783        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34784        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34785        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34786        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34787        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34788        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
34789        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34790        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34791        GIM_CheckIsSafeToFold, /*InsnID*/1,
34792        GIM_CheckIsSafeToFold, /*InsnID*/2,
34793        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
34795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sm
34799        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34800        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34801        GIR_EraseFromParent, /*InsnID*/0,
34802        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34803        // GIR_Coverage, 2337,
34804        GIR_Done,
34805      // Label 1767: @92961
34806      GIM_Try, /*On fail goto*//*Label 1768*/ 93029, // Rule ID 2323 //
34807        GIM_CheckFeatures, GIFBS_HasVFP4,
34808        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34809        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34810        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34811        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34812        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34813        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34814        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34815        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
34816        GIM_CheckIsSafeToFold, /*InsnID*/1,
34817        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
34819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
34821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34823        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34824        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34825        GIR_EraseFromParent, /*InsnID*/0,
34826        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34827        // GIR_Coverage, 2323,
34828        GIR_Done,
34829      // Label 1768: @93029
34830      GIM_Try, /*On fail goto*//*Label 1769*/ 93085, // Rule ID 638 //
34831        GIM_CheckFeatures, GIFBS_HasVFP2,
34832        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34833        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
34834        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
34835        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34836        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34837        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
34838        GIM_CheckIsSafeToFold, /*InsnID*/1,
34839        // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
34840        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
34841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
34843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
34844        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34845        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34846        GIR_EraseFromParent, /*InsnID*/0,
34847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34848        // GIR_Coverage, 638,
34849        GIR_Done,
34850      // Label 1769: @93085
34851      GIM_Try, /*On fail goto*//*Label 1770*/ 93116, // Rule ID 676 //
34852        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
34853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
34854        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
34855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS,
34856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
34857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
34858        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34859        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34860        GIR_EraseFromParent, /*InsnID*/0,
34861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34862        // GIR_Coverage, 676,
34863        GIR_Done,
34864      // Label 1770: @93116
34865      GIM_Reject,
34866    // Label 1765: @93117
34867    GIM_Reject,
34868    // Label 1753: @93118
34869    GIM_Try, /*On fail goto*//*Label 1771*/ 93446,
34870      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
34871      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34872      GIM_Try, /*On fail goto*//*Label 1772*/ 93209, // Rule ID 2333 //
34873        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34874        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34875        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34876        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34877        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34878        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34879        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
34880        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34881        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
34882        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34883        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34884        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34885        GIM_CheckIsSafeToFold, /*InsnID*/1,
34886        GIM_CheckIsSafeToFold, /*InsnID*/2,
34887        // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
34889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
34891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
34892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
34893        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34894        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34895        GIR_EraseFromParent, /*InsnID*/0,
34896        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34897        // GIR_Coverage, 2333,
34898        GIR_Done,
34899      // Label 1772: @93209
34900      GIM_Try, /*On fail goto*//*Label 1773*/ 93290, // Rule ID 2336 //
34901        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34902        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34903        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34904        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34905        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34906        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34907        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34908        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34909        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
34910        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
34911        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34912        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34913        GIM_CheckIsSafeToFold, /*InsnID*/1,
34914        GIM_CheckIsSafeToFold, /*InsnID*/2,
34915        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34916        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
34917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
34919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
34920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dm
34921        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34922        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34923        GIR_EraseFromParent, /*InsnID*/0,
34924        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34925        // GIR_Coverage, 2336,
34926        GIR_Done,
34927      // Label 1773: @93290
34928      GIM_Try, /*On fail goto*//*Label 1774*/ 93358, // Rule ID 2322 //
34929        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
34930        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34931        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
34932        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34933        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34934        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34935        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34936        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34937        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
34938        GIM_CheckIsSafeToFold, /*InsnID*/1,
34939        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
34941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
34943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
34944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
34945        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34946        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34947        GIR_EraseFromParent, /*InsnID*/0,
34948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34949        // GIR_Coverage, 2322,
34950        GIR_Done,
34951      // Label 1774: @93358
34952      GIM_Try, /*On fail goto*//*Label 1775*/ 93414, // Rule ID 637 //
34953        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
34954        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34955        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
34956        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34957        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34958        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34959        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
34960        GIM_CheckIsSafeToFold, /*InsnID*/1,
34961        // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
34962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
34963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
34965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
34966        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34967        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34968        GIR_EraseFromParent, /*InsnID*/0,
34969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34970        // GIR_Coverage, 637,
34971        GIR_Done,
34972      // Label 1775: @93414
34973      GIM_Try, /*On fail goto*//*Label 1776*/ 93445, // Rule ID 675 //
34974        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
34975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34976        // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
34977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD,
34978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
34979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
34980        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34981        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
34982        GIR_EraseFromParent, /*InsnID*/0,
34983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34984        // GIR_Coverage, 675,
34985        GIR_Done,
34986      // Label 1776: @93445
34987      GIM_Reject,
34988    // Label 1771: @93446
34989    GIM_Reject,
34990    // Label 1754: @93447
34991    GIM_Try, /*On fail goto*//*Label 1777*/ 93486, // Rule ID 1518 //
34992      GIM_CheckFeatures, GIFBS_HasNEON,
34993      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
34994      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
34995      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
34996      // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
34997      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd,
34998      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
34999      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35000      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35001      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35002      GIR_EraseFromParent, /*InsnID*/0,
35003      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35004      // GIR_Coverage, 1518,
35005      GIR_Done,
35006    // Label 1777: @93486
35007    GIM_Reject,
35008    // Label 1755: @93487
35009    GIM_Try, /*On fail goto*//*Label 1778*/ 93526, // Rule ID 1520 //
35010      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
35011      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
35012      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35013      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35014      // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
35015      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd,
35016      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35017      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35018      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35019      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35020      GIR_EraseFromParent, /*InsnID*/0,
35021      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35022      // GIR_Coverage, 1520,
35023      GIR_Done,
35024    // Label 1778: @93526
35025    GIM_Reject,
35026    // Label 1756: @93527
35027    GIM_Try, /*On fail goto*//*Label 1779*/ 93618,
35028      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35029      GIM_Try, /*On fail goto*//*Label 1780*/ 93568, // Rule ID 1519 //
35030        GIM_CheckFeatures, GIFBS_HasNEON,
35031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
35032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
35033        // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
35034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q,
35035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35037        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35038        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35039        GIR_EraseFromParent, /*InsnID*/0,
35040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35041        // GIR_Coverage, 1519,
35042        GIR_Done,
35043      // Label 1780: @93568
35044      GIM_Try, /*On fail goto*//*Label 1781*/ 93617, // Rule ID 3411 //
35045        GIM_CheckFeatures, GIFBS_HasMVEFloat,
35046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35048        // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VNEGf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src)
35049        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35050        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
35051        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
35052        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf32,
35053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
35055        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35056        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35057        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35058        GIR_EraseFromParent, /*InsnID*/0,
35059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35060        // GIR_Coverage, 3411,
35061        GIR_Done,
35062      // Label 1781: @93617
35063      GIM_Reject,
35064    // Label 1779: @93618
35065    GIM_Reject,
35066    // Label 1757: @93619
35067    GIM_Try, /*On fail goto*//*Label 1782*/ 93710,
35068      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
35069      GIM_Try, /*On fail goto*//*Label 1783*/ 93660, // Rule ID 1521 //
35070        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
35071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
35072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
35073        // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
35074        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq,
35075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35077        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35078        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35079        GIR_EraseFromParent, /*InsnID*/0,
35080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35081        // GIR_Coverage, 1521,
35082        GIR_Done,
35083      // Label 1783: @93660
35084      GIM_Try, /*On fail goto*//*Label 1784*/ 93709, // Rule ID 3410 //
35085        GIM_CheckFeatures, GIFBS_HasMVEFloat,
35086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35088        // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VNEGf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src)
35089        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35090        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
35091        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
35092        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf16,
35093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
35095        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35096        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35097        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35098        GIR_EraseFromParent, /*InsnID*/0,
35099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35100        // GIR_Coverage, 3410,
35101        GIR_Done,
35102      // Label 1784: @93709
35103      GIM_Reject,
35104    // Label 1782: @93710
35105    GIM_Reject,
35106    // Label 1758: @93711
35107    GIM_Reject,
35108    // Label 30: @93712
35109    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1787*/ 93871,
35110    /*GILLT_s32*//*Label 1785*/ 93720,
35111    /*GILLT_s64*//*Label 1786*/ 93776,
35112    // Label 1785: @93720
35113    GIM_Try, /*On fail goto*//*Label 1788*/ 93775, // Rule ID 2239 //
35114      GIM_CheckFeatures, GIFBS_HasFP16,
35115      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35116      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
35117      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35118      // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
35119      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35120      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
35121      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35122      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
35123      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35124      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS,
35125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
35126      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35127      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35128      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35129      GIR_EraseFromParent, /*InsnID*/0,
35130      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35131      // GIR_Coverage, 2239,
35132      GIR_Done,
35133    // Label 1788: @93775
35134    GIM_Reject,
35135    // Label 1786: @93776
35136    GIM_Try, /*On fail goto*//*Label 1789*/ 93815, // Rule ID 673 //
35137      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
35138      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35141      // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm)  =>  (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
35142      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS,
35143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
35144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
35145      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35146      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35147      GIR_EraseFromParent, /*InsnID*/0,
35148      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35149      // GIR_Coverage, 673,
35150      GIR_Done,
35151    // Label 1789: @93815
35152    GIM_Try, /*On fail goto*//*Label 1790*/ 93870, // Rule ID 2243 //
35153      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35154      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35156      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35157      // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
35158      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35159      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
35160      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35161      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
35162      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35163      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD,
35164      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
35165      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35166      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35167      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35168      GIR_EraseFromParent, /*InsnID*/0,
35169      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35170      // GIR_Coverage, 2243,
35171      GIR_Done,
35172    // Label 1790: @93870
35173    GIM_Reject,
35174    // Label 1787: @93871
35175    GIM_Reject,
35176    // Label 31: @93872
35177    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1793*/ 94035,
35178    /*GILLT_s16*//*Label 1791*/ 93880,
35179    /*GILLT_s32*//*Label 1792*/ 93995,
35180    // Label 1791: @93880
35181    GIM_Try, /*On fail goto*//*Label 1794*/ 93937, // Rule ID 2241 //
35182      GIM_CheckFeatures, GIFBS_HasFP16,
35183      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35184      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
35185      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35186      // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
35187      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35188      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH,
35189      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35190      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
35191      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35192      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35193      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35194      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35195      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35196      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35197      GIR_EraseFromParent, /*InsnID*/0,
35198      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0,
35199      // GIR_Coverage, 2241,
35200      GIR_Done,
35201    // Label 1794: @93937
35202    GIM_Try, /*On fail goto*//*Label 1795*/ 93994, // Rule ID 2245 //
35203      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35204      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
35206      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35207      // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
35208      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35209      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH,
35210      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35211      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
35212      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35213      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35214      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35215      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35216      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35217      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35218      GIR_EraseFromParent, /*InsnID*/0,
35219      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0,
35220      // GIR_Coverage, 2245,
35221      GIR_Done,
35222    // Label 1795: @93994
35223    GIM_Reject,
35224    // Label 1792: @93995
35225    GIM_Try, /*On fail goto*//*Label 1796*/ 94034, // Rule ID 674 //
35226      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
35227      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35228      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
35229      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35230      // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm)  =>  (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
35231      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD,
35232      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
35233      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
35234      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35235      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35236      GIR_EraseFromParent, /*InsnID*/0,
35237      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35238      // GIR_Coverage, 674,
35239      GIR_Done,
35240    // Label 1796: @94034
35241    GIM_Reject,
35242    // Label 1793: @94035
35243    GIM_Reject,
35244    // Label 32: @94036
35245    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 1804*/ 95150,
35246    /*GILLT_s32*//*Label 1797*/ 94053, 0,
35247    /*GILLT_v2s32*//*Label 1798*/ 94792, 0,
35248    /*GILLT_v4s1*//*Label 1799*/ 94832,
35249    /*GILLT_v4s16*//*Label 1800*/ 94879,
35250    /*GILLT_v4s32*//*Label 1801*/ 94919, 0,
35251    /*GILLT_v8s1*//*Label 1802*/ 95011, 0,
35252    /*GILLT_v8s16*//*Label 1803*/ 95058,
35253    // Label 1797: @94053
35254    GIM_Try, /*On fail goto*//*Label 1805*/ 94116, // Rule ID 2253 //
35255      GIM_CheckFeatures, GIFBS_HasFullFP16,
35256      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35258      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35259      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35260      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35261      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35262      GIM_CheckIsSafeToFold, /*InsnID*/1,
35263      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35264      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35265      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSH,
35266      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35267      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35268      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35269      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35270      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35271      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35272      GIR_EraseFromParent, /*InsnID*/0,
35273      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35274      // GIR_Coverage, 2253,
35275      GIR_Done,
35276    // Label 1805: @94116
35277    GIM_Try, /*On fail goto*//*Label 1806*/ 94179, // Rule ID 2255 //
35278      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35279      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35280      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35281      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35282      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35283      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35284      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35285      GIM_CheckIsSafeToFold, /*InsnID*/1,
35286      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35287      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35288      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSS,
35289      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35290      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35291      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35292      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35293      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35294      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35295      GIR_EraseFromParent, /*InsnID*/0,
35296      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35297      // GIR_Coverage, 2255,
35298      GIR_Done,
35299    // Label 1806: @94179
35300    GIM_Try, /*On fail goto*//*Label 1807*/ 94242, // Rule ID 2257 //
35301      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35302      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35303      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35304      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35305      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35306      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35307      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35308      GIM_CheckIsSafeToFold, /*InsnID*/1,
35309      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35310      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35311      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSD,
35312      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35313      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35314      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35315      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35316      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35317      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35318      GIR_EraseFromParent, /*InsnID*/0,
35319      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35320      // GIR_Coverage, 2257,
35321      GIR_Done,
35322    // Label 1807: @94242
35323    GIM_Try, /*On fail goto*//*Label 1808*/ 94305, // Rule ID 2259 //
35324      GIM_CheckFeatures, GIFBS_HasFullFP16,
35325      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35326      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35327      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35328      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35329      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35330      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35331      GIM_CheckIsSafeToFold, /*InsnID*/1,
35332      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35333      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35334      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSH,
35335      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35336      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35337      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35338      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35339      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35340      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35341      GIR_EraseFromParent, /*InsnID*/0,
35342      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35343      // GIR_Coverage, 2259,
35344      GIR_Done,
35345    // Label 1808: @94305
35346    GIM_Try, /*On fail goto*//*Label 1809*/ 94368, // Rule ID 2261 //
35347      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35348      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35349      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35350      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35351      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35352      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35353      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35354      GIM_CheckIsSafeToFold, /*InsnID*/1,
35355      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35356      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35357      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSS,
35358      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35359      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35360      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35361      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35362      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35363      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35364      GIR_EraseFromParent, /*InsnID*/0,
35365      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35366      // GIR_Coverage, 2261,
35367      GIR_Done,
35368    // Label 1809: @94368
35369    GIM_Try, /*On fail goto*//*Label 1810*/ 94431, // Rule ID 2263 //
35370      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35371      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35373      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35374      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35375      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35376      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35377      GIM_CheckIsSafeToFold, /*InsnID*/1,
35378      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35379      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35380      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSD,
35381      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35382      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35383      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35384      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35385      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35386      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35387      GIR_EraseFromParent, /*InsnID*/0,
35388      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35389      // GIR_Coverage, 2263,
35390      GIR_Done,
35391    // Label 1810: @94431
35392    GIM_Try, /*On fail goto*//*Label 1811*/ 94494, // Rule ID 2247 //
35393      GIM_CheckFeatures, GIFBS_HasFullFP16,
35394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35396      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35397      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35398      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35399      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35400      GIM_CheckIsSafeToFold, /*InsnID*/1,
35401      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35402      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35403      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASH,
35404      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35405      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35406      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35407      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35408      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35409      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35410      GIR_EraseFromParent, /*InsnID*/0,
35411      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35412      // GIR_Coverage, 2247,
35413      GIR_Done,
35414    // Label 1811: @94494
35415    GIM_Try, /*On fail goto*//*Label 1812*/ 94557, // Rule ID 2249 //
35416      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35417      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35419      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35420      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35421      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35422      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35423      GIM_CheckIsSafeToFold, /*InsnID*/1,
35424      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35425      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35426      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASS,
35427      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35428      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35429      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35430      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35431      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35432      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35433      GIR_EraseFromParent, /*InsnID*/0,
35434      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35435      // GIR_Coverage, 2249,
35436      GIR_Done,
35437    // Label 1812: @94557
35438    GIM_Try, /*On fail goto*//*Label 1813*/ 94620, // Rule ID 2251 //
35439      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35440      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35441      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35442      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35443      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35444      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35445      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35446      GIM_CheckIsSafeToFold, /*InsnID*/1,
35447      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35448      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35449      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASD,
35450      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35451      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35452      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35453      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35454      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35455      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35456      GIR_EraseFromParent, /*InsnID*/0,
35457      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35458      // GIR_Coverage, 2251,
35459      GIR_Done,
35460    // Label 1813: @94620
35461    GIM_Try, /*On fail goto*//*Label 1814*/ 94677, // Rule ID 2280 //
35462      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
35463      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35464      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35466      // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35467      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35468      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD,
35469      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35470      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35471      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35472      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35473      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35474      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35476      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35477      GIR_EraseFromParent, /*InsnID*/0,
35478      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35479      // GIR_Coverage, 2280,
35480      GIR_Done,
35481    // Label 1814: @94677
35482    GIM_Try, /*On fail goto*//*Label 1815*/ 94734, // Rule ID 2282 //
35483      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
35484      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35485      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35487      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35488      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35489      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS,
35490      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35491      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35492      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35493      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35494      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35495      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35496      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35497      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35498      GIR_EraseFromParent, /*InsnID*/0,
35499      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35500      // GIR_Coverage, 2282,
35501      GIR_Done,
35502    // Label 1815: @94734
35503    GIM_Try, /*On fail goto*//*Label 1816*/ 94791, // Rule ID 2284 //
35504      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
35505      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35506      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35507      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35508      // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35509      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35510      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH,
35511      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35512      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35513      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35514      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35515      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35516      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35518      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35519      GIR_EraseFromParent, /*InsnID*/0,
35520      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35521      // GIR_Coverage, 2284,
35522      GIR_Done,
35523    // Label 1816: @94791
35524    GIM_Reject,
35525    // Label 1798: @94792
35526    GIM_Try, /*On fail goto*//*Label 1817*/ 94831, // Rule ID 1592 //
35527      GIM_CheckFeatures, GIFBS_HasNEON,
35528      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
35529      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35530      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35531      // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
35532      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd,
35533      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35534      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35535      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35536      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35537      GIR_EraseFromParent, /*InsnID*/0,
35538      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35539      // GIR_Coverage, 1592,
35540      GIR_Done,
35541    // Label 1817: @94831
35542    GIM_Reject,
35543    // Label 1799: @94832
35544    GIM_Try, /*On fail goto*//*Label 1818*/ 94878, // Rule ID 3888 //
35545      GIM_CheckFeatures, GIFBS_HasMVEFloat,
35546      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35547      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
35548      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35549      // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
35550      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
35551      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
35552      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
35553      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
35554      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
35555      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35556      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35557      GIR_EraseFromParent, /*InsnID*/0,
35558      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35559      // GIR_Coverage, 3888,
35560      GIR_Done,
35561    // Label 1818: @94878
35562    GIM_Reject,
35563    // Label 1800: @94879
35564    GIM_Try, /*On fail goto*//*Label 1819*/ 94918, // Rule ID 1600 //
35565      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
35566      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
35567      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35568      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35569      // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
35570      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd,
35571      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35572      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35573      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35574      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35575      GIR_EraseFromParent, /*InsnID*/0,
35576      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35577      // GIR_Coverage, 1600,
35578      GIR_Done,
35579    // Label 1819: @94918
35580    GIM_Reject,
35581    // Label 1801: @94919
35582    GIM_Try, /*On fail goto*//*Label 1820*/ 95010,
35583      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35584      GIM_Try, /*On fail goto*//*Label 1821*/ 94960, // Rule ID 1596 //
35585        GIM_CheckFeatures, GIFBS_HasNEON,
35586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
35587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
35588        // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
35589        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq,
35590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35592        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35593        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35594        GIR_EraseFromParent, /*InsnID*/0,
35595        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35596        // GIR_Coverage, 1596,
35597        GIR_Done,
35598      // Label 1821: @94960
35599      GIM_Try, /*On fail goto*//*Label 1822*/ 95009, // Rule ID 3400 //
35600        GIM_CheckFeatures, GIFBS_HasMVEFloat,
35601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35603        // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
35604        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35605        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
35606        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
35607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32z,
35608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
35610        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35611        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35612        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35613        GIR_EraseFromParent, /*InsnID*/0,
35614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35615        // GIR_Coverage, 3400,
35616        GIR_Done,
35617      // Label 1822: @95009
35618      GIM_Reject,
35619    // Label 1820: @95010
35620    GIM_Reject,
35621    // Label 1802: @95011
35622    GIM_Try, /*On fail goto*//*Label 1823*/ 95057, // Rule ID 3889 //
35623      GIM_CheckFeatures, GIFBS_HasMVEFloat,
35624      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
35625      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
35626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35627      // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
35628      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
35629      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
35630      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
35631      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
35632      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
35633      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35634      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35635      GIR_EraseFromParent, /*InsnID*/0,
35636      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35637      // GIR_Coverage, 3889,
35638      GIR_Done,
35639    // Label 1823: @95057
35640    GIM_Reject,
35641    // Label 1803: @95058
35642    GIM_Try, /*On fail goto*//*Label 1824*/ 95149,
35643      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
35644      GIM_Try, /*On fail goto*//*Label 1825*/ 95099, // Rule ID 1604 //
35645        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
35646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
35647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
35648        // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
35649        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq,
35650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35652        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35653        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35654        GIR_EraseFromParent, /*InsnID*/0,
35655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35656        // GIR_Coverage, 1604,
35657        GIR_Done,
35658      // Label 1825: @95099
35659      GIM_Try, /*On fail goto*//*Label 1826*/ 95148, // Rule ID 3402 //
35660        GIM_CheckFeatures, GIFBS_HasMVEFloat,
35661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35663        // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
35664        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35665        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
35666        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
35667        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16z,
35668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
35670        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35671        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35672        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35673        GIR_EraseFromParent, /*InsnID*/0,
35674        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35675        // GIR_Coverage, 3402,
35676        GIR_Done,
35677      // Label 1826: @95148
35678      GIM_Reject,
35679    // Label 1824: @95149
35680    GIM_Reject,
35681    // Label 1804: @95150
35682    GIM_Reject,
35683    // Label 33: @95151
35684    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 1834*/ 96265,
35685    /*GILLT_s32*//*Label 1827*/ 95168, 0,
35686    /*GILLT_v2s32*//*Label 1828*/ 95907, 0,
35687    /*GILLT_v4s1*//*Label 1829*/ 95947,
35688    /*GILLT_v4s16*//*Label 1830*/ 95994,
35689    /*GILLT_v4s32*//*Label 1831*/ 96034, 0,
35690    /*GILLT_v8s1*//*Label 1832*/ 96126, 0,
35691    /*GILLT_v8s16*//*Label 1833*/ 96173,
35692    // Label 1827: @95168
35693    GIM_Try, /*On fail goto*//*Label 1835*/ 95231, // Rule ID 2254 //
35694      GIM_CheckFeatures, GIFBS_HasFullFP16,
35695      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35697      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35698      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35699      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35700      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35701      GIM_CheckIsSafeToFold, /*InsnID*/1,
35702      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35703      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35704      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUH,
35705      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35706      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35707      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35708      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35709      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35710      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35711      GIR_EraseFromParent, /*InsnID*/0,
35712      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35713      // GIR_Coverage, 2254,
35714      GIR_Done,
35715    // Label 1835: @95231
35716    GIM_Try, /*On fail goto*//*Label 1836*/ 95294, // Rule ID 2256 //
35717      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35718      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35719      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35720      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35721      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35722      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35723      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35724      GIM_CheckIsSafeToFold, /*InsnID*/1,
35725      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35726      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35727      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUS,
35728      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35729      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35730      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35731      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35733      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35734      GIR_EraseFromParent, /*InsnID*/0,
35735      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35736      // GIR_Coverage, 2256,
35737      GIR_Done,
35738    // Label 1836: @95294
35739    GIM_Try, /*On fail goto*//*Label 1837*/ 95357, // Rule ID 2258 //
35740      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35741      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35743      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35744      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
35745      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35746      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35747      GIM_CheckIsSafeToFold, /*InsnID*/1,
35748      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35749      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35750      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUD,
35751      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35752      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35753      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35754      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35755      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35756      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35757      GIR_EraseFromParent, /*InsnID*/0,
35758      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35759      // GIR_Coverage, 2258,
35760      GIR_Done,
35761    // Label 1837: @95357
35762    GIM_Try, /*On fail goto*//*Label 1838*/ 95420, // Rule ID 2260 //
35763      GIM_CheckFeatures, GIFBS_HasFullFP16,
35764      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35766      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35767      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35768      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35769      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35770      GIM_CheckIsSafeToFold, /*InsnID*/1,
35771      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35772      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35773      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUH,
35774      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35775      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35776      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35777      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35778      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35779      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35780      GIR_EraseFromParent, /*InsnID*/0,
35781      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35782      // GIR_Coverage, 2260,
35783      GIR_Done,
35784    // Label 1838: @95420
35785    GIM_Try, /*On fail goto*//*Label 1839*/ 95483, // Rule ID 2262 //
35786      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35787      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35788      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35789      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35790      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35791      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35792      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35793      GIM_CheckIsSafeToFold, /*InsnID*/1,
35794      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35795      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35796      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUS,
35797      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35798      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35799      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35802      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35803      GIR_EraseFromParent, /*InsnID*/0,
35804      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35805      // GIR_Coverage, 2262,
35806      GIR_Done,
35807    // Label 1839: @95483
35808    GIM_Try, /*On fail goto*//*Label 1840*/ 95546, // Rule ID 2264 //
35809      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35810      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35811      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35812      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35813      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
35814      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35815      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35816      GIM_CheckIsSafeToFold, /*InsnID*/1,
35817      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35818      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35819      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUD,
35820      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35821      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35822      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35823      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35824      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35825      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35826      GIR_EraseFromParent, /*InsnID*/0,
35827      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35828      // GIR_Coverage, 2264,
35829      GIR_Done,
35830    // Label 1840: @95546
35831    GIM_Try, /*On fail goto*//*Label 1841*/ 95609, // Rule ID 2248 //
35832      GIM_CheckFeatures, GIFBS_HasFullFP16,
35833      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35834      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35835      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35836      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35837      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
35838      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35839      GIM_CheckIsSafeToFold, /*InsnID*/1,
35840      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35841      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35842      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUH,
35843      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35844      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35845      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35846      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35847      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35848      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35849      GIR_EraseFromParent, /*InsnID*/0,
35850      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35851      // GIR_Coverage, 2248,
35852      GIR_Done,
35853    // Label 1841: @95609
35854    GIM_Try, /*On fail goto*//*Label 1842*/ 95672, // Rule ID 2250 //
35855      GIM_CheckFeatures, GIFBS_HasFPARMv8,
35856      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35857      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35858      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35859      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35860      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
35861      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35862      GIM_CheckIsSafeToFold, /*InsnID*/1,
35863      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35864      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35865      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUS,
35866      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35867      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35868      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35869      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35870      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35871      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35872      GIR_EraseFromParent, /*InsnID*/0,
35873      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35874      // GIR_Coverage, 2250,
35875      GIR_Done,
35876    // Label 1842: @95672
35877    GIM_Try, /*On fail goto*//*Label 1843*/ 95735, // Rule ID 2252 //
35878      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
35879      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35880      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35881      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35882      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
35883      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
35884      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35885      GIM_CheckIsSafeToFold, /*InsnID*/1,
35886      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35887      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35888      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUD,
35889      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35890      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
35891      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35892      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35893      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35894      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35895      GIR_EraseFromParent, /*InsnID*/0,
35896      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35897      // GIR_Coverage, 2252,
35898      GIR_Done,
35899    // Label 1843: @95735
35900    GIM_Try, /*On fail goto*//*Label 1844*/ 95792, // Rule ID 2285 //
35901      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
35902      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
35903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35904      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35905      // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
35906      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35907      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD,
35908      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35909      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35910      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35911      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35912      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35913      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35914      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35915      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35916      GIR_EraseFromParent, /*InsnID*/0,
35917      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35918      // GIR_Coverage, 2285,
35919      GIR_Done,
35920    // Label 1844: @95792
35921    GIM_Try, /*On fail goto*//*Label 1845*/ 95849, // Rule ID 2287 //
35922      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
35923      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35925      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
35926      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
35927      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35928      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS,
35929      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35930      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35931      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35932      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35933      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35934      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35935      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35936      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35937      GIR_EraseFromParent, /*InsnID*/0,
35938      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35939      // GIR_Coverage, 2287,
35940      GIR_Done,
35941    // Label 1845: @95849
35942    GIM_Try, /*On fail goto*//*Label 1846*/ 95906, // Rule ID 2289 //
35943      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
35944      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
35945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35946      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
35947      // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
35948      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35949      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH,
35950      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
35951      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
35952      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
35953      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
35954      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35955      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
35956      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
35957      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
35958      GIR_EraseFromParent, /*InsnID*/0,
35959      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4,
35960      // GIR_Coverage, 2289,
35961      GIR_Done,
35962    // Label 1846: @95906
35963    GIM_Reject,
35964    // Label 1828: @95907
35965    GIM_Try, /*On fail goto*//*Label 1847*/ 95946, // Rule ID 1593 //
35966      GIM_CheckFeatures, GIFBS_HasNEON,
35967      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
35968      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
35969      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
35970      // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
35971      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud,
35972      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
35973      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
35974      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35975      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35976      GIR_EraseFromParent, /*InsnID*/0,
35977      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35978      // GIR_Coverage, 1593,
35979      GIR_Done,
35980    // Label 1847: @95946
35981    GIM_Reject,
35982    // Label 1829: @95947
35983    GIM_Try, /*On fail goto*//*Label 1848*/ 95993, // Rule ID 3886 //
35984      GIM_CheckFeatures, GIFBS_HasMVEFloat,
35985      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35986      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
35987      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35988      // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
35989      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
35990      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
35991      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
35992      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
35993      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
35994      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
35995      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
35996      GIR_EraseFromParent, /*InsnID*/0,
35997      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35998      // GIR_Coverage, 3886,
35999      GIR_Done,
36000    // Label 1848: @95993
36001    GIM_Reject,
36002    // Label 1830: @95994
36003    GIM_Try, /*On fail goto*//*Label 1849*/ 96033, // Rule ID 1601 //
36004      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36005      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36006      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36008      // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
36009      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud,
36010      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36011      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36012      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36013      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36014      GIR_EraseFromParent, /*InsnID*/0,
36015      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36016      // GIR_Coverage, 1601,
36017      GIR_Done,
36018    // Label 1849: @96033
36019    GIM_Reject,
36020    // Label 1831: @96034
36021    GIM_Try, /*On fail goto*//*Label 1850*/ 96125,
36022      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36023      GIM_Try, /*On fail goto*//*Label 1851*/ 96075, // Rule ID 1597 //
36024        GIM_CheckFeatures, GIFBS_HasNEON,
36025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36027        // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
36028        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq,
36029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36031        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36032        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36033        GIR_EraseFromParent, /*InsnID*/0,
36034        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36035        // GIR_Coverage, 1597,
36036        GIR_Done,
36037      // Label 1851: @96075
36038      GIM_Try, /*On fail goto*//*Label 1852*/ 96124, // Rule ID 3401 //
36039        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36042        // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
36043        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36044        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36045        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32z,
36047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36049        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36050        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36051        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36052        GIR_EraseFromParent, /*InsnID*/0,
36053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36054        // GIR_Coverage, 3401,
36055        GIR_Done,
36056      // Label 1852: @96124
36057      GIM_Reject,
36058    // Label 1850: @96125
36059    GIM_Reject,
36060    // Label 1832: @96126
36061    GIM_Try, /*On fail goto*//*Label 1853*/ 96172, // Rule ID 3887 //
36062      GIM_CheckFeatures, GIFBS_HasMVEFloat,
36063      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
36065      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36066      // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
36067      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
36068      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
36069      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
36070      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
36071      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
36072      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36073      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36074      GIR_EraseFromParent, /*InsnID*/0,
36075      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36076      // GIR_Coverage, 3887,
36077      GIR_Done,
36078    // Label 1853: @96172
36079    GIM_Reject,
36080    // Label 1833: @96173
36081    GIM_Try, /*On fail goto*//*Label 1854*/ 96264,
36082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36083      GIM_Try, /*On fail goto*//*Label 1855*/ 96214, // Rule ID 1605 //
36084        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36087        // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
36088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq,
36089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36091        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36092        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36093        GIR_EraseFromParent, /*InsnID*/0,
36094        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36095        // GIR_Coverage, 1605,
36096        GIR_Done,
36097      // Label 1855: @96214
36098      GIM_Try, /*On fail goto*//*Label 1856*/ 96263, // Rule ID 3403 //
36099        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36102        // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
36103        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36104        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36105        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16z,
36107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36109        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36110        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36111        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36112        GIR_EraseFromParent, /*InsnID*/0,
36113        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36114        // GIR_Coverage, 3403,
36115        GIR_Done,
36116      // Label 1856: @96263
36117      GIM_Reject,
36118    // Label 1854: @96264
36119    GIM_Reject,
36120    // Label 1834: @96265
36121    GIM_Reject,
36122    // Label 34: @96266
36123    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1864*/ 96716,
36124    /*GILLT_s16*//*Label 1857*/ 96284,
36125    /*GILLT_s32*//*Label 1858*/ 96340,
36126    /*GILLT_s64*//*Label 1859*/ 96396,
36127    /*GILLT_v2s32*//*Label 1860*/ 96452, 0, 0,
36128    /*GILLT_v4s16*//*Label 1861*/ 96492,
36129    /*GILLT_v4s32*//*Label 1862*/ 96532, 0, 0, 0,
36130    /*GILLT_v8s16*//*Label 1863*/ 96624,
36131    // Label 1857: @96284
36132    GIM_Try, /*On fail goto*//*Label 1865*/ 96339, // Rule ID 2274 //
36133      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
36134      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36135      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
36136      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36137      // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36138      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36139      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36140      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36141      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36142      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36143      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH,
36144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36145      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36146      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36147      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36148      GIR_EraseFromParent, /*InsnID*/0,
36149      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36150      // GIR_Coverage, 2274,
36151      GIR_Done,
36152    // Label 1865: @96339
36153    GIM_Reject,
36154    // Label 1858: @96340
36155    GIM_Try, /*On fail goto*//*Label 1866*/ 96395, // Rule ID 2272 //
36156      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
36157      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36158      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
36159      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36160      // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36161      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36162      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36163      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36164      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36165      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36166      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS,
36167      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36168      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36169      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36170      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36171      GIR_EraseFromParent, /*InsnID*/0,
36172      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36173      // GIR_Coverage, 2272,
36174      GIR_Done,
36175    // Label 1866: @96395
36176    GIM_Reject,
36177    // Label 1859: @96396
36178    GIM_Try, /*On fail goto*//*Label 1867*/ 96451, // Rule ID 2270 //
36179      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
36180      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36183      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36184      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36185      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36186      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36187      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36188      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36189      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD,
36190      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
36191      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36192      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36193      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36194      GIR_EraseFromParent, /*InsnID*/0,
36195      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36196      // GIR_Coverage, 2270,
36197      GIR_Done,
36198    // Label 1867: @96451
36199    GIM_Reject,
36200    // Label 1860: @96452
36201    GIM_Try, /*On fail goto*//*Label 1868*/ 96491, // Rule ID 1594 //
36202      GIM_CheckFeatures, GIFBS_HasNEON,
36203      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36204      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36206      // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
36207      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd,
36208      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36209      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36210      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36211      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36212      GIR_EraseFromParent, /*InsnID*/0,
36213      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36214      // GIR_Coverage, 1594,
36215      GIR_Done,
36216    // Label 1868: @96491
36217    GIM_Reject,
36218    // Label 1861: @96492
36219    GIM_Try, /*On fail goto*//*Label 1869*/ 96531, // Rule ID 1602 //
36220      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36221      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36222      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36224      // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
36225      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd,
36226      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36227      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36228      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36229      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36230      GIR_EraseFromParent, /*InsnID*/0,
36231      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36232      // GIR_Coverage, 1602,
36233      GIR_Done,
36234    // Label 1869: @96531
36235    GIM_Reject,
36236    // Label 1862: @96532
36237    GIM_Try, /*On fail goto*//*Label 1870*/ 96623,
36238      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36239      GIM_Try, /*On fail goto*//*Label 1871*/ 96573, // Rule ID 1598 //
36240        GIM_CheckFeatures, GIFBS_HasNEON,
36241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36242        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36243        // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
36244        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq,
36245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36247        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36248        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36249        GIR_EraseFromParent, /*InsnID*/0,
36250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36251        // GIR_Coverage, 1598,
36252        GIR_Done,
36253      // Label 1871: @96573
36254      GIM_Try, /*On fail goto*//*Label 1872*/ 96622, // Rule ID 3404 //
36255        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36258        // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
36259        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36260        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36261        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32n,
36263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36265        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36266        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36267        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36268        GIR_EraseFromParent, /*InsnID*/0,
36269        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36270        // GIR_Coverage, 3404,
36271        GIR_Done,
36272      // Label 1872: @96622
36273      GIM_Reject,
36274    // Label 1870: @96623
36275    GIM_Reject,
36276    // Label 1863: @96624
36277    GIM_Try, /*On fail goto*//*Label 1873*/ 96715,
36278      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36279      GIM_Try, /*On fail goto*//*Label 1874*/ 96665, // Rule ID 1606 //
36280        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36283        // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
36284        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq,
36285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36287        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36288        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36289        GIR_EraseFromParent, /*InsnID*/0,
36290        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36291        // GIR_Coverage, 1606,
36292        GIR_Done,
36293      // Label 1874: @96665
36294      GIM_Try, /*On fail goto*//*Label 1875*/ 96714, // Rule ID 3406 //
36295        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36298        // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
36299        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36300        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36301        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36302        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16n,
36303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36305        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36306        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36307        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36308        GIR_EraseFromParent, /*InsnID*/0,
36309        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36310        // GIR_Coverage, 3406,
36311        GIR_Done,
36312      // Label 1875: @96714
36313      GIM_Reject,
36314    // Label 1873: @96715
36315    GIM_Reject,
36316    // Label 1864: @96716
36317    GIM_Reject,
36318    // Label 35: @96717
36319    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1883*/ 97167,
36320    /*GILLT_s16*//*Label 1876*/ 96735,
36321    /*GILLT_s32*//*Label 1877*/ 96791,
36322    /*GILLT_s64*//*Label 1878*/ 96847,
36323    /*GILLT_v2s32*//*Label 1879*/ 96903, 0, 0,
36324    /*GILLT_v4s16*//*Label 1880*/ 96943,
36325    /*GILLT_v4s32*//*Label 1881*/ 96983, 0, 0, 0,
36326    /*GILLT_v8s16*//*Label 1882*/ 97075,
36327    // Label 1876: @96735
36328    GIM_Try, /*On fail goto*//*Label 1884*/ 96790, // Rule ID 2279 //
36329      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
36330      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
36332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36333      // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36334      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36335      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36336      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36337      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36338      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36339      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH,
36340      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36341      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36342      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36343      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36344      GIR_EraseFromParent, /*InsnID*/0,
36345      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36346      // GIR_Coverage, 2279,
36347      GIR_Done,
36348    // Label 1884: @96790
36349    GIM_Reject,
36350    // Label 1877: @96791
36351    GIM_Try, /*On fail goto*//*Label 1885*/ 96846, // Rule ID 2277 //
36352      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
36353      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36354      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
36355      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36356      // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36357      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36358      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36359      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36360      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36361      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36362      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS,
36363      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36364      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36365      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36366      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36367      GIR_EraseFromParent, /*InsnID*/0,
36368      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36369      // GIR_Coverage, 2277,
36370      GIR_Done,
36371    // Label 1885: @96846
36372    GIM_Reject,
36373    // Label 1878: @96847
36374    GIM_Try, /*On fail goto*//*Label 1886*/ 96902, // Rule ID 2275 //
36375      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
36376      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36377      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36378      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36379      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
36380      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36381      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36382      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
36383      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
36384      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36385      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD,
36386      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
36387      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36388      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36389      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36390      GIR_EraseFromParent, /*InsnID*/0,
36391      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36392      // GIR_Coverage, 2275,
36393      GIR_Done,
36394    // Label 1886: @96902
36395    GIM_Reject,
36396    // Label 1879: @96903
36397    GIM_Try, /*On fail goto*//*Label 1887*/ 96942, // Rule ID 1595 //
36398      GIM_CheckFeatures, GIFBS_HasNEON,
36399      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36400      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36401      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36402      // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
36403      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd,
36404      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36405      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36406      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36407      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36408      GIR_EraseFromParent, /*InsnID*/0,
36409      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36410      // GIR_Coverage, 1595,
36411      GIR_Done,
36412    // Label 1887: @96942
36413    GIM_Reject,
36414    // Label 1880: @96943
36415    GIM_Try, /*On fail goto*//*Label 1888*/ 96982, // Rule ID 1603 //
36416      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36417      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36419      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36420      // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
36421      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd,
36422      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36423      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36424      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36425      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36426      GIR_EraseFromParent, /*InsnID*/0,
36427      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36428      // GIR_Coverage, 1603,
36429      GIR_Done,
36430    // Label 1888: @96982
36431    GIM_Reject,
36432    // Label 1881: @96983
36433    GIM_Try, /*On fail goto*//*Label 1889*/ 97074,
36434      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36435      GIM_Try, /*On fail goto*//*Label 1890*/ 97024, // Rule ID 1599 //
36436        GIM_CheckFeatures, GIFBS_HasNEON,
36437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36439        // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
36440        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq,
36441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36443        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36444        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36445        GIR_EraseFromParent, /*InsnID*/0,
36446        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36447        // GIR_Coverage, 1599,
36448        GIR_Done,
36449      // Label 1890: @97024
36450      GIM_Try, /*On fail goto*//*Label 1891*/ 97073, // Rule ID 3405 //
36451        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36454        // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
36455        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36456        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36457        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32n,
36459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36461        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36462        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36463        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36464        GIR_EraseFromParent, /*InsnID*/0,
36465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36466        // GIR_Coverage, 3405,
36467        GIR_Done,
36468      // Label 1891: @97073
36469      GIM_Reject,
36470    // Label 1889: @97074
36471    GIM_Reject,
36472    // Label 1882: @97075
36473    GIM_Try, /*On fail goto*//*Label 1892*/ 97166,
36474      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36475      GIM_Try, /*On fail goto*//*Label 1893*/ 97116, // Rule ID 1607 //
36476        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36479        // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
36480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq,
36481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36483        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36484        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36485        GIR_EraseFromParent, /*InsnID*/0,
36486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36487        // GIR_Coverage, 1607,
36488        GIR_Done,
36489      // Label 1893: @97116
36490      GIM_Try, /*On fail goto*//*Label 1894*/ 97165, // Rule ID 3407 //
36491        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36494        // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
36495        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36496        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36497        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36498        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16n,
36499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36501        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36502        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36503        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36504        GIR_EraseFromParent, /*InsnID*/0,
36505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36506        // GIR_Coverage, 3407,
36507        GIR_Done,
36508      // Label 1894: @97165
36509      GIM_Reject,
36510    // Label 1892: @97166
36511    GIM_Reject,
36512    // Label 1883: @97167
36513    GIM_Reject,
36514    // Label 36: @97168
36515    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1902*/ 97570,
36516    /*GILLT_s16*//*Label 1895*/ 97186,
36517    /*GILLT_s32*//*Label 1896*/ 97226,
36518    /*GILLT_s64*//*Label 1897*/ 97266,
36519    /*GILLT_v2s32*//*Label 1898*/ 97306, 0, 0,
36520    /*GILLT_v4s16*//*Label 1899*/ 97346,
36521    /*GILLT_v4s32*//*Label 1900*/ 97386, 0, 0, 0,
36522    /*GILLT_v8s16*//*Label 1901*/ 97478,
36523    // Label 1895: @97186
36524    GIM_Try, /*On fail goto*//*Label 1903*/ 97225, // Rule ID 666 //
36525      GIM_CheckFeatures, GIFBS_HasFullFP16,
36526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
36527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
36528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
36529      // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
36530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSH,
36531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
36533      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36534      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36535      GIR_EraseFromParent, /*InsnID*/0,
36536      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36537      // GIR_Coverage, 666,
36538      GIR_Done,
36539    // Label 1903: @97225
36540    GIM_Reject,
36541    // Label 1896: @97226
36542    GIM_Try, /*On fail goto*//*Label 1904*/ 97265, // Rule ID 665 //
36543      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
36544      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36545      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
36546      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
36547      // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
36548      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSS,
36549      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
36550      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
36551      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36552      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36553      GIR_EraseFromParent, /*InsnID*/0,
36554      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36555      // GIR_Coverage, 665,
36556      GIR_Done,
36557    // Label 1904: @97265
36558    GIM_Reject,
36559    // Label 1897: @97266
36560    GIM_Try, /*On fail goto*//*Label 1905*/ 97305, // Rule ID 664 //
36561      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
36562      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
36563      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36564      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36565      // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
36566      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSD,
36567      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
36568      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
36569      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36570      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36571      GIR_EraseFromParent, /*InsnID*/0,
36572      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36573      // GIR_Coverage, 664,
36574      GIR_Done,
36575    // Label 1905: @97305
36576    GIM_Reject,
36577    // Label 1898: @97306
36578    GIM_Try, /*On fail goto*//*Label 1906*/ 97345, // Rule ID 1502 //
36579      GIM_CheckFeatures, GIFBS_HasNEON,
36580      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36581      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36582      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36583      // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
36584      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfd,
36585      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36586      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36587      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36588      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36589      GIR_EraseFromParent, /*InsnID*/0,
36590      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36591      // GIR_Coverage, 1502,
36592      GIR_Done,
36593    // Label 1906: @97345
36594    GIM_Reject,
36595    // Label 1899: @97346
36596    GIM_Try, /*On fail goto*//*Label 1907*/ 97385, // Rule ID 1504 //
36597      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36598      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36600      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36601      // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
36602      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShd,
36603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36604      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36605      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36606      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36607      GIR_EraseFromParent, /*InsnID*/0,
36608      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36609      // GIR_Coverage, 1504,
36610      GIR_Done,
36611    // Label 1907: @97385
36612    GIM_Reject,
36613    // Label 1900: @97386
36614    GIM_Try, /*On fail goto*//*Label 1908*/ 97477,
36615      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36616      GIM_Try, /*On fail goto*//*Label 1909*/ 97427, // Rule ID 1503 //
36617        GIM_CheckFeatures, GIFBS_HasNEON,
36618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36620        // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
36621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfq,
36622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36624        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36625        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36626        GIR_EraseFromParent, /*InsnID*/0,
36627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36628        // GIR_Coverage, 1503,
36629        GIR_Done,
36630      // Label 1909: @97427
36631      GIM_Try, /*On fail goto*//*Label 1910*/ 97476, // Rule ID 3409 //
36632        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36635        // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VABSf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src)
36636        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36637        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36638        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf32,
36640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36642        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36643        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36644        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36645        GIR_EraseFromParent, /*InsnID*/0,
36646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36647        // GIR_Coverage, 3409,
36648        GIR_Done,
36649      // Label 1910: @97476
36650      GIM_Reject,
36651    // Label 1908: @97477
36652    GIM_Reject,
36653    // Label 1901: @97478
36654    GIM_Try, /*On fail goto*//*Label 1911*/ 97569,
36655      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36656      GIM_Try, /*On fail goto*//*Label 1912*/ 97519, // Rule ID 1505 //
36657        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
36658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36660        // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
36661        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShq,
36662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36664        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36665        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36666        GIR_EraseFromParent, /*InsnID*/0,
36667        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36668        // GIR_Coverage, 1505,
36669        GIR_Done,
36670      // Label 1912: @97519
36671      GIM_Try, /*On fail goto*//*Label 1913*/ 97568, // Rule ID 3408 //
36672        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36675        // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VABSf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src)
36676        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36677        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36678        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf16,
36680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
36682        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36683        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36684        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36685        GIR_EraseFromParent, /*InsnID*/0,
36686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36687        // GIR_Coverage, 3408,
36688        GIR_Done,
36689      // Label 1913: @97568
36690      GIM_Reject,
36691    // Label 1911: @97569
36692    GIM_Reject,
36693    // Label 1902: @97570
36694    GIM_Reject,
36695    // Label 37: @97571
36696    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1921*/ 97933,
36697    /*GILLT_s16*//*Label 1914*/ 97589,
36698    /*GILLT_s32*//*Label 1915*/ 97621,
36699    /*GILLT_s64*//*Label 1916*/ 97653,
36700    /*GILLT_v2s32*//*Label 1917*/ 97685, 0, 0,
36701    /*GILLT_v4s16*//*Label 1918*/ 97717,
36702    /*GILLT_v4s32*//*Label 1919*/ 97749, 0, 0, 0,
36703    /*GILLT_v8s16*//*Label 1920*/ 97841,
36704    // Label 1914: @97589
36705    GIM_Try, /*On fail goto*//*Label 1922*/ 97620, // Rule ID 655 //
36706      GIM_CheckFeatures, GIFBS_HasFullFP16,
36707      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
36708      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
36709      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
36710      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
36711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
36712      // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
36713      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMH,
36714      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36715      // GIR_Coverage, 655,
36716      GIR_Done,
36717    // Label 1922: @97620
36718    GIM_Reject,
36719    // Label 1915: @97621
36720    GIM_Try, /*On fail goto*//*Label 1923*/ 97652, // Rule ID 656 //
36721      GIM_CheckFeatures, GIFBS_HasFPARMv8,
36722      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36723      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
36725      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
36726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
36727      // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
36728      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMS,
36729      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36730      // GIR_Coverage, 656,
36731      GIR_Done,
36732    // Label 1923: @97652
36733    GIM_Reject,
36734    // Label 1916: @97653
36735    GIM_Try, /*On fail goto*//*Label 1924*/ 97684, // Rule ID 657 //
36736      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
36737      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
36738      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
36739      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36740      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36742      // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
36743      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMD,
36744      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36745      // GIR_Coverage, 657,
36746      GIR_Done,
36747    // Label 1924: @97684
36748    GIM_Reject,
36749    // Label 1917: @97685
36750    GIM_Try, /*On fail goto*//*Label 1925*/ 97716, // Rule ID 1221 //
36751      GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
36752      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36753      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
36754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36757      // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
36758      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDf,
36759      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36760      // GIR_Coverage, 1221,
36761      GIR_Done,
36762    // Label 1925: @97716
36763    GIM_Reject,
36764    // Label 1918: @97717
36765    GIM_Try, /*On fail goto*//*Label 1926*/ 97748, // Rule ID 1223 //
36766      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
36767      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36768      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
36769      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36772      // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
36773      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDh,
36774      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36775      // GIR_Coverage, 1223,
36776      GIR_Done,
36777    // Label 1926: @97748
36778    GIM_Reject,
36779    // Label 1919: @97749
36780    GIM_Try, /*On fail goto*//*Label 1927*/ 97840,
36781      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36782      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36783      GIM_Try, /*On fail goto*//*Label 1928*/ 97782, // Rule ID 1222 //
36784        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
36785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
36788        // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
36789        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQf,
36790        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36791        // GIR_Coverage, 1222,
36792        GIR_Done,
36793      // Label 1928: @97782
36794      GIM_Try, /*On fail goto*//*Label 1929*/ 97839, // Rule ID 2893 //
36795        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36799        // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2)  =>  (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2)
36800        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36801        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36802        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36803        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf32,
36804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
36806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2
36807        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36808        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36809        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36810        GIR_EraseFromParent, /*InsnID*/0,
36811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36812        // GIR_Coverage, 2893,
36813        GIR_Done,
36814      // Label 1929: @97839
36815      GIM_Reject,
36816    // Label 1927: @97840
36817    GIM_Reject,
36818    // Label 1920: @97841
36819    GIM_Try, /*On fail goto*//*Label 1930*/ 97932,
36820      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36821      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36822      GIM_Try, /*On fail goto*//*Label 1931*/ 97874, // Rule ID 1224 //
36823        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
36824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
36827        // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
36828        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQh,
36829        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36830        // GIR_Coverage, 1224,
36831        GIR_Done,
36832      // Label 1931: @97874
36833      GIM_Try, /*On fail goto*//*Label 1932*/ 97931, // Rule ID 2894 //
36834        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36838        // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2)  =>  (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2)
36839        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36840        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36841        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36842        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf16,
36843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
36845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2
36846        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36847        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36848        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36849        GIR_EraseFromParent, /*InsnID*/0,
36850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36851        // GIR_Coverage, 2894,
36852        GIR_Done,
36853      // Label 1932: @97931
36854      GIM_Reject,
36855    // Label 1930: @97932
36856    GIM_Reject,
36857    // Label 1921: @97933
36858    GIM_Reject,
36859    // Label 38: @97934
36860    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1940*/ 98296,
36861    /*GILLT_s16*//*Label 1933*/ 97952,
36862    /*GILLT_s32*//*Label 1934*/ 97984,
36863    /*GILLT_s64*//*Label 1935*/ 98016,
36864    /*GILLT_v2s32*//*Label 1936*/ 98048, 0, 0,
36865    /*GILLT_v4s16*//*Label 1937*/ 98080,
36866    /*GILLT_v4s32*//*Label 1938*/ 98112, 0, 0, 0,
36867    /*GILLT_v8s16*//*Label 1939*/ 98204,
36868    // Label 1933: @97952
36869    GIM_Try, /*On fail goto*//*Label 1941*/ 97983, // Rule ID 652 //
36870      GIM_CheckFeatures, GIFBS_HasFullFP16,
36871      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
36872      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
36873      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
36874      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
36875      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
36876      // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
36877      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMH,
36878      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36879      // GIR_Coverage, 652,
36880      GIR_Done,
36881    // Label 1941: @97983
36882    GIM_Reject,
36883    // Label 1934: @97984
36884    GIM_Try, /*On fail goto*//*Label 1942*/ 98015, // Rule ID 653 //
36885      GIM_CheckFeatures, GIFBS_HasFPARMv8,
36886      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
36887      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36888      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
36889      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
36890      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
36891      // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
36892      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMS,
36893      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36894      // GIR_Coverage, 653,
36895      GIR_Done,
36896    // Label 1942: @98015
36897    GIM_Reject,
36898    // Label 1935: @98016
36899    GIM_Try, /*On fail goto*//*Label 1943*/ 98047, // Rule ID 654 //
36900      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
36901      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
36902      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
36903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36904      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36905      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36906      // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
36907      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMD,
36908      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36909      // GIR_Coverage, 654,
36910      GIR_Done,
36911    // Label 1943: @98047
36912    GIM_Reject,
36913    // Label 1936: @98048
36914    GIM_Try, /*On fail goto*//*Label 1944*/ 98079, // Rule ID 1201 //
36915      GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
36916      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36917      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
36918      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36920      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36921      // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
36922      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDf,
36923      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36924      // GIR_Coverage, 1201,
36925      GIR_Done,
36926    // Label 1944: @98079
36927    GIM_Reject,
36928    // Label 1937: @98080
36929    GIM_Try, /*On fail goto*//*Label 1945*/ 98111, // Rule ID 1203 //
36930      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
36931      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36932      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
36933      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36934      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36935      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
36936      // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
36937      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDh,
36938      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36939      // GIR_Coverage, 1203,
36940      GIR_Done,
36941    // Label 1945: @98111
36942    GIM_Reject,
36943    // Label 1938: @98112
36944    GIM_Try, /*On fail goto*//*Label 1946*/ 98203,
36945      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36946      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36947      GIM_Try, /*On fail goto*//*Label 1947*/ 98145, // Rule ID 1202 //
36948        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
36949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
36952        // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
36953        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQf,
36954        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36955        // GIR_Coverage, 1202,
36956        GIR_Done,
36957      // Label 1947: @98145
36958      GIM_Try, /*On fail goto*//*Label 1948*/ 98202, // Rule ID 2889 //
36959        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
36962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36963        // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2)  =>  (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2)
36964        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36965        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36966        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
36967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf32,
36968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
36970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2
36971        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
36972        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
36973        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
36974        GIR_EraseFromParent, /*InsnID*/0,
36975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36976        // GIR_Coverage, 2889,
36977        GIR_Done,
36978      // Label 1948: @98202
36979      GIM_Reject,
36980    // Label 1946: @98203
36981    GIM_Reject,
36982    // Label 1939: @98204
36983    GIM_Try, /*On fail goto*//*Label 1949*/ 98295,
36984      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36985      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36986      GIM_Try, /*On fail goto*//*Label 1950*/ 98237, // Rule ID 1204 //
36987        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
36988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
36991        // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
36992        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQh,
36993        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36994        // GIR_Coverage, 1204,
36995        GIR_Done,
36996      // Label 1950: @98237
36997      GIM_Try, /*On fail goto*//*Label 1951*/ 98294, // Rule ID 2890 //
36998        GIM_CheckFeatures, GIFBS_HasMVEFloat,
36999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37002        // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2)  =>  (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2)
37003        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37004        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37005        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37006        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf16,
37007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37008        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
37009        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2
37010        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37011        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37012        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37013        GIR_EraseFromParent, /*InsnID*/0,
37014        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37015        // GIR_Coverage, 2890,
37016        GIR_Done,
37017      // Label 1951: @98294
37018      GIM_Reject,
37019    // Label 1949: @98295
37020    GIM_Reject,
37021    // Label 1940: @98296
37022    GIM_Reject,
37023    // Label 39: @98297
37024    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1958*/ 98807,
37025    /*GILLT_v2s32*//*Label 1952*/ 98315, 0, 0,
37026    /*GILLT_v4s16*//*Label 1953*/ 98367,
37027    /*GILLT_v4s32*//*Label 1954*/ 98419, 0, 0,
37028    /*GILLT_v8s8*//*Label 1955*/ 98531,
37029    /*GILLT_v8s16*//*Label 1956*/ 98583, 0, 0,
37030    /*GILLT_v16s8*//*Label 1957*/ 98695,
37031    // Label 1952: @98315
37032    GIM_Try, /*On fail goto*//*Label 1959*/ 98366, // Rule ID 1206 //
37033      GIM_CheckFeatures, GIFBS_HasNEON,
37034      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37035      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
37036      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37037      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37038      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37039      // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37040      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv2i32,
37041      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37042      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37043      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37044      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37045      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37046      GIR_EraseFromParent, /*InsnID*/0,
37047      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37048      // GIR_Coverage, 1206,
37049      GIR_Done,
37050    // Label 1959: @98366
37051    GIM_Reject,
37052    // Label 1953: @98367
37053    GIM_Try, /*On fail goto*//*Label 1960*/ 98418, // Rule ID 1205 //
37054      GIM_CheckFeatures, GIFBS_HasNEON,
37055      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37056      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
37057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37058      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37059      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37060      // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37061      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i16,
37062      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37063      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37064      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37065      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37066      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37067      GIR_EraseFromParent, /*InsnID*/0,
37068      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37069      // GIR_Coverage, 1205,
37070      GIR_Done,
37071    // Label 1960: @98418
37072    GIM_Reject,
37073    // Label 1954: @98419
37074    GIM_Try, /*On fail goto*//*Label 1961*/ 98530,
37075      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37076      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
37077      GIM_Try, /*On fail goto*//*Label 1962*/ 98472, // Rule ID 1208 //
37078        GIM_CheckFeatures, GIFBS_HasNEON,
37079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37082        // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i32,
37084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37088        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37089        GIR_EraseFromParent, /*InsnID*/0,
37090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37091        // GIR_Coverage, 1208,
37092        GIR_Done,
37093      // Label 1962: @98472
37094      GIM_Try, /*On fail goto*//*Label 1963*/ 98529, // Rule ID 2901 //
37095        GIM_CheckFeatures, GIFBS_HasMVEInt,
37096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37099        // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37100        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37101        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37102        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs32,
37104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37107        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37108        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37109        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37110        GIR_EraseFromParent, /*InsnID*/0,
37111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37112        // GIR_Coverage, 2901,
37113        GIR_Done,
37114      // Label 1963: @98529
37115      GIM_Reject,
37116    // Label 1961: @98530
37117    GIM_Reject,
37118    // Label 1955: @98531
37119    GIM_Try, /*On fail goto*//*Label 1964*/ 98582, // Rule ID 1209 //
37120      GIM_CheckFeatures, GIFBS_HasNEON,
37121      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37122      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
37123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37124      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37126      // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37127      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i8,
37128      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37129      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37130      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37131      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37132      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37133      GIR_EraseFromParent, /*InsnID*/0,
37134      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37135      // GIR_Coverage, 1209,
37136      GIR_Done,
37137    // Label 1964: @98582
37138    GIM_Reject,
37139    // Label 1956: @98583
37140    GIM_Try, /*On fail goto*//*Label 1965*/ 98694,
37141      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
37142      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
37143      GIM_Try, /*On fail goto*//*Label 1966*/ 98636, // Rule ID 1207 //
37144        GIM_CheckFeatures, GIFBS_HasNEON,
37145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37148        // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i16,
37150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37153        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37154        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37155        GIR_EraseFromParent, /*InsnID*/0,
37156        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37157        // GIR_Coverage, 1207,
37158        GIR_Done,
37159      // Label 1966: @98636
37160      GIM_Try, /*On fail goto*//*Label 1967*/ 98693, // Rule ID 2899 //
37161        GIM_CheckFeatures, GIFBS_HasMVEInt,
37162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37165        // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37166        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37167        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37168        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs16,
37170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37173        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37174        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37175        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37176        GIR_EraseFromParent, /*InsnID*/0,
37177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37178        // GIR_Coverage, 2899,
37179        GIR_Done,
37180      // Label 1967: @98693
37181      GIM_Reject,
37182    // Label 1965: @98694
37183    GIM_Reject,
37184    // Label 1957: @98695
37185    GIM_Try, /*On fail goto*//*Label 1968*/ 98806,
37186      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
37187      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
37188      GIM_Try, /*On fail goto*//*Label 1969*/ 98748, // Rule ID 1210 //
37189        GIM_CheckFeatures, GIFBS_HasNEON,
37190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37193        // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37194        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv16i8,
37195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37198        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37199        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37200        GIR_EraseFromParent, /*InsnID*/0,
37201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37202        // GIR_Coverage, 1210,
37203        GIR_Done,
37204      // Label 1969: @98748
37205      GIM_Try, /*On fail goto*//*Label 1970*/ 98805, // Rule ID 2897 //
37206        GIM_CheckFeatures, GIFBS_HasMVEInt,
37207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37210        // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37211        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37212        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37213        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs8,
37215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37218        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37219        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37220        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37221        GIR_EraseFromParent, /*InsnID*/0,
37222        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37223        // GIR_Coverage, 2897,
37224        GIR_Done,
37225      // Label 1970: @98805
37226      GIM_Reject,
37227    // Label 1968: @98806
37228    GIM_Reject,
37229    // Label 1958: @98807
37230    GIM_Reject,
37231    // Label 40: @98808
37232    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1977*/ 99318,
37233    /*GILLT_v2s32*//*Label 1971*/ 98826, 0, 0,
37234    /*GILLT_v4s16*//*Label 1972*/ 98878,
37235    /*GILLT_v4s32*//*Label 1973*/ 98930, 0, 0,
37236    /*GILLT_v8s8*//*Label 1974*/ 99042,
37237    /*GILLT_v8s16*//*Label 1975*/ 99094, 0, 0,
37238    /*GILLT_v16s8*//*Label 1976*/ 99206,
37239    // Label 1971: @98826
37240    GIM_Try, /*On fail goto*//*Label 1978*/ 98877, // Rule ID 1186 //
37241      GIM_CheckFeatures, GIFBS_HasNEON,
37242      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37243      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
37244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37245      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37246      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37247      // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37248      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv2i32,
37249      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37250      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37251      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37252      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37253      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37254      GIR_EraseFromParent, /*InsnID*/0,
37255      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37256      // GIR_Coverage, 1186,
37257      GIR_Done,
37258    // Label 1978: @98877
37259    GIM_Reject,
37260    // Label 1972: @98878
37261    GIM_Try, /*On fail goto*//*Label 1979*/ 98929, // Rule ID 1185 //
37262      GIM_CheckFeatures, GIFBS_HasNEON,
37263      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37264      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
37265      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37266      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37267      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37268      // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37269      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i16,
37270      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37271      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37272      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37273      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37274      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37275      GIR_EraseFromParent, /*InsnID*/0,
37276      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37277      // GIR_Coverage, 1185,
37278      GIR_Done,
37279    // Label 1979: @98929
37280    GIM_Reject,
37281    // Label 1973: @98930
37282    GIM_Try, /*On fail goto*//*Label 1980*/ 99041,
37283      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37284      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
37285      GIM_Try, /*On fail goto*//*Label 1981*/ 98983, // Rule ID 1188 //
37286        GIM_CheckFeatures, GIFBS_HasNEON,
37287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37290        // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i32,
37292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37295        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37296        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37297        GIR_EraseFromParent, /*InsnID*/0,
37298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37299        // GIR_Coverage, 1188,
37300        GIR_Done,
37301      // Label 1981: @98983
37302      GIM_Try, /*On fail goto*//*Label 1982*/ 99040, // Rule ID 2913 //
37303        GIM_CheckFeatures, GIFBS_HasMVEInt,
37304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37307        // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37308        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37309        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37310        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37311        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs32,
37312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37315        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37316        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37317        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37318        GIR_EraseFromParent, /*InsnID*/0,
37319        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37320        // GIR_Coverage, 2913,
37321        GIR_Done,
37322      // Label 1982: @99040
37323      GIM_Reject,
37324    // Label 1980: @99041
37325    GIM_Reject,
37326    // Label 1974: @99042
37327    GIM_Try, /*On fail goto*//*Label 1983*/ 99093, // Rule ID 1189 //
37328      GIM_CheckFeatures, GIFBS_HasNEON,
37329      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37330      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
37331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37334      // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37335      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i8,
37336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37337      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37338      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37339      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37340      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37341      GIR_EraseFromParent, /*InsnID*/0,
37342      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37343      // GIR_Coverage, 1189,
37344      GIR_Done,
37345    // Label 1983: @99093
37346    GIM_Reject,
37347    // Label 1975: @99094
37348    GIM_Try, /*On fail goto*//*Label 1984*/ 99205,
37349      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
37350      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
37351      GIM_Try, /*On fail goto*//*Label 1985*/ 99147, // Rule ID 1187 //
37352        GIM_CheckFeatures, GIFBS_HasNEON,
37353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37356        // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37357        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i16,
37358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37361        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37362        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37363        GIR_EraseFromParent, /*InsnID*/0,
37364        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37365        // GIR_Coverage, 1187,
37366        GIR_Done,
37367      // Label 1985: @99147
37368      GIM_Try, /*On fail goto*//*Label 1986*/ 99204, // Rule ID 2911 //
37369        GIM_CheckFeatures, GIFBS_HasMVEInt,
37370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37373        // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37374        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37375        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37376        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37377        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs16,
37378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37381        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37382        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37383        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37384        GIR_EraseFromParent, /*InsnID*/0,
37385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37386        // GIR_Coverage, 2911,
37387        GIR_Done,
37388      // Label 1986: @99204
37389      GIM_Reject,
37390    // Label 1984: @99205
37391    GIM_Reject,
37392    // Label 1976: @99206
37393    GIM_Try, /*On fail goto*//*Label 1987*/ 99317,
37394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
37395      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
37396      GIM_Try, /*On fail goto*//*Label 1988*/ 99259, // Rule ID 1190 //
37397        GIM_CheckFeatures, GIFBS_HasNEON,
37398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37401        // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv16i8,
37403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37406        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37407        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37408        GIR_EraseFromParent, /*InsnID*/0,
37409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37410        // GIR_Coverage, 1190,
37411        GIR_Done,
37412      // Label 1988: @99259
37413      GIM_Try, /*On fail goto*//*Label 1989*/ 99316, // Rule ID 2909 //
37414        GIM_CheckFeatures, GIFBS_HasMVEInt,
37415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37418        // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37419        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37420        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37421        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37422        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs8,
37423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37426        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37427        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37428        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37429        GIR_EraseFromParent, /*InsnID*/0,
37430        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37431        // GIR_Coverage, 2909,
37432        GIR_Done,
37433      // Label 1989: @99316
37434      GIM_Reject,
37435    // Label 1987: @99317
37436    GIM_Reject,
37437    // Label 1977: @99318
37438    GIM_Reject,
37439    // Label 41: @99319
37440    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1996*/ 99829,
37441    /*GILLT_v2s32*//*Label 1990*/ 99337, 0, 0,
37442    /*GILLT_v4s16*//*Label 1991*/ 99389,
37443    /*GILLT_v4s32*//*Label 1992*/ 99441, 0, 0,
37444    /*GILLT_v8s8*//*Label 1993*/ 99553,
37445    /*GILLT_v8s16*//*Label 1994*/ 99605, 0, 0,
37446    /*GILLT_v16s8*//*Label 1995*/ 99717,
37447    // Label 1990: @99337
37448    GIM_Try, /*On fail goto*//*Label 1997*/ 99388, // Rule ID 1212 //
37449      GIM_CheckFeatures, GIFBS_HasNEON,
37450      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37451      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
37452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37455      // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv2i32,
37457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37460      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37461      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37462      GIR_EraseFromParent, /*InsnID*/0,
37463      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37464      // GIR_Coverage, 1212,
37465      GIR_Done,
37466    // Label 1997: @99388
37467    GIM_Reject,
37468    // Label 1991: @99389
37469    GIM_Try, /*On fail goto*//*Label 1998*/ 99440, // Rule ID 1211 //
37470      GIM_CheckFeatures, GIFBS_HasNEON,
37471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37472      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
37473      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37476      // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37477      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i16,
37478      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37480      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37481      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37482      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37483      GIR_EraseFromParent, /*InsnID*/0,
37484      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37485      // GIR_Coverage, 1211,
37486      GIR_Done,
37487    // Label 1998: @99440
37488    GIM_Reject,
37489    // Label 1992: @99441
37490    GIM_Try, /*On fail goto*//*Label 1999*/ 99552,
37491      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37492      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
37493      GIM_Try, /*On fail goto*//*Label 2000*/ 99494, // Rule ID 1214 //
37494        GIM_CheckFeatures, GIFBS_HasNEON,
37495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37498        // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i32,
37500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37503        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37504        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37505        GIR_EraseFromParent, /*InsnID*/0,
37506        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37507        // GIR_Coverage, 1214,
37508        GIR_Done,
37509      // Label 2000: @99494
37510      GIM_Try, /*On fail goto*//*Label 2001*/ 99551, // Rule ID 2907 //
37511        GIM_CheckFeatures, GIFBS_HasMVEInt,
37512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37515        // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37516        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37517        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37518        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37519        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu32,
37520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37523        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37524        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37525        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37526        GIR_EraseFromParent, /*InsnID*/0,
37527        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37528        // GIR_Coverage, 2907,
37529        GIR_Done,
37530      // Label 2001: @99551
37531      GIM_Reject,
37532    // Label 1999: @99552
37533    GIM_Reject,
37534    // Label 1993: @99553
37535    GIM_Try, /*On fail goto*//*Label 2002*/ 99604, // Rule ID 1215 //
37536      GIM_CheckFeatures, GIFBS_HasNEON,
37537      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37538      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
37539      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37540      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37541      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37542      // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37543      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i8,
37544      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37545      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37547      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37548      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37549      GIR_EraseFromParent, /*InsnID*/0,
37550      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37551      // GIR_Coverage, 1215,
37552      GIR_Done,
37553    // Label 2002: @99604
37554    GIM_Reject,
37555    // Label 1994: @99605
37556    GIM_Try, /*On fail goto*//*Label 2003*/ 99716,
37557      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
37558      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
37559      GIM_Try, /*On fail goto*//*Label 2004*/ 99658, // Rule ID 1213 //
37560        GIM_CheckFeatures, GIFBS_HasNEON,
37561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37564        // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37565        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i16,
37566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37569        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37570        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37571        GIR_EraseFromParent, /*InsnID*/0,
37572        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37573        // GIR_Coverage, 1213,
37574        GIR_Done,
37575      // Label 2004: @99658
37576      GIM_Try, /*On fail goto*//*Label 2005*/ 99715, // Rule ID 2905 //
37577        GIM_CheckFeatures, GIFBS_HasMVEInt,
37578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37581        // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37582        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37583        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37584        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu16,
37586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37589        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37590        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37591        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37592        GIR_EraseFromParent, /*InsnID*/0,
37593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37594        // GIR_Coverage, 2905,
37595        GIR_Done,
37596      // Label 2005: @99715
37597      GIM_Reject,
37598    // Label 2003: @99716
37599    GIM_Reject,
37600    // Label 1995: @99717
37601    GIM_Try, /*On fail goto*//*Label 2006*/ 99828,
37602      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
37603      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
37604      GIM_Try, /*On fail goto*//*Label 2007*/ 99770, // Rule ID 1216 //
37605        GIM_CheckFeatures, GIFBS_HasNEON,
37606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37609        // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv16i8,
37611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37614        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37615        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37616        GIR_EraseFromParent, /*InsnID*/0,
37617        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37618        // GIR_Coverage, 1216,
37619        GIR_Done,
37620      // Label 2007: @99770
37621      GIM_Try, /*On fail goto*//*Label 2008*/ 99827, // Rule ID 2903 //
37622        GIM_CheckFeatures, GIFBS_HasMVEInt,
37623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37626        // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37627        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37628        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37629        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37630        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu8,
37631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37634        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37635        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37636        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37637        GIR_EraseFromParent, /*InsnID*/0,
37638        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37639        // GIR_Coverage, 2903,
37640        GIR_Done,
37641      // Label 2008: @99827
37642      GIM_Reject,
37643    // Label 2006: @99828
37644    GIM_Reject,
37645    // Label 1996: @99829
37646    GIM_Reject,
37647    // Label 42: @99830
37648    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2015*/ 100340,
37649    /*GILLT_v2s32*//*Label 2009*/ 99848, 0, 0,
37650    /*GILLT_v4s16*//*Label 2010*/ 99900,
37651    /*GILLT_v4s32*//*Label 2011*/ 99952, 0, 0,
37652    /*GILLT_v8s8*//*Label 2012*/ 100064,
37653    /*GILLT_v8s16*//*Label 2013*/ 100116, 0, 0,
37654    /*GILLT_v16s8*//*Label 2014*/ 100228,
37655    // Label 2009: @99848
37656    GIM_Try, /*On fail goto*//*Label 2016*/ 99899, // Rule ID 1192 //
37657      GIM_CheckFeatures, GIFBS_HasNEON,
37658      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37659      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
37660      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37661      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37662      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37663      // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37664      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv2i32,
37665      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37666      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37667      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37668      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37669      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37670      GIR_EraseFromParent, /*InsnID*/0,
37671      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37672      // GIR_Coverage, 1192,
37673      GIR_Done,
37674    // Label 2016: @99899
37675    GIM_Reject,
37676    // Label 2010: @99900
37677    GIM_Try, /*On fail goto*//*Label 2017*/ 99951, // Rule ID 1191 //
37678      GIM_CheckFeatures, GIFBS_HasNEON,
37679      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37680      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
37681      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37682      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37684      // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37685      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i16,
37686      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37687      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37688      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37689      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37690      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37691      GIR_EraseFromParent, /*InsnID*/0,
37692      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37693      // GIR_Coverage, 1191,
37694      GIR_Done,
37695    // Label 2017: @99951
37696    GIM_Reject,
37697    // Label 2011: @99952
37698    GIM_Try, /*On fail goto*//*Label 2018*/ 100063,
37699      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37700      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
37701      GIM_Try, /*On fail goto*//*Label 2019*/ 100005, // Rule ID 1194 //
37702        GIM_CheckFeatures, GIFBS_HasNEON,
37703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37706        // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37707        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i32,
37708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37710        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37711        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37712        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37713        GIR_EraseFromParent, /*InsnID*/0,
37714        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37715        // GIR_Coverage, 1194,
37716        GIR_Done,
37717      // Label 2019: @100005
37718      GIM_Try, /*On fail goto*//*Label 2020*/ 100062, // Rule ID 2919 //
37719        GIM_CheckFeatures, GIFBS_HasMVEInt,
37720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37723        // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37724        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37725        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37726        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu32,
37728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37731        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37732        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37733        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37734        GIR_EraseFromParent, /*InsnID*/0,
37735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37736        // GIR_Coverage, 2919,
37737        GIR_Done,
37738      // Label 2020: @100062
37739      GIM_Reject,
37740    // Label 2018: @100063
37741    GIM_Reject,
37742    // Label 2012: @100064
37743    GIM_Try, /*On fail goto*//*Label 2021*/ 100115, // Rule ID 1195 //
37744      GIM_CheckFeatures, GIFBS_HasNEON,
37745      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37746      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
37747      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37748      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37749      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37750      // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37751      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i8,
37752      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37753      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37754      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37755      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37756      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37757      GIR_EraseFromParent, /*InsnID*/0,
37758      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37759      // GIR_Coverage, 1195,
37760      GIR_Done,
37761    // Label 2021: @100115
37762    GIM_Reject,
37763    // Label 2013: @100116
37764    GIM_Try, /*On fail goto*//*Label 2022*/ 100227,
37765      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
37766      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
37767      GIM_Try, /*On fail goto*//*Label 2023*/ 100169, // Rule ID 1193 //
37768        GIM_CheckFeatures, GIFBS_HasNEON,
37769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37772        // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i16,
37774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37778        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37779        GIR_EraseFromParent, /*InsnID*/0,
37780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37781        // GIR_Coverage, 1193,
37782        GIR_Done,
37783      // Label 2023: @100169
37784      GIM_Try, /*On fail goto*//*Label 2024*/ 100226, // Rule ID 2917 //
37785        GIM_CheckFeatures, GIFBS_HasMVEInt,
37786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37789        // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37790        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37791        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37792        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37793        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu16,
37794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37797        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37798        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37799        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37800        GIR_EraseFromParent, /*InsnID*/0,
37801        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37802        // GIR_Coverage, 2917,
37803        GIR_Done,
37804      // Label 2024: @100226
37805      GIM_Reject,
37806    // Label 2022: @100227
37807    GIM_Reject,
37808    // Label 2014: @100228
37809    GIM_Try, /*On fail goto*//*Label 2025*/ 100339,
37810      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
37811      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
37812      GIM_Try, /*On fail goto*//*Label 2026*/ 100281, // Rule ID 1196 //
37813        GIM_CheckFeatures, GIFBS_HasNEON,
37814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37817        // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv16i8,
37819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37822        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37823        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37824        GIR_EraseFromParent, /*InsnID*/0,
37825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37826        // GIR_Coverage, 1196,
37827        GIR_Done,
37828      // Label 2026: @100281
37829      GIM_Try, /*On fail goto*//*Label 2027*/ 100338, // Rule ID 2915 //
37830        GIM_CheckFeatures, GIFBS_HasMVEInt,
37831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37834        // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37835        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37836        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37837        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu8,
37839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37842        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37843        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37844        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37845        GIR_EraseFromParent, /*InsnID*/0,
37846        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37847        // GIR_Coverage, 2915,
37848        GIR_Done,
37849      // Label 2027: @100338
37850      GIM_Reject,
37851    // Label 2025: @100339
37852    GIM_Reject,
37853    // Label 2015: @100340
37854    GIM_Reject,
37855    // Label 43: @100341
37856    GIM_Try, /*On fail goto*//*Label 2028*/ 100404,
37857      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
37858      GIM_Try, /*On fail goto*//*Label 2029*/ 100357, // Rule ID 34 //
37859        GIM_CheckFeatures, GIFBS_IsARM,
37860        // (br (bb:{ *:[Other] }):$target)  =>  (B (bb:{ *:[Other] }):$target)
37861        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::B,
37862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37863        // GIR_Coverage, 34,
37864        GIR_Done,
37865      // Label 2029: @100357
37866      GIM_Try, /*On fail goto*//*Label 2030*/ 100380, // Rule ID 291 //
37867        GIM_CheckFeatures, GIFBS_IsThumb_IsThumb1Only,
37868        // (br (bb:{ *:[Other] }):$target)  =>  (tB (bb:{ *:[Other] }):$target)
37869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB,
37870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
37871        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37872        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37873        GIR_EraseFromParent, /*InsnID*/0,
37874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37875        // GIR_Coverage, 291,
37876        GIR_Done,
37877      // Label 2030: @100380
37878      GIM_Try, /*On fail goto*//*Label 2031*/ 100403, // Rule ID 592 //
37879        GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
37880        // (br (bb:{ *:[Other] }):$target)  =>  (t2B (bb:{ *:[Other] }):$target)
37881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B,
37882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
37883        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37884        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37885        GIR_EraseFromParent, /*InsnID*/0,
37886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37887        // GIR_Coverage, 592,
37888        GIR_Done,
37889      // Label 2031: @100403
37890      GIM_Reject,
37891    // Label 2028: @100404
37892    GIM_Reject,
37893    // Label 44: @100405
37894    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2039*/ 100899,
37895    /*GILLT_s32*//*Label 2032*/ 100425, 0,
37896    /*GILLT_v2s32*//*Label 2033*/ 100503, 0, 0,
37897    /*GILLT_v4s16*//*Label 2034*/ 100543,
37898    /*GILLT_v4s32*//*Label 2035*/ 100583, 0, 0,
37899    /*GILLT_v8s8*//*Label 2036*/ 100675,
37900    /*GILLT_v8s16*//*Label 2037*/ 100715, 0, 0,
37901    /*GILLT_v16s8*//*Label 2038*/ 100807,
37902    // Label 2032: @100425
37903    GIM_Try, /*On fail goto*//*Label 2040*/ 100502,
37904      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37905      GIM_Try, /*On fail goto*//*Label 2041*/ 100466, // Rule ID 199 //
37906        GIM_CheckFeatures, GIFBS_HasV5T_IsARM,
37907        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
37908        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
37909        // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
37910        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLZ,
37911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37913        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37914        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37915        GIR_EraseFromParent, /*InsnID*/0,
37916        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37917        // GIR_Coverage, 199,
37918        GIR_Done,
37919      // Label 2041: @100466
37920      GIM_Try, /*On fail goto*//*Label 2042*/ 100501, // Rule ID 540 //
37921        GIM_CheckFeatures, GIFBS_IsThumb2,
37922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37924        // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
37925        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLZ,
37926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37928        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37929        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37930        GIR_EraseFromParent, /*InsnID*/0,
37931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37932        // GIR_Coverage, 540,
37933        GIR_Done,
37934      // Label 2042: @100501
37935      GIM_Reject,
37936    // Label 2040: @100502
37937    GIM_Reject,
37938    // Label 2033: @100503
37939    GIM_Try, /*On fail goto*//*Label 2043*/ 100542, // Rule ID 1536 //
37940      GIM_CheckFeatures, GIFBS_HasNEON,
37941      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37942      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37943      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37944      // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
37945      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv2i32,
37946      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37947      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37948      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37949      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37950      GIR_EraseFromParent, /*InsnID*/0,
37951      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37952      // GIR_Coverage, 1536,
37953      GIR_Done,
37954    // Label 2043: @100542
37955    GIM_Reject,
37956    // Label 2034: @100543
37957    GIM_Try, /*On fail goto*//*Label 2044*/ 100582, // Rule ID 1535 //
37958      GIM_CheckFeatures, GIFBS_HasNEON,
37959      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37961      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37962      // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
37963      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i16,
37964      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37965      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37966      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37967      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37968      GIR_EraseFromParent, /*InsnID*/0,
37969      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37970      // GIR_Coverage, 1535,
37971      GIR_Done,
37972    // Label 2044: @100582
37973    GIM_Reject,
37974    // Label 2035: @100583
37975    GIM_Try, /*On fail goto*//*Label 2045*/ 100674,
37976      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37977      GIM_Try, /*On fail goto*//*Label 2046*/ 100624, // Rule ID 1539 //
37978        GIM_CheckFeatures, GIFBS_HasNEON,
37979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37981        // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
37982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i32,
37983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37985        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37986        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
37987        GIR_EraseFromParent, /*InsnID*/0,
37988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37989        // GIR_Coverage, 1539,
37990        GIR_Done,
37991      // Label 2046: @100624
37992      GIM_Try, /*On fail goto*//*Label 2047*/ 100673, // Rule ID 3111 //
37993        GIM_CheckFeatures, GIFBS_HasMVEInt,
37994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37996        // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1)  =>  (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1)
37997        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37998        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37999        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38000        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs32,
38001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38003        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38004        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38005        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38006        GIR_EraseFromParent, /*InsnID*/0,
38007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38008        // GIR_Coverage, 3111,
38009        GIR_Done,
38010      // Label 2047: @100673
38011      GIM_Reject,
38012    // Label 2045: @100674
38013    GIM_Reject,
38014    // Label 2036: @100675
38015    GIM_Try, /*On fail goto*//*Label 2048*/ 100714, // Rule ID 1534 //
38016      GIM_CheckFeatures, GIFBS_HasNEON,
38017      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38018      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38020      // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
38021      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i8,
38022      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38024      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38025      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38026      GIR_EraseFromParent, /*InsnID*/0,
38027      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38028      // GIR_Coverage, 1534,
38029      GIR_Done,
38030    // Label 2048: @100714
38031    GIM_Reject,
38032    // Label 2037: @100715
38033    GIM_Try, /*On fail goto*//*Label 2049*/ 100806,
38034      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38035      GIM_Try, /*On fail goto*//*Label 2050*/ 100756, // Rule ID 1538 //
38036        GIM_CheckFeatures, GIFBS_HasNEON,
38037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38039        // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
38040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i16,
38041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38043        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38044        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38045        GIR_EraseFromParent, /*InsnID*/0,
38046        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38047        // GIR_Coverage, 1538,
38048        GIR_Done,
38049      // Label 2050: @100756
38050      GIM_Try, /*On fail goto*//*Label 2051*/ 100805, // Rule ID 3112 //
38051        GIM_CheckFeatures, GIFBS_HasMVEInt,
38052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38054        // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1)  =>  (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1)
38055        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38056        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38057        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs16,
38059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38061        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38062        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38063        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38064        GIR_EraseFromParent, /*InsnID*/0,
38065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38066        // GIR_Coverage, 3112,
38067        GIR_Done,
38068      // Label 2051: @100805
38069      GIM_Reject,
38070    // Label 2049: @100806
38071    GIM_Reject,
38072    // Label 2038: @100807
38073    GIM_Try, /*On fail goto*//*Label 2052*/ 100898,
38074      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38075      GIM_Try, /*On fail goto*//*Label 2053*/ 100848, // Rule ID 1537 //
38076        GIM_CheckFeatures, GIFBS_HasNEON,
38077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38079        // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
38080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv16i8,
38081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38083        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38084        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38085        GIR_EraseFromParent, /*InsnID*/0,
38086        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38087        // GIR_Coverage, 1537,
38088        GIR_Done,
38089      // Label 2053: @100848
38090      GIM_Try, /*On fail goto*//*Label 2054*/ 100897, // Rule ID 3110 //
38091        GIM_CheckFeatures, GIFBS_HasMVEInt,
38092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38094        // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1)  =>  (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1)
38095        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38096        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38097        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38098        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs8,
38099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38101        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38102        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38103        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38104        GIR_EraseFromParent, /*InsnID*/0,
38105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38106        // GIR_Coverage, 3110,
38107        GIR_Done,
38108      // Label 2054: @100897
38109      GIM_Reject,
38110    // Label 2052: @100898
38111    GIM_Reject,
38112    // Label 2039: @100899
38113    GIM_Reject,
38114    // Label 45: @100900
38115    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/10, 15, /*)*//*default:*//*Label 2057*/ 100991,
38116    /*GILLT_v8s8*//*Label 2055*/ 100911, 0, 0, 0,
38117    /*GILLT_v16s8*//*Label 2056*/ 100951,
38118    // Label 2055: @100911
38119    GIM_Try, /*On fail goto*//*Label 2058*/ 100950, // Rule ID 1540 //
38120      GIM_CheckFeatures, GIFBS_HasNEON,
38121      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38122      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38124      // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
38125      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTd,
38126      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38127      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38128      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38129      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38130      GIR_EraseFromParent, /*InsnID*/0,
38131      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38132      // GIR_Coverage, 1540,
38133      GIR_Done,
38134    // Label 2058: @100950
38135    GIM_Reject,
38136    // Label 2056: @100951
38137    GIM_Try, /*On fail goto*//*Label 2059*/ 100990, // Rule ID 1541 //
38138      GIM_CheckFeatures, GIFBS_HasNEON,
38139      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38141      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38142      // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
38143      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTq,
38144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38145      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38146      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38147      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38148      GIR_EraseFromParent, /*InsnID*/0,
38149      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38150      // GIR_Coverage, 1541,
38151      GIR_Done,
38152    // Label 2059: @100990
38153    GIM_Reject,
38154    // Label 2057: @100991
38155    GIM_Reject,
38156    // Label 46: @100992
38157    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2063*/ 101230,
38158    /*GILLT_s32*//*Label 2060*/ 101009, 0, 0, 0, 0, 0,
38159    /*GILLT_v4s32*//*Label 2061*/ 101122, 0, 0, 0,
38160    /*GILLT_v8s16*//*Label 2062*/ 101176,
38161    // Label 2060: @101009
38162    GIM_Try, /*On fail goto*//*Label 2064*/ 101121,
38163      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38164      GIM_Try, /*On fail goto*//*Label 2065*/ 101050, // Rule ID 201 //
38165        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
38166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38168        // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV,
38170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38172        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38173        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38174        GIR_EraseFromParent, /*InsnID*/0,
38175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38176        // GIR_Coverage, 201,
38177        GIR_Done,
38178      // Label 2065: @101050
38179      GIM_Try, /*On fail goto*//*Label 2066*/ 101085, // Rule ID 334 //
38180        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
38181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
38182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
38183        // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)  =>  (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38184        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV,
38185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38187        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38188        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38189        GIR_EraseFromParent, /*InsnID*/0,
38190        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38191        // GIR_Coverage, 334,
38192        GIR_Done,
38193      // Label 2066: @101085
38194      GIM_Try, /*On fail goto*//*Label 2067*/ 101120, // Rule ID 542 //
38195        GIM_CheckFeatures, GIFBS_IsThumb2,
38196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38198        // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV,
38200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38202        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38203        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38204        GIR_EraseFromParent, /*InsnID*/0,
38205        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38206        // GIR_Coverage, 542,
38207        GIR_Done,
38208      // Label 2067: @101120
38209      GIM_Reject,
38210    // Label 2064: @101121
38211    GIM_Reject,
38212    // Label 2061: @101122
38213    GIM_Try, /*On fail goto*//*Label 2068*/ 101175, // Rule ID 2922 //
38214      GIM_CheckFeatures, GIFBS_HasMVEInt,
38215      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38216      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38217      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38218      // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
38219      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38220      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38221      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38222      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
38223      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38224      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
38225      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38226      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38227      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38228      GIR_EraseFromParent, /*InsnID*/0,
38229      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38230      // GIR_Coverage, 2922,
38231      GIR_Done,
38232    // Label 2068: @101175
38233    GIM_Reject,
38234    // Label 2062: @101176
38235    GIM_Try, /*On fail goto*//*Label 2069*/ 101229, // Rule ID 2921 //
38236      GIM_CheckFeatures, GIFBS_HasMVEInt,
38237      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38240      // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
38241      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38242      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38243      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38244      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
38245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38246      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
38247      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38248      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38249      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38250      GIR_EraseFromParent, /*InsnID*/0,
38251      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38252      // GIR_Coverage, 2921,
38253      GIR_Done,
38254    // Label 2069: @101229
38255    GIM_Reject,
38256    // Label 2063: @101230
38257    GIM_Reject,
38258    // Label 47: @101231
38259    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2074*/ 101581,
38260    /*GILLT_s32*//*Label 2070*/ 101251, 0, 0, 0, 0, 0,
38261    /*GILLT_v4s32*//*Label 2071*/ 101329, 0, 0, 0,
38262    /*GILLT_v8s16*//*Label 2072*/ 101413, 0, 0,
38263    /*GILLT_v16s8*//*Label 2073*/ 101497,
38264    // Label 2070: @101251
38265    GIM_Try, /*On fail goto*//*Label 2075*/ 101328,
38266      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38267      GIM_Try, /*On fail goto*//*Label 2076*/ 101292, // Rule ID 200 //
38268        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
38269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38271        // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RBIT,
38273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38275        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38276        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38277        GIR_EraseFromParent, /*InsnID*/0,
38278        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38279        // GIR_Coverage, 200,
38280        GIR_Done,
38281      // Label 2076: @101292
38282      GIM_Try, /*On fail goto*//*Label 2077*/ 101327, // Rule ID 541 //
38283        GIM_CheckFeatures, GIFBS_IsThumb2,
38284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38286        // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RBIT,
38288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38290        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38291        GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38292        GIR_EraseFromParent, /*InsnID*/0,
38293        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38294        // GIR_Coverage, 541,
38295        GIR_Done,
38296      // Label 2077: @101327
38297      GIM_Reject,
38298    // Label 2075: @101328
38299    GIM_Reject,
38300    // Label 2071: @101329
38301    GIM_Try, /*On fail goto*//*Label 2078*/ 101412, // Rule ID 3676 //
38302      GIM_CheckFeatures, GIFBS_HasMVEInt,
38303      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38304      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38305      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38306      // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1)  =>  (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
38307      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38308      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
38309      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38310      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
38311      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
38312      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
38313      GIR_AddImm, /*InsnID*/1, /*Imm*/32,
38314      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
38315      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38316      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38317      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38318      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
38319      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38320      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38321      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38322      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38323      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38324      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
38325      GIR_EraseFromParent, /*InsnID*/0,
38326      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38327      // GIR_Coverage, 3676,
38328      GIR_Done,
38329    // Label 2078: @101412
38330    GIM_Reject,
38331    // Label 2072: @101413
38332    GIM_Try, /*On fail goto*//*Label 2079*/ 101496, // Rule ID 3677 //
38333      GIM_CheckFeatures, GIFBS_HasMVEInt,
38334      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38335      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38336      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38337      // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1)  =>  (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
38338      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38339      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
38340      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38341      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
38342      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
38343      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
38344      GIR_AddImm, /*InsnID*/1, /*Imm*/16,
38345      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
38346      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38347      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38348      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38349      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
38350      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38351      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38352      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38353      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38354      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38355      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
38356      GIR_EraseFromParent, /*InsnID*/0,
38357      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38358      // GIR_Coverage, 3677,
38359      GIR_Done,
38360    // Label 2079: @101496
38361    GIM_Reject,
38362    // Label 2073: @101497
38363    GIM_Try, /*On fail goto*//*Label 2080*/ 101580, // Rule ID 3675 //
38364      GIM_CheckFeatures, GIFBS_HasMVEInt,
38365      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38366      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38367      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38368      // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1)  =>  (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
38369      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38370      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
38371      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38372      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
38373      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
38374      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
38375      GIR_AddImm, /*InsnID*/1, /*Imm*/8,
38376      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
38377      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38378      GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0,
38379      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38380      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
38381      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38382      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38383      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38384      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38385      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38386      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
38387      GIR_EraseFromParent, /*InsnID*/0,
38388      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38389      // GIR_Coverage, 3675,
38390      GIR_Done,
38391    // Label 2080: @101580
38392    GIM_Reject,
38393    // Label 2074: @101581
38394    GIM_Reject,
38395    // Label 48: @101582
38396    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2086*/ 101780,
38397    /*GILLT_s16*//*Label 2081*/ 101600,
38398    /*GILLT_s32*//*Label 2082*/ 101624,
38399    /*GILLT_s64*//*Label 2083*/ 101648, 0, 0, 0, 0,
38400    /*GILLT_v4s32*//*Label 2084*/ 101672, 0, 0, 0,
38401    /*GILLT_v8s16*//*Label 2085*/ 101726,
38402    // Label 2081: @101600
38403    GIM_Try, /*On fail goto*//*Label 2087*/ 101623, // Rule ID 693 //
38404      GIM_CheckFeatures, GIFBS_HasFullFP16,
38405      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
38406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
38407      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
38408      // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
38409      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPH,
38410      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38411      // GIR_Coverage, 693,
38412      GIR_Done,
38413    // Label 2087: @101623
38414    GIM_Reject,
38415    // Label 2082: @101624
38416    GIM_Try, /*On fail goto*//*Label 2088*/ 101647, // Rule ID 694 //
38417      GIM_CheckFeatures, GIFBS_HasFPARMv8,
38418      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38419      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38420      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
38421      // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
38422      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPS,
38423      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38424      // GIR_Coverage, 694,
38425      GIR_Done,
38426    // Label 2088: @101647
38427    GIM_Reject,
38428    // Label 2083: @101648
38429    GIM_Try, /*On fail goto*//*Label 2089*/ 101671, // Rule ID 695 //
38430      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
38431      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38432      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38434      // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
38435      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPD,
38436      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38437      // GIR_Coverage, 695,
38438      GIR_Done,
38439    // Label 2089: @101671
38440    GIM_Reject,
38441    // Label 2084: @101672
38442    GIM_Try, /*On fail goto*//*Label 2090*/ 101725, // Rule ID 3370 //
38443      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38444      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38445      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38446      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38447      // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)  =>  (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)
38448      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38449      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38450      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38451      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32P,
38452      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38453      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38454      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38455      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38456      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38457      GIR_EraseFromParent, /*InsnID*/0,
38458      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38459      // GIR_Coverage, 3370,
38460      GIR_Done,
38461    // Label 2090: @101725
38462    GIM_Reject,
38463    // Label 2085: @101726
38464    GIM_Try, /*On fail goto*//*Label 2091*/ 101779, // Rule ID 3371 //
38465      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38466      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38469      // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)  =>  (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)
38470      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38471      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38472      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38473      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16P,
38474      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38476      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38477      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38478      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38479      GIR_EraseFromParent, /*InsnID*/0,
38480      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38481      // GIR_Coverage, 3371,
38482      GIR_Done,
38483    // Label 2091: @101779
38484    GIM_Reject,
38485    // Label 2086: @101780
38486    GIM_Reject,
38487    // Label 49: @101781
38488    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2095*/ 101910,
38489    /*GILLT_s16*//*Label 2092*/ 101790,
38490    /*GILLT_s32*//*Label 2093*/ 101830,
38491    /*GILLT_s64*//*Label 2094*/ 101870,
38492    // Label 2092: @101790
38493    GIM_Try, /*On fail goto*//*Label 2096*/ 101829, // Rule ID 701 //
38494      GIM_CheckFeatures, GIFBS_HasFullFP16,
38495      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
38496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
38497      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
38498      // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
38499      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTH,
38500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38502      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38503      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38504      GIR_EraseFromParent, /*InsnID*/0,
38505      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38506      // GIR_Coverage, 701,
38507      GIR_Done,
38508    // Label 2096: @101829
38509    GIM_Reject,
38510    // Label 2093: @101830
38511    GIM_Try, /*On fail goto*//*Label 2097*/ 101869, // Rule ID 700 //
38512      GIM_CheckFeatures, GIFBS_HasVFP2,
38513      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
38516      // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
38517      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTS,
38518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38520      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38521      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38522      GIR_EraseFromParent, /*InsnID*/0,
38523      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38524      // GIR_Coverage, 700,
38525      GIR_Done,
38526    // Label 2097: @101869
38527    GIM_Reject,
38528    // Label 2094: @101870
38529    GIM_Try, /*On fail goto*//*Label 2098*/ 101909, // Rule ID 699 //
38530      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
38531      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38532      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38533      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38534      // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
38535      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTD,
38536      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
38537      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
38538      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38539      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38540      GIR_EraseFromParent, /*InsnID*/0,
38541      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38542      // GIR_Coverage, 699,
38543      GIR_Done,
38544    // Label 2098: @101909
38545    GIM_Reject,
38546    // Label 2095: @101910
38547    GIM_Reject,
38548    // Label 50: @101911
38549    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2104*/ 102109,
38550    /*GILLT_s16*//*Label 2099*/ 101929,
38551    /*GILLT_s32*//*Label 2100*/ 101953,
38552    /*GILLT_s64*//*Label 2101*/ 101977, 0, 0, 0, 0,
38553    /*GILLT_v4s32*//*Label 2102*/ 102001, 0, 0, 0,
38554    /*GILLT_v8s16*//*Label 2103*/ 102055,
38555    // Label 2099: @101929
38556    GIM_Try, /*On fail goto*//*Label 2105*/ 101952, // Rule ID 696 //
38557      GIM_CheckFeatures, GIFBS_HasFullFP16,
38558      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
38559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
38560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
38561      // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
38562      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMH,
38563      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38564      // GIR_Coverage, 696,
38565      GIR_Done,
38566    // Label 2105: @101952
38567    GIM_Reject,
38568    // Label 2100: @101953
38569    GIM_Try, /*On fail goto*//*Label 2106*/ 101976, // Rule ID 697 //
38570      GIM_CheckFeatures, GIFBS_HasFPARMv8,
38571      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38572      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38573      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
38574      // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
38575      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMS,
38576      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38577      // GIR_Coverage, 697,
38578      GIR_Done,
38579    // Label 2106: @101976
38580    GIM_Reject,
38581    // Label 2101: @101977
38582    GIM_Try, /*On fail goto*//*Label 2107*/ 102000, // Rule ID 698 //
38583      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
38584      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38585      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38586      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38587      // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
38588      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMD,
38589      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38590      // GIR_Coverage, 698,
38591      GIR_Done,
38592    // Label 2107: @102000
38593    GIM_Reject,
38594    // Label 2102: @102001
38595    GIM_Try, /*On fail goto*//*Label 2108*/ 102054, // Rule ID 3368 //
38596      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38597      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38600      // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)  =>  (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)
38601      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38602      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38603      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38604      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32M,
38605      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38606      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38607      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38608      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38609      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38610      GIR_EraseFromParent, /*InsnID*/0,
38611      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38612      // GIR_Coverage, 3368,
38613      GIR_Done,
38614    // Label 2108: @102054
38615    GIM_Reject,
38616    // Label 2103: @102055
38617    GIM_Try, /*On fail goto*//*Label 2109*/ 102108, // Rule ID 3369 //
38618      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38619      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38620      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38621      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38622      // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)  =>  (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)
38623      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38624      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38625      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38626      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16M,
38627      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38628      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38629      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38630      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38631      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38632      GIR_EraseFromParent, /*InsnID*/0,
38633      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38634      // GIR_Coverage, 3369,
38635      GIR_Done,
38636    // Label 2109: @102108
38637    GIM_Reject,
38638    // Label 2104: @102109
38639    GIM_Reject,
38640    // Label 51: @102110
38641    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2115*/ 102356,
38642    /*GILLT_s16*//*Label 2110*/ 102128,
38643    /*GILLT_s32*//*Label 2111*/ 102168,
38644    /*GILLT_s64*//*Label 2112*/ 102208, 0, 0, 0, 0,
38645    /*GILLT_v4s32*//*Label 2113*/ 102248, 0, 0, 0,
38646    /*GILLT_v8s16*//*Label 2114*/ 102302,
38647    // Label 2110: @102128
38648    GIM_Try, /*On fail goto*//*Label 2116*/ 102167, // Rule ID 684 //
38649      GIM_CheckFeatures, GIFBS_HasFullFP16,
38650      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
38651      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
38652      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
38653      // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
38654      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXH,
38655      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38656      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38657      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38658      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38659      GIR_EraseFromParent, /*InsnID*/0,
38660      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38661      // GIR_Coverage, 684,
38662      GIR_Done,
38663    // Label 2116: @102167
38664    GIM_Reject,
38665    // Label 2111: @102168
38666    GIM_Try, /*On fail goto*//*Label 2117*/ 102207, // Rule ID 685 //
38667      GIM_CheckFeatures, GIFBS_HasFPARMv8,
38668      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38669      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38670      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
38671      // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
38672      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXS,
38673      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38674      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38675      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38676      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38677      GIR_EraseFromParent, /*InsnID*/0,
38678      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38679      // GIR_Coverage, 685,
38680      GIR_Done,
38681    // Label 2117: @102207
38682    GIM_Reject,
38683    // Label 2112: @102208
38684    GIM_Try, /*On fail goto*//*Label 2118*/ 102247, // Rule ID 686 //
38685      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
38686      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38687      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38688      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38689      // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
38690      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXD,
38691      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
38692      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
38693      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38694      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38695      GIR_EraseFromParent, /*InsnID*/0,
38696      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38697      // GIR_Coverage, 686,
38698      GIR_Done,
38699    // Label 2118: @102247
38700    GIM_Reject,
38701    // Label 2113: @102248
38702    GIM_Try, /*On fail goto*//*Label 2119*/ 102301, // Rule ID 3362 //
38703      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38704      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38705      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38706      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38707      // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)  =>  (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1)
38708      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38709      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38710      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38711      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32X,
38712      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38713      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38714      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38715      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38716      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38717      GIR_EraseFromParent, /*InsnID*/0,
38718      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38719      // GIR_Coverage, 3362,
38720      GIR_Done,
38721    // Label 2119: @102301
38722    GIM_Reject,
38723    // Label 2114: @102302
38724    GIM_Try, /*On fail goto*//*Label 2120*/ 102355, // Rule ID 3363 //
38725      GIM_CheckFeatures, GIFBS_HasMVEFloat,
38726      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38729      // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)  =>  (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1)
38730      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38731      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38732      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38733      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16X,
38734      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
38736      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38737      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38738      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38739      GIR_EraseFromParent, /*InsnID*/0,
38740      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38741      // GIR_Coverage, 3363,
38742      GIR_Done,
38743    // Label 2120: @102355
38744    GIM_Reject,
38745    // Label 2115: @102356
38746    GIM_Reject,
38747    // Label 52: @102357
38748    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2124*/ 102486,
38749    /*GILLT_s16*//*Label 2121*/ 102366,
38750    /*GILLT_s32*//*Label 2122*/ 102406,
38751    /*GILLT_s64*//*Label 2123*/ 102446,
38752    // Label 2121: @102366
38753    GIM_Try, /*On fail goto*//*Label 2125*/ 102405, // Rule ID 681 //
38754      GIM_CheckFeatures, GIFBS_HasFullFP16,
38755      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
38756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
38757      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
38758      // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
38759      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRH,
38760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38761      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38762      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38763      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38764      GIR_EraseFromParent, /*InsnID*/0,
38765      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38766      // GIR_Coverage, 681,
38767      GIR_Done,
38768    // Label 2125: @102405
38769    GIM_Reject,
38770    // Label 2122: @102406
38771    GIM_Try, /*On fail goto*//*Label 2126*/ 102445, // Rule ID 682 //
38772      GIM_CheckFeatures, GIFBS_HasFPARMv8,
38773      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38775      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
38776      // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
38777      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRS,
38778      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38779      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
38780      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38781      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38782      GIR_EraseFromParent, /*InsnID*/0,
38783      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38784      // GIR_Coverage, 682,
38785      GIR_Done,
38786    // Label 2126: @102445
38787    GIM_Reject,
38788    // Label 2123: @102446
38789    GIM_Try, /*On fail goto*//*Label 2127*/ 102485, // Rule ID 683 //
38790      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
38791      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38792      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38793      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38794      // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
38795      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRD,
38796      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
38797      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
38798      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38799      GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
38800      GIR_EraseFromParent, /*InsnID*/0,
38801      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38802      // GIR_Coverage, 683,
38803      GIR_Done,
38804    // Label 2127: @102485
38805    GIM_Reject,
38806    // Label 2124: @102486
38807    GIM_Reject,
38808    // Label 53: @102487
38809    GIM_Reject,
38810    };
38811  return MatchTable0;
38812}
38813#endif // ifdef GET_GLOBALISEL_IMPL
38814#ifdef GET_GLOBALISEL_PREDICATES_DECL
38815PredicateBitset AvailableModuleFeatures;
38816mutable PredicateBitset AvailableFunctionFeatures;
38817PredicateBitset getAvailableFeatures() const {
38818  return AvailableModuleFeatures | AvailableFunctionFeatures;
38819}
38820PredicateBitset
38821computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
38822PredicateBitset
38823computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
38824                                 const MachineFunction *MF) const;
38825void setupGeneratedPerFunctionState(MachineFunction &MF) override;
38826#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
38827#ifdef GET_GLOBALISEL_PREDICATES_INIT
38828AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
38829AvailableFunctionFeatures()
38830#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
38831