1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Assembly Writer Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 11 12#include <stdio.h> // debug 13#include <capstone/platform.h> 14 15 16/// printInstruction - This method is automatically generated by tablegen 17/// from the instruction set description. 18static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 19{ 20 static const uint32_t OpInfo[] = { 21 0U, // PHI 22 0U, // INLINEASM 23 0U, // CFI_INSTRUCTION 24 0U, // EH_LABEL 25 0U, // GC_LABEL 26 0U, // KILL 27 0U, // EXTRACT_SUBREG 28 0U, // INSERT_SUBREG 29 0U, // IMPLICIT_DEF 30 0U, // SUBREG_TO_REG 31 0U, // COPY_TO_REGCLASS 32 2452U, // DBG_VALUE 33 0U, // REG_SEQUENCE 34 0U, // COPY 35 2445U, // BUNDLE 36 2462U, // LIFETIME_START 37 2432U, // LIFETIME_END 38 0U, // STACKMAP 39 0U, // PATCHPOINT 40 0U, // LOAD_STACK_GUARD 41 0U, // STATEPOINT 42 0U, // FRAME_ALLOC 43 4688U, // ADDCCri 44 4688U, // ADDCCrr 45 5925U, // ADDCri 46 5925U, // ADDCrr 47 4772U, // ADDEri 48 4772U, // ADDErr 49 4786U, // ADDXC 50 4678U, // ADDXCCC 51 4808U, // ADDXri 52 4808U, // ADDXrr 53 4808U, // ADDri 54 4808U, // ADDrr 55 74166U, // ADJCALLSTACKDOWN 56 74185U, // ADJCALLSTACKUP 57 5497U, // ALIGNADDR 58 5127U, // ALIGNADDRL 59 4695U, // ANDCCri 60 4695U, // ANDCCrr 61 4718U, // ANDNCCri 62 4718U, // ANDNCCrr 63 5182U, // ANDNri 64 5182U, // ANDNrr 65 5182U, // ANDXNrr 66 4876U, // ANDXri 67 4876U, // ANDXrr 68 4876U, // ANDri 69 4876U, // ANDrr 70 4502U, // ARRAY16 71 4255U, // ARRAY32 72 4526U, // ARRAY8 73 0U, // ATOMIC_LOAD_ADD_32 74 0U, // ATOMIC_LOAD_ADD_64 75 0U, // ATOMIC_LOAD_AND_32 76 0U, // ATOMIC_LOAD_AND_64 77 0U, // ATOMIC_LOAD_MAX_32 78 0U, // ATOMIC_LOAD_MAX_64 79 0U, // ATOMIC_LOAD_MIN_32 80 0U, // ATOMIC_LOAD_MIN_64 81 0U, // ATOMIC_LOAD_NAND_32 82 0U, // ATOMIC_LOAD_NAND_64 83 0U, // ATOMIC_LOAD_OR_32 84 0U, // ATOMIC_LOAD_OR_64 85 0U, // ATOMIC_LOAD_SUB_32 86 0U, // ATOMIC_LOAD_SUB_64 87 0U, // ATOMIC_LOAD_UMAX_32 88 0U, // ATOMIC_LOAD_UMAX_64 89 0U, // ATOMIC_LOAD_UMIN_32 90 0U, // ATOMIC_LOAD_UMIN_64 91 0U, // ATOMIC_LOAD_XOR_32 92 0U, // ATOMIC_LOAD_XOR_64 93 0U, // ATOMIC_SWAP_64 94 74271U, // BA 95 1194492U, // BCOND 96 1260028U, // BCONDA 97 17659U, // BINDri 98 17659U, // BINDrr 99 5065U, // BMASK 100 145915U, // BPFCC 101 211451U, // BPFCCA 102 276987U, // BPFCCANT 103 342523U, // BPFCCNT 104 2106465U, // BPGEZapn 105 2105838U, // BPGEZapt 106 2106532U, // BPGEZnapn 107 2107288U, // BPGEZnapt 108 2106489U, // BPGZapn 109 2105856U, // BPGZapt 110 2106552U, // BPGZnapn 111 2107384U, // BPGZnapt 112 1456636U, // BPICC 113 473596U, // BPICCA 114 539132U, // BPICCANT 115 604668U, // BPICCNT 116 2106477U, // BPLEZapn 117 2105847U, // BPLEZapt 118 2106542U, // BPLEZnapn 119 2107337U, // BPLEZnapt 120 2106500U, // BPLZapn 121 2105864U, // BPLZapt 122 2106561U, // BPLZnapn 123 2107428U, // BPLZnapt 124 2106511U, // BPNZapn 125 2105872U, // BPNZapt 126 2106570U, // BPNZnapn 127 2107472U, // BPNZnapt 128 1718780U, // BPXCC 129 735740U, // BPXCCA 130 801276U, // BPXCCANT 131 866812U, // BPXCCNT 132 2106522U, // BPZapn 133 2105880U, // BPZapt 134 2106579U, // BPZnapn 135 2107505U, // BPZnapt 136 4983U, // BSHUFFLE 137 74742U, // CALL 138 17398U, // CALLri 139 17398U, // CALLrr 140 924148U, // CASXrr 141 924129U, // CASrr 142 74001U, // CMASK16 143 73833U, // CMASK32 144 74150U, // CMASK8 145 2106607U, // CMPri 146 2106607U, // CMPrr 147 4332U, // EDGE16 148 5081U, // EDGE16L 149 5198U, // EDGE16LN 150 5165U, // EDGE16N 151 4164U, // EDGE32 152 5072U, // EDGE32L 153 5188U, // EDGE32LN 154 5156U, // EDGE32N 155 4511U, // EDGE8 156 5090U, // EDGE8L 157 5208U, // EDGE8LN 158 5174U, // EDGE8N 159 1053516U, // FABSD 160 1054031U, // FABSQ 161 1054376U, // FABSS 162 4813U, // FADDD 163 5383U, // FADDQ 164 5645U, // FADDS 165 4648U, // FALIGNADATA 166 4875U, // FAND 167 4112U, // FANDNOT1 168 5544U, // FANDNOT1S 169 4271U, // FANDNOT2 170 5591U, // FANDNOT2S 171 5677U, // FANDS 172 1194491U, // FBCOND 173 1260027U, // FBCONDA 174 4394U, // FCHKSM16 175 2106173U, // FCMPD 176 4413U, // FCMPEQ16 177 4226U, // FCMPEQ32 178 4432U, // FCMPGT16 179 4245U, // FCMPGT32 180 4340U, // FCMPLE16 181 4172U, // FCMPLE32 182 4350U, // FCMPNE16 183 4182U, // FCMPNE32 184 2106696U, // FCMPQ 185 2107005U, // FCMPS 186 4960U, // FDIVD 187 5475U, // FDIVQ 188 5815U, // FDIVS 189 5405U, // FDMULQ 190 1053620U, // FDTOI 191 1053996U, // FDTOQ 192 1054305U, // FDTOS 193 1054536U, // FDTOX 194 1053464U, // FEXPAND 195 4820U, // FHADDD 196 5652U, // FHADDS 197 4800U, // FHSUBD 198 5637U, // FHSUBS 199 1053473U, // FITOD 200 1054003U, // FITOQ 201 1054312U, // FITOS 202 6300484U, // FLCMPD 203 6301316U, // FLCMPS 204 2606U, // FLUSHW 205 4404U, // FMEAN16 206 1053543U, // FMOVD 207 1006078U, // FMOVD_FCC 208 23484926U, // FMOVD_ICC 209 23747070U, // FMOVD_XCC 210 1054058U, // FMOVQ 211 1006102U, // FMOVQ_FCC 212 23484950U, // FMOVQ_ICC 213 23747094U, // FMOVQ_XCC 214 6018U, // FMOVRGEZD 215 6029U, // FMOVRGEZQ 216 6056U, // FMOVRGEZS 217 6116U, // FMOVRGZD 218 6126U, // FMOVRGZQ 219 6150U, // FMOVRGZS 220 6067U, // FMOVRLEZD 221 6078U, // FMOVRLEZQ 222 6105U, // FMOVRLEZS 223 6160U, // FMOVRLZD 224 6170U, // FMOVRLZQ 225 6194U, // FMOVRLZS 226 6204U, // FMOVRNZD 227 6214U, // FMOVRNZQ 228 6238U, // FMOVRNZS 229 6009U, // FMOVRZD 230 6248U, // FMOVRZQ 231 6269U, // FMOVRZS 232 1054398U, // FMOVS 233 1006114U, // FMOVS_FCC 234 23484962U, // FMOVS_ICC 235 23747106U, // FMOVS_XCC 236 4490U, // FMUL8SUX16 237 4465U, // FMUL8ULX16 238 4442U, // FMUL8X16 239 5098U, // FMUL8X16AL 240 5849U, // FMUL8X16AU 241 4860U, // FMULD 242 4477U, // FMULD8SUX16 243 4452U, // FMULD8ULX16 244 5413U, // FMULQ 245 5714U, // FMULS 246 4837U, // FNADDD 247 5669U, // FNADDS 248 4881U, // FNAND 249 5684U, // FNANDS 250 1053429U, // FNEGD 251 1053974U, // FNEGQ 252 1054283U, // FNEGS 253 4828U, // FNHADDD 254 5660U, // FNHADDS 255 4828U, // FNMULD 256 5660U, // FNMULS 257 5513U, // FNOR 258 5778U, // FNORS 259 1052698U, // FNOT1 260 1054131U, // FNOT1S 261 1052857U, // FNOT2 262 1054178U, // FNOT2S 263 5660U, // FNSMULD 264 74625U, // FONE 265 75324U, // FONES 266 5508U, // FOR 267 4129U, // FORNOT1 268 5563U, // FORNOT1S 269 4288U, // FORNOT2 270 5610U, // FORNOT2S 271 5772U, // FORS 272 1052936U, // FPACK16 273 4192U, // FPACK32 274 1054507U, // FPACKFIX 275 4323U, // FPADD16 276 5620U, // FPADD16S 277 4155U, // FPADD32 278 5573U, // FPADD32S 279 4297U, // FPADD64 280 4974U, // FPMERGE 281 4314U, // FPSUB16 282 4580U, // FPSUB16S 283 4146U, // FPSUB32 284 4570U, // FPSUB32S 285 1053480U, // FQTOD 286 1053627U, // FQTOI 287 1054319U, // FQTOS 288 1054552U, // FQTOX 289 4423U, // FSLAS16 290 4236U, // FSLAS32 291 4378U, // FSLL16 292 4210U, // FSLL32 293 4867U, // FSMULD 294 1053523U, // FSQRTD 295 1054038U, // FSQRTQ 296 1054383U, // FSQRTS 297 4306U, // FSRA16 298 4138U, // FSRA32 299 1052681U, // FSRC1 300 1054112U, // FSRC1S 301 1052840U, // FSRC2 302 1054159U, // FSRC2S 303 4386U, // FSRL16 304 4218U, // FSRL32 305 1053487U, // FSTOD 306 1053634U, // FSTOI 307 1054010U, // FSTOQ 308 1054559U, // FSTOX 309 4793U, // FSUBD 310 5376U, // FSUBQ 311 5630U, // FSUBS 312 5519U, // FXNOR 313 5785U, // FXNORS 314 5526U, // FXOR 315 5793U, // FXORS 316 1053494U, // FXTOD 317 1054017U, // FXTOQ 318 1054326U, // FXTOS 319 74984U, // FZERO 320 75353U, // FZEROS 321 24584U, // GETPCX 322 1078273U, // JMPLri 323 1078273U, // JMPLrr 324 1997243U, // LDDFri 325 1997243U, // LDDFrr 326 1997249U, // LDFri 327 1997249U, // LDFrr 328 1997275U, // LDQFri 329 1997275U, // LDQFrr 330 1997229U, // LDSBri 331 1997229U, // LDSBrr 332 1997254U, // LDSHri 333 1997254U, // LDSHrr 334 1997287U, // LDSWri 335 1997287U, // LDSWrr 336 1997236U, // LDUBri 337 1997236U, // LDUBrr 338 1997261U, // LDUHri 339 1997261U, // LDUHrr 340 1997294U, // LDXri 341 1997294U, // LDXrr 342 1997249U, // LDri 343 1997249U, // LDrr 344 33480U, // LEAX_ADDri 345 33480U, // LEA_ADDri 346 1054405U, // LZCNT 347 75121U, // MEMBARi 348 1054543U, // MOVDTOX 349 1006122U, // MOVFCCri 350 1006122U, // MOVFCCrr 351 23484970U, // MOVICCri 352 23484970U, // MOVICCrr 353 6047U, // MOVRGEZri 354 6047U, // MOVRGEZrr 355 6142U, // MOVRGZri 356 6142U, // MOVRGZrr 357 6096U, // MOVRLEZri 358 6096U, // MOVRLEZrr 359 6186U, // MOVRLZri 360 6186U, // MOVRLZrr 361 6230U, // MOVRNZri 362 6230U, // MOVRNZrr 363 6262U, // MOVRRZri 364 6262U, // MOVRRZrr 365 1054469U, // MOVSTOSW 366 1054479U, // MOVSTOUW 367 1054543U, // MOVWTOS 368 23747114U, // MOVXCCri 369 23747114U, // MOVXCCrr 370 1054543U, // MOVXTOD 371 5954U, // MULXri 372 5954U, // MULXrr 373 2578U, // NOP 374 4735U, // ORCCri 375 4735U, // ORCCrr 376 4726U, // ORNCCri 377 4726U, // ORNCCrr 378 5339U, // ORNri 379 5339U, // ORNrr 380 5339U, // ORXNrr 381 5509U, // ORXri 382 5509U, // ORXrr 383 5509U, // ORri 384 5509U, // ORrr 385 5836U, // PDIST 386 5344U, // PDISTN 387 1053356U, // POPCrr 388 73729U, // RDY 389 4999U, // RESTOREri 390 4999U, // RESTORErr 391 76132U, // RET 392 76141U, // RETL 393 18131U, // RETTri 394 18131U, // RETTrr 395 5008U, // SAVEri 396 5008U, // SAVErr 397 4748U, // SDIVCCri 398 4748U, // SDIVCCrr 399 5995U, // SDIVXri 400 5995U, // SDIVXrr 401 5861U, // SDIVri 402 5861U, // SDIVrr 403 2182U, // SELECT_CC_DFP_FCC 404 2293U, // SELECT_CC_DFP_ICC 405 2238U, // SELECT_CC_FP_FCC 406 2349U, // SELECT_CC_FP_ICC 407 2265U, // SELECT_CC_Int_FCC 408 2376U, // SELECT_CC_Int_ICC 409 2210U, // SELECT_CC_QFP_FCC 410 2321U, // SELECT_CC_QFP_ICC 411 1053595U, // SETHIXi 412 1053595U, // SETHIi 413 2569U, // SHUTDOWN 414 2564U, // SIAM 415 5941U, // SLLXri 416 5941U, // SLLXrr 417 5116U, // SLLri 418 5116U, // SLLrr 419 4702U, // SMULCCri 420 4702U, // SMULCCrr 421 5144U, // SMULri 422 5144U, // SMULrr 423 5913U, // SRAXri 424 5913U, // SRAXrr 425 4643U, // SRAri 426 4643U, // SRArr 427 5947U, // SRLXri 428 5947U, // SRLXrr 429 5139U, // SRLri 430 5139U, // SRLrr 431 2588U, // STBAR 432 37428U, // STBri 433 37428U, // STBrr 434 37723U, // STDFri 435 37723U, // STDFrr 436 38607U, // STFri 437 38607U, // STFrr 438 37782U, // STHri 439 37782U, // STHrr 440 38238U, // STQFri 441 38238U, // STQFrr 442 38758U, // STXri 443 38758U, // STXrr 444 38607U, // STri 445 38607U, // STrr 446 4671U, // SUBCCri 447 4671U, // SUBCCrr 448 5919U, // SUBCri 449 5919U, // SUBCrr 450 4764U, // SUBEri 451 4764U, // SUBErr 452 4665U, // SUBXri 453 4665U, // SUBXrr 454 4665U, // SUBri 455 4665U, // SUBrr 456 1997268U, // SWAPri 457 1997268U, // SWAPrr 458 2422U, // TA3 459 2427U, // TA5 460 5883U, // TADDCCTVri 461 5883U, // TADDCCTVrr 462 4687U, // TADDCCri 463 4687U, // TADDCCrr 464 9873960U, // TICCri 465 9873960U, // TICCrr 466 37753544U, // TLS_ADDXrr 467 37753544U, // TLS_ADDrr 468 2106358U, // TLS_CALL 469 39746030U, // TLS_LDXrr 470 39745985U, // TLS_LDrr 471 5873U, // TSUBCCTVri 472 5873U, // TSUBCCTVrr 473 4670U, // TSUBCCri 474 4670U, // TSUBCCrr 475 10136104U, // TXCCri 476 10136104U, // TXCCrr 477 4756U, // UDIVCCri 478 4756U, // UDIVCCrr 479 6002U, // UDIVXri 480 6002U, // UDIVXrr 481 5867U, // UDIVri 482 5867U, // UDIVrr 483 4710U, // UMULCCri 484 4710U, // UMULCCrr 485 5026U, // UMULXHI 486 5150U, // UMULri 487 5150U, // UMULrr 488 74996U, // UNIMP 489 6300477U, // V9FCMPD 490 6300397U, // V9FCMPED 491 6300942U, // V9FCMPEQ 492 6301251U, // V9FCMPES 493 6301000U, // V9FCMPQ 494 6301309U, // V9FCMPS 495 47614U, // V9FMOVD_FCC 496 47638U, // V9FMOVQ_FCC 497 47650U, // V9FMOVS_FCC 498 47658U, // V9MOVFCCri 499 47658U, // V9MOVFCCrr 500 14689692U, // WRYri 501 14689692U, // WRYrr 502 5953U, // XMULX 503 5035U, // XMULXHI 504 4733U, // XNORCCri 505 4733U, // XNORCCrr 506 5520U, // XNORXrr 507 5520U, // XNORri 508 5520U, // XNORrr 509 4741U, // XORCCri 510 4741U, // XORCCrr 511 5527U, // XORXri 512 5527U, // XORXrr 513 5527U, // XORri 514 5527U, // XORrr 515 0U 516 }; 517 518#ifndef CAPSTONE_DIET 519 static const char AsmStrs[] = { 520 /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0, 521 /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0, 522 /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0, 523 /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0, 524 /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0, 525 /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0, 526 /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0, 527 /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0, 528 /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0, 529 /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0, 530 /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0, 531 /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0, 532 /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0, 533 /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0, 534 /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0, 535 /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0, 536 /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0, 537 /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0, 538 /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0, 539 /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0, 540 /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0, 541 /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0, 542 /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0, 543 /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0, 544 /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0, 545 /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0, 546 /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0, 547 /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0, 548 /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0, 549 /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0, 550 /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0, 551 /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0, 552 /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0, 553 /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0, 554 /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0, 555 /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0, 556 /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0, 557 /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0, 558 /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0, 559 /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0, 560 /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0, 561 /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0, 562 /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0, 563 /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0, 564 /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0, 565 /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0, 566 /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0, 567 /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0, 568 /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, 569 /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, 570 /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0, 571 /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0, 572 /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0, 573 /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0, 574 /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0, 575 /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0, 576 /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0, 577 /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0, 578 /* 542 */ 'b', 'a', 32, 0, 579 /* 546 */ 's', 'r', 'a', 32, 0, 580 /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0, 581 /* 563 */ 's', 't', 'b', 32, 0, 582 /* 568 */ 's', 'u', 'b', 32, 0, 583 /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0, 584 /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0, 585 /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0, 586 /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0, 587 /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0, 588 /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0, 589 /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0, 590 /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0, 591 /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0, 592 /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0, 593 /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0, 594 /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0, 595 /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0, 596 /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0, 597 /* 683 */ 'p', 'o', 'p', 'c', 32, 0, 598 /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0, 599 /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0, 600 /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0, 601 /* 711 */ 'a', 'd', 'd', 32, 0, 602 /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0, 603 /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0, 604 /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0, 605 /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0, 606 /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0, 607 /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0, 608 /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0, 609 /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0, 610 /* 778 */ 'f', 'a', 'n', 'd', 32, 0, 611 /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0, 612 /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0, 613 /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0, 614 /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0, 615 /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0, 616 /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0, 617 /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0, 618 /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0, 619 /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0, 620 /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0, 621 /* 858 */ 's', 't', 'd', 32, 0, 622 /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0, 623 /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0, 624 /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0, 625 /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0, 626 /* 896 */ 'f', 'o', 'n', 'e', 32, 0, 627 /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0, 628 /* 911 */ 's', 'a', 'v', 'e', 32, 0, 629 /* 917 */ 's', 't', 'h', 32, 0, 630 /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0, 631 /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, 632 /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, 633 /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0, 634 /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0, 635 /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0, 636 /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0, 637 /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0, 638 /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0, 639 /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0, 640 /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0, 641 /* 1013 */ 'c', 'a', 'l', 'l', 32, 0, 642 /* 1019 */ 's', 'l', 'l', 32, 0, 643 /* 1024 */ 'j', 'm', 'p', 'l', 32, 0, 644 /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0, 645 /* 1042 */ 's', 'r', 'l', 32, 0, 646 /* 1047 */ 's', 'm', 'u', 'l', 32, 0, 647 /* 1053 */ 'u', 'm', 'u', 'l', 32, 0, 648 /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0, 649 /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0, 650 /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0, 651 /* 1085 */ 'a', 'n', 'd', 'n', 32, 0, 652 /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0, 653 /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0, 654 /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0, 655 /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 656 /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 657 /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 658 /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 659 /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 660 /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0, 661 /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0, 662 /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0, 663 /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0, 664 /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0, 665 /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0, 666 /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0, 667 /* 1242 */ 'o', 'r', 'n', 32, 0, 668 /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0, 669 /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0, 670 /* 1262 */ 'c', 'm', 'p', 32, 0, 671 /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0, 672 /* 1274 */ 'j', 'm', 'p', 32, 0, 673 /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0, 674 /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0, 675 /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, 676 /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0, 677 /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0, 678 /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0, 679 /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0, 680 /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0, 681 /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0, 682 /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0, 683 /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0, 684 /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0, 685 /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0, 686 /* 1373 */ 's', 't', 'q', 32, 0, 687 /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0, 688 /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0, 689 /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0, 690 /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0, 691 /* 1411 */ 'f', 'o', 'r', 32, 0, 692 /* 1416 */ 'f', 'n', 'o', 'r', 32, 0, 693 /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0, 694 /* 1429 */ 'f', 'x', 'o', 'r', 32, 0, 695 /* 1435 */ 'w', 'r', 32, 0, 696 /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0, 697 /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0, 698 /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0, 699 /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0, 700 /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0, 701 /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0, 702 /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0, 703 /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0, 704 /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0, 705 /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0, 706 /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0, 707 /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0, 708 /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0, 709 /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0, 710 /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0, 711 /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0, 712 /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0, 713 /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0, 714 /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0, 715 /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0, 716 /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0, 717 /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0, 718 /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0, 719 /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0, 720 /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0, 721 /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0, 722 /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0, 723 /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0, 724 /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0, 725 /* 1675 */ 'f', 'o', 'r', 's', 32, 0, 726 /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0, 727 /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0, 728 /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0, 729 /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0, 730 /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, 731 /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0, 732 /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0, 733 /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0, 734 /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0, 735 /* 1746 */ 'r', 'e', 't', 't', 32, 0, 736 /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0, 737 /* 1764 */ 's', 'd', 'i', 'v', 32, 0, 738 /* 1770 */ 'u', 'd', 'i', 'v', 32, 0, 739 /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0, 740 /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0, 741 /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0, 742 /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0, 743 /* 1816 */ 's', 'r', 'a', 'x', 32, 0, 744 /* 1822 */ 's', 'u', 'b', 'x', 32, 0, 745 /* 1828 */ 'a', 'd', 'd', 'x', 32, 0, 746 /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0, 747 /* 1844 */ 's', 'l', 'l', 'x', 32, 0, 748 /* 1850 */ 's', 'r', 'l', 'x', 32, 0, 749 /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0, 750 /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0, 751 /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0, 752 /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0, 753 /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0, 754 /* 1893 */ 's', 't', 'x', 32, 0, 755 /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0, 756 /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0, 757 /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0, 758 /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0, 759 /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0, 760 /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0, 761 /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0, 762 /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0, 763 /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0, 764 /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0, 765 /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0, 766 /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0, 767 /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0, 768 /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0, 769 /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0, 770 /* 2039 */ 'b', 'r', 'g', 'z', 32, 0, 771 /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0, 772 /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0, 773 /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0, 774 /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0, 775 /* 2083 */ 'b', 'r', 'l', 'z', 32, 0, 776 /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0, 777 /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0, 778 /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0, 779 /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0, 780 /* 2127 */ 'b', 'r', 'n', 'z', 32, 0, 781 /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0, 782 /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0, 783 /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0, 784 /* 2160 */ 'b', 'r', 'z', 32, 0, 785 /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0, 786 /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0, 787 /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 788 /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 789 /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 790 /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 791 /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 792 /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 793 /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 794 /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, 795 /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0, 796 /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0, 797 /* 2421 */ 't', 'a', 32, '3', 0, 798 /* 2426 */ 't', 'a', 32, '5', 0, 799 /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, 800 /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, 801 /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, 802 /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, 803 /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0, 804 /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0, 805 /* 2490 */ 'l', 'd', 'd', 32, '[', 0, 806 /* 2496 */ 'l', 'd', 32, '[', 0, 807 /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0, 808 /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0, 809 /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0, 810 /* 2522 */ 'l', 'd', 'q', 32, '[', 0, 811 /* 2528 */ 'c', 'a', 's', 32, '[', 0, 812 /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0, 813 /* 2541 */ 'l', 'd', 'x', 32, '[', 0, 814 /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0, 815 /* 2554 */ 'f', 'b', 0, 816 /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0, 817 /* 2563 */ 's', 'i', 'a', 'm', 0, 818 /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0, 819 /* 2577 */ 'n', 'o', 'p', 0, 820 /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0, 821 /* 2587 */ 's', 't', 'b', 'a', 'r', 0, 822 /* 2593 */ 'f', 'm', 'o', 'v', 's', 0, 823 /* 2599 */ 't', 0, 824 /* 2601 */ 'm', 'o', 'v', 0, 825 /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0, 826 }; 827#endif 828 829 // Emit the opcode for the instruction. 830 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; 831#ifndef CAPSTONE_DIET 832 // assert(Bits != 0 && "Cannot print this instruction."); 833 SStream_concat0(O, AsmStrs+(Bits & 4095)-1); 834#endif 835 836 837 // Fragment 0 encoded into 4 bits for 12 unique commands. 838 // printf("Frag-0: %u\n", (Bits >> 12) & 15); 839 switch ((Bits >> 12) & 15) { 840 default: // unreachable. 841 case 0: 842 // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C... 843 return; 844 break; 845 case 1: 846 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... 847 printOperand(MI, 1, O); 848 break; 849 case 2: 850 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... 851 printOperand(MI, 0, O); 852 break; 853 case 3: 854 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... 855 printCCOperand(MI, 1, O); 856 break; 857 case 4: 858 // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr 859 printMemOperand(MI, 0, O, NULL); 860 return; 861 break; 862 case 5: 863 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... 864 printCCOperand(MI, 3, O); 865 break; 866 case 6: 867 // GETPCX 868 printGetPCX(MI, 0, O); 869 return; 870 break; 871 case 7: 872 // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ... 873 printMemOperand(MI, 1, O, NULL); 874 break; 875 case 8: 876 // LEAX_ADDri, LEA_ADDri 877 printMemOperand(MI, 1, O, "arith"); 878 SStream_concat0(O, ", "); 879 printOperand(MI, 0, O); 880 return; 881 break; 882 case 9: 883 // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF... 884 printOperand(MI, 2, O); 885 SStream_concat0(O, ", ["); 886 printMemOperand(MI, 0, O, NULL); 887 SStream_concat0(O, "]"); 888 return; 889 break; 890 case 10: 891 // TICCri, TICCrr, TXCCri, TXCCrr 892 printCCOperand(MI, 2, O); 893 break; 894 case 11: 895 // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr 896 printCCOperand(MI, 4, O); 897 SStream_concat0(O, " "); 898 printOperand(MI, 1, O); 899 SStream_concat0(O, ", "); 900 printOperand(MI, 2, O); 901 SStream_concat0(O, ", "); 902 printOperand(MI, 0, O); 903 return; 904 break; 905 } 906 907 908 // Fragment 1 encoded into 4 bits for 16 unique commands. 909 // printf("Frag-1: %u\n", (Bits >> 16) & 15); 910 switch ((Bits >> 16) & 15) { 911 default: // unreachable. 912 case 0: 913 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... 914 SStream_concat0(O, ", "); 915 break; 916 case 1: 917 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ... 918 return; 919 break; 920 case 2: 921 // BCOND, BPFCC, FBCOND 922 SStream_concat0(O, " "); 923 break; 924 case 3: 925 // BCONDA, BPFCCA, FBCONDA 926 SStream_concat0(O, ",a "); 927 Sparc_add_hint(MI, SPARC_HINT_A); 928 break; 929 case 4: 930 // BPFCCANT 931 SStream_concat0(O, ",a,pn "); 932 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); 933 printOperand(MI, 2, O); 934 SStream_concat0(O, ", "); 935 printOperand(MI, 0, O); 936 return; 937 break; 938 case 5: 939 // BPFCCNT 940 SStream_concat0(O, ",pn "); 941 Sparc_add_hint(MI, SPARC_HINT_PN); 942 printOperand(MI, 2, O); 943 SStream_concat0(O, ", "); 944 printOperand(MI, 0, O); 945 return; 946 break; 947 case 6: 948 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... 949 SStream_concat0(O, " %icc, "); 950 Sparc_add_reg(MI, SPARC_REG_ICC); 951 break; 952 case 7: 953 // BPICCA 954 SStream_concat0(O, ",a %icc, "); 955 Sparc_add_hint(MI, SPARC_HINT_A); 956 Sparc_add_reg(MI, SPARC_REG_ICC); 957 printOperand(MI, 0, O); 958 return; 959 break; 960 case 8: 961 // BPICCANT 962 SStream_concat0(O, ",a,pn %icc, "); 963 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); 964 Sparc_add_reg(MI, SPARC_REG_ICC); 965 printOperand(MI, 0, O); 966 return; 967 break; 968 case 9: 969 // BPICCNT 970 SStream_concat0(O, ",pn %icc, "); 971 Sparc_add_hint(MI, SPARC_HINT_PN); 972 Sparc_add_reg(MI, SPARC_REG_ICC); 973 printOperand(MI, 0, O); 974 return; 975 break; 976 case 10: 977 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... 978 SStream_concat0(O, " %xcc, "); 979 Sparc_add_reg(MI, SPARC_REG_XCC); 980 break; 981 case 11: 982 // BPXCCA 983 SStream_concat0(O, ",a %xcc, "); 984 Sparc_add_hint(MI, SPARC_HINT_A); 985 Sparc_add_reg(MI, SPARC_REG_XCC); 986 printOperand(MI, 0, O); 987 return; 988 break; 989 case 12: 990 // BPXCCANT 991 SStream_concat0(O, ",a,pn %xcc, "); 992 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); 993 Sparc_add_reg(MI, SPARC_REG_XCC); 994 printOperand(MI, 0, O); 995 return; 996 break; 997 case 13: 998 // BPXCCNT 999 SStream_concat0(O, ",pn %xcc, "); 1000 Sparc_add_hint(MI, SPARC_HINT_PN); 1001 Sparc_add_reg(MI, SPARC_REG_XCC); 1002 printOperand(MI, 0, O); 1003 return; 1004 break; 1005 case 14: 1006 // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L... 1007 SStream_concat0(O, "], "); 1008 break; 1009 case 15: 1010 // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr 1011 SStream_concat0(O, " %fcc0, "); 1012 Sparc_add_reg(MI, SPARC_REG_FCC0); 1013 printOperand(MI, 1, O); 1014 SStream_concat0(O, ", "); 1015 printOperand(MI, 0, O); 1016 return; 1017 break; 1018 } 1019 1020 1021 // Fragment 2 encoded into 2 bits for 3 unique commands. 1022 // printf("Frag-2: %u\n", (Bits >> 20) & 3); 1023 switch ((Bits >> 20) & 3) { 1024 default: // unreachable. 1025 case 0: 1026 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... 1027 printOperand(MI, 2, O); 1028 SStream_concat0(O, ", "); 1029 printOperand(MI, 0, O); 1030 break; 1031 case 1: 1032 // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT... 1033 printOperand(MI, 0, O); 1034 break; 1035 case 2: 1036 // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ... 1037 printOperand(MI, 1, O); 1038 break; 1039 } 1040 1041 1042 // Fragment 3 encoded into 2 bits for 4 unique commands. 1043 // printf("Frag-3: %u\n", (Bits >> 22) & 3); 1044 switch ((Bits >> 22) & 3) { 1045 default: // unreachable. 1046 case 0: 1047 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... 1048 return; 1049 break; 1050 case 1: 1051 // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,... 1052 SStream_concat0(O, ", "); 1053 break; 1054 case 2: 1055 // TICCri, TICCrr, TXCCri, TXCCrr 1056 SStream_concat0(O, " + "); // qq 1057 printOperand(MI, 1, O); 1058 return; 1059 break; 1060 case 3: 1061 // WRYri, WRYrr 1062 SStream_concat0(O, ", %y"); 1063 Sparc_add_reg(MI, SPARC_REG_Y); 1064 return; 1065 break; 1066 } 1067 1068 1069 // Fragment 4 encoded into 2 bits for 3 unique commands. 1070 // printf("Frag-4: %u\n", (Bits >> 24) & 3); 1071 switch ((Bits >> 24) & 3) { 1072 default: // unreachable. 1073 case 0: 1074 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... 1075 printOperand(MI, 2, O); 1076 return; 1077 break; 1078 case 1: 1079 // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI... 1080 printOperand(MI, 0, O); 1081 return; 1082 break; 1083 case 2: 1084 // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr 1085 printOperand(MI, 3, O); 1086 return; 1087 break; 1088 } 1089} 1090 1091 1092/// getRegisterName - This method is automatically generated by tblgen 1093/// from the register set description. This returns the assembler name 1094/// for the specified register. 1095static const char *getRegisterName(unsigned RegNo) 1096{ 1097 // assert(RegNo && RegNo < 119 && "Invalid register number!"); 1098 1099#ifndef CAPSTONE_DIET 1100 static const char AsmStrs[] = { 1101 /* 0 */ 'f', '1', '0', 0, 1102 /* 4 */ 'f', '2', '0', 0, 1103 /* 8 */ 'f', '3', '0', 0, 1104 /* 12 */ 'f', '4', '0', 0, 1105 /* 16 */ 'f', '5', '0', 0, 1106 /* 20 */ 'f', '6', '0', 0, 1107 /* 24 */ 'f', 'c', 'c', '0', 0, 1108 /* 29 */ 'f', '0', 0, 1109 /* 32 */ 'g', '0', 0, 1110 /* 35 */ 'i', '0', 0, 1111 /* 38 */ 'l', '0', 0, 1112 /* 41 */ 'o', '0', 0, 1113 /* 44 */ 'f', '1', '1', 0, 1114 /* 48 */ 'f', '2', '1', 0, 1115 /* 52 */ 'f', '3', '1', 0, 1116 /* 56 */ 'f', 'c', 'c', '1', 0, 1117 /* 61 */ 'f', '1', 0, 1118 /* 64 */ 'g', '1', 0, 1119 /* 67 */ 'i', '1', 0, 1120 /* 70 */ 'l', '1', 0, 1121 /* 73 */ 'o', '1', 0, 1122 /* 76 */ 'f', '1', '2', 0, 1123 /* 80 */ 'f', '2', '2', 0, 1124 /* 84 */ 'f', '3', '2', 0, 1125 /* 88 */ 'f', '4', '2', 0, 1126 /* 92 */ 'f', '5', '2', 0, 1127 /* 96 */ 'f', '6', '2', 0, 1128 /* 100 */ 'f', 'c', 'c', '2', 0, 1129 /* 105 */ 'f', '2', 0, 1130 /* 108 */ 'g', '2', 0, 1131 /* 111 */ 'i', '2', 0, 1132 /* 114 */ 'l', '2', 0, 1133 /* 117 */ 'o', '2', 0, 1134 /* 120 */ 'f', '1', '3', 0, 1135 /* 124 */ 'f', '2', '3', 0, 1136 /* 128 */ 'f', 'c', 'c', '3', 0, 1137 /* 133 */ 'f', '3', 0, 1138 /* 136 */ 'g', '3', 0, 1139 /* 139 */ 'i', '3', 0, 1140 /* 142 */ 'l', '3', 0, 1141 /* 145 */ 'o', '3', 0, 1142 /* 148 */ 'f', '1', '4', 0, 1143 /* 152 */ 'f', '2', '4', 0, 1144 /* 156 */ 'f', '3', '4', 0, 1145 /* 160 */ 'f', '4', '4', 0, 1146 /* 164 */ 'f', '5', '4', 0, 1147 /* 168 */ 'f', '4', 0, 1148 /* 171 */ 'g', '4', 0, 1149 /* 174 */ 'i', '4', 0, 1150 /* 177 */ 'l', '4', 0, 1151 /* 180 */ 'o', '4', 0, 1152 /* 183 */ 'f', '1', '5', 0, 1153 /* 187 */ 'f', '2', '5', 0, 1154 /* 191 */ 'f', '5', 0, 1155 /* 194 */ 'g', '5', 0, 1156 /* 197 */ 'i', '5', 0, 1157 /* 200 */ 'l', '5', 0, 1158 /* 203 */ 'o', '5', 0, 1159 /* 206 */ 'f', '1', '6', 0, 1160 /* 210 */ 'f', '2', '6', 0, 1161 /* 214 */ 'f', '3', '6', 0, 1162 /* 218 */ 'f', '4', '6', 0, 1163 /* 222 */ 'f', '5', '6', 0, 1164 /* 226 */ 'f', '6', 0, 1165 /* 229 */ 'g', '6', 0, 1166 /* 232 */ 'l', '6', 0, 1167 /* 235 */ 'f', '1', '7', 0, 1168 /* 239 */ 'f', '2', '7', 0, 1169 /* 243 */ 'f', '7', 0, 1170 /* 246 */ 'g', '7', 0, 1171 /* 249 */ 'i', '7', 0, 1172 /* 252 */ 'l', '7', 0, 1173 /* 255 */ 'o', '7', 0, 1174 /* 258 */ 'f', '1', '8', 0, 1175 /* 262 */ 'f', '2', '8', 0, 1176 /* 266 */ 'f', '3', '8', 0, 1177 /* 270 */ 'f', '4', '8', 0, 1178 /* 274 */ 'f', '5', '8', 0, 1179 /* 278 */ 'f', '8', 0, 1180 /* 281 */ 'f', '1', '9', 0, 1181 /* 285 */ 'f', '2', '9', 0, 1182 /* 289 */ 'f', '9', 0, 1183 /* 292 */ 'i', 'c', 'c', 0, 1184 /* 296 */ 'f', 'p', 0, 1185 /* 299 */ 's', 'p', 0, 1186 /* 302 */ 'y', 0, 1187 }; 1188 1189 static const uint16_t RegAsmOffset[] = { 1190 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 1191 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 1192 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 1193 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 1194 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 1195 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 1196 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 1197 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 1198 12, 160, 270, 92, 222, 20, 1199 }; 1200 1201 //int i; 1202 //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) 1203 // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); 1204 //printf("*************************\n"); 1205 return AsmStrs+RegAsmOffset[RegNo-1]; 1206#else 1207 return NULL; 1208#endif 1209} 1210 1211#ifdef PRINT_ALIAS_INSTR 1212#undef PRINT_ALIAS_INSTR 1213 1214static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, 1215 unsigned PrintMethodIdx, SStream *OS) 1216{ 1217} 1218 1219static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) 1220{ 1221 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) 1222 const char *AsmString; 1223 char *tmp, *AsmMnem, *AsmOps, *c; 1224 int OpIdx, PrintMethodIdx; 1225 MCRegisterInfo *MRI = (MCRegisterInfo *)info; 1226 switch (MCInst_getOpcode(MI)) { 1227 default: return NULL; 1228 case SP_BCOND: 1229 if (MCInst_getNumOperands(MI) == 2 && 1230 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1231 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 1232 // (BCOND brtarget:$imm, 8) 1233 AsmString = "ba $\x01"; 1234 break; 1235 } 1236 if (MCInst_getNumOperands(MI) == 2 && 1237 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1238 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 1239 // (BCOND brtarget:$imm, 0) 1240 AsmString = "bn $\x01"; 1241 break; 1242 } 1243 if (MCInst_getNumOperands(MI) == 2 && 1244 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1245 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 1246 // (BCOND brtarget:$imm, 9) 1247 AsmString = "bne $\x01"; 1248 break; 1249 } 1250 if (MCInst_getNumOperands(MI) == 2 && 1251 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1252 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1253 // (BCOND brtarget:$imm, 1) 1254 AsmString = "be $\x01"; 1255 break; 1256 } 1257 if (MCInst_getNumOperands(MI) == 2 && 1258 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1259 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 1260 // (BCOND brtarget:$imm, 10) 1261 AsmString = "bg $\x01"; 1262 break; 1263 } 1264 if (MCInst_getNumOperands(MI) == 2 && 1265 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1266 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1267 // (BCOND brtarget:$imm, 2) 1268 AsmString = "ble $\x01"; 1269 break; 1270 } 1271 if (MCInst_getNumOperands(MI) == 2 && 1272 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1273 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 1274 // (BCOND brtarget:$imm, 11) 1275 AsmString = "bge $\x01"; 1276 break; 1277 } 1278 if (MCInst_getNumOperands(MI) == 2 && 1279 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1280 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 1281 // (BCOND brtarget:$imm, 3) 1282 AsmString = "bl $\x01"; 1283 break; 1284 } 1285 if (MCInst_getNumOperands(MI) == 2 && 1286 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1287 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 1288 // (BCOND brtarget:$imm, 12) 1289 AsmString = "bgu $\x01"; 1290 break; 1291 } 1292 if (MCInst_getNumOperands(MI) == 2 && 1293 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1294 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 1295 // (BCOND brtarget:$imm, 4) 1296 AsmString = "bleu $\x01"; 1297 break; 1298 } 1299 if (MCInst_getNumOperands(MI) == 2 && 1300 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1301 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 1302 // (BCOND brtarget:$imm, 13) 1303 AsmString = "bcc $\x01"; 1304 break; 1305 } 1306 if (MCInst_getNumOperands(MI) == 2 && 1307 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1308 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 1309 // (BCOND brtarget:$imm, 5) 1310 AsmString = "bcs $\x01"; 1311 break; 1312 } 1313 if (MCInst_getNumOperands(MI) == 2 && 1314 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1315 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 1316 // (BCOND brtarget:$imm, 14) 1317 AsmString = "bpos $\x01"; 1318 break; 1319 } 1320 if (MCInst_getNumOperands(MI) == 2 && 1321 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1322 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 1323 // (BCOND brtarget:$imm, 6) 1324 AsmString = "bneg $\x01"; 1325 break; 1326 } 1327 if (MCInst_getNumOperands(MI) == 2 && 1328 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1329 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 1330 // (BCOND brtarget:$imm, 15) 1331 AsmString = "bvc $\x01"; 1332 break; 1333 } 1334 if (MCInst_getNumOperands(MI) == 2 && 1335 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1336 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 1337 // (BCOND brtarget:$imm, 7) 1338 AsmString = "bvs $\x01"; 1339 break; 1340 } 1341 return NULL; 1342 case SP_BCONDA: 1343 if (MCInst_getNumOperands(MI) == 2 && 1344 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1345 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 1346 // (BCONDA brtarget:$imm, 8) 1347 AsmString = "ba,a $\x01"; 1348 break; 1349 } 1350 if (MCInst_getNumOperands(MI) == 2 && 1351 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1352 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 1353 // (BCONDA brtarget:$imm, 0) 1354 AsmString = "bn,a $\x01"; 1355 break; 1356 } 1357 if (MCInst_getNumOperands(MI) == 2 && 1358 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1359 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 1360 // (BCONDA brtarget:$imm, 9) 1361 AsmString = "bne,a $\x01"; 1362 break; 1363 } 1364 if (MCInst_getNumOperands(MI) == 2 && 1365 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1366 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1367 // (BCONDA brtarget:$imm, 1) 1368 AsmString = "be,a $\x01"; 1369 break; 1370 } 1371 if (MCInst_getNumOperands(MI) == 2 && 1372 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1373 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 1374 // (BCONDA brtarget:$imm, 10) 1375 AsmString = "bg,a $\x01"; 1376 break; 1377 } 1378 if (MCInst_getNumOperands(MI) == 2 && 1379 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1380 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1381 // (BCONDA brtarget:$imm, 2) 1382 AsmString = "ble,a $\x01"; 1383 break; 1384 } 1385 if (MCInst_getNumOperands(MI) == 2 && 1386 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1387 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 1388 // (BCONDA brtarget:$imm, 11) 1389 AsmString = "bge,a $\x01"; 1390 break; 1391 } 1392 if (MCInst_getNumOperands(MI) == 2 && 1393 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1394 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 1395 // (BCONDA brtarget:$imm, 3) 1396 AsmString = "bl,a $\x01"; 1397 break; 1398 } 1399 if (MCInst_getNumOperands(MI) == 2 && 1400 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1401 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 1402 // (BCONDA brtarget:$imm, 12) 1403 AsmString = "bgu,a $\x01"; 1404 break; 1405 } 1406 if (MCInst_getNumOperands(MI) == 2 && 1407 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1408 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 1409 // (BCONDA brtarget:$imm, 4) 1410 AsmString = "bleu,a $\x01"; 1411 break; 1412 } 1413 if (MCInst_getNumOperands(MI) == 2 && 1414 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1415 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 1416 // (BCONDA brtarget:$imm, 13) 1417 AsmString = "bcc,a $\x01"; 1418 break; 1419 } 1420 if (MCInst_getNumOperands(MI) == 2 && 1421 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1422 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 1423 // (BCONDA brtarget:$imm, 5) 1424 AsmString = "bcs,a $\x01"; 1425 break; 1426 } 1427 if (MCInst_getNumOperands(MI) == 2 && 1428 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1429 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 1430 // (BCONDA brtarget:$imm, 14) 1431 AsmString = "bpos,a $\x01"; 1432 break; 1433 } 1434 if (MCInst_getNumOperands(MI) == 2 && 1435 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1436 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 1437 // (BCONDA brtarget:$imm, 6) 1438 AsmString = "bneg,a $\x01"; 1439 break; 1440 } 1441 if (MCInst_getNumOperands(MI) == 2 && 1442 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1443 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 1444 // (BCONDA brtarget:$imm, 15) 1445 AsmString = "bvc,a $\x01"; 1446 break; 1447 } 1448 if (MCInst_getNumOperands(MI) == 2 && 1449 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1450 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 1451 // (BCONDA brtarget:$imm, 7) 1452 AsmString = "bvs,a $\x01"; 1453 break; 1454 } 1455 return NULL; 1456 case SP_BPFCCANT: 1457 if (MCInst_getNumOperands(MI) == 3 && 1458 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1459 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && 1460 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1461 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1462 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) 1463 AsmString = "fba,a,pn $\x03, $\x01"; 1464 break; 1465 } 1466 if (MCInst_getNumOperands(MI) == 3 && 1467 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1468 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && 1469 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1470 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1471 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) 1472 AsmString = "fbn,a,pn $\x03, $\x01"; 1473 break; 1474 } 1475 if (MCInst_getNumOperands(MI) == 3 && 1476 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1477 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && 1478 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1479 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1480 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) 1481 AsmString = "fbu,a,pn $\x03, $\x01"; 1482 break; 1483 } 1484 if (MCInst_getNumOperands(MI) == 3 && 1485 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1486 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && 1487 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1488 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1489 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) 1490 AsmString = "fbg,a,pn $\x03, $\x01"; 1491 break; 1492 } 1493 if (MCInst_getNumOperands(MI) == 3 && 1494 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1495 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && 1496 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1497 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1498 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) 1499 AsmString = "fbug,a,pn $\x03, $\x01"; 1500 break; 1501 } 1502 if (MCInst_getNumOperands(MI) == 3 && 1503 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1504 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && 1505 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1506 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1507 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) 1508 AsmString = "fbl,a,pn $\x03, $\x01"; 1509 break; 1510 } 1511 if (MCInst_getNumOperands(MI) == 3 && 1512 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1513 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && 1514 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1515 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1516 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) 1517 AsmString = "fbul,a,pn $\x03, $\x01"; 1518 break; 1519 } 1520 if (MCInst_getNumOperands(MI) == 3 && 1521 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1522 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && 1523 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1524 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1525 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) 1526 AsmString = "fblg,a,pn $\x03, $\x01"; 1527 break; 1528 } 1529 if (MCInst_getNumOperands(MI) == 3 && 1530 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1531 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && 1532 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1533 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1534 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) 1535 AsmString = "fbne,a,pn $\x03, $\x01"; 1536 break; 1537 } 1538 if (MCInst_getNumOperands(MI) == 3 && 1539 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1540 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && 1541 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1542 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1543 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) 1544 AsmString = "fbe,a,pn $\x03, $\x01"; 1545 break; 1546 } 1547 if (MCInst_getNumOperands(MI) == 3 && 1548 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1549 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && 1550 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1551 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1552 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) 1553 AsmString = "fbue,a,pn $\x03, $\x01"; 1554 break; 1555 } 1556 if (MCInst_getNumOperands(MI) == 3 && 1557 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1558 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && 1559 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1560 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1561 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) 1562 AsmString = "fbge,a,pn $\x03, $\x01"; 1563 break; 1564 } 1565 if (MCInst_getNumOperands(MI) == 3 && 1566 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1567 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && 1568 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1569 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1570 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) 1571 AsmString = "fbuge,a,pn $\x03, $\x01"; 1572 break; 1573 } 1574 if (MCInst_getNumOperands(MI) == 3 && 1575 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1576 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && 1577 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1578 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1579 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) 1580 AsmString = "fble,a,pn $\x03, $\x01"; 1581 break; 1582 } 1583 if (MCInst_getNumOperands(MI) == 3 && 1584 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1585 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && 1586 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1587 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1588 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) 1589 AsmString = "fbule,a,pn $\x03, $\x01"; 1590 break; 1591 } 1592 if (MCInst_getNumOperands(MI) == 3 && 1593 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1594 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && 1595 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1596 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1597 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) 1598 AsmString = "fbo,a,pn $\x03, $\x01"; 1599 break; 1600 } 1601 return NULL; 1602 case SP_BPFCCNT: 1603 if (MCInst_getNumOperands(MI) == 3 && 1604 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1605 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && 1606 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1607 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1608 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) 1609 AsmString = "fba,pn $\x03, $\x01"; 1610 break; 1611 } 1612 if (MCInst_getNumOperands(MI) == 3 && 1613 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1614 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && 1615 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1616 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1617 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) 1618 AsmString = "fbn,pn $\x03, $\x01"; 1619 break; 1620 } 1621 if (MCInst_getNumOperands(MI) == 3 && 1622 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1623 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && 1624 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1625 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1626 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) 1627 AsmString = "fbu,pn $\x03, $\x01"; 1628 break; 1629 } 1630 if (MCInst_getNumOperands(MI) == 3 && 1631 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1632 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && 1633 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1634 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1635 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) 1636 AsmString = "fbg,pn $\x03, $\x01"; 1637 break; 1638 } 1639 if (MCInst_getNumOperands(MI) == 3 && 1640 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1641 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && 1642 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1643 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1644 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) 1645 AsmString = "fbug,pn $\x03, $\x01"; 1646 break; 1647 } 1648 if (MCInst_getNumOperands(MI) == 3 && 1649 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1650 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && 1651 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1652 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1653 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) 1654 AsmString = "fbl,pn $\x03, $\x01"; 1655 break; 1656 } 1657 if (MCInst_getNumOperands(MI) == 3 && 1658 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1659 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && 1660 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1661 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1662 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) 1663 AsmString = "fbul,pn $\x03, $\x01"; 1664 break; 1665 } 1666 if (MCInst_getNumOperands(MI) == 3 && 1667 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1668 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && 1669 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1670 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1671 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) 1672 AsmString = "fblg,pn $\x03, $\x01"; 1673 break; 1674 } 1675 if (MCInst_getNumOperands(MI) == 3 && 1676 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1677 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && 1678 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1679 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1680 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) 1681 AsmString = "fbne,pn $\x03, $\x01"; 1682 break; 1683 } 1684 if (MCInst_getNumOperands(MI) == 3 && 1685 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1686 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && 1687 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1688 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1689 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) 1690 AsmString = "fbe,pn $\x03, $\x01"; 1691 break; 1692 } 1693 if (MCInst_getNumOperands(MI) == 3 && 1694 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1695 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && 1696 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1697 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1698 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) 1699 AsmString = "fbue,pn $\x03, $\x01"; 1700 break; 1701 } 1702 if (MCInst_getNumOperands(MI) == 3 && 1703 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1704 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && 1705 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1706 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1707 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) 1708 AsmString = "fbge,pn $\x03, $\x01"; 1709 break; 1710 } 1711 if (MCInst_getNumOperands(MI) == 3 && 1712 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1713 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && 1714 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1715 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1716 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) 1717 AsmString = "fbuge,pn $\x03, $\x01"; 1718 break; 1719 } 1720 if (MCInst_getNumOperands(MI) == 3 && 1721 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1722 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && 1723 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1724 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1725 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) 1726 AsmString = "fble,pn $\x03, $\x01"; 1727 break; 1728 } 1729 if (MCInst_getNumOperands(MI) == 3 && 1730 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1731 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && 1732 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1733 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1734 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) 1735 AsmString = "fbule,pn $\x03, $\x01"; 1736 break; 1737 } 1738 if (MCInst_getNumOperands(MI) == 3 && 1739 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1740 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && 1741 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1742 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { 1743 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) 1744 AsmString = "fbo,pn $\x03, $\x01"; 1745 break; 1746 } 1747 return NULL; 1748 case SP_BPICCANT: 1749 if (MCInst_getNumOperands(MI) == 2 && 1750 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1751 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 1752 // (BPICCANT brtarget:$imm, 8) 1753 AsmString = "ba,a,pn %icc, $\x01"; 1754 break; 1755 } 1756 if (MCInst_getNumOperands(MI) == 2 && 1757 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1758 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 1759 // (BPICCANT brtarget:$imm, 0) 1760 AsmString = "bn,a,pn %icc, $\x01"; 1761 break; 1762 } 1763 if (MCInst_getNumOperands(MI) == 2 && 1764 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1765 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 1766 // (BPICCANT brtarget:$imm, 9) 1767 AsmString = "bne,a,pn %icc, $\x01"; 1768 break; 1769 } 1770 if (MCInst_getNumOperands(MI) == 2 && 1771 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1772 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1773 // (BPICCANT brtarget:$imm, 1) 1774 AsmString = "be,a,pn %icc, $\x01"; 1775 break; 1776 } 1777 if (MCInst_getNumOperands(MI) == 2 && 1778 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1779 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 1780 // (BPICCANT brtarget:$imm, 10) 1781 AsmString = "bg,a,pn %icc, $\x01"; 1782 break; 1783 } 1784 if (MCInst_getNumOperands(MI) == 2 && 1785 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1786 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1787 // (BPICCANT brtarget:$imm, 2) 1788 AsmString = "ble,a,pn %icc, $\x01"; 1789 break; 1790 } 1791 if (MCInst_getNumOperands(MI) == 2 && 1792 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1793 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 1794 // (BPICCANT brtarget:$imm, 11) 1795 AsmString = "bge,a,pn %icc, $\x01"; 1796 break; 1797 } 1798 if (MCInst_getNumOperands(MI) == 2 && 1799 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1800 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 1801 // (BPICCANT brtarget:$imm, 3) 1802 AsmString = "bl,a,pn %icc, $\x01"; 1803 break; 1804 } 1805 if (MCInst_getNumOperands(MI) == 2 && 1806 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1807 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 1808 // (BPICCANT brtarget:$imm, 12) 1809 AsmString = "bgu,a,pn %icc, $\x01"; 1810 break; 1811 } 1812 if (MCInst_getNumOperands(MI) == 2 && 1813 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1814 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 1815 // (BPICCANT brtarget:$imm, 4) 1816 AsmString = "bleu,a,pn %icc, $\x01"; 1817 break; 1818 } 1819 if (MCInst_getNumOperands(MI) == 2 && 1820 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1821 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 1822 // (BPICCANT brtarget:$imm, 13) 1823 AsmString = "bcc,a,pn %icc, $\x01"; 1824 break; 1825 } 1826 if (MCInst_getNumOperands(MI) == 2 && 1827 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1828 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 1829 // (BPICCANT brtarget:$imm, 5) 1830 AsmString = "bcs,a,pn %icc, $\x01"; 1831 break; 1832 } 1833 if (MCInst_getNumOperands(MI) == 2 && 1834 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1835 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 1836 // (BPICCANT brtarget:$imm, 14) 1837 AsmString = "bpos,a,pn %icc, $\x01"; 1838 break; 1839 } 1840 if (MCInst_getNumOperands(MI) == 2 && 1841 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1842 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 1843 // (BPICCANT brtarget:$imm, 6) 1844 AsmString = "bneg,a,pn %icc, $\x01"; 1845 break; 1846 } 1847 if (MCInst_getNumOperands(MI) == 2 && 1848 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1849 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 1850 // (BPICCANT brtarget:$imm, 15) 1851 AsmString = "bvc,a,pn %icc, $\x01"; 1852 break; 1853 } 1854 if (MCInst_getNumOperands(MI) == 2 && 1855 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1856 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 1857 // (BPICCANT brtarget:$imm, 7) 1858 AsmString = "bvs,a,pn %icc, $\x01"; 1859 break; 1860 } 1861 return NULL; 1862 case SP_BPICCNT: 1863 if (MCInst_getNumOperands(MI) == 2 && 1864 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1865 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 1866 // (BPICCNT brtarget:$imm, 8) 1867 AsmString = "ba,pn %icc, $\x01"; 1868 break; 1869 } 1870 if (MCInst_getNumOperands(MI) == 2 && 1871 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1872 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 1873 // (BPICCNT brtarget:$imm, 0) 1874 AsmString = "bn,pn %icc, $\x01"; 1875 break; 1876 } 1877 if (MCInst_getNumOperands(MI) == 2 && 1878 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1879 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 1880 // (BPICCNT brtarget:$imm, 9) 1881 AsmString = "bne,pn %icc, $\x01"; 1882 break; 1883 } 1884 if (MCInst_getNumOperands(MI) == 2 && 1885 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1886 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1887 // (BPICCNT brtarget:$imm, 1) 1888 AsmString = "be,pn %icc, $\x01"; 1889 break; 1890 } 1891 if (MCInst_getNumOperands(MI) == 2 && 1892 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1893 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 1894 // (BPICCNT brtarget:$imm, 10) 1895 AsmString = "bg,pn %icc, $\x01"; 1896 break; 1897 } 1898 if (MCInst_getNumOperands(MI) == 2 && 1899 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1900 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1901 // (BPICCNT brtarget:$imm, 2) 1902 AsmString = "ble,pn %icc, $\x01"; 1903 break; 1904 } 1905 if (MCInst_getNumOperands(MI) == 2 && 1906 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1907 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 1908 // (BPICCNT brtarget:$imm, 11) 1909 AsmString = "bge,pn %icc, $\x01"; 1910 break; 1911 } 1912 if (MCInst_getNumOperands(MI) == 2 && 1913 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1914 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 1915 // (BPICCNT brtarget:$imm, 3) 1916 AsmString = "bl,pn %icc, $\x01"; 1917 break; 1918 } 1919 if (MCInst_getNumOperands(MI) == 2 && 1920 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1921 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 1922 // (BPICCNT brtarget:$imm, 12) 1923 AsmString = "bgu,pn %icc, $\x01"; 1924 break; 1925 } 1926 if (MCInst_getNumOperands(MI) == 2 && 1927 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1928 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 1929 // (BPICCNT brtarget:$imm, 4) 1930 AsmString = "bleu,pn %icc, $\x01"; 1931 break; 1932 } 1933 if (MCInst_getNumOperands(MI) == 2 && 1934 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1935 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 1936 // (BPICCNT brtarget:$imm, 13) 1937 AsmString = "bcc,pn %icc, $\x01"; 1938 break; 1939 } 1940 if (MCInst_getNumOperands(MI) == 2 && 1941 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1942 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 1943 // (BPICCNT brtarget:$imm, 5) 1944 AsmString = "bcs,pn %icc, $\x01"; 1945 break; 1946 } 1947 if (MCInst_getNumOperands(MI) == 2 && 1948 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1949 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 1950 // (BPICCNT brtarget:$imm, 14) 1951 AsmString = "bpos,pn %icc, $\x01"; 1952 break; 1953 } 1954 if (MCInst_getNumOperands(MI) == 2 && 1955 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1956 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 1957 // (BPICCNT brtarget:$imm, 6) 1958 AsmString = "bneg,pn %icc, $\x01"; 1959 break; 1960 } 1961 if (MCInst_getNumOperands(MI) == 2 && 1962 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1963 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 1964 // (BPICCNT brtarget:$imm, 15) 1965 AsmString = "bvc,pn %icc, $\x01"; 1966 break; 1967 } 1968 if (MCInst_getNumOperands(MI) == 2 && 1969 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1970 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 1971 // (BPICCNT brtarget:$imm, 7) 1972 AsmString = "bvs,pn %icc, $\x01"; 1973 break; 1974 } 1975 return NULL; 1976 case SP_BPXCCANT: 1977 if (MCInst_getNumOperands(MI) == 2 && 1978 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1979 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 1980 // (BPXCCANT brtarget:$imm, 8) 1981 AsmString = "ba,a,pn %xcc, $\x01"; 1982 break; 1983 } 1984 if (MCInst_getNumOperands(MI) == 2 && 1985 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1986 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 1987 // (BPXCCANT brtarget:$imm, 0) 1988 AsmString = "bn,a,pn %xcc, $\x01"; 1989 break; 1990 } 1991 if (MCInst_getNumOperands(MI) == 2 && 1992 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1993 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 1994 // (BPXCCANT brtarget:$imm, 9) 1995 AsmString = "bne,a,pn %xcc, $\x01"; 1996 break; 1997 } 1998 if (MCInst_getNumOperands(MI) == 2 && 1999 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2000 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 2001 // (BPXCCANT brtarget:$imm, 1) 2002 AsmString = "be,a,pn %xcc, $\x01"; 2003 break; 2004 } 2005 if (MCInst_getNumOperands(MI) == 2 && 2006 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2007 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 2008 // (BPXCCANT brtarget:$imm, 10) 2009 AsmString = "bg,a,pn %xcc, $\x01"; 2010 break; 2011 } 2012 if (MCInst_getNumOperands(MI) == 2 && 2013 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2014 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 2015 // (BPXCCANT brtarget:$imm, 2) 2016 AsmString = "ble,a,pn %xcc, $\x01"; 2017 break; 2018 } 2019 if (MCInst_getNumOperands(MI) == 2 && 2020 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2021 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 2022 // (BPXCCANT brtarget:$imm, 11) 2023 AsmString = "bge,a,pn %xcc, $\x01"; 2024 break; 2025 } 2026 if (MCInst_getNumOperands(MI) == 2 && 2027 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2028 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 2029 // (BPXCCANT brtarget:$imm, 3) 2030 AsmString = "bl,a,pn %xcc, $\x01"; 2031 break; 2032 } 2033 if (MCInst_getNumOperands(MI) == 2 && 2034 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2035 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 2036 // (BPXCCANT brtarget:$imm, 12) 2037 AsmString = "bgu,a,pn %xcc, $\x01"; 2038 break; 2039 } 2040 if (MCInst_getNumOperands(MI) == 2 && 2041 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2042 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 2043 // (BPXCCANT brtarget:$imm, 4) 2044 AsmString = "bleu,a,pn %xcc, $\x01"; 2045 break; 2046 } 2047 if (MCInst_getNumOperands(MI) == 2 && 2048 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2049 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 2050 // (BPXCCANT brtarget:$imm, 13) 2051 AsmString = "bcc,a,pn %xcc, $\x01"; 2052 break; 2053 } 2054 if (MCInst_getNumOperands(MI) == 2 && 2055 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2056 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 2057 // (BPXCCANT brtarget:$imm, 5) 2058 AsmString = "bcs,a,pn %xcc, $\x01"; 2059 break; 2060 } 2061 if (MCInst_getNumOperands(MI) == 2 && 2062 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2063 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 2064 // (BPXCCANT brtarget:$imm, 14) 2065 AsmString = "bpos,a,pn %xcc, $\x01"; 2066 break; 2067 } 2068 if (MCInst_getNumOperands(MI) == 2 && 2069 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2070 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 2071 // (BPXCCANT brtarget:$imm, 6) 2072 AsmString = "bneg,a,pn %xcc, $\x01"; 2073 break; 2074 } 2075 if (MCInst_getNumOperands(MI) == 2 && 2076 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2077 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 2078 // (BPXCCANT brtarget:$imm, 15) 2079 AsmString = "bvc,a,pn %xcc, $\x01"; 2080 break; 2081 } 2082 if (MCInst_getNumOperands(MI) == 2 && 2083 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2084 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 2085 // (BPXCCANT brtarget:$imm, 7) 2086 AsmString = "bvs,a,pn %xcc, $\x01"; 2087 break; 2088 } 2089 return NULL; 2090 case SP_BPXCCNT: 2091 if (MCInst_getNumOperands(MI) == 2 && 2092 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2093 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { 2094 // (BPXCCNT brtarget:$imm, 8) 2095 AsmString = "ba,pn %xcc, $\x01"; 2096 break; 2097 } 2098 if (MCInst_getNumOperands(MI) == 2 && 2099 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2100 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { 2101 // (BPXCCNT brtarget:$imm, 0) 2102 AsmString = "bn,pn %xcc, $\x01"; 2103 break; 2104 } 2105 if (MCInst_getNumOperands(MI) == 2 && 2106 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2107 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { 2108 // (BPXCCNT brtarget:$imm, 9) 2109 AsmString = "bne,pn %xcc, $\x01"; 2110 break; 2111 } 2112 if (MCInst_getNumOperands(MI) == 2 && 2113 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2114 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 2115 // (BPXCCNT brtarget:$imm, 1) 2116 AsmString = "be,pn %xcc, $\x01"; 2117 break; 2118 } 2119 if (MCInst_getNumOperands(MI) == 2 && 2120 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2121 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { 2122 // (BPXCCNT brtarget:$imm, 10) 2123 AsmString = "bg,pn %xcc, $\x01"; 2124 break; 2125 } 2126 if (MCInst_getNumOperands(MI) == 2 && 2127 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2128 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 2129 // (BPXCCNT brtarget:$imm, 2) 2130 AsmString = "ble,pn %xcc, $\x01"; 2131 break; 2132 } 2133 if (MCInst_getNumOperands(MI) == 2 && 2134 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2135 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { 2136 // (BPXCCNT brtarget:$imm, 11) 2137 AsmString = "bge,pn %xcc, $\x01"; 2138 break; 2139 } 2140 if (MCInst_getNumOperands(MI) == 2 && 2141 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2142 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { 2143 // (BPXCCNT brtarget:$imm, 3) 2144 AsmString = "bl,pn %xcc, $\x01"; 2145 break; 2146 } 2147 if (MCInst_getNumOperands(MI) == 2 && 2148 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2149 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { 2150 // (BPXCCNT brtarget:$imm, 12) 2151 AsmString = "bgu,pn %xcc, $\x01"; 2152 break; 2153 } 2154 if (MCInst_getNumOperands(MI) == 2 && 2155 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2156 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { 2157 // (BPXCCNT brtarget:$imm, 4) 2158 AsmString = "bleu,pn %xcc, $\x01"; 2159 break; 2160 } 2161 if (MCInst_getNumOperands(MI) == 2 && 2162 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2163 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { 2164 // (BPXCCNT brtarget:$imm, 13) 2165 AsmString = "bcc,pn %xcc, $\x01"; 2166 break; 2167 } 2168 if (MCInst_getNumOperands(MI) == 2 && 2169 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2170 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { 2171 // (BPXCCNT brtarget:$imm, 5) 2172 AsmString = "bcs,pn %xcc, $\x01"; 2173 break; 2174 } 2175 if (MCInst_getNumOperands(MI) == 2 && 2176 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2177 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { 2178 // (BPXCCNT brtarget:$imm, 14) 2179 AsmString = "bpos,pn %xcc, $\x01"; 2180 break; 2181 } 2182 if (MCInst_getNumOperands(MI) == 2 && 2183 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2184 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { 2185 // (BPXCCNT brtarget:$imm, 6) 2186 AsmString = "bneg,pn %xcc, $\x01"; 2187 break; 2188 } 2189 if (MCInst_getNumOperands(MI) == 2 && 2190 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2191 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 2192 // (BPXCCNT brtarget:$imm, 15) 2193 AsmString = "bvc,pn %xcc, $\x01"; 2194 break; 2195 } 2196 if (MCInst_getNumOperands(MI) == 2 && 2197 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2198 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { 2199 // (BPXCCNT brtarget:$imm, 7) 2200 AsmString = "bvs,pn %xcc, $\x01"; 2201 break; 2202 } 2203 return NULL; 2204 case SP_FMOVD_ICC: 2205 if (MCInst_getNumOperands(MI) == 3 && 2206 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2207 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2208 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2209 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2210 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2211 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 2212 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) 2213 AsmString = "fmovda %icc, $\x02, $\x01"; 2214 break; 2215 } 2216 if (MCInst_getNumOperands(MI) == 3 && 2217 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2218 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2219 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2220 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2221 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2222 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2223 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) 2224 AsmString = "fmovdn %icc, $\x02, $\x01"; 2225 break; 2226 } 2227 if (MCInst_getNumOperands(MI) == 3 && 2228 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2229 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2230 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2231 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2232 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2233 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 2234 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) 2235 AsmString = "fmovdne %icc, $\x02, $\x01"; 2236 break; 2237 } 2238 if (MCInst_getNumOperands(MI) == 3 && 2239 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2240 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2241 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2242 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2243 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2244 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2245 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) 2246 AsmString = "fmovde %icc, $\x02, $\x01"; 2247 break; 2248 } 2249 if (MCInst_getNumOperands(MI) == 3 && 2250 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2251 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2252 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2253 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2254 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2255 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 2256 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) 2257 AsmString = "fmovdg %icc, $\x02, $\x01"; 2258 break; 2259 } 2260 if (MCInst_getNumOperands(MI) == 3 && 2261 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2262 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2263 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2264 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2265 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2266 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 2267 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) 2268 AsmString = "fmovdle %icc, $\x02, $\x01"; 2269 break; 2270 } 2271 if (MCInst_getNumOperands(MI) == 3 && 2272 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2273 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2274 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2275 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2276 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2277 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 2278 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) 2279 AsmString = "fmovdge %icc, $\x02, $\x01"; 2280 break; 2281 } 2282 if (MCInst_getNumOperands(MI) == 3 && 2283 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2284 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2285 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2286 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2287 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2288 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 2289 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) 2290 AsmString = "fmovdl %icc, $\x02, $\x01"; 2291 break; 2292 } 2293 if (MCInst_getNumOperands(MI) == 3 && 2294 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2295 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2296 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2297 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2298 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2299 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 2300 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) 2301 AsmString = "fmovdgu %icc, $\x02, $\x01"; 2302 break; 2303 } 2304 if (MCInst_getNumOperands(MI) == 3 && 2305 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2306 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2307 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2308 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2309 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2310 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 2311 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) 2312 AsmString = "fmovdleu %icc, $\x02, $\x01"; 2313 break; 2314 } 2315 if (MCInst_getNumOperands(MI) == 3 && 2316 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2317 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2318 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2319 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2320 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2321 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 2322 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) 2323 AsmString = "fmovdcc %icc, $\x02, $\x01"; 2324 break; 2325 } 2326 if (MCInst_getNumOperands(MI) == 3 && 2327 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2328 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2329 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2330 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2331 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2332 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 2333 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) 2334 AsmString = "fmovdcs %icc, $\x02, $\x01"; 2335 break; 2336 } 2337 if (MCInst_getNumOperands(MI) == 3 && 2338 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2339 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2340 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2341 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2342 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2343 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 2344 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) 2345 AsmString = "fmovdpos %icc, $\x02, $\x01"; 2346 break; 2347 } 2348 if (MCInst_getNumOperands(MI) == 3 && 2349 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2350 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2351 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2352 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2353 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2354 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 2355 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) 2356 AsmString = "fmovdneg %icc, $\x02, $\x01"; 2357 break; 2358 } 2359 if (MCInst_getNumOperands(MI) == 3 && 2360 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2361 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2362 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2363 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2364 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2365 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 2366 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) 2367 AsmString = "fmovdvc %icc, $\x02, $\x01"; 2368 break; 2369 } 2370 if (MCInst_getNumOperands(MI) == 3 && 2371 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2372 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2373 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2374 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2375 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2376 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2377 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) 2378 AsmString = "fmovdvs %icc, $\x02, $\x01"; 2379 break; 2380 } 2381 return NULL; 2382 case SP_FMOVD_XCC: 2383 if (MCInst_getNumOperands(MI) == 3 && 2384 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2385 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2386 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2387 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2388 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2389 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 2390 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) 2391 AsmString = "fmovda %xcc, $\x02, $\x01"; 2392 break; 2393 } 2394 if (MCInst_getNumOperands(MI) == 3 && 2395 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2396 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2397 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2398 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2399 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2400 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2401 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) 2402 AsmString = "fmovdn %xcc, $\x02, $\x01"; 2403 break; 2404 } 2405 if (MCInst_getNumOperands(MI) == 3 && 2406 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2407 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2408 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2409 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2410 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2411 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 2412 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) 2413 AsmString = "fmovdne %xcc, $\x02, $\x01"; 2414 break; 2415 } 2416 if (MCInst_getNumOperands(MI) == 3 && 2417 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2418 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2419 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2420 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2421 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2422 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2423 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) 2424 AsmString = "fmovde %xcc, $\x02, $\x01"; 2425 break; 2426 } 2427 if (MCInst_getNumOperands(MI) == 3 && 2428 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2429 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2430 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2431 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2432 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2433 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 2434 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) 2435 AsmString = "fmovdg %xcc, $\x02, $\x01"; 2436 break; 2437 } 2438 if (MCInst_getNumOperands(MI) == 3 && 2439 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2440 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2441 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2442 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2443 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2444 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 2445 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) 2446 AsmString = "fmovdle %xcc, $\x02, $\x01"; 2447 break; 2448 } 2449 if (MCInst_getNumOperands(MI) == 3 && 2450 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2451 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2452 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2453 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2454 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2455 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 2456 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) 2457 AsmString = "fmovdge %xcc, $\x02, $\x01"; 2458 break; 2459 } 2460 if (MCInst_getNumOperands(MI) == 3 && 2461 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2462 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2463 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2464 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2465 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2466 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 2467 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) 2468 AsmString = "fmovdl %xcc, $\x02, $\x01"; 2469 break; 2470 } 2471 if (MCInst_getNumOperands(MI) == 3 && 2472 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2473 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2474 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2475 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2476 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2477 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 2478 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) 2479 AsmString = "fmovdgu %xcc, $\x02, $\x01"; 2480 break; 2481 } 2482 if (MCInst_getNumOperands(MI) == 3 && 2483 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2484 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2485 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2486 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2487 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2488 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 2489 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) 2490 AsmString = "fmovdleu %xcc, $\x02, $\x01"; 2491 break; 2492 } 2493 if (MCInst_getNumOperands(MI) == 3 && 2494 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2495 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2496 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2497 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2498 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2499 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 2500 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) 2501 AsmString = "fmovdcc %xcc, $\x02, $\x01"; 2502 break; 2503 } 2504 if (MCInst_getNumOperands(MI) == 3 && 2505 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2506 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2507 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2508 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2509 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2510 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 2511 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) 2512 AsmString = "fmovdcs %xcc, $\x02, $\x01"; 2513 break; 2514 } 2515 if (MCInst_getNumOperands(MI) == 3 && 2516 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2517 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2518 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2519 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2520 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2521 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 2522 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) 2523 AsmString = "fmovdpos %xcc, $\x02, $\x01"; 2524 break; 2525 } 2526 if (MCInst_getNumOperands(MI) == 3 && 2527 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2528 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2529 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2530 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2531 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2532 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 2533 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) 2534 AsmString = "fmovdneg %xcc, $\x02, $\x01"; 2535 break; 2536 } 2537 if (MCInst_getNumOperands(MI) == 3 && 2538 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2539 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2540 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2541 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2542 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2543 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 2544 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) 2545 AsmString = "fmovdvc %xcc, $\x02, $\x01"; 2546 break; 2547 } 2548 if (MCInst_getNumOperands(MI) == 3 && 2549 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2550 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 2551 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2552 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 2553 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2554 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2555 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) 2556 AsmString = "fmovdvs %xcc, $\x02, $\x01"; 2557 break; 2558 } 2559 return NULL; 2560 case SP_FMOVQ_ICC: 2561 if (MCInst_getNumOperands(MI) == 3 && 2562 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2563 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2564 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2565 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2566 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2567 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 2568 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) 2569 AsmString = "fmovqa %icc, $\x02, $\x01"; 2570 break; 2571 } 2572 if (MCInst_getNumOperands(MI) == 3 && 2573 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2574 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2575 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2576 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2577 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2578 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2579 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) 2580 AsmString = "fmovqn %icc, $\x02, $\x01"; 2581 break; 2582 } 2583 if (MCInst_getNumOperands(MI) == 3 && 2584 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2585 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2586 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2587 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2588 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2589 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 2590 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) 2591 AsmString = "fmovqne %icc, $\x02, $\x01"; 2592 break; 2593 } 2594 if (MCInst_getNumOperands(MI) == 3 && 2595 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2596 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2597 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2598 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2599 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2600 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2601 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) 2602 AsmString = "fmovqe %icc, $\x02, $\x01"; 2603 break; 2604 } 2605 if (MCInst_getNumOperands(MI) == 3 && 2606 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2607 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2608 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2609 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2610 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2611 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 2612 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) 2613 AsmString = "fmovqg %icc, $\x02, $\x01"; 2614 break; 2615 } 2616 if (MCInst_getNumOperands(MI) == 3 && 2617 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2618 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2619 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2620 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2621 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2622 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 2623 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) 2624 AsmString = "fmovqle %icc, $\x02, $\x01"; 2625 break; 2626 } 2627 if (MCInst_getNumOperands(MI) == 3 && 2628 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2629 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2630 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2631 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2632 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2633 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 2634 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) 2635 AsmString = "fmovqge %icc, $\x02, $\x01"; 2636 break; 2637 } 2638 if (MCInst_getNumOperands(MI) == 3 && 2639 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2640 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2641 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2642 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2643 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2644 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 2645 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) 2646 AsmString = "fmovql %icc, $\x02, $\x01"; 2647 break; 2648 } 2649 if (MCInst_getNumOperands(MI) == 3 && 2650 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2651 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2652 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2653 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2654 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2655 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 2656 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) 2657 AsmString = "fmovqgu %icc, $\x02, $\x01"; 2658 break; 2659 } 2660 if (MCInst_getNumOperands(MI) == 3 && 2661 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2662 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2663 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2664 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2665 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2666 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 2667 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) 2668 AsmString = "fmovqleu %icc, $\x02, $\x01"; 2669 break; 2670 } 2671 if (MCInst_getNumOperands(MI) == 3 && 2672 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2673 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2674 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2675 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2676 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2677 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 2678 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) 2679 AsmString = "fmovqcc %icc, $\x02, $\x01"; 2680 break; 2681 } 2682 if (MCInst_getNumOperands(MI) == 3 && 2683 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2684 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2685 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2686 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2687 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2688 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 2689 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) 2690 AsmString = "fmovqcs %icc, $\x02, $\x01"; 2691 break; 2692 } 2693 if (MCInst_getNumOperands(MI) == 3 && 2694 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2695 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2696 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2697 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2698 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2699 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 2700 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) 2701 AsmString = "fmovqpos %icc, $\x02, $\x01"; 2702 break; 2703 } 2704 if (MCInst_getNumOperands(MI) == 3 && 2705 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2706 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2707 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2708 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2709 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2710 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 2711 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) 2712 AsmString = "fmovqneg %icc, $\x02, $\x01"; 2713 break; 2714 } 2715 if (MCInst_getNumOperands(MI) == 3 && 2716 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2717 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2718 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2719 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2720 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2721 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 2722 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) 2723 AsmString = "fmovqvc %icc, $\x02, $\x01"; 2724 break; 2725 } 2726 if (MCInst_getNumOperands(MI) == 3 && 2727 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2728 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2729 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2730 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2731 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2732 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2733 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) 2734 AsmString = "fmovqvs %icc, $\x02, $\x01"; 2735 break; 2736 } 2737 return NULL; 2738 case SP_FMOVQ_XCC: 2739 if (MCInst_getNumOperands(MI) == 3 && 2740 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2741 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2742 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2743 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2744 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2745 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 2746 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) 2747 AsmString = "fmovqa %xcc, $\x02, $\x01"; 2748 break; 2749 } 2750 if (MCInst_getNumOperands(MI) == 3 && 2751 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2752 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2753 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2754 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2755 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2756 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2757 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) 2758 AsmString = "fmovqn %xcc, $\x02, $\x01"; 2759 break; 2760 } 2761 if (MCInst_getNumOperands(MI) == 3 && 2762 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2763 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2764 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2765 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2766 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2767 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 2768 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) 2769 AsmString = "fmovqne %xcc, $\x02, $\x01"; 2770 break; 2771 } 2772 if (MCInst_getNumOperands(MI) == 3 && 2773 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2774 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2775 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2776 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2777 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2778 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2779 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) 2780 AsmString = "fmovqe %xcc, $\x02, $\x01"; 2781 break; 2782 } 2783 if (MCInst_getNumOperands(MI) == 3 && 2784 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2785 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2786 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2787 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2788 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2789 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 2790 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) 2791 AsmString = "fmovqg %xcc, $\x02, $\x01"; 2792 break; 2793 } 2794 if (MCInst_getNumOperands(MI) == 3 && 2795 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2796 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2797 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2798 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2799 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2800 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 2801 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) 2802 AsmString = "fmovqle %xcc, $\x02, $\x01"; 2803 break; 2804 } 2805 if (MCInst_getNumOperands(MI) == 3 && 2806 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2807 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2808 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2809 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2810 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2811 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 2812 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) 2813 AsmString = "fmovqge %xcc, $\x02, $\x01"; 2814 break; 2815 } 2816 if (MCInst_getNumOperands(MI) == 3 && 2817 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2818 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2819 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2820 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2821 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2822 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 2823 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) 2824 AsmString = "fmovql %xcc, $\x02, $\x01"; 2825 break; 2826 } 2827 if (MCInst_getNumOperands(MI) == 3 && 2828 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2829 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2830 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2831 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2832 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2833 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 2834 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) 2835 AsmString = "fmovqgu %xcc, $\x02, $\x01"; 2836 break; 2837 } 2838 if (MCInst_getNumOperands(MI) == 3 && 2839 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2840 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2841 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2842 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2843 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2844 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 2845 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) 2846 AsmString = "fmovqleu %xcc, $\x02, $\x01"; 2847 break; 2848 } 2849 if (MCInst_getNumOperands(MI) == 3 && 2850 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2851 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2852 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2853 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2854 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2855 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 2856 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) 2857 AsmString = "fmovqcc %xcc, $\x02, $\x01"; 2858 break; 2859 } 2860 if (MCInst_getNumOperands(MI) == 3 && 2861 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2862 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2863 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2864 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2865 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2866 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 2867 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) 2868 AsmString = "fmovqcs %xcc, $\x02, $\x01"; 2869 break; 2870 } 2871 if (MCInst_getNumOperands(MI) == 3 && 2872 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2873 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2874 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2875 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2876 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2877 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 2878 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) 2879 AsmString = "fmovqpos %xcc, $\x02, $\x01"; 2880 break; 2881 } 2882 if (MCInst_getNumOperands(MI) == 3 && 2883 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2884 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2885 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2886 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2887 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2888 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 2889 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) 2890 AsmString = "fmovqneg %xcc, $\x02, $\x01"; 2891 break; 2892 } 2893 if (MCInst_getNumOperands(MI) == 3 && 2894 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2895 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2896 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2897 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2898 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2899 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 2900 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) 2901 AsmString = "fmovqvc %xcc, $\x02, $\x01"; 2902 break; 2903 } 2904 if (MCInst_getNumOperands(MI) == 3 && 2905 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2906 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 2907 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2908 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 2909 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2910 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2911 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) 2912 AsmString = "fmovqvs %xcc, $\x02, $\x01"; 2913 break; 2914 } 2915 return NULL; 2916 case SP_FMOVS_ICC: 2917 if (MCInst_getNumOperands(MI) == 3 && 2918 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2919 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2920 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2921 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2922 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2923 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 2924 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) 2925 AsmString = "fmovsa %icc, $\x02, $\x01"; 2926 break; 2927 } 2928 if (MCInst_getNumOperands(MI) == 3 && 2929 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2930 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2931 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2932 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2933 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2934 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2935 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) 2936 AsmString = "fmovsn %icc, $\x02, $\x01"; 2937 break; 2938 } 2939 if (MCInst_getNumOperands(MI) == 3 && 2940 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2941 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2942 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2943 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2944 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2945 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 2946 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) 2947 AsmString = "fmovsne %icc, $\x02, $\x01"; 2948 break; 2949 } 2950 if (MCInst_getNumOperands(MI) == 3 && 2951 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2952 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2953 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2954 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2955 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2956 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2957 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) 2958 AsmString = "fmovse %icc, $\x02, $\x01"; 2959 break; 2960 } 2961 if (MCInst_getNumOperands(MI) == 3 && 2962 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2963 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2964 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2965 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2966 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2967 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 2968 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) 2969 AsmString = "fmovsg %icc, $\x02, $\x01"; 2970 break; 2971 } 2972 if (MCInst_getNumOperands(MI) == 3 && 2973 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2974 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2975 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2976 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2977 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2978 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 2979 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) 2980 AsmString = "fmovsle %icc, $\x02, $\x01"; 2981 break; 2982 } 2983 if (MCInst_getNumOperands(MI) == 3 && 2984 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2985 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2986 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2987 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2988 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2989 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 2990 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) 2991 AsmString = "fmovsge %icc, $\x02, $\x01"; 2992 break; 2993 } 2994 if (MCInst_getNumOperands(MI) == 3 && 2995 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2996 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 2997 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2998 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 2999 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3000 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3001 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) 3002 AsmString = "fmovsl %icc, $\x02, $\x01"; 3003 break; 3004 } 3005 if (MCInst_getNumOperands(MI) == 3 && 3006 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3007 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3008 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3009 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3010 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3011 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3012 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) 3013 AsmString = "fmovsgu %icc, $\x02, $\x01"; 3014 break; 3015 } 3016 if (MCInst_getNumOperands(MI) == 3 && 3017 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3018 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3019 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3020 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3021 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3022 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3023 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) 3024 AsmString = "fmovsleu %icc, $\x02, $\x01"; 3025 break; 3026 } 3027 if (MCInst_getNumOperands(MI) == 3 && 3028 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3029 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3030 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3031 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3032 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3033 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3034 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) 3035 AsmString = "fmovscc %icc, $\x02, $\x01"; 3036 break; 3037 } 3038 if (MCInst_getNumOperands(MI) == 3 && 3039 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3040 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3041 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3042 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3043 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3044 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3045 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) 3046 AsmString = "fmovscs %icc, $\x02, $\x01"; 3047 break; 3048 } 3049 if (MCInst_getNumOperands(MI) == 3 && 3050 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3051 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3052 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3053 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3054 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3055 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3056 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) 3057 AsmString = "fmovspos %icc, $\x02, $\x01"; 3058 break; 3059 } 3060 if (MCInst_getNumOperands(MI) == 3 && 3061 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3062 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3063 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3064 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3065 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3066 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3067 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) 3068 AsmString = "fmovsneg %icc, $\x02, $\x01"; 3069 break; 3070 } 3071 if (MCInst_getNumOperands(MI) == 3 && 3072 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3073 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3074 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3075 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3076 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3077 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3078 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) 3079 AsmString = "fmovsvc %icc, $\x02, $\x01"; 3080 break; 3081 } 3082 if (MCInst_getNumOperands(MI) == 3 && 3083 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3084 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3085 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3086 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3087 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3088 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3089 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) 3090 AsmString = "fmovsvs %icc, $\x02, $\x01"; 3091 break; 3092 } 3093 return NULL; 3094 case SP_FMOVS_XCC: 3095 if (MCInst_getNumOperands(MI) == 3 && 3096 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3097 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3098 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3099 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3100 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3101 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3102 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) 3103 AsmString = "fmovsa %xcc, $\x02, $\x01"; 3104 break; 3105 } 3106 if (MCInst_getNumOperands(MI) == 3 && 3107 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3108 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3109 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3110 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3111 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3112 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3113 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) 3114 AsmString = "fmovsn %xcc, $\x02, $\x01"; 3115 break; 3116 } 3117 if (MCInst_getNumOperands(MI) == 3 && 3118 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3119 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3120 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3121 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3122 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3123 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 3124 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) 3125 AsmString = "fmovsne %xcc, $\x02, $\x01"; 3126 break; 3127 } 3128 if (MCInst_getNumOperands(MI) == 3 && 3129 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3130 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3131 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3132 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3133 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3134 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 3135 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) 3136 AsmString = "fmovse %xcc, $\x02, $\x01"; 3137 break; 3138 } 3139 if (MCInst_getNumOperands(MI) == 3 && 3140 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3141 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3142 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3143 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3144 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3145 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 3146 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) 3147 AsmString = "fmovsg %xcc, $\x02, $\x01"; 3148 break; 3149 } 3150 if (MCInst_getNumOperands(MI) == 3 && 3151 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3152 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3153 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3154 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3155 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3156 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 3157 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) 3158 AsmString = "fmovsle %xcc, $\x02, $\x01"; 3159 break; 3160 } 3161 if (MCInst_getNumOperands(MI) == 3 && 3162 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3163 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3164 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3165 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3166 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3167 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 3168 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) 3169 AsmString = "fmovsge %xcc, $\x02, $\x01"; 3170 break; 3171 } 3172 if (MCInst_getNumOperands(MI) == 3 && 3173 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3174 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3175 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3176 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3177 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3178 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3179 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) 3180 AsmString = "fmovsl %xcc, $\x02, $\x01"; 3181 break; 3182 } 3183 if (MCInst_getNumOperands(MI) == 3 && 3184 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3185 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3186 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3187 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3188 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3189 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3190 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) 3191 AsmString = "fmovsgu %xcc, $\x02, $\x01"; 3192 break; 3193 } 3194 if (MCInst_getNumOperands(MI) == 3 && 3195 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3196 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3197 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3198 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3199 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3200 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3201 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) 3202 AsmString = "fmovsleu %xcc, $\x02, $\x01"; 3203 break; 3204 } 3205 if (MCInst_getNumOperands(MI) == 3 && 3206 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3207 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3208 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3209 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3210 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3211 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3212 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) 3213 AsmString = "fmovscc %xcc, $\x02, $\x01"; 3214 break; 3215 } 3216 if (MCInst_getNumOperands(MI) == 3 && 3217 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3218 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3219 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3220 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3221 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3222 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3223 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) 3224 AsmString = "fmovscs %xcc, $\x02, $\x01"; 3225 break; 3226 } 3227 if (MCInst_getNumOperands(MI) == 3 && 3228 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3229 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3230 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3231 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3232 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3233 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3234 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) 3235 AsmString = "fmovspos %xcc, $\x02, $\x01"; 3236 break; 3237 } 3238 if (MCInst_getNumOperands(MI) == 3 && 3239 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3240 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3241 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3242 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3243 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3244 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3245 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) 3246 AsmString = "fmovsneg %xcc, $\x02, $\x01"; 3247 break; 3248 } 3249 if (MCInst_getNumOperands(MI) == 3 && 3250 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3251 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3252 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3253 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3254 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3255 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3256 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) 3257 AsmString = "fmovsvc %xcc, $\x02, $\x01"; 3258 break; 3259 } 3260 if (MCInst_getNumOperands(MI) == 3 && 3261 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3262 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 3263 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3264 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 3265 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3266 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3267 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) 3268 AsmString = "fmovsvs %xcc, $\x02, $\x01"; 3269 break; 3270 } 3271 return NULL; 3272 case SP_MOVICCri: 3273 if (MCInst_getNumOperands(MI) == 3 && 3274 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3275 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3276 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3277 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3278 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) 3279 AsmString = "mova %icc, $\x02, $\x01"; 3280 break; 3281 } 3282 if (MCInst_getNumOperands(MI) == 3 && 3283 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3284 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3285 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3286 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3287 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) 3288 AsmString = "movn %icc, $\x02, $\x01"; 3289 break; 3290 } 3291 if (MCInst_getNumOperands(MI) == 3 && 3292 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3293 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3294 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3295 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 3296 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) 3297 AsmString = "movne %icc, $\x02, $\x01"; 3298 break; 3299 } 3300 if (MCInst_getNumOperands(MI) == 3 && 3301 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3302 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3303 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3304 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 3305 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) 3306 AsmString = "move %icc, $\x02, $\x01"; 3307 break; 3308 } 3309 if (MCInst_getNumOperands(MI) == 3 && 3310 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3311 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3312 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3313 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 3314 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) 3315 AsmString = "movg %icc, $\x02, $\x01"; 3316 break; 3317 } 3318 if (MCInst_getNumOperands(MI) == 3 && 3319 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3320 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3321 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3322 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 3323 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) 3324 AsmString = "movle %icc, $\x02, $\x01"; 3325 break; 3326 } 3327 if (MCInst_getNumOperands(MI) == 3 && 3328 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3329 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3330 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3331 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 3332 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) 3333 AsmString = "movge %icc, $\x02, $\x01"; 3334 break; 3335 } 3336 if (MCInst_getNumOperands(MI) == 3 && 3337 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3338 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3339 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3340 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3341 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) 3342 AsmString = "movl %icc, $\x02, $\x01"; 3343 break; 3344 } 3345 if (MCInst_getNumOperands(MI) == 3 && 3346 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3347 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3348 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3349 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3350 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) 3351 AsmString = "movgu %icc, $\x02, $\x01"; 3352 break; 3353 } 3354 if (MCInst_getNumOperands(MI) == 3 && 3355 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3356 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3357 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3358 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3359 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) 3360 AsmString = "movleu %icc, $\x02, $\x01"; 3361 break; 3362 } 3363 if (MCInst_getNumOperands(MI) == 3 && 3364 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3365 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3366 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3367 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3368 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) 3369 AsmString = "movcc %icc, $\x02, $\x01"; 3370 break; 3371 } 3372 if (MCInst_getNumOperands(MI) == 3 && 3373 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3374 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3375 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3376 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3377 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) 3378 AsmString = "movcs %icc, $\x02, $\x01"; 3379 break; 3380 } 3381 if (MCInst_getNumOperands(MI) == 3 && 3382 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3383 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3384 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3385 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3386 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) 3387 AsmString = "movpos %icc, $\x02, $\x01"; 3388 break; 3389 } 3390 if (MCInst_getNumOperands(MI) == 3 && 3391 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3392 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3393 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3394 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3395 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) 3396 AsmString = "movneg %icc, $\x02, $\x01"; 3397 break; 3398 } 3399 if (MCInst_getNumOperands(MI) == 3 && 3400 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3401 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3402 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3403 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3404 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) 3405 AsmString = "movvc %icc, $\x02, $\x01"; 3406 break; 3407 } 3408 if (MCInst_getNumOperands(MI) == 3 && 3409 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3410 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3411 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3412 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3413 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) 3414 AsmString = "movvs %icc, $\x02, $\x01"; 3415 break; 3416 } 3417 return NULL; 3418 case SP_MOVICCrr: 3419 if (MCInst_getNumOperands(MI) == 3 && 3420 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3421 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3422 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3423 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3424 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3425 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3426 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) 3427 AsmString = "mova %icc, $\x02, $\x01"; 3428 break; 3429 } 3430 if (MCInst_getNumOperands(MI) == 3 && 3431 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3432 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3433 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3434 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3435 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3436 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3437 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) 3438 AsmString = "movn %icc, $\x02, $\x01"; 3439 break; 3440 } 3441 if (MCInst_getNumOperands(MI) == 3 && 3442 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3443 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3444 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3445 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3446 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3447 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 3448 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) 3449 AsmString = "movne %icc, $\x02, $\x01"; 3450 break; 3451 } 3452 if (MCInst_getNumOperands(MI) == 3 && 3453 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3454 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3455 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3456 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3457 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3458 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 3459 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) 3460 AsmString = "move %icc, $\x02, $\x01"; 3461 break; 3462 } 3463 if (MCInst_getNumOperands(MI) == 3 && 3464 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3465 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3466 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3467 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3468 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3469 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 3470 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) 3471 AsmString = "movg %icc, $\x02, $\x01"; 3472 break; 3473 } 3474 if (MCInst_getNumOperands(MI) == 3 && 3475 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3476 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3477 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3478 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3479 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3480 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 3481 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) 3482 AsmString = "movle %icc, $\x02, $\x01"; 3483 break; 3484 } 3485 if (MCInst_getNumOperands(MI) == 3 && 3486 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3487 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3488 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3489 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3490 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3491 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 3492 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) 3493 AsmString = "movge %icc, $\x02, $\x01"; 3494 break; 3495 } 3496 if (MCInst_getNumOperands(MI) == 3 && 3497 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3498 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3499 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3500 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3501 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3502 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3503 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) 3504 AsmString = "movl %icc, $\x02, $\x01"; 3505 break; 3506 } 3507 if (MCInst_getNumOperands(MI) == 3 && 3508 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3509 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3510 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3511 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3512 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3513 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3514 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) 3515 AsmString = "movgu %icc, $\x02, $\x01"; 3516 break; 3517 } 3518 if (MCInst_getNumOperands(MI) == 3 && 3519 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3520 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3521 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3522 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3523 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3524 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3525 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) 3526 AsmString = "movleu %icc, $\x02, $\x01"; 3527 break; 3528 } 3529 if (MCInst_getNumOperands(MI) == 3 && 3530 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3531 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3532 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3533 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3534 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3535 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3536 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) 3537 AsmString = "movcc %icc, $\x02, $\x01"; 3538 break; 3539 } 3540 if (MCInst_getNumOperands(MI) == 3 && 3541 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3542 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3543 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3544 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3545 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3546 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3547 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) 3548 AsmString = "movcs %icc, $\x02, $\x01"; 3549 break; 3550 } 3551 if (MCInst_getNumOperands(MI) == 3 && 3552 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3553 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3554 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3555 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3556 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3557 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3558 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) 3559 AsmString = "movpos %icc, $\x02, $\x01"; 3560 break; 3561 } 3562 if (MCInst_getNumOperands(MI) == 3 && 3563 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3564 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3565 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3566 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3567 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3568 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3569 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) 3570 AsmString = "movneg %icc, $\x02, $\x01"; 3571 break; 3572 } 3573 if (MCInst_getNumOperands(MI) == 3 && 3574 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3575 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3576 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3577 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3578 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3579 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3580 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) 3581 AsmString = "movvc %icc, $\x02, $\x01"; 3582 break; 3583 } 3584 if (MCInst_getNumOperands(MI) == 3 && 3585 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3586 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3587 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3588 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3589 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3590 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3591 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) 3592 AsmString = "movvs %icc, $\x02, $\x01"; 3593 break; 3594 } 3595 return NULL; 3596 case SP_MOVXCCri: 3597 if (MCInst_getNumOperands(MI) == 3 && 3598 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3599 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3600 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3601 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3602 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) 3603 AsmString = "mova %xcc, $\x02, $\x01"; 3604 break; 3605 } 3606 if (MCInst_getNumOperands(MI) == 3 && 3607 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3608 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3609 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3610 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3611 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) 3612 AsmString = "movn %xcc, $\x02, $\x01"; 3613 break; 3614 } 3615 if (MCInst_getNumOperands(MI) == 3 && 3616 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3617 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3618 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3619 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 3620 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) 3621 AsmString = "movne %xcc, $\x02, $\x01"; 3622 break; 3623 } 3624 if (MCInst_getNumOperands(MI) == 3 && 3625 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3626 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3627 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3628 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 3629 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) 3630 AsmString = "move %xcc, $\x02, $\x01"; 3631 break; 3632 } 3633 if (MCInst_getNumOperands(MI) == 3 && 3634 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3635 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3636 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3637 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 3638 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) 3639 AsmString = "movg %xcc, $\x02, $\x01"; 3640 break; 3641 } 3642 if (MCInst_getNumOperands(MI) == 3 && 3643 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3644 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3645 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3646 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 3647 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) 3648 AsmString = "movle %xcc, $\x02, $\x01"; 3649 break; 3650 } 3651 if (MCInst_getNumOperands(MI) == 3 && 3652 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3653 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3654 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3655 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 3656 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) 3657 AsmString = "movge %xcc, $\x02, $\x01"; 3658 break; 3659 } 3660 if (MCInst_getNumOperands(MI) == 3 && 3661 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3662 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3663 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3664 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3665 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) 3666 AsmString = "movl %xcc, $\x02, $\x01"; 3667 break; 3668 } 3669 if (MCInst_getNumOperands(MI) == 3 && 3670 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3671 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3672 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3673 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3674 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) 3675 AsmString = "movgu %xcc, $\x02, $\x01"; 3676 break; 3677 } 3678 if (MCInst_getNumOperands(MI) == 3 && 3679 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3680 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3681 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3682 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3683 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) 3684 AsmString = "movleu %xcc, $\x02, $\x01"; 3685 break; 3686 } 3687 if (MCInst_getNumOperands(MI) == 3 && 3688 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3689 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3690 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3691 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3692 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) 3693 AsmString = "movcc %xcc, $\x02, $\x01"; 3694 break; 3695 } 3696 if (MCInst_getNumOperands(MI) == 3 && 3697 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3698 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3699 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3700 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3701 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) 3702 AsmString = "movcs %xcc, $\x02, $\x01"; 3703 break; 3704 } 3705 if (MCInst_getNumOperands(MI) == 3 && 3706 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3707 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3708 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3709 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3710 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) 3711 AsmString = "movpos %xcc, $\x02, $\x01"; 3712 break; 3713 } 3714 if (MCInst_getNumOperands(MI) == 3 && 3715 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3716 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3717 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3718 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3719 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) 3720 AsmString = "movneg %xcc, $\x02, $\x01"; 3721 break; 3722 } 3723 if (MCInst_getNumOperands(MI) == 3 && 3724 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3725 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3726 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3727 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3728 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) 3729 AsmString = "movvc %xcc, $\x02, $\x01"; 3730 break; 3731 } 3732 if (MCInst_getNumOperands(MI) == 3 && 3733 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3734 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3735 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3736 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3737 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) 3738 AsmString = "movvs %xcc, $\x02, $\x01"; 3739 break; 3740 } 3741 return NULL; 3742 case SP_MOVXCCrr: 3743 if (MCInst_getNumOperands(MI) == 3 && 3744 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3745 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3746 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3747 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3748 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3749 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3750 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) 3751 AsmString = "mova %xcc, $\x02, $\x01"; 3752 break; 3753 } 3754 if (MCInst_getNumOperands(MI) == 3 && 3755 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3756 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3757 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3758 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3759 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3760 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3761 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) 3762 AsmString = "movn %xcc, $\x02, $\x01"; 3763 break; 3764 } 3765 if (MCInst_getNumOperands(MI) == 3 && 3766 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3767 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3768 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3769 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3770 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3771 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 3772 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) 3773 AsmString = "movne %xcc, $\x02, $\x01"; 3774 break; 3775 } 3776 if (MCInst_getNumOperands(MI) == 3 && 3777 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3778 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3779 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3780 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3781 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3782 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 3783 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) 3784 AsmString = "move %xcc, $\x02, $\x01"; 3785 break; 3786 } 3787 if (MCInst_getNumOperands(MI) == 3 && 3788 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3789 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3790 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3791 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3792 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3793 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 3794 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) 3795 AsmString = "movg %xcc, $\x02, $\x01"; 3796 break; 3797 } 3798 if (MCInst_getNumOperands(MI) == 3 && 3799 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3800 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3801 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3802 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3803 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3804 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 3805 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) 3806 AsmString = "movle %xcc, $\x02, $\x01"; 3807 break; 3808 } 3809 if (MCInst_getNumOperands(MI) == 3 && 3810 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3811 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3812 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3813 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3814 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3815 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 3816 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) 3817 AsmString = "movge %xcc, $\x02, $\x01"; 3818 break; 3819 } 3820 if (MCInst_getNumOperands(MI) == 3 && 3821 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3822 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3823 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3824 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3825 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3826 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 3827 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) 3828 AsmString = "movl %xcc, $\x02, $\x01"; 3829 break; 3830 } 3831 if (MCInst_getNumOperands(MI) == 3 && 3832 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3833 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3834 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3835 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3836 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3837 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 3838 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) 3839 AsmString = "movgu %xcc, $\x02, $\x01"; 3840 break; 3841 } 3842 if (MCInst_getNumOperands(MI) == 3 && 3843 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3844 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3845 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3846 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3847 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3848 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 3849 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) 3850 AsmString = "movleu %xcc, $\x02, $\x01"; 3851 break; 3852 } 3853 if (MCInst_getNumOperands(MI) == 3 && 3854 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3855 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3856 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3857 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3858 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3859 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 3860 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) 3861 AsmString = "movcc %xcc, $\x02, $\x01"; 3862 break; 3863 } 3864 if (MCInst_getNumOperands(MI) == 3 && 3865 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3866 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3867 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3868 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3869 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3870 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 3871 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) 3872 AsmString = "movcs %xcc, $\x02, $\x01"; 3873 break; 3874 } 3875 if (MCInst_getNumOperands(MI) == 3 && 3876 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3877 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3878 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3879 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3880 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3881 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 3882 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) 3883 AsmString = "movpos %xcc, $\x02, $\x01"; 3884 break; 3885 } 3886 if (MCInst_getNumOperands(MI) == 3 && 3887 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3888 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3889 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3890 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3891 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3892 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 3893 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) 3894 AsmString = "movneg %xcc, $\x02, $\x01"; 3895 break; 3896 } 3897 if (MCInst_getNumOperands(MI) == 3 && 3898 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3899 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3900 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3901 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3902 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3903 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 3904 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) 3905 AsmString = "movvc %xcc, $\x02, $\x01"; 3906 break; 3907 } 3908 if (MCInst_getNumOperands(MI) == 3 && 3909 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3910 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3911 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 3912 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 3913 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3914 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 3915 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) 3916 AsmString = "movvs %xcc, $\x02, $\x01"; 3917 break; 3918 } 3919 return NULL; 3920 case SP_ORri: 3921 if (MCInst_getNumOperands(MI) == 3 && 3922 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3923 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3924 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) { 3925 // (ORri IntRegs:$rd, G0, i32imm:$simm13) 3926 AsmString = "mov $\x03, $\x01"; 3927 break; 3928 } 3929 return NULL; 3930 case SP_ORrr: 3931 if (MCInst_getNumOperands(MI) == 3 && 3932 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3933 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3934 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && 3935 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 3936 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) { 3937 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) 3938 AsmString = "mov $\x03, $\x01"; 3939 break; 3940 } 3941 return NULL; 3942 case SP_RESTORErr: 3943 if (MCInst_getNumOperands(MI) == 3 && 3944 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 3945 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && 3946 MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) { 3947 // (RESTORErr G0, G0, G0) 3948 AsmString = "restore"; 3949 break; 3950 } 3951 return NULL; 3952 case SP_RET: 3953 if (MCInst_getNumOperands(MI) == 1 && 3954 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 3955 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { 3956 // (RET 8) 3957 AsmString = "ret"; 3958 break; 3959 } 3960 return NULL; 3961 case SP_RETL: 3962 if (MCInst_getNumOperands(MI) == 1 && 3963 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 3964 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { 3965 // (RETL 8) 3966 AsmString = "retl"; 3967 break; 3968 } 3969 return NULL; 3970 case SP_TXCCri: 3971 if (MCInst_getNumOperands(MI) == 3 && 3972 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3973 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3974 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3975 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3976 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) 3977 AsmString = "ta %xcc, $\x01 + $\x02"; 3978 break; 3979 } 3980 if (MCInst_getNumOperands(MI) == 3 && 3981 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 3982 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3983 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 3984 // (TXCCri G0, i32imm:$imm, 8) 3985 AsmString = "ta %xcc, $\x02"; 3986 break; 3987 } 3988 if (MCInst_getNumOperands(MI) == 3 && 3989 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 3990 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 3991 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 3992 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 3993 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) 3994 AsmString = "tn %xcc, $\x01 + $\x02"; 3995 break; 3996 } 3997 if (MCInst_getNumOperands(MI) == 3 && 3998 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 3999 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4000 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 4001 // (TXCCri G0, i32imm:$imm, 0) 4002 AsmString = "tn %xcc, $\x02"; 4003 break; 4004 } 4005 if (MCInst_getNumOperands(MI) == 3 && 4006 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4007 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4008 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4009 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 4010 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) 4011 AsmString = "tne %xcc, $\x01 + $\x02"; 4012 break; 4013 } 4014 if (MCInst_getNumOperands(MI) == 3 && 4015 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4016 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4017 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 4018 // (TXCCri G0, i32imm:$imm, 9) 4019 AsmString = "tne %xcc, $\x02"; 4020 break; 4021 } 4022 if (MCInst_getNumOperands(MI) == 3 && 4023 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4024 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4025 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4026 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 4027 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) 4028 AsmString = "te %xcc, $\x01 + $\x02"; 4029 break; 4030 } 4031 if (MCInst_getNumOperands(MI) == 3 && 4032 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4033 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4034 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 4035 // (TXCCri G0, i32imm:$imm, 1) 4036 AsmString = "te %xcc, $\x02"; 4037 break; 4038 } 4039 if (MCInst_getNumOperands(MI) == 3 && 4040 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4041 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4042 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4043 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 4044 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) 4045 AsmString = "tg %xcc, $\x01 + $\x02"; 4046 break; 4047 } 4048 if (MCInst_getNumOperands(MI) == 3 && 4049 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4050 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4051 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 4052 // (TXCCri G0, i32imm:$imm, 10) 4053 AsmString = "tg %xcc, $\x02"; 4054 break; 4055 } 4056 if (MCInst_getNumOperands(MI) == 3 && 4057 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4058 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4059 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4060 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 4061 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) 4062 AsmString = "tle %xcc, $\x01 + $\x02"; 4063 break; 4064 } 4065 if (MCInst_getNumOperands(MI) == 3 && 4066 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4067 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4068 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 4069 // (TXCCri G0, i32imm:$imm, 2) 4070 AsmString = "tle %xcc, $\x02"; 4071 break; 4072 } 4073 if (MCInst_getNumOperands(MI) == 3 && 4074 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4075 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4076 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4077 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 4078 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) 4079 AsmString = "tge %xcc, $\x01 + $\x02"; 4080 break; 4081 } 4082 if (MCInst_getNumOperands(MI) == 3 && 4083 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4084 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4085 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 4086 // (TXCCri G0, i32imm:$imm, 11) 4087 AsmString = "tge %xcc, $\x02"; 4088 break; 4089 } 4090 if (MCInst_getNumOperands(MI) == 3 && 4091 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4092 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4093 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4094 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 4095 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) 4096 AsmString = "tl %xcc, $\x01 + $\x02"; 4097 break; 4098 } 4099 if (MCInst_getNumOperands(MI) == 3 && 4100 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4101 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4102 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 4103 // (TXCCri G0, i32imm:$imm, 3) 4104 AsmString = "tl %xcc, $\x02"; 4105 break; 4106 } 4107 if (MCInst_getNumOperands(MI) == 3 && 4108 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4109 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4110 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4111 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 4112 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) 4113 AsmString = "tgu %xcc, $\x01 + $\x02"; 4114 break; 4115 } 4116 if (MCInst_getNumOperands(MI) == 3 && 4117 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4118 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4119 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 4120 // (TXCCri G0, i32imm:$imm, 12) 4121 AsmString = "tgu %xcc, $\x02"; 4122 break; 4123 } 4124 if (MCInst_getNumOperands(MI) == 3 && 4125 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4126 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4127 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4128 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 4129 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) 4130 AsmString = "tleu %xcc, $\x01 + $\x02"; 4131 break; 4132 } 4133 if (MCInst_getNumOperands(MI) == 3 && 4134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4135 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4136 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 4137 // (TXCCri G0, i32imm:$imm, 4) 4138 AsmString = "tleu %xcc, $\x02"; 4139 break; 4140 } 4141 if (MCInst_getNumOperands(MI) == 3 && 4142 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4143 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4144 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4145 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 4146 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) 4147 AsmString = "tcc %xcc, $\x01 + $\x02"; 4148 break; 4149 } 4150 if (MCInst_getNumOperands(MI) == 3 && 4151 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4152 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4153 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 4154 // (TXCCri G0, i32imm:$imm, 13) 4155 AsmString = "tcc %xcc, $\x02"; 4156 break; 4157 } 4158 if (MCInst_getNumOperands(MI) == 3 && 4159 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4160 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4161 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4162 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 4163 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) 4164 AsmString = "tcs %xcc, $\x01 + $\x02"; 4165 break; 4166 } 4167 if (MCInst_getNumOperands(MI) == 3 && 4168 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4169 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4170 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 4171 // (TXCCri G0, i32imm:$imm, 5) 4172 AsmString = "tcs %xcc, $\x02"; 4173 break; 4174 } 4175 if (MCInst_getNumOperands(MI) == 3 && 4176 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4177 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4178 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4179 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 4180 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) 4181 AsmString = "tpos %xcc, $\x01 + $\x02"; 4182 break; 4183 } 4184 if (MCInst_getNumOperands(MI) == 3 && 4185 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4186 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4187 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 4188 // (TXCCri G0, i32imm:$imm, 14) 4189 AsmString = "tpos %xcc, $\x02"; 4190 break; 4191 } 4192 if (MCInst_getNumOperands(MI) == 3 && 4193 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4194 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4195 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4196 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 4197 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) 4198 AsmString = "tneg %xcc, $\x01 + $\x02"; 4199 break; 4200 } 4201 if (MCInst_getNumOperands(MI) == 3 && 4202 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4203 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4204 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 4205 // (TXCCri G0, i32imm:$imm, 6) 4206 AsmString = "tneg %xcc, $\x02"; 4207 break; 4208 } 4209 if (MCInst_getNumOperands(MI) == 3 && 4210 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4211 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4212 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4213 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 4214 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) 4215 AsmString = "tvc %xcc, $\x01 + $\x02"; 4216 break; 4217 } 4218 if (MCInst_getNumOperands(MI) == 3 && 4219 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4220 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4221 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 4222 // (TXCCri G0, i32imm:$imm, 15) 4223 AsmString = "tvc %xcc, $\x02"; 4224 break; 4225 } 4226 if (MCInst_getNumOperands(MI) == 3 && 4227 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4228 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4229 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4230 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 4231 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) 4232 AsmString = "tvs %xcc, $\x01 + $\x02"; 4233 break; 4234 } 4235 if (MCInst_getNumOperands(MI) == 3 && 4236 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4237 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4238 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 4239 // (TXCCri G0, i32imm:$imm, 7) 4240 AsmString = "tvs %xcc, $\x02"; 4241 break; 4242 } 4243 return NULL; 4244 case SP_TXCCrr: 4245 if (MCInst_getNumOperands(MI) == 3 && 4246 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4247 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4248 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4249 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4250 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4251 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 4252 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) 4253 AsmString = "ta %xcc, $\x01 + $\x02"; 4254 break; 4255 } 4256 if (MCInst_getNumOperands(MI) == 3 && 4257 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4258 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4259 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4260 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4261 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { 4262 // (TXCCrr G0, IntRegs:$rs2, 8) 4263 AsmString = "ta %xcc, $\x02"; 4264 break; 4265 } 4266 if (MCInst_getNumOperands(MI) == 3 && 4267 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4268 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4269 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4270 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4271 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4272 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 4273 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) 4274 AsmString = "tn %xcc, $\x01 + $\x02"; 4275 break; 4276 } 4277 if (MCInst_getNumOperands(MI) == 3 && 4278 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4279 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4280 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4281 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4282 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 4283 // (TXCCrr G0, IntRegs:$rs2, 0) 4284 AsmString = "tn %xcc, $\x02"; 4285 break; 4286 } 4287 if (MCInst_getNumOperands(MI) == 3 && 4288 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4289 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4290 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4291 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4292 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4293 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 4294 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) 4295 AsmString = "tne %xcc, $\x01 + $\x02"; 4296 break; 4297 } 4298 if (MCInst_getNumOperands(MI) == 3 && 4299 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4300 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4301 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4302 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4303 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { 4304 // (TXCCrr G0, IntRegs:$rs2, 9) 4305 AsmString = "tne %xcc, $\x02"; 4306 break; 4307 } 4308 if (MCInst_getNumOperands(MI) == 3 && 4309 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4310 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4311 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4312 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4313 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4314 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 4315 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) 4316 AsmString = "te %xcc, $\x01 + $\x02"; 4317 break; 4318 } 4319 if (MCInst_getNumOperands(MI) == 3 && 4320 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4321 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4322 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4323 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4324 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 4325 // (TXCCrr G0, IntRegs:$rs2, 1) 4326 AsmString = "te %xcc, $\x02"; 4327 break; 4328 } 4329 if (MCInst_getNumOperands(MI) == 3 && 4330 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4331 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4332 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4333 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4334 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4335 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 4336 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) 4337 AsmString = "tg %xcc, $\x01 + $\x02"; 4338 break; 4339 } 4340 if (MCInst_getNumOperands(MI) == 3 && 4341 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4342 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4343 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4344 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4345 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { 4346 // (TXCCrr G0, IntRegs:$rs2, 10) 4347 AsmString = "tg %xcc, $\x02"; 4348 break; 4349 } 4350 if (MCInst_getNumOperands(MI) == 3 && 4351 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4352 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4353 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4354 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4355 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4356 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 4357 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) 4358 AsmString = "tle %xcc, $\x01 + $\x02"; 4359 break; 4360 } 4361 if (MCInst_getNumOperands(MI) == 3 && 4362 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4363 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4364 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4365 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4366 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { 4367 // (TXCCrr G0, IntRegs:$rs2, 2) 4368 AsmString = "tle %xcc, $\x02"; 4369 break; 4370 } 4371 if (MCInst_getNumOperands(MI) == 3 && 4372 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4373 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4374 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4375 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4376 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4377 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 4378 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) 4379 AsmString = "tge %xcc, $\x01 + $\x02"; 4380 break; 4381 } 4382 if (MCInst_getNumOperands(MI) == 3 && 4383 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4384 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4385 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4386 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4387 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { 4388 // (TXCCrr G0, IntRegs:$rs2, 11) 4389 AsmString = "tge %xcc, $\x02"; 4390 break; 4391 } 4392 if (MCInst_getNumOperands(MI) == 3 && 4393 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4394 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4395 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4396 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4397 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4398 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 4399 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) 4400 AsmString = "tl %xcc, $\x01 + $\x02"; 4401 break; 4402 } 4403 if (MCInst_getNumOperands(MI) == 3 && 4404 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4405 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4406 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4407 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4408 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { 4409 // (TXCCrr G0, IntRegs:$rs2, 3) 4410 AsmString = "tl %xcc, $\x02"; 4411 break; 4412 } 4413 if (MCInst_getNumOperands(MI) == 3 && 4414 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4415 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4416 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4417 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4418 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4419 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 4420 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) 4421 AsmString = "tgu %xcc, $\x01 + $\x02"; 4422 break; 4423 } 4424 if (MCInst_getNumOperands(MI) == 3 && 4425 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4426 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4427 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4428 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4429 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { 4430 // (TXCCrr G0, IntRegs:$rs2, 12) 4431 AsmString = "tgu %xcc, $\x02"; 4432 break; 4433 } 4434 if (MCInst_getNumOperands(MI) == 3 && 4435 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4436 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4437 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4438 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4439 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4440 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 4441 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) 4442 AsmString = "tleu %xcc, $\x01 + $\x02"; 4443 break; 4444 } 4445 if (MCInst_getNumOperands(MI) == 3 && 4446 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4447 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4448 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4449 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4450 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { 4451 // (TXCCrr G0, IntRegs:$rs2, 4) 4452 AsmString = "tleu %xcc, $\x02"; 4453 break; 4454 } 4455 if (MCInst_getNumOperands(MI) == 3 && 4456 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4457 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4458 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4459 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4460 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4461 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 4462 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) 4463 AsmString = "tcc %xcc, $\x01 + $\x02"; 4464 break; 4465 } 4466 if (MCInst_getNumOperands(MI) == 3 && 4467 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4468 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4469 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4470 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4471 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { 4472 // (TXCCrr G0, IntRegs:$rs2, 13) 4473 AsmString = "tcc %xcc, $\x02"; 4474 break; 4475 } 4476 if (MCInst_getNumOperands(MI) == 3 && 4477 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4478 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4479 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4480 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4481 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4482 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 4483 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) 4484 AsmString = "tcs %xcc, $\x01 + $\x02"; 4485 break; 4486 } 4487 if (MCInst_getNumOperands(MI) == 3 && 4488 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4489 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4490 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4491 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4492 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { 4493 // (TXCCrr G0, IntRegs:$rs2, 5) 4494 AsmString = "tcs %xcc, $\x02"; 4495 break; 4496 } 4497 if (MCInst_getNumOperands(MI) == 3 && 4498 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4499 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4500 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4501 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4502 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4503 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 4504 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) 4505 AsmString = "tpos %xcc, $\x01 + $\x02"; 4506 break; 4507 } 4508 if (MCInst_getNumOperands(MI) == 3 && 4509 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4510 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4511 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4512 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4513 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { 4514 // (TXCCrr G0, IntRegs:$rs2, 14) 4515 AsmString = "tpos %xcc, $\x02"; 4516 break; 4517 } 4518 if (MCInst_getNumOperands(MI) == 3 && 4519 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4520 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4521 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4522 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4523 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4524 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 4525 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) 4526 AsmString = "tneg %xcc, $\x01 + $\x02"; 4527 break; 4528 } 4529 if (MCInst_getNumOperands(MI) == 3 && 4530 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4531 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4532 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4533 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4534 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { 4535 // (TXCCrr G0, IntRegs:$rs2, 6) 4536 AsmString = "tneg %xcc, $\x02"; 4537 break; 4538 } 4539 if (MCInst_getNumOperands(MI) == 3 && 4540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4541 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4542 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4543 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4544 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4545 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 4546 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) 4547 AsmString = "tvc %xcc, $\x01 + $\x02"; 4548 break; 4549 } 4550 if (MCInst_getNumOperands(MI) == 3 && 4551 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4552 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4553 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4554 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4555 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { 4556 // (TXCCrr G0, IntRegs:$rs2, 15) 4557 AsmString = "tvc %xcc, $\x02"; 4558 break; 4559 } 4560 if (MCInst_getNumOperands(MI) == 3 && 4561 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4562 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 4563 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4564 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4565 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4566 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 4567 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) 4568 AsmString = "tvs %xcc, $\x01 + $\x02"; 4569 break; 4570 } 4571 if (MCInst_getNumOperands(MI) == 3 && 4572 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && 4573 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4574 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && 4575 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 4576 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 4577 // (TXCCrr G0, IntRegs:$rs2, 7) 4578 AsmString = "tvs %xcc, $\x02"; 4579 break; 4580 } 4581 return NULL; 4582 case SP_V9FCMPD: 4583 if (MCInst_getNumOperands(MI) == 3 && 4584 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4585 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4586 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 4587 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4588 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { 4589 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) 4590 AsmString = "fcmpd $\x02, $\x03"; 4591 break; 4592 } 4593 return NULL; 4594 case SP_V9FCMPED: 4595 if (MCInst_getNumOperands(MI) == 3 && 4596 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4597 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4598 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && 4599 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4600 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { 4601 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) 4602 AsmString = "fcmped $\x02, $\x03"; 4603 break; 4604 } 4605 return NULL; 4606 case SP_V9FCMPEQ: 4607 if (MCInst_getNumOperands(MI) == 3 && 4608 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4609 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4610 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 4611 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4612 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { 4613 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) 4614 AsmString = "fcmpeq $\x02, $\x03"; 4615 break; 4616 } 4617 return NULL; 4618 case SP_V9FCMPES: 4619 if (MCInst_getNumOperands(MI) == 3 && 4620 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4621 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4622 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 4623 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4624 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { 4625 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) 4626 AsmString = "fcmpes $\x02, $\x03"; 4627 break; 4628 } 4629 return NULL; 4630 case SP_V9FCMPQ: 4631 if (MCInst_getNumOperands(MI) == 3 && 4632 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4633 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4634 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && 4635 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4636 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { 4637 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) 4638 AsmString = "fcmpq $\x02, $\x03"; 4639 break; 4640 } 4641 return NULL; 4642 case SP_V9FCMPS: 4643 if (MCInst_getNumOperands(MI) == 3 && 4644 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && 4645 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4646 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && 4647 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4648 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { 4649 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) 4650 AsmString = "fcmps $\x02, $\x03"; 4651 break; 4652 } 4653 return NULL; 4654 case SP_V9FMOVD_FCC: 4655 if (MCInst_getNumOperands(MI) == 4 && 4656 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4657 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4658 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4659 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4660 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4661 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4662 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4663 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 4664 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) 4665 AsmString = "fmovda $\x02, $\x03, $\x01"; 4666 break; 4667 } 4668 if (MCInst_getNumOperands(MI) == 4 && 4669 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4670 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4671 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4672 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4673 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4674 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4675 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4676 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { 4677 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) 4678 AsmString = "fmovdn $\x02, $\x03, $\x01"; 4679 break; 4680 } 4681 if (MCInst_getNumOperands(MI) == 4 && 4682 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4683 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4684 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4685 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4686 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4687 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4688 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4689 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 4690 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) 4691 AsmString = "fmovdu $\x02, $\x03, $\x01"; 4692 break; 4693 } 4694 if (MCInst_getNumOperands(MI) == 4 && 4695 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4696 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4697 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4698 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4699 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4700 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4701 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4702 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { 4703 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) 4704 AsmString = "fmovdg $\x02, $\x03, $\x01"; 4705 break; 4706 } 4707 if (MCInst_getNumOperands(MI) == 4 && 4708 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4709 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4710 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4711 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4712 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4713 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4714 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4715 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { 4716 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) 4717 AsmString = "fmovdug $\x02, $\x03, $\x01"; 4718 break; 4719 } 4720 if (MCInst_getNumOperands(MI) == 4 && 4721 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4722 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4723 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4724 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4725 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4726 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4727 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4728 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { 4729 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) 4730 AsmString = "fmovdl $\x02, $\x03, $\x01"; 4731 break; 4732 } 4733 if (MCInst_getNumOperands(MI) == 4 && 4734 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4735 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4736 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4737 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4738 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4739 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4740 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4741 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { 4742 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) 4743 AsmString = "fmovdul $\x02, $\x03, $\x01"; 4744 break; 4745 } 4746 if (MCInst_getNumOperands(MI) == 4 && 4747 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4748 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4749 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4750 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4751 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4752 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4753 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4754 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { 4755 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) 4756 AsmString = "fmovdlg $\x02, $\x03, $\x01"; 4757 break; 4758 } 4759 if (MCInst_getNumOperands(MI) == 4 && 4760 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4761 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4762 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4763 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4764 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4765 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4766 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4767 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { 4768 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) 4769 AsmString = "fmovdne $\x02, $\x03, $\x01"; 4770 break; 4771 } 4772 if (MCInst_getNumOperands(MI) == 4 && 4773 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4774 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4775 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4776 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4777 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4778 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4779 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4780 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { 4781 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) 4782 AsmString = "fmovde $\x02, $\x03, $\x01"; 4783 break; 4784 } 4785 if (MCInst_getNumOperands(MI) == 4 && 4786 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4787 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4788 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4789 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4790 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4791 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4792 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4793 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { 4794 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) 4795 AsmString = "fmovdue $\x02, $\x03, $\x01"; 4796 break; 4797 } 4798 if (MCInst_getNumOperands(MI) == 4 && 4799 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4800 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4801 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4802 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4803 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4804 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4805 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4806 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { 4807 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) 4808 AsmString = "fmovdge $\x02, $\x03, $\x01"; 4809 break; 4810 } 4811 if (MCInst_getNumOperands(MI) == 4 && 4812 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4813 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4814 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4815 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4816 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4817 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4818 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4819 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { 4820 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) 4821 AsmString = "fmovduge $\x02, $\x03, $\x01"; 4822 break; 4823 } 4824 if (MCInst_getNumOperands(MI) == 4 && 4825 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4826 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4827 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4828 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4829 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4830 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4831 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4832 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { 4833 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) 4834 AsmString = "fmovdle $\x02, $\x03, $\x01"; 4835 break; 4836 } 4837 if (MCInst_getNumOperands(MI) == 4 && 4838 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4839 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4840 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4841 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4842 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4843 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4844 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4845 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { 4846 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) 4847 AsmString = "fmovdule $\x02, $\x03, $\x01"; 4848 break; 4849 } 4850 if (MCInst_getNumOperands(MI) == 4 && 4851 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4852 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && 4853 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4854 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4855 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4856 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && 4857 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4858 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 4859 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) 4860 AsmString = "fmovdo $\x02, $\x03, $\x01"; 4861 break; 4862 } 4863 return NULL; 4864 case SP_V9FMOVQ_FCC: 4865 if (MCInst_getNumOperands(MI) == 4 && 4866 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4867 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4868 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4869 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4870 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4871 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4872 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4873 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 4874 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) 4875 AsmString = "fmovqa $\x02, $\x03, $\x01"; 4876 break; 4877 } 4878 if (MCInst_getNumOperands(MI) == 4 && 4879 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4880 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4881 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4882 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4883 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4884 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4885 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4886 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { 4887 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) 4888 AsmString = "fmovqn $\x02, $\x03, $\x01"; 4889 break; 4890 } 4891 if (MCInst_getNumOperands(MI) == 4 && 4892 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4893 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4894 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4895 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4896 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4897 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4898 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4899 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 4900 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) 4901 AsmString = "fmovqu $\x02, $\x03, $\x01"; 4902 break; 4903 } 4904 if (MCInst_getNumOperands(MI) == 4 && 4905 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4906 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4907 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4908 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4909 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4910 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4911 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4912 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { 4913 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) 4914 AsmString = "fmovqg $\x02, $\x03, $\x01"; 4915 break; 4916 } 4917 if (MCInst_getNumOperands(MI) == 4 && 4918 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4919 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4920 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4921 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4922 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4923 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4924 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4925 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { 4926 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) 4927 AsmString = "fmovqug $\x02, $\x03, $\x01"; 4928 break; 4929 } 4930 if (MCInst_getNumOperands(MI) == 4 && 4931 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4932 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4933 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4934 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4935 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4936 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4937 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4938 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { 4939 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) 4940 AsmString = "fmovql $\x02, $\x03, $\x01"; 4941 break; 4942 } 4943 if (MCInst_getNumOperands(MI) == 4 && 4944 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4945 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4946 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4947 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4948 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4949 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4950 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4951 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { 4952 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) 4953 AsmString = "fmovqul $\x02, $\x03, $\x01"; 4954 break; 4955 } 4956 if (MCInst_getNumOperands(MI) == 4 && 4957 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4958 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4959 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4960 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4961 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4962 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4963 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4964 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { 4965 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) 4966 AsmString = "fmovqlg $\x02, $\x03, $\x01"; 4967 break; 4968 } 4969 if (MCInst_getNumOperands(MI) == 4 && 4970 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4971 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4972 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4973 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4974 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4975 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4976 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4977 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { 4978 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) 4979 AsmString = "fmovqne $\x02, $\x03, $\x01"; 4980 break; 4981 } 4982 if (MCInst_getNumOperands(MI) == 4 && 4983 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4984 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4985 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4986 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 4987 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 4988 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 4989 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 4990 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { 4991 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) 4992 AsmString = "fmovqe $\x02, $\x03, $\x01"; 4993 break; 4994 } 4995 if (MCInst_getNumOperands(MI) == 4 && 4996 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 4997 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 4998 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 4999 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5000 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5001 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5002 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5003 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { 5004 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) 5005 AsmString = "fmovque $\x02, $\x03, $\x01"; 5006 break; 5007 } 5008 if (MCInst_getNumOperands(MI) == 4 && 5009 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5010 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 5011 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5012 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5013 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5014 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5015 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5016 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { 5017 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) 5018 AsmString = "fmovqge $\x02, $\x03, $\x01"; 5019 break; 5020 } 5021 if (MCInst_getNumOperands(MI) == 4 && 5022 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5023 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 5024 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5025 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5026 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5027 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5028 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5029 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { 5030 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) 5031 AsmString = "fmovquge $\x02, $\x03, $\x01"; 5032 break; 5033 } 5034 if (MCInst_getNumOperands(MI) == 4 && 5035 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5036 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 5037 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5038 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5039 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5040 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5041 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5042 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { 5043 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) 5044 AsmString = "fmovqle $\x02, $\x03, $\x01"; 5045 break; 5046 } 5047 if (MCInst_getNumOperands(MI) == 4 && 5048 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5049 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 5050 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5051 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5052 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5053 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5054 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5055 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { 5056 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) 5057 AsmString = "fmovqule $\x02, $\x03, $\x01"; 5058 break; 5059 } 5060 if (MCInst_getNumOperands(MI) == 4 && 5061 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5062 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && 5063 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5064 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5065 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5066 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && 5067 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5068 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 5069 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) 5070 AsmString = "fmovqo $\x02, $\x03, $\x01"; 5071 break; 5072 } 5073 return NULL; 5074 case SP_V9FMOVS_FCC: 5075 if (MCInst_getNumOperands(MI) == 4 && 5076 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5077 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5078 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5079 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5080 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5081 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5082 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5083 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 5084 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) 5085 AsmString = "fmovsa $\x02, $\x03, $\x01"; 5086 break; 5087 } 5088 if (MCInst_getNumOperands(MI) == 4 && 5089 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5090 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5091 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5092 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5093 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5094 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5095 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5096 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { 5097 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) 5098 AsmString = "fmovsn $\x02, $\x03, $\x01"; 5099 break; 5100 } 5101 if (MCInst_getNumOperands(MI) == 4 && 5102 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5103 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5104 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5105 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5106 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5107 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5108 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5109 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 5110 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) 5111 AsmString = "fmovsu $\x02, $\x03, $\x01"; 5112 break; 5113 } 5114 if (MCInst_getNumOperands(MI) == 4 && 5115 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5116 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5117 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5118 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5119 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5120 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5121 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5122 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { 5123 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) 5124 AsmString = "fmovsg $\x02, $\x03, $\x01"; 5125 break; 5126 } 5127 if (MCInst_getNumOperands(MI) == 4 && 5128 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5129 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5130 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5131 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5132 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5133 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5134 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5135 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { 5136 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) 5137 AsmString = "fmovsug $\x02, $\x03, $\x01"; 5138 break; 5139 } 5140 if (MCInst_getNumOperands(MI) == 4 && 5141 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5142 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5143 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5144 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5145 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5146 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5147 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5148 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { 5149 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) 5150 AsmString = "fmovsl $\x02, $\x03, $\x01"; 5151 break; 5152 } 5153 if (MCInst_getNumOperands(MI) == 4 && 5154 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5155 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5156 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5157 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5158 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5159 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5160 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5161 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { 5162 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) 5163 AsmString = "fmovsul $\x02, $\x03, $\x01"; 5164 break; 5165 } 5166 if (MCInst_getNumOperands(MI) == 4 && 5167 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5168 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5169 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5170 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5171 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5172 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5173 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5174 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { 5175 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) 5176 AsmString = "fmovslg $\x02, $\x03, $\x01"; 5177 break; 5178 } 5179 if (MCInst_getNumOperands(MI) == 4 && 5180 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5181 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5183 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5184 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5185 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5186 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5187 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { 5188 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) 5189 AsmString = "fmovsne $\x02, $\x03, $\x01"; 5190 break; 5191 } 5192 if (MCInst_getNumOperands(MI) == 4 && 5193 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5194 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5195 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5196 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5197 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5198 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5199 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5200 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { 5201 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) 5202 AsmString = "fmovse $\x02, $\x03, $\x01"; 5203 break; 5204 } 5205 if (MCInst_getNumOperands(MI) == 4 && 5206 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5207 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5208 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5209 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5210 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5211 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5212 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5213 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { 5214 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) 5215 AsmString = "fmovsue $\x02, $\x03, $\x01"; 5216 break; 5217 } 5218 if (MCInst_getNumOperands(MI) == 4 && 5219 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5220 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5221 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5222 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5223 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5224 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5225 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5226 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { 5227 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) 5228 AsmString = "fmovsge $\x02, $\x03, $\x01"; 5229 break; 5230 } 5231 if (MCInst_getNumOperands(MI) == 4 && 5232 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5233 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5234 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5235 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5236 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5237 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5238 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5239 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { 5240 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) 5241 AsmString = "fmovsuge $\x02, $\x03, $\x01"; 5242 break; 5243 } 5244 if (MCInst_getNumOperands(MI) == 4 && 5245 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5246 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5247 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5248 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5249 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5250 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5251 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5252 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { 5253 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) 5254 AsmString = "fmovsle $\x02, $\x03, $\x01"; 5255 break; 5256 } 5257 if (MCInst_getNumOperands(MI) == 4 && 5258 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5259 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5260 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5261 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5262 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5263 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5264 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5265 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { 5266 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) 5267 AsmString = "fmovsule $\x02, $\x03, $\x01"; 5268 break; 5269 } 5270 if (MCInst_getNumOperands(MI) == 4 && 5271 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5272 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && 5273 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5274 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5275 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5276 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && 5277 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5278 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 5279 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) 5280 AsmString = "fmovso $\x02, $\x03, $\x01"; 5281 break; 5282 } 5283 return NULL; 5284 case SP_V9MOVFCCri: 5285 if (MCInst_getNumOperands(MI) == 4 && 5286 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5287 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5288 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5289 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5290 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5291 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 5292 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) 5293 AsmString = "mova $\x02, $\x03, $\x01"; 5294 break; 5295 } 5296 if (MCInst_getNumOperands(MI) == 4 && 5297 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5298 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5299 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5300 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5301 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5302 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { 5303 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) 5304 AsmString = "movn $\x02, $\x03, $\x01"; 5305 break; 5306 } 5307 if (MCInst_getNumOperands(MI) == 4 && 5308 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5309 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5310 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5311 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5312 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5313 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 5314 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) 5315 AsmString = "movu $\x02, $\x03, $\x01"; 5316 break; 5317 } 5318 if (MCInst_getNumOperands(MI) == 4 && 5319 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5320 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5321 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5322 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5323 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5324 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { 5325 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) 5326 AsmString = "movg $\x02, $\x03, $\x01"; 5327 break; 5328 } 5329 if (MCInst_getNumOperands(MI) == 4 && 5330 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5331 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5332 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5333 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5334 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5335 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { 5336 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) 5337 AsmString = "movug $\x02, $\x03, $\x01"; 5338 break; 5339 } 5340 if (MCInst_getNumOperands(MI) == 4 && 5341 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5342 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5343 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5344 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5345 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5346 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { 5347 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) 5348 AsmString = "movl $\x02, $\x03, $\x01"; 5349 break; 5350 } 5351 if (MCInst_getNumOperands(MI) == 4 && 5352 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5353 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5354 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5355 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5356 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5357 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { 5358 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) 5359 AsmString = "movul $\x02, $\x03, $\x01"; 5360 break; 5361 } 5362 if (MCInst_getNumOperands(MI) == 4 && 5363 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5364 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5365 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5366 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5367 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5368 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { 5369 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) 5370 AsmString = "movlg $\x02, $\x03, $\x01"; 5371 break; 5372 } 5373 if (MCInst_getNumOperands(MI) == 4 && 5374 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5375 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5376 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5377 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5378 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5379 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { 5380 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) 5381 AsmString = "movne $\x02, $\x03, $\x01"; 5382 break; 5383 } 5384 if (MCInst_getNumOperands(MI) == 4 && 5385 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5386 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5387 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5388 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5389 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5390 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { 5391 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) 5392 AsmString = "move $\x02, $\x03, $\x01"; 5393 break; 5394 } 5395 if (MCInst_getNumOperands(MI) == 4 && 5396 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5397 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5398 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5399 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5400 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5401 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { 5402 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) 5403 AsmString = "movue $\x02, $\x03, $\x01"; 5404 break; 5405 } 5406 if (MCInst_getNumOperands(MI) == 4 && 5407 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5408 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5409 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5410 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5411 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5412 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { 5413 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) 5414 AsmString = "movge $\x02, $\x03, $\x01"; 5415 break; 5416 } 5417 if (MCInst_getNumOperands(MI) == 4 && 5418 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5419 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5420 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5421 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5422 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5423 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { 5424 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) 5425 AsmString = "movuge $\x02, $\x03, $\x01"; 5426 break; 5427 } 5428 if (MCInst_getNumOperands(MI) == 4 && 5429 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5430 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5431 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5432 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5433 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5434 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { 5435 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) 5436 AsmString = "movle $\x02, $\x03, $\x01"; 5437 break; 5438 } 5439 if (MCInst_getNumOperands(MI) == 4 && 5440 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5441 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5442 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5443 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5444 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5445 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { 5446 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) 5447 AsmString = "movule $\x02, $\x03, $\x01"; 5448 break; 5449 } 5450 if (MCInst_getNumOperands(MI) == 4 && 5451 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5452 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5453 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5454 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5455 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5456 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 5457 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) 5458 AsmString = "movo $\x02, $\x03, $\x01"; 5459 break; 5460 } 5461 return NULL; 5462 case SP_V9MOVFCCrr: 5463 if (MCInst_getNumOperands(MI) == 4 && 5464 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5465 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5466 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5467 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5468 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5469 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5470 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5471 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 5472 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) 5473 AsmString = "mova $\x02, $\x03, $\x01"; 5474 break; 5475 } 5476 if (MCInst_getNumOperands(MI) == 4 && 5477 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5478 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5479 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5480 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5481 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5482 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5483 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5484 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { 5485 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) 5486 AsmString = "movn $\x02, $\x03, $\x01"; 5487 break; 5488 } 5489 if (MCInst_getNumOperands(MI) == 4 && 5490 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5491 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5492 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5493 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5494 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5495 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5496 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5497 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 5498 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) 5499 AsmString = "movu $\x02, $\x03, $\x01"; 5500 break; 5501 } 5502 if (MCInst_getNumOperands(MI) == 4 && 5503 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5504 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5505 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5506 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5507 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5508 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5509 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5510 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { 5511 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) 5512 AsmString = "movg $\x02, $\x03, $\x01"; 5513 break; 5514 } 5515 if (MCInst_getNumOperands(MI) == 4 && 5516 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5517 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5518 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5519 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5520 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5521 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5522 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5523 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { 5524 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) 5525 AsmString = "movug $\x02, $\x03, $\x01"; 5526 break; 5527 } 5528 if (MCInst_getNumOperands(MI) == 4 && 5529 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5530 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5531 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5532 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5533 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5534 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5535 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5536 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { 5537 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) 5538 AsmString = "movl $\x02, $\x03, $\x01"; 5539 break; 5540 } 5541 if (MCInst_getNumOperands(MI) == 4 && 5542 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5543 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5544 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5545 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5546 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5547 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5548 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5549 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { 5550 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) 5551 AsmString = "movul $\x02, $\x03, $\x01"; 5552 break; 5553 } 5554 if (MCInst_getNumOperands(MI) == 4 && 5555 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5556 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5557 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5558 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5559 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5560 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5561 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5562 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { 5563 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) 5564 AsmString = "movlg $\x02, $\x03, $\x01"; 5565 break; 5566 } 5567 if (MCInst_getNumOperands(MI) == 4 && 5568 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5569 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5570 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5571 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5572 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5573 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5574 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5575 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { 5576 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) 5577 AsmString = "movne $\x02, $\x03, $\x01"; 5578 break; 5579 } 5580 if (MCInst_getNumOperands(MI) == 4 && 5581 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5582 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5583 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5584 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5585 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5586 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5587 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5588 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { 5589 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) 5590 AsmString = "move $\x02, $\x03, $\x01"; 5591 break; 5592 } 5593 if (MCInst_getNumOperands(MI) == 4 && 5594 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5595 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5596 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5597 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5598 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5599 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5600 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5601 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { 5602 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) 5603 AsmString = "movue $\x02, $\x03, $\x01"; 5604 break; 5605 } 5606 if (MCInst_getNumOperands(MI) == 4 && 5607 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5608 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5609 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5610 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5611 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5612 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5613 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5614 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { 5615 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) 5616 AsmString = "movge $\x02, $\x03, $\x01"; 5617 break; 5618 } 5619 if (MCInst_getNumOperands(MI) == 4 && 5620 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5621 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5622 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5623 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5624 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5625 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5626 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5627 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { 5628 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) 5629 AsmString = "movuge $\x02, $\x03, $\x01"; 5630 break; 5631 } 5632 if (MCInst_getNumOperands(MI) == 4 && 5633 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5634 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5635 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5636 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5637 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5638 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5639 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5640 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { 5641 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) 5642 AsmString = "movle $\x02, $\x03, $\x01"; 5643 break; 5644 } 5645 if (MCInst_getNumOperands(MI) == 4 && 5646 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5647 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5648 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5649 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5650 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5651 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5652 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5653 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { 5654 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) 5655 AsmString = "movule $\x02, $\x03, $\x01"; 5656 break; 5657 } 5658 if (MCInst_getNumOperands(MI) == 4 && 5659 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 5660 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && 5661 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 5662 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && 5663 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 5664 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && 5665 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 5666 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 5667 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) 5668 AsmString = "movo $\x02, $\x03, $\x01"; 5669 break; 5670 } 5671 return NULL; 5672 } 5673 5674 tmp = cs_strdup(AsmString); 5675 AsmMnem = tmp; 5676 for(AsmOps = tmp; *AsmOps; AsmOps++) { 5677 if (*AsmOps == ' ' || *AsmOps == '\t') { 5678 *AsmOps = '\0'; 5679 AsmOps++; 5680 break; 5681 } 5682 } 5683 SStream_concat0(OS, AsmMnem); 5684 if (*AsmOps) { 5685 SStream_concat0(OS, "\t"); 5686 if (strstr(AsmOps, "icc")) 5687 Sparc_addReg(MI, SPARC_REG_ICC); 5688 if (strstr(AsmOps, "xcc")) 5689 Sparc_addReg(MI, SPARC_REG_XCC); 5690 for (c = AsmOps; *c; c++) { 5691 if (*c == '$') { 5692 c += 1; 5693 if (*c == (char)0xff) { 5694 c += 1; 5695 OpIdx = *c - 1; 5696 c += 1; 5697 PrintMethodIdx = *c - 1; 5698 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); 5699 } else 5700 printOperand(MI, *c - 1, OS); 5701 } else { 5702 SStream_concat(OS, "%c", *c); 5703 } 5704 } 5705 } 5706 return tmp; 5707} 5708 5709#endif // PRINT_ALIAS_INSTR 5710