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1 /*
2  * Copyright (c) 2017-2018 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in all
14  * copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 #pragma once
25 
26 #ifdef __arm__
27 
28 #include <arm_neon.h>
29 
30 #include "../asmlib.hpp"
31 
32 template<>
interleave_block(float * & outptr,const float * const * in,size_t width,size_t height,size_t row_offset,bool)33 void interleave_block<6, 1, VLType::None, false>(
34     float * &outptr, const float * const * in, size_t width, size_t height,
35     size_t row_offset, bool
36 )
37 {
38     const float *inptr0 = in[0] + row_offset;
39     const float *inptr1 = in[1] + row_offset;
40     const float *inptr2 = in[2] + row_offset;
41     const float *inptr3 = in[3] + row_offset;
42     const float *inptr4 = in[4] + row_offset;
43     const float *inptr5 = in[5] + row_offset;
44 
45     // Cope with ragged cases by aliasing the first row (which is always valid).
46     // The nonsense output produced will be suppressed later anyway.
47     switch (height) {
48         case 1:
49             inptr1 = inptr0;
50             // fall through
51         case 2:
52             inptr2 = inptr0;
53             // fall through
54         case 3:
55             inptr3 = inptr0;
56             // fall through
57         case 4:
58             inptr4 = inptr0;
59             // fall through
60         case 5:
61             inptr5 = inptr0;
62             // fall through
63         default:
64         case 6:
65             break;
66     }
67 
68     //prefetch_2x(inptr0);
69     //prefetch_2x(inptr1);
70     //prefetch_2x(inptr2);
71     //prefetch_2x(inptr3);
72     //prefetch_2x(inptr4);
73     //prefetch_2x(inptr5);
74 
75     for (;width>7;width-=8) {
76         __asm __volatile (
77             // Load up 8 elements (2 vectors) from each of 8 sources.
78             "VLD1.32	{d0-d3}, [%[inptr0]]!\n"   // q0=A0A1A2A3
79             "VLD1.32	{d4-d7}, [%[inptr1]]!\n"   // q2=B0B1B2B3
80             "VLD1.32	{d8-d11}, [%[inptr2]]!\n"  // q4=C0C1C2C3
81             "VZIP.32	q0, q4\n"     // q0=A0C0A1C1, q4 = A2C2A3C3
82             "VLD1.32	{d12-d15}, [%[inptr3]]!\n" // q6=D0D1D2D3
83             "VZIP.32	q2, q6\n"     // q2=B0D0B1D1, q6 = B2D2B3D3
84             "VLD1.32	{d16-d19}, [%[inptr4]]!\n"
85             "VLD1.32	{d20-d23}, [%[inptr5]]!\n"
86             "VZIP.32	q8, q10\n"    // q8=E0F0E1F1, q10 = E2F2E3F3
87             ASM_PREFETCH("[%[inptr0], #128]")
88             "VZIP.32	q0, q2\n"    // q0 = A0B0C0D0, q2 = A1B1C1D1
89 
90             // Store first elements
91             "VST1.32	{d0-d1}, [%[outptr]]!\n"
92             "VST1.32	{d16}, [%[outptr]]!\n"
93 
94             "VZIP.32	q4, q6\n"    // q4 = A2B2C2D2, q6 = A3B3C3D3
95 
96             // Store second elements
97             "VST1.32	{d4-d5}, [%[outptr]]!\n"
98             "VZIP.32	q1, q5\n"
99             ASM_PREFETCH("[%[inptr1], #128]")
100             "VST1.32	{d17}, [%[outptr]]!\n"
101             "VZIP.32	q3, q7\n"
102 
103             // Store third elements
104             "VZIP.32	q9, q11\n"
105             "VST1.32	{d8-d9}, [%[outptr]]!\n"
106             "VZIP.32	q1, q3\n"
107             ASM_PREFETCH("[%[inptr2], #128]")
108             "VST1.32	{d20}, [%[outptr]]!\n"
109 
110             // Store fourth elements
111             "VZIP.32	q5, q7\n"
112             "VST1.32	{d12-d13}, [%[outptr]]!\n"
113             ASM_PREFETCH("[%[inptr3], #128]")
114             "VST1.32	{d21}, [%[outptr]]!\n"
115 
116             // Fifth
117             "VST1.32	{d2-d3}, [%[outptr]]!\n"
118             ASM_PREFETCH("[%[inptr4], #128]")
119             "VST1.32	{d18}, [%[outptr]]!\n"
120 
121             // Sixth
122             "VST1.32	{d6-d7}, [%[outptr]]!\n"
123             ASM_PREFETCH("[%[inptr5], #128]")
124             "VST1.32	{d19}, [%[outptr]]!\n"
125 
126             // Seventh
127             "VST1.32	{d10-d11}, [%[outptr]]!\n"
128             "VST1.32	{d22}, [%[outptr]]!\n"
129 
130             // Eighth
131             "VST1.32	{d14-d15}, [%[outptr]]!\n"
132             "VST1.32	{d23}, [%[outptr]]!\n"
133 
134             : [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3),
135               [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [outptr] "+r" (outptr)
136             :
137             : "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11", "q12", "memory"
138         );
139     }
140 
141     for (;width>0;width--) {
142         *outptr++ = *inptr0++;
143         *outptr++ = *inptr1++;
144         *outptr++ = *inptr2++;
145         *outptr++ = *inptr3++;
146         *outptr++ = *inptr4++;
147         *outptr++ = *inptr5++;
148     }
149 }
150 
151 #endif  // __arm__
152