1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Assembly Writer Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 11 12/// printInstruction - This method is automatically generated by tablegen 13/// from the instruction set description. 14static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 15{ 16 static const uint32_t OpInfo[] = { 17 0U, // PHI 18 0U, // INLINEASM 19 0U, // CFI_INSTRUCTION 20 0U, // EH_LABEL 21 0U, // GC_LABEL 22 0U, // KILL 23 0U, // EXTRACT_SUBREG 24 0U, // INSERT_SUBREG 25 0U, // IMPLICIT_DEF 26 0U, // SUBREG_TO_REG 27 0U, // COPY_TO_REGCLASS 28 2694U, // DBG_VALUE 29 0U, // REG_SEQUENCE 30 0U, // COPY 31 2687U, // BUNDLE 32 2704U, // LIFETIME_START 33 2674U, // LIFETIME_END 34 0U, // STACKMAP 35 0U, // PATCHPOINT 36 0U, // LOAD_STACK_GUARD 37 0U, // STATEPOINT 38 0U, // FRAME_ALLOC 39 6182U, // ABSv16i8 40 553920550U, // ABSv1i64 41 1074272294U, // ABSv2i32 42 1611405350U, // ABSv2i64 43 2148538406U, // ABSv4i16 44 2685671462U, // ABSv4i32 45 3222804518U, // ABSv8i16 46 3759937574U, // ABSv8i8 47 17049662U, // ADCSWr 48 17049662U, // ADCSXr 49 17048298U, // ADCWr 50 17048298U, // ADCXr 51 537400863U, // ADDHNv2i64_v2i32 52 571748634U, // ADDHNv2i64_v4i32 53 1074796063U, // ADDHNv4i32_v4i16 54 1108881690U, // ADDHNv4i32_v8i16 55 1644179738U, // ADDHNv8i16_v16i8 56 1612453407U, // ADDHNv8i16_v8i8 57 2147489464U, // ADDPv16i8 58 2684884664U, // ADDPv2i32 59 537663160U, // ADDPv2i64 60 1610884792U, // ADDPv2i64p 61 3222279864U, // ADDPv4i16 62 1075058360U, // ADDPv4i32 63 1612191416U, // ADDPv8i16 64 3759937208U, // ADDPv8i8 65 17049674U, // ADDSWri 66 0U, // ADDSWrr 67 17049674U, // ADDSWrs 68 17049674U, // ADDSWrx 69 17049674U, // ADDSXri 70 0U, // ADDSXrr 71 17049674U, // ADDSXrs 72 17049674U, // ADDSXrx 73 17049674U, // ADDSXrx64 74 272671U, // ADDVv16i8v 75 2147756319U, // ADDVv4i16v 76 2684627231U, // ADDVv4i32v 77 3221498143U, // ADDVv8i16v 78 3758369055U, // ADDVv8i8v 79 17048359U, // ADDWri 80 0U, // ADDWrr 81 17048359U, // ADDWrs 82 17048359U, // ADDWrx 83 17048359U, // ADDXri 84 0U, // ADDXrr 85 17048359U, // ADDXrs 86 17048359U, // ADDXrx 87 17048359U, // ADDXrx64 88 2147488551U, // ADDv16i8 89 17048359U, // ADDv1i64 90 2684883751U, // ADDv2i32 91 537662247U, // ADDv2i64 92 3222278951U, // ADDv4i16 93 1075057447U, // ADDv4i32 94 1612190503U, // ADDv8i16 95 3759936295U, // ADDv8i8 96 0U, // ADJCALLSTACKDOWN 97 0U, // ADJCALLSTACKUP 98 553920403U, // ADR 99 50603811U, // ADRP 100 33567598U, // AESDrr 101 33567656U, // AESErr 102 4852U, // AESIMCrr 103 4860U, // AESMCrr 104 17049680U, // ANDSWri 105 0U, // ANDSWrr 106 17049680U, // ANDSWrs 107 17049680U, // ANDSXri 108 0U, // ANDSXrr 109 17049680U, // ANDSXrs 110 17048425U, // ANDWri 111 0U, // ANDWrr 112 17048425U, // ANDWrs 113 17048425U, // ANDXri 114 0U, // ANDXrr 115 17048425U, // ANDXrs 116 2147488617U, // ANDv16i8 117 3759936361U, // ANDv8i8 118 17049553U, // ASRVWr 119 17049553U, // ASRVXr 120 16935U, // B 121 67380710U, // BFMWri 122 67380710U, // BFMXri 123 0U, // BICSWrr 124 17049668U, // BICSWrs 125 0U, // BICSXrr 126 17049668U, // BICSXrs 127 0U, // BICWrr 128 17048303U, // BICWrs 129 0U, // BICXrr 130 17048303U, // BICXrs 131 2147488495U, // BICv16i8 132 84423407U, // BICv2i32 133 84947695U, // BICv4i16 134 85209839U, // BICv4i32 135 85471983U, // BICv8i16 136 3759936239U, // BICv8i8 137 2147488704U, // BIFv16i8 138 3759936448U, // BIFv8i8 139 2181052603U, // BITv16i8 140 3793500347U, // BITv8i8 141 17641U, // BL 142 2107319U, // BLR 143 2107279U, // BR 144 21688U, // BRK 145 2181051810U, // BSLv16i8 146 3793499554U, // BSLv8i8 147 27247U, // Bcc 148 100936257U, // CBNZW 149 100936257U, // CBNZX 150 100936242U, // CBZW 151 100936242U, // CBZX 152 17049144U, // CCMNWi 153 17049144U, // CCMNWr 154 17049144U, // CCMNXi 155 17049144U, // CCMNXr 156 17049316U, // CCMPWi 157 17049316U, // CCMPWr 158 17049316U, // CCMPXi 159 17049316U, // CCMPXr 160 2107924U, // CLREX 161 553920604U, // CLSWr 162 553920604U, // CLSXr 163 6236U, // CLSv16i8 164 1074272348U, // CLSv2i32 165 2148538460U, // CLSv4i16 166 2685671516U, // CLSv4i32 167 3222804572U, // CLSv8i16 168 3759937628U, // CLSv8i8 169 553921084U, // CLZWr 170 553921084U, // CLZXr 171 6716U, // CLZv16i8 172 1074272828U, // CLZv2i32 173 2148538940U, // CLZv4i16 174 2685671996U, // CLZv4i32 175 3222805052U, // CLZv8i16 176 3759938108U, // CLZv8i8 177 2147489643U, // CMEQv16i8 178 5995U, // CMEQv16i8rz 179 17049451U, // CMEQv1i64 180 553920363U, // CMEQv1i64rz 181 2684884843U, // CMEQv2i32 182 1074272107U, // CMEQv2i32rz 183 537663339U, // CMEQv2i64 184 1611405163U, // CMEQv2i64rz 185 3222280043U, // CMEQv4i16 186 2148538219U, // CMEQv4i16rz 187 1075058539U, // CMEQv4i32 188 2685671275U, // CMEQv4i32rz 189 1612191595U, // CMEQv8i16 190 3222804331U, // CMEQv8i16rz 191 3759937387U, // CMEQv8i8 192 3759937387U, // CMEQv8i8rz 193 2147488636U, // CMGEv16i8 194 4988U, // CMGEv16i8rz 195 17048444U, // CMGEv1i64 196 553919356U, // CMGEv1i64rz 197 2684883836U, // CMGEv2i32 198 1074271100U, // CMGEv2i32rz 199 537662332U, // CMGEv2i64 200 1611404156U, // CMGEv2i64rz 201 3222279036U, // CMGEv4i16 202 2148537212U, // CMGEv4i16rz 203 1075057532U, // CMGEv4i32 204 2685670268U, // CMGEv4i32rz 205 1612190588U, // CMGEv8i16 206 3222803324U, // CMGEv8i16rz 207 3759936380U, // CMGEv8i8 208 3759936380U, // CMGEv8i8rz 209 2147489972U, // CMGTv16i8 210 6324U, // CMGTv16i8rz 211 17049780U, // CMGTv1i64 212 553920692U, // CMGTv1i64rz 213 2684885172U, // CMGTv2i32 214 1074272436U, // CMGTv2i32rz 215 537663668U, // CMGTv2i64 216 1611405492U, // CMGTv2i64rz 217 3222280372U, // CMGTv4i16 218 2148538548U, // CMGTv4i16rz 219 1075058868U, // CMGTv4i32 220 2685671604U, // CMGTv4i32rz 221 1612191924U, // CMGTv8i16 222 3222804660U, // CMGTv8i16rz 223 3759937716U, // CMGTv8i8 224 3759937716U, // CMGTv8i8rz 225 2147488916U, // CMHIv16i8 226 17048724U, // CMHIv1i64 227 2684884116U, // CMHIv2i32 228 537662612U, // CMHIv2i64 229 3222279316U, // CMHIv4i16 230 1075057812U, // CMHIv4i32 231 1612190868U, // CMHIv8i16 232 3759936660U, // CMHIv8i8 233 2147489878U, // CMHSv16i8 234 17049686U, // CMHSv1i64 235 2684885078U, // CMHSv2i32 236 537663574U, // CMHSv2i64 237 3222280278U, // CMHSv4i16 238 1075058774U, // CMHSv4i32 239 1612191830U, // CMHSv8i16 240 3759937622U, // CMHSv8i8 241 4995U, // CMLEv16i8rz 242 553919363U, // CMLEv1i64rz 243 1074271107U, // CMLEv2i32rz 244 1611404163U, // CMLEv2i64rz 245 2148537219U, // CMLEv4i16rz 246 2685670275U, // CMLEv4i32rz 247 3222803331U, // CMLEv8i16rz 248 3759936387U, // CMLEv8i8rz 249 6342U, // CMLTv16i8rz 250 553920710U, // CMLTv1i64rz 251 1074272454U, // CMLTv2i32rz 252 1611405510U, // CMLTv2i64rz 253 2148538566U, // CMLTv4i16rz 254 2685671622U, // CMLTv4i32rz 255 3222804678U, // CMLTv8i16rz 256 3759937734U, // CMLTv8i8rz 257 2147490013U, // CMTSTv16i8 258 17049821U, // CMTSTv1i64 259 2684885213U, // CMTSTv2i32 260 537663709U, // CMTSTv2i64 261 3222280413U, // CMTSTv4i16 262 1075058909U, // CMTSTv4i32 263 1612191965U, // CMTSTv8i16 264 3759937757U, // CMTSTv8i8 265 6348U, // CNTv16i8 266 3759937740U, // CNTv8i8 267 272763U, // CPYi16 268 537143675U, // CPYi32 269 1074014587U, // CPYi64 270 1610885499U, // CPYi8 271 17048098U, // CRC32Brr 272 17048106U, // CRC32CBrr 273 17048575U, // CRC32CHrr 274 17050039U, // CRC32CWrr 275 17050123U, // CRC32CXrr 276 17048558U, // CRC32Hrr 277 17050017U, // CRC32Wrr 278 17050092U, // CRC32Xrr 279 17048888U, // CSELWr 280 17048888U, // CSELXr 281 17048323U, // CSINCWr 282 17048323U, // CSINCXr 283 17049971U, // CSINVWr 284 17049971U, // CSINVXr 285 17048544U, // CSNEGWr 286 17048544U, // CSNEGXr 287 20524U, // DCPS1 288 20889U, // DCPS2 289 20938U, // DCPS3 290 29235U, // DMB 291 2719U, // DRPS 292 29324U, // DSB 293 553654070U, // DUPv16i8gpr 294 1610618678U, // DUPv16i8lane 295 554178358U, // DUPv2i32gpr 296 537401142U, // DUPv2i32lane 297 554440502U, // DUPv2i64gpr 298 1074534198U, // DUPv2i64lane 299 554702646U, // DUPv4i16gpr 300 1054518U, // DUPv4i16lane 301 554964790U, // DUPv4i32gpr 302 538187574U, // DUPv4i32lane 303 555226934U, // DUPv8i16gpr 304 1578806U, // DUPv8i16lane 305 555489078U, // DUPv8i8gpr 306 1612453686U, // DUPv8i8lane 307 0U, // EONWrr 308 17049150U, // EONWrs 309 0U, // EONXrr 310 17049150U, // EONXrs 311 17049538U, // EORWri 312 0U, // EORWrr 313 17049538U, // EORWrs 314 17049538U, // EORXri 315 0U, // EORXrr 316 17049538U, // EORXrs 317 2147489730U, // EORv16i8 318 3759937474U, // EORv8i8 319 2724U, // ERET 320 17049585U, // EXTRWrri 321 17049585U, // EXTRXrri 322 2147490026U, // EXTv16i8 323 3759937770U, // EXTv8i8 324 0U, // F128CSEL 325 17048340U, // FABD32 326 17048340U, // FABD64 327 2684883732U, // FABDv2f32 328 537662228U, // FABDv2f64 329 1075057428U, // FABDv4f32 330 553920549U, // FABSDr 331 553920549U, // FABSSr 332 1074272293U, // FABSv2f32 333 1611405349U, // FABSv2f64 334 2685671461U, // FABSv4f32 335 17048436U, // FACGE32 336 17048436U, // FACGE64 337 2684883828U, // FACGEv2f32 338 537662324U, // FACGEv2f64 339 1075057524U, // FACGEv4f32 340 17049772U, // FACGT32 341 17049772U, // FACGT64 342 2684885164U, // FACGTv2f32 343 537663660U, // FACGTv2f64 344 1075058860U, // FACGTv4f32 345 17048358U, // FADDDrr 346 2684884663U, // FADDPv2f32 347 537663159U, // FADDPv2f64 348 1074013879U, // FADDPv2i32p 349 1610884791U, // FADDPv2i64p 350 1075058359U, // FADDPv4f32 351 17048358U, // FADDSrr 352 2684883750U, // FADDv2f32 353 537662246U, // FADDv2f64 354 1075057446U, // FADDv4f32 355 17049315U, // FCCMPDrr 356 17048473U, // FCCMPEDrr 357 17048473U, // FCCMPESrr 358 17049315U, // FCCMPSrr 359 17049450U, // FCMEQ32 360 17049450U, // FCMEQ64 361 2164533098U, // FCMEQv1i32rz 362 2164533098U, // FCMEQv1i64rz 363 2684884842U, // FCMEQv2f32 364 537663338U, // FCMEQv2f64 365 2684884842U, // FCMEQv2i32rz 366 3222017898U, // FCMEQv2i64rz 367 1075058538U, // FCMEQv4f32 368 3759413098U, // FCMEQv4i32rz 369 17048443U, // FCMGE32 370 17048443U, // FCMGE64 371 2164532091U, // FCMGEv1i32rz 372 2164532091U, // FCMGEv1i64rz 373 2684883835U, // FCMGEv2f32 374 537662331U, // FCMGEv2f64 375 2684883835U, // FCMGEv2i32rz 376 3222016891U, // FCMGEv2i64rz 377 1075057531U, // FCMGEv4f32 378 3759412091U, // FCMGEv4i32rz 379 17049779U, // FCMGT32 380 17049779U, // FCMGT64 381 2164533427U, // FCMGTv1i32rz 382 2164533427U, // FCMGTv1i64rz 383 2684885171U, // FCMGTv2f32 384 537663667U, // FCMGTv2f64 385 2684885171U, // FCMGTv2i32rz 386 3222018227U, // FCMGTv2i64rz 387 1075058867U, // FCMGTv4f32 388 3759413427U, // FCMGTv4i32rz 389 2164532098U, // FCMLEv1i32rz 390 2164532098U, // FCMLEv1i64rz 391 2684883842U, // FCMLEv2i32rz 392 3222016898U, // FCMLEv2i64rz 393 3759412098U, // FCMLEv4i32rz 394 2164533445U, // FCMLTv1i32rz 395 2164533445U, // FCMLTv1i64rz 396 2684885189U, // FCMLTv2i32rz 397 3222018245U, // FCMLTv2i64rz 398 3759413445U, // FCMLTv4i32rz 399 2369258U, // FCMPDri 400 553920234U, // FCMPDrr 401 2368417U, // FCMPEDri 402 553919393U, // FCMPEDrr 403 2368417U, // FCMPESri 404 553919393U, // FCMPESrr 405 2369258U, // FCMPSri 406 553920234U, // FCMPSrr 407 17048887U, // FCSELDrrr 408 17048887U, // FCSELSrrr 409 553920541U, // FCVTASUWDr 410 553920541U, // FCVTASUWSr 411 553920541U, // FCVTASUXDr 412 553920541U, // FCVTASUXSr 413 553920541U, // FCVTASv1i32 414 553920541U, // FCVTASv1i64 415 1074272285U, // FCVTASv2f32 416 1611405341U, // FCVTASv2f64 417 2685671453U, // FCVTASv4f32 418 553920751U, // FCVTAUUWDr 419 553920751U, // FCVTAUUWSr 420 553920751U, // FCVTAUUXDr 421 553920751U, // FCVTAUUXSr 422 553920751U, // FCVTAUv1i32 423 553920751U, // FCVTAUv1i64 424 1074272495U, // FCVTAUv2f32 425 1611405551U, // FCVTAUv2f64 426 2685671663U, // FCVTAUv4f32 427 553920740U, // FCVTDHr 428 553920740U, // FCVTDSr 429 553920740U, // FCVTHDr 430 553920740U, // FCVTHSr 431 1074533828U, // FCVTLv2i32 432 2148799940U, // FCVTLv4i16 433 2685145352U, // FCVTLv4i32 434 3222540552U, // FCVTLv8i16 435 553920615U, // FCVTMSUWDr 436 553920615U, // FCVTMSUWSr 437 553920615U, // FCVTMSUXDr 438 553920615U, // FCVTMSUXSr 439 553920615U, // FCVTMSv1i32 440 553920615U, // FCVTMSv1i64 441 1074272359U, // FCVTMSv2f32 442 1611405415U, // FCVTMSv2f64 443 2685671527U, // FCVTMSv4f32 444 553920767U, // FCVTMUUWDr 445 553920767U, // FCVTMUUWSr 446 553920767U, // FCVTMUUXDr 447 553920767U, // FCVTMUUXSr 448 553920767U, // FCVTMUv1i32 449 553920767U, // FCVTMUv1i64 450 1074272511U, // FCVTMUv2f32 451 1611405567U, // FCVTMUv2f64 452 2685671679U, // FCVTMUv4f32 453 553920628U, // FCVTNSUWDr 454 553920628U, // FCVTNSUWSr 455 553920628U, // FCVTNSUXDr 456 553920628U, // FCVTNSUXSr 457 553920628U, // FCVTNSv1i32 458 553920628U, // FCVTNSv1i64 459 1074272372U, // FCVTNSv2f32 460 1611405428U, // FCVTNSv2f64 461 2685671540U, // FCVTNSv4f32 462 553920775U, // FCVTNUUWDr 463 553920775U, // FCVTNUUWSr 464 553920775U, // FCVTNUUXDr 465 553920775U, // FCVTNUUXSr 466 553920775U, // FCVTNUv1i32 467 553920775U, // FCVTNUv1i64 468 1074272519U, // FCVTNUv2f32 469 1611405575U, // FCVTNUv2f64 470 2685671687U, // FCVTNUv4f32 471 1611142770U, // FCVTNv2i32 472 2685408882U, // FCVTNv4i16 473 1645490510U, // FCVTNv4i32 474 2719494478U, // FCVTNv8i16 475 553920644U, // FCVTPSUWDr 476 553920644U, // FCVTPSUWSr 477 553920644U, // FCVTPSUXDr 478 553920644U, // FCVTPSUXSr 479 553920644U, // FCVTPSv1i32 480 553920644U, // FCVTPSv1i64 481 1074272388U, // FCVTPSv2f32 482 1611405444U, // FCVTPSv2f64 483 2685671556U, // FCVTPSv4f32 484 553920783U, // FCVTPUUWDr 485 553920783U, // FCVTPUUWSr 486 553920783U, // FCVTPUUXDr 487 553920783U, // FCVTPUUXSr 488 553920783U, // FCVTPUv1i32 489 553920783U, // FCVTPUv1i64 490 1074272527U, // FCVTPUv2f32 491 1611405583U, // FCVTPUv2f64 492 2685671695U, // FCVTPUv4f32 493 553920740U, // FCVTSDr 494 553920740U, // FCVTSHr 495 553920168U, // FCVTXNv1i64 496 1611142824U, // FCVTXNv2f32 497 1645490564U, // FCVTXNv4f32 498 17049759U, // FCVTZSSWDri 499 17049759U, // FCVTZSSWSri 500 17049759U, // FCVTZSSXDri 501 17049759U, // FCVTZSSXSri 502 553920671U, // FCVTZSUWDr 503 553920671U, // FCVTZSUWSr 504 553920671U, // FCVTZSUXDr 505 553920671U, // FCVTZSUXSr 506 17049759U, // FCVTZS_IntSWDri 507 17049759U, // FCVTZS_IntSWSri 508 17049759U, // FCVTZS_IntSXDri 509 17049759U, // FCVTZS_IntSXSri 510 553920671U, // FCVTZS_IntUWDr 511 553920671U, // FCVTZS_IntUWSr 512 553920671U, // FCVTZS_IntUXDr 513 553920671U, // FCVTZS_IntUXSr 514 1074272415U, // FCVTZS_Intv2f32 515 1611405471U, // FCVTZS_Intv2f64 516 2685671583U, // FCVTZS_Intv4f32 517 17049759U, // FCVTZSd 518 17049759U, // FCVTZSs 519 553920671U, // FCVTZSv1i32 520 553920671U, // FCVTZSv1i64 521 1074272415U, // FCVTZSv2f32 522 1611405471U, // FCVTZSv2f64 523 2684885151U, // FCVTZSv2i32_shift 524 537663647U, // FCVTZSv2i64_shift 525 2685671583U, // FCVTZSv4f32 526 1075058847U, // FCVTZSv4i32_shift 527 17049879U, // FCVTZUSWDri 528 17049879U, // FCVTZUSWSri 529 17049879U, // FCVTZUSXDri 530 17049879U, // FCVTZUSXSri 531 553920791U, // FCVTZUUWDr 532 553920791U, // FCVTZUUWSr 533 553920791U, // FCVTZUUXDr 534 553920791U, // FCVTZUUXSr 535 17049879U, // FCVTZU_IntSWDri 536 17049879U, // FCVTZU_IntSWSri 537 17049879U, // FCVTZU_IntSXDri 538 17049879U, // FCVTZU_IntSXSri 539 553920791U, // FCVTZU_IntUWDr 540 553920791U, // FCVTZU_IntUWSr 541 553920791U, // FCVTZU_IntUXDr 542 553920791U, // FCVTZU_IntUXSr 543 1074272535U, // FCVTZU_Intv2f32 544 1611405591U, // FCVTZU_Intv2f64 545 2685671703U, // FCVTZU_Intv4f32 546 17049879U, // FCVTZUd 547 17049879U, // FCVTZUs 548 553920791U, // FCVTZUv1i32 549 553920791U, // FCVTZUv1i64 550 1074272535U, // FCVTZUv2f32 551 1611405591U, // FCVTZUv2f64 552 2684885271U, // FCVTZUv2i32_shift 553 537663767U, // FCVTZUv2i64_shift 554 2685671703U, // FCVTZUv4f32 555 1075058967U, // FCVTZUv4i32_shift 556 17049898U, // FDIVDrr 557 17049898U, // FDIVSrr 558 2684885290U, // FDIVv2f32 559 537663786U, // FDIVv2f64 560 1075058986U, // FDIVv4f32 561 17048394U, // FMADDDrrr 562 17048394U, // FMADDSrrr 563 17050100U, // FMAXDrr 564 17049087U, // FMAXNMDrr 565 2684884729U, // FMAXNMPv2f32 566 537663225U, // FMAXNMPv2f64 567 1074013945U, // FMAXNMPv2i32p 568 1610884857U, // FMAXNMPv2i64p 569 1075058425U, // FMAXNMPv4f32 570 17049087U, // FMAXNMSrr 571 2684627285U, // FMAXNMVv4i32v 572 2684884479U, // FMAXNMv2f32 573 537662975U, // FMAXNMv2f64 574 1075058175U, // FMAXNMv4f32 575 2684884802U, // FMAXPv2f32 576 537663298U, // FMAXPv2f64 577 1074014018U, // FMAXPv2i32p 578 1610884930U, // FMAXPv2i64p 579 1075058498U, // FMAXPv4f32 580 17050100U, // FMAXSrr 581 2684627340U, // FMAXVv4i32v 582 2684885492U, // FMAXv2f32 583 537663988U, // FMAXv2f64 584 1075059188U, // FMAXv4f32 585 17049126U, // FMINDrr 586 17049079U, // FMINNMDrr 587 2684884720U, // FMINNMPv2f32 588 537663216U, // FMINNMPv2f64 589 1074013936U, // FMINNMPv2i32p 590 1610884848U, // FMINNMPv2i64p 591 1075058416U, // FMINNMPv4f32 592 17049079U, // FMINNMSrr 593 2684627276U, // FMINNMVv4i32v 594 2684884471U, // FMINNMv2f32 595 537662967U, // FMINNMv2f64 596 1075058167U, // FMINNMv4f32 597 2684884744U, // FMINPv2f32 598 537663240U, // FMINPv2f64 599 1074013960U, // FMINPv2i32p 600 1610884872U, // FMINPv2i64p 601 1075058440U, // FMINPv4f32 602 17049126U, // FMINSrr 603 2684627294U, // FMINVv4i32v 604 2684884518U, // FMINv2f32 605 537663014U, // FMINv2f64 606 1075058214U, // FMINv4f32 607 67404282U, // FMLAv1i32_indexed 608 67404282U, // FMLAv1i64_indexed 609 2718446074U, // FMLAv2f32 610 571224570U, // FMLAv2f64 611 2718446074U, // FMLAv2i32_indexed 612 571224570U, // FMLAv2i64_indexed 613 1108619770U, // FMLAv4f32 614 1108619770U, // FMLAv4i32_indexed 615 67405921U, // FMLSv1i32_indexed 616 67405921U, // FMLSv1i64_indexed 617 2718447713U, // FMLSv2f32 618 571226209U, // FMLSv2f64 619 2718447713U, // FMLSv2i32_indexed 620 571226209U, // FMLSv2i64_indexed 621 1108621409U, // FMLSv4f32 622 1108621409U, // FMLSv4i32_indexed 623 1074014586U, // FMOVDXHighr 624 553920890U, // FMOVDXr 625 117713274U, // FMOVDi 626 553920890U, // FMOVDr 627 553920890U, // FMOVSWr 628 117713274U, // FMOVSi 629 553920890U, // FMOVSr 630 553920890U, // FMOVWSr 631 556276090U, // FMOVXDHighr 632 553920890U, // FMOVXDr 633 117971322U, // FMOVv2f32_ns 634 118233466U, // FMOVv2f64_ns 635 118757754U, // FMOVv4f32_ns 636 17048257U, // FMSUBDrrr 637 17048257U, // FMSUBSrrr 638 17049035U, // FMULDrr 639 17049035U, // FMULSrr 640 17050139U, // FMULX32 641 17050139U, // FMULX64 642 17050139U, // FMULXv1i32_indexed 643 17050139U, // FMULXv1i64_indexed 644 2684885531U, // FMULXv2f32 645 537664027U, // FMULXv2f64 646 2684885531U, // FMULXv2i32_indexed 647 537664027U, // FMULXv2i64_indexed 648 1075059227U, // FMULXv4f32 649 1075059227U, // FMULXv4i32_indexed 650 17049035U, // FMULv1i32_indexed 651 17049035U, // FMULv1i64_indexed 652 2684884427U, // FMULv2f32 653 537662923U, // FMULv2f64 654 2684884427U, // FMULv2i32_indexed 655 537662923U, // FMULv2i64_indexed 656 1075058123U, // FMULv4f32 657 1075058123U, // FMULv4i32_indexed 658 553919443U, // FNEGDr 659 553919443U, // FNEGSr 660 1074271187U, // FNEGv2f32 661 1611404243U, // FNEGv2f64 662 2685670355U, // FNEGv4f32 663 17048401U, // FNMADDDrrr 664 17048401U, // FNMADDSrrr 665 17048264U, // FNMSUBDrrr 666 17048264U, // FNMSUBSrrr 667 17049041U, // FNMULDrr 668 17049041U, // FNMULSrr 669 553919369U, // FRECPEv1i32 670 553919369U, // FRECPEv1i64 671 1074271113U, // FRECPEv2f32 672 1611404169U, // FRECPEv2f64 673 2685670281U, // FRECPEv4f32 674 17049724U, // FRECPS32 675 17049724U, // FRECPS64 676 2684885116U, // FRECPSv2f32 677 537663612U, // FRECPSv2f64 678 1075058812U, // FRECPSv4f32 679 553921058U, // FRECPXv1i32 680 553921058U, // FRECPXv1i64 681 553919002U, // FRINTADr 682 553919002U, // FRINTASr 683 1074270746U, // FRINTAv2f32 684 1611403802U, // FRINTAv2f64 685 2685669914U, // FRINTAv4f32 686 553919658U, // FRINTIDr 687 553919658U, // FRINTISr 688 1074271402U, // FRINTIv2f32 689 1611404458U, // FRINTIv2f64 690 2685670570U, // FRINTIv4f32 691 553920007U, // FRINTMDr 692 553920007U, // FRINTMSr 693 1074271751U, // FRINTMv2f32 694 1611404807U, // FRINTMv2f64 695 2685670919U, // FRINTMv4f32 696 553920106U, // FRINTNDr 697 553920106U, // FRINTNSr 698 1074271850U, // FRINTNv2f32 699 1611404906U, // FRINTNv2f64 700 2685671018U, // FRINTNv4f32 701 553920297U, // FRINTPDr 702 553920297U, // FRINTPSr 703 1074272041U, // FRINTPv2f32 704 1611405097U, // FRINTPv2f64 705 2685671209U, // FRINTPv4f32 706 553921066U, // FRINTXDr 707 553921066U, // FRINTXSr 708 1074272810U, // FRINTXv2f32 709 1611405866U, // FRINTXv2f64 710 2685671978U, // FRINTXv4f32 711 553921101U, // FRINTZDr 712 553921101U, // FRINTZSr 713 1074272845U, // FRINTZv2f32 714 1611405901U, // FRINTZv2f64 715 2685672013U, // FRINTZv4f32 716 553919406U, // FRSQRTEv1i32 717 553919406U, // FRSQRTEv1i64 718 1074271150U, // FRSQRTEv2f32 719 1611404206U, // FRSQRTEv2f64 720 2685670318U, // FRSQRTEv4f32 721 17049745U, // FRSQRTS32 722 17049745U, // FRSQRTS64 723 2684885137U, // FRSQRTSv2f32 724 537663633U, // FRSQRTSv2f64 725 1075058833U, // FRSQRTSv4f32 726 553920726U, // FSQRTDr 727 553920726U, // FSQRTSr 728 1074272470U, // FSQRTv2f32 729 1611405526U, // FSQRTv2f64 730 2685671638U, // FSQRTv4f32 731 17048237U, // FSUBDrr 732 17048237U, // FSUBSrr 733 2684883629U, // FSUBv2f32 734 537662125U, // FSUBv2f64 735 1075057325U, // FSUBv4f32 736 23145U, // HINT 737 22720U, // HLT 738 21258U, // HVC 739 137115759U, // INSvi16gpr 740 153892975U, // INSvi16lane 741 137377903U, // INSvi32gpr 742 691026031U, // INSvi32lane 743 136853615U, // INSvi64gpr 744 1227372655U, // INSvi64lane 745 137640047U, // INSvi8gpr 746 1765029999U, // INSvi8lane 747 29329U, // ISB 748 36885U, // LD1Fourv16b 749 3710997U, // LD1Fourv16b_POST 750 45077U, // LD1Fourv1d 751 3981333U, // LD1Fourv1d_POST 752 53269U, // LD1Fourv2d 753 3727381U, // LD1Fourv2d_POST 754 61461U, // LD1Fourv2s 755 3997717U, // LD1Fourv2s_POST 756 69653U, // LD1Fourv4h 757 4005909U, // LD1Fourv4h_POST 758 77845U, // LD1Fourv4s 759 3751957U, // LD1Fourv4s_POST 760 86037U, // LD1Fourv8b 761 4022293U, // LD1Fourv8b_POST 762 94229U, // LD1Fourv8h 763 3768341U, // LD1Fourv8h_POST 764 36885U, // LD1Onev16b 765 4235285U, // LD1Onev16b_POST 766 45077U, // LD1Onev1d 767 4505621U, // LD1Onev1d_POST 768 53269U, // LD1Onev2d 769 4251669U, // LD1Onev2d_POST 770 61461U, // LD1Onev2s 771 4522005U, // LD1Onev2s_POST 772 69653U, // LD1Onev4h 773 4530197U, // LD1Onev4h_POST 774 77845U, // LD1Onev4s 775 4276245U, // LD1Onev4s_POST 776 86037U, // LD1Onev8b 777 4546581U, // LD1Onev8b_POST 778 94229U, // LD1Onev8h 779 4292629U, // LD1Onev8h_POST 780 38769U, // LD1Rv16b 781 4761457U, // LD1Rv16b_POST 782 46961U, // LD1Rv1d 783 4507505U, // LD1Rv1d_POST 784 55153U, // LD1Rv2d 785 4515697U, // LD1Rv2d_POST 786 63345U, // LD1Rv2s 787 5048177U, // LD1Rv2s_POST 788 71537U, // LD1Rv4h 789 5318513U, // LD1Rv4h_POST 790 79729U, // LD1Rv4s 791 5064561U, // LD1Rv4s_POST 792 87921U, // LD1Rv8b 793 4810609U, // LD1Rv8b_POST 794 96113U, // LD1Rv8h 795 5343089U, // LD1Rv8h_POST 796 36885U, // LD1Threev16b 797 5546005U, // LD1Threev16b_POST 798 45077U, // LD1Threev1d 799 5816341U, // LD1Threev1d_POST 800 53269U, // LD1Threev2d 801 5562389U, // LD1Threev2d_POST 802 61461U, // LD1Threev2s 803 5832725U, // LD1Threev2s_POST 804 69653U, // LD1Threev4h 805 5840917U, // LD1Threev4h_POST 806 77845U, // LD1Threev4s 807 5586965U, // LD1Threev4s_POST 808 86037U, // LD1Threev8b 809 5857301U, // LD1Threev8b_POST 810 94229U, // LD1Threev8h 811 5603349U, // LD1Threev8h_POST 812 36885U, // LD1Twov16b 813 3973141U, // LD1Twov16b_POST 814 45077U, // LD1Twov1d 815 4243477U, // LD1Twov1d_POST 816 53269U, // LD1Twov2d 817 3989525U, // LD1Twov2d_POST 818 61461U, // LD1Twov2s 819 4259861U, // LD1Twov2s_POST 820 69653U, // LD1Twov4h 821 4268053U, // LD1Twov4h_POST 822 77845U, // LD1Twov4s 823 4014101U, // LD1Twov4s_POST 824 86037U, // LD1Twov8b 825 4284437U, // LD1Twov8b_POST 826 94229U, // LD1Twov8h 827 4030485U, // LD1Twov8h_POST 828 6131733U, // LD1i16 829 6397973U, // LD1i16_POST 830 6139925U, // LD1i32 831 6668309U, // LD1i32_POST 832 6148117U, // LD1i64 833 6938645U, // LD1i64_POST 834 6156309U, // LD1i8 835 7208981U, // LD1i8_POST 836 38775U, // LD2Rv16b 837 5285751U, // LD2Rv16b_POST 838 46967U, // LD2Rv1d 839 4245367U, // LD2Rv1d_POST 840 55159U, // LD2Rv2d 841 4253559U, // LD2Rv2d_POST 842 63351U, // LD2Rv2s 843 4523895U, // LD2Rv2s_POST 844 71543U, // LD2Rv4h 845 5056375U, // LD2Rv4h_POST 846 79735U, // LD2Rv4s 847 4540279U, // LD2Rv4s_POST 848 87927U, // LD2Rv8b 849 5334903U, // LD2Rv8b_POST 850 96119U, // LD2Rv8h 851 5080951U, // LD2Rv8h_POST 852 36947U, // LD2Twov16b 853 3973203U, // LD2Twov16b_POST 854 53331U, // LD2Twov2d 855 3989587U, // LD2Twov2d_POST 856 61523U, // LD2Twov2s 857 4259923U, // LD2Twov2s_POST 858 69715U, // LD2Twov4h 859 4268115U, // LD2Twov4h_POST 860 77907U, // LD2Twov4s 861 4014163U, // LD2Twov4s_POST 862 86099U, // LD2Twov8b 863 4284499U, // LD2Twov8b_POST 864 94291U, // LD2Twov8h 865 4030547U, // LD2Twov8h_POST 866 6131795U, // LD2i16 867 6660179U, // LD2i16_POST 868 6139987U, // LD2i32 869 6930515U, // LD2i32_POST 870 6148179U, // LD2i64 871 7462995U, // LD2i64_POST 872 6156371U, // LD2i8 873 6422611U, // LD2i8_POST 874 38781U, // LD3Rv16b 875 7645053U, // LD3Rv16b_POST 876 46973U, // LD3Rv1d 877 5818237U, // LD3Rv1d_POST 878 55165U, // LD3Rv2d 879 5826429U, // LD3Rv2d_POST 880 63357U, // LD3Rv2s 881 7931773U, // LD3Rv2s_POST 882 71549U, // LD3Rv4h 883 8202109U, // LD3Rv4h_POST 884 79741U, // LD3Rv4s 885 7948157U, // LD3Rv4s_POST 886 87933U, // LD3Rv8b 887 7694205U, // LD3Rv8b_POST 888 96125U, // LD3Rv8h 889 8226685U, // LD3Rv8h_POST 890 37317U, // LD3Threev16b 891 5546437U, // LD3Threev16b_POST 892 53701U, // LD3Threev2d 893 5562821U, // LD3Threev2d_POST 894 61893U, // LD3Threev2s 895 5833157U, // LD3Threev2s_POST 896 70085U, // LD3Threev4h 897 5841349U, // LD3Threev4h_POST 898 78277U, // LD3Threev4s 899 5587397U, // LD3Threev4s_POST 900 86469U, // LD3Threev8b 901 5857733U, // LD3Threev8b_POST 902 94661U, // LD3Threev8h 903 5603781U, // LD3Threev8h_POST 904 6132165U, // LD3i16 905 8495557U, // LD3i16_POST 906 6140357U, // LD3i32 907 8765893U, // LD3i32_POST 908 6148549U, // LD3i64 909 9036229U, // LD3i64_POST 910 6156741U, // LD3i8 911 9306565U, // LD3i8_POST 912 37341U, // LD4Fourv16b 913 3711453U, // LD4Fourv16b_POST 914 53725U, // LD4Fourv2d 915 3727837U, // LD4Fourv2d_POST 916 61917U, // LD4Fourv2s 917 3998173U, // LD4Fourv2s_POST 918 70109U, // LD4Fourv4h 919 4006365U, // LD4Fourv4h_POST 920 78301U, // LD4Fourv4s 921 3752413U, // LD4Fourv4s_POST 922 86493U, // LD4Fourv8b 923 4022749U, // LD4Fourv8b_POST 924 94685U, // LD4Fourv8h 925 3768797U, // LD4Fourv8h_POST 926 38787U, // LD4Rv16b 927 5023619U, // LD4Rv16b_POST 928 46979U, // LD4Rv1d 929 3983235U, // LD4Rv1d_POST 930 55171U, // LD4Rv2d 931 3991427U, // LD4Rv2d_POST 932 63363U, // LD4Rv2s 933 4261763U, // LD4Rv2s_POST 934 71555U, // LD4Rv4h 935 4532099U, // LD4Rv4h_POST 936 79747U, // LD4Rv4s 937 4278147U, // LD4Rv4s_POST 938 87939U, // LD4Rv8b 939 5072771U, // LD4Rv8b_POST 940 96131U, // LD4Rv8h 941 4556675U, // LD4Rv8h_POST 942 6132189U, // LD4i16 943 6922717U, // LD4i16_POST 944 6140381U, // LD4i32 945 7455197U, // LD4i32_POST 946 6148573U, // LD4i64 947 9560541U, // LD4i64_POST 948 6156765U, // LD4i8 949 6685149U, // LD4i8_POST 950 26485304U, // LDARB 951 26485801U, // LDARH 952 26486665U, // LDARW 953 26486665U, // LDARX 954 553920315U, // LDAXPW 955 553920315U, // LDAXPX 956 26485358U, // LDAXRB 957 26485855U, // LDAXRH 958 26486787U, // LDAXRW 959 26486787U, // LDAXRX 960 553920258U, // LDNPDi 961 553920258U, // LDNPQi 962 553920258U, // LDNPSi 963 553920258U, // LDNPWi 964 553920258U, // LDNPXi 965 553920190U, // LDPDi 966 604276414U, // LDPDpost 967 604276414U, // LDPDpre 968 553920190U, // LDPQi 969 604276414U, // LDPQpost 970 604276414U, // LDPQpre 971 553920974U, // LDPSWi 972 604277198U, // LDPSWpost 973 604277198U, // LDPSWpre 974 553920190U, // LDPSi 975 604276414U, // LDPSpost 976 604276414U, // LDPSpre 977 553920190U, // LDPWi 978 604276414U, // LDPWpost 979 604276414U, // LDPWpre 980 553920190U, // LDPXi 981 604276414U, // LDPXpost 982 604276414U, // LDPXpre 983 1150583359U, // LDRBBpost 984 76841535U, // LDRBBpre 985 26485311U, // LDRBBroW 986 26485311U, // LDRBBroX 987 26485311U, // LDRBBui 988 1150584728U, // LDRBpost 989 76842904U, // LDRBpre 990 26486680U, // LDRBroW 991 26486680U, // LDRBroX 992 26486680U, // LDRBui 993 100935576U, // LDRDl 994 1150584728U, // LDRDpost 995 76842904U, // LDRDpre 996 26486680U, // LDRDroW 997 26486680U, // LDRDroX 998 26486680U, // LDRDui 999 1150583856U, // LDRHHpost 1000 76842032U, // LDRHHpre 1001 26485808U, // LDRHHroW 1002 26485808U, // LDRHHroX 1003 26485808U, // LDRHHui 1004 1150584728U, // LDRHpost 1005 76842904U, // LDRHpre 1006 26486680U, // LDRHroW 1007 26486680U, // LDRHroX 1008 26486680U, // LDRHui 1009 100935576U, // LDRQl 1010 1150584728U, // LDRQpost 1011 76842904U, // LDRQpre 1012 26486680U, // LDRQroW 1013 26486680U, // LDRQroX 1014 26486680U, // LDRQui 1015 1150583446U, // LDRSBWpost 1016 76841622U, // LDRSBWpre 1017 26485398U, // LDRSBWroW 1018 26485398U, // LDRSBWroX 1019 26485398U, // LDRSBWui 1020 1150583446U, // LDRSBXpost 1021 76841622U, // LDRSBXpre 1022 26485398U, // LDRSBXroW 1023 26485398U, // LDRSBXroX 1024 26485398U, // LDRSBXui 1025 1150583933U, // LDRSHWpost 1026 76842109U, // LDRSHWpre 1027 26485885U, // LDRSHWroW 1028 26485885U, // LDRSHWroX 1029 26485885U, // LDRSHWui 1030 1150583933U, // LDRSHXpost 1031 76842109U, // LDRSHXpre 1032 26485885U, // LDRSHXroW 1033 26485885U, // LDRSHXroX 1034 26485885U, // LDRSHXui 1035 100936149U, // LDRSWl 1036 1150585301U, // LDRSWpost 1037 76843477U, // LDRSWpre 1038 26487253U, // LDRSWroW 1039 26487253U, // LDRSWroX 1040 26487253U, // LDRSWui 1041 100935576U, // LDRSl 1042 1150584728U, // LDRSpost 1043 76842904U, // LDRSpre 1044 26486680U, // LDRSroW 1045 26486680U, // LDRSroX 1046 26486680U, // LDRSui 1047 100935576U, // LDRWl 1048 1150584728U, // LDRWpost 1049 76842904U, // LDRWpre 1050 26486680U, // LDRWroW 1051 26486680U, // LDRWroX 1052 26486680U, // LDRWui 1053 100935576U, // LDRXl 1054 1150584728U, // LDRXpost 1055 76842904U, // LDRXpre 1056 26486680U, // LDRXroW 1057 26486680U, // LDRXroX 1058 26486680U, // LDRXui 1059 26485324U, // LDTRBi 1060 26485821U, // LDTRHi 1061 26485405U, // LDTRSBWi 1062 26485405U, // LDTRSBXi 1063 26485892U, // LDTRSHWi 1064 26485892U, // LDTRSHXi 1065 26487260U, // LDTRSWi 1066 26486752U, // LDTRWi 1067 26486752U, // LDTRXi 1068 26485344U, // LDURBBi 1069 26486775U, // LDURBi 1070 26486775U, // LDURDi 1071 26485841U, // LDURHHi 1072 26486775U, // LDURHi 1073 26486775U, // LDURQi 1074 26485413U, // LDURSBWi 1075 26485413U, // LDURSBXi 1076 26485900U, // LDURSHWi 1077 26485900U, // LDURSHXi 1078 26487268U, // LDURSWi 1079 26486775U, // LDURSi 1080 26486775U, // LDURWi 1081 26486775U, // LDURXi 1082 553920343U, // LDXPW 1083 553920343U, // LDXPX 1084 26485366U, // LDXRB 1085 26485863U, // LDXRH 1086 26486794U, // LDXRW 1087 26486794U, // LDXRX 1088 0U, // LOADgot 1089 17049003U, // LSLVWr 1090 17049003U, // LSLVXr 1091 17049558U, // LSRVWr 1092 17049558U, // LSRVXr 1093 17048395U, // MADDWrrr 1094 17048395U, // MADDXrrr 1095 2181050875U, // MLAv16i8 1096 2718446075U, // MLAv2i32 1097 2718446075U, // MLAv2i32_indexed 1098 3255841275U, // MLAv4i16 1099 3255841275U, // MLAv4i16_indexed 1100 1108619771U, // MLAv4i32 1101 1108619771U, // MLAv4i32_indexed 1102 1645752827U, // MLAv8i16 1103 1645752827U, // MLAv8i16_indexed 1104 3793498619U, // MLAv8i8 1105 2181052514U, // MLSv16i8 1106 2718447714U, // MLSv2i32 1107 2718447714U, // MLSv2i32_indexed 1108 3255842914U, // MLSv4i16 1109 3255842914U, // MLSv4i16_indexed 1110 1108621410U, // MLSv4i32 1111 1108621410U, // MLSv4i32_indexed 1112 1645754466U, // MLSv8i16 1113 1645754466U, // MLSv8i16_indexed 1114 3793500258U, // MLSv8i8 1115 168043698U, // MOVID 1116 721425586U, // MOVIv16b_ns 1117 168563890U, // MOVIv2d_ns 1118 1795691698U, // MOVIv2i32 1119 1795691698U, // MOVIv2s_msl 1120 1796215986U, // MOVIv4i16 1121 1796478130U, // MOVIv4i32 1122 1796478130U, // MOVIv4s_msl 1123 723260594U, // MOVIv8b_ns 1124 1796740274U, // MOVIv8i16 1125 84157629U, // MOVKWi 1126 84157629U, // MOVKXi 1127 1795434146U, // MOVNWi 1128 1795434146U, // MOVNXi 1129 1795435093U, // MOVZWi 1130 1795435093U, // MOVZXi 1131 0U, // MOVaddr 1132 0U, // MOVaddrBA 1133 0U, // MOVaddrCP 1134 0U, // MOVaddrEXT 1135 0U, // MOVaddrJT 1136 0U, // MOVaddrTLS 1137 0U, // MOVi32imm 1138 0U, // MOVi64imm 1139 201599116U, // MRS 1140 137179U, // MSR 1141 141275U, // MSRpstate 1142 17048258U, // MSUBWrrr 1143 17048258U, // MSUBXrrr 1144 2147489228U, // MULv16i8 1145 2684884428U, // MULv2i32 1146 2684884428U, // MULv2i32_indexed 1147 3222279628U, // MULv4i16 1148 3222279628U, // MULv4i16_indexed 1149 1075058124U, // MULv4i32 1150 1075058124U, // MULv4i32_indexed 1151 1612191180U, // MULv8i16 1152 1612191180U, // MULv8i16_indexed 1153 3759936972U, // MULv8i8 1154 1795691679U, // MVNIv2i32 1155 1795691679U, // MVNIv2s_msl 1156 1796215967U, // MVNIv4i16 1157 1796478111U, // MVNIv4i32 1158 1796478111U, // MVNIv4s_msl 1159 1796740255U, // MVNIv8i16 1160 5076U, // NEGv16i8 1161 553919444U, // NEGv1i64 1162 1074271188U, // NEGv2i32 1163 1611404244U, // NEGv2i64 1164 2148537300U, // NEGv4i16 1165 2685670356U, // NEGv4i32 1166 3222803412U, // NEGv8i16 1167 3759936468U, // NEGv8i8 1168 6353U, // NOTv16i8 1169 3759937745U, // NOTv8i8 1170 0U, // ORNWrr 1171 17049189U, // ORNWrs 1172 0U, // ORNXrr 1173 17049189U, // ORNXrs 1174 2147489381U, // ORNv16i8 1175 3759937125U, // ORNv8i8 1176 17049548U, // ORRWri 1177 0U, // ORRWrr 1178 17049548U, // ORRWrs 1179 17049548U, // ORRXri 1180 0U, // ORRXrr 1181 17049548U, // ORRXrs 1182 2147489740U, // ORRv16i8 1183 84424652U, // ORRv2i32 1184 84948940U, // ORRv4i16 1185 85211084U, // ORRv4i32 1186 85473228U, // ORRv8i16 1187 3759937484U, // ORRv8i8 1188 2149060822U, // PMULLv16i8 1189 228070797U, // PMULLv1i64 1190 244846806U, // PMULLv2i64 1191 3759674765U, // PMULLv8i8 1192 2147489240U, // PMULv16i8 1193 3759936984U, // PMULv8i8 1194 101070321U, // PRFMl 1195 26621425U, // PRFMroW 1196 26621425U, // PRFMroX 1197 26621425U, // PRFMui 1198 26621455U, // PRFUMi 1199 537400862U, // RADDHNv2i64_v2i32 1200 571748633U, // RADDHNv2i64_v4i32 1201 1074796062U, // RADDHNv4i32_v4i16 1202 1108881689U, // RADDHNv4i32_v8i16 1203 1644179737U, // RADDHNv8i16_v16i8 1204 1612453406U, // RADDHNv8i16_v8i8 1205 553920698U, // RBITWr 1206 553920698U, // RBITXr 1207 6330U, // RBITv16i8 1208 3759937722U, // RBITv8i8 1209 2107559U, // RET 1210 0U, // RET_ReallyLR 1211 553918951U, // REV16Wr 1212 553918951U, // REV16Xr 1213 4583U, // REV16v16i8 1214 3759935975U, // REV16v8i8 1215 553918540U, // REV32Xr 1216 4172U, // REV32v16i8 1217 2148536396U, // REV32v4i16 1218 3222802508U, // REV32v8i16 1219 3759935564U, // REV32v8i8 1220 4566U, // REV64v16i8 1221 1074270678U, // REV64v2i32 1222 2148536790U, // REV64v4i16 1223 2685669846U, // REV64v4i32 1224 3222802902U, // REV64v8i16 1225 3759935958U, // REV64v8i8 1226 553920805U, // REVWr 1227 553920805U, // REVXr 1228 17049543U, // RORVWr 1229 17049543U, // RORVXr 1230 1644179766U, // RSHRNv16i8_shift 1231 537400917U, // RSHRNv2i32_shift 1232 1074796117U, // RSHRNv4i16_shift 1233 571748662U, // RSHRNv4i32_shift 1234 1108881718U, // RSHRNv8i16_shift 1235 1612453461U, // RSHRNv8i8_shift 1236 537400854U, // RSUBHNv2i64_v2i32 1237 571748624U, // RSUBHNv2i64_v4i32 1238 1074796054U, // RSUBHNv4i32_v4i16 1239 1108881680U, // RSUBHNv4i32_v8i16 1240 1644179728U, // RSUBHNv8i16_v16i8 1241 1612453398U, // RSUBHNv8i16_v8i8 1242 2182623330U, // SABALv16i8_v8i16 1243 2718708931U, // SABALv2i32_v2i64 1244 3256104131U, // SABALv4i16_v4i32 1245 1108095074U, // SABALv4i32_v2i64 1246 1645490274U, // SABALv8i16_v4i32 1247 3793237187U, // SABALv8i8_v8i16 1248 2181050862U, // SABAv16i8 1249 2718446062U, // SABAv2i32 1250 3255841262U, // SABAv4i16 1251 1108619758U, // SABAv4i32 1252 1645752814U, // SABAv8i16 1253 3793498606U, // SABAv8i8 1254 2149060764U, // SABDLv16i8_v8i16 1255 2685146379U, // SABDLv2i32_v2i64 1256 3222541579U, // SABDLv4i16_v4i32 1257 1074532508U, // SABDLv4i32_v2i64 1258 1611927708U, // SABDLv8i16_v4i32 1259 3759674635U, // SABDLv8i8_v8i16 1260 2147488538U, // SABDv16i8 1261 2684883738U, // SABDv2i32 1262 3222278938U, // SABDv4i16 1263 1075057434U, // SABDv4i32 1264 1612190490U, // SABDv8i16 1265 3759936282U, // SABDv8i8 1266 35141315U, // SADALPv16i8_v8i16 1267 1117533891U, // SADALPv2i32_v1i64 1268 2181576387U, // SADALPv4i16_v2i32 1269 2718709443U, // SADALPv4i32_v2i64 1270 3256104643U, // SADALPv8i16_v4i32 1271 3792713411U, // SADALPv8i8_v4i16 1272 1578707U, // SADDLPv16i8_v8i16 1273 1083971283U, // SADDLPv2i32_v1i64 1274 2148013779U, // SADDLPv4i16_v2i32 1275 2685146835U, // SADDLPv4i32_v2i64 1276 3222542035U, // SADDLPv8i16_v4i32 1277 3759150803U, // SADDLPv8i8_v4i16 1278 272700U, // SADDLVv16i8v 1279 2147756348U, // SADDLVv4i16v 1280 2684627260U, // SADDLVv4i32v 1281 3221498172U, // SADDLVv8i16v 1282 3758369084U, // SADDLVv8i8v 1283 2149060780U, // SADDLv16i8_v8i16 1284 2685146409U, // SADDLv2i32_v2i64 1285 3222541609U, // SADDLv4i16_v4i32 1286 1074532524U, // SADDLv4i32_v2i64 1287 1611927724U, // SADDLv8i16_v4i32 1288 3759674665U, // SADDLv8i8_v8i16 1289 1612190133U, // SADDWv16i8_v8i16 1290 537663936U, // SADDWv2i32_v2i64 1291 1075059136U, // SADDWv4i16_v4i32 1292 537661877U, // SADDWv4i32_v2i64 1293 1075057077U, // SADDWv8i16_v4i32 1294 1612192192U, // SADDWv8i8_v8i16 1295 17049656U, // SBCSWr 1296 17049656U, // SBCSXr 1297 17048293U, // SBCWr 1298 17048293U, // SBCXr 1299 17049061U, // SBFMWri 1300 17049061U, // SBFMXri 1301 17048517U, // SCVTFSWDri 1302 17048517U, // SCVTFSWSri 1303 17048517U, // SCVTFSXDri 1304 17048517U, // SCVTFSXSri 1305 553919429U, // SCVTFUWDri 1306 553919429U, // SCVTFUWSri 1307 553919429U, // SCVTFUXDri 1308 553919429U, // SCVTFUXSri 1309 17048517U, // SCVTFd 1310 17048517U, // SCVTFs 1311 553919429U, // SCVTFv1i32 1312 553919429U, // SCVTFv1i64 1313 1074271173U, // SCVTFv2f32 1314 1611404229U, // SCVTFv2f64 1315 2684883909U, // SCVTFv2i32_shift 1316 537662405U, // SCVTFv2i64_shift 1317 2685670341U, // SCVTFv4f32 1318 1075057605U, // SCVTFv4i32_shift 1319 17049904U, // SDIVWr 1320 17049904U, // SDIVXr 1321 17049904U, // SDIV_IntWr 1322 17049904U, // SDIV_IntXr 1323 67404510U, // SHA1Crrr 1324 553919463U, // SHA1Hrr 1325 67405278U, // SHA1Mrrr 1326 67405488U, // SHA1Prrr 1327 1108619265U, // SHA1SU0rrr 1328 2719232056U, // SHA1SU1rr 1329 67403864U, // SHA256H2rrr 1330 67404790U, // SHA256Hrrr 1331 2719232010U, // SHA256SU0rr 1332 1108619329U, // SHA256SU1rrr 1333 2147488572U, // SHADDv16i8 1334 2684883772U, // SHADDv2i32 1335 3222278972U, // SHADDv4i16 1336 1075057468U, // SHADDv4i32 1337 1612190524U, // SHADDv8i16 1338 3759936316U, // SHADDv8i8 1339 2149060797U, // SHLLv16i8 1340 2685146487U, // SHLLv2i32 1341 3222541687U, // SHLLv4i16 1342 3758887101U, // SHLLv4i32 1343 1315005U, // SHLLv8i16 1344 538449271U, // SHLLv8i8 1345 17048896U, // SHLd 1346 2147489088U, // SHLv16i8_shift 1347 2684884288U, // SHLv2i32_shift 1348 537662784U, // SHLv2i64_shift 1349 3222279488U, // SHLv4i16_shift 1350 1075057984U, // SHLv4i32_shift 1351 1612191040U, // SHLv8i16_shift 1352 3759936832U, // SHLv8i8_shift 1353 1644179748U, // SHRNv16i8_shift 1354 537400901U, // SHRNv2i32_shift 1355 1074796101U, // SHRNv4i16_shift 1356 571748644U, // SHRNv4i32_shift 1357 1108881700U, // SHRNv8i16_shift 1358 1612453445U, // SHRNv8i8_shift 1359 2147488435U, // SHSUBv16i8 1360 2684883635U, // SHSUBv2i32 1361 3222278835U, // SHSUBv4i16 1362 1075057331U, // SHSUBv4i32 1363 1612190387U, // SHSUBv8i16 1364 3759936179U, // SHSUBv8i8 1365 67404954U, // SLId 1366 2181051546U, // SLIv16i8_shift 1367 2718446746U, // SLIv2i32_shift 1368 571225242U, // SLIv2i64_shift 1369 3255841946U, // SLIv4i16_shift 1370 1108620442U, // SLIv4i32_shift 1371 1645753498U, // SLIv8i16_shift 1372 3793499290U, // SLIv8i8_shift 1373 17048857U, // SMADDLrrr 1374 2147489609U, // SMAXPv16i8 1375 2684884809U, // SMAXPv2i32 1376 3222280009U, // SMAXPv4i16 1377 1075058505U, // SMAXPv4i32 1378 1612191561U, // SMAXPv8i16 1379 3759937353U, // SMAXPv8i8 1380 272787U, // SMAXVv16i8v 1381 2147756435U, // SMAXVv4i16v 1382 2684627347U, // SMAXVv4i32v 1383 3221498259U, // SMAXVv8i16v 1384 3758369171U, // SMAXVv8i8v 1385 2147490298U, // SMAXv16i8 1386 2684885498U, // SMAXv2i32 1387 3222280698U, // SMAXv4i16 1388 1075059194U, // SMAXv4i32 1389 1612192250U, // SMAXv8i16 1390 3759938042U, // SMAXv8i8 1391 21246U, // SMC 1392 2147489551U, // SMINPv16i8 1393 2684884751U, // SMINPv2i32 1394 3222279951U, // SMINPv4i16 1395 1075058447U, // SMINPv4i32 1396 1612191503U, // SMINPv8i16 1397 3759937295U, // SMINPv8i8 1398 272741U, // SMINVv16i8v 1399 2147756389U, // SMINVv4i16v 1400 2684627301U, // SMINVv4i32v 1401 3221498213U, // SMINVv8i16v 1402 3758369125U, // SMINVv8i8v 1403 2147489324U, // SMINv16i8 1404 2684884524U, // SMINv2i32 1405 3222279724U, // SMINv4i16 1406 1075058220U, // SMINv4i32 1407 1612191276U, // SMINv8i16 1408 3759937068U, // SMINv8i8 1409 2182623356U, // SMLALv16i8_v8i16 1410 2718708954U, // SMLALv2i32_indexed 1411 2718708954U, // SMLALv2i32_v2i64 1412 3256104154U, // SMLALv4i16_indexed 1413 3256104154U, // SMLALv4i16_v4i32 1414 1108095100U, // SMLALv4i32_indexed 1415 1108095100U, // SMLALv4i32_v2i64 1416 1645490300U, // SMLALv8i16_indexed 1417 1645490300U, // SMLALv8i16_v4i32 1418 3793237210U, // SMLALv8i8_v8i16 1419 2182623480U, // SMLSLv16i8_v8i16 1420 2718709168U, // SMLSLv2i32_indexed 1421 2718709168U, // SMLSLv2i32_v2i64 1422 3256104368U, // SMLSLv4i16_indexed 1423 3256104368U, // SMLSLv4i16_v4i32 1424 1108095224U, // SMLSLv4i32_indexed 1425 1108095224U, // SMLSLv4i32_v2i64 1426 1645490424U, // SMLSLv8i16_indexed 1427 1645490424U, // SMLSLv8i16_v4i32 1428 3793237424U, // SMLSLv8i8_v8i16 1429 272768U, // SMOVvi16to32 1430 272768U, // SMOVvi16to64 1431 537143680U, // SMOVvi32to64 1432 1610885504U, // SMOVvi8to32 1433 1610885504U, // SMOVvi8to64 1434 17048813U, // SMSUBLrrr 1435 17048603U, // SMULHrr 1436 2149060830U, // SMULLv16i8_v8i16 1437 2685146516U, // SMULLv2i32_indexed 1438 2685146516U, // SMULLv2i32_v2i64 1439 3222541716U, // SMULLv4i16_indexed 1440 3222541716U, // SMULLv4i16_v4i32 1441 1074532574U, // SMULLv4i32_indexed 1442 1074532574U, // SMULLv4i32_v2i64 1443 1611927774U, // SMULLv8i16_indexed 1444 1611927774U, // SMULLv8i16_v4i32 1445 3759674772U, // SMULLv8i8_v8i16 1446 6187U, // SQABSv16i8 1447 553920555U, // SQABSv1i16 1448 553920555U, // SQABSv1i32 1449 553920555U, // SQABSv1i64 1450 553920555U, // SQABSv1i8 1451 1074272299U, // SQABSv2i32 1452 1611405355U, // SQABSv2i64 1453 2148538411U, // SQABSv4i16 1454 2685671467U, // SQABSv4i32 1455 3222804523U, // SQABSv8i16 1456 3759937579U, // SQABSv8i8 1457 2147488602U, // SQADDv16i8 1458 17048410U, // SQADDv1i16 1459 17048410U, // SQADDv1i32 1460 17048410U, // SQADDv1i64 1461 17048410U, // SQADDv1i8 1462 2684883802U, // SQADDv2i32 1463 537662298U, // SQADDv2i64 1464 3222279002U, // SQADDv4i16 1465 1075057498U, // SQADDv4i32 1466 1612190554U, // SQADDv8i16 1467 3759936346U, // SQADDv8i8 1468 67405009U, // SQDMLALi16 1469 67405009U, // SQDMLALi32 1470 67405009U, // SQDMLALv1i32_indexed 1471 67405009U, // SQDMLALv1i64_indexed 1472 2718708945U, // SQDMLALv2i32_indexed 1473 2718708945U, // SQDMLALv2i32_v2i64 1474 3256104145U, // SQDMLALv4i16_indexed 1475 3256104145U, // SQDMLALv4i16_v4i32 1476 1108095090U, // SQDMLALv4i32_indexed 1477 1108095090U, // SQDMLALv4i32_v2i64 1478 1645490290U, // SQDMLALv8i16_indexed 1479 1645490290U, // SQDMLALv8i16_v4i32 1480 67405223U, // SQDMLSLi16 1481 67405223U, // SQDMLSLi32 1482 67405223U, // SQDMLSLv1i32_indexed 1483 67405223U, // SQDMLSLv1i64_indexed 1484 2718709159U, // SQDMLSLv2i32_indexed 1485 2718709159U, // SQDMLSLv2i32_v2i64 1486 3256104359U, // SQDMLSLv4i16_indexed 1487 3256104359U, // SQDMLSLv4i16_v4i32 1488 1108095214U, // SQDMLSLv4i32_indexed 1489 1108095214U, // SQDMLSLv4i32_v2i64 1490 1645490414U, // SQDMLSLv8i16_indexed 1491 1645490414U, // SQDMLSLv8i16_v4i32 1492 17048584U, // SQDMULHv1i16 1493 17048584U, // SQDMULHv1i16_indexed 1494 17048584U, // SQDMULHv1i32 1495 17048584U, // SQDMULHv1i32_indexed 1496 2684883976U, // SQDMULHv2i32 1497 2684883976U, // SQDMULHv2i32_indexed 1498 3222279176U, // SQDMULHv4i16 1499 3222279176U, // SQDMULHv4i16_indexed 1500 1075057672U, // SQDMULHv4i32 1501 1075057672U, // SQDMULHv4i32_indexed 1502 1612190728U, // SQDMULHv8i16 1503 1612190728U, // SQDMULHv8i16_indexed 1504 17048964U, // SQDMULLi16 1505 17048964U, // SQDMULLi32 1506 17048964U, // SQDMULLv1i32_indexed 1507 17048964U, // SQDMULLv1i64_indexed 1508 2685146500U, // SQDMULLv2i32_indexed 1509 2685146500U, // SQDMULLv2i32_v2i64 1510 3222541700U, // SQDMULLv4i16_indexed 1511 3222541700U, // SQDMULLv4i16_v4i32 1512 1074532556U, // SQDMULLv4i32_indexed 1513 1074532556U, // SQDMULLv4i32_v2i64 1514 1611927756U, // SQDMULLv8i16_indexed 1515 1611927756U, // SQDMULLv8i16_v4i32 1516 5081U, // SQNEGv16i8 1517 553919449U, // SQNEGv1i16 1518 553919449U, // SQNEGv1i32 1519 553919449U, // SQNEGv1i64 1520 553919449U, // SQNEGv1i8 1521 1074271193U, // SQNEGv2i32 1522 1611404249U, // SQNEGv2i64 1523 2148537305U, // SQNEGv4i16 1524 2685670361U, // SQNEGv4i32 1525 3222803417U, // SQNEGv8i16 1526 3759936473U, // SQNEGv8i8 1527 17048593U, // SQRDMULHv1i16 1528 17048593U, // SQRDMULHv1i16_indexed 1529 17048593U, // SQRDMULHv1i32 1530 17048593U, // SQRDMULHv1i32_indexed 1531 2684883985U, // SQRDMULHv2i32 1532 2684883985U, // SQRDMULHv2i32_indexed 1533 3222279185U, // SQRDMULHv4i16 1534 3222279185U, // SQRDMULHv4i16_indexed 1535 1075057681U, // SQRDMULHv4i32 1536 1075057681U, // SQRDMULHv4i32_indexed 1537 1612190737U, // SQRDMULHv8i16 1538 1612190737U, // SQRDMULHv8i16_indexed 1539 2147489100U, // SQRSHLv16i8 1540 17048908U, // SQRSHLv1i16 1541 17048908U, // SQRSHLv1i32 1542 17048908U, // SQRSHLv1i64 1543 17048908U, // SQRSHLv1i8 1544 2684884300U, // SQRSHLv2i32 1545 537662796U, // SQRSHLv2i64 1546 3222279500U, // SQRSHLv4i16 1547 1075057996U, // SQRSHLv4i32 1548 1612191052U, // SQRSHLv8i16 1549 3759936844U, // SQRSHLv8i8 1550 17049171U, // SQRSHRNb 1551 17049171U, // SQRSHRNh 1552 17049171U, // SQRSHRNs 1553 1644179764U, // SQRSHRNv16i8_shift 1554 537400915U, // SQRSHRNv2i32_shift 1555 1074796115U, // SQRSHRNv4i16_shift 1556 571748660U, // SQRSHRNv4i32_shift 1557 1108881716U, // SQRSHRNv8i16_shift 1558 1612453459U, // SQRSHRNv8i8_shift 1559 17049232U, // SQRSHRUNb 1560 17049232U, // SQRSHRUNh 1561 17049232U, // SQRSHRUNs 1562 1644179824U, // SQRSHRUNv16i8_shift 1563 537400976U, // SQRSHRUNv2i32_shift 1564 1074796176U, // SQRSHRUNv4i16_shift 1565 571748720U, // SQRSHRUNv4i32_shift 1566 1108881776U, // SQRSHRUNv8i16_shift 1567 1612453520U, // SQRSHRUNv8i8_shift 1568 17049847U, // SQSHLUb 1569 17049847U, // SQSHLUd 1570 17049847U, // SQSHLUh 1571 17049847U, // SQSHLUs 1572 2147490039U, // SQSHLUv16i8_shift 1573 2684885239U, // SQSHLUv2i32_shift 1574 537663735U, // SQSHLUv2i64_shift 1575 3222280439U, // SQSHLUv4i16_shift 1576 1075058935U, // SQSHLUv4i32_shift 1577 1612191991U, // SQSHLUv8i16_shift 1578 3759937783U, // SQSHLUv8i8_shift 1579 17048894U, // SQSHLb 1580 17048894U, // SQSHLd 1581 17048894U, // SQSHLh 1582 17048894U, // SQSHLs 1583 2147489086U, // SQSHLv16i8 1584 2147489086U, // SQSHLv16i8_shift 1585 17048894U, // SQSHLv1i16 1586 17048894U, // SQSHLv1i32 1587 17048894U, // SQSHLv1i64 1588 17048894U, // SQSHLv1i8 1589 2684884286U, // SQSHLv2i32 1590 2684884286U, // SQSHLv2i32_shift 1591 537662782U, // SQSHLv2i64 1592 537662782U, // SQSHLv2i64_shift 1593 3222279486U, // SQSHLv4i16 1594 3222279486U, // SQSHLv4i16_shift 1595 1075057982U, // SQSHLv4i32 1596 1075057982U, // SQSHLv4i32_shift 1597 1612191038U, // SQSHLv8i16 1598 1612191038U, // SQSHLv8i16_shift 1599 3759936830U, // SQSHLv8i8 1600 3759936830U, // SQSHLv8i8_shift 1601 17049155U, // SQSHRNb 1602 17049155U, // SQSHRNh 1603 17049155U, // SQSHRNs 1604 1644179746U, // SQSHRNv16i8_shift 1605 537400899U, // SQSHRNv2i32_shift 1606 1074796099U, // SQSHRNv4i16_shift 1607 571748642U, // SQSHRNv4i32_shift 1608 1108881698U, // SQSHRNv8i16_shift 1609 1612453443U, // SQSHRNv8i8_shift 1610 17049223U, // SQSHRUNb 1611 17049223U, // SQSHRUNh 1612 17049223U, // SQSHRUNs 1613 1644179814U, // SQSHRUNv16i8_shift 1614 537400967U, // SQSHRUNv2i32_shift 1615 1074796167U, // SQSHRUNv4i16_shift 1616 571748710U, // SQSHRUNv4i32_shift 1617 1108881766U, // SQSHRUNv8i16_shift 1618 1612453511U, // SQSHRUNv8i8_shift 1619 2147488464U, // SQSUBv16i8 1620 17048272U, // SQSUBv1i16 1621 17048272U, // SQSUBv1i32 1622 17048272U, // SQSUBv1i64 1623 17048272U, // SQSUBv1i8 1624 2684883664U, // SQSUBv2i32 1625 537662160U, // SQSUBv2i64 1626 3222278864U, // SQSUBv4i16 1627 1075057360U, // SQSUBv4i32 1628 1612190416U, // SQSUBv8i16 1629 3759936208U, // SQSUBv8i8 1630 3254792534U, // SQXTNv16i8 1631 553920121U, // SQXTNv1i16 1632 553920121U, // SQXTNv1i32 1633 553920121U, // SQXTNv1i8 1634 1611142777U, // SQXTNv2i32 1635 2685408889U, // SQXTNv4i16 1636 1645490518U, // SQXTNv4i32 1637 2719494486U, // SQXTNv8i16 1638 3223066233U, // SQXTNv8i8 1639 3254792571U, // SQXTUNv16i8 1640 553920154U, // SQXTUNv1i16 1641 553920154U, // SQXTUNv1i32 1642 553920154U, // SQXTUNv1i8 1643 1611142810U, // SQXTUNv2i32 1644 2685408922U, // SQXTUNv4i16 1645 1645490555U, // SQXTUNv4i32 1646 2719494523U, // SQXTUNv8i16 1647 3223066266U, // SQXTUNv8i8 1648 2147488556U, // SRHADDv16i8 1649 2684883756U, // SRHADDv2i32 1650 3222278956U, // SRHADDv4i16 1651 1075057452U, // SRHADDv4i32 1652 1612190508U, // SRHADDv8i16 1653 3759936300U, // SRHADDv8i8 1654 67404965U, // SRId 1655 2181051557U, // SRIv16i8_shift 1656 2718446757U, // SRIv2i32_shift 1657 571225253U, // SRIv2i64_shift 1658 3255841957U, // SRIv4i16_shift 1659 1108620453U, // SRIv4i32_shift 1660 1645753509U, // SRIv8i16_shift 1661 3793499301U, // SRIv8i8_shift 1662 2147489116U, // SRSHLv16i8 1663 17048924U, // SRSHLv1i64 1664 2684884316U, // SRSHLv2i32 1665 537662812U, // SRSHLv2i64 1666 3222279516U, // SRSHLv4i16 1667 1075058012U, // SRSHLv4i32 1668 1612191068U, // SRSHLv8i16 1669 3759936860U, // SRSHLv8i8 1670 17049501U, // SRSHRd 1671 2147489693U, // SRSHRv16i8_shift 1672 2684884893U, // SRSHRv2i32_shift 1673 537663389U, // SRSHRv2i64_shift 1674 3222280093U, // SRSHRv4i16_shift 1675 1075058589U, // SRSHRv4i32_shift 1676 1612191645U, // SRSHRv8i16_shift 1677 3759937437U, // SRSHRv8i8_shift 1678 67404288U, // SRSRAd 1679 2181050880U, // SRSRAv16i8_shift 1680 2718446080U, // SRSRAv2i32_shift 1681 571224576U, // SRSRAv2i64_shift 1682 3255841280U, // SRSRAv4i16_shift 1683 1108619776U, // SRSRAv4i32_shift 1684 1645752832U, // SRSRAv8i16_shift 1685 3793498624U, // SRSRAv8i8_shift 1686 2149060796U, // SSHLLv16i8_shift 1687 2685146486U, // SSHLLv2i32_shift 1688 3222541686U, // SSHLLv4i16_shift 1689 1074532540U, // SSHLLv4i32_shift 1690 1611927740U, // SSHLLv8i16_shift 1691 3759674742U, // SSHLLv8i8_shift 1692 2147489130U, // SSHLv16i8 1693 17048938U, // SSHLv1i64 1694 2684884330U, // SSHLv2i32 1695 537662826U, // SSHLv2i64 1696 3222279530U, // SSHLv4i16 1697 1075058026U, // SSHLv4i32 1698 1612191082U, // SSHLv8i16 1699 3759936874U, // SSHLv8i8 1700 17049515U, // SSHRd 1701 2147489707U, // SSHRv16i8_shift 1702 2684884907U, // SSHRv2i32_shift 1703 537663403U, // SSHRv2i64_shift 1704 3222280107U, // SSHRv4i16_shift 1705 1075058603U, // SSHRv4i32_shift 1706 1612191659U, // SSHRv8i16_shift 1707 3759937451U, // SSHRv8i8_shift 1708 67404302U, // SSRAd 1709 2181050894U, // SSRAv16i8_shift 1710 2718446094U, // SSRAv2i32_shift 1711 571224590U, // SSRAv2i64_shift 1712 3255841294U, // SSRAv4i16_shift 1713 1108619790U, // SSRAv4i32_shift 1714 1645752846U, // SSRAv8i16_shift 1715 3793498638U, // SSRAv8i8_shift 1716 2149060748U, // SSUBLv16i8_v8i16 1717 2685146365U, // SSUBLv2i32_v2i64 1718 3222541565U, // SSUBLv4i16_v4i32 1719 1074532492U, // SSUBLv4i32_v2i64 1720 1611927692U, // SSUBLv8i16_v4i32 1721 3759674621U, // SSUBLv8i8_v8i16 1722 1612190117U, // SSUBWv16i8_v8i16 1723 537663913U, // SSUBWv2i32_v2i64 1724 1075059113U, // SSUBWv4i16_v4i32 1725 537661861U, // SSUBWv4i32_v2i64 1726 1075057061U, // SSUBWv8i16_v4i32 1727 1612192169U, // SSUBWv8i8_v8i16 1728 36915U, // ST1Fourv16b 1729 3711027U, // ST1Fourv16b_POST 1730 45107U, // ST1Fourv1d 1731 3981363U, // ST1Fourv1d_POST 1732 53299U, // ST1Fourv2d 1733 3727411U, // ST1Fourv2d_POST 1734 61491U, // ST1Fourv2s 1735 3997747U, // ST1Fourv2s_POST 1736 69683U, // ST1Fourv4h 1737 4005939U, // ST1Fourv4h_POST 1738 77875U, // ST1Fourv4s 1739 3751987U, // ST1Fourv4s_POST 1740 86067U, // ST1Fourv8b 1741 4022323U, // ST1Fourv8b_POST 1742 94259U, // ST1Fourv8h 1743 3768371U, // ST1Fourv8h_POST 1744 36915U, // ST1Onev16b 1745 4235315U, // ST1Onev16b_POST 1746 45107U, // ST1Onev1d 1747 4505651U, // ST1Onev1d_POST 1748 53299U, // ST1Onev2d 1749 4251699U, // ST1Onev2d_POST 1750 61491U, // ST1Onev2s 1751 4522035U, // ST1Onev2s_POST 1752 69683U, // ST1Onev4h 1753 4530227U, // ST1Onev4h_POST 1754 77875U, // ST1Onev4s 1755 4276275U, // ST1Onev4s_POST 1756 86067U, // ST1Onev8b 1757 4546611U, // ST1Onev8b_POST 1758 94259U, // ST1Onev8h 1759 4292659U, // ST1Onev8h_POST 1760 36915U, // ST1Threev16b 1761 5546035U, // ST1Threev16b_POST 1762 45107U, // ST1Threev1d 1763 5816371U, // ST1Threev1d_POST 1764 53299U, // ST1Threev2d 1765 5562419U, // ST1Threev2d_POST 1766 61491U, // ST1Threev2s 1767 5832755U, // ST1Threev2s_POST 1768 69683U, // ST1Threev4h 1769 5840947U, // ST1Threev4h_POST 1770 77875U, // ST1Threev4s 1771 5586995U, // ST1Threev4s_POST 1772 86067U, // ST1Threev8b 1773 5857331U, // ST1Threev8b_POST 1774 94259U, // ST1Threev8h 1775 5603379U, // ST1Threev8h_POST 1776 36915U, // ST1Twov16b 1777 3973171U, // ST1Twov16b_POST 1778 45107U, // ST1Twov1d 1779 4243507U, // ST1Twov1d_POST 1780 53299U, // ST1Twov2d 1781 3989555U, // ST1Twov2d_POST 1782 61491U, // ST1Twov2s 1783 4259891U, // ST1Twov2s_POST 1784 69683U, // ST1Twov4h 1785 4268083U, // ST1Twov4h_POST 1786 77875U, // ST1Twov4s 1787 4014131U, // ST1Twov4s_POST 1788 86067U, // ST1Twov8b 1789 4284467U, // ST1Twov8b_POST 1790 94259U, // ST1Twov8h 1791 4030515U, // ST1Twov8h_POST 1792 147507U, // ST1i16 1793 262246451U, // ST1i16_POST 1794 151603U, // ST1i32 1795 279031859U, // ST1i32_POST 1796 155699U, // ST1i64 1797 295817267U, // ST1i64_POST 1798 159795U, // ST1i8 1799 312602675U, // ST1i8_POST 1800 37280U, // ST2Twov16b 1801 3973536U, // ST2Twov16b_POST 1802 53664U, // ST2Twov2d 1803 3989920U, // ST2Twov2d_POST 1804 61856U, // ST2Twov2s 1805 4260256U, // ST2Twov2s_POST 1806 70048U, // ST2Twov4h 1807 4268448U, // ST2Twov4h_POST 1808 78240U, // ST2Twov4s 1809 4014496U, // ST2Twov4s_POST 1810 86432U, // ST2Twov8b 1811 4284832U, // ST2Twov8b_POST 1812 94624U, // ST2Twov8h 1813 4030880U, // ST2Twov8h_POST 1814 147872U, // ST2i16 1815 279024032U, // ST2i16_POST 1816 151968U, // ST2i32 1817 295809440U, // ST2i32_POST 1818 156064U, // ST2i64 1819 329372064U, // ST2i64_POST 1820 160160U, // ST2i8 1821 262271392U, // ST2i8_POST 1822 37329U, // ST3Threev16b 1823 5546449U, // ST3Threev16b_POST 1824 53713U, // ST3Threev2d 1825 5562833U, // ST3Threev2d_POST 1826 61905U, // ST3Threev2s 1827 5833169U, // ST3Threev2s_POST 1828 70097U, // ST3Threev4h 1829 5841361U, // ST3Threev4h_POST 1830 78289U, // ST3Threev4s 1831 5587409U, // ST3Threev4s_POST 1832 86481U, // ST3Threev8b 1833 5857745U, // ST3Threev8b_POST 1834 94673U, // ST3Threev8h 1835 5603793U, // ST3Threev8h_POST 1836 147921U, // ST3i16 1837 346132945U, // ST3i16_POST 1838 152017U, // ST3i32 1839 362918353U, // ST3i32_POST 1840 156113U, // ST3i64 1841 379703761U, // ST3i64_POST 1842 160209U, // ST3i8 1843 396489169U, // ST3i8_POST 1844 37346U, // ST4Fourv16b 1845 3711458U, // ST4Fourv16b_POST 1846 53730U, // ST4Fourv2d 1847 3727842U, // ST4Fourv2d_POST 1848 61922U, // ST4Fourv2s 1849 3998178U, // ST4Fourv2s_POST 1850 70114U, // ST4Fourv4h 1851 4006370U, // ST4Fourv4h_POST 1852 78306U, // ST4Fourv4s 1853 3752418U, // ST4Fourv4s_POST 1854 86498U, // ST4Fourv8b 1855 4022754U, // ST4Fourv8b_POST 1856 94690U, // ST4Fourv8h 1857 3768802U, // ST4Fourv8h_POST 1858 147938U, // ST4i16 1859 295801314U, // ST4i16_POST 1860 152034U, // ST4i32 1861 329363938U, // ST4i32_POST 1862 156130U, // ST4i64 1863 413258210U, // ST4i64_POST 1864 160226U, // ST4i8 1865 279048674U, // ST4i8_POST 1866 26485317U, // STLRB 1867 26485814U, // STLRH 1868 26486716U, // STLRW 1869 26486716U, // STLRX 1870 17049437U, // STLXPW 1871 17049437U, // STLXPX 1872 553919101U, // STLXRB 1873 553919598U, // STLXRH 1874 553920528U, // STLXRW 1875 553920528U, // STLXRX 1876 553920285U, // STNPDi 1877 553920285U, // STNPQi 1878 553920285U, // STNPSi 1879 553920285U, // STNPWi 1880 553920285U, // STNPXi 1881 553920305U, // STPDi 1882 604276529U, // STPDpost 1883 604276529U, // STPDpre 1884 553920305U, // STPQi 1885 604276529U, // STPQpost 1886 604276529U, // STPQpre 1887 553920305U, // STPSi 1888 604276529U, // STPSpost 1889 604276529U, // STPSpre 1890 553920305U, // STPWi 1891 604276529U, // STPWpost 1892 604276529U, // STPWpre 1893 553920305U, // STPXi 1894 604276529U, // STPXpost 1895 604276529U, // STPXpre 1896 1150583379U, // STRBBpost 1897 76841555U, // STRBBpre 1898 26485331U, // STRBBroW 1899 26485331U, // STRBBroX 1900 26485331U, // STRBBui 1901 1150584806U, // STRBpost 1902 76842982U, // STRBpre 1903 26486758U, // STRBroW 1904 26486758U, // STRBroX 1905 26486758U, // STRBui 1906 1150584806U, // STRDpost 1907 76842982U, // STRDpre 1908 26486758U, // STRDroW 1909 26486758U, // STRDroX 1910 26486758U, // STRDui 1911 1150583876U, // STRHHpost 1912 76842052U, // STRHHpre 1913 26485828U, // STRHHroW 1914 26485828U, // STRHHroX 1915 26485828U, // STRHHui 1916 1150584806U, // STRHpost 1917 76842982U, // STRHpre 1918 26486758U, // STRHroW 1919 26486758U, // STRHroX 1920 26486758U, // STRHui 1921 1150584806U, // STRQpost 1922 76842982U, // STRQpre 1923 26486758U, // STRQroW 1924 26486758U, // STRQroX 1925 26486758U, // STRQui 1926 1150584806U, // STRSpost 1927 76842982U, // STRSpre 1928 26486758U, // STRSroW 1929 26486758U, // STRSroX 1930 26486758U, // STRSui 1931 1150584806U, // STRWpost 1932 76842982U, // STRWpre 1933 26486758U, // STRWroW 1934 26486758U, // STRWroX 1935 26486758U, // STRWui 1936 1150584806U, // STRXpost 1937 76842982U, // STRXpre 1938 26486758U, // STRXroW 1939 26486758U, // STRXroX 1940 26486758U, // STRXui 1941 26485337U, // STTRBi 1942 26485834U, // STTRHi 1943 26486763U, // STTRWi 1944 26486763U, // STTRXi 1945 26485351U, // STURBBi 1946 26486781U, // STURBi 1947 26486781U, // STURDi 1948 26485848U, // STURHHi 1949 26486781U, // STURHi 1950 26486781U, // STURQi 1951 26486781U, // STURSi 1952 26486781U, // STURWi 1953 26486781U, // STURXi 1954 17049444U, // STXPW 1955 17049444U, // STXPX 1956 553919109U, // STXRB 1957 553919606U, // STXRH 1958 553920535U, // STXRW 1959 553920535U, // STXRX 1960 537400855U, // SUBHNv2i64_v2i32 1961 571748625U, // SUBHNv2i64_v4i32 1962 1074796055U, // SUBHNv4i32_v4i16 1963 1108881681U, // SUBHNv4i32_v8i16 1964 1644179729U, // SUBHNv8i16_v16i8 1965 1612453399U, // SUBHNv8i16_v8i8 1966 17049650U, // SUBSWri 1967 0U, // SUBSWrr 1968 17049650U, // SUBSWrs 1969 17049650U, // SUBSWrx 1970 17049650U, // SUBSXri 1971 0U, // SUBSXrr 1972 17049650U, // SUBSXrs 1973 17049650U, // SUBSXrx 1974 17049650U, // SUBSXrx64 1975 17048238U, // SUBWri 1976 0U, // SUBWrr 1977 17048238U, // SUBWrs 1978 17048238U, // SUBWrx 1979 17048238U, // SUBXri 1980 0U, // SUBXrr 1981 17048238U, // SUBXrs 1982 17048238U, // SUBXrx 1983 17048238U, // SUBXrx64 1984 2147488430U, // SUBv16i8 1985 17048238U, // SUBv1i64 1986 2684883630U, // SUBv2i32 1987 537662126U, // SUBv2i64 1988 3222278830U, // SUBv4i16 1989 1075057326U, // SUBv4i32 1990 1612190382U, // SUBv8i16 1991 3759936174U, // SUBv8i8 1992 33567585U, // SUQADDv16i8 1993 604275553U, // SUQADDv1i16 1994 604275553U, // SUQADDv1i32 1995 604275553U, // SUQADDv1i64 1996 604275553U, // SUQADDv1i8 1997 1107833697U, // SUQADDv2i32 1998 1644966753U, // SUQADDv2i64 1999 2182099809U, // SUQADDv4i16 2000 2719232865U, // SUQADDv4i32 2001 3256365921U, // SUQADDv8i16 2002 3793498977U, // SUQADDv8i8 2003 21263U, // SVC 2004 17049022U, // SYSLxt 2005 419702938U, // SYSxt 2006 436212968U, // TBLv16i8Four 2007 436212968U, // TBLv16i8One 2008 436212968U, // TBLv16i8Three 2009 436212968U, // TBLv16i8Two 2010 4196144360U, // TBLv8i8Four 2011 4196144360U, // TBLv8i8One 2012 4196144360U, // TBLv8i8Three 2013 4196144360U, // TBLv8i8Two 2014 17050183U, // TBNZW 2015 17050183U, // TBNZX 2016 452999686U, // TBXv16i8Four 2017 452999686U, // TBXv16i8One 2018 452999686U, // TBXv16i8Three 2019 452999686U, // TBXv16i8Two 2020 4212931078U, // TBXv8i8Four 2021 4212931078U, // TBXv8i8One 2022 4212931078U, // TBXv8i8Three 2023 4212931078U, // TBXv8i8Two 2024 17050167U, // TBZW 2025 17050167U, // TBZX 2026 0U, // TCRETURNdi 2027 0U, // TCRETURNri 2028 2107995U, // TLSDESCCALL 2029 0U, // TLSDESC_BLR 2030 2147487770U, // TRN1v16i8 2031 2684882970U, // TRN1v2i32 2032 537661466U, // TRN1v2i64 2033 3222278170U, // TRN1v4i16 2034 1075056666U, // TRN1v4i32 2035 1612189722U, // TRN1v8i16 2036 3759935514U, // TRN1v8i8 2037 2147488072U, // TRN2v16i8 2038 2684883272U, // TRN2v2i32 2039 537661768U, // TRN2v2i64 2040 3222278472U, // TRN2v4i16 2041 1075056968U, // TRN2v4i32 2042 1612190024U, // TRN2v8i16 2043 3759935816U, // TRN2v8i8 2044 2182623338U, // UABALv16i8_v8i16 2045 2718708938U, // UABALv2i32_v2i64 2046 3256104138U, // UABALv4i16_v4i32 2047 1108095082U, // UABALv4i32_v2i64 2048 1645490282U, // UABALv8i16_v4i32 2049 3793237194U, // UABALv8i8_v8i16 2050 2181050868U, // UABAv16i8 2051 2718446068U, // UABAv2i32 2052 3255841268U, // UABAv4i16 2053 1108619764U, // UABAv4i32 2054 1645752820U, // UABAv8i16 2055 3793498612U, // UABAv8i8 2056 2149060772U, // UABDLv16i8_v8i16 2057 2685146386U, // UABDLv2i32_v2i64 2058 3222541586U, // UABDLv4i16_v4i32 2059 1074532516U, // UABDLv4i32_v2i64 2060 1611927716U, // UABDLv8i16_v4i32 2061 3759674642U, // UABDLv8i8_v8i16 2062 2147488544U, // UABDv16i8 2063 2684883744U, // UABDv2i32 2064 3222278944U, // UABDv4i16 2065 1075057440U, // UABDv4i32 2066 1612190496U, // UABDv8i16 2067 3759936288U, // UABDv8i8 2068 35141323U, // UADALPv16i8_v8i16 2069 1117533899U, // UADALPv2i32_v1i64 2070 2181576395U, // UADALPv4i16_v2i32 2071 2718709451U, // UADALPv4i32_v2i64 2072 3256104651U, // UADALPv8i16_v4i32 2073 3792713419U, // UADALPv8i8_v4i16 2074 1578715U, // UADDLPv16i8_v8i16 2075 1083971291U, // UADDLPv2i32_v1i64 2076 2148013787U, // UADDLPv4i16_v2i32 2077 2685146843U, // UADDLPv4i32_v2i64 2078 3222542043U, // UADDLPv8i16_v4i32 2079 3759150811U, // UADDLPv8i8_v4i16 2080 272708U, // UADDLVv16i8v 2081 2147756356U, // UADDLVv4i16v 2082 2684627268U, // UADDLVv4i32v 2083 3221498180U, // UADDLVv8i16v 2084 3758369092U, // UADDLVv8i8v 2085 2149060788U, // UADDLv16i8_v8i16 2086 2685146416U, // UADDLv2i32_v2i64 2087 3222541616U, // UADDLv4i16_v4i32 2088 1074532532U, // UADDLv4i32_v2i64 2089 1611927732U, // UADDLv8i16_v4i32 2090 3759674672U, // UADDLv8i8_v8i16 2091 1612190141U, // UADDWv16i8_v8i16 2092 537663943U, // UADDWv2i32_v2i64 2093 1075059143U, // UADDWv4i16_v4i32 2094 537661885U, // UADDWv4i32_v2i64 2095 1075057085U, // UADDWv8i16_v4i32 2096 1612192199U, // UADDWv8i8_v8i16 2097 17049067U, // UBFMWri 2098 17049067U, // UBFMXri 2099 17048524U, // UCVTFSWDri 2100 17048524U, // UCVTFSWSri 2101 17048524U, // UCVTFSXDri 2102 17048524U, // UCVTFSXSri 2103 553919436U, // UCVTFUWDri 2104 553919436U, // UCVTFUWSri 2105 553919436U, // UCVTFUXDri 2106 553919436U, // UCVTFUXSri 2107 17048524U, // UCVTFd 2108 17048524U, // UCVTFs 2109 553919436U, // UCVTFv1i32 2110 553919436U, // UCVTFv1i64 2111 1074271180U, // UCVTFv2f32 2112 1611404236U, // UCVTFv2f64 2113 2684883916U, // UCVTFv2i32_shift 2114 537662412U, // UCVTFv2i64_shift 2115 2685670348U, // UCVTFv4f32 2116 1075057612U, // UCVTFv4i32_shift 2117 17049910U, // UDIVWr 2118 17049910U, // UDIVXr 2119 17049910U, // UDIV_IntWr 2120 17049910U, // UDIV_IntXr 2121 2147488579U, // UHADDv16i8 2122 2684883779U, // UHADDv2i32 2123 3222278979U, // UHADDv4i16 2124 1075057475U, // UHADDv4i32 2125 1612190531U, // UHADDv8i16 2126 3759936323U, // UHADDv8i8 2127 2147488442U, // UHSUBv16i8 2128 2684883642U, // UHSUBv2i32 2129 3222278842U, // UHSUBv4i16 2130 1075057338U, // UHSUBv4i32 2131 1612190394U, // UHSUBv8i16 2132 3759936186U, // UHSUBv8i8 2133 17048865U, // UMADDLrrr 2134 2147489616U, // UMAXPv16i8 2135 2684884816U, // UMAXPv2i32 2136 3222280016U, // UMAXPv4i16 2137 1075058512U, // UMAXPv4i32 2138 1612191568U, // UMAXPv8i16 2139 3759937360U, // UMAXPv8i8 2140 272794U, // UMAXVv16i8v 2141 2147756442U, // UMAXVv4i16v 2142 2684627354U, // UMAXVv4i32v 2143 3221498266U, // UMAXVv8i16v 2144 3758369178U, // UMAXVv8i8v 2145 2147490304U, // UMAXv16i8 2146 2684885504U, // UMAXv2i32 2147 3222280704U, // UMAXv4i16 2148 1075059200U, // UMAXv4i32 2149 1612192256U, // UMAXv8i16 2150 3759938048U, // UMAXv8i8 2151 2147489558U, // UMINPv16i8 2152 2684884758U, // UMINPv2i32 2153 3222279958U, // UMINPv4i16 2154 1075058454U, // UMINPv4i32 2155 1612191510U, // UMINPv8i16 2156 3759937302U, // UMINPv8i8 2157 272748U, // UMINVv16i8v 2158 2147756396U, // UMINVv4i16v 2159 2684627308U, // UMINVv4i32v 2160 3221498220U, // UMINVv8i16v 2161 3758369132U, // UMINVv8i8v 2162 2147489330U, // UMINv16i8 2163 2684884530U, // UMINv2i32 2164 3222279730U, // UMINv4i16 2165 1075058226U, // UMINv4i32 2166 1612191282U, // UMINv8i16 2167 3759937074U, // UMINv8i8 2168 2182623364U, // UMLALv16i8_v8i16 2169 2718708961U, // UMLALv2i32_indexed 2170 2718708961U, // UMLALv2i32_v2i64 2171 3256104161U, // UMLALv4i16_indexed 2172 3256104161U, // UMLALv4i16_v4i32 2173 1108095108U, // UMLALv4i32_indexed 2174 1108095108U, // UMLALv4i32_v2i64 2175 1645490308U, // UMLALv8i16_indexed 2176 1645490308U, // UMLALv8i16_v4i32 2177 3793237217U, // UMLALv8i8_v8i16 2178 2182623488U, // UMLSLv16i8_v8i16 2179 2718709175U, // UMLSLv2i32_indexed 2180 2718709175U, // UMLSLv2i32_v2i64 2181 3256104375U, // UMLSLv4i16_indexed 2182 3256104375U, // UMLSLv4i16_v4i32 2183 1108095232U, // UMLSLv4i32_indexed 2184 1108095232U, // UMLSLv4i32_v2i64 2185 1645490432U, // UMLSLv8i16_indexed 2186 1645490432U, // UMLSLv8i16_v4i32 2187 3793237431U, // UMLSLv8i8_v8i16 2188 272774U, // UMOVvi16 2189 537143686U, // UMOVvi32 2190 1074014598U, // UMOVvi64 2191 1610885510U, // UMOVvi8 2192 17048821U, // UMSUBLrrr 2193 17048610U, // UMULHrr 2194 2149060838U, // UMULLv16i8_v8i16 2195 2685146523U, // UMULLv2i32_indexed 2196 2685146523U, // UMULLv2i32_v2i64 2197 3222541723U, // UMULLv4i16_indexed 2198 3222541723U, // UMULLv4i16_v4i32 2199 1074532582U, // UMULLv4i32_indexed 2200 1074532582U, // UMULLv4i32_v2i64 2201 1611927782U, // UMULLv8i16_indexed 2202 1611927782U, // UMULLv8i16_v4i32 2203 3759674779U, // UMULLv8i8_v8i16 2204 2147488610U, // UQADDv16i8 2205 17048418U, // UQADDv1i16 2206 17048418U, // UQADDv1i32 2207 17048418U, // UQADDv1i64 2208 17048418U, // UQADDv1i8 2209 2684883810U, // UQADDv2i32 2210 537662306U, // UQADDv2i64 2211 3222279010U, // UQADDv4i16 2212 1075057506U, // UQADDv4i32 2213 1612190562U, // UQADDv8i16 2214 3759936354U, // UQADDv8i8 2215 2147489108U, // UQRSHLv16i8 2216 17048916U, // UQRSHLv1i16 2217 17048916U, // UQRSHLv1i32 2218 17048916U, // UQRSHLv1i64 2219 17048916U, // UQRSHLv1i8 2220 2684884308U, // UQRSHLv2i32 2221 537662804U, // UQRSHLv2i64 2222 3222279508U, // UQRSHLv4i16 2223 1075058004U, // UQRSHLv4i32 2224 1612191060U, // UQRSHLv8i16 2225 3759936852U, // UQRSHLv8i8 2226 17049180U, // UQRSHRNb 2227 17049180U, // UQRSHRNh 2228 17049180U, // UQRSHRNs 2229 1644179774U, // UQRSHRNv16i8_shift 2230 537400924U, // UQRSHRNv2i32_shift 2231 1074796124U, // UQRSHRNv4i16_shift 2232 571748670U, // UQRSHRNv4i32_shift 2233 1108881726U, // UQRSHRNv8i16_shift 2234 1612453468U, // UQRSHRNv8i8_shift 2235 17048901U, // UQSHLb 2236 17048901U, // UQSHLd 2237 17048901U, // UQSHLh 2238 17048901U, // UQSHLs 2239 2147489093U, // UQSHLv16i8 2240 2147489093U, // UQSHLv16i8_shift 2241 17048901U, // UQSHLv1i16 2242 17048901U, // UQSHLv1i32 2243 17048901U, // UQSHLv1i64 2244 17048901U, // UQSHLv1i8 2245 2684884293U, // UQSHLv2i32 2246 2684884293U, // UQSHLv2i32_shift 2247 537662789U, // UQSHLv2i64 2248 537662789U, // UQSHLv2i64_shift 2249 3222279493U, // UQSHLv4i16 2250 3222279493U, // UQSHLv4i16_shift 2251 1075057989U, // UQSHLv4i32 2252 1075057989U, // UQSHLv4i32_shift 2253 1612191045U, // UQSHLv8i16 2254 1612191045U, // UQSHLv8i16_shift 2255 3759936837U, // UQSHLv8i8 2256 3759936837U, // UQSHLv8i8_shift 2257 17049163U, // UQSHRNb 2258 17049163U, // UQSHRNh 2259 17049163U, // UQSHRNs 2260 1644179755U, // UQSHRNv16i8_shift 2261 537400907U, // UQSHRNv2i32_shift 2262 1074796107U, // UQSHRNv4i16_shift 2263 571748651U, // UQSHRNv4i32_shift 2264 1108881707U, // UQSHRNv8i16_shift 2265 1612453451U, // UQSHRNv8i8_shift 2266 2147488471U, // UQSUBv16i8 2267 17048279U, // UQSUBv1i16 2268 17048279U, // UQSUBv1i32 2269 17048279U, // UQSUBv1i64 2270 17048279U, // UQSUBv1i8 2271 2684883671U, // UQSUBv2i32 2272 537662167U, // UQSUBv2i64 2273 3222278871U, // UQSUBv4i16 2274 1075057367U, // UQSUBv4i32 2275 1612190423U, // UQSUBv8i16 2276 3759936215U, // UQSUBv8i8 2277 3254792542U, // UQXTNv16i8 2278 553920128U, // UQXTNv1i16 2279 553920128U, // UQXTNv1i32 2280 553920128U, // UQXTNv1i8 2281 1611142784U, // UQXTNv2i32 2282 2685408896U, // UQXTNv4i16 2283 1645490526U, // UQXTNv4i32 2284 2719494494U, // UQXTNv8i16 2285 3223066240U, // UQXTNv8i8 2286 1074271121U, // URECPEv2i32 2287 2685670289U, // URECPEv4i32 2288 2147488564U, // URHADDv16i8 2289 2684883764U, // URHADDv2i32 2290 3222278964U, // URHADDv4i16 2291 1075057460U, // URHADDv4i32 2292 1612190516U, // URHADDv8i16 2293 3759936308U, // URHADDv8i8 2294 2147489123U, // URSHLv16i8 2295 17048931U, // URSHLv1i64 2296 2684884323U, // URSHLv2i32 2297 537662819U, // URSHLv2i64 2298 3222279523U, // URSHLv4i16 2299 1075058019U, // URSHLv4i32 2300 1612191075U, // URSHLv8i16 2301 3759936867U, // URSHLv8i8 2302 17049508U, // URSHRd 2303 2147489700U, // URSHRv16i8_shift 2304 2684884900U, // URSHRv2i32_shift 2305 537663396U, // URSHRv2i64_shift 2306 3222280100U, // URSHRv4i16_shift 2307 1075058596U, // URSHRv4i32_shift 2308 1612191652U, // URSHRv8i16_shift 2309 3759937444U, // URSHRv8i8_shift 2310 1074271159U, // URSQRTEv2i32 2311 2685670327U, // URSQRTEv4i32 2312 67404295U, // URSRAd 2313 2181050887U, // URSRAv16i8_shift 2314 2718446087U, // URSRAv2i32_shift 2315 571224583U, // URSRAv2i64_shift 2316 3255841287U, // URSRAv4i16_shift 2317 1108619783U, // URSRAv4i32_shift 2318 1645752839U, // URSRAv8i16_shift 2319 3793498631U, // URSRAv8i8_shift 2320 2149060804U, // USHLLv16i8_shift 2321 2685146493U, // USHLLv2i32_shift 2322 3222541693U, // USHLLv4i16_shift 2323 1074532548U, // USHLLv4i32_shift 2324 1611927748U, // USHLLv8i16_shift 2325 3759674749U, // USHLLv8i8_shift 2326 2147489136U, // USHLv16i8 2327 17048944U, // USHLv1i64 2328 2684884336U, // USHLv2i32 2329 537662832U, // USHLv2i64 2330 3222279536U, // USHLv4i16 2331 1075058032U, // USHLv4i32 2332 1612191088U, // USHLv8i16 2333 3759936880U, // USHLv8i8 2334 17049521U, // USHRd 2335 2147489713U, // USHRv16i8_shift 2336 2684884913U, // USHRv2i32_shift 2337 537663409U, // USHRv2i64_shift 2338 3222280113U, // USHRv4i16_shift 2339 1075058609U, // USHRv4i32_shift 2340 1612191665U, // USHRv8i16_shift 2341 3759937457U, // USHRv8i8_shift 2342 33567577U, // USQADDv16i8 2343 604275545U, // USQADDv1i16 2344 604275545U, // USQADDv1i32 2345 604275545U, // USQADDv1i64 2346 604275545U, // USQADDv1i8 2347 1107833689U, // USQADDv2i32 2348 1644966745U, // USQADDv2i64 2349 2182099801U, // USQADDv4i16 2350 2719232857U, // USQADDv4i32 2351 3256365913U, // USQADDv8i16 2352 3793498969U, // USQADDv8i8 2353 67404308U, // USRAd 2354 2181050900U, // USRAv16i8_shift 2355 2718446100U, // USRAv2i32_shift 2356 571224596U, // USRAv2i64_shift 2357 3255841300U, // USRAv4i16_shift 2358 1108619796U, // USRAv4i32_shift 2359 1645752852U, // USRAv8i16_shift 2360 3793498644U, // USRAv8i8_shift 2361 2149060756U, // USUBLv16i8_v8i16 2362 2685146372U, // USUBLv2i32_v2i64 2363 3222541572U, // USUBLv4i16_v4i32 2364 1074532500U, // USUBLv4i32_v2i64 2365 1611927700U, // USUBLv8i16_v4i32 2366 3759674628U, // USUBLv8i8_v8i16 2367 1612190125U, // USUBWv16i8_v8i16 2368 537663920U, // USUBWv2i32_v2i64 2369 1075059120U, // USUBWv4i16_v4i32 2370 537661869U, // USUBWv4i32_v2i64 2371 1075057069U, // USUBWv8i16_v4i32 2372 1612192176U, // USUBWv8i8_v8i16 2373 2147487782U, // UZP1v16i8 2374 2684882982U, // UZP1v2i32 2375 537661478U, // UZP1v2i64 2376 3222278182U, // UZP1v4i16 2377 1075056678U, // UZP1v4i32 2378 1612189734U, // UZP1v8i16 2379 3759935526U, // UZP1v8i8 2380 2147488147U, // UZP2v16i8 2381 2684883347U, // UZP2v2i32 2382 537661843U, // UZP2v2i64 2383 3222278547U, // UZP2v4i16 2384 1075057043U, // UZP2v4i32 2385 1612190099U, // UZP2v8i16 2386 3759935891U, // UZP2v8i8 2387 3254792536U, // XTNv16i8 2388 1611142779U, // XTNv2i32 2389 2685408891U, // XTNv4i16 2390 1645490520U, // XTNv4i32 2391 2719494488U, // XTNv8i16 2392 3223066235U, // XTNv8i8 2393 2147487776U, // ZIP1v16i8 2394 2684882976U, // ZIP1v2i32 2395 537661472U, // ZIP1v2i64 2396 3222278176U, // ZIP1v4i16 2397 1075056672U, // ZIP1v4i32 2398 1612189728U, // ZIP1v8i16 2399 3759935520U, // ZIP1v8i8 2400 2147488141U, // ZIP2v16i8 2401 2684883341U, // ZIP2v2i32 2402 537661837U, // ZIP2v2i64 2403 3222278541U, // ZIP2v4i16 2404 1075057037U, // ZIP2v4i32 2405 1612190093U, // ZIP2v8i16 2406 3759935885U, // ZIP2v8i8 2407 0U 2408 }; 2409 2410 static const uint32_t OpInfo2[] = { 2411 0U, // PHI 2412 0U, // INLINEASM 2413 0U, // CFI_INSTRUCTION 2414 0U, // EH_LABEL 2415 0U, // GC_LABEL 2416 0U, // KILL 2417 0U, // EXTRACT_SUBREG 2418 0U, // INSERT_SUBREG 2419 0U, // IMPLICIT_DEF 2420 0U, // SUBREG_TO_REG 2421 0U, // COPY_TO_REGCLASS 2422 0U, // DBG_VALUE 2423 0U, // REG_SEQUENCE 2424 0U, // COPY 2425 0U, // BUNDLE 2426 0U, // LIFETIME_START 2427 0U, // LIFETIME_END 2428 0U, // STACKMAP 2429 0U, // PATCHPOINT 2430 0U, // LOAD_STACK_GUARD 2431 0U, // STATEPOINT 2432 0U, // FRAME_ALLOC 2433 0U, // ABSv16i8 2434 0U, // ABSv1i64 2435 0U, // ABSv2i32 2436 0U, // ABSv2i64 2437 0U, // ABSv4i16 2438 0U, // ABSv4i32 2439 0U, // ABSv8i16 2440 0U, // ABSv8i8 2441 1U, // ADCSWr 2442 1U, // ADCSXr 2443 1U, // ADCWr 2444 1U, // ADCXr 2445 265U, // ADDHNv2i64_v2i32 2446 273U, // ADDHNv2i64_v4i32 2447 521U, // ADDHNv4i32_v4i16 2448 529U, // ADDHNv4i32_v8i16 2449 785U, // ADDHNv8i16_v16i8 2450 777U, // ADDHNv8i16_v8i8 2451 1033U, // ADDPv16i8 2452 1289U, // ADDPv2i32 2453 265U, // ADDPv2i64 2454 0U, // ADDPv2i64p 2455 1545U, // ADDPv4i16 2456 521U, // ADDPv4i32 2457 777U, // ADDPv8i16 2458 1801U, // ADDPv8i8 2459 25U, // ADDSWri 2460 0U, // ADDSWrr 2461 33U, // ADDSWrs 2462 41U, // ADDSWrx 2463 25U, // ADDSXri 2464 0U, // ADDSXrr 2465 33U, // ADDSXrs 2466 41U, // ADDSXrx 2467 2049U, // ADDSXrx64 2468 0U, // ADDVv16i8v 2469 0U, // ADDVv4i16v 2470 0U, // ADDVv4i32v 2471 0U, // ADDVv8i16v 2472 0U, // ADDVv8i8v 2473 25U, // ADDWri 2474 0U, // ADDWrr 2475 33U, // ADDWrs 2476 41U, // ADDWrx 2477 25U, // ADDXri 2478 0U, // ADDXrr 2479 33U, // ADDXrs 2480 41U, // ADDXrx 2481 2049U, // ADDXrx64 2482 1033U, // ADDv16i8 2483 1U, // ADDv1i64 2484 1289U, // ADDv2i32 2485 265U, // ADDv2i64 2486 1545U, // ADDv4i16 2487 521U, // ADDv4i32 2488 777U, // ADDv8i16 2489 1801U, // ADDv8i8 2490 0U, // ADJCALLSTACKDOWN 2491 0U, // ADJCALLSTACKUP 2492 0U, // ADR 2493 0U, // ADRP 2494 0U, // AESDrr 2495 0U, // AESErr 2496 0U, // AESIMCrr 2497 0U, // AESMCrr 2498 49U, // ANDSWri 2499 0U, // ANDSWrr 2500 33U, // ANDSWrs 2501 57U, // ANDSXri 2502 0U, // ANDSXrr 2503 33U, // ANDSXrs 2504 49U, // ANDWri 2505 0U, // ANDWrr 2506 33U, // ANDWrs 2507 57U, // ANDXri 2508 0U, // ANDXrr 2509 33U, // ANDXrs 2510 1033U, // ANDv16i8 2511 1801U, // ANDv8i8 2512 1U, // ASRVWr 2513 1U, // ASRVXr 2514 0U, // B 2515 2369U, // BFMWri 2516 2369U, // BFMXri 2517 0U, // BICSWrr 2518 33U, // BICSWrs 2519 0U, // BICSXrr 2520 33U, // BICSXrs 2521 0U, // BICWrr 2522 33U, // BICWrs 2523 0U, // BICXrr 2524 33U, // BICXrs 2525 1033U, // BICv16i8 2526 0U, // BICv2i32 2527 0U, // BICv4i16 2528 0U, // BICv4i32 2529 0U, // BICv8i16 2530 1801U, // BICv8i8 2531 1033U, // BIFv16i8 2532 1801U, // BIFv8i8 2533 1041U, // BITv16i8 2534 1809U, // BITv8i8 2535 0U, // BL 2536 0U, // BLR 2537 0U, // BR 2538 0U, // BRK 2539 1041U, // BSLv16i8 2540 1809U, // BSLv8i8 2541 0U, // Bcc 2542 0U, // CBNZW 2543 0U, // CBNZX 2544 0U, // CBZW 2545 0U, // CBZX 2546 10497U, // CCMNWi 2547 10497U, // CCMNWr 2548 10497U, // CCMNXi 2549 10497U, // CCMNXr 2550 10497U, // CCMPWi 2551 10497U, // CCMPWr 2552 10497U, // CCMPXi 2553 10497U, // CCMPXr 2554 0U, // CLREX 2555 0U, // CLSWr 2556 0U, // CLSXr 2557 0U, // CLSv16i8 2558 0U, // CLSv2i32 2559 0U, // CLSv4i16 2560 0U, // CLSv4i32 2561 0U, // CLSv8i16 2562 0U, // CLSv8i8 2563 0U, // CLZWr 2564 0U, // CLZXr 2565 0U, // CLZv16i8 2566 0U, // CLZv2i32 2567 0U, // CLZv4i16 2568 0U, // CLZv4i32 2569 0U, // CLZv8i16 2570 0U, // CLZv8i8 2571 1033U, // CMEQv16i8 2572 2U, // CMEQv16i8rz 2573 1U, // CMEQv1i64 2574 2U, // CMEQv1i64rz 2575 1289U, // CMEQv2i32 2576 2U, // CMEQv2i32rz 2577 265U, // CMEQv2i64 2578 2U, // CMEQv2i64rz 2579 1545U, // CMEQv4i16 2580 2U, // CMEQv4i16rz 2581 521U, // CMEQv4i32 2582 2U, // CMEQv4i32rz 2583 777U, // CMEQv8i16 2584 2U, // CMEQv8i16rz 2585 1801U, // CMEQv8i8 2586 2U, // CMEQv8i8rz 2587 1033U, // CMGEv16i8 2588 2U, // CMGEv16i8rz 2589 1U, // CMGEv1i64 2590 2U, // CMGEv1i64rz 2591 1289U, // CMGEv2i32 2592 2U, // CMGEv2i32rz 2593 265U, // CMGEv2i64 2594 2U, // CMGEv2i64rz 2595 1545U, // CMGEv4i16 2596 2U, // CMGEv4i16rz 2597 521U, // CMGEv4i32 2598 2U, // CMGEv4i32rz 2599 777U, // CMGEv8i16 2600 2U, // CMGEv8i16rz 2601 1801U, // CMGEv8i8 2602 2U, // CMGEv8i8rz 2603 1033U, // CMGTv16i8 2604 2U, // CMGTv16i8rz 2605 1U, // CMGTv1i64 2606 2U, // CMGTv1i64rz 2607 1289U, // CMGTv2i32 2608 2U, // CMGTv2i32rz 2609 265U, // CMGTv2i64 2610 2U, // CMGTv2i64rz 2611 1545U, // CMGTv4i16 2612 2U, // CMGTv4i16rz 2613 521U, // CMGTv4i32 2614 2U, // CMGTv4i32rz 2615 777U, // CMGTv8i16 2616 2U, // CMGTv8i16rz 2617 1801U, // CMGTv8i8 2618 2U, // CMGTv8i8rz 2619 1033U, // CMHIv16i8 2620 1U, // CMHIv1i64 2621 1289U, // CMHIv2i32 2622 265U, // CMHIv2i64 2623 1545U, // CMHIv4i16 2624 521U, // CMHIv4i32 2625 777U, // CMHIv8i16 2626 1801U, // CMHIv8i8 2627 1033U, // CMHSv16i8 2628 1U, // CMHSv1i64 2629 1289U, // CMHSv2i32 2630 265U, // CMHSv2i64 2631 1545U, // CMHSv4i16 2632 521U, // CMHSv4i32 2633 777U, // CMHSv8i16 2634 1801U, // CMHSv8i8 2635 2U, // CMLEv16i8rz 2636 2U, // CMLEv1i64rz 2637 2U, // CMLEv2i32rz 2638 2U, // CMLEv2i64rz 2639 2U, // CMLEv4i16rz 2640 2U, // CMLEv4i32rz 2641 2U, // CMLEv8i16rz 2642 2U, // CMLEv8i8rz 2643 2U, // CMLTv16i8rz 2644 2U, // CMLTv1i64rz 2645 2U, // CMLTv2i32rz 2646 2U, // CMLTv2i64rz 2647 2U, // CMLTv4i16rz 2648 2U, // CMLTv4i32rz 2649 2U, // CMLTv8i16rz 2650 2U, // CMLTv8i8rz 2651 1033U, // CMTSTv16i8 2652 1U, // CMTSTv1i64 2653 1289U, // CMTSTv2i32 2654 265U, // CMTSTv2i64 2655 1545U, // CMTSTv4i16 2656 521U, // CMTSTv4i32 2657 777U, // CMTSTv8i16 2658 1801U, // CMTSTv8i8 2659 0U, // CNTv16i8 2660 0U, // CNTv8i8 2661 75U, // CPYi16 2662 75U, // CPYi32 2663 75U, // CPYi64 2664 75U, // CPYi8 2665 1U, // CRC32Brr 2666 1U, // CRC32CBrr 2667 1U, // CRC32CHrr 2668 1U, // CRC32CWrr 2669 1U, // CRC32CXrr 2670 1U, // CRC32Hrr 2671 1U, // CRC32Wrr 2672 1U, // CRC32Xrr 2673 10497U, // CSELWr 2674 10497U, // CSELXr 2675 10497U, // CSINCWr 2676 10497U, // CSINCXr 2677 10497U, // CSINVWr 2678 10497U, // CSINVXr 2679 10497U, // CSNEGWr 2680 10497U, // CSNEGXr 2681 0U, // DCPS1 2682 0U, // DCPS2 2683 0U, // DCPS3 2684 0U, // DMB 2685 0U, // DRPS 2686 0U, // DSB 2687 0U, // DUPv16i8gpr 2688 75U, // DUPv16i8lane 2689 0U, // DUPv2i32gpr 2690 75U, // DUPv2i32lane 2691 0U, // DUPv2i64gpr 2692 75U, // DUPv2i64lane 2693 0U, // DUPv4i16gpr 2694 75U, // DUPv4i16lane 2695 0U, // DUPv4i32gpr 2696 75U, // DUPv4i32lane 2697 0U, // DUPv8i16gpr 2698 75U, // DUPv8i16lane 2699 0U, // DUPv8i8gpr 2700 75U, // DUPv8i8lane 2701 0U, // EONWrr 2702 33U, // EONWrs 2703 0U, // EONXrr 2704 33U, // EONXrs 2705 49U, // EORWri 2706 0U, // EORWrr 2707 33U, // EORWrs 2708 57U, // EORXri 2709 0U, // EORXrr 2710 33U, // EORXrs 2711 1033U, // EORv16i8 2712 1801U, // EORv8i8 2713 0U, // ERET 2714 18689U, // EXTRWrri 2715 18689U, // EXTRXrri 2716 2569U, // EXTv16i8 2717 2825U, // EXTv8i8 2718 0U, // F128CSEL 2719 1U, // FABD32 2720 1U, // FABD64 2721 1289U, // FABDv2f32 2722 265U, // FABDv2f64 2723 521U, // FABDv4f32 2724 0U, // FABSDr 2725 0U, // FABSSr 2726 0U, // FABSv2f32 2727 0U, // FABSv2f64 2728 0U, // FABSv4f32 2729 1U, // FACGE32 2730 1U, // FACGE64 2731 1289U, // FACGEv2f32 2732 265U, // FACGEv2f64 2733 521U, // FACGEv4f32 2734 1U, // FACGT32 2735 1U, // FACGT64 2736 1289U, // FACGTv2f32 2737 265U, // FACGTv2f64 2738 521U, // FACGTv4f32 2739 1U, // FADDDrr 2740 1289U, // FADDPv2f32 2741 265U, // FADDPv2f64 2742 0U, // FADDPv2i32p 2743 0U, // FADDPv2i64p 2744 521U, // FADDPv4f32 2745 1U, // FADDSrr 2746 1289U, // FADDv2f32 2747 265U, // FADDv2f64 2748 521U, // FADDv4f32 2749 10497U, // FCCMPDrr 2750 10497U, // FCCMPEDrr 2751 10497U, // FCCMPESrr 2752 10497U, // FCCMPSrr 2753 1U, // FCMEQ32 2754 1U, // FCMEQ64 2755 3U, // FCMEQv1i32rz 2756 3U, // FCMEQv1i64rz 2757 1289U, // FCMEQv2f32 2758 265U, // FCMEQv2f64 2759 3U, // FCMEQv2i32rz 2760 3U, // FCMEQv2i64rz 2761 521U, // FCMEQv4f32 2762 3U, // FCMEQv4i32rz 2763 1U, // FCMGE32 2764 1U, // FCMGE64 2765 3U, // FCMGEv1i32rz 2766 3U, // FCMGEv1i64rz 2767 1289U, // FCMGEv2f32 2768 265U, // FCMGEv2f64 2769 3U, // FCMGEv2i32rz 2770 3U, // FCMGEv2i64rz 2771 521U, // FCMGEv4f32 2772 3U, // FCMGEv4i32rz 2773 1U, // FCMGT32 2774 1U, // FCMGT64 2775 3U, // FCMGTv1i32rz 2776 3U, // FCMGTv1i64rz 2777 1289U, // FCMGTv2f32 2778 265U, // FCMGTv2f64 2779 3U, // FCMGTv2i32rz 2780 3U, // FCMGTv2i64rz 2781 521U, // FCMGTv4f32 2782 3U, // FCMGTv4i32rz 2783 3U, // FCMLEv1i32rz 2784 3U, // FCMLEv1i64rz 2785 3U, // FCMLEv2i32rz 2786 3U, // FCMLEv2i64rz 2787 3U, // FCMLEv4i32rz 2788 3U, // FCMLTv1i32rz 2789 3U, // FCMLTv1i64rz 2790 3U, // FCMLTv2i32rz 2791 3U, // FCMLTv2i64rz 2792 3U, // FCMLTv4i32rz 2793 0U, // FCMPDri 2794 0U, // FCMPDrr 2795 0U, // FCMPEDri 2796 0U, // FCMPEDrr 2797 0U, // FCMPESri 2798 0U, // FCMPESrr 2799 0U, // FCMPSri 2800 0U, // FCMPSrr 2801 10497U, // FCSELDrrr 2802 10497U, // FCSELSrrr 2803 0U, // FCVTASUWDr 2804 0U, // FCVTASUWSr 2805 0U, // FCVTASUXDr 2806 0U, // FCVTASUXSr 2807 0U, // FCVTASv1i32 2808 0U, // FCVTASv1i64 2809 0U, // FCVTASv2f32 2810 0U, // FCVTASv2f64 2811 0U, // FCVTASv4f32 2812 0U, // FCVTAUUWDr 2813 0U, // FCVTAUUWSr 2814 0U, // FCVTAUUXDr 2815 0U, // FCVTAUUXSr 2816 0U, // FCVTAUv1i32 2817 0U, // FCVTAUv1i64 2818 0U, // FCVTAUv2f32 2819 0U, // FCVTAUv2f64 2820 0U, // FCVTAUv4f32 2821 0U, // FCVTDHr 2822 0U, // FCVTDSr 2823 0U, // FCVTHDr 2824 0U, // FCVTHSr 2825 0U, // FCVTLv2i32 2826 0U, // FCVTLv4i16 2827 0U, // FCVTLv4i32 2828 0U, // FCVTLv8i16 2829 0U, // FCVTMSUWDr 2830 0U, // FCVTMSUWSr 2831 0U, // FCVTMSUXDr 2832 0U, // FCVTMSUXSr 2833 0U, // FCVTMSv1i32 2834 0U, // FCVTMSv1i64 2835 0U, // FCVTMSv2f32 2836 0U, // FCVTMSv2f64 2837 0U, // FCVTMSv4f32 2838 0U, // FCVTMUUWDr 2839 0U, // FCVTMUUWSr 2840 0U, // FCVTMUUXDr 2841 0U, // FCVTMUUXSr 2842 0U, // FCVTMUv1i32 2843 0U, // FCVTMUv1i64 2844 0U, // FCVTMUv2f32 2845 0U, // FCVTMUv2f64 2846 0U, // FCVTMUv4f32 2847 0U, // FCVTNSUWDr 2848 0U, // FCVTNSUWSr 2849 0U, // FCVTNSUXDr 2850 0U, // FCVTNSUXSr 2851 0U, // FCVTNSv1i32 2852 0U, // FCVTNSv1i64 2853 0U, // FCVTNSv2f32 2854 0U, // FCVTNSv2f64 2855 0U, // FCVTNSv4f32 2856 0U, // FCVTNUUWDr 2857 0U, // FCVTNUUWSr 2858 0U, // FCVTNUUXDr 2859 0U, // FCVTNUUXSr 2860 0U, // FCVTNUv1i32 2861 0U, // FCVTNUv1i64 2862 0U, // FCVTNUv2f32 2863 0U, // FCVTNUv2f64 2864 0U, // FCVTNUv4f32 2865 0U, // FCVTNv2i32 2866 0U, // FCVTNv4i16 2867 0U, // FCVTNv4i32 2868 0U, // FCVTNv8i16 2869 0U, // FCVTPSUWDr 2870 0U, // FCVTPSUWSr 2871 0U, // FCVTPSUXDr 2872 0U, // FCVTPSUXSr 2873 0U, // FCVTPSv1i32 2874 0U, // FCVTPSv1i64 2875 0U, // FCVTPSv2f32 2876 0U, // FCVTPSv2f64 2877 0U, // FCVTPSv4f32 2878 0U, // FCVTPUUWDr 2879 0U, // FCVTPUUWSr 2880 0U, // FCVTPUUXDr 2881 0U, // FCVTPUUXSr 2882 0U, // FCVTPUv1i32 2883 0U, // FCVTPUv1i64 2884 0U, // FCVTPUv2f32 2885 0U, // FCVTPUv2f64 2886 0U, // FCVTPUv4f32 2887 0U, // FCVTSDr 2888 0U, // FCVTSHr 2889 0U, // FCVTXNv1i64 2890 0U, // FCVTXNv2f32 2891 0U, // FCVTXNv4f32 2892 1U, // FCVTZSSWDri 2893 1U, // FCVTZSSWSri 2894 1U, // FCVTZSSXDri 2895 1U, // FCVTZSSXSri 2896 0U, // FCVTZSUWDr 2897 0U, // FCVTZSUWSr 2898 0U, // FCVTZSUXDr 2899 0U, // FCVTZSUXSr 2900 1U, // FCVTZS_IntSWDri 2901 1U, // FCVTZS_IntSWSri 2902 1U, // FCVTZS_IntSXDri 2903 1U, // FCVTZS_IntSXSri 2904 0U, // FCVTZS_IntUWDr 2905 0U, // FCVTZS_IntUWSr 2906 0U, // FCVTZS_IntUXDr 2907 0U, // FCVTZS_IntUXSr 2908 0U, // FCVTZS_Intv2f32 2909 0U, // FCVTZS_Intv2f64 2910 0U, // FCVTZS_Intv4f32 2911 1U, // FCVTZSd 2912 1U, // FCVTZSs 2913 0U, // FCVTZSv1i32 2914 0U, // FCVTZSv1i64 2915 0U, // FCVTZSv2f32 2916 0U, // FCVTZSv2f64 2917 1U, // FCVTZSv2i32_shift 2918 1U, // FCVTZSv2i64_shift 2919 0U, // FCVTZSv4f32 2920 1U, // FCVTZSv4i32_shift 2921 1U, // FCVTZUSWDri 2922 1U, // FCVTZUSWSri 2923 1U, // FCVTZUSXDri 2924 1U, // FCVTZUSXSri 2925 0U, // FCVTZUUWDr 2926 0U, // FCVTZUUWSr 2927 0U, // FCVTZUUXDr 2928 0U, // FCVTZUUXSr 2929 1U, // FCVTZU_IntSWDri 2930 1U, // FCVTZU_IntSWSri 2931 1U, // FCVTZU_IntSXDri 2932 1U, // FCVTZU_IntSXSri 2933 0U, // FCVTZU_IntUWDr 2934 0U, // FCVTZU_IntUWSr 2935 0U, // FCVTZU_IntUXDr 2936 0U, // FCVTZU_IntUXSr 2937 0U, // FCVTZU_Intv2f32 2938 0U, // FCVTZU_Intv2f64 2939 0U, // FCVTZU_Intv4f32 2940 1U, // FCVTZUd 2941 1U, // FCVTZUs 2942 0U, // FCVTZUv1i32 2943 0U, // FCVTZUv1i64 2944 0U, // FCVTZUv2f32 2945 0U, // FCVTZUv2f64 2946 1U, // FCVTZUv2i32_shift 2947 1U, // FCVTZUv2i64_shift 2948 0U, // FCVTZUv4f32 2949 1U, // FCVTZUv4i32_shift 2950 1U, // FDIVDrr 2951 1U, // FDIVSrr 2952 1289U, // FDIVv2f32 2953 265U, // FDIVv2f64 2954 521U, // FDIVv4f32 2955 18689U, // FMADDDrrr 2956 18689U, // FMADDSrrr 2957 1U, // FMAXDrr 2958 1U, // FMAXNMDrr 2959 1289U, // FMAXNMPv2f32 2960 265U, // FMAXNMPv2f64 2961 0U, // FMAXNMPv2i32p 2962 0U, // FMAXNMPv2i64p 2963 521U, // FMAXNMPv4f32 2964 1U, // FMAXNMSrr 2965 0U, // FMAXNMVv4i32v 2966 1289U, // FMAXNMv2f32 2967 265U, // FMAXNMv2f64 2968 521U, // FMAXNMv4f32 2969 1289U, // FMAXPv2f32 2970 265U, // FMAXPv2f64 2971 0U, // FMAXPv2i32p 2972 0U, // FMAXPv2i64p 2973 521U, // FMAXPv4f32 2974 1U, // FMAXSrr 2975 0U, // FMAXVv4i32v 2976 1289U, // FMAXv2f32 2977 265U, // FMAXv2f64 2978 521U, // FMAXv4f32 2979 1U, // FMINDrr 2980 1U, // FMINNMDrr 2981 1289U, // FMINNMPv2f32 2982 265U, // FMINNMPv2f64 2983 0U, // FMINNMPv2i32p 2984 0U, // FMINNMPv2i64p 2985 521U, // FMINNMPv4f32 2986 1U, // FMINNMSrr 2987 0U, // FMINNMVv4i32v 2988 1289U, // FMINNMv2f32 2989 265U, // FMINNMv2f64 2990 521U, // FMINNMv4f32 2991 1289U, // FMINPv2f32 2992 265U, // FMINPv2f64 2993 0U, // FMINPv2i32p 2994 0U, // FMINPv2i64p 2995 521U, // FMINPv4f32 2996 1U, // FMINSrr 2997 0U, // FMINVv4i32v 2998 1289U, // FMINv2f32 2999 265U, // FMINv2f64 3000 521U, // FMINv4f32 3001 27665U, // FMLAv1i32_indexed 3002 27921U, // FMLAv1i64_indexed 3003 1297U, // FMLAv2f32 3004 273U, // FMLAv2f64 3005 27665U, // FMLAv2i32_indexed 3006 27921U, // FMLAv2i64_indexed 3007 529U, // FMLAv4f32 3008 27665U, // FMLAv4i32_indexed 3009 27665U, // FMLSv1i32_indexed 3010 27921U, // FMLSv1i64_indexed 3011 1297U, // FMLSv2f32 3012 273U, // FMLSv2f64 3013 27665U, // FMLSv2i32_indexed 3014 27921U, // FMLSv2i64_indexed 3015 529U, // FMLSv4f32 3016 27665U, // FMLSv4i32_indexed 3017 75U, // FMOVDXHighr 3018 0U, // FMOVDXr 3019 0U, // FMOVDi 3020 0U, // FMOVDr 3021 0U, // FMOVSWr 3022 0U, // FMOVSi 3023 0U, // FMOVSr 3024 0U, // FMOVWSr 3025 0U, // FMOVXDHighr 3026 0U, // FMOVXDr 3027 0U, // FMOVv2f32_ns 3028 0U, // FMOVv2f64_ns 3029 0U, // FMOVv4f32_ns 3030 18689U, // FMSUBDrrr 3031 18689U, // FMSUBSrrr 3032 1U, // FMULDrr 3033 1U, // FMULSrr 3034 1U, // FMULX32 3035 1U, // FMULX64 3036 35849U, // FMULXv1i32_indexed 3037 36105U, // FMULXv1i64_indexed 3038 1289U, // FMULXv2f32 3039 265U, // FMULXv2f64 3040 35849U, // FMULXv2i32_indexed 3041 36105U, // FMULXv2i64_indexed 3042 521U, // FMULXv4f32 3043 35849U, // FMULXv4i32_indexed 3044 35849U, // FMULv1i32_indexed 3045 36105U, // FMULv1i64_indexed 3046 1289U, // FMULv2f32 3047 265U, // FMULv2f64 3048 35849U, // FMULv2i32_indexed 3049 36105U, // FMULv2i64_indexed 3050 521U, // FMULv4f32 3051 35849U, // FMULv4i32_indexed 3052 0U, // FNEGDr 3053 0U, // FNEGSr 3054 0U, // FNEGv2f32 3055 0U, // FNEGv2f64 3056 0U, // FNEGv4f32 3057 18689U, // FNMADDDrrr 3058 18689U, // FNMADDSrrr 3059 18689U, // FNMSUBDrrr 3060 18689U, // FNMSUBSrrr 3061 1U, // FNMULDrr 3062 1U, // FNMULSrr 3063 0U, // FRECPEv1i32 3064 0U, // FRECPEv1i64 3065 0U, // FRECPEv2f32 3066 0U, // FRECPEv2f64 3067 0U, // FRECPEv4f32 3068 1U, // FRECPS32 3069 1U, // FRECPS64 3070 1289U, // FRECPSv2f32 3071 265U, // FRECPSv2f64 3072 521U, // FRECPSv4f32 3073 0U, // FRECPXv1i32 3074 0U, // FRECPXv1i64 3075 0U, // FRINTADr 3076 0U, // FRINTASr 3077 0U, // FRINTAv2f32 3078 0U, // FRINTAv2f64 3079 0U, // FRINTAv4f32 3080 0U, // FRINTIDr 3081 0U, // FRINTISr 3082 0U, // FRINTIv2f32 3083 0U, // FRINTIv2f64 3084 0U, // FRINTIv4f32 3085 0U, // FRINTMDr 3086 0U, // FRINTMSr 3087 0U, // FRINTMv2f32 3088 0U, // FRINTMv2f64 3089 0U, // FRINTMv4f32 3090 0U, // FRINTNDr 3091 0U, // FRINTNSr 3092 0U, // FRINTNv2f32 3093 0U, // FRINTNv2f64 3094 0U, // FRINTNv4f32 3095 0U, // FRINTPDr 3096 0U, // FRINTPSr 3097 0U, // FRINTPv2f32 3098 0U, // FRINTPv2f64 3099 0U, // FRINTPv4f32 3100 0U, // FRINTXDr 3101 0U, // FRINTXSr 3102 0U, // FRINTXv2f32 3103 0U, // FRINTXv2f64 3104 0U, // FRINTXv4f32 3105 0U, // FRINTZDr 3106 0U, // FRINTZSr 3107 0U, // FRINTZv2f32 3108 0U, // FRINTZv2f64 3109 0U, // FRINTZv4f32 3110 0U, // FRSQRTEv1i32 3111 0U, // FRSQRTEv1i64 3112 0U, // FRSQRTEv2f32 3113 0U, // FRSQRTEv2f64 3114 0U, // FRSQRTEv4f32 3115 1U, // FRSQRTS32 3116 1U, // FRSQRTS64 3117 1289U, // FRSQRTSv2f32 3118 265U, // FRSQRTSv2f64 3119 521U, // FRSQRTSv4f32 3120 0U, // FSQRTDr 3121 0U, // FSQRTSr 3122 0U, // FSQRTv2f32 3123 0U, // FSQRTv2f64 3124 0U, // FSQRTv4f32 3125 1U, // FSUBDrr 3126 1U, // FSUBSrr 3127 1289U, // FSUBv2f32 3128 265U, // FSUBv2f64 3129 521U, // FSUBv4f32 3130 0U, // HINT 3131 0U, // HLT 3132 0U, // HVC 3133 0U, // INSvi16gpr 3134 83U, // INSvi16lane 3135 0U, // INSvi32gpr 3136 83U, // INSvi32lane 3137 0U, // INSvi64gpr 3138 83U, // INSvi64lane 3139 0U, // INSvi8gpr 3140 83U, // INSvi8lane 3141 0U, // ISB 3142 0U, // LD1Fourv16b 3143 0U, // LD1Fourv16b_POST 3144 0U, // LD1Fourv1d 3145 0U, // LD1Fourv1d_POST 3146 0U, // LD1Fourv2d 3147 0U, // LD1Fourv2d_POST 3148 0U, // LD1Fourv2s 3149 0U, // LD1Fourv2s_POST 3150 0U, // LD1Fourv4h 3151 0U, // LD1Fourv4h_POST 3152 0U, // LD1Fourv4s 3153 0U, // LD1Fourv4s_POST 3154 0U, // LD1Fourv8b 3155 0U, // LD1Fourv8b_POST 3156 0U, // LD1Fourv8h 3157 0U, // LD1Fourv8h_POST 3158 0U, // LD1Onev16b 3159 0U, // LD1Onev16b_POST 3160 0U, // LD1Onev1d 3161 0U, // LD1Onev1d_POST 3162 0U, // LD1Onev2d 3163 0U, // LD1Onev2d_POST 3164 0U, // LD1Onev2s 3165 0U, // LD1Onev2s_POST 3166 0U, // LD1Onev4h 3167 0U, // LD1Onev4h_POST 3168 0U, // LD1Onev4s 3169 0U, // LD1Onev4s_POST 3170 0U, // LD1Onev8b 3171 0U, // LD1Onev8b_POST 3172 0U, // LD1Onev8h 3173 0U, // LD1Onev8h_POST 3174 0U, // LD1Rv16b 3175 0U, // LD1Rv16b_POST 3176 0U, // LD1Rv1d 3177 0U, // LD1Rv1d_POST 3178 0U, // LD1Rv2d 3179 0U, // LD1Rv2d_POST 3180 0U, // LD1Rv2s 3181 0U, // LD1Rv2s_POST 3182 0U, // LD1Rv4h 3183 0U, // LD1Rv4h_POST 3184 0U, // LD1Rv4s 3185 0U, // LD1Rv4s_POST 3186 0U, // LD1Rv8b 3187 0U, // LD1Rv8b_POST 3188 0U, // LD1Rv8h 3189 0U, // LD1Rv8h_POST 3190 0U, // LD1Threev16b 3191 0U, // LD1Threev16b_POST 3192 0U, // LD1Threev1d 3193 0U, // LD1Threev1d_POST 3194 0U, // LD1Threev2d 3195 0U, // LD1Threev2d_POST 3196 0U, // LD1Threev2s 3197 0U, // LD1Threev2s_POST 3198 0U, // LD1Threev4h 3199 0U, // LD1Threev4h_POST 3200 0U, // LD1Threev4s 3201 0U, // LD1Threev4s_POST 3202 0U, // LD1Threev8b 3203 0U, // LD1Threev8b_POST 3204 0U, // LD1Threev8h 3205 0U, // LD1Threev8h_POST 3206 0U, // LD1Twov16b 3207 0U, // LD1Twov16b_POST 3208 0U, // LD1Twov1d 3209 0U, // LD1Twov1d_POST 3210 0U, // LD1Twov2d 3211 0U, // LD1Twov2d_POST 3212 0U, // LD1Twov2s 3213 0U, // LD1Twov2s_POST 3214 0U, // LD1Twov4h 3215 0U, // LD1Twov4h_POST 3216 0U, // LD1Twov4s 3217 0U, // LD1Twov4s_POST 3218 0U, // LD1Twov8b 3219 0U, // LD1Twov8b_POST 3220 0U, // LD1Twov8h 3221 0U, // LD1Twov8h_POST 3222 0U, // LD1i16 3223 0U, // LD1i16_POST 3224 0U, // LD1i32 3225 0U, // LD1i32_POST 3226 0U, // LD1i64 3227 0U, // LD1i64_POST 3228 0U, // LD1i8 3229 0U, // LD1i8_POST 3230 0U, // LD2Rv16b 3231 0U, // LD2Rv16b_POST 3232 0U, // LD2Rv1d 3233 0U, // LD2Rv1d_POST 3234 0U, // LD2Rv2d 3235 0U, // LD2Rv2d_POST 3236 0U, // LD2Rv2s 3237 0U, // LD2Rv2s_POST 3238 0U, // LD2Rv4h 3239 0U, // LD2Rv4h_POST 3240 0U, // LD2Rv4s 3241 0U, // LD2Rv4s_POST 3242 0U, // LD2Rv8b 3243 0U, // LD2Rv8b_POST 3244 0U, // LD2Rv8h 3245 0U, // LD2Rv8h_POST 3246 0U, // LD2Twov16b 3247 0U, // LD2Twov16b_POST 3248 0U, // LD2Twov2d 3249 0U, // LD2Twov2d_POST 3250 0U, // LD2Twov2s 3251 0U, // LD2Twov2s_POST 3252 0U, // LD2Twov4h 3253 0U, // LD2Twov4h_POST 3254 0U, // LD2Twov4s 3255 0U, // LD2Twov4s_POST 3256 0U, // LD2Twov8b 3257 0U, // LD2Twov8b_POST 3258 0U, // LD2Twov8h 3259 0U, // LD2Twov8h_POST 3260 0U, // LD2i16 3261 0U, // LD2i16_POST 3262 0U, // LD2i32 3263 0U, // LD2i32_POST 3264 0U, // LD2i64 3265 0U, // LD2i64_POST 3266 0U, // LD2i8 3267 0U, // LD2i8_POST 3268 0U, // LD3Rv16b 3269 0U, // LD3Rv16b_POST 3270 0U, // LD3Rv1d 3271 0U, // LD3Rv1d_POST 3272 0U, // LD3Rv2d 3273 0U, // LD3Rv2d_POST 3274 0U, // LD3Rv2s 3275 0U, // LD3Rv2s_POST 3276 0U, // LD3Rv4h 3277 0U, // LD3Rv4h_POST 3278 0U, // LD3Rv4s 3279 0U, // LD3Rv4s_POST 3280 0U, // LD3Rv8b 3281 0U, // LD3Rv8b_POST 3282 0U, // LD3Rv8h 3283 0U, // LD3Rv8h_POST 3284 0U, // LD3Threev16b 3285 0U, // LD3Threev16b_POST 3286 0U, // LD3Threev2d 3287 0U, // LD3Threev2d_POST 3288 0U, // LD3Threev2s 3289 0U, // LD3Threev2s_POST 3290 0U, // LD3Threev4h 3291 0U, // LD3Threev4h_POST 3292 0U, // LD3Threev4s 3293 0U, // LD3Threev4s_POST 3294 0U, // LD3Threev8b 3295 0U, // LD3Threev8b_POST 3296 0U, // LD3Threev8h 3297 0U, // LD3Threev8h_POST 3298 0U, // LD3i16 3299 0U, // LD3i16_POST 3300 0U, // LD3i32 3301 0U, // LD3i32_POST 3302 0U, // LD3i64 3303 0U, // LD3i64_POST 3304 0U, // LD3i8 3305 0U, // LD3i8_POST 3306 0U, // LD4Fourv16b 3307 0U, // LD4Fourv16b_POST 3308 0U, // LD4Fourv2d 3309 0U, // LD4Fourv2d_POST 3310 0U, // LD4Fourv2s 3311 0U, // LD4Fourv2s_POST 3312 0U, // LD4Fourv4h 3313 0U, // LD4Fourv4h_POST 3314 0U, // LD4Fourv4s 3315 0U, // LD4Fourv4s_POST 3316 0U, // LD4Fourv8b 3317 0U, // LD4Fourv8b_POST 3318 0U, // LD4Fourv8h 3319 0U, // LD4Fourv8h_POST 3320 0U, // LD4Rv16b 3321 0U, // LD4Rv16b_POST 3322 0U, // LD4Rv1d 3323 0U, // LD4Rv1d_POST 3324 0U, // LD4Rv2d 3325 0U, // LD4Rv2d_POST 3326 0U, // LD4Rv2s 3327 0U, // LD4Rv2s_POST 3328 0U, // LD4Rv4h 3329 0U, // LD4Rv4h_POST 3330 0U, // LD4Rv4s 3331 0U, // LD4Rv4s_POST 3332 0U, // LD4Rv8b 3333 0U, // LD4Rv8b_POST 3334 0U, // LD4Rv8h 3335 0U, // LD4Rv8h_POST 3336 0U, // LD4i16 3337 0U, // LD4i16_POST 3338 0U, // LD4i32 3339 0U, // LD4i32_POST 3340 0U, // LD4i64 3341 0U, // LD4i64_POST 3342 0U, // LD4i8 3343 0U, // LD4i8_POST 3344 4U, // LDARB 3345 4U, // LDARH 3346 4U, // LDARW 3347 4U, // LDARX 3348 3588U, // LDAXPW 3349 3588U, // LDAXPX 3350 4U, // LDAXRB 3351 4U, // LDAXRH 3352 4U, // LDAXRW 3353 4U, // LDAXRX 3354 43268U, // LDNPDi 3355 51460U, // LDNPQi 3356 59652U, // LDNPSi 3357 59652U, // LDNPWi 3358 43268U, // LDNPXi 3359 43268U, // LDPDi 3360 69444U, // LDPDpost 3361 330052U, // LDPDpre 3362 51460U, // LDPQi 3363 77636U, // LDPQpost 3364 338244U, // LDPQpre 3365 59652U, // LDPSWi 3366 85828U, // LDPSWpost 3367 346436U, // LDPSWpre 3368 59652U, // LDPSi 3369 85828U, // LDPSpost 3370 346436U, // LDPSpre 3371 59652U, // LDPWi 3372 85828U, // LDPWpost 3373 346436U, // LDPWpre 3374 43268U, // LDPXi 3375 69444U, // LDPXpost 3376 330052U, // LDPXpre 3377 4U, // LDRBBpost 3378 4161U, // LDRBBpre 3379 92417U, // LDRBBroW 3380 100609U, // LDRBBroX 3381 89U, // LDRBBui 3382 4U, // LDRBpost 3383 4161U, // LDRBpre 3384 92417U, // LDRBroW 3385 100609U, // LDRBroX 3386 89U, // LDRBui 3387 0U, // LDRDl 3388 4U, // LDRDpost 3389 4161U, // LDRDpre 3390 108801U, // LDRDroW 3391 116993U, // LDRDroX 3392 97U, // LDRDui 3393 4U, // LDRHHpost 3394 4161U, // LDRHHpre 3395 125185U, // LDRHHroW 3396 133377U, // LDRHHroX 3397 105U, // LDRHHui 3398 4U, // LDRHpost 3399 4161U, // LDRHpre 3400 125185U, // LDRHroW 3401 133377U, // LDRHroX 3402 105U, // LDRHui 3403 0U, // LDRQl 3404 4U, // LDRQpost 3405 4161U, // LDRQpre 3406 141569U, // LDRQroW 3407 149761U, // LDRQroX 3408 113U, // LDRQui 3409 4U, // LDRSBWpost 3410 4161U, // LDRSBWpre 3411 92417U, // LDRSBWroW 3412 100609U, // LDRSBWroX 3413 89U, // LDRSBWui 3414 4U, // LDRSBXpost 3415 4161U, // LDRSBXpre 3416 92417U, // LDRSBXroW 3417 100609U, // LDRSBXroX 3418 89U, // LDRSBXui 3419 4U, // LDRSHWpost 3420 4161U, // LDRSHWpre 3421 125185U, // LDRSHWroW 3422 133377U, // LDRSHWroX 3423 105U, // LDRSHWui 3424 4U, // LDRSHXpost 3425 4161U, // LDRSHXpre 3426 125185U, // LDRSHXroW 3427 133377U, // LDRSHXroX 3428 105U, // LDRSHXui 3429 0U, // LDRSWl 3430 4U, // LDRSWpost 3431 4161U, // LDRSWpre 3432 157953U, // LDRSWroW 3433 166145U, // LDRSWroX 3434 121U, // LDRSWui 3435 0U, // LDRSl 3436 4U, // LDRSpost 3437 4161U, // LDRSpre 3438 157953U, // LDRSroW 3439 166145U, // LDRSroX 3440 121U, // LDRSui 3441 0U, // LDRWl 3442 4U, // LDRWpost 3443 4161U, // LDRWpre 3444 157953U, // LDRWroW 3445 166145U, // LDRWroX 3446 121U, // LDRWui 3447 0U, // LDRXl 3448 4U, // LDRXpost 3449 4161U, // LDRXpre 3450 108801U, // LDRXroW 3451 116993U, // LDRXroX 3452 97U, // LDRXui 3453 3585U, // LDTRBi 3454 3585U, // LDTRHi 3455 3585U, // LDTRSBWi 3456 3585U, // LDTRSBXi 3457 3585U, // LDTRSHWi 3458 3585U, // LDTRSHXi 3459 3585U, // LDTRSWi 3460 3585U, // LDTRWi 3461 3585U, // LDTRXi 3462 3585U, // LDURBBi 3463 3585U, // LDURBi 3464 3585U, // LDURDi 3465 3585U, // LDURHHi 3466 3585U, // LDURHi 3467 3585U, // LDURQi 3468 3585U, // LDURSBWi 3469 3585U, // LDURSBXi 3470 3585U, // LDURSHWi 3471 3585U, // LDURSHXi 3472 3585U, // LDURSWi 3473 3585U, // LDURSi 3474 3585U, // LDURWi 3475 3585U, // LDURXi 3476 3588U, // LDXPW 3477 3588U, // LDXPX 3478 4U, // LDXRB 3479 4U, // LDXRH 3480 4U, // LDXRW 3481 4U, // LDXRX 3482 0U, // LOADgot 3483 1U, // LSLVWr 3484 1U, // LSLVXr 3485 1U, // LSRVWr 3486 1U, // LSRVXr 3487 18689U, // MADDWrrr 3488 18689U, // MADDXrrr 3489 1041U, // MLAv16i8 3490 1297U, // MLAv2i32 3491 27665U, // MLAv2i32_indexed 3492 1553U, // MLAv4i16 3493 28945U, // MLAv4i16_indexed 3494 529U, // MLAv4i32 3495 27665U, // MLAv4i32_indexed 3496 785U, // MLAv8i16 3497 28945U, // MLAv8i16_indexed 3498 1809U, // MLAv8i8 3499 1041U, // MLSv16i8 3500 1297U, // MLSv2i32 3501 27665U, // MLSv2i32_indexed 3502 1553U, // MLSv4i16 3503 28945U, // MLSv4i16_indexed 3504 529U, // MLSv4i32 3505 27665U, // MLSv4i32_indexed 3506 785U, // MLSv8i16 3507 28945U, // MLSv8i16_indexed 3508 1809U, // MLSv8i8 3509 0U, // MOVID 3510 0U, // MOVIv16b_ns 3511 0U, // MOVIv2d_ns 3512 4U, // MOVIv2i32 3513 4U, // MOVIv2s_msl 3514 4U, // MOVIv4i16 3515 4U, // MOVIv4i32 3516 4U, // MOVIv4s_msl 3517 0U, // MOVIv8b_ns 3518 4U, // MOVIv8i16 3519 0U, // MOVKWi 3520 0U, // MOVKXi 3521 4U, // MOVNWi 3522 4U, // MOVNXi 3523 4U, // MOVZWi 3524 4U, // MOVZXi 3525 0U, // MOVaddr 3526 0U, // MOVaddrBA 3527 0U, // MOVaddrCP 3528 0U, // MOVaddrEXT 3529 0U, // MOVaddrJT 3530 0U, // MOVaddrTLS 3531 0U, // MOVi32imm 3532 0U, // MOVi64imm 3533 0U, // MRS 3534 0U, // MSR 3535 0U, // MSRpstate 3536 18689U, // MSUBWrrr 3537 18689U, // MSUBXrrr 3538 1033U, // MULv16i8 3539 1289U, // MULv2i32 3540 35849U, // MULv2i32_indexed 3541 1545U, // MULv4i16 3542 37129U, // MULv4i16_indexed 3543 521U, // MULv4i32 3544 35849U, // MULv4i32_indexed 3545 777U, // MULv8i16 3546 37129U, // MULv8i16_indexed 3547 1801U, // MULv8i8 3548 4U, // MVNIv2i32 3549 4U, // MVNIv2s_msl 3550 4U, // MVNIv4i16 3551 4U, // MVNIv4i32 3552 4U, // MVNIv4s_msl 3553 4U, // MVNIv8i16 3554 0U, // NEGv16i8 3555 0U, // NEGv1i64 3556 0U, // NEGv2i32 3557 0U, // NEGv2i64 3558 0U, // NEGv4i16 3559 0U, // NEGv4i32 3560 0U, // NEGv8i16 3561 0U, // NEGv8i8 3562 0U, // NOTv16i8 3563 0U, // NOTv8i8 3564 0U, // ORNWrr 3565 33U, // ORNWrs 3566 0U, // ORNXrr 3567 33U, // ORNXrs 3568 1033U, // ORNv16i8 3569 1801U, // ORNv8i8 3570 49U, // ORRWri 3571 0U, // ORRWrr 3572 33U, // ORRWrs 3573 57U, // ORRXri 3574 0U, // ORRXrr 3575 33U, // ORRXrs 3576 1033U, // ORRv16i8 3577 0U, // ORRv2i32 3578 0U, // ORRv4i16 3579 0U, // ORRv4i32 3580 0U, // ORRv8i16 3581 1801U, // ORRv8i8 3582 1033U, // PMULLv16i8 3583 0U, // PMULLv1i64 3584 0U, // PMULLv2i64 3585 1801U, // PMULLv8i8 3586 1033U, // PMULv16i8 3587 1801U, // PMULv8i8 3588 0U, // PRFMl 3589 108801U, // PRFMroW 3590 116993U, // PRFMroX 3591 97U, // PRFMui 3592 3585U, // PRFUMi 3593 265U, // RADDHNv2i64_v2i32 3594 273U, // RADDHNv2i64_v4i32 3595 521U, // RADDHNv4i32_v4i16 3596 529U, // RADDHNv4i32_v8i16 3597 785U, // RADDHNv8i16_v16i8 3598 777U, // RADDHNv8i16_v8i8 3599 0U, // RBITWr 3600 0U, // RBITXr 3601 0U, // RBITv16i8 3602 0U, // RBITv8i8 3603 0U, // RET 3604 0U, // RET_ReallyLR 3605 0U, // REV16Wr 3606 0U, // REV16Xr 3607 0U, // REV16v16i8 3608 0U, // REV16v8i8 3609 0U, // REV32Xr 3610 0U, // REV32v16i8 3611 0U, // REV32v4i16 3612 0U, // REV32v8i16 3613 0U, // REV32v8i8 3614 0U, // REV64v16i8 3615 0U, // REV64v2i32 3616 0U, // REV64v4i16 3617 0U, // REV64v4i32 3618 0U, // REV64v8i16 3619 0U, // REV64v8i8 3620 0U, // REVWr 3621 0U, // REVXr 3622 1U, // RORVWr 3623 1U, // RORVXr 3624 65U, // RSHRNv16i8_shift 3625 1U, // RSHRNv2i32_shift 3626 1U, // RSHRNv4i16_shift 3627 65U, // RSHRNv4i32_shift 3628 65U, // RSHRNv8i16_shift 3629 1U, // RSHRNv8i8_shift 3630 265U, // RSUBHNv2i64_v2i32 3631 273U, // RSUBHNv2i64_v4i32 3632 521U, // RSUBHNv4i32_v4i16 3633 529U, // RSUBHNv4i32_v8i16 3634 785U, // RSUBHNv8i16_v16i8 3635 777U, // RSUBHNv8i16_v8i8 3636 1041U, // SABALv16i8_v8i16 3637 1297U, // SABALv2i32_v2i64 3638 1553U, // SABALv4i16_v4i32 3639 529U, // SABALv4i32_v2i64 3640 785U, // SABALv8i16_v4i32 3641 1809U, // SABALv8i8_v8i16 3642 1041U, // SABAv16i8 3643 1297U, // SABAv2i32 3644 1553U, // SABAv4i16 3645 529U, // SABAv4i32 3646 785U, // SABAv8i16 3647 1809U, // SABAv8i8 3648 1033U, // SABDLv16i8_v8i16 3649 1289U, // SABDLv2i32_v2i64 3650 1545U, // SABDLv4i16_v4i32 3651 521U, // SABDLv4i32_v2i64 3652 777U, // SABDLv8i16_v4i32 3653 1801U, // SABDLv8i8_v8i16 3654 1033U, // SABDv16i8 3655 1289U, // SABDv2i32 3656 1545U, // SABDv4i16 3657 521U, // SABDv4i32 3658 777U, // SABDv8i16 3659 1801U, // SABDv8i8 3660 0U, // SADALPv16i8_v8i16 3661 0U, // SADALPv2i32_v1i64 3662 0U, // SADALPv4i16_v2i32 3663 0U, // SADALPv4i32_v2i64 3664 0U, // SADALPv8i16_v4i32 3665 0U, // SADALPv8i8_v4i16 3666 0U, // SADDLPv16i8_v8i16 3667 0U, // SADDLPv2i32_v1i64 3668 0U, // SADDLPv4i16_v2i32 3669 0U, // SADDLPv4i32_v2i64 3670 0U, // SADDLPv8i16_v4i32 3671 0U, // SADDLPv8i8_v4i16 3672 0U, // SADDLVv16i8v 3673 0U, // SADDLVv4i16v 3674 0U, // SADDLVv4i32v 3675 0U, // SADDLVv8i16v 3676 0U, // SADDLVv8i8v 3677 1033U, // SADDLv16i8_v8i16 3678 1289U, // SADDLv2i32_v2i64 3679 1545U, // SADDLv4i16_v4i32 3680 521U, // SADDLv4i32_v2i64 3681 777U, // SADDLv8i16_v4i32 3682 1801U, // SADDLv8i8_v8i16 3683 1033U, // SADDWv16i8_v8i16 3684 1289U, // SADDWv2i32_v2i64 3685 1545U, // SADDWv4i16_v4i32 3686 521U, // SADDWv4i32_v2i64 3687 777U, // SADDWv8i16_v4i32 3688 1801U, // SADDWv8i8_v8i16 3689 1U, // SBCSWr 3690 1U, // SBCSXr 3691 1U, // SBCWr 3692 1U, // SBCXr 3693 18689U, // SBFMWri 3694 18689U, // SBFMXri 3695 1U, // SCVTFSWDri 3696 1U, // SCVTFSWSri 3697 1U, // SCVTFSXDri 3698 1U, // SCVTFSXSri 3699 0U, // SCVTFUWDri 3700 0U, // SCVTFUWSri 3701 0U, // SCVTFUXDri 3702 0U, // SCVTFUXSri 3703 1U, // SCVTFd 3704 1U, // SCVTFs 3705 0U, // SCVTFv1i32 3706 0U, // SCVTFv1i64 3707 0U, // SCVTFv2f32 3708 0U, // SCVTFv2f64 3709 1U, // SCVTFv2i32_shift 3710 1U, // SCVTFv2i64_shift 3711 0U, // SCVTFv4f32 3712 1U, // SCVTFv4i32_shift 3713 1U, // SDIVWr 3714 1U, // SDIVXr 3715 1U, // SDIV_IntWr 3716 1U, // SDIV_IntXr 3717 529U, // SHA1Crrr 3718 0U, // SHA1Hrr 3719 529U, // SHA1Mrrr 3720 529U, // SHA1Prrr 3721 529U, // SHA1SU0rrr 3722 0U, // SHA1SU1rr 3723 529U, // SHA256H2rrr 3724 529U, // SHA256Hrrr 3725 0U, // SHA256SU0rr 3726 529U, // SHA256SU1rrr 3727 1033U, // SHADDv16i8 3728 1289U, // SHADDv2i32 3729 1545U, // SHADDv4i16 3730 521U, // SHADDv4i32 3731 777U, // SHADDv8i16 3732 1801U, // SHADDv8i8 3733 4U, // SHLLv16i8 3734 4U, // SHLLv2i32 3735 4U, // SHLLv4i16 3736 4U, // SHLLv4i32 3737 5U, // SHLLv8i16 3738 5U, // SHLLv8i8 3739 1U, // SHLd 3740 1U, // SHLv16i8_shift 3741 1U, // SHLv2i32_shift 3742 1U, // SHLv2i64_shift 3743 1U, // SHLv4i16_shift 3744 1U, // SHLv4i32_shift 3745 1U, // SHLv8i16_shift 3746 1U, // SHLv8i8_shift 3747 65U, // SHRNv16i8_shift 3748 1U, // SHRNv2i32_shift 3749 1U, // SHRNv4i16_shift 3750 65U, // SHRNv4i32_shift 3751 65U, // SHRNv8i16_shift 3752 1U, // SHRNv8i8_shift 3753 1033U, // SHSUBv16i8 3754 1289U, // SHSUBv2i32 3755 1545U, // SHSUBv4i16 3756 521U, // SHSUBv4i32 3757 777U, // SHSUBv8i16 3758 1801U, // SHSUBv8i8 3759 65U, // SLId 3760 65U, // SLIv16i8_shift 3761 65U, // SLIv2i32_shift 3762 65U, // SLIv2i64_shift 3763 65U, // SLIv4i16_shift 3764 65U, // SLIv4i32_shift 3765 65U, // SLIv8i16_shift 3766 65U, // SLIv8i8_shift 3767 18689U, // SMADDLrrr 3768 1033U, // SMAXPv16i8 3769 1289U, // SMAXPv2i32 3770 1545U, // SMAXPv4i16 3771 521U, // SMAXPv4i32 3772 777U, // SMAXPv8i16 3773 1801U, // SMAXPv8i8 3774 0U, // SMAXVv16i8v 3775 0U, // SMAXVv4i16v 3776 0U, // SMAXVv4i32v 3777 0U, // SMAXVv8i16v 3778 0U, // SMAXVv8i8v 3779 1033U, // SMAXv16i8 3780 1289U, // SMAXv2i32 3781 1545U, // SMAXv4i16 3782 521U, // SMAXv4i32 3783 777U, // SMAXv8i16 3784 1801U, // SMAXv8i8 3785 0U, // SMC 3786 1033U, // SMINPv16i8 3787 1289U, // SMINPv2i32 3788 1545U, // SMINPv4i16 3789 521U, // SMINPv4i32 3790 777U, // SMINPv8i16 3791 1801U, // SMINPv8i8 3792 0U, // SMINVv16i8v 3793 0U, // SMINVv4i16v 3794 0U, // SMINVv4i32v 3795 0U, // SMINVv8i16v 3796 0U, // SMINVv8i8v 3797 1033U, // SMINv16i8 3798 1289U, // SMINv2i32 3799 1545U, // SMINv4i16 3800 521U, // SMINv4i32 3801 777U, // SMINv8i16 3802 1801U, // SMINv8i8 3803 1041U, // SMLALv16i8_v8i16 3804 27665U, // SMLALv2i32_indexed 3805 1297U, // SMLALv2i32_v2i64 3806 28945U, // SMLALv4i16_indexed 3807 1553U, // SMLALv4i16_v4i32 3808 27665U, // SMLALv4i32_indexed 3809 529U, // SMLALv4i32_v2i64 3810 28945U, // SMLALv8i16_indexed 3811 785U, // SMLALv8i16_v4i32 3812 1809U, // SMLALv8i8_v8i16 3813 1041U, // SMLSLv16i8_v8i16 3814 27665U, // SMLSLv2i32_indexed 3815 1297U, // SMLSLv2i32_v2i64 3816 28945U, // SMLSLv4i16_indexed 3817 1553U, // SMLSLv4i16_v4i32 3818 27665U, // SMLSLv4i32_indexed 3819 529U, // SMLSLv4i32_v2i64 3820 28945U, // SMLSLv8i16_indexed 3821 785U, // SMLSLv8i16_v4i32 3822 1809U, // SMLSLv8i8_v8i16 3823 75U, // SMOVvi16to32 3824 75U, // SMOVvi16to64 3825 75U, // SMOVvi32to64 3826 75U, // SMOVvi8to32 3827 75U, // SMOVvi8to64 3828 18689U, // SMSUBLrrr 3829 1U, // SMULHrr 3830 1033U, // SMULLv16i8_v8i16 3831 35849U, // SMULLv2i32_indexed 3832 1289U, // SMULLv2i32_v2i64 3833 37129U, // SMULLv4i16_indexed 3834 1545U, // SMULLv4i16_v4i32 3835 35849U, // SMULLv4i32_indexed 3836 521U, // SMULLv4i32_v2i64 3837 37129U, // SMULLv8i16_indexed 3838 777U, // SMULLv8i16_v4i32 3839 1801U, // SMULLv8i8_v8i16 3840 0U, // SQABSv16i8 3841 0U, // SQABSv1i16 3842 0U, // SQABSv1i32 3843 0U, // SQABSv1i64 3844 0U, // SQABSv1i8 3845 0U, // SQABSv2i32 3846 0U, // SQABSv2i64 3847 0U, // SQABSv4i16 3848 0U, // SQABSv4i32 3849 0U, // SQABSv8i16 3850 0U, // SQABSv8i8 3851 1033U, // SQADDv16i8 3852 1U, // SQADDv1i16 3853 1U, // SQADDv1i32 3854 1U, // SQADDv1i64 3855 1U, // SQADDv1i8 3856 1289U, // SQADDv2i32 3857 265U, // SQADDv2i64 3858 1545U, // SQADDv4i16 3859 521U, // SQADDv4i32 3860 777U, // SQADDv8i16 3861 1801U, // SQADDv8i8 3862 65U, // SQDMLALi16 3863 65U, // SQDMLALi32 3864 28945U, // SQDMLALv1i32_indexed 3865 27665U, // SQDMLALv1i64_indexed 3866 27665U, // SQDMLALv2i32_indexed 3867 1297U, // SQDMLALv2i32_v2i64 3868 28945U, // SQDMLALv4i16_indexed 3869 1553U, // SQDMLALv4i16_v4i32 3870 27665U, // SQDMLALv4i32_indexed 3871 529U, // SQDMLALv4i32_v2i64 3872 28945U, // SQDMLALv8i16_indexed 3873 785U, // SQDMLALv8i16_v4i32 3874 65U, // SQDMLSLi16 3875 65U, // SQDMLSLi32 3876 28945U, // SQDMLSLv1i32_indexed 3877 27665U, // SQDMLSLv1i64_indexed 3878 27665U, // SQDMLSLv2i32_indexed 3879 1297U, // SQDMLSLv2i32_v2i64 3880 28945U, // SQDMLSLv4i16_indexed 3881 1553U, // SQDMLSLv4i16_v4i32 3882 27665U, // SQDMLSLv4i32_indexed 3883 529U, // SQDMLSLv4i32_v2i64 3884 28945U, // SQDMLSLv8i16_indexed 3885 785U, // SQDMLSLv8i16_v4i32 3886 1U, // SQDMULHv1i16 3887 37129U, // SQDMULHv1i16_indexed 3888 1U, // SQDMULHv1i32 3889 35849U, // SQDMULHv1i32_indexed 3890 1289U, // SQDMULHv2i32 3891 35849U, // SQDMULHv2i32_indexed 3892 1545U, // SQDMULHv4i16 3893 37129U, // SQDMULHv4i16_indexed 3894 521U, // SQDMULHv4i32 3895 35849U, // SQDMULHv4i32_indexed 3896 777U, // SQDMULHv8i16 3897 37129U, // SQDMULHv8i16_indexed 3898 1U, // SQDMULLi16 3899 1U, // SQDMULLi32 3900 37129U, // SQDMULLv1i32_indexed 3901 35849U, // SQDMULLv1i64_indexed 3902 35849U, // SQDMULLv2i32_indexed 3903 1289U, // SQDMULLv2i32_v2i64 3904 37129U, // SQDMULLv4i16_indexed 3905 1545U, // SQDMULLv4i16_v4i32 3906 35849U, // SQDMULLv4i32_indexed 3907 521U, // SQDMULLv4i32_v2i64 3908 37129U, // SQDMULLv8i16_indexed 3909 777U, // SQDMULLv8i16_v4i32 3910 0U, // SQNEGv16i8 3911 0U, // SQNEGv1i16 3912 0U, // SQNEGv1i32 3913 0U, // SQNEGv1i64 3914 0U, // SQNEGv1i8 3915 0U, // SQNEGv2i32 3916 0U, // SQNEGv2i64 3917 0U, // SQNEGv4i16 3918 0U, // SQNEGv4i32 3919 0U, // SQNEGv8i16 3920 0U, // SQNEGv8i8 3921 1U, // SQRDMULHv1i16 3922 37129U, // SQRDMULHv1i16_indexed 3923 1U, // SQRDMULHv1i32 3924 35849U, // SQRDMULHv1i32_indexed 3925 1289U, // SQRDMULHv2i32 3926 35849U, // SQRDMULHv2i32_indexed 3927 1545U, // SQRDMULHv4i16 3928 37129U, // SQRDMULHv4i16_indexed 3929 521U, // SQRDMULHv4i32 3930 35849U, // SQRDMULHv4i32_indexed 3931 777U, // SQRDMULHv8i16 3932 37129U, // SQRDMULHv8i16_indexed 3933 1033U, // SQRSHLv16i8 3934 1U, // SQRSHLv1i16 3935 1U, // SQRSHLv1i32 3936 1U, // SQRSHLv1i64 3937 1U, // SQRSHLv1i8 3938 1289U, // SQRSHLv2i32 3939 265U, // SQRSHLv2i64 3940 1545U, // SQRSHLv4i16 3941 521U, // SQRSHLv4i32 3942 777U, // SQRSHLv8i16 3943 1801U, // SQRSHLv8i8 3944 1U, // SQRSHRNb 3945 1U, // SQRSHRNh 3946 1U, // SQRSHRNs 3947 65U, // SQRSHRNv16i8_shift 3948 1U, // SQRSHRNv2i32_shift 3949 1U, // SQRSHRNv4i16_shift 3950 65U, // SQRSHRNv4i32_shift 3951 65U, // SQRSHRNv8i16_shift 3952 1U, // SQRSHRNv8i8_shift 3953 1U, // SQRSHRUNb 3954 1U, // SQRSHRUNh 3955 1U, // SQRSHRUNs 3956 65U, // SQRSHRUNv16i8_shift 3957 1U, // SQRSHRUNv2i32_shift 3958 1U, // SQRSHRUNv4i16_shift 3959 65U, // SQRSHRUNv4i32_shift 3960 65U, // SQRSHRUNv8i16_shift 3961 1U, // SQRSHRUNv8i8_shift 3962 1U, // SQSHLUb 3963 1U, // SQSHLUd 3964 1U, // SQSHLUh 3965 1U, // SQSHLUs 3966 1U, // SQSHLUv16i8_shift 3967 1U, // SQSHLUv2i32_shift 3968 1U, // SQSHLUv2i64_shift 3969 1U, // SQSHLUv4i16_shift 3970 1U, // SQSHLUv4i32_shift 3971 1U, // SQSHLUv8i16_shift 3972 1U, // SQSHLUv8i8_shift 3973 1U, // SQSHLb 3974 1U, // SQSHLd 3975 1U, // SQSHLh 3976 1U, // SQSHLs 3977 1033U, // SQSHLv16i8 3978 1U, // SQSHLv16i8_shift 3979 1U, // SQSHLv1i16 3980 1U, // SQSHLv1i32 3981 1U, // SQSHLv1i64 3982 1U, // SQSHLv1i8 3983 1289U, // SQSHLv2i32 3984 1U, // SQSHLv2i32_shift 3985 265U, // SQSHLv2i64 3986 1U, // SQSHLv2i64_shift 3987 1545U, // SQSHLv4i16 3988 1U, // SQSHLv4i16_shift 3989 521U, // SQSHLv4i32 3990 1U, // SQSHLv4i32_shift 3991 777U, // SQSHLv8i16 3992 1U, // SQSHLv8i16_shift 3993 1801U, // SQSHLv8i8 3994 1U, // SQSHLv8i8_shift 3995 1U, // SQSHRNb 3996 1U, // SQSHRNh 3997 1U, // SQSHRNs 3998 65U, // SQSHRNv16i8_shift 3999 1U, // SQSHRNv2i32_shift 4000 1U, // SQSHRNv4i16_shift 4001 65U, // SQSHRNv4i32_shift 4002 65U, // SQSHRNv8i16_shift 4003 1U, // SQSHRNv8i8_shift 4004 1U, // SQSHRUNb 4005 1U, // SQSHRUNh 4006 1U, // SQSHRUNs 4007 65U, // SQSHRUNv16i8_shift 4008 1U, // SQSHRUNv2i32_shift 4009 1U, // SQSHRUNv4i16_shift 4010 65U, // SQSHRUNv4i32_shift 4011 65U, // SQSHRUNv8i16_shift 4012 1U, // SQSHRUNv8i8_shift 4013 1033U, // SQSUBv16i8 4014 1U, // SQSUBv1i16 4015 1U, // SQSUBv1i32 4016 1U, // SQSUBv1i64 4017 1U, // SQSUBv1i8 4018 1289U, // SQSUBv2i32 4019 265U, // SQSUBv2i64 4020 1545U, // SQSUBv4i16 4021 521U, // SQSUBv4i32 4022 777U, // SQSUBv8i16 4023 1801U, // SQSUBv8i8 4024 0U, // SQXTNv16i8 4025 0U, // SQXTNv1i16 4026 0U, // SQXTNv1i32 4027 0U, // SQXTNv1i8 4028 0U, // SQXTNv2i32 4029 0U, // SQXTNv4i16 4030 0U, // SQXTNv4i32 4031 0U, // SQXTNv8i16 4032 0U, // SQXTNv8i8 4033 0U, // SQXTUNv16i8 4034 0U, // SQXTUNv1i16 4035 0U, // SQXTUNv1i32 4036 0U, // SQXTUNv1i8 4037 0U, // SQXTUNv2i32 4038 0U, // SQXTUNv4i16 4039 0U, // SQXTUNv4i32 4040 0U, // SQXTUNv8i16 4041 0U, // SQXTUNv8i8 4042 1033U, // SRHADDv16i8 4043 1289U, // SRHADDv2i32 4044 1545U, // SRHADDv4i16 4045 521U, // SRHADDv4i32 4046 777U, // SRHADDv8i16 4047 1801U, // SRHADDv8i8 4048 65U, // SRId 4049 65U, // SRIv16i8_shift 4050 65U, // SRIv2i32_shift 4051 65U, // SRIv2i64_shift 4052 65U, // SRIv4i16_shift 4053 65U, // SRIv4i32_shift 4054 65U, // SRIv8i16_shift 4055 65U, // SRIv8i8_shift 4056 1033U, // SRSHLv16i8 4057 1U, // SRSHLv1i64 4058 1289U, // SRSHLv2i32 4059 265U, // SRSHLv2i64 4060 1545U, // SRSHLv4i16 4061 521U, // SRSHLv4i32 4062 777U, // SRSHLv8i16 4063 1801U, // SRSHLv8i8 4064 1U, // SRSHRd 4065 1U, // SRSHRv16i8_shift 4066 1U, // SRSHRv2i32_shift 4067 1U, // SRSHRv2i64_shift 4068 1U, // SRSHRv4i16_shift 4069 1U, // SRSHRv4i32_shift 4070 1U, // SRSHRv8i16_shift 4071 1U, // SRSHRv8i8_shift 4072 65U, // SRSRAd 4073 65U, // SRSRAv16i8_shift 4074 65U, // SRSRAv2i32_shift 4075 65U, // SRSRAv2i64_shift 4076 65U, // SRSRAv4i16_shift 4077 65U, // SRSRAv4i32_shift 4078 65U, // SRSRAv8i16_shift 4079 65U, // SRSRAv8i8_shift 4080 1U, // SSHLLv16i8_shift 4081 1U, // SSHLLv2i32_shift 4082 1U, // SSHLLv4i16_shift 4083 1U, // SSHLLv4i32_shift 4084 1U, // SSHLLv8i16_shift 4085 1U, // SSHLLv8i8_shift 4086 1033U, // SSHLv16i8 4087 1U, // SSHLv1i64 4088 1289U, // SSHLv2i32 4089 265U, // SSHLv2i64 4090 1545U, // SSHLv4i16 4091 521U, // SSHLv4i32 4092 777U, // SSHLv8i16 4093 1801U, // SSHLv8i8 4094 1U, // SSHRd 4095 1U, // SSHRv16i8_shift 4096 1U, // SSHRv2i32_shift 4097 1U, // SSHRv2i64_shift 4098 1U, // SSHRv4i16_shift 4099 1U, // SSHRv4i32_shift 4100 1U, // SSHRv8i16_shift 4101 1U, // SSHRv8i8_shift 4102 65U, // SSRAd 4103 65U, // SSRAv16i8_shift 4104 65U, // SSRAv2i32_shift 4105 65U, // SSRAv2i64_shift 4106 65U, // SSRAv4i16_shift 4107 65U, // SSRAv4i32_shift 4108 65U, // SSRAv8i16_shift 4109 65U, // SSRAv8i8_shift 4110 1033U, // SSUBLv16i8_v8i16 4111 1289U, // SSUBLv2i32_v2i64 4112 1545U, // SSUBLv4i16_v4i32 4113 521U, // SSUBLv4i32_v2i64 4114 777U, // SSUBLv8i16_v4i32 4115 1801U, // SSUBLv8i8_v8i16 4116 1033U, // SSUBWv16i8_v8i16 4117 1289U, // SSUBWv2i32_v2i64 4118 1545U, // SSUBWv4i16_v4i32 4119 521U, // SSUBWv4i32_v2i64 4120 777U, // SSUBWv8i16_v4i32 4121 1801U, // SSUBWv8i8_v8i16 4122 0U, // ST1Fourv16b 4123 0U, // ST1Fourv16b_POST 4124 0U, // ST1Fourv1d 4125 0U, // ST1Fourv1d_POST 4126 0U, // ST1Fourv2d 4127 0U, // ST1Fourv2d_POST 4128 0U, // ST1Fourv2s 4129 0U, // ST1Fourv2s_POST 4130 0U, // ST1Fourv4h 4131 0U, // ST1Fourv4h_POST 4132 0U, // ST1Fourv4s 4133 0U, // ST1Fourv4s_POST 4134 0U, // ST1Fourv8b 4135 0U, // ST1Fourv8b_POST 4136 0U, // ST1Fourv8h 4137 0U, // ST1Fourv8h_POST 4138 0U, // ST1Onev16b 4139 0U, // ST1Onev16b_POST 4140 0U, // ST1Onev1d 4141 0U, // ST1Onev1d_POST 4142 0U, // ST1Onev2d 4143 0U, // ST1Onev2d_POST 4144 0U, // ST1Onev2s 4145 0U, // ST1Onev2s_POST 4146 0U, // ST1Onev4h 4147 0U, // ST1Onev4h_POST 4148 0U, // ST1Onev4s 4149 0U, // ST1Onev4s_POST 4150 0U, // ST1Onev8b 4151 0U, // ST1Onev8b_POST 4152 0U, // ST1Onev8h 4153 0U, // ST1Onev8h_POST 4154 0U, // ST1Threev16b 4155 0U, // ST1Threev16b_POST 4156 0U, // ST1Threev1d 4157 0U, // ST1Threev1d_POST 4158 0U, // ST1Threev2d 4159 0U, // ST1Threev2d_POST 4160 0U, // ST1Threev2s 4161 0U, // ST1Threev2s_POST 4162 0U, // ST1Threev4h 4163 0U, // ST1Threev4h_POST 4164 0U, // ST1Threev4s 4165 0U, // ST1Threev4s_POST 4166 0U, // ST1Threev8b 4167 0U, // ST1Threev8b_POST 4168 0U, // ST1Threev8h 4169 0U, // ST1Threev8h_POST 4170 0U, // ST1Twov16b 4171 0U, // ST1Twov16b_POST 4172 0U, // ST1Twov1d 4173 0U, // ST1Twov1d_POST 4174 0U, // ST1Twov2d 4175 0U, // ST1Twov2d_POST 4176 0U, // ST1Twov2s 4177 0U, // ST1Twov2s_POST 4178 0U, // ST1Twov4h 4179 0U, // ST1Twov4h_POST 4180 0U, // ST1Twov4s 4181 0U, // ST1Twov4s_POST 4182 0U, // ST1Twov8b 4183 0U, // ST1Twov8b_POST 4184 0U, // ST1Twov8h 4185 0U, // ST1Twov8h_POST 4186 0U, // ST1i16 4187 0U, // ST1i16_POST 4188 0U, // ST1i32 4189 0U, // ST1i32_POST 4190 0U, // ST1i64 4191 0U, // ST1i64_POST 4192 0U, // ST1i8 4193 0U, // ST1i8_POST 4194 0U, // ST2Twov16b 4195 0U, // ST2Twov16b_POST 4196 0U, // ST2Twov2d 4197 0U, // ST2Twov2d_POST 4198 0U, // ST2Twov2s 4199 0U, // ST2Twov2s_POST 4200 0U, // ST2Twov4h 4201 0U, // ST2Twov4h_POST 4202 0U, // ST2Twov4s 4203 0U, // ST2Twov4s_POST 4204 0U, // ST2Twov8b 4205 0U, // ST2Twov8b_POST 4206 0U, // ST2Twov8h 4207 0U, // ST2Twov8h_POST 4208 0U, // ST2i16 4209 0U, // ST2i16_POST 4210 0U, // ST2i32 4211 0U, // ST2i32_POST 4212 0U, // ST2i64 4213 0U, // ST2i64_POST 4214 0U, // ST2i8 4215 0U, // ST2i8_POST 4216 0U, // ST3Threev16b 4217 0U, // ST3Threev16b_POST 4218 0U, // ST3Threev2d 4219 0U, // ST3Threev2d_POST 4220 0U, // ST3Threev2s 4221 0U, // ST3Threev2s_POST 4222 0U, // ST3Threev4h 4223 0U, // ST3Threev4h_POST 4224 0U, // ST3Threev4s 4225 0U, // ST3Threev4s_POST 4226 0U, // ST3Threev8b 4227 0U, // ST3Threev8b_POST 4228 0U, // ST3Threev8h 4229 0U, // ST3Threev8h_POST 4230 0U, // ST3i16 4231 0U, // ST3i16_POST 4232 0U, // ST3i32 4233 0U, // ST3i32_POST 4234 0U, // ST3i64 4235 0U, // ST3i64_POST 4236 0U, // ST3i8 4237 0U, // ST3i8_POST 4238 0U, // ST4Fourv16b 4239 0U, // ST4Fourv16b_POST 4240 0U, // ST4Fourv2d 4241 0U, // ST4Fourv2d_POST 4242 0U, // ST4Fourv2s 4243 0U, // ST4Fourv2s_POST 4244 0U, // ST4Fourv4h 4245 0U, // ST4Fourv4h_POST 4246 0U, // ST4Fourv4s 4247 0U, // ST4Fourv4s_POST 4248 0U, // ST4Fourv8b 4249 0U, // ST4Fourv8b_POST 4250 0U, // ST4Fourv8h 4251 0U, // ST4Fourv8h_POST 4252 0U, // ST4i16 4253 0U, // ST4i16_POST 4254 0U, // ST4i32 4255 0U, // ST4i32_POST 4256 0U, // ST4i64 4257 0U, // ST4i64_POST 4258 0U, // ST4i8 4259 0U, // ST4i8_POST 4260 4U, // STLRB 4261 4U, // STLRH 4262 4U, // STLRW 4263 4U, // STLRX 4264 4609U, // STLXPW 4265 4609U, // STLXPX 4266 3588U, // STLXRB 4267 3588U, // STLXRH 4268 3588U, // STLXRW 4269 3588U, // STLXRX 4270 43268U, // STNPDi 4271 51460U, // STNPQi 4272 59652U, // STNPSi 4273 59652U, // STNPWi 4274 43268U, // STNPXi 4275 43268U, // STPDi 4276 69444U, // STPDpost 4277 330052U, // STPDpre 4278 51460U, // STPQi 4279 77636U, // STPQpost 4280 338244U, // STPQpre 4281 59652U, // STPSi 4282 85828U, // STPSpost 4283 346436U, // STPSpre 4284 59652U, // STPWi 4285 85828U, // STPWpost 4286 346436U, // STPWpre 4287 43268U, // STPXi 4288 69444U, // STPXpost 4289 330052U, // STPXpre 4290 4U, // STRBBpost 4291 4161U, // STRBBpre 4292 92417U, // STRBBroW 4293 100609U, // STRBBroX 4294 89U, // STRBBui 4295 4U, // STRBpost 4296 4161U, // STRBpre 4297 92417U, // STRBroW 4298 100609U, // STRBroX 4299 89U, // STRBui 4300 4U, // STRDpost 4301 4161U, // STRDpre 4302 108801U, // STRDroW 4303 116993U, // STRDroX 4304 97U, // STRDui 4305 4U, // STRHHpost 4306 4161U, // STRHHpre 4307 125185U, // STRHHroW 4308 133377U, // STRHHroX 4309 105U, // STRHHui 4310 4U, // STRHpost 4311 4161U, // STRHpre 4312 125185U, // STRHroW 4313 133377U, // STRHroX 4314 105U, // STRHui 4315 4U, // STRQpost 4316 4161U, // STRQpre 4317 141569U, // STRQroW 4318 149761U, // STRQroX 4319 113U, // STRQui 4320 4U, // STRSpost 4321 4161U, // STRSpre 4322 157953U, // STRSroW 4323 166145U, // STRSroX 4324 121U, // STRSui 4325 4U, // STRWpost 4326 4161U, // STRWpre 4327 157953U, // STRWroW 4328 166145U, // STRWroX 4329 121U, // STRWui 4330 4U, // STRXpost 4331 4161U, // STRXpre 4332 108801U, // STRXroW 4333 116993U, // STRXroX 4334 97U, // STRXui 4335 3585U, // STTRBi 4336 3585U, // STTRHi 4337 3585U, // STTRWi 4338 3585U, // STTRXi 4339 3585U, // STURBBi 4340 3585U, // STURBi 4341 3585U, // STURDi 4342 3585U, // STURHHi 4343 3585U, // STURHi 4344 3585U, // STURQi 4345 3585U, // STURSi 4346 3585U, // STURWi 4347 3585U, // STURXi 4348 4609U, // STXPW 4349 4609U, // STXPX 4350 3588U, // STXRB 4351 3588U, // STXRH 4352 3588U, // STXRW 4353 3588U, // STXRX 4354 265U, // SUBHNv2i64_v2i32 4355 273U, // SUBHNv2i64_v4i32 4356 521U, // SUBHNv4i32_v4i16 4357 529U, // SUBHNv4i32_v8i16 4358 785U, // SUBHNv8i16_v16i8 4359 777U, // SUBHNv8i16_v8i8 4360 25U, // SUBSWri 4361 0U, // SUBSWrr 4362 33U, // SUBSWrs 4363 41U, // SUBSWrx 4364 25U, // SUBSXri 4365 0U, // SUBSXrr 4366 33U, // SUBSXrs 4367 41U, // SUBSXrx 4368 2049U, // SUBSXrx64 4369 25U, // SUBWri 4370 0U, // SUBWrr 4371 33U, // SUBWrs 4372 41U, // SUBWrx 4373 25U, // SUBXri 4374 0U, // SUBXrr 4375 33U, // SUBXrs 4376 41U, // SUBXrx 4377 2049U, // SUBXrx64 4378 1033U, // SUBv16i8 4379 1U, // SUBv1i64 4380 1289U, // SUBv2i32 4381 265U, // SUBv2i64 4382 1545U, // SUBv4i16 4383 521U, // SUBv4i32 4384 777U, // SUBv8i16 4385 1801U, // SUBv8i8 4386 0U, // SUQADDv16i8 4387 0U, // SUQADDv1i16 4388 0U, // SUQADDv1i32 4389 0U, // SUQADDv1i64 4390 0U, // SUQADDv1i8 4391 0U, // SUQADDv2i32 4392 0U, // SUQADDv2i64 4393 0U, // SUQADDv4i16 4394 0U, // SUQADDv4i32 4395 0U, // SUQADDv8i16 4396 0U, // SUQADDv8i8 4397 0U, // SVC 4398 129U, // SYSLxt 4399 0U, // SYSxt 4400 0U, // TBLv16i8Four 4401 0U, // TBLv16i8One 4402 0U, // TBLv16i8Three 4403 0U, // TBLv16i8Two 4404 0U, // TBLv8i8Four 4405 0U, // TBLv8i8One 4406 0U, // TBLv8i8Three 4407 0U, // TBLv8i8Two 4408 137U, // TBNZW 4409 137U, // TBNZX 4410 0U, // TBXv16i8Four 4411 0U, // TBXv16i8One 4412 0U, // TBXv16i8Three 4413 0U, // TBXv16i8Two 4414 0U, // TBXv8i8Four 4415 0U, // TBXv8i8One 4416 0U, // TBXv8i8Three 4417 0U, // TBXv8i8Two 4418 137U, // TBZW 4419 137U, // TBZX 4420 0U, // TCRETURNdi 4421 0U, // TCRETURNri 4422 0U, // TLSDESCCALL 4423 0U, // TLSDESC_BLR 4424 1033U, // TRN1v16i8 4425 1289U, // TRN1v2i32 4426 265U, // TRN1v2i64 4427 1545U, // TRN1v4i16 4428 521U, // TRN1v4i32 4429 777U, // TRN1v8i16 4430 1801U, // TRN1v8i8 4431 1033U, // TRN2v16i8 4432 1289U, // TRN2v2i32 4433 265U, // TRN2v2i64 4434 1545U, // TRN2v4i16 4435 521U, // TRN2v4i32 4436 777U, // TRN2v8i16 4437 1801U, // TRN2v8i8 4438 1041U, // UABALv16i8_v8i16 4439 1297U, // UABALv2i32_v2i64 4440 1553U, // UABALv4i16_v4i32 4441 529U, // UABALv4i32_v2i64 4442 785U, // UABALv8i16_v4i32 4443 1809U, // UABALv8i8_v8i16 4444 1041U, // UABAv16i8 4445 1297U, // UABAv2i32 4446 1553U, // UABAv4i16 4447 529U, // UABAv4i32 4448 785U, // UABAv8i16 4449 1809U, // UABAv8i8 4450 1033U, // UABDLv16i8_v8i16 4451 1289U, // UABDLv2i32_v2i64 4452 1545U, // UABDLv4i16_v4i32 4453 521U, // UABDLv4i32_v2i64 4454 777U, // UABDLv8i16_v4i32 4455 1801U, // UABDLv8i8_v8i16 4456 1033U, // UABDv16i8 4457 1289U, // UABDv2i32 4458 1545U, // UABDv4i16 4459 521U, // UABDv4i32 4460 777U, // UABDv8i16 4461 1801U, // UABDv8i8 4462 0U, // UADALPv16i8_v8i16 4463 0U, // UADALPv2i32_v1i64 4464 0U, // UADALPv4i16_v2i32 4465 0U, // UADALPv4i32_v2i64 4466 0U, // UADALPv8i16_v4i32 4467 0U, // UADALPv8i8_v4i16 4468 0U, // UADDLPv16i8_v8i16 4469 0U, // UADDLPv2i32_v1i64 4470 0U, // UADDLPv4i16_v2i32 4471 0U, // UADDLPv4i32_v2i64 4472 0U, // UADDLPv8i16_v4i32 4473 0U, // UADDLPv8i8_v4i16 4474 0U, // UADDLVv16i8v 4475 0U, // UADDLVv4i16v 4476 0U, // UADDLVv4i32v 4477 0U, // UADDLVv8i16v 4478 0U, // UADDLVv8i8v 4479 1033U, // UADDLv16i8_v8i16 4480 1289U, // UADDLv2i32_v2i64 4481 1545U, // UADDLv4i16_v4i32 4482 521U, // UADDLv4i32_v2i64 4483 777U, // UADDLv8i16_v4i32 4484 1801U, // UADDLv8i8_v8i16 4485 1033U, // UADDWv16i8_v8i16 4486 1289U, // UADDWv2i32_v2i64 4487 1545U, // UADDWv4i16_v4i32 4488 521U, // UADDWv4i32_v2i64 4489 777U, // UADDWv8i16_v4i32 4490 1801U, // UADDWv8i8_v8i16 4491 18689U, // UBFMWri 4492 18689U, // UBFMXri 4493 1U, // UCVTFSWDri 4494 1U, // UCVTFSWSri 4495 1U, // UCVTFSXDri 4496 1U, // UCVTFSXSri 4497 0U, // UCVTFUWDri 4498 0U, // UCVTFUWSri 4499 0U, // UCVTFUXDri 4500 0U, // UCVTFUXSri 4501 1U, // UCVTFd 4502 1U, // UCVTFs 4503 0U, // UCVTFv1i32 4504 0U, // UCVTFv1i64 4505 0U, // UCVTFv2f32 4506 0U, // UCVTFv2f64 4507 1U, // UCVTFv2i32_shift 4508 1U, // UCVTFv2i64_shift 4509 0U, // UCVTFv4f32 4510 1U, // UCVTFv4i32_shift 4511 1U, // UDIVWr 4512 1U, // UDIVXr 4513 1U, // UDIV_IntWr 4514 1U, // UDIV_IntXr 4515 1033U, // UHADDv16i8 4516 1289U, // UHADDv2i32 4517 1545U, // UHADDv4i16 4518 521U, // UHADDv4i32 4519 777U, // UHADDv8i16 4520 1801U, // UHADDv8i8 4521 1033U, // UHSUBv16i8 4522 1289U, // UHSUBv2i32 4523 1545U, // UHSUBv4i16 4524 521U, // UHSUBv4i32 4525 777U, // UHSUBv8i16 4526 1801U, // UHSUBv8i8 4527 18689U, // UMADDLrrr 4528 1033U, // UMAXPv16i8 4529 1289U, // UMAXPv2i32 4530 1545U, // UMAXPv4i16 4531 521U, // UMAXPv4i32 4532 777U, // UMAXPv8i16 4533 1801U, // UMAXPv8i8 4534 0U, // UMAXVv16i8v 4535 0U, // UMAXVv4i16v 4536 0U, // UMAXVv4i32v 4537 0U, // UMAXVv8i16v 4538 0U, // UMAXVv8i8v 4539 1033U, // UMAXv16i8 4540 1289U, // UMAXv2i32 4541 1545U, // UMAXv4i16 4542 521U, // UMAXv4i32 4543 777U, // UMAXv8i16 4544 1801U, // UMAXv8i8 4545 1033U, // UMINPv16i8 4546 1289U, // UMINPv2i32 4547 1545U, // UMINPv4i16 4548 521U, // UMINPv4i32 4549 777U, // UMINPv8i16 4550 1801U, // UMINPv8i8 4551 0U, // UMINVv16i8v 4552 0U, // UMINVv4i16v 4553 0U, // UMINVv4i32v 4554 0U, // UMINVv8i16v 4555 0U, // UMINVv8i8v 4556 1033U, // UMINv16i8 4557 1289U, // UMINv2i32 4558 1545U, // UMINv4i16 4559 521U, // UMINv4i32 4560 777U, // UMINv8i16 4561 1801U, // UMINv8i8 4562 1041U, // UMLALv16i8_v8i16 4563 27665U, // UMLALv2i32_indexed 4564 1297U, // UMLALv2i32_v2i64 4565 28945U, // UMLALv4i16_indexed 4566 1553U, // UMLALv4i16_v4i32 4567 27665U, // UMLALv4i32_indexed 4568 529U, // UMLALv4i32_v2i64 4569 28945U, // UMLALv8i16_indexed 4570 785U, // UMLALv8i16_v4i32 4571 1809U, // UMLALv8i8_v8i16 4572 1041U, // UMLSLv16i8_v8i16 4573 27665U, // UMLSLv2i32_indexed 4574 1297U, // UMLSLv2i32_v2i64 4575 28945U, // UMLSLv4i16_indexed 4576 1553U, // UMLSLv4i16_v4i32 4577 27665U, // UMLSLv4i32_indexed 4578 529U, // UMLSLv4i32_v2i64 4579 28945U, // UMLSLv8i16_indexed 4580 785U, // UMLSLv8i16_v4i32 4581 1809U, // UMLSLv8i8_v8i16 4582 75U, // UMOVvi16 4583 75U, // UMOVvi32 4584 75U, // UMOVvi64 4585 75U, // UMOVvi8 4586 18689U, // UMSUBLrrr 4587 1U, // UMULHrr 4588 1033U, // UMULLv16i8_v8i16 4589 35849U, // UMULLv2i32_indexed 4590 1289U, // UMULLv2i32_v2i64 4591 37129U, // UMULLv4i16_indexed 4592 1545U, // UMULLv4i16_v4i32 4593 35849U, // UMULLv4i32_indexed 4594 521U, // UMULLv4i32_v2i64 4595 37129U, // UMULLv8i16_indexed 4596 777U, // UMULLv8i16_v4i32 4597 1801U, // UMULLv8i8_v8i16 4598 1033U, // UQADDv16i8 4599 1U, // UQADDv1i16 4600 1U, // UQADDv1i32 4601 1U, // UQADDv1i64 4602 1U, // UQADDv1i8 4603 1289U, // UQADDv2i32 4604 265U, // UQADDv2i64 4605 1545U, // UQADDv4i16 4606 521U, // UQADDv4i32 4607 777U, // UQADDv8i16 4608 1801U, // UQADDv8i8 4609 1033U, // UQRSHLv16i8 4610 1U, // UQRSHLv1i16 4611 1U, // UQRSHLv1i32 4612 1U, // UQRSHLv1i64 4613 1U, // UQRSHLv1i8 4614 1289U, // UQRSHLv2i32 4615 265U, // UQRSHLv2i64 4616 1545U, // UQRSHLv4i16 4617 521U, // UQRSHLv4i32 4618 777U, // UQRSHLv8i16 4619 1801U, // UQRSHLv8i8 4620 1U, // UQRSHRNb 4621 1U, // UQRSHRNh 4622 1U, // UQRSHRNs 4623 65U, // UQRSHRNv16i8_shift 4624 1U, // UQRSHRNv2i32_shift 4625 1U, // UQRSHRNv4i16_shift 4626 65U, // UQRSHRNv4i32_shift 4627 65U, // UQRSHRNv8i16_shift 4628 1U, // UQRSHRNv8i8_shift 4629 1U, // UQSHLb 4630 1U, // UQSHLd 4631 1U, // UQSHLh 4632 1U, // UQSHLs 4633 1033U, // UQSHLv16i8 4634 1U, // UQSHLv16i8_shift 4635 1U, // UQSHLv1i16 4636 1U, // UQSHLv1i32 4637 1U, // UQSHLv1i64 4638 1U, // UQSHLv1i8 4639 1289U, // UQSHLv2i32 4640 1U, // UQSHLv2i32_shift 4641 265U, // UQSHLv2i64 4642 1U, // UQSHLv2i64_shift 4643 1545U, // UQSHLv4i16 4644 1U, // UQSHLv4i16_shift 4645 521U, // UQSHLv4i32 4646 1U, // UQSHLv4i32_shift 4647 777U, // UQSHLv8i16 4648 1U, // UQSHLv8i16_shift 4649 1801U, // UQSHLv8i8 4650 1U, // UQSHLv8i8_shift 4651 1U, // UQSHRNb 4652 1U, // UQSHRNh 4653 1U, // UQSHRNs 4654 65U, // UQSHRNv16i8_shift 4655 1U, // UQSHRNv2i32_shift 4656 1U, // UQSHRNv4i16_shift 4657 65U, // UQSHRNv4i32_shift 4658 65U, // UQSHRNv8i16_shift 4659 1U, // UQSHRNv8i8_shift 4660 1033U, // UQSUBv16i8 4661 1U, // UQSUBv1i16 4662 1U, // UQSUBv1i32 4663 1U, // UQSUBv1i64 4664 1U, // UQSUBv1i8 4665 1289U, // UQSUBv2i32 4666 265U, // UQSUBv2i64 4667 1545U, // UQSUBv4i16 4668 521U, // UQSUBv4i32 4669 777U, // UQSUBv8i16 4670 1801U, // UQSUBv8i8 4671 0U, // UQXTNv16i8 4672 0U, // UQXTNv1i16 4673 0U, // UQXTNv1i32 4674 0U, // UQXTNv1i8 4675 0U, // UQXTNv2i32 4676 0U, // UQXTNv4i16 4677 0U, // UQXTNv4i32 4678 0U, // UQXTNv8i16 4679 0U, // UQXTNv8i8 4680 0U, // URECPEv2i32 4681 0U, // URECPEv4i32 4682 1033U, // URHADDv16i8 4683 1289U, // URHADDv2i32 4684 1545U, // URHADDv4i16 4685 521U, // URHADDv4i32 4686 777U, // URHADDv8i16 4687 1801U, // URHADDv8i8 4688 1033U, // URSHLv16i8 4689 1U, // URSHLv1i64 4690 1289U, // URSHLv2i32 4691 265U, // URSHLv2i64 4692 1545U, // URSHLv4i16 4693 521U, // URSHLv4i32 4694 777U, // URSHLv8i16 4695 1801U, // URSHLv8i8 4696 1U, // URSHRd 4697 1U, // URSHRv16i8_shift 4698 1U, // URSHRv2i32_shift 4699 1U, // URSHRv2i64_shift 4700 1U, // URSHRv4i16_shift 4701 1U, // URSHRv4i32_shift 4702 1U, // URSHRv8i16_shift 4703 1U, // URSHRv8i8_shift 4704 0U, // URSQRTEv2i32 4705 0U, // URSQRTEv4i32 4706 65U, // URSRAd 4707 65U, // URSRAv16i8_shift 4708 65U, // URSRAv2i32_shift 4709 65U, // URSRAv2i64_shift 4710 65U, // URSRAv4i16_shift 4711 65U, // URSRAv4i32_shift 4712 65U, // URSRAv8i16_shift 4713 65U, // URSRAv8i8_shift 4714 1U, // USHLLv16i8_shift 4715 1U, // USHLLv2i32_shift 4716 1U, // USHLLv4i16_shift 4717 1U, // USHLLv4i32_shift 4718 1U, // USHLLv8i16_shift 4719 1U, // USHLLv8i8_shift 4720 1033U, // USHLv16i8 4721 1U, // USHLv1i64 4722 1289U, // USHLv2i32 4723 265U, // USHLv2i64 4724 1545U, // USHLv4i16 4725 521U, // USHLv4i32 4726 777U, // USHLv8i16 4727 1801U, // USHLv8i8 4728 1U, // USHRd 4729 1U, // USHRv16i8_shift 4730 1U, // USHRv2i32_shift 4731 1U, // USHRv2i64_shift 4732 1U, // USHRv4i16_shift 4733 1U, // USHRv4i32_shift 4734 1U, // USHRv8i16_shift 4735 1U, // USHRv8i8_shift 4736 0U, // USQADDv16i8 4737 0U, // USQADDv1i16 4738 0U, // USQADDv1i32 4739 0U, // USQADDv1i64 4740 0U, // USQADDv1i8 4741 0U, // USQADDv2i32 4742 0U, // USQADDv2i64 4743 0U, // USQADDv4i16 4744 0U, // USQADDv4i32 4745 0U, // USQADDv8i16 4746 0U, // USQADDv8i8 4747 65U, // USRAd 4748 65U, // USRAv16i8_shift 4749 65U, // USRAv2i32_shift 4750 65U, // USRAv2i64_shift 4751 65U, // USRAv4i16_shift 4752 65U, // USRAv4i32_shift 4753 65U, // USRAv8i16_shift 4754 65U, // USRAv8i8_shift 4755 1033U, // USUBLv16i8_v8i16 4756 1289U, // USUBLv2i32_v2i64 4757 1545U, // USUBLv4i16_v4i32 4758 521U, // USUBLv4i32_v2i64 4759 777U, // USUBLv8i16_v4i32 4760 1801U, // USUBLv8i8_v8i16 4761 1033U, // USUBWv16i8_v8i16 4762 1289U, // USUBWv2i32_v2i64 4763 1545U, // USUBWv4i16_v4i32 4764 521U, // USUBWv4i32_v2i64 4765 777U, // USUBWv8i16_v4i32 4766 1801U, // USUBWv8i8_v8i16 4767 1033U, // UZP1v16i8 4768 1289U, // UZP1v2i32 4769 265U, // UZP1v2i64 4770 1545U, // UZP1v4i16 4771 521U, // UZP1v4i32 4772 777U, // UZP1v8i16 4773 1801U, // UZP1v8i8 4774 1033U, // UZP2v16i8 4775 1289U, // UZP2v2i32 4776 265U, // UZP2v2i64 4777 1545U, // UZP2v4i16 4778 521U, // UZP2v4i32 4779 777U, // UZP2v8i16 4780 1801U, // UZP2v8i8 4781 0U, // XTNv16i8 4782 0U, // XTNv2i32 4783 0U, // XTNv4i16 4784 0U, // XTNv4i32 4785 0U, // XTNv8i16 4786 0U, // XTNv8i8 4787 1033U, // ZIP1v16i8 4788 1289U, // ZIP1v2i32 4789 265U, // ZIP1v2i64 4790 1545U, // ZIP1v4i16 4791 521U, // ZIP1v4i32 4792 777U, // ZIP1v8i16 4793 1801U, // ZIP1v8i8 4794 1033U, // ZIP2v16i8 4795 1289U, // ZIP2v2i32 4796 265U, // ZIP2v2i64 4797 1545U, // ZIP2v4i16 4798 521U, // ZIP2v4i32 4799 777U, // ZIP2v8i16 4800 1801U, // ZIP2v8i8 4801 0U 4802 }; 4803 4804#ifndef CAPSTONE_DIET 4805 static const char AsmStrs[] = { 4806 /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, 4807 /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, 4808 /* 20 */ 'l', 'd', '1', 9, 0, 4809 /* 25 */ 't', 'r', 'n', '1', 9, 0, 4810 /* 31 */ 'z', 'i', 'p', '1', 9, 0, 4811 /* 37 */ 'u', 'z', 'p', '1', 9, 0, 4812 /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0, 4813 /* 50 */ 's', 't', '1', 9, 0, 4814 /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, 4815 /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, 4816 /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0, 4817 /* 82 */ 'l', 'd', '2', 9, 0, 4818 /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, 4819 /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, 4820 /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, 4821 /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, 4822 /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, 4823 /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, 4824 /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, 4825 /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, 4826 /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, 4827 /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, 4828 /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, 4829 /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, 4830 /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, 4831 /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, 4832 /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, 4833 /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, 4834 /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, 4835 /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, 4836 /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, 4837 /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, 4838 /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, 4839 /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, 4840 /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, 4841 /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, 4842 /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, 4843 /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, 4844 /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, 4845 /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, 4846 /* 327 */ 't', 'r', 'n', '2', 9, 0, 4847 /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, 4848 /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, 4849 /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, 4850 /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, 4851 /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, 4852 /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, 4853 /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, 4854 /* 396 */ 'z', 'i', 'p', '2', 9, 0, 4855 /* 402 */ 'u', 'z', 'p', '2', 9, 0, 4856 /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0, 4857 /* 415 */ 's', 't', '2', 9, 0, 4858 /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, 4859 /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, 4860 /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, 4861 /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, 4862 /* 452 */ 'l', 'd', '3', 9, 0, 4863 /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0, 4864 /* 464 */ 's', 't', '3', 9, 0, 4865 /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0, 4866 /* 476 */ 'l', 'd', '4', 9, 0, 4867 /* 481 */ 's', 't', '4', 9, 0, 4868 /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0, 4869 /* 493 */ 's', 'a', 'b', 'a', 9, 0, 4870 /* 499 */ 'u', 'a', 'b', 'a', 9, 0, 4871 /* 505 */ 'f', 'm', 'l', 'a', 9, 0, 4872 /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0, 4873 /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0, 4874 /* 525 */ 's', 's', 'r', 'a', 9, 0, 4875 /* 531 */ 'u', 's', 'r', 'a', 9, 0, 4876 /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, 4877 /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, 4878 /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, 4879 /* 562 */ 'd', 'm', 'b', 9, 0, 4880 /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0, 4881 /* 574 */ 'l', 'd', 'r', 'b', 9, 0, 4882 /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0, 4883 /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0, 4884 /* 594 */ 's', 't', 'r', 'b', 9, 0, 4885 /* 600 */ 's', 't', 't', 'r', 'b', 9, 0, 4886 /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0, 4887 /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0, 4888 /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, 4889 /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0, 4890 /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, 4891 /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0, 4892 /* 651 */ 'd', 's', 'b', 9, 0, 4893 /* 656 */ 'i', 's', 'b', 9, 0, 4894 /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0, 4895 /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, 4896 /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, 4897 /* 684 */ 'f', 's', 'u', 'b', 9, 0, 4898 /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0, 4899 /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0, 4900 /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0, 4901 /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, 4902 /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0, 4903 /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0, 4904 /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0, 4905 /* 740 */ 's', 'b', 'c', 9, 0, 4906 /* 745 */ 'a', 'd', 'c', 9, 0, 4907 /* 750 */ 'b', 'i', 'c', 9, 0, 4908 /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, 4909 /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0, 4910 /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0, 4911 /* 777 */ 'h', 'v', 'c', 9, 0, 4912 /* 782 */ 's', 'v', 'c', 9, 0, 4913 /* 787 */ 'f', 'a', 'b', 'd', 9, 0, 4914 /* 793 */ 's', 'a', 'b', 'd', 9, 0, 4915 /* 799 */ 'u', 'a', 'b', 'd', 9, 0, 4916 /* 805 */ 'f', 'a', 'd', 'd', 9, 0, 4917 /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, 4918 /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, 4919 /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0, 4920 /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0, 4921 /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0, 4922 /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, 4923 /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, 4924 /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, 4925 /* 872 */ 'a', 'n', 'd', 9, 0, 4926 /* 877 */ 'a', 'e', 's', 'd', 9, 0, 4927 /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0, 4928 /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0, 4929 /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0, 4930 /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, 4931 /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, 4932 /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, 4933 /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0, 4934 /* 935 */ 'a', 'e', 's', 'e', 9, 0, 4935 /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, 4936 /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, 4937 /* 959 */ 'b', 'i', 'f', 9, 0, 4938 /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0, 4939 /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0, 4940 /* 978 */ 'f', 'n', 'e', 'g', 9, 0, 4941 /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0, 4942 /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0, 4943 /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0, 4944 /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, 4945 /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, 4946 /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, 4947 /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, 4948 /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, 4949 /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0, 4950 /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0, 4951 /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0, 4952 /* 1071 */ 'l', 'd', 'r', 'h', 9, 0, 4953 /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0, 4954 /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0, 4955 /* 1091 */ 's', 't', 'r', 'h', 9, 0, 4956 /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0, 4957 /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0, 4958 /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0, 4959 /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, 4960 /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0, 4961 /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, 4962 /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0, 4963 /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0, 4964 /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, 4965 /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, 4966 /* 1171 */ 'c', 'm', 'h', 'i', 9, 0, 4967 /* 1177 */ 's', 'l', 'i', 9, 0, 4968 /* 1182 */ 'm', 'v', 'n', 'i', 9, 0, 4969 /* 1188 */ 's', 'r', 'i', 9, 0, 4970 /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, 4971 /* 1201 */ 'm', 'o', 'v', 'i', 9, 0, 4972 /* 1207 */ 'b', 'r', 'k', 9, 0, 4973 /* 1212 */ 'm', 'o', 'v', 'k', 9, 0, 4974 /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0, 4975 /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0, 4976 /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, 4977 /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0, 4978 /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0, 4979 /* 1255 */ 't', 'b', 'l', 9, 0, 4980 /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, 4981 /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, 4982 /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0, 4983 /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0, 4984 /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0, 4985 /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0, 4986 /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, 4987 /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, 4988 /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0, 4989 /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0, 4990 /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0, 4991 /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0, 4992 /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0, 4993 /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, 4994 /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, 4995 /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0, 4996 /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0, 4997 /* 1385 */ 's', 's', 'h', 'l', 9, 0, 4998 /* 1391 */ 'u', 's', 'h', 'l', 9, 0, 4999 /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0, 5000 /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0, 5001 /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, 5002 /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0, 5003 /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0, 5004 /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0, 5005 /* 1441 */ 'b', 's', 'l', 9, 0, 5006 /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, 5007 /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0, 5008 /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0, 5009 /* 1469 */ 's', 'y', 's', 'l', 9, 0, 5010 /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0, 5011 /* 1482 */ 'f', 'm', 'u', 'l', 9, 0, 5012 /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0, 5013 /* 1495 */ 'p', 'm', 'u', 'l', 9, 0, 5014 /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0, 5015 /* 1508 */ 's', 'b', 'f', 'm', 9, 0, 5016 /* 1514 */ 'u', 'b', 'f', 'm', 9, 0, 5017 /* 1520 */ 'p', 'r', 'f', 'm', 9, 0, 5018 /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, 5019 /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, 5020 /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, 5021 /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0, 5022 /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, 5023 /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, 5024 /* 1573 */ 'f', 'm', 'i', 'n', 9, 0, 5025 /* 1579 */ 's', 'm', 'i', 'n', 9, 0, 5026 /* 1585 */ 'u', 'm', 'i', 'n', 9, 0, 5027 /* 1591 */ 'c', 'c', 'm', 'n', 9, 0, 5028 /* 1597 */ 'e', 'o', 'n', 9, 0, 5029 /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, 5030 /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, 5031 /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, 5032 /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, 5033 /* 1636 */ 'o', 'r', 'n', 9, 0, 5034 /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, 5035 /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0, 5036 /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0, 5037 /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0, 5038 /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, 5039 /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, 5040 /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, 5041 /* 1697 */ 'm', 'o', 'v', 'n', 9, 0, 5042 /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, 5043 /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0, 5044 /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0, 5045 /* 1725 */ 'l', 'd', 'p', 9, 0, 5046 /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, 5047 /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, 5048 /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, 5049 /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, 5050 /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0, 5051 /* 1769 */ 'f', 'c', 'm', 'p', 9, 0, 5052 /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, 5053 /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, 5054 /* 1793 */ 'l', 'd', 'n', 'p', 9, 0, 5055 /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0, 5056 /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0, 5057 /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0, 5058 /* 1820 */ 's', 't', 'n', 'p', 9, 0, 5059 /* 1826 */ 'a', 'd', 'r', 'p', 9, 0, 5060 /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, 5061 /* 1840 */ 's', 't', 'p', 9, 0, 5062 /* 1845 */ 'd', 'u', 'p', 9, 0, 5063 /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0, 5064 /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0, 5065 /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0, 5066 /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0, 5067 /* 1878 */ 'l', 'd', 'x', 'p', 9, 0, 5068 /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0, 5069 /* 1891 */ 's', 't', 'x', 'p', 9, 0, 5070 /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0, 5071 /* 1904 */ 'l', 'd', '1', 'r', 9, 0, 5072 /* 1910 */ 'l', 'd', '2', 'r', 9, 0, 5073 /* 1916 */ 'l', 'd', '3', 'r', 9, 0, 5074 /* 1922 */ 'l', 'd', '4', 'r', 9, 0, 5075 /* 1928 */ 'l', 'd', 'a', 'r', 9, 0, 5076 /* 1934 */ 'b', 'r', 9, 0, 5077 /* 1938 */ 'a', 'd', 'r', 9, 0, 5078 /* 1943 */ 'l', 'd', 'r', 9, 0, 5079 /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0, 5080 /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0, 5081 /* 1962 */ 's', 's', 'h', 'r', 9, 0, 5082 /* 1968 */ 'u', 's', 'h', 'r', 9, 0, 5083 /* 1974 */ 'b', 'l', 'r', 9, 0, 5084 /* 1979 */ 's', 't', 'l', 'r', 9, 0, 5085 /* 1985 */ 'e', 'o', 'r', 9, 0, 5086 /* 1990 */ 'r', 'o', 'r', 9, 0, 5087 /* 1995 */ 'o', 'r', 'r', 9, 0, 5088 /* 2000 */ 'a', 's', 'r', 9, 0, 5089 /* 2005 */ 'l', 's', 'r', 9, 0, 5090 /* 2010 */ 'm', 's', 'r', 9, 0, 5091 /* 2015 */ 'l', 'd', 't', 'r', 9, 0, 5092 /* 2021 */ 's', 't', 'r', 9, 0, 5093 /* 2026 */ 's', 't', 't', 'r', 9, 0, 5094 /* 2032 */ 'e', 'x', 't', 'r', 9, 0, 5095 /* 2038 */ 'l', 'd', 'u', 'r', 9, 0, 5096 /* 2044 */ 's', 't', 'u', 'r', 9, 0, 5097 /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0, 5098 /* 2057 */ 'l', 'd', 'x', 'r', 9, 0, 5099 /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0, 5100 /* 2070 */ 's', 't', 'x', 'r', 9, 0, 5101 /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, 5102 /* 2084 */ 'f', 'a', 'b', 's', 9, 0, 5103 /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0, 5104 /* 2097 */ 's', 'u', 'b', 's', 9, 0, 5105 /* 2103 */ 's', 'b', 'c', 's', 9, 0, 5106 /* 2109 */ 'a', 'd', 'c', 's', 9, 0, 5107 /* 2115 */ 'b', 'i', 'c', 's', 9, 0, 5108 /* 2121 */ 'a', 'd', 'd', 's', 9, 0, 5109 /* 2127 */ 'a', 'n', 'd', 's', 9, 0, 5110 /* 2133 */ 'c', 'm', 'h', 's', 9, 0, 5111 /* 2139 */ 'c', 'l', 's', 9, 0, 5112 /* 2144 */ 'f', 'm', 'l', 's', 9, 0, 5113 /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, 5114 /* 2158 */ 'i', 'n', 's', 9, 0, 5115 /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, 5116 /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, 5117 /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, 5118 /* 2187 */ 'm', 'r', 's', 9, 0, 5119 /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, 5120 /* 2201 */ 's', 'y', 's', 9, 0, 5121 /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, 5122 /* 2214 */ 'r', 'e', 't', 9, 0, 5123 /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0, 5124 /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0, 5125 /* 2233 */ 'r', 'b', 'i', 't', 9, 0, 5126 /* 2239 */ 'h', 'l', 't', 9, 0, 5127 /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0, 5128 /* 2251 */ 'c', 'n', 't', 9, 0, 5129 /* 2256 */ 'n', 'o', 't', 9, 0, 5130 /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0, 5131 /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0, 5132 /* 2275 */ 'f', 'c', 'v', 't', 9, 0, 5133 /* 2281 */ 'e', 'x', 't', 9, 0, 5134 /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, 5135 /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, 5136 /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, 5137 /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, 5138 /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, 5139 /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, 5140 /* 2334 */ 'a', 'd', 'd', 'v', 9, 0, 5141 /* 2340 */ 'r', 'e', 'v', 9, 0, 5142 /* 2345 */ 'f', 'd', 'i', 'v', 9, 0, 5143 /* 2351 */ 's', 'd', 'i', 'v', 9, 0, 5144 /* 2357 */ 'u', 'd', 'i', 'v', 9, 0, 5145 /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, 5146 /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, 5147 /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, 5148 /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, 5149 /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0, 5150 /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0, 5151 /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0, 5152 /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0, 5153 /* 2425 */ 'f', 'm', 'o', 'v', 9, 0, 5154 /* 2431 */ 's', 'm', 'o', 'v', 9, 0, 5155 /* 2437 */ 'u', 'm', 'o', 'v', 9, 0, 5156 /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0, 5157 /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0, 5158 /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0, 5159 /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, 5160 /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0, 5161 /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0, 5162 /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, 5163 /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0, 5164 /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0, 5165 /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0, 5166 /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0, 5167 /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, 5168 /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, 5169 /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, 5170 /* 2547 */ 'f', 'm', 'a', 'x', 9, 0, 5171 /* 2553 */ 's', 'm', 'a', 'x', 9, 0, 5172 /* 2559 */ 'u', 'm', 'a', 'x', 9, 0, 5173 /* 2565 */ 't', 'b', 'x', 9, 0, 5174 /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, 5175 /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0, 5176 /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0, 5177 /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, 5178 /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, 5179 /* 2609 */ 'c', 'b', 'z', 9, 0, 5180 /* 2614 */ 't', 'b', 'z', 9, 0, 5181 /* 2619 */ 'c', 'l', 'z', 9, 0, 5182 /* 2624 */ 'c', 'b', 'n', 'z', 9, 0, 5183 /* 2630 */ 't', 'b', 'n', 'z', 9, 0, 5184 /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, 5185 /* 2644 */ 'm', 'o', 'v', 'z', 9, 0, 5186 /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, 5187 /* 2664 */ 'h', 'i', 'n', 't', 32, 0, 5188 /* 2670 */ 'b', '.', 0, 5189 /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, 5190 /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, 5191 /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, 5192 /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, 5193 /* 2718 */ 'd', 'r', 'p', 's', 0, 5194 /* 2723 */ 'e', 'r', 'e', 't', 0, 5195 }; 5196#endif 5197 5198 // Emit the opcode for the instruction. 5199 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; 5200 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; 5201 uint64_t Bits = (Bits2 << 32) | Bits1; 5202 // assert(Bits != 0 && "Cannot print this instruction."); 5203#ifndef CAPSTONE_DIET 5204 SStream_concat0(O, AsmStrs+(Bits & 4095)-1); 5205#endif 5206 5207 5208 // Fragment 0 encoded into 6 bits for 40 unique commands. 5209 //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63); 5210 switch ((Bits >> 12) & 63) { 5211 default: // unreachable. 5212 case 0: 5213 // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET 5214 return; 5215 break; 5216 case 1: 5217 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... 5218 printVRegOperand(MI, 0, O); 5219 break; 5220 case 2: 5221 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... 5222 printOperand(MI, 0, O); 5223 break; 5224 case 3: 5225 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... 5226 printVRegOperand(MI, 1, O); 5227 break; 5228 case 4: 5229 // B, BL 5230 printAlignedLabel(MI, 0, O); 5231 return; 5232 break; 5233 case 5: 5234 // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC 5235 printHexImm(MI, 0, O); 5236 return; 5237 break; 5238 case 6: 5239 // Bcc 5240 printCondCode(MI, 0, O); 5241 SStream_concat0(O, "\t"); 5242 printAlignedLabel(MI, 1, O); 5243 return; 5244 break; 5245 case 7: 5246 // DMB, DSB, ISB 5247 printBarrierOption(MI, 0, O); 5248 return; 5249 break; 5250 case 8: 5251 // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind... 5252 printOperand(MI, 1, O); 5253 break; 5254 case 9: 5255 // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... 5256 printTypedVectorList(MI, 0, O, 16, 'b', MRI); 5257 SStream_concat0(O, ", ["); 5258 set_mem_access(MI, true); 5259 printOperand(MI, 1, O); 5260 SStream_concat0(O, "]"); 5261 set_mem_access(MI, false); 5262 return; 5263 break; 5264 case 10: 5265 // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... 5266 printTypedVectorList(MI, 1, O, 16, 'b', MRI); 5267 SStream_concat0(O, ", ["); 5268 set_mem_access(MI, true); 5269 printOperand(MI, 2, O); 5270 SStream_concat0(O, "], "); 5271 set_mem_access(MI, false); 5272 break; 5273 case 11: 5274 // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... 5275 printTypedVectorList(MI, 0, O, 1, 'd', MRI); 5276 SStream_concat0(O, ", ["); 5277 set_mem_access(MI, true); 5278 printOperand(MI, 1, O); 5279 SStream_concat0(O, "]"); 5280 set_mem_access(MI, false); 5281 return; 5282 break; 5283 case 12: 5284 // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... 5285 printTypedVectorList(MI, 1, O, 1, 'd', MRI); 5286 SStream_concat0(O, ", ["); 5287 set_mem_access(MI, true); 5288 printOperand(MI, 2, O); 5289 SStream_concat0(O, "], "); 5290 set_mem_access(MI, false); 5291 break; 5292 case 13: 5293 // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... 5294 printTypedVectorList(MI, 0, O, 2, 'd', MRI); 5295 SStream_concat0(O, ", ["); 5296 set_mem_access(MI, true); 5297 printOperand(MI, 1, O); 5298 SStream_concat0(O, "]"); 5299 set_mem_access(MI, false); 5300 return; 5301 break; 5302 case 14: 5303 // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... 5304 printTypedVectorList(MI, 1, O, 2, 'd', MRI); 5305 SStream_concat0(O, ", ["); 5306 set_mem_access(MI, true); 5307 printOperand(MI, 2, O); 5308 SStream_concat0(O, "], "); 5309 set_mem_access(MI, false); 5310 break; 5311 case 15: 5312 // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... 5313 printTypedVectorList(MI, 0, O, 2, 's', MRI); 5314 SStream_concat0(O, ", ["); 5315 set_mem_access(MI, true); 5316 printOperand(MI, 1, O); 5317 SStream_concat0(O, "]"); 5318 set_mem_access(MI, false); 5319 return; 5320 break; 5321 case 16: 5322 // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... 5323 printTypedVectorList(MI, 1, O, 2, 's', MRI); 5324 SStream_concat0(O, ", ["); 5325 set_mem_access(MI, true); 5326 printOperand(MI, 2, O); 5327 SStream_concat0(O, "], "); 5328 set_mem_access(MI, false); 5329 break; 5330 case 17: 5331 // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... 5332 printTypedVectorList(MI, 0, O, 4, 'h', MRI); 5333 SStream_concat0(O, ", ["); 5334 set_mem_access(MI, true); 5335 printOperand(MI, 1, O); 5336 SStream_concat0(O, "]"); 5337 set_mem_access(MI, false); 5338 return; 5339 break; 5340 case 18: 5341 // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... 5342 printTypedVectorList(MI, 1, O, 4, 'h', MRI); 5343 SStream_concat0(O, ", ["); 5344 set_mem_access(MI, true); 5345 printOperand(MI, 2, O); 5346 SStream_concat0(O, "], "); 5347 set_mem_access(MI, false); 5348 break; 5349 case 19: 5350 // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... 5351 printTypedVectorList(MI, 0, O, 4, 's', MRI); 5352 SStream_concat0(O, ", ["); 5353 set_mem_access(MI, true); 5354 printOperand(MI, 1, O); 5355 SStream_concat0(O, "]"); 5356 set_mem_access(MI, false); 5357 return; 5358 break; 5359 case 20: 5360 // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... 5361 printTypedVectorList(MI, 1, O, 4, 's', MRI); 5362 SStream_concat0(O, ", ["); 5363 set_mem_access(MI, true); 5364 printOperand(MI, 2, O); 5365 SStream_concat0(O, "], "); 5366 set_mem_access(MI, false); 5367 break; 5368 case 21: 5369 // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... 5370 printTypedVectorList(MI, 0, O, 8, 'b', MRI); 5371 SStream_concat0(O, ", ["); 5372 set_mem_access(MI, true); 5373 printOperand(MI, 1, O); 5374 SStream_concat0(O, "]"); 5375 set_mem_access(MI, false); 5376 return; 5377 break; 5378 case 22: 5379 // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... 5380 printTypedVectorList(MI, 1, O, 8, 'b', MRI); 5381 SStream_concat0(O, ", ["); 5382 set_mem_access(MI, true); 5383 printOperand(MI, 2, O); 5384 SStream_concat0(O, "], "); 5385 set_mem_access(MI, false); 5386 break; 5387 case 23: 5388 // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... 5389 printTypedVectorList(MI, 0, O, 8, 'h', MRI); 5390 SStream_concat0(O, ", ["); 5391 set_mem_access(MI, true); 5392 printOperand(MI, 1, O); 5393 SStream_concat0(O, "]"); 5394 set_mem_access(MI, false); 5395 return; 5396 break; 5397 case 24: 5398 // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... 5399 printTypedVectorList(MI, 1, O, 8, 'h', MRI); 5400 SStream_concat0(O, ", ["); 5401 set_mem_access(MI, true); 5402 printOperand(MI, 2, O); 5403 SStream_concat0(O, "], "); 5404 set_mem_access(MI, false); 5405 break; 5406 case 25: 5407 // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... 5408 printTypedVectorList(MI, 1, O, 0, 'h', MRI); 5409 printVectorIndex(MI, 2, O); 5410 SStream_concat0(O, ", ["); 5411 set_mem_access(MI, true); 5412 printOperand(MI, 3, O); 5413 break; 5414 case 26: 5415 // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST 5416 printTypedVectorList(MI, 2, O, 0, 'h', MRI); 5417 printVectorIndex(MI, 3, O); 5418 SStream_concat0(O, ", ["); 5419 set_mem_access(MI, true); 5420 printOperand(MI, 4, O); 5421 SStream_concat0(O, "], "); 5422 set_mem_access(MI, false); 5423 break; 5424 case 27: 5425 // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... 5426 printTypedVectorList(MI, 1, O, 0, 's', MRI); 5427 printVectorIndex(MI, 2, O); 5428 SStream_concat0(O, ", ["); 5429 set_mem_access(MI, true); 5430 printOperand(MI, 3, O); 5431 break; 5432 case 28: 5433 // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST 5434 printTypedVectorList(MI, 2, O, 0, 's', MRI); 5435 printVectorIndex(MI, 3, O); 5436 SStream_concat0(O, ", ["); 5437 set_mem_access(MI, true); 5438 printOperand(MI, 4, O); 5439 SStream_concat0(O, "], "); 5440 set_mem_access(MI, false); 5441 break; 5442 case 29: 5443 // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... 5444 printTypedVectorList(MI, 1, O, 0, 'd', MRI); 5445 printVectorIndex(MI, 2, O); 5446 SStream_concat0(O, ", ["); 5447 set_mem_access(MI, true); 5448 printOperand(MI, 3, O); 5449 break; 5450 case 30: 5451 // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST 5452 printTypedVectorList(MI, 2, O, 0, 'd', MRI); 5453 printVectorIndex(MI, 3, O); 5454 SStream_concat0(O, ", ["); 5455 set_mem_access(MI, true); 5456 printOperand(MI, 4, O); 5457 SStream_concat0(O, "], "); 5458 set_mem_access(MI, false); 5459 break; 5460 case 31: 5461 // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... 5462 printTypedVectorList(MI, 1, O, 0, 'b', MRI); 5463 printVectorIndex(MI, 2, O); 5464 SStream_concat0(O, ", ["); 5465 set_mem_access(MI, true); 5466 printOperand(MI, 3, O); 5467 break; 5468 case 32: 5469 // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST 5470 printTypedVectorList(MI, 2, O, 0, 'b', MRI); 5471 printVectorIndex(MI, 3, O); 5472 SStream_concat0(O, ", ["); 5473 set_mem_access(MI, true); 5474 printOperand(MI, 4, O); 5475 SStream_concat0(O, "], "); 5476 set_mem_access(MI, false); 5477 break; 5478 case 33: 5479 // MSR 5480 printMSRSystemRegister(MI, 0, O); 5481 SStream_concat0(O, ", "); 5482 printOperand(MI, 1, O); 5483 return; 5484 break; 5485 case 34: 5486 // MSRpstate 5487 printSystemPStateField(MI, 0, O); 5488 SStream_concat0(O, ", "); 5489 printOperand(MI, 1, O); 5490 return; 5491 break; 5492 case 35: 5493 // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi 5494 printPrefetchOp(MI, 0, O); 5495 break; 5496 case 36: 5497 // ST1i16, ST2i16, ST3i16, ST4i16 5498 printTypedVectorList(MI, 0, O, 0, 'h', MRI); 5499 printVectorIndex(MI, 1, O); 5500 SStream_concat0(O, ", ["); 5501 set_mem_access(MI, true); 5502 printOperand(MI, 2, O); 5503 SStream_concat0(O, "]"); 5504 set_mem_access(MI, false); 5505 return; 5506 break; 5507 case 37: 5508 // ST1i32, ST2i32, ST3i32, ST4i32 5509 printTypedVectorList(MI, 0, O, 0, 's', MRI); 5510 printVectorIndex(MI, 1, O); 5511 SStream_concat0(O, ", ["); 5512 set_mem_access(MI, true); 5513 printOperand(MI, 2, O); 5514 SStream_concat0(O, "]"); 5515 set_mem_access(MI, false); 5516 return; 5517 break; 5518 case 38: 5519 // ST1i64, ST2i64, ST3i64, ST4i64 5520 printTypedVectorList(MI, 0, O, 0, 'd', MRI); 5521 printVectorIndex(MI, 1, O); 5522 SStream_concat0(O, ", ["); 5523 set_mem_access(MI, true); 5524 printOperand(MI, 2, O); 5525 SStream_concat0(O, "]"); 5526 set_mem_access(MI, false); 5527 return; 5528 break; 5529 case 39: 5530 // ST1i8, ST2i8, ST3i8, ST4i8 5531 printTypedVectorList(MI, 0, O, 0, 'b', MRI); 5532 printVectorIndex(MI, 1, O); 5533 SStream_concat0(O, ", ["); 5534 set_mem_access(MI, true); 5535 printOperand(MI, 2, O); 5536 SStream_concat0(O, "]"); 5537 set_mem_access(MI, false); 5538 return; 5539 break; 5540 } 5541 5542 5543 // Fragment 1 encoded into 6 bits for 41 unique commands. 5544 //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63); 5545 switch ((Bits >> 18) & 63) { 5546 default: // unreachable. 5547 case 0: 5548 // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... 5549 SStream_concat0(O, ".16b, "); 5550 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5551 break; 5552 case 1: 5553 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... 5554 SStream_concat0(O, ", "); 5555 break; 5556 case 2: 5557 // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... 5558 SStream_concat0(O, ".2s, "); 5559 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 5560 break; 5561 case 3: 5562 // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... 5563 SStream_concat0(O, ".2d, "); 5564 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5565 break; 5566 case 4: 5567 // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... 5568 SStream_concat0(O, ".4h, "); 5569 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 5570 break; 5571 case 5: 5572 // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... 5573 SStream_concat0(O, ".4s, "); 5574 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5575 break; 5576 case 6: 5577 // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... 5578 SStream_concat0(O, ".8h, "); 5579 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5580 break; 5581 case 7: 5582 // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... 5583 SStream_concat0(O, ".8b, "); 5584 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 5585 break; 5586 case 8: 5587 // BLR, BR, CLREX, RET, TLSDESCCALL 5588 return; 5589 break; 5590 case 9: 5591 // FCMPDri, FCMPEDri, FCMPESri, FCMPSri 5592 SStream_concat0(O, ", #0.0"); 5593 arm64_op_addFP(MI, 0.0); 5594 return; 5595 break; 5596 case 10: 5597 // FMOVXDHighr, INSvi64gpr, INSvi64lane 5598 SStream_concat0(O, ".d"); 5599 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 5600 printVectorIndex(MI, 2, O); 5601 SStream_concat0(O, ", "); 5602 break; 5603 case 11: 5604 // INSvi16gpr, INSvi16lane 5605 SStream_concat0(O, ".h"); 5606 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 5607 printVectorIndex(MI, 2, O); 5608 SStream_concat0(O, ", "); 5609 break; 5610 case 12: 5611 // INSvi32gpr, INSvi32lane 5612 SStream_concat0(O, ".s"); 5613 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 5614 printVectorIndex(MI, 2, O); 5615 SStream_concat0(O, ", "); 5616 break; 5617 case 13: 5618 // INSvi8gpr, INSvi8lane 5619 SStream_concat0(O, ".b"); 5620 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); 5621 printVectorIndex(MI, 2, O); 5622 SStream_concat0(O, ", "); 5623 break; 5624 case 14: 5625 // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... 5626 printPostIncOperand2(MI, 3, O, 64); 5627 return; 5628 break; 5629 case 15: 5630 // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... 5631 printPostIncOperand2(MI, 3, O, 32); 5632 return; 5633 break; 5634 case 16: 5635 // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... 5636 printPostIncOperand2(MI, 3, O, 16); 5637 return; 5638 break; 5639 case 17: 5640 // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... 5641 printPostIncOperand2(MI, 3, O, 8); 5642 return; 5643 break; 5644 case 18: 5645 // LD1Rv16b_POST, LD1Rv8b_POST 5646 printPostIncOperand2(MI, 3, O, 1); 5647 return; 5648 break; 5649 case 19: 5650 // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... 5651 printPostIncOperand2(MI, 3, O, 4); 5652 return; 5653 break; 5654 case 20: 5655 // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST 5656 printPostIncOperand2(MI, 3, O, 2); 5657 return; 5658 break; 5659 case 21: 5660 // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... 5661 printPostIncOperand2(MI, 3, O, 48); 5662 return; 5663 break; 5664 case 22: 5665 // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... 5666 printPostIncOperand2(MI, 3, O, 24); 5667 return; 5668 break; 5669 case 23: 5670 // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... 5671 SStream_concat0(O, "]"); 5672 set_mem_access(MI, false); 5673 return; 5674 break; 5675 case 24: 5676 // LD1i16_POST, LD2i8_POST 5677 printPostIncOperand2(MI, 5, O, 2); 5678 return; 5679 break; 5680 case 25: 5681 // LD1i32_POST, LD2i16_POST, LD4i8_POST 5682 printPostIncOperand2(MI, 5, O, 4); 5683 return; 5684 break; 5685 case 26: 5686 // LD1i64_POST, LD2i32_POST, LD4i16_POST 5687 printPostIncOperand2(MI, 5, O, 8); 5688 return; 5689 break; 5690 case 27: 5691 // LD1i8_POST 5692 printPostIncOperand2(MI, 5, O, 1); 5693 return; 5694 break; 5695 case 28: 5696 // LD2i64_POST, LD4i32_POST 5697 printPostIncOperand2(MI, 5, O, 16); 5698 return; 5699 break; 5700 case 29: 5701 // LD3Rv16b_POST, LD3Rv8b_POST 5702 printPostIncOperand2(MI, 3, O, 3); 5703 return; 5704 break; 5705 case 30: 5706 // LD3Rv2s_POST, LD3Rv4s_POST 5707 printPostIncOperand2(MI, 3, O, 12); 5708 return; 5709 break; 5710 case 31: 5711 // LD3Rv4h_POST, LD3Rv8h_POST 5712 printPostIncOperand2(MI, 3, O, 6); 5713 return; 5714 break; 5715 case 32: 5716 // LD3i16_POST 5717 printPostIncOperand2(MI, 5, O, 6); 5718 return; 5719 break; 5720 case 33: 5721 // LD3i32_POST 5722 printPostIncOperand2(MI, 5, O, 12); 5723 return; 5724 break; 5725 case 34: 5726 // LD3i64_POST 5727 printPostIncOperand2(MI, 5, O, 24); 5728 return; 5729 break; 5730 case 35: 5731 // LD3i8_POST 5732 printPostIncOperand2(MI, 5, O, 3); 5733 return; 5734 break; 5735 case 36: 5736 // LD4i64_POST 5737 printPostIncOperand2(MI, 5, O, 32); 5738 return; 5739 break; 5740 case 37: 5741 // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,... 5742 SStream_concat0(O, ", ["); 5743 set_mem_access(MI, true); 5744 break; 5745 case 38: 5746 // PMULLv1i64, PMULLv2i64 5747 SStream_concat0(O, ".1q, "); 5748 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); 5749 printVRegOperand(MI, 1, O); 5750 break; 5751 case 39: 5752 // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... 5753 SStream_concat0(O, ".1d, "); 5754 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5755 break; 5756 case 40: 5757 // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... 5758 SStream_concat0(O, "], "); 5759 set_mem_access(MI, false); 5760 break; 5761 } 5762 5763 5764 // Fragment 2 encoded into 5 bits for 28 unique commands. 5765 //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); 5766 switch ((Bits >> 24) & 31) { 5767 default: // unreachable. 5768 case 0: 5769 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... 5770 printVRegOperand(MI, 1, O); 5771 break; 5772 case 1: 5773 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD... 5774 printOperand(MI, 1, O); 5775 break; 5776 case 2: 5777 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... 5778 printVRegOperand(MI, 2, O); 5779 break; 5780 case 3: 5781 // ADRP 5782 printAdrpLabel(MI, 1, O); 5783 return; 5784 break; 5785 case 4: 5786 // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe... 5787 printOperand(MI, 2, O); 5788 break; 5789 case 5: 5790 // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... 5791 printHexImm(MI, 2, O); 5792 printShifter(MI, 3, O); 5793 return; 5794 break; 5795 case 6: 5796 // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... 5797 printAlignedLabel(MI, 1, O); 5798 return; 5799 break; 5800 case 7: 5801 // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns 5802 printFPImmOperand(MI, 1, O); 5803 return; 5804 break; 5805 case 8: 5806 // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr 5807 printOperand(MI, 3, O); 5808 return; 5809 break; 5810 case 9: 5811 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane 5812 printVRegOperand(MI, 3, O); 5813 break; 5814 case 10: 5815 // MOVID, MOVIv2d_ns 5816 printSIMDType10Operand(MI, 1, O); 5817 return; 5818 break; 5819 case 11: 5820 // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... 5821 printHexImm(MI, 1, O); 5822 break; 5823 case 12: 5824 // MRS 5825 printMRSSystemRegister(MI, 1, O); 5826 return; 5827 break; 5828 case 13: 5829 // PMULLv1i64 5830 SStream_concat0(O, ".1d, "); 5831 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5832 printVRegOperand(MI, 2, O); 5833 SStream_concat0(O, ".1d"); 5834 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5835 return; 5836 break; 5837 case 14: 5838 // PMULLv2i64 5839 SStream_concat0(O, ".2d, "); 5840 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5841 printVRegOperand(MI, 2, O); 5842 SStream_concat0(O, ".2d"); 5843 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5844 return; 5845 break; 5846 case 15: 5847 // ST1i16_POST, ST2i8_POST 5848 printPostIncOperand2(MI, 4, O, 2); 5849 return; 5850 break; 5851 case 16: 5852 // ST1i32_POST, ST2i16_POST, ST4i8_POST 5853 printPostIncOperand2(MI, 4, O, 4); 5854 return; 5855 break; 5856 case 17: 5857 // ST1i64_POST, ST2i32_POST, ST4i16_POST 5858 printPostIncOperand2(MI, 4, O, 8); 5859 return; 5860 break; 5861 case 18: 5862 // ST1i8_POST 5863 printPostIncOperand2(MI, 4, O, 1); 5864 return; 5865 break; 5866 case 19: 5867 // ST2i64_POST, ST4i32_POST 5868 printPostIncOperand2(MI, 4, O, 16); 5869 return; 5870 break; 5871 case 20: 5872 // ST3i16_POST 5873 printPostIncOperand2(MI, 4, O, 6); 5874 return; 5875 break; 5876 case 21: 5877 // ST3i32_POST 5878 printPostIncOperand2(MI, 4, O, 12); 5879 return; 5880 break; 5881 case 22: 5882 // ST3i64_POST 5883 printPostIncOperand2(MI, 4, O, 24); 5884 return; 5885 break; 5886 case 23: 5887 // ST3i8_POST 5888 printPostIncOperand2(MI, 4, O, 3); 5889 return; 5890 break; 5891 case 24: 5892 // ST4i64_POST 5893 printPostIncOperand2(MI, 4, O, 32); 5894 return; 5895 break; 5896 case 25: 5897 // SYSxt 5898 printSysCROperand(MI, 1, O); 5899 SStream_concat0(O, ", "); 5900 printSysCROperand(MI, 2, O); 5901 SStream_concat0(O, ", "); 5902 printOperand(MI, 3, O); 5903 SStream_concat0(O, ", "); 5904 printOperand(MI, 4, O); 5905 return; 5906 break; 5907 case 26: 5908 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... 5909 printTypedVectorList(MI, 1, O, 16, 'b', MRI); 5910 SStream_concat0(O, ", "); 5911 printVRegOperand(MI, 2, O); 5912 break; 5913 case 27: 5914 // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... 5915 printTypedVectorList(MI, 2, O, 16, 'b', MRI); 5916 SStream_concat0(O, ", "); 5917 printVRegOperand(MI, 3, O); 5918 break; 5919 } 5920 5921 5922 // Fragment 3 encoded into 6 bits for 42 unique commands. 5923 //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63); 5924 switch ((Bits >> 29) & 63) { 5925 default: // unreachable. 5926 case 0: 5927 // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... 5928 SStream_concat0(O, ".16b"); 5929 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5930 return; 5931 break; 5932 case 1: 5933 // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D... 5934 return; 5935 break; 5936 case 2: 5937 // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... 5938 SStream_concat0(O, ".2s"); 5939 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 5940 return; 5941 break; 5942 case 3: 5943 // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... 5944 SStream_concat0(O, ".2d"); 5945 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5946 return; 5947 break; 5948 case 4: 5949 // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v... 5950 SStream_concat0(O, ".4h"); 5951 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 5952 return; 5953 break; 5954 case 5: 5955 // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... 5956 SStream_concat0(O, ".4s"); 5957 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5958 return; 5959 break; 5960 case 6: 5961 // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v... 5962 SStream_concat0(O, ".8h"); 5963 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5964 return; 5965 break; 5966 case 7: 5967 // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... 5968 SStream_concat0(O, ".8b"); 5969 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 5970 return; 5971 break; 5972 case 8: 5973 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS... 5974 SStream_concat0(O, ", "); 5975 break; 5976 case 9: 5977 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... 5978 SStream_concat0(O, ".2d, "); 5979 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5980 break; 5981 case 10: 5982 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... 5983 SStream_concat0(O, ".4s, "); 5984 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5985 break; 5986 case 11: 5987 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... 5988 SStream_concat0(O, ".8h, "); 5989 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5990 break; 5991 case 12: 5992 // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... 5993 SStream_concat0(O, ".16b, "); 5994 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5995 break; 5996 case 13: 5997 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... 5998 SStream_concat0(O, ".2s, "); 5999 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6000 break; 6001 case 14: 6002 // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... 6003 SStream_concat0(O, ".4h, "); 6004 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6005 break; 6006 case 15: 6007 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... 6008 SStream_concat0(O, ".8b, "); 6009 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6010 break; 6011 case 16: 6012 // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz 6013 SStream_concat0(O, ".16b, #0"); 6014 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6015 arm64_op_addFP(MI, 0.0); 6016 return; 6017 break; 6018 case 17: 6019 // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz 6020 SStream_concat0(O, ", #0"); 6021 arm64_op_addImm(MI, 0); 6022 return; 6023 break; 6024 case 18: 6025 // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz 6026 SStream_concat0(O, ".2s, #0"); 6027 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6028 arm64_op_addImm(MI, 0); 6029 return; 6030 break; 6031 case 19: 6032 // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz 6033 SStream_concat0(O, ".2d, #0"); 6034 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6035 arm64_op_addImm(MI, 0); 6036 return; 6037 break; 6038 case 20: 6039 // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz 6040 SStream_concat0(O, ".4h, #0"); 6041 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6042 arm64_op_addImm(MI, 0); 6043 return; 6044 break; 6045 case 21: 6046 // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz 6047 SStream_concat0(O, ".4s, #0"); 6048 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6049 arm64_op_addImm(MI, 0); 6050 return; 6051 break; 6052 case 22: 6053 // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz 6054 SStream_concat0(O, ".8h, #0"); 6055 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6056 arm64_op_addImm(MI, 0); 6057 return; 6058 break; 6059 case 23: 6060 // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz 6061 SStream_concat0(O, ".8b, #0"); 6062 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6063 arm64_op_addImm(MI, 0); 6064 return; 6065 break; 6066 case 24: 6067 // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... 6068 SStream_concat0(O, ".h"); 6069 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 6070 break; 6071 case 25: 6072 // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... 6073 SStream_concat0(O, ".s"); 6074 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 6075 break; 6076 case 26: 6077 // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 6078 SStream_concat0(O, ".d"); 6079 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 6080 break; 6081 case 27: 6082 // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... 6083 SStream_concat0(O, ".b"); 6084 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); 6085 break; 6086 case 28: 6087 // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ... 6088 SStream_concat0(O, ", #0.0"); 6089 arm64_op_addFP(MI, 0.0); 6090 return; 6091 break; 6092 case 29: 6093 // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz 6094 SStream_concat0(O, ".2s, #0.0"); 6095 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6096 arm64_op_addFP(MI, 0.0); 6097 return; 6098 break; 6099 case 30: 6100 // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz 6101 SStream_concat0(O, ".2d, #0.0"); 6102 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6103 arm64_op_addFP(MI, 0.0); 6104 return; 6105 break; 6106 case 31: 6107 // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz 6108 SStream_concat0(O, ".4s, #0.0"); 6109 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6110 arm64_op_addFP(MI, 0.0); 6111 return; 6112 break; 6113 case 32: 6114 // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX... 6115 SStream_concat0(O, "]"); 6116 set_mem_access(MI, false); 6117 return; 6118 break; 6119 case 33: 6120 // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos... 6121 SStream_concat0(O, ", ["); 6122 set_mem_access(MI, true); 6123 break; 6124 case 34: 6125 // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... 6126 SStream_concat0(O, "], "); 6127 set_mem_access(MI, false); 6128 printOperand(MI, 3, O); 6129 return; 6130 break; 6131 case 35: 6132 // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... 6133 printShifter(MI, 2, O); 6134 return; 6135 break; 6136 case 36: 6137 // SHLLv16i8 6138 SStream_concat0(O, ".16b, #8"); 6139 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6140 arm64_op_addImm(MI, 8); 6141 return; 6142 break; 6143 case 37: 6144 // SHLLv2i32 6145 SStream_concat0(O, ".2s, #32"); 6146 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6147 arm64_op_addImm(MI, 32); 6148 return; 6149 break; 6150 case 38: 6151 // SHLLv4i16 6152 SStream_concat0(O, ".4h, #16"); 6153 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6154 arm64_op_addImm(MI, 16); 6155 return; 6156 break; 6157 case 39: 6158 // SHLLv4i32 6159 SStream_concat0(O, ".4s, #32"); 6160 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6161 arm64_op_addImm(MI, 32); 6162 return; 6163 break; 6164 case 40: 6165 // SHLLv8i16 6166 SStream_concat0(O, ".8h, #16"); 6167 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6168 arm64_op_addImm(MI, 16); 6169 return; 6170 break; 6171 case 41: 6172 // SHLLv8i8 6173 SStream_concat0(O, ".8b, #8"); 6174 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6175 arm64_op_addImm(MI, 8); 6176 return; 6177 break; 6178 } 6179 6180 6181 // Fragment 4 encoded into 5 bits for 18 unique commands. 6182 //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); 6183 switch ((Bits >> 35) & 31) { 6184 default: // unreachable. 6185 case 0: 6186 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A... 6187 printOperand(MI, 2, O); 6188 break; 6189 case 1: 6190 // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... 6191 printVRegOperand(MI, 2, O); 6192 break; 6193 case 2: 6194 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... 6195 printVRegOperand(MI, 3, O); 6196 break; 6197 case 3: 6198 // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri 6199 printAddSubImm(MI, 2, O); 6200 return; 6201 break; 6202 case 4: 6203 // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... 6204 printShiftedRegister(MI, 2, O); 6205 return; 6206 break; 6207 case 5: 6208 // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx 6209 printExtendedRegister(MI, 2, O); 6210 return; 6211 break; 6212 case 6: 6213 // ANDSWri, ANDWri, EORWri, ORRWri 6214 printLogicalImm32(MI, 2, O); 6215 return; 6216 break; 6217 case 7: 6218 // ANDSXri, ANDXri, EORXri, ORRXri 6219 printLogicalImm64(MI, 2, O); 6220 return; 6221 break; 6222 case 8: 6223 // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW... 6224 printOperand(MI, 3, O); 6225 break; 6226 case 9: 6227 // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... 6228 printVectorIndex(MI, 2, O); 6229 return; 6230 break; 6231 case 10: 6232 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane 6233 printVectorIndex(MI, 4, O); 6234 return; 6235 break; 6236 case 11: 6237 // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui 6238 printUImm12Offset2(MI, 2, O, 1); 6239 SStream_concat0(O, "]"); 6240 set_mem_access(MI, false); 6241 return; 6242 break; 6243 case 12: 6244 // LDRDui, LDRXui, PRFMui, STRDui, STRXui 6245 printUImm12Offset2(MI, 2, O, 8); 6246 SStream_concat0(O, "]"); 6247 set_mem_access(MI, false); 6248 return; 6249 break; 6250 case 13: 6251 // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui 6252 printUImm12Offset2(MI, 2, O, 2); 6253 SStream_concat0(O, "]"); 6254 set_mem_access(MI, false); 6255 return; 6256 break; 6257 case 14: 6258 // LDRQui, STRQui 6259 printUImm12Offset2(MI, 2, O, 16); 6260 SStream_concat0(O, "]"); 6261 set_mem_access(MI, false); 6262 return; 6263 break; 6264 case 15: 6265 // LDRSWui, LDRSui, LDRWui, STRSui, STRWui 6266 printUImm12Offset2(MI, 2, O, 4); 6267 SStream_concat0(O, "]"); 6268 set_mem_access(MI, false); 6269 return; 6270 break; 6271 case 16: 6272 // SYSLxt 6273 printSysCROperand(MI, 2, O); 6274 SStream_concat0(O, ", "); 6275 printSysCROperand(MI, 3, O); 6276 SStream_concat0(O, ", "); 6277 printOperand(MI, 4, O); 6278 return; 6279 break; 6280 case 17: 6281 // TBNZW, TBNZX, TBZW, TBZX 6282 printAlignedLabel(MI, 2, O); 6283 return; 6284 break; 6285 } 6286 6287 6288 // Fragment 5 encoded into 5 bits for 19 unique commands. 6289 //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31); 6290 switch ((Bits >> 40) & 31) { 6291 default: // unreachable. 6292 case 0: 6293 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG... 6294 return; 6295 break; 6296 case 1: 6297 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... 6298 SStream_concat0(O, ".2d"); 6299 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6300 return; 6301 break; 6302 case 2: 6303 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... 6304 SStream_concat0(O, ".4s"); 6305 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6306 return; 6307 break; 6308 case 3: 6309 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... 6310 SStream_concat0(O, ".8h"); 6311 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6312 return; 6313 break; 6314 case 4: 6315 // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... 6316 SStream_concat0(O, ".16b"); 6317 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6318 return; 6319 break; 6320 case 5: 6321 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... 6322 SStream_concat0(O, ".2s"); 6323 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6324 return; 6325 break; 6326 case 6: 6327 // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... 6328 SStream_concat0(O, ".4h"); 6329 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6330 return; 6331 break; 6332 case 7: 6333 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... 6334 SStream_concat0(O, ".8b"); 6335 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6336 return; 6337 break; 6338 case 8: 6339 // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 6340 printArithExtend(MI, 3, O); 6341 return; 6342 break; 6343 case 9: 6344 // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi... 6345 SStream_concat0(O, ", "); 6346 break; 6347 case 10: 6348 // EXTv16i8 6349 SStream_concat0(O, ".16b, "); 6350 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6351 printOperand(MI, 3, O); 6352 return; 6353 break; 6354 case 11: 6355 // EXTv8i8 6356 SStream_concat0(O, ".8b, "); 6357 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6358 printOperand(MI, 3, O); 6359 return; 6360 break; 6361 case 12: 6362 // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind... 6363 SStream_concat0(O, ".s"); 6364 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 6365 break; 6366 case 13: 6367 // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... 6368 SStream_concat0(O, ".d"); 6369 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 6370 break; 6371 case 14: 6372 // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi... 6373 SStream_concat0(O, "]"); 6374 set_mem_access(MI, false); 6375 return; 6376 break; 6377 case 15: 6378 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... 6379 SStream_concat0(O, "], "); 6380 set_mem_access(MI, false); 6381 break; 6382 case 16: 6383 // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... 6384 SStream_concat0(O, "]!"); 6385 set_mem_access(MI, false); 6386 return; 6387 break; 6388 case 17: 6389 // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed... 6390 SStream_concat0(O, ".h"); 6391 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 6392 break; 6393 case 18: 6394 // STLXPW, STLXPX, STXPW, STXPX 6395 SStream_concat0(O, ", ["); 6396 set_mem_access(MI, true); 6397 printOperand(MI, 3, O); 6398 SStream_concat0(O, "]"); 6399 set_mem_access(MI, false); 6400 return; 6401 break; 6402 } 6403 6404 6405 // Fragment 6 encoded into 5 bits for 21 unique commands. 6406 //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31); 6407 switch ((Bits >> 45) & 31) { 6408 default: // unreachable. 6409 case 0: 6410 // BFMWri, BFMXri 6411 printOperand(MI, 4, O); 6412 return; 6413 break; 6414 case 1: 6415 // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... 6416 printCondCode(MI, 3, O); 6417 return; 6418 break; 6419 case 2: 6420 // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD... 6421 printOperand(MI, 3, O); 6422 return; 6423 break; 6424 case 3: 6425 // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind... 6426 printVectorIndex(MI, 4, O); 6427 return; 6428 break; 6429 case 4: 6430 // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64... 6431 printVectorIndex(MI, 3, O); 6432 return; 6433 break; 6434 case 5: 6435 // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi 6436 printImmScale(MI, 3, O, 8); 6437 SStream_concat0(O, "]"); 6438 set_mem_access(MI, false); 6439 return; 6440 break; 6441 case 6: 6442 // LDNPQi, LDPQi, STNPQi, STPQi 6443 printImmScale(MI, 3, O, 16); 6444 SStream_concat0(O, "]"); 6445 set_mem_access(MI, false); 6446 return; 6447 break; 6448 case 7: 6449 // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi 6450 printImmScale(MI, 3, O, 4); 6451 SStream_concat0(O, "]"); 6452 set_mem_access(MI, false); 6453 return; 6454 break; 6455 case 8: 6456 // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... 6457 printImmScale(MI, 4, O, 8); 6458 break; 6459 case 9: 6460 // LDPQpost, LDPQpre, STPQpost, STPQpre 6461 printImmScale(MI, 4, O, 16); 6462 break; 6463 case 10: 6464 // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... 6465 printImmScale(MI, 4, O, 4); 6466 break; 6467 case 11: 6468 // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW 6469 printMemExtend(MI, 3, O, 'w', 8); 6470 SStream_concat0(O, "]"); 6471 set_mem_access(MI, false); 6472 return; 6473 break; 6474 case 12: 6475 // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX 6476 printMemExtend(MI, 3, O, 'x', 8); 6477 SStream_concat0(O, "]"); 6478 set_mem_access(MI, false); 6479 return; 6480 break; 6481 case 13: 6482 // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW 6483 printMemExtend(MI, 3, O, 'w', 64); 6484 SStream_concat0(O, "]"); 6485 set_mem_access(MI, false); 6486 return; 6487 break; 6488 case 14: 6489 // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX 6490 printMemExtend(MI, 3, O, 'x', 64); 6491 SStream_concat0(O, "]"); 6492 set_mem_access(MI, false); 6493 return; 6494 break; 6495 case 15: 6496 // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW 6497 printMemExtend(MI, 3, O, 'w', 16); 6498 SStream_concat0(O, "]"); 6499 set_mem_access(MI, false); 6500 return; 6501 break; 6502 case 16: 6503 // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX 6504 printMemExtend(MI, 3, O, 'x', 16); 6505 SStream_concat0(O, "]"); 6506 set_mem_access(MI, false); 6507 return; 6508 break; 6509 case 17: 6510 // LDRQroW, STRQroW 6511 printMemExtend(MI, 3, O, 'w', 128); 6512 SStream_concat0(O, "]"); 6513 set_mem_access(MI, false); 6514 return; 6515 break; 6516 case 18: 6517 // LDRQroX, STRQroX 6518 printMemExtend(MI, 3, O, 'x', 128); 6519 SStream_concat0(O, "]"); 6520 set_mem_access(MI, false); 6521 return; 6522 break; 6523 case 19: 6524 // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW 6525 printMemExtend(MI, 3, O, 'w', 32); 6526 SStream_concat0(O, "]"); 6527 set_mem_access(MI, false); 6528 return; 6529 break; 6530 case 20: 6531 // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX 6532 printMemExtend(MI, 3, O, 'x', 32); 6533 SStream_concat0(O, "]"); 6534 set_mem_access(MI, false); 6535 return; 6536 break; 6537 } 6538 6539 6540 // Fragment 7 encoded into 1 bits for 2 unique commands. 6541 //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1); 6542 if ((Bits >> 50) & 1) { 6543 // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... 6544 SStream_concat0(O, "]!"); 6545 set_mem_access(MI, false); 6546 return; 6547 } else { 6548 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... 6549 return; 6550 } 6551} 6552 6553 6554/// getRegisterName - This method is automatically generated by tblgen 6555/// from the register set description. This returns the assembler name 6556/// for the specified register. 6557static const char *getRegisterName(unsigned RegNo, int AltIdx) 6558{ 6559 // assert(RegNo && RegNo < 420 && "Invalid register number!"); 6560 6561#ifndef CAPSTONE_DIET 6562 static const char AsmStrsNoRegAltName[] = { 6563 /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, 6564 /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, 6565 /* 26 */ 'b', '1', '0', 0, 6566 /* 30 */ 'd', '1', '0', 0, 6567 /* 34 */ 'h', '1', '0', 0, 6568 /* 38 */ 'q', '1', '0', 0, 6569 /* 42 */ 's', '1', '0', 0, 6570 /* 46 */ 'w', '1', '0', 0, 6571 /* 50 */ 'x', '1', '0', 0, 6572 /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, 6573 /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, 6574 /* 86 */ 'b', '2', '0', 0, 6575 /* 90 */ 'd', '2', '0', 0, 6576 /* 94 */ 'h', '2', '0', 0, 6577 /* 98 */ 'q', '2', '0', 0, 6578 /* 102 */ 's', '2', '0', 0, 6579 /* 106 */ 'w', '2', '0', 0, 6580 /* 110 */ 'x', '2', '0', 0, 6581 /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, 6582 /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, 6583 /* 146 */ 'b', '3', '0', 0, 6584 /* 150 */ 'd', '3', '0', 0, 6585 /* 154 */ 'h', '3', '0', 0, 6586 /* 158 */ 'q', '3', '0', 0, 6587 /* 162 */ 's', '3', '0', 0, 6588 /* 166 */ 'w', '3', '0', 0, 6589 /* 170 */ 'x', '3', '0', 0, 6590 /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, 6591 /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, 6592 /* 204 */ 'b', '0', 0, 6593 /* 207 */ 'd', '0', 0, 6594 /* 210 */ 'h', '0', 0, 6595 /* 213 */ 'q', '0', 0, 6596 /* 216 */ 's', '0', 0, 6597 /* 219 */ 'w', '0', 0, 6598 /* 222 */ 'x', '0', 0, 6599 /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, 6600 /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, 6601 /* 253 */ 'b', '1', '1', 0, 6602 /* 257 */ 'd', '1', '1', 0, 6603 /* 261 */ 'h', '1', '1', 0, 6604 /* 265 */ 'q', '1', '1', 0, 6605 /* 269 */ 's', '1', '1', 0, 6606 /* 273 */ 'w', '1', '1', 0, 6607 /* 277 */ 'x', '1', '1', 0, 6608 /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, 6609 /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, 6610 /* 313 */ 'b', '2', '1', 0, 6611 /* 317 */ 'd', '2', '1', 0, 6612 /* 321 */ 'h', '2', '1', 0, 6613 /* 325 */ 'q', '2', '1', 0, 6614 /* 329 */ 's', '2', '1', 0, 6615 /* 333 */ 'w', '2', '1', 0, 6616 /* 337 */ 'x', '2', '1', 0, 6617 /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, 6618 /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, 6619 /* 373 */ 'b', '3', '1', 0, 6620 /* 377 */ 'd', '3', '1', 0, 6621 /* 381 */ 'h', '3', '1', 0, 6622 /* 385 */ 'q', '3', '1', 0, 6623 /* 389 */ 's', '3', '1', 0, 6624 /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, 6625 /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, 6626 /* 421 */ 'b', '1', 0, 6627 /* 424 */ 'd', '1', 0, 6628 /* 427 */ 'h', '1', 0, 6629 /* 430 */ 'q', '1', 0, 6630 /* 433 */ 's', '1', 0, 6631 /* 436 */ 'w', '1', 0, 6632 /* 439 */ 'x', '1', 0, 6633 /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, 6634 /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, 6635 /* 472 */ 'b', '1', '2', 0, 6636 /* 476 */ 'd', '1', '2', 0, 6637 /* 480 */ 'h', '1', '2', 0, 6638 /* 484 */ 'q', '1', '2', 0, 6639 /* 488 */ 's', '1', '2', 0, 6640 /* 492 */ 'w', '1', '2', 0, 6641 /* 496 */ 'x', '1', '2', 0, 6642 /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, 6643 /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, 6644 /* 532 */ 'b', '2', '2', 0, 6645 /* 536 */ 'd', '2', '2', 0, 6646 /* 540 */ 'h', '2', '2', 0, 6647 /* 544 */ 'q', '2', '2', 0, 6648 /* 548 */ 's', '2', '2', 0, 6649 /* 552 */ 'w', '2', '2', 0, 6650 /* 556 */ 'x', '2', '2', 0, 6651 /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, 6652 /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, 6653 /* 586 */ 'b', '2', 0, 6654 /* 589 */ 'd', '2', 0, 6655 /* 592 */ 'h', '2', 0, 6656 /* 595 */ 'q', '2', 0, 6657 /* 598 */ 's', '2', 0, 6658 /* 601 */ 'w', '2', 0, 6659 /* 604 */ 'x', '2', 0, 6660 /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, 6661 /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, 6662 /* 639 */ 'b', '1', '3', 0, 6663 /* 643 */ 'd', '1', '3', 0, 6664 /* 647 */ 'h', '1', '3', 0, 6665 /* 651 */ 'q', '1', '3', 0, 6666 /* 655 */ 's', '1', '3', 0, 6667 /* 659 */ 'w', '1', '3', 0, 6668 /* 663 */ 'x', '1', '3', 0, 6669 /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, 6670 /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, 6671 /* 699 */ 'b', '2', '3', 0, 6672 /* 703 */ 'd', '2', '3', 0, 6673 /* 707 */ 'h', '2', '3', 0, 6674 /* 711 */ 'q', '2', '3', 0, 6675 /* 715 */ 's', '2', '3', 0, 6676 /* 719 */ 'w', '2', '3', 0, 6677 /* 723 */ 'x', '2', '3', 0, 6678 /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, 6679 /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, 6680 /* 751 */ 'b', '3', 0, 6681 /* 754 */ 'd', '3', 0, 6682 /* 757 */ 'h', '3', 0, 6683 /* 760 */ 'q', '3', 0, 6684 /* 763 */ 's', '3', 0, 6685 /* 766 */ 'w', '3', 0, 6686 /* 769 */ 'x', '3', 0, 6687 /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, 6688 /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, 6689 /* 804 */ 'b', '1', '4', 0, 6690 /* 808 */ 'd', '1', '4', 0, 6691 /* 812 */ 'h', '1', '4', 0, 6692 /* 816 */ 'q', '1', '4', 0, 6693 /* 820 */ 's', '1', '4', 0, 6694 /* 824 */ 'w', '1', '4', 0, 6695 /* 828 */ 'x', '1', '4', 0, 6696 /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, 6697 /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, 6698 /* 864 */ 'b', '2', '4', 0, 6699 /* 868 */ 'd', '2', '4', 0, 6700 /* 872 */ 'h', '2', '4', 0, 6701 /* 876 */ 'q', '2', '4', 0, 6702 /* 880 */ 's', '2', '4', 0, 6703 /* 884 */ 'w', '2', '4', 0, 6704 /* 888 */ 'x', '2', '4', 0, 6705 /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, 6706 /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, 6707 /* 916 */ 'b', '4', 0, 6708 /* 919 */ 'd', '4', 0, 6709 /* 922 */ 'h', '4', 0, 6710 /* 925 */ 'q', '4', 0, 6711 /* 928 */ 's', '4', 0, 6712 /* 931 */ 'w', '4', 0, 6713 /* 934 */ 'x', '4', 0, 6714 /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, 6715 /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, 6716 /* 969 */ 'b', '1', '5', 0, 6717 /* 973 */ 'd', '1', '5', 0, 6718 /* 977 */ 'h', '1', '5', 0, 6719 /* 981 */ 'q', '1', '5', 0, 6720 /* 985 */ 's', '1', '5', 0, 6721 /* 989 */ 'w', '1', '5', 0, 6722 /* 993 */ 'x', '1', '5', 0, 6723 /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, 6724 /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, 6725 /* 1029 */ 'b', '2', '5', 0, 6726 /* 1033 */ 'd', '2', '5', 0, 6727 /* 1037 */ 'h', '2', '5', 0, 6728 /* 1041 */ 'q', '2', '5', 0, 6729 /* 1045 */ 's', '2', '5', 0, 6730 /* 1049 */ 'w', '2', '5', 0, 6731 /* 1053 */ 'x', '2', '5', 0, 6732 /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, 6733 /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, 6734 /* 1081 */ 'b', '5', 0, 6735 /* 1084 */ 'd', '5', 0, 6736 /* 1087 */ 'h', '5', 0, 6737 /* 1090 */ 'q', '5', 0, 6738 /* 1093 */ 's', '5', 0, 6739 /* 1096 */ 'w', '5', 0, 6740 /* 1099 */ 'x', '5', 0, 6741 /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, 6742 /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, 6743 /* 1134 */ 'b', '1', '6', 0, 6744 /* 1138 */ 'd', '1', '6', 0, 6745 /* 1142 */ 'h', '1', '6', 0, 6746 /* 1146 */ 'q', '1', '6', 0, 6747 /* 1150 */ 's', '1', '6', 0, 6748 /* 1154 */ 'w', '1', '6', 0, 6749 /* 1158 */ 'x', '1', '6', 0, 6750 /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, 6751 /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, 6752 /* 1194 */ 'b', '2', '6', 0, 6753 /* 1198 */ 'd', '2', '6', 0, 6754 /* 1202 */ 'h', '2', '6', 0, 6755 /* 1206 */ 'q', '2', '6', 0, 6756 /* 1210 */ 's', '2', '6', 0, 6757 /* 1214 */ 'w', '2', '6', 0, 6758 /* 1218 */ 'x', '2', '6', 0, 6759 /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, 6760 /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, 6761 /* 1246 */ 'b', '6', 0, 6762 /* 1249 */ 'd', '6', 0, 6763 /* 1252 */ 'h', '6', 0, 6764 /* 1255 */ 'q', '6', 0, 6765 /* 1258 */ 's', '6', 0, 6766 /* 1261 */ 'w', '6', 0, 6767 /* 1264 */ 'x', '6', 0, 6768 /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, 6769 /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, 6770 /* 1299 */ 'b', '1', '7', 0, 6771 /* 1303 */ 'd', '1', '7', 0, 6772 /* 1307 */ 'h', '1', '7', 0, 6773 /* 1311 */ 'q', '1', '7', 0, 6774 /* 1315 */ 's', '1', '7', 0, 6775 /* 1319 */ 'w', '1', '7', 0, 6776 /* 1323 */ 'x', '1', '7', 0, 6777 /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, 6778 /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, 6779 /* 1359 */ 'b', '2', '7', 0, 6780 /* 1363 */ 'd', '2', '7', 0, 6781 /* 1367 */ 'h', '2', '7', 0, 6782 /* 1371 */ 'q', '2', '7', 0, 6783 /* 1375 */ 's', '2', '7', 0, 6784 /* 1379 */ 'w', '2', '7', 0, 6785 /* 1383 */ 'x', '2', '7', 0, 6786 /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, 6787 /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, 6788 /* 1411 */ 'b', '7', 0, 6789 /* 1414 */ 'd', '7', 0, 6790 /* 1417 */ 'h', '7', 0, 6791 /* 1420 */ 'q', '7', 0, 6792 /* 1423 */ 's', '7', 0, 6793 /* 1426 */ 'w', '7', 0, 6794 /* 1429 */ 'x', '7', 0, 6795 /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, 6796 /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, 6797 /* 1464 */ 'b', '1', '8', 0, 6798 /* 1468 */ 'd', '1', '8', 0, 6799 /* 1472 */ 'h', '1', '8', 0, 6800 /* 1476 */ 'q', '1', '8', 0, 6801 /* 1480 */ 's', '1', '8', 0, 6802 /* 1484 */ 'w', '1', '8', 0, 6803 /* 1488 */ 'x', '1', '8', 0, 6804 /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, 6805 /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, 6806 /* 1524 */ 'b', '2', '8', 0, 6807 /* 1528 */ 'd', '2', '8', 0, 6808 /* 1532 */ 'h', '2', '8', 0, 6809 /* 1536 */ 'q', '2', '8', 0, 6810 /* 1540 */ 's', '2', '8', 0, 6811 /* 1544 */ 'w', '2', '8', 0, 6812 /* 1548 */ 'x', '2', '8', 0, 6813 /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, 6814 /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, 6815 /* 1576 */ 'b', '8', 0, 6816 /* 1579 */ 'd', '8', 0, 6817 /* 1582 */ 'h', '8', 0, 6818 /* 1585 */ 'q', '8', 0, 6819 /* 1588 */ 's', '8', 0, 6820 /* 1591 */ 'w', '8', 0, 6821 /* 1594 */ 'x', '8', 0, 6822 /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, 6823 /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, 6824 /* 1629 */ 'b', '1', '9', 0, 6825 /* 1633 */ 'd', '1', '9', 0, 6826 /* 1637 */ 'h', '1', '9', 0, 6827 /* 1641 */ 'q', '1', '9', 0, 6828 /* 1645 */ 's', '1', '9', 0, 6829 /* 1649 */ 'w', '1', '9', 0, 6830 /* 1653 */ 'x', '1', '9', 0, 6831 /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, 6832 /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, 6833 /* 1689 */ 'b', '2', '9', 0, 6834 /* 1693 */ 'd', '2', '9', 0, 6835 /* 1697 */ 'h', '2', '9', 0, 6836 /* 1701 */ 'q', '2', '9', 0, 6837 /* 1705 */ 's', '2', '9', 0, 6838 /* 1709 */ 'w', '2', '9', 0, 6839 /* 1713 */ 'x', '2', '9', 0, 6840 /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, 6841 /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, 6842 /* 1741 */ 'b', '9', 0, 6843 /* 1744 */ 'd', '9', 0, 6844 /* 1747 */ 'h', '9', 0, 6845 /* 1750 */ 'q', '9', 0, 6846 /* 1753 */ 's', '9', 0, 6847 /* 1756 */ 'w', '9', 0, 6848 /* 1759 */ 'x', '9', 0, 6849 /* 1762 */ 'w', 's', 'p', 0, 6850 /* 1766 */ 'w', 'z', 'r', 0, 6851 /* 1770 */ 'x', 'z', 'r', 0, 6852 /* 1774 */ 'n', 'z', 'c', 'v', 0, 6853 }; 6854 6855 static const uint16_t RegAsmOffsetNoRegAltName[] = { 6856 1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, 6857 1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, 6858 313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, 6859 754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, 6860 1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, 6861 377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, 6862 647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, 6863 1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, 6864 1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, 6865 711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, 6866 1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, 6867 1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, 6868 436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, 6869 989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, 6870 1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, 6871 496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, 6872 1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, 6873 449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, 6874 1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, 6875 0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, 6876 832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, 6877 1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, 6878 1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, 6879 397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, 6880 796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, 6881 1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, 6882 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, 6883 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, 6884 1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, 6885 301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, 6886 }; 6887 6888 static const char AsmStrsvreg[] = { 6889 /* 0 */ 'v', '1', '0', 0, 6890 /* 4 */ 'v', '2', '0', 0, 6891 /* 8 */ 'v', '3', '0', 0, 6892 /* 12 */ 'v', '0', 0, 6893 /* 15 */ 'v', '1', '1', 0, 6894 /* 19 */ 'v', '2', '1', 0, 6895 /* 23 */ 'v', '3', '1', 0, 6896 /* 27 */ 'v', '1', 0, 6897 /* 30 */ 'v', '1', '2', 0, 6898 /* 34 */ 'v', '2', '2', 0, 6899 /* 38 */ 'v', '2', 0, 6900 /* 41 */ 'v', '1', '3', 0, 6901 /* 45 */ 'v', '2', '3', 0, 6902 /* 49 */ 'v', '3', 0, 6903 /* 52 */ 'v', '1', '4', 0, 6904 /* 56 */ 'v', '2', '4', 0, 6905 /* 60 */ 'v', '4', 0, 6906 /* 63 */ 'v', '1', '5', 0, 6907 /* 67 */ 'v', '2', '5', 0, 6908 /* 71 */ 'v', '5', 0, 6909 /* 74 */ 'v', '1', '6', 0, 6910 /* 78 */ 'v', '2', '6', 0, 6911 /* 82 */ 'v', '6', 0, 6912 /* 85 */ 'v', '1', '7', 0, 6913 /* 89 */ 'v', '2', '7', 0, 6914 /* 93 */ 'v', '7', 0, 6915 /* 96 */ 'v', '1', '8', 0, 6916 /* 100 */ 'v', '2', '8', 0, 6917 /* 104 */ 'v', '8', 0, 6918 /* 107 */ 'v', '1', '9', 0, 6919 /* 111 */ 'v', '2', '9', 0, 6920 /* 115 */ 'v', '9', 0, 6921 }; 6922 6923 static const uint16_t RegAsmOffsetvreg[] = { 6924 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6925 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6926 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 6927 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 6928 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 6929 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6930 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6931 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 6932 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 6933 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 6934 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6935 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6936 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6937 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6938 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6939 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6940 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 6941 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 6942 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 6943 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 6944 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 6945 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 6946 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 6947 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 6948 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 6949 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 6950 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 6951 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 6952 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 6953 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 6954 }; 6955 6956 const uint16_t *RegAsmOffset; 6957 const char *AsmStrs; 6958 6959 switch(AltIdx) { 6960 default: // llvm_unreachable("Invalid register alt name index!"); 6961 case AArch64_NoRegAltName: 6962 AsmStrs = AsmStrsNoRegAltName; 6963 RegAsmOffset = RegAsmOffsetNoRegAltName; 6964 break; 6965 case AArch64_vreg: 6966 AsmStrs = AsmStrsvreg; 6967 RegAsmOffset = RegAsmOffsetvreg; 6968 break; 6969 } 6970 //int i; 6971 //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/2; i++) 6972 // printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1); 6973 //printf("*************************\n"); 6974 //for (i = 0; i < sizeof(RegAsmOffsetvreg)/2; i++) 6975 // printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1); 6976 //printf("-------------------------\n"); 6977 return AsmStrs+RegAsmOffset[RegNo-1]; 6978#else 6979 return NULL; 6980#endif 6981} 6982 6983#ifdef PRINT_ALIAS_INSTR 6984#undef PRINT_ALIAS_INSTR 6985 6986static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, 6987 unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI) 6988{ 6989 // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx); 6990 switch (PrintMethodIdx) { 6991 default: 6992 // llvm_unreachable("Unknown PrintMethod kind"); 6993 break; 6994 case 0: 6995 printAddSubImm(MI, OpIdx, OS); 6996 break; 6997 case 1: 6998 printShifter(MI, OpIdx, OS); 6999 break; 7000 case 2: 7001 printArithExtend(MI, OpIdx, OS); 7002 break; 7003 case 3: 7004 printLogicalImm32(MI, OpIdx, OS); 7005 break; 7006 case 4: 7007 printLogicalImm64(MI, OpIdx, OS); 7008 break; 7009 case 5: 7010 printVRegOperand(MI, OpIdx, OS); 7011 break; 7012 case 6: 7013 printHexImm(MI, OpIdx, OS); 7014 break; 7015 case 7: 7016 printInverseCondCode(MI, OpIdx, OS); 7017 break; 7018 case 8: 7019 printVectorIndex(MI, OpIdx, OS); 7020 break; 7021 case 9: 7022 printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI); 7023 break; 7024 case 10: 7025 printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI); 7026 break; 7027 case 11: 7028 printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI); 7029 break; 7030 case 12: 7031 printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI); 7032 break; 7033 case 13: 7034 printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI); 7035 break; 7036 case 14: 7037 printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI); 7038 break; 7039 case 15: 7040 printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI); 7041 break; 7042 case 16: 7043 printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI); 7044 break; 7045 case 17: 7046 printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI); 7047 break; 7048 case 18: 7049 printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI); 7050 break; 7051 case 19: 7052 printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI); 7053 break; 7054 case 20: 7055 printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI); 7056 break; 7057 case 21: 7058 printPrefetchOp(MI, OpIdx, OS); 7059 break; 7060 case 22: 7061 printSysCROperand(MI, OpIdx, OS); 7062 break; 7063 } 7064} 7065 7066static bool AArch64InstPrinterValidateMCOperand( 7067 MCOperand *MCOp, unsigned PredicateIndex) 7068{ 7069 switch (PredicateIndex) { 7070 default: 7071 // llvm_unreachable("Unknown MCOperandPredicate kind"); 7072 case 1: { 7073 return (MCOperand_isImm(MCOp) && 7074 MCOperand_getImm(MCOp) != ARM64_CC_AL && 7075 MCOperand_getImm(MCOp) != ARM64_CC_NV); 7076 } 7077 } 7078} 7079 7080static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) 7081{ 7082 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) 7083 const char *AsmString; 7084 char *tmp, *AsmMnem, *AsmOps, *c; 7085 int OpIdx, PrintMethodIdx; 7086 MCRegisterInfo *MRI = (MCRegisterInfo *)info; 7087 switch (MCInst_getOpcode(MI)) { 7088 default: return NULL; 7089 case AArch64_ADDSWri: 7090 if (MCInst_getNumOperands(MI) == 4 && 7091 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7092 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7093 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { 7094 // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) 7095 AsmString = "cmn $\x02, $\xFF\x03\x01"; 7096 break; 7097 } 7098 return NULL; 7099 case AArch64_ADDSWrs: 7100 if (MCInst_getNumOperands(MI) == 4 && 7101 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7102 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7103 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7104 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7105 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7106 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7107 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7108 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 7109 AsmString = "cmn $\x02, $\x03"; 7110 break; 7111 } 7112 if (MCInst_getNumOperands(MI) == 4 && 7113 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7114 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7115 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7116 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7117 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7118 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) 7119 AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; 7120 break; 7121 } 7122 if (MCInst_getNumOperands(MI) == 4 && 7123 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7124 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7125 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7126 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7127 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7128 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7129 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7130 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7131 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7132 AsmString = "adds $\x01, $\x02, $\x03"; 7133 break; 7134 } 7135 return NULL; 7136 case AArch64_ADDSWrx: 7137 if (MCInst_getNumOperands(MI) == 4 && 7138 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7139 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7140 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7141 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7142 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7143 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7144 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7145 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) 7146 AsmString = "cmn $\x02, $\x03"; 7147 break; 7148 } 7149 if (MCInst_getNumOperands(MI) == 4 && 7150 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7151 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7152 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7153 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7154 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7155 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) 7156 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7157 break; 7158 } 7159 if (MCInst_getNumOperands(MI) == 4 && 7160 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7161 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7162 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7163 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7164 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7165 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7166 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7167 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7168 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 7169 AsmString = "adds $\x01, $\x02, $\x03"; 7170 break; 7171 } 7172 return NULL; 7173 case AArch64_ADDSXri: 7174 if (MCInst_getNumOperands(MI) == 4 && 7175 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7176 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7177 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { 7178 // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) 7179 AsmString = "cmn $\x02, $\xFF\x03\x01"; 7180 break; 7181 } 7182 return NULL; 7183 case AArch64_ADDSXrs: 7184 if (MCInst_getNumOperands(MI) == 4 && 7185 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7186 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7187 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7188 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7189 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7190 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7191 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7192 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 7193 AsmString = "cmn $\x02, $\x03"; 7194 break; 7195 } 7196 if (MCInst_getNumOperands(MI) == 4 && 7197 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7198 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7199 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7200 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7201 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7202 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) 7203 AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; 7204 break; 7205 } 7206 if (MCInst_getNumOperands(MI) == 4 && 7207 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7208 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7209 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7210 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7211 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7212 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7213 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7214 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7215 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7216 AsmString = "adds $\x01, $\x02, $\x03"; 7217 break; 7218 } 7219 return NULL; 7220 case AArch64_ADDSXrx: 7221 if (MCInst_getNumOperands(MI) == 4 && 7222 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7223 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7224 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7225 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7226 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7227 // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) 7228 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7229 break; 7230 } 7231 return NULL; 7232 case AArch64_ADDSXrx64: 7233 if (MCInst_getNumOperands(MI) == 4 && 7234 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7235 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7236 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7237 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7238 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7239 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7240 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7241 // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) 7242 AsmString = "cmn $\x02, $\x03"; 7243 break; 7244 } 7245 if (MCInst_getNumOperands(MI) == 4 && 7246 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7247 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7248 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7249 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7250 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7251 // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) 7252 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7253 break; 7254 } 7255 if (MCInst_getNumOperands(MI) == 4 && 7256 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7257 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7258 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7259 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7260 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7261 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7262 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7263 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7264 // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 7265 AsmString = "adds $\x01, $\x02, $\x03"; 7266 break; 7267 } 7268 return NULL; 7269 case AArch64_ADDWri: 7270 if (MCInst_getNumOperands(MI) == 4 && 7271 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7272 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 7273 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7274 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7275 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7276 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7277 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7278 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7279 // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) 7280 AsmString = "mov $\x01, $\x02"; 7281 break; 7282 } 7283 if (MCInst_getNumOperands(MI) == 4 && 7284 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7285 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 7286 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7287 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7288 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7289 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7290 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7291 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7292 // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) 7293 AsmString = "mov $\x01, $\x02"; 7294 break; 7295 } 7296 return NULL; 7297 case AArch64_ADDWrs: 7298 if (MCInst_getNumOperands(MI) == 4 && 7299 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7300 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7301 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7302 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7303 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7304 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7305 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7306 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7307 // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7308 AsmString = "add $\x01, $\x02, $\x03"; 7309 break; 7310 } 7311 return NULL; 7312 case AArch64_ADDWrx: 7313 if (MCInst_getNumOperands(MI) == 4 && 7314 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7315 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 7316 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7317 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7318 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7319 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7320 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7321 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7322 // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) 7323 AsmString = "add $\x01, $\x02, $\x03"; 7324 break; 7325 } 7326 if (MCInst_getNumOperands(MI) == 4 && 7327 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7328 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 7329 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7330 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7331 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7332 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7333 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7334 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7335 // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 7336 AsmString = "add $\x01, $\x02, $\x03"; 7337 break; 7338 } 7339 return NULL; 7340 case AArch64_ADDXri: 7341 if (MCInst_getNumOperands(MI) == 4 && 7342 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7343 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 7344 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7345 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7346 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7347 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7348 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7349 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7350 // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) 7351 AsmString = "mov $\x01, $\x02"; 7352 break; 7353 } 7354 if (MCInst_getNumOperands(MI) == 4 && 7355 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7356 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 7357 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7358 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7359 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7360 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7361 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7362 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7363 // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) 7364 AsmString = "mov $\x01, $\x02"; 7365 break; 7366 } 7367 return NULL; 7368 case AArch64_ADDXrs: 7369 if (MCInst_getNumOperands(MI) == 4 && 7370 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7371 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7372 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7373 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7374 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7375 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7376 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7377 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7378 // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7379 AsmString = "add $\x01, $\x02, $\x03"; 7380 break; 7381 } 7382 return NULL; 7383 case AArch64_ADDXrx64: 7384 if (MCInst_getNumOperands(MI) == 4 && 7385 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7386 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 7387 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7388 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7389 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7390 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7391 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7392 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7393 // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) 7394 AsmString = "add $\x01, $\x02, $\x03"; 7395 break; 7396 } 7397 if (MCInst_getNumOperands(MI) == 4 && 7398 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7399 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 7400 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7401 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7402 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7403 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7404 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7405 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7406 // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 7407 AsmString = "add $\x01, $\x02, $\x03"; 7408 break; 7409 } 7410 return NULL; 7411 case AArch64_ANDSWri: 7412 if (MCInst_getNumOperands(MI) == 3 && 7413 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7414 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7415 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) { 7416 // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) 7417 AsmString = "tst $\x02, $\xFF\x03\x04"; 7418 break; 7419 } 7420 return NULL; 7421 case AArch64_ANDSWrs: 7422 if (MCInst_getNumOperands(MI) == 4 && 7423 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7424 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7425 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7426 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7427 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7428 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7429 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7430 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 7431 AsmString = "tst $\x02, $\x03"; 7432 break; 7433 } 7434 if (MCInst_getNumOperands(MI) == 4 && 7435 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7436 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7437 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7438 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7439 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7440 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) 7441 AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; 7442 break; 7443 } 7444 if (MCInst_getNumOperands(MI) == 4 && 7445 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7446 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7447 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7448 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7449 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7450 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7451 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7452 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7453 // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7454 AsmString = "ands $\x01, $\x02, $\x03"; 7455 break; 7456 } 7457 return NULL; 7458 case AArch64_ANDSXri: 7459 if (MCInst_getNumOperands(MI) == 3 && 7460 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7461 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7462 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) { 7463 // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) 7464 AsmString = "tst $\x02, $\xFF\x03\x05"; 7465 break; 7466 } 7467 return NULL; 7468 case AArch64_ANDSXrs: 7469 if (MCInst_getNumOperands(MI) == 4 && 7470 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7471 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7472 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7473 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7474 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7475 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7476 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7477 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 7478 AsmString = "tst $\x02, $\x03"; 7479 break; 7480 } 7481 if (MCInst_getNumOperands(MI) == 4 && 7482 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7483 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7484 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7485 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7486 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7487 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) 7488 AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; 7489 break; 7490 } 7491 if (MCInst_getNumOperands(MI) == 4 && 7492 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7493 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7494 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7495 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7496 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7497 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7498 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7499 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7500 // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7501 AsmString = "ands $\x01, $\x02, $\x03"; 7502 break; 7503 } 7504 return NULL; 7505 case AArch64_ANDWrs: 7506 if (MCInst_getNumOperands(MI) == 4 && 7507 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7508 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7509 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7510 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7511 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7512 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7513 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7514 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7515 // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7516 AsmString = "and $\x01, $\x02, $\x03"; 7517 break; 7518 } 7519 return NULL; 7520 case AArch64_ANDXrs: 7521 if (MCInst_getNumOperands(MI) == 4 && 7522 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7523 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7524 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7525 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7526 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7527 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7528 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7529 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7530 // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7531 AsmString = "and $\x01, $\x02, $\x03"; 7532 break; 7533 } 7534 return NULL; 7535 case AArch64_BICSWrs: 7536 if (MCInst_getNumOperands(MI) == 4 && 7537 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7538 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7539 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7540 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7541 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7542 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7543 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7544 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7545 // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7546 AsmString = "bics $\x01, $\x02, $\x03"; 7547 break; 7548 } 7549 return NULL; 7550 case AArch64_BICSXrs: 7551 if (MCInst_getNumOperands(MI) == 4 && 7552 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7553 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7554 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7555 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7556 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7557 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7558 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7559 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7560 // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7561 AsmString = "bics $\x01, $\x02, $\x03"; 7562 break; 7563 } 7564 return NULL; 7565 case AArch64_BICWrs: 7566 if (MCInst_getNumOperands(MI) == 4 && 7567 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7568 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7569 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7570 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7571 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7572 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7573 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7574 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7575 // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7576 AsmString = "bic $\x01, $\x02, $\x03"; 7577 break; 7578 } 7579 return NULL; 7580 case AArch64_BICXrs: 7581 if (MCInst_getNumOperands(MI) == 4 && 7582 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7583 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7584 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7585 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7586 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7587 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7588 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7589 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7590 // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7591 AsmString = "bic $\x01, $\x02, $\x03"; 7592 break; 7593 } 7594 return NULL; 7595 case AArch64_BICv2i32: 7596 if (MCInst_getNumOperands(MI) == 3 && 7597 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7598 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 7599 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7600 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7601 // (BICv2i32 V64:$Vd, imm0_255:$imm, 0) 7602 AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07"; 7603 break; 7604 } 7605 return NULL; 7606 case AArch64_BICv4i16: 7607 if (MCInst_getNumOperands(MI) == 3 && 7608 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7609 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 7610 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7611 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7612 // (BICv4i16 V64:$Vd, imm0_255:$imm, 0) 7613 AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07"; 7614 break; 7615 } 7616 return NULL; 7617 case AArch64_BICv4i32: 7618 if (MCInst_getNumOperands(MI) == 3 && 7619 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7620 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7621 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7622 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7623 // (BICv4i32 V128:$Vd, imm0_255:$imm, 0) 7624 AsmString = "bic $\xFF\x01\x06.4s, $\xFF\x02\x07"; 7625 break; 7626 } 7627 return NULL; 7628 case AArch64_BICv8i16: 7629 if (MCInst_getNumOperands(MI) == 3 && 7630 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7631 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7632 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7633 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7634 // (BICv8i16 V128:$Vd, imm0_255:$imm, 0) 7635 AsmString = "bic $\xFF\x01\x06.8h, $\xFF\x02\x07"; 7636 break; 7637 } 7638 return NULL; 7639 case AArch64_CLREX: 7640 if (MCInst_getNumOperands(MI) == 1 && 7641 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7642 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { 7643 // (CLREX 15) 7644 AsmString = "clrex"; 7645 break; 7646 } 7647 return NULL; 7648 case AArch64_CSINCWr: 7649 if (MCInst_getNumOperands(MI) == 4 && 7650 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7651 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7652 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 7653 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && 7654 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7655 // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) 7656 AsmString = "cset $\x01, $\xFF\x04\x08"; 7657 break; 7658 } 7659 if (MCInst_getNumOperands(MI) == 4 && 7660 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7661 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7662 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7663 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7664 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7665 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7666 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7667 // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7668 AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; 7669 break; 7670 } 7671 return NULL; 7672 case AArch64_CSINCXr: 7673 if (MCInst_getNumOperands(MI) == 4 && 7674 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7675 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7676 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 7677 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && 7678 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7679 // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) 7680 AsmString = "cset $\x01, $\xFF\x04\x08"; 7681 break; 7682 } 7683 if (MCInst_getNumOperands(MI) == 4 && 7684 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7685 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7686 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7687 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7688 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7689 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7690 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7691 // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7692 AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; 7693 break; 7694 } 7695 return NULL; 7696 case AArch64_CSINVWr: 7697 if (MCInst_getNumOperands(MI) == 4 && 7698 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7699 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7700 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 7701 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && 7702 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7703 // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) 7704 AsmString = "csetm $\x01, $\xFF\x04\x08"; 7705 break; 7706 } 7707 if (MCInst_getNumOperands(MI) == 4 && 7708 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7709 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7710 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7711 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7712 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7713 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7714 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7715 // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7716 AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; 7717 break; 7718 } 7719 return NULL; 7720 case AArch64_CSINVXr: 7721 if (MCInst_getNumOperands(MI) == 4 && 7722 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7723 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7724 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 7725 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && 7726 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7727 // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) 7728 AsmString = "csetm $\x01, $\xFF\x04\x08"; 7729 break; 7730 } 7731 if (MCInst_getNumOperands(MI) == 4 && 7732 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7733 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7734 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7735 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7736 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7737 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7738 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7739 // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7740 AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; 7741 break; 7742 } 7743 return NULL; 7744 case AArch64_CSNEGWr: 7745 if (MCInst_getNumOperands(MI) == 4 && 7746 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7747 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7748 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7749 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7750 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7751 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7752 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7753 // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7754 AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; 7755 break; 7756 } 7757 return NULL; 7758 case AArch64_CSNEGXr: 7759 if (MCInst_getNumOperands(MI) == 4 && 7760 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7761 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7762 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7763 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7764 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7765 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7766 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7767 // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7768 AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; 7769 break; 7770 } 7771 return NULL; 7772 case AArch64_DCPS1: 7773 if (MCInst_getNumOperands(MI) == 1 && 7774 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7775 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7776 // (DCPS1 0) 7777 AsmString = "dcps1"; 7778 break; 7779 } 7780 return NULL; 7781 case AArch64_DCPS2: 7782 if (MCInst_getNumOperands(MI) == 1 && 7783 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7784 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7785 // (DCPS2 0) 7786 AsmString = "dcps2"; 7787 break; 7788 } 7789 return NULL; 7790 case AArch64_DCPS3: 7791 if (MCInst_getNumOperands(MI) == 1 && 7792 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7793 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7794 // (DCPS3 0) 7795 AsmString = "dcps3"; 7796 break; 7797 } 7798 return NULL; 7799 case AArch64_EONWrs: 7800 if (MCInst_getNumOperands(MI) == 4 && 7801 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7802 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7803 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7804 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7805 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7806 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7807 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7808 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7809 // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7810 AsmString = "eon $\x01, $\x02, $\x03"; 7811 break; 7812 } 7813 return NULL; 7814 case AArch64_EONXrs: 7815 if (MCInst_getNumOperands(MI) == 4 && 7816 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7817 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7818 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7819 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7820 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7821 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7822 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7823 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7824 // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7825 AsmString = "eon $\x01, $\x02, $\x03"; 7826 break; 7827 } 7828 return NULL; 7829 case AArch64_EORWrs: 7830 if (MCInst_getNumOperands(MI) == 4 && 7831 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7832 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7833 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7834 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7835 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7836 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7837 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7838 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7839 // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7840 AsmString = "eor $\x01, $\x02, $\x03"; 7841 break; 7842 } 7843 return NULL; 7844 case AArch64_EORXrs: 7845 if (MCInst_getNumOperands(MI) == 4 && 7846 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7847 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7848 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7849 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7850 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7851 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7852 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7853 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7854 // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7855 AsmString = "eor $\x01, $\x02, $\x03"; 7856 break; 7857 } 7858 return NULL; 7859 case AArch64_EXTRWrri: 7860 if (MCInst_getNumOperands(MI) == 4 && 7861 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7862 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7863 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7864 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7865 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7866 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 7867 // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) 7868 AsmString = "ror $\x01, $\x02, $\x04"; 7869 break; 7870 } 7871 return NULL; 7872 case AArch64_EXTRXrri: 7873 if (MCInst_getNumOperands(MI) == 4 && 7874 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7875 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7876 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7877 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7878 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7879 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 7880 // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) 7881 AsmString = "ror $\x01, $\x02, $\x04"; 7882 break; 7883 } 7884 return NULL; 7885 case AArch64_HINT: 7886 if (MCInst_getNumOperands(MI) == 1 && 7887 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7888 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7889 // (HINT { 0, 0, 0 }) 7890 AsmString = "nop"; 7891 break; 7892 } 7893 if (MCInst_getNumOperands(MI) == 1 && 7894 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7895 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { 7896 // (HINT { 0, 0, 1 }) 7897 AsmString = "yield"; 7898 break; 7899 } 7900 if (MCInst_getNumOperands(MI) == 1 && 7901 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7902 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { 7903 // (HINT { 0, 1, 0 }) 7904 AsmString = "wfe"; 7905 break; 7906 } 7907 if (MCInst_getNumOperands(MI) == 1 && 7908 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7909 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { 7910 // (HINT { 0, 1, 1 }) 7911 AsmString = "wfi"; 7912 break; 7913 } 7914 if (MCInst_getNumOperands(MI) == 1 && 7915 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7916 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { 7917 // (HINT { 1, 0, 0 }) 7918 AsmString = "sev"; 7919 break; 7920 } 7921 if (MCInst_getNumOperands(MI) == 1 && 7922 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7923 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { 7924 // (HINT { 1, 0, 1 }) 7925 AsmString = "sevl"; 7926 break; 7927 } 7928 return NULL; 7929 case AArch64_INSvi16gpr: 7930 if (MCInst_getNumOperands(MI) == 3 && 7931 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7932 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7933 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7934 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7935 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) 7936 AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\x03"; 7937 break; 7938 } 7939 return NULL; 7940 case AArch64_INSvi16lane: 7941 if (MCInst_getNumOperands(MI) == 4 && 7942 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7943 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7944 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7945 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7946 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) 7947 AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\xFF\x03\x06.h$\xFF\x04\x09"; 7948 break; 7949 } 7950 return NULL; 7951 case AArch64_INSvi32gpr: 7952 if (MCInst_getNumOperands(MI) == 3 && 7953 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7954 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7955 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7956 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7957 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) 7958 AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\x03"; 7959 break; 7960 } 7961 return NULL; 7962 case AArch64_INSvi32lane: 7963 if (MCInst_getNumOperands(MI) == 4 && 7964 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7965 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7966 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7967 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7968 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) 7969 AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\xFF\x03\x06.s$\xFF\x04\x09"; 7970 break; 7971 } 7972 return NULL; 7973 case AArch64_INSvi64gpr: 7974 if (MCInst_getNumOperands(MI) == 3 && 7975 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7976 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7977 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7978 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7979 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) 7980 AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\x03"; 7981 break; 7982 } 7983 return NULL; 7984 case AArch64_INSvi64lane: 7985 if (MCInst_getNumOperands(MI) == 4 && 7986 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7987 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7988 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7989 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7990 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) 7991 AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\xFF\x03\x06.d$\xFF\x04\x09"; 7992 break; 7993 } 7994 return NULL; 7995 case AArch64_INSvi8gpr: 7996 if (MCInst_getNumOperands(MI) == 3 && 7997 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7998 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7999 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 8000 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 8001 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) 8002 AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\x03"; 8003 break; 8004 } 8005 return NULL; 8006 case AArch64_INSvi8lane: 8007 if (MCInst_getNumOperands(MI) == 4 && 8008 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8009 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 8010 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 8011 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 8012 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) 8013 AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\xFF\x03\x06.b$\xFF\x04\x09"; 8014 break; 8015 } 8016 return NULL; 8017 case AArch64_ISB: 8018 if (MCInst_getNumOperands(MI) == 1 && 8019 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 8020 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { 8021 // (ISB 15) 8022 AsmString = "isb"; 8023 break; 8024 } 8025 return NULL; 8026 case AArch64_LD1Fourv16b_POST: 8027 if (MCInst_getNumOperands(MI) == 3 && 8028 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8029 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8030 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8031 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8032 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8033 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 8034 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #64"; 8035 break; 8036 } 8037 return NULL; 8038 case AArch64_LD1Fourv1d_POST: 8039 if (MCInst_getNumOperands(MI) == 3 && 8040 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8041 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8042 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8043 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8044 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8045 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 8046 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #32"; 8047 break; 8048 } 8049 return NULL; 8050 case AArch64_LD1Fourv2d_POST: 8051 if (MCInst_getNumOperands(MI) == 3 && 8052 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8053 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8054 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8055 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8056 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8057 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 8058 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #64"; 8059 break; 8060 } 8061 return NULL; 8062 case AArch64_LD1Fourv2s_POST: 8063 if (MCInst_getNumOperands(MI) == 3 && 8064 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8065 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8066 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8067 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8068 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8069 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 8070 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #32"; 8071 break; 8072 } 8073 return NULL; 8074 case AArch64_LD1Fourv4h_POST: 8075 if (MCInst_getNumOperands(MI) == 3 && 8076 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8077 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8078 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8079 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8080 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8081 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 8082 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #32"; 8083 break; 8084 } 8085 return NULL; 8086 case AArch64_LD1Fourv4s_POST: 8087 if (MCInst_getNumOperands(MI) == 3 && 8088 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8089 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8090 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8091 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8092 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8093 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 8094 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #64"; 8095 break; 8096 } 8097 return NULL; 8098 case AArch64_LD1Fourv8b_POST: 8099 if (MCInst_getNumOperands(MI) == 3 && 8100 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8101 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8102 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8103 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8104 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8105 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 8106 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #32"; 8107 break; 8108 } 8109 return NULL; 8110 case AArch64_LD1Fourv8h_POST: 8111 if (MCInst_getNumOperands(MI) == 3 && 8112 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8113 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8114 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8115 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8116 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8117 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 8118 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #64"; 8119 break; 8120 } 8121 return NULL; 8122 case AArch64_LD1Onev16b_POST: 8123 if (MCInst_getNumOperands(MI) == 3 && 8124 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8125 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8126 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8127 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8128 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8129 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 8130 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #16"; 8131 break; 8132 } 8133 return NULL; 8134 case AArch64_LD1Onev1d_POST: 8135 if (MCInst_getNumOperands(MI) == 3 && 8136 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8137 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8138 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8139 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8140 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8141 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 8142 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #8"; 8143 break; 8144 } 8145 return NULL; 8146 case AArch64_LD1Onev2d_POST: 8147 if (MCInst_getNumOperands(MI) == 3 && 8148 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8149 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8150 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8151 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8152 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8153 // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 8154 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #16"; 8155 break; 8156 } 8157 return NULL; 8158 case AArch64_LD1Onev2s_POST: 8159 if (MCInst_getNumOperands(MI) == 3 && 8160 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8161 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8162 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8163 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8164 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8165 // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 8166 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #8"; 8167 break; 8168 } 8169 return NULL; 8170 case AArch64_LD1Onev4h_POST: 8171 if (MCInst_getNumOperands(MI) == 3 && 8172 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8173 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8174 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8175 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8176 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8177 // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 8178 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #8"; 8179 break; 8180 } 8181 return NULL; 8182 case AArch64_LD1Onev4s_POST: 8183 if (MCInst_getNumOperands(MI) == 3 && 8184 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8185 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8186 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8187 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8188 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8189 // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 8190 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #16"; 8191 break; 8192 } 8193 return NULL; 8194 case AArch64_LD1Onev8b_POST: 8195 if (MCInst_getNumOperands(MI) == 3 && 8196 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8197 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8198 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8199 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8200 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8201 // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 8202 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #8"; 8203 break; 8204 } 8205 return NULL; 8206 case AArch64_LD1Onev8h_POST: 8207 if (MCInst_getNumOperands(MI) == 3 && 8208 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8209 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8210 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8211 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8212 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8213 // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 8214 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #16"; 8215 break; 8216 } 8217 return NULL; 8218 case AArch64_LD1Rv16b_POST: 8219 if (MCInst_getNumOperands(MI) == 3 && 8220 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8221 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8222 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8223 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8224 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8225 // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 8226 AsmString = "ld1r $\xFF\x02\x0A, [$\x01], #1"; 8227 break; 8228 } 8229 return NULL; 8230 case AArch64_LD1Rv1d_POST: 8231 if (MCInst_getNumOperands(MI) == 3 && 8232 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8233 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8234 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8235 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8236 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8237 // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 8238 AsmString = "ld1r $\xFF\x02\x0B, [$\x01], #8"; 8239 break; 8240 } 8241 return NULL; 8242 case AArch64_LD1Rv2d_POST: 8243 if (MCInst_getNumOperands(MI) == 3 && 8244 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8245 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8246 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8247 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8248 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8249 // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 8250 AsmString = "ld1r $\xFF\x02\x0C, [$\x01], #8"; 8251 break; 8252 } 8253 return NULL; 8254 case AArch64_LD1Rv2s_POST: 8255 if (MCInst_getNumOperands(MI) == 3 && 8256 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8257 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8258 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8259 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8260 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8261 // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 8262 AsmString = "ld1r $\xFF\x02\x0D, [$\x01], #4"; 8263 break; 8264 } 8265 return NULL; 8266 case AArch64_LD1Rv4h_POST: 8267 if (MCInst_getNumOperands(MI) == 3 && 8268 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8269 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8270 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8271 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8272 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8273 // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 8274 AsmString = "ld1r $\xFF\x02\x0E, [$\x01], #2"; 8275 break; 8276 } 8277 return NULL; 8278 case AArch64_LD1Rv4s_POST: 8279 if (MCInst_getNumOperands(MI) == 3 && 8280 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8281 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8282 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8283 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8284 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8285 // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 8286 AsmString = "ld1r $\xFF\x02\x0F, [$\x01], #4"; 8287 break; 8288 } 8289 return NULL; 8290 case AArch64_LD1Rv8b_POST: 8291 if (MCInst_getNumOperands(MI) == 3 && 8292 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8293 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8294 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8295 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8296 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8297 // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 8298 AsmString = "ld1r $\xFF\x02\x10, [$\x01], #1"; 8299 break; 8300 } 8301 return NULL; 8302 case AArch64_LD1Rv8h_POST: 8303 if (MCInst_getNumOperands(MI) == 3 && 8304 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8305 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8306 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8307 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8308 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8309 // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 8310 AsmString = "ld1r $\xFF\x02\x11, [$\x01], #2"; 8311 break; 8312 } 8313 return NULL; 8314 case AArch64_LD1Threev16b_POST: 8315 if (MCInst_getNumOperands(MI) == 3 && 8316 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8317 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8318 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8319 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8320 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8321 // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8322 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #48"; 8323 break; 8324 } 8325 return NULL; 8326 case AArch64_LD1Threev1d_POST: 8327 if (MCInst_getNumOperands(MI) == 3 && 8328 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8329 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8330 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8331 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8332 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8333 // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 8334 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #24"; 8335 break; 8336 } 8337 return NULL; 8338 case AArch64_LD1Threev2d_POST: 8339 if (MCInst_getNumOperands(MI) == 3 && 8340 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8341 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8342 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8343 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8344 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8345 // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8346 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #48"; 8347 break; 8348 } 8349 return NULL; 8350 case AArch64_LD1Threev2s_POST: 8351 if (MCInst_getNumOperands(MI) == 3 && 8352 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8353 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8354 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8355 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8356 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8357 // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8358 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #24"; 8359 break; 8360 } 8361 return NULL; 8362 case AArch64_LD1Threev4h_POST: 8363 if (MCInst_getNumOperands(MI) == 3 && 8364 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8365 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8366 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8367 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8368 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8369 // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8370 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #24"; 8371 break; 8372 } 8373 return NULL; 8374 case AArch64_LD1Threev4s_POST: 8375 if (MCInst_getNumOperands(MI) == 3 && 8376 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8377 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8378 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8379 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8380 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8381 // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8382 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #48"; 8383 break; 8384 } 8385 return NULL; 8386 case AArch64_LD1Threev8b_POST: 8387 if (MCInst_getNumOperands(MI) == 3 && 8388 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8389 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8390 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8391 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8392 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8393 // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8394 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #24"; 8395 break; 8396 } 8397 return NULL; 8398 case AArch64_LD1Threev8h_POST: 8399 if (MCInst_getNumOperands(MI) == 3 && 8400 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8401 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8402 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8403 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8404 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8405 // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8406 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #48"; 8407 break; 8408 } 8409 return NULL; 8410 case AArch64_LD1Twov16b_POST: 8411 if (MCInst_getNumOperands(MI) == 3 && 8412 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8413 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8414 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8415 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8416 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8417 // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8418 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #32"; 8419 break; 8420 } 8421 return NULL; 8422 case AArch64_LD1Twov1d_POST: 8423 if (MCInst_getNumOperands(MI) == 3 && 8424 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8425 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8426 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8427 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8428 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8429 // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 8430 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #16"; 8431 break; 8432 } 8433 return NULL; 8434 case AArch64_LD1Twov2d_POST: 8435 if (MCInst_getNumOperands(MI) == 3 && 8436 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8437 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8438 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8439 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8440 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8441 // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8442 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #32"; 8443 break; 8444 } 8445 return NULL; 8446 case AArch64_LD1Twov2s_POST: 8447 if (MCInst_getNumOperands(MI) == 3 && 8448 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8449 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8450 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8451 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8452 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8453 // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8454 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #16"; 8455 break; 8456 } 8457 return NULL; 8458 case AArch64_LD1Twov4h_POST: 8459 if (MCInst_getNumOperands(MI) == 3 && 8460 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8461 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8462 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8463 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8464 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8465 // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8466 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #16"; 8467 break; 8468 } 8469 return NULL; 8470 case AArch64_LD1Twov4s_POST: 8471 if (MCInst_getNumOperands(MI) == 3 && 8472 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8473 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8474 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8475 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8476 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8477 // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8478 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #32"; 8479 break; 8480 } 8481 return NULL; 8482 case AArch64_LD1Twov8b_POST: 8483 if (MCInst_getNumOperands(MI) == 3 && 8484 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8485 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8486 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8487 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8488 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8489 // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8490 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #16"; 8491 break; 8492 } 8493 return NULL; 8494 case AArch64_LD1Twov8h_POST: 8495 if (MCInst_getNumOperands(MI) == 3 && 8496 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8497 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8498 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8499 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8500 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8501 // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8502 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #32"; 8503 break; 8504 } 8505 return NULL; 8506 case AArch64_LD1i16_POST: 8507 if (MCInst_getNumOperands(MI) == 4 && 8508 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8509 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8510 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8511 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8512 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8513 // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) 8514 AsmString = "ld1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; 8515 break; 8516 } 8517 return NULL; 8518 case AArch64_LD1i32_POST: 8519 if (MCInst_getNumOperands(MI) == 4 && 8520 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8521 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8522 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8523 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8524 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8525 // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) 8526 AsmString = "ld1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; 8527 break; 8528 } 8529 return NULL; 8530 case AArch64_LD1i64_POST: 8531 if (MCInst_getNumOperands(MI) == 4 && 8532 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8533 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8534 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8535 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8536 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8537 // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) 8538 AsmString = "ld1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; 8539 break; 8540 } 8541 return NULL; 8542 case AArch64_LD1i8_POST: 8543 if (MCInst_getNumOperands(MI) == 4 && 8544 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8545 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8546 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8547 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8548 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8549 // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) 8550 AsmString = "ld1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; 8551 break; 8552 } 8553 return NULL; 8554 case AArch64_LD2Rv16b_POST: 8555 if (MCInst_getNumOperands(MI) == 3 && 8556 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8557 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8558 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8559 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8560 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8561 // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8562 AsmString = "ld2r $\xFF\x02\x0A, [$\x01], #2"; 8563 break; 8564 } 8565 return NULL; 8566 case AArch64_LD2Rv1d_POST: 8567 if (MCInst_getNumOperands(MI) == 3 && 8568 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8569 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8570 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8571 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8572 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8573 // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 8574 AsmString = "ld2r $\xFF\x02\x0B, [$\x01], #16"; 8575 break; 8576 } 8577 return NULL; 8578 case AArch64_LD2Rv2d_POST: 8579 if (MCInst_getNumOperands(MI) == 3 && 8580 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8581 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8582 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8583 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8584 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8585 // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8586 AsmString = "ld2r $\xFF\x02\x0C, [$\x01], #16"; 8587 break; 8588 } 8589 return NULL; 8590 case AArch64_LD2Rv2s_POST: 8591 if (MCInst_getNumOperands(MI) == 3 && 8592 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8593 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8594 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8595 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8596 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8597 // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8598 AsmString = "ld2r $\xFF\x02\x0D, [$\x01], #8"; 8599 break; 8600 } 8601 return NULL; 8602 case AArch64_LD2Rv4h_POST: 8603 if (MCInst_getNumOperands(MI) == 3 && 8604 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8605 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8606 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8607 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8608 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8609 // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8610 AsmString = "ld2r $\xFF\x02\x0E, [$\x01], #4"; 8611 break; 8612 } 8613 return NULL; 8614 case AArch64_LD2Rv4s_POST: 8615 if (MCInst_getNumOperands(MI) == 3 && 8616 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8617 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8618 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8619 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8620 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8621 // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8622 AsmString = "ld2r $\xFF\x02\x0F, [$\x01], #8"; 8623 break; 8624 } 8625 return NULL; 8626 case AArch64_LD2Rv8b_POST: 8627 if (MCInst_getNumOperands(MI) == 3 && 8628 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8629 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8630 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8631 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8632 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8633 // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8634 AsmString = "ld2r $\xFF\x02\x10, [$\x01], #2"; 8635 break; 8636 } 8637 return NULL; 8638 case AArch64_LD2Rv8h_POST: 8639 if (MCInst_getNumOperands(MI) == 3 && 8640 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8641 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8642 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8643 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8644 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8645 // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8646 AsmString = "ld2r $\xFF\x02\x11, [$\x01], #4"; 8647 break; 8648 } 8649 return NULL; 8650 case AArch64_LD2Twov16b_POST: 8651 if (MCInst_getNumOperands(MI) == 3 && 8652 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8653 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8654 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8655 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8656 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8657 // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8658 AsmString = "ld2 $\xFF\x02\x0A, [$\x01], #32"; 8659 break; 8660 } 8661 return NULL; 8662 case AArch64_LD2Twov2d_POST: 8663 if (MCInst_getNumOperands(MI) == 3 && 8664 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8665 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8666 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8667 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8668 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8669 // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8670 AsmString = "ld2 $\xFF\x02\x0C, [$\x01], #32"; 8671 break; 8672 } 8673 return NULL; 8674 case AArch64_LD2Twov2s_POST: 8675 if (MCInst_getNumOperands(MI) == 3 && 8676 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8677 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8678 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8679 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8680 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8681 // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8682 AsmString = "ld2 $\xFF\x02\x0D, [$\x01], #16"; 8683 break; 8684 } 8685 return NULL; 8686 case AArch64_LD2Twov4h_POST: 8687 if (MCInst_getNumOperands(MI) == 3 && 8688 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8689 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8690 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8691 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8692 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8693 // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8694 AsmString = "ld2 $\xFF\x02\x0E, [$\x01], #16"; 8695 break; 8696 } 8697 return NULL; 8698 case AArch64_LD2Twov4s_POST: 8699 if (MCInst_getNumOperands(MI) == 3 && 8700 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8701 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8702 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8703 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8704 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8705 // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8706 AsmString = "ld2 $\xFF\x02\x0F, [$\x01], #32"; 8707 break; 8708 } 8709 return NULL; 8710 case AArch64_LD2Twov8b_POST: 8711 if (MCInst_getNumOperands(MI) == 3 && 8712 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8713 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8714 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8715 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8716 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8717 // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8718 AsmString = "ld2 $\xFF\x02\x10, [$\x01], #16"; 8719 break; 8720 } 8721 return NULL; 8722 case AArch64_LD2Twov8h_POST: 8723 if (MCInst_getNumOperands(MI) == 3 && 8724 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8725 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8726 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8727 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8728 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8729 // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8730 AsmString = "ld2 $\xFF\x02\x11, [$\x01], #32"; 8731 break; 8732 } 8733 return NULL; 8734 case AArch64_LD2i16_POST: 8735 if (MCInst_getNumOperands(MI) == 4 && 8736 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8737 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8738 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8739 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8740 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8741 // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) 8742 AsmString = "ld2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; 8743 break; 8744 } 8745 return NULL; 8746 case AArch64_LD2i32_POST: 8747 if (MCInst_getNumOperands(MI) == 4 && 8748 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8749 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8750 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8751 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8752 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8753 // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) 8754 AsmString = "ld2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; 8755 break; 8756 } 8757 return NULL; 8758 case AArch64_LD2i64_POST: 8759 if (MCInst_getNumOperands(MI) == 4 && 8760 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8761 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8762 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8763 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8764 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8765 // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) 8766 AsmString = "ld2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; 8767 break; 8768 } 8769 return NULL; 8770 case AArch64_LD2i8_POST: 8771 if (MCInst_getNumOperands(MI) == 4 && 8772 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8773 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8774 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8775 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8776 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8777 // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) 8778 AsmString = "ld2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; 8779 break; 8780 } 8781 return NULL; 8782 case AArch64_LD3Rv16b_POST: 8783 if (MCInst_getNumOperands(MI) == 3 && 8784 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8785 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8786 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8787 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8788 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8789 // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8790 AsmString = "ld3r $\xFF\x02\x0A, [$\x01], #3"; 8791 break; 8792 } 8793 return NULL; 8794 case AArch64_LD3Rv1d_POST: 8795 if (MCInst_getNumOperands(MI) == 3 && 8796 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8797 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8798 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8799 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8800 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8801 // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 8802 AsmString = "ld3r $\xFF\x02\x0B, [$\x01], #24"; 8803 break; 8804 } 8805 return NULL; 8806 case AArch64_LD3Rv2d_POST: 8807 if (MCInst_getNumOperands(MI) == 3 && 8808 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8809 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8810 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8811 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8812 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8813 // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8814 AsmString = "ld3r $\xFF\x02\x0C, [$\x01], #24"; 8815 break; 8816 } 8817 return NULL; 8818 case AArch64_LD3Rv2s_POST: 8819 if (MCInst_getNumOperands(MI) == 3 && 8820 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8821 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8822 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8823 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8824 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8825 // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8826 AsmString = "ld3r $\xFF\x02\x0D, [$\x01], #12"; 8827 break; 8828 } 8829 return NULL; 8830 case AArch64_LD3Rv4h_POST: 8831 if (MCInst_getNumOperands(MI) == 3 && 8832 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8833 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8834 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8835 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8836 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8837 // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8838 AsmString = "ld3r $\xFF\x02\x0E, [$\x01], #6"; 8839 break; 8840 } 8841 return NULL; 8842 case AArch64_LD3Rv4s_POST: 8843 if (MCInst_getNumOperands(MI) == 3 && 8844 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8845 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8846 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8847 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8848 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8849 // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8850 AsmString = "ld3r $\xFF\x02\x0F, [$\x01], #12"; 8851 break; 8852 } 8853 return NULL; 8854 case AArch64_LD3Rv8b_POST: 8855 if (MCInst_getNumOperands(MI) == 3 && 8856 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8857 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8858 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8859 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8860 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8861 // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8862 AsmString = "ld3r $\xFF\x02\x10, [$\x01], #3"; 8863 break; 8864 } 8865 return NULL; 8866 case AArch64_LD3Rv8h_POST: 8867 if (MCInst_getNumOperands(MI) == 3 && 8868 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8869 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8870 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8871 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8872 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8873 // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8874 AsmString = "ld3r $\xFF\x02\x11, [$\x01], #6"; 8875 break; 8876 } 8877 return NULL; 8878 case AArch64_LD3Threev16b_POST: 8879 if (MCInst_getNumOperands(MI) == 3 && 8880 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8881 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8882 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8883 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8884 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8885 // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8886 AsmString = "ld3 $\xFF\x02\x0A, [$\x01], #48"; 8887 break; 8888 } 8889 return NULL; 8890 case AArch64_LD3Threev2d_POST: 8891 if (MCInst_getNumOperands(MI) == 3 && 8892 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8893 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8894 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8895 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8896 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8897 // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8898 AsmString = "ld3 $\xFF\x02\x0C, [$\x01], #48"; 8899 break; 8900 } 8901 return NULL; 8902 case AArch64_LD3Threev2s_POST: 8903 if (MCInst_getNumOperands(MI) == 3 && 8904 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8905 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8906 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8907 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8908 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8909 // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8910 AsmString = "ld3 $\xFF\x02\x0D, [$\x01], #24"; 8911 break; 8912 } 8913 return NULL; 8914 case AArch64_LD3Threev4h_POST: 8915 if (MCInst_getNumOperands(MI) == 3 && 8916 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8917 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8918 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8919 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8920 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8921 // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8922 AsmString = "ld3 $\xFF\x02\x0E, [$\x01], #24"; 8923 break; 8924 } 8925 return NULL; 8926 case AArch64_LD3Threev4s_POST: 8927 if (MCInst_getNumOperands(MI) == 3 && 8928 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8929 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8930 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8931 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8932 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8933 // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8934 AsmString = "ld3 $\xFF\x02\x0F, [$\x01], #48"; 8935 break; 8936 } 8937 return NULL; 8938 case AArch64_LD3Threev8b_POST: 8939 if (MCInst_getNumOperands(MI) == 3 && 8940 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8941 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8942 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8943 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8944 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8945 // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8946 AsmString = "ld3 $\xFF\x02\x10, [$\x01], #24"; 8947 break; 8948 } 8949 return NULL; 8950 case AArch64_LD3Threev8h_POST: 8951 if (MCInst_getNumOperands(MI) == 3 && 8952 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8953 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8954 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8955 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8956 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8957 // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8958 AsmString = "ld3 $\xFF\x02\x11, [$\x01], #48"; 8959 break; 8960 } 8961 return NULL; 8962 case AArch64_LD3i16_POST: 8963 if (MCInst_getNumOperands(MI) == 4 && 8964 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8965 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8966 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8967 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8968 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8969 // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) 8970 AsmString = "ld3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; 8971 break; 8972 } 8973 return NULL; 8974 case AArch64_LD3i32_POST: 8975 if (MCInst_getNumOperands(MI) == 4 && 8976 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8977 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8978 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8979 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8980 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8981 // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) 8982 AsmString = "ld3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; 8983 break; 8984 } 8985 return NULL; 8986 case AArch64_LD3i64_POST: 8987 if (MCInst_getNumOperands(MI) == 4 && 8988 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8989 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8990 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8991 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8992 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8993 // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) 8994 AsmString = "ld3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; 8995 break; 8996 } 8997 return NULL; 8998 case AArch64_LD3i8_POST: 8999 if (MCInst_getNumOperands(MI) == 4 && 9000 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9001 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9002 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9003 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 9004 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9005 // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) 9006 AsmString = "ld3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; 9007 break; 9008 } 9009 return NULL; 9010 case AArch64_LD4Fourv16b_POST: 9011 if (MCInst_getNumOperands(MI) == 3 && 9012 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9013 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9014 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9015 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9016 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9017 // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 9018 AsmString = "ld4 $\xFF\x02\x0A, [$\x01], #64"; 9019 break; 9020 } 9021 return NULL; 9022 case AArch64_LD4Fourv2d_POST: 9023 if (MCInst_getNumOperands(MI) == 3 && 9024 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9025 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9026 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9027 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9028 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9029 // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 9030 AsmString = "ld4 $\xFF\x02\x0C, [$\x01], #64"; 9031 break; 9032 } 9033 return NULL; 9034 case AArch64_LD4Fourv2s_POST: 9035 if (MCInst_getNumOperands(MI) == 3 && 9036 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9037 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9038 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9039 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9040 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9041 // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 9042 AsmString = "ld4 $\xFF\x02\x0D, [$\x01], #32"; 9043 break; 9044 } 9045 return NULL; 9046 case AArch64_LD4Fourv4h_POST: 9047 if (MCInst_getNumOperands(MI) == 3 && 9048 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9049 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9050 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9051 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9052 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9053 // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 9054 AsmString = "ld4 $\xFF\x02\x0E, [$\x01], #32"; 9055 break; 9056 } 9057 return NULL; 9058 case AArch64_LD4Fourv4s_POST: 9059 if (MCInst_getNumOperands(MI) == 3 && 9060 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9061 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9062 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9063 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9064 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9065 // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 9066 AsmString = "ld4 $\xFF\x02\x0F, [$\x01], #64"; 9067 break; 9068 } 9069 return NULL; 9070 case AArch64_LD4Fourv8b_POST: 9071 if (MCInst_getNumOperands(MI) == 3 && 9072 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9073 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9074 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9075 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9076 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9077 // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 9078 AsmString = "ld4 $\xFF\x02\x10, [$\x01], #32"; 9079 break; 9080 } 9081 return NULL; 9082 case AArch64_LD4Fourv8h_POST: 9083 if (MCInst_getNumOperands(MI) == 3 && 9084 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9085 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9086 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9087 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9088 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9089 // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 9090 AsmString = "ld4 $\xFF\x02\x11, [$\x01], #64"; 9091 break; 9092 } 9093 return NULL; 9094 case AArch64_LD4Rv16b_POST: 9095 if (MCInst_getNumOperands(MI) == 3 && 9096 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9097 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9098 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9099 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9100 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9101 // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 9102 AsmString = "ld4r $\xFF\x02\x0A, [$\x01], #4"; 9103 break; 9104 } 9105 return NULL; 9106 case AArch64_LD4Rv1d_POST: 9107 if (MCInst_getNumOperands(MI) == 3 && 9108 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9109 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9110 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9111 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9112 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9113 // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 9114 AsmString = "ld4r $\xFF\x02\x0B, [$\x01], #32"; 9115 break; 9116 } 9117 return NULL; 9118 case AArch64_LD4Rv2d_POST: 9119 if (MCInst_getNumOperands(MI) == 3 && 9120 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9121 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9122 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9123 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9124 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9125 // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 9126 AsmString = "ld4r $\xFF\x02\x0C, [$\x01], #32"; 9127 break; 9128 } 9129 return NULL; 9130 case AArch64_LD4Rv2s_POST: 9131 if (MCInst_getNumOperands(MI) == 3 && 9132 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9133 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9134 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9135 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9136 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9137 // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 9138 AsmString = "ld4r $\xFF\x02\x0D, [$\x01], #16"; 9139 break; 9140 } 9141 return NULL; 9142 case AArch64_LD4Rv4h_POST: 9143 if (MCInst_getNumOperands(MI) == 3 && 9144 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9145 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9146 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9147 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9148 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9149 // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 9150 AsmString = "ld4r $\xFF\x02\x0E, [$\x01], #8"; 9151 break; 9152 } 9153 return NULL; 9154 case AArch64_LD4Rv4s_POST: 9155 if (MCInst_getNumOperands(MI) == 3 && 9156 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9157 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9158 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9159 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9160 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9161 // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 9162 AsmString = "ld4r $\xFF\x02\x0F, [$\x01], #16"; 9163 break; 9164 } 9165 return NULL; 9166 case AArch64_LD4Rv8b_POST: 9167 if (MCInst_getNumOperands(MI) == 3 && 9168 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9169 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9170 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9171 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9172 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9173 // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 9174 AsmString = "ld4r $\xFF\x02\x10, [$\x01], #4"; 9175 break; 9176 } 9177 return NULL; 9178 case AArch64_LD4Rv8h_POST: 9179 if (MCInst_getNumOperands(MI) == 3 && 9180 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9181 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9183 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9184 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9185 // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 9186 AsmString = "ld4r $\xFF\x02\x11, [$\x01], #8"; 9187 break; 9188 } 9189 return NULL; 9190 case AArch64_LD4i16_POST: 9191 if (MCInst_getNumOperands(MI) == 4 && 9192 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9193 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9195 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9196 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9197 // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) 9198 AsmString = "ld4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; 9199 break; 9200 } 9201 return NULL; 9202 case AArch64_LD4i32_POST: 9203 if (MCInst_getNumOperands(MI) == 4 && 9204 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9205 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9206 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9207 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9208 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9209 // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) 9210 AsmString = "ld4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; 9211 break; 9212 } 9213 return NULL; 9214 case AArch64_LD4i64_POST: 9215 if (MCInst_getNumOperands(MI) == 4 && 9216 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9217 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9218 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9219 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9220 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9221 // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) 9222 AsmString = "ld4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; 9223 break; 9224 } 9225 return NULL; 9226 case AArch64_LD4i8_POST: 9227 if (MCInst_getNumOperands(MI) == 4 && 9228 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9229 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9230 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9231 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9232 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9233 // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) 9234 AsmString = "ld4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; 9235 break; 9236 } 9237 return NULL; 9238 case AArch64_LDNPDi: 9239 if (MCInst_getNumOperands(MI) == 4 && 9240 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9241 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9242 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9243 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 9244 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9245 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9246 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9247 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9248 // (LDNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 9249 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9250 break; 9251 } 9252 return NULL; 9253 case AArch64_LDNPQi: 9254 if (MCInst_getNumOperands(MI) == 4 && 9255 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9256 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9257 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9258 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 9259 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9260 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9261 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9262 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9263 // (LDNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 9264 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9265 break; 9266 } 9267 return NULL; 9268 case AArch64_LDNPSi: 9269 if (MCInst_getNumOperands(MI) == 4 && 9270 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9271 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9272 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9273 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 9274 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9275 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9276 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9277 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9278 // (LDNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 9279 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9280 break; 9281 } 9282 return NULL; 9283 case AArch64_LDNPWi: 9284 if (MCInst_getNumOperands(MI) == 4 && 9285 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9286 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9287 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9288 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 9289 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9290 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9291 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9292 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9293 // (LDNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 9294 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9295 break; 9296 } 9297 return NULL; 9298 case AArch64_LDNPXi: 9299 if (MCInst_getNumOperands(MI) == 4 && 9300 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9301 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9302 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9303 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9304 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9305 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9306 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9307 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9308 // (LDNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9309 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9310 break; 9311 } 9312 return NULL; 9313 case AArch64_LDPDi: 9314 if (MCInst_getNumOperands(MI) == 4 && 9315 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9316 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9317 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9318 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 9319 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9320 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9321 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9322 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9323 // (LDPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 9324 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9325 break; 9326 } 9327 return NULL; 9328 case AArch64_LDPQi: 9329 if (MCInst_getNumOperands(MI) == 4 && 9330 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9331 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9332 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9333 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 9334 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9335 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9336 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9337 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9338 // (LDPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 9339 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9340 break; 9341 } 9342 return NULL; 9343 case AArch64_LDPSWi: 9344 if (MCInst_getNumOperands(MI) == 4 && 9345 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9346 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9347 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9348 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9349 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9350 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9351 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9352 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9353 // (LDPSWi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9354 AsmString = "ldpsw $\x01, $\x02, [$\x03]"; 9355 break; 9356 } 9357 return NULL; 9358 case AArch64_LDPSi: 9359 if (MCInst_getNumOperands(MI) == 4 && 9360 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9361 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9362 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9363 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 9364 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9365 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9366 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9367 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9368 // (LDPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 9369 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9370 break; 9371 } 9372 return NULL; 9373 case AArch64_LDPWi: 9374 if (MCInst_getNumOperands(MI) == 4 && 9375 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9376 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9377 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9378 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 9379 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9380 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9381 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9382 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9383 // (LDPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 9384 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9385 break; 9386 } 9387 return NULL; 9388 case AArch64_LDPXi: 9389 if (MCInst_getNumOperands(MI) == 4 && 9390 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9391 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9392 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9393 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9394 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9395 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9396 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9397 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9398 // (LDPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9399 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9400 break; 9401 } 9402 return NULL; 9403 case AArch64_LDRBBroX: 9404 if (MCInst_getNumOperands(MI) == 5 && 9405 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9406 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9407 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9408 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9409 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9410 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9411 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9412 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9413 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9414 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9415 // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9416 AsmString = "ldrb $\x01, [$\x02, $\x03]"; 9417 break; 9418 } 9419 return NULL; 9420 case AArch64_LDRBBui: 9421 if (MCInst_getNumOperands(MI) == 3 && 9422 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9423 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9424 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9425 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9426 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9427 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9428 // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) 9429 AsmString = "ldrb $\x01, [$\x02]"; 9430 break; 9431 } 9432 return NULL; 9433 case AArch64_LDRBroX: 9434 if (MCInst_getNumOperands(MI) == 5 && 9435 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9436 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9437 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9438 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9439 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9440 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9441 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9442 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9443 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9444 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9445 // (LDRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9446 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9447 break; 9448 } 9449 return NULL; 9450 case AArch64_LDRBui: 9451 if (MCInst_getNumOperands(MI) == 3 && 9452 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9453 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9454 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9455 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9456 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9457 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9458 // (LDRBui FPR8:$Rt, GPR64sp:$Rn, 0) 9459 AsmString = "ldr $\x01, [$\x02]"; 9460 break; 9461 } 9462 return NULL; 9463 case AArch64_LDRDroX: 9464 if (MCInst_getNumOperands(MI) == 5 && 9465 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9466 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9467 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9468 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9469 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9470 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9471 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9472 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9473 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9474 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9475 // (LDRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9476 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9477 break; 9478 } 9479 return NULL; 9480 case AArch64_LDRDui: 9481 if (MCInst_getNumOperands(MI) == 3 && 9482 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9483 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9484 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9485 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9486 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9487 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9488 // (LDRDui FPR64:$Rt, GPR64sp:$Rn, 0) 9489 AsmString = "ldr $\x01, [$\x02]"; 9490 break; 9491 } 9492 return NULL; 9493 case AArch64_LDRHHroX: 9494 if (MCInst_getNumOperands(MI) == 5 && 9495 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9496 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9497 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9498 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9499 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9500 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9501 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9502 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9503 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9504 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9505 // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9506 AsmString = "ldrh $\x01, [$\x02, $\x03]"; 9507 break; 9508 } 9509 return NULL; 9510 case AArch64_LDRHHui: 9511 if (MCInst_getNumOperands(MI) == 3 && 9512 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9513 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9514 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9515 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9516 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9517 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9518 // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) 9519 AsmString = "ldrh $\x01, [$\x02]"; 9520 break; 9521 } 9522 return NULL; 9523 case AArch64_LDRHroX: 9524 if (MCInst_getNumOperands(MI) == 5 && 9525 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9526 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9527 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9528 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9529 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9530 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9531 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9532 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9533 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9534 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9535 // (LDRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9536 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9537 break; 9538 } 9539 return NULL; 9540 case AArch64_LDRHui: 9541 if (MCInst_getNumOperands(MI) == 3 && 9542 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9543 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9544 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9545 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9546 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9547 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9548 // (LDRHui FPR16:$Rt, GPR64sp:$Rn, 0) 9549 AsmString = "ldr $\x01, [$\x02]"; 9550 break; 9551 } 9552 return NULL; 9553 case AArch64_LDRQroX: 9554 if (MCInst_getNumOperands(MI) == 5 && 9555 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9556 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9557 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9558 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9559 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9560 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9561 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9562 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9563 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9564 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9565 // (LDRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9566 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9567 break; 9568 } 9569 return NULL; 9570 case AArch64_LDRQui: 9571 if (MCInst_getNumOperands(MI) == 3 && 9572 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9573 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9574 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9575 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9576 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9577 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9578 // (LDRQui FPR128:$Rt, GPR64sp:$Rn, 0) 9579 AsmString = "ldr $\x01, [$\x02]"; 9580 break; 9581 } 9582 return NULL; 9583 case AArch64_LDRSBWroX: 9584 if (MCInst_getNumOperands(MI) == 5 && 9585 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9586 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9587 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9588 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9589 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9590 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9591 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9592 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9593 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9594 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9595 // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9596 AsmString = "ldrsb $\x01, [$\x02, $\x03]"; 9597 break; 9598 } 9599 return NULL; 9600 case AArch64_LDRSBWui: 9601 if (MCInst_getNumOperands(MI) == 3 && 9602 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9603 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9604 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9605 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9606 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9607 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9608 // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) 9609 AsmString = "ldrsb $\x01, [$\x02]"; 9610 break; 9611 } 9612 return NULL; 9613 case AArch64_LDRSBXroX: 9614 if (MCInst_getNumOperands(MI) == 5 && 9615 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9616 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9617 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9618 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9619 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9620 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9621 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9622 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9623 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9624 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9625 // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9626 AsmString = "ldrsb $\x01, [$\x02, $\x03]"; 9627 break; 9628 } 9629 return NULL; 9630 case AArch64_LDRSBXui: 9631 if (MCInst_getNumOperands(MI) == 3 && 9632 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9633 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9634 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9635 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9636 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9637 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9638 // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) 9639 AsmString = "ldrsb $\x01, [$\x02]"; 9640 break; 9641 } 9642 return NULL; 9643 case AArch64_LDRSHWroX: 9644 if (MCInst_getNumOperands(MI) == 5 && 9645 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9646 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9647 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9648 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9649 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9650 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9651 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9652 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9653 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9654 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9655 // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9656 AsmString = "ldrsh $\x01, [$\x02, $\x03]"; 9657 break; 9658 } 9659 return NULL; 9660 case AArch64_LDRSHWui: 9661 if (MCInst_getNumOperands(MI) == 3 && 9662 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9663 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9664 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9665 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9666 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9667 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9668 // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) 9669 AsmString = "ldrsh $\x01, [$\x02]"; 9670 break; 9671 } 9672 return NULL; 9673 case AArch64_LDRSHXroX: 9674 if (MCInst_getNumOperands(MI) == 5 && 9675 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9676 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9677 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9678 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9679 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9680 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9681 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9682 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9683 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9684 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9685 // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9686 AsmString = "ldrsh $\x01, [$\x02, $\x03]"; 9687 break; 9688 } 9689 return NULL; 9690 case AArch64_LDRSHXui: 9691 if (MCInst_getNumOperands(MI) == 3 && 9692 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9693 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9694 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9695 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9696 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9697 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9698 // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) 9699 AsmString = "ldrsh $\x01, [$\x02]"; 9700 break; 9701 } 9702 return NULL; 9703 case AArch64_LDRSWroX: 9704 if (MCInst_getNumOperands(MI) == 5 && 9705 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9706 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9707 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9708 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9709 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9710 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9711 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9712 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9713 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9714 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9715 // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9716 AsmString = "ldrsw $\x01, [$\x02, $\x03]"; 9717 break; 9718 } 9719 return NULL; 9720 case AArch64_LDRSWui: 9721 if (MCInst_getNumOperands(MI) == 3 && 9722 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9723 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9724 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9725 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9726 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9727 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9728 // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) 9729 AsmString = "ldrsw $\x01, [$\x02]"; 9730 break; 9731 } 9732 return NULL; 9733 case AArch64_LDRSroX: 9734 if (MCInst_getNumOperands(MI) == 5 && 9735 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9736 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9737 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9738 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9739 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9740 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9741 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9742 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9743 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9744 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9745 // (LDRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9746 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9747 break; 9748 } 9749 return NULL; 9750 case AArch64_LDRSui: 9751 if (MCInst_getNumOperands(MI) == 3 && 9752 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9753 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9754 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9755 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9756 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9757 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9758 // (LDRSui FPR32:$Rt, GPR64sp:$Rn, 0) 9759 AsmString = "ldr $\x01, [$\x02]"; 9760 break; 9761 } 9762 return NULL; 9763 case AArch64_LDRWroX: 9764 if (MCInst_getNumOperands(MI) == 5 && 9765 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9766 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9767 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9768 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9769 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9770 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9771 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9772 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9773 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9774 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9775 // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9776 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9777 break; 9778 } 9779 return NULL; 9780 case AArch64_LDRWui: 9781 if (MCInst_getNumOperands(MI) == 3 && 9782 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9783 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9784 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9785 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9786 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9787 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9788 // (LDRWui GPR32:$Rt, GPR64sp:$Rn, 0) 9789 AsmString = "ldr $\x01, [$\x02]"; 9790 break; 9791 } 9792 return NULL; 9793 case AArch64_LDRXroX: 9794 if (MCInst_getNumOperands(MI) == 5 && 9795 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9796 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9797 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9798 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9799 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9800 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9801 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9802 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9803 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9804 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9805 // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9806 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9807 break; 9808 } 9809 return NULL; 9810 case AArch64_LDRXui: 9811 if (MCInst_getNumOperands(MI) == 3 && 9812 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9813 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9814 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9815 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9816 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9817 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9818 // (LDRXui GPR64:$Rt, GPR64sp:$Rn, 0) 9819 AsmString = "ldr $\x01, [$\x02]"; 9820 break; 9821 } 9822 return NULL; 9823 case AArch64_LDTRBi: 9824 if (MCInst_getNumOperands(MI) == 3 && 9825 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9826 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9827 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9828 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9829 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9830 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9831 // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) 9832 AsmString = "ldtrb $\x01, [$\x02]"; 9833 break; 9834 } 9835 return NULL; 9836 case AArch64_LDTRHi: 9837 if (MCInst_getNumOperands(MI) == 3 && 9838 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9839 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9840 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9841 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9842 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9843 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9844 // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) 9845 AsmString = "ldtrh $\x01, [$\x02]"; 9846 break; 9847 } 9848 return NULL; 9849 case AArch64_LDTRSBWi: 9850 if (MCInst_getNumOperands(MI) == 3 && 9851 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9852 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9853 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9854 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9855 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9856 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9857 // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) 9858 AsmString = "ldtrsb $\x01, [$\x02]"; 9859 break; 9860 } 9861 return NULL; 9862 case AArch64_LDTRSBXi: 9863 if (MCInst_getNumOperands(MI) == 3 && 9864 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9865 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9866 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9867 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9868 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9869 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9870 // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) 9871 AsmString = "ldtrsb $\x01, [$\x02]"; 9872 break; 9873 } 9874 return NULL; 9875 case AArch64_LDTRSHWi: 9876 if (MCInst_getNumOperands(MI) == 3 && 9877 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9878 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9879 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9880 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9881 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9882 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9883 // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) 9884 AsmString = "ldtrsh $\x01, [$\x02]"; 9885 break; 9886 } 9887 return NULL; 9888 case AArch64_LDTRSHXi: 9889 if (MCInst_getNumOperands(MI) == 3 && 9890 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9891 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9892 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9893 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9894 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9895 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9896 // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) 9897 AsmString = "ldtrsh $\x01, [$\x02]"; 9898 break; 9899 } 9900 return NULL; 9901 case AArch64_LDTRSWi: 9902 if (MCInst_getNumOperands(MI) == 3 && 9903 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9904 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9905 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9906 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9907 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9908 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9909 // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) 9910 AsmString = "ldtrsw $\x01, [$\x02]"; 9911 break; 9912 } 9913 return NULL; 9914 case AArch64_LDTRWi: 9915 if (MCInst_getNumOperands(MI) == 3 && 9916 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9917 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9918 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9919 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9920 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9921 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9922 // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) 9923 AsmString = "ldtr $\x01, [$\x02]"; 9924 break; 9925 } 9926 return NULL; 9927 case AArch64_LDTRXi: 9928 if (MCInst_getNumOperands(MI) == 3 && 9929 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9930 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9931 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9932 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9933 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9934 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9935 // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) 9936 AsmString = "ldtr $\x01, [$\x02]"; 9937 break; 9938 } 9939 return NULL; 9940 case AArch64_LDURBBi: 9941 if (MCInst_getNumOperands(MI) == 3 && 9942 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9943 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9944 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9945 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9946 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9947 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9948 // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) 9949 AsmString = "ldurb $\x01, [$\x02]"; 9950 break; 9951 } 9952 return NULL; 9953 case AArch64_LDURBi: 9954 if (MCInst_getNumOperands(MI) == 3 && 9955 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9956 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9957 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9958 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9959 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9960 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9961 // (LDURBi FPR8:$Rt, GPR64sp:$Rn, 0) 9962 AsmString = "ldur $\x01, [$\x02]"; 9963 break; 9964 } 9965 return NULL; 9966 case AArch64_LDURDi: 9967 if (MCInst_getNumOperands(MI) == 3 && 9968 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9969 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9970 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9971 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9972 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9973 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9974 // (LDURDi FPR64:$Rt, GPR64sp:$Rn, 0) 9975 AsmString = "ldur $\x01, [$\x02]"; 9976 break; 9977 } 9978 return NULL; 9979 case AArch64_LDURHHi: 9980 if (MCInst_getNumOperands(MI) == 3 && 9981 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9982 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9983 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9984 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9985 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9986 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9987 // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) 9988 AsmString = "ldurh $\x01, [$\x02]"; 9989 break; 9990 } 9991 return NULL; 9992 case AArch64_LDURHi: 9993 if (MCInst_getNumOperands(MI) == 3 && 9994 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9995 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9996 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9997 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9998 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9999 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10000 // (LDURHi FPR16:$Rt, GPR64sp:$Rn, 0) 10001 AsmString = "ldur $\x01, [$\x02]"; 10002 break; 10003 } 10004 return NULL; 10005 case AArch64_LDURQi: 10006 if (MCInst_getNumOperands(MI) == 3 && 10007 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10008 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10009 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10010 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10011 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10012 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10013 // (LDURQi FPR128:$Rt, GPR64sp:$Rn, 0) 10014 AsmString = "ldur $\x01, [$\x02]"; 10015 break; 10016 } 10017 return NULL; 10018 case AArch64_LDURSBWi: 10019 if (MCInst_getNumOperands(MI) == 3 && 10020 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10021 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10022 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10023 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10024 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10025 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10026 // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) 10027 AsmString = "ldursb $\x01, [$\x02]"; 10028 break; 10029 } 10030 return NULL; 10031 case AArch64_LDURSBXi: 10032 if (MCInst_getNumOperands(MI) == 3 && 10033 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10034 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10035 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10036 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10037 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10038 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10039 // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) 10040 AsmString = "ldursb $\x01, [$\x02]"; 10041 break; 10042 } 10043 return NULL; 10044 case AArch64_LDURSHWi: 10045 if (MCInst_getNumOperands(MI) == 3 && 10046 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10047 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10048 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10049 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10050 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10051 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10052 // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) 10053 AsmString = "ldursh $\x01, [$\x02]"; 10054 break; 10055 } 10056 return NULL; 10057 case AArch64_LDURSHXi: 10058 if (MCInst_getNumOperands(MI) == 3 && 10059 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10060 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10061 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10062 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10063 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10064 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10065 // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) 10066 AsmString = "ldursh $\x01, [$\x02]"; 10067 break; 10068 } 10069 return NULL; 10070 case AArch64_LDURSWi: 10071 if (MCInst_getNumOperands(MI) == 3 && 10072 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10073 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10074 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10075 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10076 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10077 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10078 // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) 10079 AsmString = "ldursw $\x01, [$\x02]"; 10080 break; 10081 } 10082 return NULL; 10083 case AArch64_LDURSi: 10084 if (MCInst_getNumOperands(MI) == 3 && 10085 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10086 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 10087 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10088 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10089 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10090 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10091 // (LDURSi FPR32:$Rt, GPR64sp:$Rn, 0) 10092 AsmString = "ldur $\x01, [$\x02]"; 10093 break; 10094 } 10095 return NULL; 10096 case AArch64_LDURWi: 10097 if (MCInst_getNumOperands(MI) == 3 && 10098 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10099 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10100 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10101 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10102 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10103 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10104 // (LDURWi GPR32:$Rt, GPR64sp:$Rn, 0) 10105 AsmString = "ldur $\x01, [$\x02]"; 10106 break; 10107 } 10108 return NULL; 10109 case AArch64_LDURXi: 10110 if (MCInst_getNumOperands(MI) == 3 && 10111 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10112 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10113 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10114 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10115 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10116 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10117 // (LDURXi GPR64:$Rt, GPR64sp:$Rn, 0) 10118 AsmString = "ldur $\x01, [$\x02]"; 10119 break; 10120 } 10121 return NULL; 10122 case AArch64_MADDWrrr: 10123 if (MCInst_getNumOperands(MI) == 4 && 10124 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10125 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10126 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10127 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10128 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10129 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10130 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { 10131 // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) 10132 AsmString = "mul $\x01, $\x02, $\x03"; 10133 break; 10134 } 10135 return NULL; 10136 case AArch64_MADDXrrr: 10137 if (MCInst_getNumOperands(MI) == 4 && 10138 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10139 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10140 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10141 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10142 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10143 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10144 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10145 // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) 10146 AsmString = "mul $\x01, $\x02, $\x03"; 10147 break; 10148 } 10149 return NULL; 10150 case AArch64_MOVKWi: 10151 if (MCInst_getNumOperands(MI) == 3 && 10152 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10153 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10154 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10155 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { 10156 // (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16) 10157 AsmString = "movk $\x01, $\x02"; 10158 break; 10159 } 10160 return NULL; 10161 case AArch64_MOVKXi: 10162 if (MCInst_getNumOperands(MI) == 3 && 10163 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10164 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10165 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10166 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) { 10167 // (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48) 10168 AsmString = "movk $\x01, $\x02"; 10169 break; 10170 } 10171 if (MCInst_getNumOperands(MI) == 3 && 10172 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10173 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10174 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10175 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) { 10176 // (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32) 10177 AsmString = "movk $\x01, $\x02"; 10178 break; 10179 } 10180 if (MCInst_getNumOperands(MI) == 3 && 10181 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10182 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10183 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10184 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { 10185 // (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16) 10186 AsmString = "movk $\x01, $\x02"; 10187 break; 10188 } 10189 return NULL; 10190 case AArch64_MSUBWrrr: 10191 if (MCInst_getNumOperands(MI) == 4 && 10192 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10193 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10195 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10196 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10197 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10198 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { 10199 // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) 10200 AsmString = "mneg $\x01, $\x02, $\x03"; 10201 break; 10202 } 10203 return NULL; 10204 case AArch64_MSUBXrrr: 10205 if (MCInst_getNumOperands(MI) == 4 && 10206 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10207 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10208 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10209 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10210 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10211 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10212 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10213 // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) 10214 AsmString = "mneg $\x01, $\x02, $\x03"; 10215 break; 10216 } 10217 return NULL; 10218 case AArch64_NOTv16i8: 10219 if (MCInst_getNumOperands(MI) == 2 && 10220 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10221 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10222 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10223 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 10224 // (NOTv16i8 V128:$Vd, V128:$Vn) 10225 AsmString = "mvn $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; 10226 break; 10227 } 10228 return NULL; 10229 case AArch64_NOTv8i8: 10230 if (MCInst_getNumOperands(MI) == 2 && 10231 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10232 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10233 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10234 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { 10235 // (NOTv8i8 V64:$Vd, V64:$Vn) 10236 AsmString = "mvn $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; 10237 break; 10238 } 10239 return NULL; 10240 case AArch64_ORNWrs: 10241 if (MCInst_getNumOperands(MI) == 4 && 10242 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10243 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10244 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10245 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10246 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10247 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10248 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10249 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) 10250 AsmString = "mvn $\x01, $\x03"; 10251 break; 10252 } 10253 if (MCInst_getNumOperands(MI) == 4 && 10254 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10255 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10256 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10257 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10258 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10259 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) 10260 AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; 10261 break; 10262 } 10263 if (MCInst_getNumOperands(MI) == 4 && 10264 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10265 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10266 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10267 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10268 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10269 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10270 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10271 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10272 // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 10273 AsmString = "orn $\x01, $\x02, $\x03"; 10274 break; 10275 } 10276 return NULL; 10277 case AArch64_ORNXrs: 10278 if (MCInst_getNumOperands(MI) == 4 && 10279 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10280 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10281 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10282 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10283 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10284 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10285 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10286 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) 10287 AsmString = "mvn $\x01, $\x03"; 10288 break; 10289 } 10290 if (MCInst_getNumOperands(MI) == 4 && 10291 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10292 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10293 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10294 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10295 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10296 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) 10297 AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; 10298 break; 10299 } 10300 if (MCInst_getNumOperands(MI) == 4 && 10301 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10302 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10303 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10304 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10305 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10306 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10307 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10308 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10309 // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 10310 AsmString = "orn $\x01, $\x02, $\x03"; 10311 break; 10312 } 10313 return NULL; 10314 case AArch64_ORRWrs: 10315 if (MCInst_getNumOperands(MI) == 4 && 10316 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10317 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10318 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10319 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10320 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10321 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10322 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10323 // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) 10324 AsmString = "mov $\x01, $\x03"; 10325 break; 10326 } 10327 if (MCInst_getNumOperands(MI) == 4 && 10328 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10329 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10330 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10331 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10332 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10333 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10334 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10335 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10336 // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 10337 AsmString = "orr $\x01, $\x02, $\x03"; 10338 break; 10339 } 10340 return NULL; 10341 case AArch64_ORRXrs: 10342 if (MCInst_getNumOperands(MI) == 4 && 10343 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10344 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10345 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10346 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10347 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10348 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10349 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10350 // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) 10351 AsmString = "mov $\x01, $\x03"; 10352 break; 10353 } 10354 if (MCInst_getNumOperands(MI) == 4 && 10355 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10356 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10357 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10358 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10359 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10360 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10361 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10362 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10363 // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 10364 AsmString = "orr $\x01, $\x02, $\x03"; 10365 break; 10366 } 10367 return NULL; 10368 case AArch64_ORRv16i8: 10369 if (MCInst_getNumOperands(MI) == 3 && 10370 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10371 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10372 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10373 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10374 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10375 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 10376 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) 10377 AsmString = "mov $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; 10378 break; 10379 } 10380 return NULL; 10381 case AArch64_ORRv2i32: 10382 if (MCInst_getNumOperands(MI) == 3 && 10383 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10384 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10385 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10386 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10387 // (ORRv2i32 V64:$Vd, imm0_255:$imm, 0) 10388 AsmString = "orr $\xFF\x01\x06.2s, $\xFF\x02\x07"; 10389 break; 10390 } 10391 return NULL; 10392 case AArch64_ORRv4i16: 10393 if (MCInst_getNumOperands(MI) == 3 && 10394 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10395 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10396 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10397 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10398 // (ORRv4i16 V64:$Vd, imm0_255:$imm, 0) 10399 AsmString = "orr $\xFF\x01\x06.4h, $\xFF\x02\x07"; 10400 break; 10401 } 10402 return NULL; 10403 case AArch64_ORRv4i32: 10404 if (MCInst_getNumOperands(MI) == 3 && 10405 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10406 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10407 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10408 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10409 // (ORRv4i32 V128:$Vd, imm0_255:$imm, 0) 10410 AsmString = "orr $\xFF\x01\x06.4s, $\xFF\x02\x07"; 10411 break; 10412 } 10413 return NULL; 10414 case AArch64_ORRv8i16: 10415 if (MCInst_getNumOperands(MI) == 3 && 10416 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10417 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10418 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10419 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10420 // (ORRv8i16 V128:$Vd, imm0_255:$imm, 0) 10421 AsmString = "orr $\xFF\x01\x06.8h, $\xFF\x02\x07"; 10422 break; 10423 } 10424 return NULL; 10425 case AArch64_ORRv8i8: 10426 if (MCInst_getNumOperands(MI) == 3 && 10427 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10428 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10429 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10430 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10431 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10432 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 10433 // (ORRv8i8 V64:$dst, V64:$src, V64:$src) 10434 AsmString = "mov $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; 10435 break; 10436 } 10437 return NULL; 10438 case AArch64_PRFMroX: 10439 if (MCInst_getNumOperands(MI) == 5 && 10440 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10441 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10442 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10443 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10444 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10445 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 10446 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 10447 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 10448 // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 10449 AsmString = "prfm $\xFF\x01\x16, [$\x02, $\x03]"; 10450 break; 10451 } 10452 return NULL; 10453 case AArch64_PRFMui: 10454 if (MCInst_getNumOperands(MI) == 3 && 10455 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10456 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10457 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10458 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10459 // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) 10460 AsmString = "prfm $\xFF\x01\x16, [$\x02]"; 10461 break; 10462 } 10463 return NULL; 10464 case AArch64_PRFUMi: 10465 if (MCInst_getNumOperands(MI) == 3 && 10466 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10467 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10468 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10469 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10470 // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) 10471 AsmString = "prfum $\xFF\x01\x16, [$\x02]"; 10472 break; 10473 } 10474 return NULL; 10475 case AArch64_RET: 10476 if (MCInst_getNumOperands(MI) == 1 && 10477 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) { 10478 // (RET LR) 10479 AsmString = "ret"; 10480 break; 10481 } 10482 return NULL; 10483 case AArch64_SBCSWr: 10484 if (MCInst_getNumOperands(MI) == 3 && 10485 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10486 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10487 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10488 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10489 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10490 // (SBCSWr GPR32:$dst, WZR, GPR32:$src) 10491 AsmString = "ngcs $\x01, $\x03"; 10492 break; 10493 } 10494 return NULL; 10495 case AArch64_SBCSXr: 10496 if (MCInst_getNumOperands(MI) == 3 && 10497 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10498 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10499 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10500 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10501 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10502 // (SBCSXr GPR64:$dst, XZR, GPR64:$src) 10503 AsmString = "ngcs $\x01, $\x03"; 10504 break; 10505 } 10506 return NULL; 10507 case AArch64_SBCWr: 10508 if (MCInst_getNumOperands(MI) == 3 && 10509 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10510 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10511 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10512 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10513 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10514 // (SBCWr GPR32:$dst, WZR, GPR32:$src) 10515 AsmString = "ngc $\x01, $\x03"; 10516 break; 10517 } 10518 return NULL; 10519 case AArch64_SBCXr: 10520 if (MCInst_getNumOperands(MI) == 3 && 10521 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10522 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10523 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10524 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10525 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10526 // (SBCXr GPR64:$dst, XZR, GPR64:$src) 10527 AsmString = "ngc $\x01, $\x03"; 10528 break; 10529 } 10530 return NULL; 10531 case AArch64_SBFMWri: 10532 if (MCInst_getNumOperands(MI) == 4 && 10533 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10534 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10535 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10536 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10537 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10538 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 10539 // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) 10540 AsmString = "asr $\x01, $\x02, $\x03"; 10541 break; 10542 } 10543 if (MCInst_getNumOperands(MI) == 4 && 10544 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10545 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10546 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10547 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10548 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10549 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10550 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10551 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 10552 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) 10553 AsmString = "sxtb $\x01, $\x02"; 10554 break; 10555 } 10556 if (MCInst_getNumOperands(MI) == 4 && 10557 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10558 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10559 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10560 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10561 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10562 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10563 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10564 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 10565 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) 10566 AsmString = "sxth $\x01, $\x02"; 10567 break; 10568 } 10569 return NULL; 10570 case AArch64_SBFMXri: 10571 if (MCInst_getNumOperands(MI) == 4 && 10572 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10573 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10574 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10575 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10576 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10577 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { 10578 // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) 10579 AsmString = "asr $\x01, $\x02, $\x03"; 10580 break; 10581 } 10582 if (MCInst_getNumOperands(MI) == 4 && 10583 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10584 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10585 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10586 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10587 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10588 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10589 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10590 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 10591 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) 10592 AsmString = "sxtb $\x01, $\x02"; 10593 break; 10594 } 10595 if (MCInst_getNumOperands(MI) == 4 && 10596 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10597 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10598 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10599 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10600 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10601 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10602 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10603 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 10604 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) 10605 AsmString = "sxth $\x01, $\x02"; 10606 break; 10607 } 10608 if (MCInst_getNumOperands(MI) == 4 && 10609 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10610 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10611 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10612 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10613 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10614 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10615 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10616 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 10617 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) 10618 AsmString = "sxtw $\x01, $\x02"; 10619 break; 10620 } 10621 return NULL; 10622 case AArch64_SMADDLrrr: 10623 if (MCInst_getNumOperands(MI) == 4 && 10624 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10625 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10626 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10627 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10628 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10629 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10630 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10631 // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 10632 AsmString = "smull $\x01, $\x02, $\x03"; 10633 break; 10634 } 10635 return NULL; 10636 case AArch64_SMSUBLrrr: 10637 if (MCInst_getNumOperands(MI) == 4 && 10638 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10639 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10640 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10641 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10642 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10643 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10644 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10645 // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 10646 AsmString = "smnegl $\x01, $\x02, $\x03"; 10647 break; 10648 } 10649 return NULL; 10650 case AArch64_ST1Fourv16b_POST: 10651 if (MCInst_getNumOperands(MI) == 3 && 10652 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10653 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10654 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10655 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10656 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10657 // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 10658 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #64"; 10659 break; 10660 } 10661 return NULL; 10662 case AArch64_ST1Fourv1d_POST: 10663 if (MCInst_getNumOperands(MI) == 3 && 10664 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10665 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10666 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10667 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10668 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10669 // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 10670 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #32"; 10671 break; 10672 } 10673 return NULL; 10674 case AArch64_ST1Fourv2d_POST: 10675 if (MCInst_getNumOperands(MI) == 3 && 10676 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10677 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10678 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10679 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10680 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10681 // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 10682 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #64"; 10683 break; 10684 } 10685 return NULL; 10686 case AArch64_ST1Fourv2s_POST: 10687 if (MCInst_getNumOperands(MI) == 3 && 10688 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10689 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10690 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10691 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10692 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10693 // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 10694 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #32"; 10695 break; 10696 } 10697 return NULL; 10698 case AArch64_ST1Fourv4h_POST: 10699 if (MCInst_getNumOperands(MI) == 3 && 10700 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10701 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10702 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10703 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10704 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10705 // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 10706 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #32"; 10707 break; 10708 } 10709 return NULL; 10710 case AArch64_ST1Fourv4s_POST: 10711 if (MCInst_getNumOperands(MI) == 3 && 10712 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10713 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10714 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10715 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10716 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10717 // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 10718 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #64"; 10719 break; 10720 } 10721 return NULL; 10722 case AArch64_ST1Fourv8b_POST: 10723 if (MCInst_getNumOperands(MI) == 3 && 10724 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10725 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10726 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10727 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10728 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10729 // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 10730 AsmString = "st1 $\xFF\x02\x10, [$\x01], #32"; 10731 break; 10732 } 10733 return NULL; 10734 case AArch64_ST1Fourv8h_POST: 10735 if (MCInst_getNumOperands(MI) == 3 && 10736 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10737 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10738 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10739 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10740 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10741 // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 10742 AsmString = "st1 $\xFF\x02\x11, [$\x01], #64"; 10743 break; 10744 } 10745 return NULL; 10746 case AArch64_ST1Onev16b_POST: 10747 if (MCInst_getNumOperands(MI) == 3 && 10748 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10749 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10750 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10751 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10752 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10753 // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 10754 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #16"; 10755 break; 10756 } 10757 return NULL; 10758 case AArch64_ST1Onev1d_POST: 10759 if (MCInst_getNumOperands(MI) == 3 && 10760 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10761 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10762 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10763 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10764 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10765 // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 10766 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #8"; 10767 break; 10768 } 10769 return NULL; 10770 case AArch64_ST1Onev2d_POST: 10771 if (MCInst_getNumOperands(MI) == 3 && 10772 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10773 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10774 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10775 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10776 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10777 // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 10778 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #16"; 10779 break; 10780 } 10781 return NULL; 10782 case AArch64_ST1Onev2s_POST: 10783 if (MCInst_getNumOperands(MI) == 3 && 10784 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10785 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10786 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10787 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10788 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10789 // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 10790 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #8"; 10791 break; 10792 } 10793 return NULL; 10794 case AArch64_ST1Onev4h_POST: 10795 if (MCInst_getNumOperands(MI) == 3 && 10796 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10797 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10798 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10799 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10800 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10801 // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 10802 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #8"; 10803 break; 10804 } 10805 return NULL; 10806 case AArch64_ST1Onev4s_POST: 10807 if (MCInst_getNumOperands(MI) == 3 && 10808 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10809 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10810 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10811 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10812 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10813 // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 10814 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #16"; 10815 break; 10816 } 10817 return NULL; 10818 case AArch64_ST1Onev8b_POST: 10819 if (MCInst_getNumOperands(MI) == 3 && 10820 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10821 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10822 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10823 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10824 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10825 // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 10826 AsmString = "st1 $\xFF\x02\x10, [$\x01], #8"; 10827 break; 10828 } 10829 return NULL; 10830 case AArch64_ST1Onev8h_POST: 10831 if (MCInst_getNumOperands(MI) == 3 && 10832 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10833 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10834 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10835 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10836 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10837 // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 10838 AsmString = "st1 $\xFF\x02\x11, [$\x01], #16"; 10839 break; 10840 } 10841 return NULL; 10842 case AArch64_ST1Threev16b_POST: 10843 if (MCInst_getNumOperands(MI) == 3 && 10844 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10845 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10846 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10847 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10848 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10849 // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 10850 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #48"; 10851 break; 10852 } 10853 return NULL; 10854 case AArch64_ST1Threev1d_POST: 10855 if (MCInst_getNumOperands(MI) == 3 && 10856 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10857 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10858 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10859 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10860 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10861 // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 10862 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #24"; 10863 break; 10864 } 10865 return NULL; 10866 case AArch64_ST1Threev2d_POST: 10867 if (MCInst_getNumOperands(MI) == 3 && 10868 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10869 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10870 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10871 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10872 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10873 // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 10874 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #48"; 10875 break; 10876 } 10877 return NULL; 10878 case AArch64_ST1Threev2s_POST: 10879 if (MCInst_getNumOperands(MI) == 3 && 10880 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10881 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10882 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10883 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10884 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10885 // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 10886 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #24"; 10887 break; 10888 } 10889 return NULL; 10890 case AArch64_ST1Threev4h_POST: 10891 if (MCInst_getNumOperands(MI) == 3 && 10892 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10893 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10894 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10895 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10896 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10897 // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 10898 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #24"; 10899 break; 10900 } 10901 return NULL; 10902 case AArch64_ST1Threev4s_POST: 10903 if (MCInst_getNumOperands(MI) == 3 && 10904 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10905 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10906 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10907 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10908 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10909 // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 10910 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #48"; 10911 break; 10912 } 10913 return NULL; 10914 case AArch64_ST1Threev8b_POST: 10915 if (MCInst_getNumOperands(MI) == 3 && 10916 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10917 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10918 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10919 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10920 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10921 // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 10922 AsmString = "st1 $\xFF\x02\x10, [$\x01], #24"; 10923 break; 10924 } 10925 return NULL; 10926 case AArch64_ST1Threev8h_POST: 10927 if (MCInst_getNumOperands(MI) == 3 && 10928 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10929 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10930 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10931 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10932 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10933 // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 10934 AsmString = "st1 $\xFF\x02\x11, [$\x01], #48"; 10935 break; 10936 } 10937 return NULL; 10938 case AArch64_ST1Twov16b_POST: 10939 if (MCInst_getNumOperands(MI) == 3 && 10940 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10941 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10942 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10943 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 10944 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10945 // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 10946 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #32"; 10947 break; 10948 } 10949 return NULL; 10950 case AArch64_ST1Twov1d_POST: 10951 if (MCInst_getNumOperands(MI) == 3 && 10952 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10953 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10954 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10955 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10956 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10957 // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 10958 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #16"; 10959 break; 10960 } 10961 return NULL; 10962 case AArch64_ST1Twov2d_POST: 10963 if (MCInst_getNumOperands(MI) == 3 && 10964 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10965 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10966 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10967 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 10968 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10969 // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 10970 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #32"; 10971 break; 10972 } 10973 return NULL; 10974 case AArch64_ST1Twov2s_POST: 10975 if (MCInst_getNumOperands(MI) == 3 && 10976 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10977 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10978 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10979 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10980 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10981 // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 10982 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #16"; 10983 break; 10984 } 10985 return NULL; 10986 case AArch64_ST1Twov4h_POST: 10987 if (MCInst_getNumOperands(MI) == 3 && 10988 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10989 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10990 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10991 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10992 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10993 // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 10994 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #16"; 10995 break; 10996 } 10997 return NULL; 10998 case AArch64_ST1Twov4s_POST: 10999 if (MCInst_getNumOperands(MI) == 3 && 11000 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11001 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11002 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11003 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11004 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11005 // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 11006 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #32"; 11007 break; 11008 } 11009 return NULL; 11010 case AArch64_ST1Twov8b_POST: 11011 if (MCInst_getNumOperands(MI) == 3 && 11012 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11013 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11014 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11015 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11016 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11017 // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 11018 AsmString = "st1 $\xFF\x02\x10, [$\x01], #16"; 11019 break; 11020 } 11021 return NULL; 11022 case AArch64_ST1Twov8h_POST: 11023 if (MCInst_getNumOperands(MI) == 3 && 11024 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11025 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11026 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11027 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11028 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11029 // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 11030 AsmString = "st1 $\xFF\x02\x11, [$\x01], #32"; 11031 break; 11032 } 11033 return NULL; 11034 case AArch64_ST1i16_POST: 11035 if (MCInst_getNumOperands(MI) == 4 && 11036 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11037 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11038 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11039 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11040 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11041 // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) 11042 AsmString = "st1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; 11043 break; 11044 } 11045 return NULL; 11046 case AArch64_ST1i32_POST: 11047 if (MCInst_getNumOperands(MI) == 4 && 11048 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11049 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11050 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11051 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11052 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11053 // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) 11054 AsmString = "st1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; 11055 break; 11056 } 11057 return NULL; 11058 case AArch64_ST1i64_POST: 11059 if (MCInst_getNumOperands(MI) == 4 && 11060 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11061 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11062 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11063 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11064 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11065 // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) 11066 AsmString = "st1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; 11067 break; 11068 } 11069 return NULL; 11070 case AArch64_ST1i8_POST: 11071 if (MCInst_getNumOperands(MI) == 4 && 11072 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11073 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11074 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11075 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11076 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11077 // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) 11078 AsmString = "st1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; 11079 break; 11080 } 11081 return NULL; 11082 case AArch64_ST2Twov16b_POST: 11083 if (MCInst_getNumOperands(MI) == 3 && 11084 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11085 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11086 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11087 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11088 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11089 // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 11090 AsmString = "st2 $\xFF\x02\x0A, [$\x01], #32"; 11091 break; 11092 } 11093 return NULL; 11094 case AArch64_ST2Twov2d_POST: 11095 if (MCInst_getNumOperands(MI) == 3 && 11096 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11097 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11098 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11099 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11100 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11101 // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 11102 AsmString = "st2 $\xFF\x02\x0C, [$\x01], #32"; 11103 break; 11104 } 11105 return NULL; 11106 case AArch64_ST2Twov2s_POST: 11107 if (MCInst_getNumOperands(MI) == 3 && 11108 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11109 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11110 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11111 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11112 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11113 // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 11114 AsmString = "st2 $\xFF\x02\x0D, [$\x01], #16"; 11115 break; 11116 } 11117 return NULL; 11118 case AArch64_ST2Twov4h_POST: 11119 if (MCInst_getNumOperands(MI) == 3 && 11120 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11121 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11122 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11123 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11124 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11125 // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 11126 AsmString = "st2 $\xFF\x02\x0E, [$\x01], #16"; 11127 break; 11128 } 11129 return NULL; 11130 case AArch64_ST2Twov4s_POST: 11131 if (MCInst_getNumOperands(MI) == 3 && 11132 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11133 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11134 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11135 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11136 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11137 // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 11138 AsmString = "st2 $\xFF\x02\x0F, [$\x01], #32"; 11139 break; 11140 } 11141 return NULL; 11142 case AArch64_ST2Twov8b_POST: 11143 if (MCInst_getNumOperands(MI) == 3 && 11144 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11145 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11146 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11147 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11148 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11149 // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 11150 AsmString = "st2 $\xFF\x02\x10, [$\x01], #16"; 11151 break; 11152 } 11153 return NULL; 11154 case AArch64_ST2Twov8h_POST: 11155 if (MCInst_getNumOperands(MI) == 3 && 11156 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11157 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11158 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11159 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11160 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11161 // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 11162 AsmString = "st2 $\xFF\x02\x11, [$\x01], #32"; 11163 break; 11164 } 11165 return NULL; 11166 case AArch64_ST2i16_POST: 11167 if (MCInst_getNumOperands(MI) == 4 && 11168 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11169 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11170 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11171 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11172 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11173 // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) 11174 AsmString = "st2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; 11175 break; 11176 } 11177 return NULL; 11178 case AArch64_ST2i32_POST: 11179 if (MCInst_getNumOperands(MI) == 4 && 11180 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11181 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11183 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11184 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11185 // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) 11186 AsmString = "st2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; 11187 break; 11188 } 11189 return NULL; 11190 case AArch64_ST2i64_POST: 11191 if (MCInst_getNumOperands(MI) == 4 && 11192 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11193 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11195 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11196 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11197 // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) 11198 AsmString = "st2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; 11199 break; 11200 } 11201 return NULL; 11202 case AArch64_ST2i8_POST: 11203 if (MCInst_getNumOperands(MI) == 4 && 11204 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11205 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11206 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11207 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11208 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11209 // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) 11210 AsmString = "st2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; 11211 break; 11212 } 11213 return NULL; 11214 case AArch64_ST3Threev16b_POST: 11215 if (MCInst_getNumOperands(MI) == 3 && 11216 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11217 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11218 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11219 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11220 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11221 // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 11222 AsmString = "st3 $\xFF\x02\x0A, [$\x01], #48"; 11223 break; 11224 } 11225 return NULL; 11226 case AArch64_ST3Threev2d_POST: 11227 if (MCInst_getNumOperands(MI) == 3 && 11228 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11229 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11230 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11231 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11232 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11233 // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 11234 AsmString = "st3 $\xFF\x02\x0C, [$\x01], #48"; 11235 break; 11236 } 11237 return NULL; 11238 case AArch64_ST3Threev2s_POST: 11239 if (MCInst_getNumOperands(MI) == 3 && 11240 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11241 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11242 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11243 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11244 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11245 // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 11246 AsmString = "st3 $\xFF\x02\x0D, [$\x01], #24"; 11247 break; 11248 } 11249 return NULL; 11250 case AArch64_ST3Threev4h_POST: 11251 if (MCInst_getNumOperands(MI) == 3 && 11252 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11253 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11254 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11255 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11256 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11257 // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 11258 AsmString = "st3 $\xFF\x02\x0E, [$\x01], #24"; 11259 break; 11260 } 11261 return NULL; 11262 case AArch64_ST3Threev4s_POST: 11263 if (MCInst_getNumOperands(MI) == 3 && 11264 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11265 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11266 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11267 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11268 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11269 // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 11270 AsmString = "st3 $\xFF\x02\x0F, [$\x01], #48"; 11271 break; 11272 } 11273 return NULL; 11274 case AArch64_ST3Threev8b_POST: 11275 if (MCInst_getNumOperands(MI) == 3 && 11276 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11277 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11278 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11279 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11280 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11281 // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 11282 AsmString = "st3 $\xFF\x02\x10, [$\x01], #24"; 11283 break; 11284 } 11285 return NULL; 11286 case AArch64_ST3Threev8h_POST: 11287 if (MCInst_getNumOperands(MI) == 3 && 11288 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11289 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11290 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11291 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11292 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11293 // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 11294 AsmString = "st3 $\xFF\x02\x11, [$\x01], #48"; 11295 break; 11296 } 11297 return NULL; 11298 case AArch64_ST3i16_POST: 11299 if (MCInst_getNumOperands(MI) == 4 && 11300 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11301 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11302 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11303 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11304 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11305 // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) 11306 AsmString = "st3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; 11307 break; 11308 } 11309 return NULL; 11310 case AArch64_ST3i32_POST: 11311 if (MCInst_getNumOperands(MI) == 4 && 11312 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11313 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11314 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11315 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11316 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11317 // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) 11318 AsmString = "st3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; 11319 break; 11320 } 11321 return NULL; 11322 case AArch64_ST3i64_POST: 11323 if (MCInst_getNumOperands(MI) == 4 && 11324 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11325 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11326 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11327 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11328 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11329 // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) 11330 AsmString = "st3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; 11331 break; 11332 } 11333 return NULL; 11334 case AArch64_ST3i8_POST: 11335 if (MCInst_getNumOperands(MI) == 4 && 11336 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11337 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11338 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11339 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11340 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11341 // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) 11342 AsmString = "st3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; 11343 break; 11344 } 11345 return NULL; 11346 case AArch64_ST4Fourv16b_POST: 11347 if (MCInst_getNumOperands(MI) == 3 && 11348 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11349 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11350 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11351 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11352 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11353 // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 11354 AsmString = "st4 $\xFF\x02\x0A, [$\x01], #64"; 11355 break; 11356 } 11357 return NULL; 11358 case AArch64_ST4Fourv2d_POST: 11359 if (MCInst_getNumOperands(MI) == 3 && 11360 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11361 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11362 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11363 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11364 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11365 // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 11366 AsmString = "st4 $\xFF\x02\x0C, [$\x01], #64"; 11367 break; 11368 } 11369 return NULL; 11370 case AArch64_ST4Fourv2s_POST: 11371 if (MCInst_getNumOperands(MI) == 3 && 11372 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11373 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11374 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11375 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11376 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11377 // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 11378 AsmString = "st4 $\xFF\x02\x0D, [$\x01], #32"; 11379 break; 11380 } 11381 return NULL; 11382 case AArch64_ST4Fourv4h_POST: 11383 if (MCInst_getNumOperands(MI) == 3 && 11384 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11385 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11386 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11387 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11388 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11389 // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 11390 AsmString = "st4 $\xFF\x02\x0E, [$\x01], #32"; 11391 break; 11392 } 11393 return NULL; 11394 case AArch64_ST4Fourv4s_POST: 11395 if (MCInst_getNumOperands(MI) == 3 && 11396 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11397 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11398 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11399 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11400 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11401 // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 11402 AsmString = "st4 $\xFF\x02\x0F, [$\x01], #64"; 11403 break; 11404 } 11405 return NULL; 11406 case AArch64_ST4Fourv8b_POST: 11407 if (MCInst_getNumOperands(MI) == 3 && 11408 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11409 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11410 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11411 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11412 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11413 // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 11414 AsmString = "st4 $\xFF\x02\x10, [$\x01], #32"; 11415 break; 11416 } 11417 return NULL; 11418 case AArch64_ST4Fourv8h_POST: 11419 if (MCInst_getNumOperands(MI) == 3 && 11420 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11421 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11422 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11423 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11424 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11425 // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 11426 AsmString = "st4 $\xFF\x02\x11, [$\x01], #64"; 11427 break; 11428 } 11429 return NULL; 11430 case AArch64_ST4i16_POST: 11431 if (MCInst_getNumOperands(MI) == 4 && 11432 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11433 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11434 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11435 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11436 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11437 // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) 11438 AsmString = "st4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; 11439 break; 11440 } 11441 return NULL; 11442 case AArch64_ST4i32_POST: 11443 if (MCInst_getNumOperands(MI) == 4 && 11444 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11445 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11446 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11447 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11448 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11449 // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) 11450 AsmString = "st4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; 11451 break; 11452 } 11453 return NULL; 11454 case AArch64_ST4i64_POST: 11455 if (MCInst_getNumOperands(MI) == 4 && 11456 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11457 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11458 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11459 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11460 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11461 // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) 11462 AsmString = "st4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; 11463 break; 11464 } 11465 return NULL; 11466 case AArch64_ST4i8_POST: 11467 if (MCInst_getNumOperands(MI) == 4 && 11468 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11469 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11470 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11471 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11472 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11473 // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) 11474 AsmString = "st4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; 11475 break; 11476 } 11477 return NULL; 11478 case AArch64_STNPDi: 11479 if (MCInst_getNumOperands(MI) == 4 && 11480 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11481 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11482 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11483 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 11484 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11485 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11486 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11487 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11488 // (STNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 11489 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11490 break; 11491 } 11492 return NULL; 11493 case AArch64_STNPQi: 11494 if (MCInst_getNumOperands(MI) == 4 && 11495 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11496 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11497 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11498 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11499 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11500 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11501 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11502 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11503 // (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 11504 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11505 break; 11506 } 11507 return NULL; 11508 case AArch64_STNPSi: 11509 if (MCInst_getNumOperands(MI) == 4 && 11510 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11511 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11512 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11513 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 11514 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11515 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11516 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11517 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11518 // (STNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 11519 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11520 break; 11521 } 11522 return NULL; 11523 case AArch64_STNPWi: 11524 if (MCInst_getNumOperands(MI) == 4 && 11525 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11526 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11527 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11528 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 11529 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11530 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11531 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11532 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11533 // (STNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 11534 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11535 break; 11536 } 11537 return NULL; 11538 case AArch64_STNPXi: 11539 if (MCInst_getNumOperands(MI) == 4 && 11540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11541 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11542 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11543 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 11544 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11545 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11546 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11547 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11548 // (STNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 11549 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11550 break; 11551 } 11552 return NULL; 11553 case AArch64_STPDi: 11554 if (MCInst_getNumOperands(MI) == 4 && 11555 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11556 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11557 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11558 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 11559 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11560 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11561 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11562 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11563 // (STPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 11564 AsmString = "stp $\x01, $\x02, [$\x03]"; 11565 break; 11566 } 11567 return NULL; 11568 case AArch64_STPQi: 11569 if (MCInst_getNumOperands(MI) == 4 && 11570 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11571 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11572 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11573 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11574 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11575 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11576 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11577 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11578 // (STPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 11579 AsmString = "stp $\x01, $\x02, [$\x03]"; 11580 break; 11581 } 11582 return NULL; 11583 case AArch64_STPSi: 11584 if (MCInst_getNumOperands(MI) == 4 && 11585 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11586 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11587 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11588 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 11589 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11590 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11591 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11592 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11593 // (STPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 11594 AsmString = "stp $\x01, $\x02, [$\x03]"; 11595 break; 11596 } 11597 return NULL; 11598 case AArch64_STPWi: 11599 if (MCInst_getNumOperands(MI) == 4 && 11600 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11601 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11602 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11603 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 11604 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11605 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11606 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11607 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11608 // (STPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 11609 AsmString = "stp $\x01, $\x02, [$\x03]"; 11610 break; 11611 } 11612 return NULL; 11613 case AArch64_STPXi: 11614 if (MCInst_getNumOperands(MI) == 4 && 11615 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11616 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11617 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11618 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 11619 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11620 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11621 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11622 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11623 // (STPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 11624 AsmString = "stp $\x01, $\x02, [$\x03]"; 11625 break; 11626 } 11627 return NULL; 11628 case AArch64_STRBBroX: 11629 if (MCInst_getNumOperands(MI) == 5 && 11630 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11631 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11632 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11633 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11634 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11635 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11636 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11637 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11638 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11639 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11640 // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11641 AsmString = "strb $\x01, [$\x02, $\x03]"; 11642 break; 11643 } 11644 return NULL; 11645 case AArch64_STRBBui: 11646 if (MCInst_getNumOperands(MI) == 3 && 11647 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11648 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11649 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11650 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11651 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11652 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11653 // (STRBBui GPR32:$Rt, GPR64sp:$Rn, 0) 11654 AsmString = "strb $\x01, [$\x02]"; 11655 break; 11656 } 11657 return NULL; 11658 case AArch64_STRBroX: 11659 if (MCInst_getNumOperands(MI) == 5 && 11660 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11661 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11662 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11663 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11664 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11665 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11666 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11667 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11668 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11669 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11670 // (STRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11671 AsmString = "str $\x01, [$\x02, $\x03]"; 11672 break; 11673 } 11674 return NULL; 11675 case AArch64_STRBui: 11676 if (MCInst_getNumOperands(MI) == 3 && 11677 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11678 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11679 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11680 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11681 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11682 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11683 // (STRBui FPR8:$Rt, GPR64sp:$Rn, 0) 11684 AsmString = "str $\x01, [$\x02]"; 11685 break; 11686 } 11687 return NULL; 11688 case AArch64_STRDroX: 11689 if (MCInst_getNumOperands(MI) == 5 && 11690 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11691 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11692 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11693 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11694 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11695 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11696 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11697 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11698 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11699 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11700 // (STRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11701 AsmString = "str $\x01, [$\x02, $\x03]"; 11702 break; 11703 } 11704 return NULL; 11705 case AArch64_STRDui: 11706 if (MCInst_getNumOperands(MI) == 3 && 11707 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11708 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11709 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11710 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11711 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11712 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11713 // (STRDui FPR64:$Rt, GPR64sp:$Rn, 0) 11714 AsmString = "str $\x01, [$\x02]"; 11715 break; 11716 } 11717 return NULL; 11718 case AArch64_STRHHroX: 11719 if (MCInst_getNumOperands(MI) == 5 && 11720 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11721 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11722 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11723 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11724 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11725 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11726 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11727 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11728 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11729 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11730 // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11731 AsmString = "strh $\x01, [$\x02, $\x03]"; 11732 break; 11733 } 11734 return NULL; 11735 case AArch64_STRHHui: 11736 if (MCInst_getNumOperands(MI) == 3 && 11737 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11738 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11739 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11740 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11741 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11742 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11743 // (STRHHui GPR32:$Rt, GPR64sp:$Rn, 0) 11744 AsmString = "strh $\x01, [$\x02]"; 11745 break; 11746 } 11747 return NULL; 11748 case AArch64_STRHroX: 11749 if (MCInst_getNumOperands(MI) == 5 && 11750 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11751 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 11752 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11753 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11754 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11755 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11756 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11757 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11758 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11759 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11760 // (STRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11761 AsmString = "str $\x01, [$\x02, $\x03]"; 11762 break; 11763 } 11764 return NULL; 11765 case AArch64_STRHui: 11766 if (MCInst_getNumOperands(MI) == 3 && 11767 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11768 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 11769 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11770 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11771 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11772 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11773 // (STRHui FPR16:$Rt, GPR64sp:$Rn, 0) 11774 AsmString = "str $\x01, [$\x02]"; 11775 break; 11776 } 11777 return NULL; 11778 case AArch64_STRQroX: 11779 if (MCInst_getNumOperands(MI) == 5 && 11780 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11781 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11782 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11783 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11784 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11785 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11786 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11787 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11788 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11789 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11790 // (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11791 AsmString = "str $\x01, [$\x02, $\x03]"; 11792 break; 11793 } 11794 return NULL; 11795 case AArch64_STRQui: 11796 if (MCInst_getNumOperands(MI) == 3 && 11797 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11798 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11799 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11800 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11801 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11802 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11803 // (STRQui FPR128:$Rt, GPR64sp:$Rn, 0) 11804 AsmString = "str $\x01, [$\x02]"; 11805 break; 11806 } 11807 return NULL; 11808 case AArch64_STRSroX: 11809 if (MCInst_getNumOperands(MI) == 5 && 11810 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11811 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11812 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11813 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11814 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11815 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11816 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11817 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11818 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11819 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11820 // (STRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11821 AsmString = "str $\x01, [$\x02, $\x03]"; 11822 break; 11823 } 11824 return NULL; 11825 case AArch64_STRSui: 11826 if (MCInst_getNumOperands(MI) == 3 && 11827 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11828 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11829 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11830 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11831 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11832 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11833 // (STRSui FPR32:$Rt, GPR64sp:$Rn, 0) 11834 AsmString = "str $\x01, [$\x02]"; 11835 break; 11836 } 11837 return NULL; 11838 case AArch64_STRWroX: 11839 if (MCInst_getNumOperands(MI) == 5 && 11840 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11841 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11842 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11843 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11844 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11845 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11846 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11847 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11848 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11849 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11850 // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11851 AsmString = "str $\x01, [$\x02, $\x03]"; 11852 break; 11853 } 11854 return NULL; 11855 case AArch64_STRWui: 11856 if (MCInst_getNumOperands(MI) == 3 && 11857 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11858 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11859 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11860 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11861 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11862 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11863 // (STRWui GPR32:$Rt, GPR64sp:$Rn, 0) 11864 AsmString = "str $\x01, [$\x02]"; 11865 break; 11866 } 11867 return NULL; 11868 case AArch64_STRXroX: 11869 if (MCInst_getNumOperands(MI) == 5 && 11870 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11871 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11872 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11873 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11874 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11875 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11876 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11877 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11878 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11879 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11880 // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11881 AsmString = "str $\x01, [$\x02, $\x03]"; 11882 break; 11883 } 11884 return NULL; 11885 case AArch64_STRXui: 11886 if (MCInst_getNumOperands(MI) == 3 && 11887 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11888 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11889 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11890 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11891 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11892 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11893 // (STRXui GPR64:$Rt, GPR64sp:$Rn, 0) 11894 AsmString = "str $\x01, [$\x02]"; 11895 break; 11896 } 11897 return NULL; 11898 case AArch64_STTRBi: 11899 if (MCInst_getNumOperands(MI) == 3 && 11900 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11901 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11902 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11903 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11904 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11905 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11906 // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) 11907 AsmString = "sttrb $\x01, [$\x02]"; 11908 break; 11909 } 11910 return NULL; 11911 case AArch64_STTRHi: 11912 if (MCInst_getNumOperands(MI) == 3 && 11913 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11914 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11915 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11916 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11917 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11918 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11919 // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) 11920 AsmString = "sttrh $\x01, [$\x02]"; 11921 break; 11922 } 11923 return NULL; 11924 case AArch64_STTRWi: 11925 if (MCInst_getNumOperands(MI) == 3 && 11926 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11927 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11928 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11929 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11930 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11931 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11932 // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) 11933 AsmString = "sttr $\x01, [$\x02]"; 11934 break; 11935 } 11936 return NULL; 11937 case AArch64_STTRXi: 11938 if (MCInst_getNumOperands(MI) == 3 && 11939 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11940 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11941 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11942 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11943 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11944 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11945 // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) 11946 AsmString = "sttr $\x01, [$\x02]"; 11947 break; 11948 } 11949 return NULL; 11950 case AArch64_STURBBi: 11951 if (MCInst_getNumOperands(MI) == 3 && 11952 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11953 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11954 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11955 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11956 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11957 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11958 // (STURBBi GPR32:$Rt, GPR64sp:$Rn, 0) 11959 AsmString = "sturb $\x01, [$\x02]"; 11960 break; 11961 } 11962 return NULL; 11963 case AArch64_STURBi: 11964 if (MCInst_getNumOperands(MI) == 3 && 11965 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11966 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11967 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11968 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11969 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11970 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11971 // (STURBi FPR8:$Rt, GPR64sp:$Rn, 0) 11972 AsmString = "stur $\x01, [$\x02]"; 11973 break; 11974 } 11975 return NULL; 11976 case AArch64_STURDi: 11977 if (MCInst_getNumOperands(MI) == 3 && 11978 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11979 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11980 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11981 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11982 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11983 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11984 // (STURDi FPR64:$Rt, GPR64sp:$Rn, 0) 11985 AsmString = "stur $\x01, [$\x02]"; 11986 break; 11987 } 11988 return NULL; 11989 case AArch64_STURHHi: 11990 if (MCInst_getNumOperands(MI) == 3 && 11991 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11992 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11993 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11994 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11995 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11996 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11997 // (STURHHi GPR32:$Rt, GPR64sp:$Rn, 0) 11998 AsmString = "sturh $\x01, [$\x02]"; 11999 break; 12000 } 12001 return NULL; 12002 case AArch64_STURHi: 12003 if (MCInst_getNumOperands(MI) == 3 && 12004 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12005 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 12006 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12007 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12008 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12009 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12010 // (STURHi FPR16:$Rt, GPR64sp:$Rn, 0) 12011 AsmString = "stur $\x01, [$\x02]"; 12012 break; 12013 } 12014 return NULL; 12015 case AArch64_STURQi: 12016 if (MCInst_getNumOperands(MI) == 3 && 12017 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12018 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 12019 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12020 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12021 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12022 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12023 // (STURQi FPR128:$Rt, GPR64sp:$Rn, 0) 12024 AsmString = "stur $\x01, [$\x02]"; 12025 break; 12026 } 12027 return NULL; 12028 case AArch64_STURSi: 12029 if (MCInst_getNumOperands(MI) == 3 && 12030 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12031 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 12032 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12033 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12034 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12035 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12036 // (STURSi FPR32:$Rt, GPR64sp:$Rn, 0) 12037 AsmString = "stur $\x01, [$\x02]"; 12038 break; 12039 } 12040 return NULL; 12041 case AArch64_STURWi: 12042 if (MCInst_getNumOperands(MI) == 3 && 12043 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12044 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12045 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12046 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12047 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12048 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12049 // (STURWi GPR32:$Rt, GPR64sp:$Rn, 0) 12050 AsmString = "stur $\x01, [$\x02]"; 12051 break; 12052 } 12053 return NULL; 12054 case AArch64_STURXi: 12055 if (MCInst_getNumOperands(MI) == 3 && 12056 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12057 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12058 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12059 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12060 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12061 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12062 // (STURXi GPR64:$Rt, GPR64sp:$Rn, 0) 12063 AsmString = "stur $\x01, [$\x02]"; 12064 break; 12065 } 12066 return NULL; 12067 case AArch64_SUBSWri: 12068 if (MCInst_getNumOperands(MI) == 4 && 12069 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12070 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12071 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { 12072 // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) 12073 AsmString = "cmp $\x02, $\xFF\x03\x01"; 12074 break; 12075 } 12076 return NULL; 12077 case AArch64_SUBSWrs: 12078 if (MCInst_getNumOperands(MI) == 4 && 12079 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12080 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12081 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12082 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12083 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12084 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12085 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12086 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 12087 AsmString = "cmp $\x02, $\x03"; 12088 break; 12089 } 12090 if (MCInst_getNumOperands(MI) == 4 && 12091 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12092 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12093 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12094 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12095 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12096 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) 12097 AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; 12098 break; 12099 } 12100 if (MCInst_getNumOperands(MI) == 4 && 12101 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12102 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12103 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12104 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12105 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12106 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12107 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12108 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) 12109 AsmString = "negs $\x01, $\x03"; 12110 break; 12111 } 12112 if (MCInst_getNumOperands(MI) == 4 && 12113 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12114 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12115 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12116 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12117 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12118 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) 12119 AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; 12120 break; 12121 } 12122 if (MCInst_getNumOperands(MI) == 4 && 12123 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12124 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12125 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12126 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12127 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12128 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12129 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12130 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12131 // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 12132 AsmString = "subs $\x01, $\x02, $\x03"; 12133 break; 12134 } 12135 return NULL; 12136 case AArch64_SUBSWrx: 12137 if (MCInst_getNumOperands(MI) == 4 && 12138 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12139 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12140 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12141 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12142 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12143 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12144 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12145 // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) 12146 AsmString = "cmp $\x02, $\x03"; 12147 break; 12148 } 12149 if (MCInst_getNumOperands(MI) == 4 && 12150 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12151 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12152 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 12153 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12154 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12155 // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) 12156 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12157 break; 12158 } 12159 if (MCInst_getNumOperands(MI) == 4 && 12160 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12161 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12162 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12163 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12164 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12165 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12166 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12167 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12168 // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 12169 AsmString = "subs $\x01, $\x02, $\x03"; 12170 break; 12171 } 12172 return NULL; 12173 case AArch64_SUBSXri: 12174 if (MCInst_getNumOperands(MI) == 4 && 12175 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12176 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12177 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { 12178 // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) 12179 AsmString = "cmp $\x02, $\xFF\x03\x01"; 12180 break; 12181 } 12182 return NULL; 12183 case AArch64_SUBSXrs: 12184 if (MCInst_getNumOperands(MI) == 4 && 12185 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12186 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12187 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12188 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12189 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12190 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12191 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12192 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 12193 AsmString = "cmp $\x02, $\x03"; 12194 break; 12195 } 12196 if (MCInst_getNumOperands(MI) == 4 && 12197 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12198 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12199 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12200 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12201 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12202 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) 12203 AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; 12204 break; 12205 } 12206 if (MCInst_getNumOperands(MI) == 4 && 12207 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12208 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12209 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12210 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12211 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12212 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12213 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12214 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) 12215 AsmString = "negs $\x01, $\x03"; 12216 break; 12217 } 12218 if (MCInst_getNumOperands(MI) == 4 && 12219 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12220 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12221 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12222 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12223 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12224 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) 12225 AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; 12226 break; 12227 } 12228 if (MCInst_getNumOperands(MI) == 4 && 12229 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12230 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12231 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12232 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12233 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12234 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12235 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12236 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12237 // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 12238 AsmString = "subs $\x01, $\x02, $\x03"; 12239 break; 12240 } 12241 return NULL; 12242 case AArch64_SUBSXrx: 12243 if (MCInst_getNumOperands(MI) == 4 && 12244 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12245 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12246 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12247 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12248 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12249 // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) 12250 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12251 break; 12252 } 12253 return NULL; 12254 case AArch64_SUBSXrx64: 12255 if (MCInst_getNumOperands(MI) == 4 && 12256 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12257 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12258 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12259 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12260 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12261 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12262 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12263 // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) 12264 AsmString = "cmp $\x02, $\x03"; 12265 break; 12266 } 12267 if (MCInst_getNumOperands(MI) == 4 && 12268 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12269 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12270 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12271 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12272 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12273 // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) 12274 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12275 break; 12276 } 12277 if (MCInst_getNumOperands(MI) == 4 && 12278 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12279 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12280 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12281 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12282 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12283 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12284 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12285 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12286 // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 12287 AsmString = "subs $\x01, $\x02, $\x03"; 12288 break; 12289 } 12290 return NULL; 12291 case AArch64_SUBWrs: 12292 if (MCInst_getNumOperands(MI) == 4 && 12293 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12294 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12295 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12296 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12297 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12298 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12299 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12300 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) 12301 AsmString = "neg $\x01, $\x03"; 12302 break; 12303 } 12304 if (MCInst_getNumOperands(MI) == 4 && 12305 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12306 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12307 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12308 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12309 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12310 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) 12311 AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; 12312 break; 12313 } 12314 if (MCInst_getNumOperands(MI) == 4 && 12315 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12316 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12317 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12318 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12319 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12320 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12321 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12322 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12323 // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 12324 AsmString = "sub $\x01, $\x02, $\x03"; 12325 break; 12326 } 12327 return NULL; 12328 case AArch64_SUBWrx: 12329 if (MCInst_getNumOperands(MI) == 4 && 12330 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12331 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 12332 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12333 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 12334 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12335 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12336 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12337 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12338 // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) 12339 AsmString = "sub $\x01, $\x02, $\x03"; 12340 break; 12341 } 12342 if (MCInst_getNumOperands(MI) == 4 && 12343 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12344 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 12345 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12346 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12347 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12348 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12349 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12350 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12351 // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 12352 AsmString = "sub $\x01, $\x02, $\x03"; 12353 break; 12354 } 12355 return NULL; 12356 case AArch64_SUBXrs: 12357 if (MCInst_getNumOperands(MI) == 4 && 12358 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12359 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12360 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12361 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12362 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12363 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12364 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12365 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) 12366 AsmString = "neg $\x01, $\x03"; 12367 break; 12368 } 12369 if (MCInst_getNumOperands(MI) == 4 && 12370 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12371 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12372 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12373 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12374 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12375 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) 12376 AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; 12377 break; 12378 } 12379 if (MCInst_getNumOperands(MI) == 4 && 12380 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12381 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12382 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12383 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12384 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12385 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12386 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12387 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12388 // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 12389 AsmString = "sub $\x01, $\x02, $\x03"; 12390 break; 12391 } 12392 return NULL; 12393 case AArch64_SUBXrx64: 12394 if (MCInst_getNumOperands(MI) == 4 && 12395 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12396 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 12397 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12398 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12399 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12400 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12401 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12402 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12403 // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) 12404 AsmString = "sub $\x01, $\x02, $\x03"; 12405 break; 12406 } 12407 if (MCInst_getNumOperands(MI) == 4 && 12408 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12409 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 12410 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12411 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12412 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12413 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12414 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12415 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12416 // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 12417 AsmString = "sub $\x01, $\x02, $\x03"; 12418 break; 12419 } 12420 return NULL; 12421 case AArch64_SYSxt: 12422 if (MCInst_getNumOperands(MI) == 5 && 12423 MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { 12424 // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) 12425 AsmString = "sys $\x01, $\xFF\x02\x17, $\xFF\x03\x17, $\x04"; 12426 break; 12427 } 12428 return NULL; 12429 case AArch64_UBFMWri: 12430 if (MCInst_getNumOperands(MI) == 4 && 12431 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12432 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12433 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12434 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12435 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12436 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 12437 // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) 12438 AsmString = "lsr $\x01, $\x02, $\x03"; 12439 break; 12440 } 12441 if (MCInst_getNumOperands(MI) == 4 && 12442 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12443 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12444 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12445 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12446 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12447 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12448 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12449 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 12450 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) 12451 AsmString = "uxtb $\x01, $\x02"; 12452 break; 12453 } 12454 if (MCInst_getNumOperands(MI) == 4 && 12455 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12456 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12457 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12458 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12459 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12460 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12461 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12462 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 12463 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) 12464 AsmString = "uxth $\x01, $\x02"; 12465 break; 12466 } 12467 return NULL; 12468 case AArch64_UBFMXri: 12469 if (MCInst_getNumOperands(MI) == 4 && 12470 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12471 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12472 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12473 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12474 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12475 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { 12476 // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) 12477 AsmString = "lsr $\x01, $\x02, $\x03"; 12478 break; 12479 } 12480 if (MCInst_getNumOperands(MI) == 4 && 12481 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12482 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12483 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12484 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12485 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12486 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12487 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12488 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 12489 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) 12490 AsmString = "uxtb $\x01, $\x02"; 12491 break; 12492 } 12493 if (MCInst_getNumOperands(MI) == 4 && 12494 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12495 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12496 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12497 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12498 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12499 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12500 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12501 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 12502 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) 12503 AsmString = "uxth $\x01, $\x02"; 12504 break; 12505 } 12506 if (MCInst_getNumOperands(MI) == 4 && 12507 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12508 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12509 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12510 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12511 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12512 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12513 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12514 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 12515 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) 12516 AsmString = "uxtw $\x01, $\x02"; 12517 break; 12518 } 12519 return NULL; 12520 case AArch64_UMADDLrrr: 12521 if (MCInst_getNumOperands(MI) == 4 && 12522 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12523 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12524 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12525 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12526 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12527 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12528 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 12529 // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 12530 AsmString = "umull $\x01, $\x02, $\x03"; 12531 break; 12532 } 12533 return NULL; 12534 case AArch64_UMOVvi32: 12535 if (MCInst_getNumOperands(MI) == 3 && 12536 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12537 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12538 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12539 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 12540 // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) 12541 AsmString = "mov $\x01, $\xFF\x02\x06.s$\xFF\x03\x09"; 12542 break; 12543 } 12544 return NULL; 12545 case AArch64_UMOVvi64: 12546 if (MCInst_getNumOperands(MI) == 3 && 12547 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12548 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12549 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12550 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 12551 // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) 12552 AsmString = "mov $\x01, $\xFF\x02\x06.d$\xFF\x03\x09"; 12553 break; 12554 } 12555 return NULL; 12556 case AArch64_UMSUBLrrr: 12557 if (MCInst_getNumOperands(MI) == 4 && 12558 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12559 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12560 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12561 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12562 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12563 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12564 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 12565 // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 12566 AsmString = "umnegl $\x01, $\x02, $\x03"; 12567 break; 12568 } 12569 return NULL; 12570 } 12571 12572 tmp = cs_strdup(AsmString); 12573 AsmMnem = tmp; 12574 for(AsmOps = tmp; *AsmOps; AsmOps++) { 12575 if (*AsmOps == ' ' || *AsmOps == '\t') { 12576 *AsmOps = '\0'; 12577 AsmOps++; 12578 break; 12579 } 12580 } 12581 SStream_concat0(OS, AsmMnem); 12582 if (*AsmOps) { 12583 SStream_concat0(OS, "\t"); 12584 for (c = AsmOps; *c; c++) { 12585 if (*c == '[') { 12586 SStream_concat0(OS, "["); 12587 set_mem_access(MI, true); 12588 } 12589 else if (*c == ']') { 12590 SStream_concat0(OS, "]"); 12591 set_mem_access(MI, false); 12592 } 12593 else if (*c == '$') { 12594 c += 1; 12595 if (*c == (char)0xff) { 12596 c += 1; 12597 OpIdx = *c - 1; 12598 c += 1; 12599 PrintMethodIdx = *c - 1; 12600 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS, MRI); 12601 } else 12602 printOperand(MI, *c - 1, OS); 12603 } else { 12604 SStream_concat(OS, "%c", *c); 12605 } 12606 } 12607 } 12608 return tmp; 12609} 12610 12611#endif // PRINT_ALIAS_INSTR 12612