1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13 #ifdef CAPSTONE_HAS_ARM
14
15 #include <stdio.h>
16 #include <string.h>
17 #include <stdlib.h>
18 #include <capstone/platform.h>
19
20 #include "ARMAddressingModes.h"
21 #include "ARMBaseInfo.h"
22 #include "../../MCFixedLenDisassembler.h"
23 #include "../../MCInst.h"
24 #include "../../MCInstrDesc.h"
25 #include "../../MCRegisterInfo.h"
26 #include "../../LEB128.h"
27 #include "../../MCDisassembler.h"
28 #include "../../cs_priv.h"
29 #include "../../utils.h"
30
31 #include "ARMDisassembler.h"
32
33 //#define GET_REGINFO_ENUM
34 //#include "X86GenRegisterInfo.inc"
35
36 #define GET_SUBTARGETINFO_ENUM
37 #include "ARMGenSubtargetInfo.inc"
38
39 #define GET_INSTRINFO_MC_DESC
40 #include "ARMGenInstrInfo.inc"
41
42 #define GET_INSTRINFO_ENUM
43 #include "ARMGenInstrInfo.inc"
44
ITStatus_push_back(ARM_ITStatus * it,char v)45 static bool ITStatus_push_back(ARM_ITStatus *it, char v)
46 {
47 if (it->size >= sizeof(it->ITStates)) {
48 // TODO: consider warning user.
49 it->size = 0;
50 }
51 it->ITStates[it->size] = v;
52 it->size++;
53
54 return true;
55 }
56
57 // Returns true if the current instruction is in an IT block
ITStatus_instrInITBlock(ARM_ITStatus * it)58 static bool ITStatus_instrInITBlock(ARM_ITStatus *it)
59 {
60 //return !ITStates.empty();
61 return (it->size > 0);
62 }
63
64 // Returns true if current instruction is the last instruction in an IT block
ITStatus_instrLastInITBlock(ARM_ITStatus * it)65 static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it)
66 {
67 return (it->size == 1);
68 }
69
70 // Handles the condition code status of instructions in IT blocks
71
72 // Returns the condition code for instruction in IT block
ITStatus_getITCC(ARM_ITStatus * it)73 static unsigned ITStatus_getITCC(ARM_ITStatus *it)
74 {
75 unsigned CC = ARMCC_AL;
76 if (ITStatus_instrInITBlock(it))
77 //CC = ITStates.back();
78 CC = it->ITStates[it->size-1];
79 return CC;
80 }
81
82 // Advances the IT block state to the next T or E
ITStatus_advanceITState(ARM_ITStatus * it)83 static void ITStatus_advanceITState(ARM_ITStatus *it)
84 {
85 //ITStates.pop_back();
86 it->size--;
87 }
88
89 // Called when decoding an IT instruction. Sets the IT state for the following
90 // instructions that for the IT block. Firstcond and Mask correspond to the
91 // fields in the IT instruction encoding.
ITStatus_setITState(ARM_ITStatus * it,char Firstcond,char Mask)92 static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask)
93 {
94 // (3 - the number of trailing zeros) is the number of then / else.
95 unsigned CondBit0 = Firstcond & 1;
96 unsigned NumTZ = CountTrailingZeros_32(Mask);
97 unsigned char CCBits = (unsigned char)Firstcond & 0xf;
98 unsigned Pos;
99 //assert(NumTZ <= 3 && "Invalid IT mask!");
100 // push condition codes onto the stack the correct order for the pops
101 for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
102 bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
103 if (T)
104 ITStatus_push_back(it, CCBits);
105 else
106 ITStatus_push_back(it, CCBits ^ 1);
107 }
108 ITStatus_push_back(it, CCBits);
109 }
110
111 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
112
Check(DecodeStatus * Out,DecodeStatus In)113 static bool Check(DecodeStatus *Out, DecodeStatus In)
114 {
115 switch (In) {
116 case MCDisassembler_Success:
117 // Out stays the same.
118 return true;
119 case MCDisassembler_SoftFail:
120 *Out = In;
121 return true;
122 case MCDisassembler_Fail:
123 *Out = In;
124 return false;
125 default: // never reached
126 return false;
127 }
128 }
129
130 // Forward declare these because the autogenerated code will reference them.
131 // Definitions are further down.
132 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst,
135 unsigned RegNo, uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst,
137 unsigned RegNo, uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst,
153 unsigned RegNo, uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
159 unsigned RegNo, uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst,
175 unsigned Insn, uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst,
185 unsigned Insn, uint64_t Adddress, const void *Decoder);
186 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
313 uint64_t Address, const void* Decoder);
314 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
315 uint64_t Address, const void* Decoder);
316 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
317 uint64_t Address, const void* Decoder);
318 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
319 uint64_t Address, const void* Decoder);
320 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
363 uint64_t Address, const void *Decoder);
364
365 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369
370 // Hacky: enable all features for disassembler
ARM_getFeatureBits(unsigned int mode)371 uint64_t ARM_getFeatureBits(unsigned int mode)
372 {
373 uint64_t Bits = (uint64_t)-1; // everything by default
374
375 // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
376 Bits &= (~ARM_FeatureVFPOnlySP);
377
378 // FIXME: no Armv8 support?
379 //Bits -= ARM_HasV7Ops;
380 //Bits &= ~ARM_FeatureMP;
381 if ((mode & CS_MODE_V8) == 0)
382 Bits &= ~ARM_HasV8Ops;
383 //Bits &= ~ARM_HasV6Ops;
384
385 if ((mode & CS_MODE_MCLASS) == 0)
386 Bits &= (~ARM_FeatureMClass);
387
388 // some features are mutually exclusive
389 if (mode & CS_MODE_THUMB) {
390 //Bits &= ~ARM_HasV6Ops;
391 //Bits &= ~ARM_FeatureCRC;
392 //Bits &= ~ARM_HasV5TEOps;
393 //Bits &= ~ARM_HasV4TOps;
394 //Bits &= ~ARM_HasV6T2Ops;
395 //Bits &= ~ARM_FeatureDB;
396 //Bits &= ~ARM_FeatureHWDivARM;
397 //Bits &= ~ARM_FeatureNaClTrap;
398 //Bits &= ~ARM_FeatureMClass;
399 // ArmV8
400 } else { // ARM mode
401 Bits &= ~ARM_ModeThumb;
402 Bits &= ~ARM_FeatureThumb2;
403 }
404
405 return Bits;
406 }
407
408 #include "ARMGenDisassemblerTables.inc"
409
DecodePredicateOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)410 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
411 uint64_t Address, const void *Decoder)
412 {
413 if (Val == 0xF) return MCDisassembler_Fail;
414 // AL predicate is not allowed on Thumb1 branches.
415 if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
416 return MCDisassembler_Fail;
417 MCOperand_CreateImm0(Inst, Val);
418 if (Val == ARMCC_AL) {
419 MCOperand_CreateReg0(Inst, 0);
420 } else
421 MCOperand_CreateReg0(Inst, ARM_CPSR);
422 return MCDisassembler_Success;
423 }
424
425 #define GET_REGINFO_MC_DESC
426 #include "ARMGenRegisterInfo.inc"
ARM_init(MCRegisterInfo * MRI)427 void ARM_init(MCRegisterInfo *MRI)
428 {
429 /*
430 InitMCRegisterInfo(ARMRegDesc, 289,
431 RA, PC,
432 ARMMCRegisterClasses, 100,
433 ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
434 ARMSubRegIdxLists, 57,
435 ARMSubRegIdxRanges, ARMRegEncodingTable);
436 */
437
438 MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
439 0, 0,
440 ARMMCRegisterClasses, 100,
441 0, 0, ARMRegDiffLists, 0,
442 ARMSubRegIdxLists, 57,
443 0);
444 }
445
446 // Post-decoding checks
checkDecodedInstruction(MCInst * MI,uint32_t Insn,DecodeStatus Result)447 static DecodeStatus checkDecodedInstruction(MCInst *MI,
448 uint32_t Insn,
449 DecodeStatus Result)
450 {
451 switch (MCInst_getOpcode(MI)) {
452 case ARM_HVC: {
453 // HVC is undefined if condition = 0xf otherwise upredictable
454 // if condition != 0xe
455 uint32_t Cond = (Insn >> 28) & 0xF;
456 if (Cond == 0xF)
457 return MCDisassembler_Fail;
458 if (Cond != 0xE)
459 return MCDisassembler_SoftFail;
460 return Result;
461 }
462 default:
463 return Result;
464 }
465 }
466
_ARM_getInstruction(cs_struct * ud,MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address)467 static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
468 uint16_t *Size, uint64_t Address)
469 {
470 uint32_t insn, i;
471 DecodeStatus result;
472
473 if (code_len < 4)
474 // not enough data
475 return MCDisassembler_Fail;
476
477 if (MI->flat_insn->detail) {
478 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
479 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
480 MI->flat_insn->detail->arm.operands[i].vector_index = -1;
481 MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
482 }
483 }
484
485 if (MODE_IS_BIG_ENDIAN(ud->mode))
486 insn = (code[3] << 0) |
487 (code[2] << 8) |
488 (code[1] << 16) |
489 ((uint32_t) code[0] << 24);
490 else
491 insn = ((uint32_t) code[3] << 24) |
492 (code[2] << 16) |
493 (code[1] << 8) |
494 (code[0] << 0);
495
496 // Calling the auto-generated decoder function.
497 result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
498 if (result != MCDisassembler_Fail) {
499 result = checkDecodedInstruction(MI, insn, result);
500 if (result != MCDisassembler_Fail)
501 *Size = 4;
502 return result;
503 }
504
505 // VFP and NEON instructions, similarly, are shared between ARM
506 // and Thumb modes.
507 MCInst_clear(MI);
508 result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode);
509 if (result != MCDisassembler_Fail) {
510 *Size = 4;
511 return result;
512 }
513
514 MCInst_clear(MI);
515 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode);
516 if (result != MCDisassembler_Fail) {
517 *Size = 4;
518 return result;
519 }
520
521 MCInst_clear(MI);
522 result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode);
523 if (result != MCDisassembler_Fail) {
524 *Size = 4;
525 // Add a fake predicate operand, because we share these instruction
526 // definitions with Thumb2 where these instructions are predicable.
527 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
528 return MCDisassembler_Fail;
529 return result;
530 }
531
532 MCInst_clear(MI);
533 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode);
534 if (result != MCDisassembler_Fail) {
535 *Size = 4;
536 // Add a fake predicate operand, because we share these instruction
537 // definitions with Thumb2 where these instructions are predicable.
538 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
539 return MCDisassembler_Fail;
540 return result;
541 }
542
543 MCInst_clear(MI);
544 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode);
545 if (result != MCDisassembler_Fail) {
546 *Size = 4;
547 // Add a fake predicate operand, because we share these instruction
548 // definitions with Thumb2 where these instructions are predicable.
549 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
550 return MCDisassembler_Fail;
551 return result;
552 }
553
554 MCInst_clear(MI);
555 result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode);
556 if (result != MCDisassembler_Fail) {
557 *Size = 4;
558 return result;
559 }
560
561 MCInst_clear(MI);
562 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode);
563 if (result != MCDisassembler_Fail) {
564 *Size = 4;
565 return result;
566 }
567
568 MCInst_clear(MI);
569 *Size = 0;
570 return MCDisassembler_Fail;
571 }
572
573 // Thumb1 instructions don't have explicit S bits. Rather, they
574 // implicitly set CPSR. Since it's not represented in the encoding, the
575 // auto-generated decoder won't inject the CPSR operand. We need to fix
576 // that as a post-pass.
AddThumb1SBit(MCInst * MI,bool InITBlock)577 static void AddThumb1SBit(MCInst *MI, bool InITBlock)
578 {
579 const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
580 unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
581 unsigned i;
582
583 for (i = 0; i < NumOps; ++i) {
584 if (i == MCInst_getNumOperands(MI)) break;
585 if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) {
586 if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue;
587 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
588 return;
589 }
590 }
591
592 //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
593 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
594 }
595
596 // Most Thumb instructions don't have explicit predicates in the
597 // encoding, but rather get their predicates from IT context. We need
598 // to fix up the predicate operands using this context information as a
599 // post-pass.
AddThumbPredicate(cs_struct * ud,MCInst * MI)600 static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
601 {
602 DecodeStatus S = MCDisassembler_Success;
603 const MCOperandInfo *OpInfo;
604 unsigned short NumOps;
605 unsigned int i;
606 unsigned CC;
607
608 // A few instructions actually have predicates encoded in them. Don't
609 // try to overwrite it if we're seeing one of those.
610 switch (MCInst_getOpcode(MI)) {
611 case ARM_tBcc:
612 case ARM_t2Bcc:
613 case ARM_tCBZ:
614 case ARM_tCBNZ:
615 case ARM_tCPS:
616 case ARM_t2CPS3p:
617 case ARM_t2CPS2p:
618 case ARM_t2CPS1p:
619 case ARM_tMOVSr:
620 case ARM_tSETEND:
621 // Some instructions (mostly conditional branches) are not
622 // allowed in IT blocks.
623 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
624 S = MCDisassembler_SoftFail;
625 else
626 return MCDisassembler_Success;
627 break;
628 case ARM_tB:
629 case ARM_t2B:
630 case ARM_t2TBB:
631 case ARM_t2TBH:
632 // Some instructions (mostly unconditional branches) can
633 // only appears at the end of, or outside of, an IT.
634 //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
635 if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock)))
636 S = MCDisassembler_SoftFail;
637 break;
638 default:
639 break;
640 }
641
642 // If we're in an IT block, base the predicate on that. Otherwise,
643 // assume a predicate of AL.
644 CC = ITStatus_getITCC(&(ud->ITBlock));
645 if (CC == 0xF)
646 CC = ARMCC_AL;
647 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
648 ITStatus_advanceITState(&(ud->ITBlock));
649
650 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
651 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
652
653 for (i = 0; i < NumOps; ++i) {
654 if (i == MCInst_getNumOperands(MI)) break;
655 if (MCOperandInfo_isPredicate(&OpInfo[i])) {
656 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
657 if (CC == ARMCC_AL)
658 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
659 else
660 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
661 return S;
662 }
663 }
664
665 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
666 if (CC == ARMCC_AL)
667 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
668 else
669 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
670
671 return S;
672 }
673
674 // Thumb VFP instructions are a special case. Because we share their
675 // encodings between ARM and Thumb modes, and they are predicable in ARM
676 // mode, the auto-generated decoder will give them an (incorrect)
677 // predicate operand. We need to rewrite these operands based on the IT
678 // context as a post-pass.
UpdateThumbVFPPredicate(cs_struct * ud,MCInst * MI)679 static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
680 {
681 unsigned CC;
682 unsigned short NumOps;
683 const MCOperandInfo *OpInfo;
684 unsigned i;
685
686 CC = ITStatus_getITCC(&(ud->ITBlock));
687 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
688 ITStatus_advanceITState(&(ud->ITBlock));
689
690 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
691 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
692
693 for (i = 0; i < NumOps; ++i) {
694 if (MCOperandInfo_isPredicate(&OpInfo[i])) {
695 MCOperand_setImm(MCInst_getOperand(MI, i), CC);
696 if (CC == ARMCC_AL)
697 MCOperand_setReg(MCInst_getOperand(MI, i+1), 0);
698 else
699 MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR);
700 return;
701 }
702 }
703 }
704
_Thumb_getInstruction(cs_struct * ud,MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address)705 static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
706 uint16_t *Size, uint64_t Address)
707 {
708 uint16_t insn16;
709 DecodeStatus result;
710 bool InITBlock;
711 unsigned Firstcond, Mask;
712 uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
713 size_t i;
714
715 // We want to read exactly 2 bytes of data.
716 if (code_len < 2)
717 // not enough data
718 return MCDisassembler_Fail;
719
720 if (MI->flat_insn->detail) {
721 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
722 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
723 MI->flat_insn->detail->arm.operands[i].vector_index = -1;
724 MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
725 }
726 }
727
728 if (MODE_IS_BIG_ENDIAN(ud->mode))
729 insn16 = (code[0] << 8) | code[1];
730 else
731 insn16 = (code[1] << 8) | code[0];
732
733 result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
734 if (result != MCDisassembler_Fail) {
735 *Size = 2;
736 Check(&result, AddThumbPredicate(ud, MI));
737 return result;
738 }
739
740 MCInst_clear(MI);
741 result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode);
742 if (result) {
743 *Size = 2;
744 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
745 Check(&result, AddThumbPredicate(ud, MI));
746 AddThumb1SBit(MI, InITBlock);
747 return result;
748 }
749
750 MCInst_clear(MI);
751 result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode);
752 if (result != MCDisassembler_Fail) {
753 *Size = 2;
754
755 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
756 // the Thumb predicate.
757 if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock)))
758 return MCDisassembler_SoftFail;
759 Check(&result, AddThumbPredicate(ud, MI));
760
761 // If we find an IT instruction, we need to parse its condition
762 // code and mask operands so that we can apply them correctly
763 // to the subsequent instructions.
764 if (MCInst_getOpcode(MI) == ARM_t2IT) {
765
766 Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
767 Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
768 ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
769 }
770
771 return result;
772 }
773
774 // We want to read exactly 4 bytes of data.
775 if (code_len < 4)
776 // not enough data
777 return MCDisassembler_Fail;
778
779 if (MODE_IS_BIG_ENDIAN(ud->mode))
780 insn32 = (code[3] << 0) |
781 (code[2] << 8) |
782 (code[1] << 16) |
783 ((uint32_t) code[0] << 24);
784 else
785 insn32 = (code[3] << 8) |
786 (code[2] << 0) |
787 ((uint32_t) code[1] << 24) |
788 (code[0] << 16);
789
790 MCInst_clear(MI);
791 result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
792 if (result != MCDisassembler_Fail) {
793 *Size = 4;
794 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
795 Check(&result, AddThumbPredicate(ud, MI));
796 AddThumb1SBit(MI, InITBlock);
797 return result;
798 }
799
800 MCInst_clear(MI);
801 result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode);
802 if (result != MCDisassembler_Fail) {
803 *Size = 4;
804 Check(&result, AddThumbPredicate(ud, MI));
805 return result;
806 }
807
808 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
809 MCInst_clear(MI);
810 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
811 if (result != MCDisassembler_Fail) {
812 *Size = 4;
813 UpdateThumbVFPPredicate(ud, MI);
814 return result;
815 }
816 }
817
818 MCInst_clear(MI);
819 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode);
820 if (result != MCDisassembler_Fail) {
821 *Size = 4;
822 return result;
823 }
824
825 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
826 MCInst_clear(MI);
827 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode);
828 if (result != MCDisassembler_Fail) {
829 *Size = 4;
830 Check(&result, AddThumbPredicate(ud, MI));
831 return result;
832 }
833 }
834
835 if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
836 MCInst_clear(MI);
837 NEONLdStInsn = insn32;
838 NEONLdStInsn &= 0xF0FFFFFF;
839 NEONLdStInsn |= 0x04000000;
840 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode);
841 if (result != MCDisassembler_Fail) {
842 *Size = 4;
843 Check(&result, AddThumbPredicate(ud, MI));
844 return result;
845 }
846 }
847
848 if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
849 MCInst_clear(MI);
850 NEONDataInsn = insn32;
851 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
852 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
853 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
854 result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode);
855 if (result != MCDisassembler_Fail) {
856 *Size = 4;
857 Check(&result, AddThumbPredicate(ud, MI));
858 return result;
859 }
860 }
861
862 MCInst_clear(MI);
863 NEONCryptoInsn = insn32;
864 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
865 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
866 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
867 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
868 Address, NULL, ud->mode);
869 if (result != MCDisassembler_Fail) {
870 *Size = 4;
871 return result;
872 }
873
874 MCInst_clear(MI);
875 NEONv8Insn = insn32;
876 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
877 result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode);
878 if (result != MCDisassembler_Fail) {
879 *Size = 4;
880 return result;
881 }
882
883 MCInst_clear(MI);
884 *Size = 0;
885 return MCDisassembler_Fail;
886 }
887
Thumb_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)888 bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
889 uint16_t *size, uint64_t address, void *info)
890 {
891 DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
892
893 //return status == MCDisassembler_Success;
894 return status != MCDisassembler_Fail;
895 }
896
ARM_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)897 bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
898 uint16_t *size, uint64_t address, void *info)
899 {
900 DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
901
902 //return status == MCDisassembler_Success;
903 return status != MCDisassembler_Fail;
904 }
905
906 static const uint16_t GPRDecoderTable[] = {
907 ARM_R0, ARM_R1, ARM_R2, ARM_R3,
908 ARM_R4, ARM_R5, ARM_R6, ARM_R7,
909 ARM_R8, ARM_R9, ARM_R10, ARM_R11,
910 ARM_R12, ARM_SP, ARM_LR, ARM_PC
911 };
912
DecodeGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)913 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
914 uint64_t Address, const void *Decoder)
915 {
916 unsigned Register;
917 if (RegNo > 15)
918 return MCDisassembler_Fail;
919
920 Register = GPRDecoderTable[RegNo];
921 MCOperand_CreateReg0(Inst, Register);
922 return MCDisassembler_Success;
923 }
924
DecodeGPRnopcRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)925 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
926 uint64_t Address, const void *Decoder)
927 {
928 DecodeStatus S = MCDisassembler_Success;
929
930 if (RegNo == 15)
931 S = MCDisassembler_SoftFail;
932
933 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
934
935 return S;
936 }
937
DecodeGPRwithAPSRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)938 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
939 uint64_t Address, const void *Decoder)
940 {
941 DecodeStatus S = MCDisassembler_Success;
942
943 if (RegNo == 15) {
944 MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
945 return MCDisassembler_Success;
946 }
947
948 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
949 return S;
950 }
951
DecodetGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)952 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
953 uint64_t Address, const void *Decoder)
954 {
955 if (RegNo > 7)
956 return MCDisassembler_Fail;
957 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
958 }
959
960 static const uint16_t GPRPairDecoderTable[] = {
961 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
962 ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
963 };
964
DecodeGPRPairRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)965 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
966 uint64_t Address, const void *Decoder)
967 {
968 unsigned RegisterPair;
969 DecodeStatus S = MCDisassembler_Success;
970
971 if (RegNo > 13)
972 return MCDisassembler_Fail;
973
974 if ((RegNo & 1) || RegNo == 0xe)
975 S = MCDisassembler_SoftFail;
976
977 RegisterPair = GPRPairDecoderTable[RegNo/2];
978 MCOperand_CreateReg0(Inst, RegisterPair);
979 return S;
980 }
981
DecodetcGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)982 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
983 uint64_t Address, const void *Decoder)
984 {
985 unsigned Register = 0;
986 switch (RegNo) {
987 case 0:
988 Register = ARM_R0;
989 break;
990 case 1:
991 Register = ARM_R1;
992 break;
993 case 2:
994 Register = ARM_R2;
995 break;
996 case 3:
997 Register = ARM_R3;
998 break;
999 case 9:
1000 Register = ARM_R9;
1001 break;
1002 case 12:
1003 Register = ARM_R12;
1004 break;
1005 default:
1006 return MCDisassembler_Fail;
1007 }
1008
1009 MCOperand_CreateReg0(Inst, Register);
1010 return MCDisassembler_Success;
1011 }
1012
DecoderGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1013 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1014 uint64_t Address, const void *Decoder)
1015 {
1016 DecodeStatus S = MCDisassembler_Success;
1017 if (RegNo == 13 || RegNo == 15)
1018 S = MCDisassembler_SoftFail;
1019 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1020 return S;
1021 }
1022
1023 static const uint16_t SPRDecoderTable[] = {
1024 ARM_S0, ARM_S1, ARM_S2, ARM_S3,
1025 ARM_S4, ARM_S5, ARM_S6, ARM_S7,
1026 ARM_S8, ARM_S9, ARM_S10, ARM_S11,
1027 ARM_S12, ARM_S13, ARM_S14, ARM_S15,
1028 ARM_S16, ARM_S17, ARM_S18, ARM_S19,
1029 ARM_S20, ARM_S21, ARM_S22, ARM_S23,
1030 ARM_S24, ARM_S25, ARM_S26, ARM_S27,
1031 ARM_S28, ARM_S29, ARM_S30, ARM_S31
1032 };
1033
DecodeSPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1034 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
1035 uint64_t Address, const void *Decoder)
1036 {
1037 unsigned Register;
1038 if (RegNo > 31)
1039 return MCDisassembler_Fail;
1040
1041 Register = SPRDecoderTable[RegNo];
1042 MCOperand_CreateReg0(Inst, Register);
1043 return MCDisassembler_Success;
1044 }
1045
1046 static const uint16_t DPRDecoderTable[] = {
1047 ARM_D0, ARM_D1, ARM_D2, ARM_D3,
1048 ARM_D4, ARM_D5, ARM_D6, ARM_D7,
1049 ARM_D8, ARM_D9, ARM_D10, ARM_D11,
1050 ARM_D12, ARM_D13, ARM_D14, ARM_D15,
1051 ARM_D16, ARM_D17, ARM_D18, ARM_D19,
1052 ARM_D20, ARM_D21, ARM_D22, ARM_D23,
1053 ARM_D24, ARM_D25, ARM_D26, ARM_D27,
1054 ARM_D28, ARM_D29, ARM_D30, ARM_D31
1055 };
1056
DecodeDPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1057 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
1058 uint64_t Address, const void *Decoder)
1059 {
1060 unsigned Register;
1061
1062 //uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
1063 //bool hasD16 = featureBits & ARM_FeatureD16;
1064
1065 //if (RegNo > 31 || (hasD16 && RegNo > 15)) // FIXME
1066 if (RegNo > 31)
1067 return MCDisassembler_Fail;
1068
1069 Register = DPRDecoderTable[RegNo];
1070 MCOperand_CreateReg0(Inst, Register);
1071
1072 return MCDisassembler_Success;
1073 }
1074
DecodeDPR_8RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1075 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
1076 uint64_t Address, const void *Decoder)
1077 {
1078 if (RegNo > 7)
1079 return MCDisassembler_Fail;
1080 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1081 }
1082
1083 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1084 DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
1085 uint64_t Address, const void *Decoder)
1086 {
1087 if (RegNo > 15)
1088 return MCDisassembler_Fail;
1089 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1090 }
1091
1092 static const uint16_t QPRDecoderTable[] = {
1093 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
1094 ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
1095 ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11,
1096 ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15
1097 };
1098
DecodeQPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1099 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
1100 uint64_t Address, const void *Decoder)
1101 {
1102 unsigned Register;
1103 if (RegNo > 31 || (RegNo & 1) != 0)
1104 return MCDisassembler_Fail;
1105 RegNo >>= 1;
1106
1107 Register = QPRDecoderTable[RegNo];
1108 MCOperand_CreateReg0(Inst, Register);
1109 return MCDisassembler_Success;
1110 }
1111
1112 static const uint16_t DPairDecoderTable[] = {
1113 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6,
1114 ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12,
1115 ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18,
1116 ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
1117 ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30,
1118 ARM_Q15
1119 };
1120
DecodeDPairRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1121 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
1122 uint64_t Address, const void *Decoder)
1123 {
1124 unsigned Register;
1125 if (RegNo > 30)
1126 return MCDisassembler_Fail;
1127
1128 Register = DPairDecoderTable[RegNo];
1129 MCOperand_CreateReg0(Inst, Register);
1130 return MCDisassembler_Success;
1131 }
1132
1133 static const uint16_t DPairSpacedDecoderTable[] = {
1134 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5,
1135 ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
1136 ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13,
1137 ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
1138 ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
1139 ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25,
1140 ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29,
1141 ARM_D28_D30, ARM_D29_D31
1142 };
1143
DecodeDPairSpacedRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1144 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
1145 unsigned RegNo, uint64_t Address, const void *Decoder)
1146 {
1147 unsigned Register;
1148 if (RegNo > 29)
1149 return MCDisassembler_Fail;
1150
1151 Register = DPairSpacedDecoderTable[RegNo];
1152 MCOperand_CreateReg0(Inst, Register);
1153 return MCDisassembler_Success;
1154 }
1155
DecodeCCOutOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1156 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
1157 uint64_t Address, const void *Decoder)
1158 {
1159 if (Val)
1160 MCOperand_CreateReg0(Inst, ARM_CPSR);
1161 else
1162 MCOperand_CreateReg0(Inst, 0);
1163 return MCDisassembler_Success;
1164 }
1165
DecodeSORegImmOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1166 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
1167 uint64_t Address, const void *Decoder)
1168 {
1169 DecodeStatus S = MCDisassembler_Success;
1170 ARM_AM_ShiftOpc Shift;
1171 unsigned Op;
1172 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1173 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1174 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1175
1176 // Register-immediate
1177 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1178 return MCDisassembler_Fail;
1179
1180 Shift = ARM_AM_lsl;
1181 switch (type) {
1182 case 0:
1183 Shift = ARM_AM_lsl;
1184 break;
1185 case 1:
1186 Shift = ARM_AM_lsr;
1187 break;
1188 case 2:
1189 Shift = ARM_AM_asr;
1190 break;
1191 case 3:
1192 Shift = ARM_AM_ror;
1193 break;
1194 }
1195
1196 if (Shift == ARM_AM_ror && imm == 0)
1197 Shift = ARM_AM_rrx;
1198
1199 Op = Shift | (imm << 3);
1200 MCOperand_CreateImm0(Inst, Op);
1201
1202 return S;
1203 }
1204
DecodeSORegRegOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1205 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
1206 uint64_t Address, const void *Decoder)
1207 {
1208 DecodeStatus S = MCDisassembler_Success;
1209 ARM_AM_ShiftOpc Shift;
1210
1211 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1212 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1213 unsigned Rs = fieldFromInstruction_4(Val, 8, 4);
1214
1215 // Register-register
1216 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1217 return MCDisassembler_Fail;
1218 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1219 return MCDisassembler_Fail;
1220
1221 Shift = ARM_AM_lsl;
1222 switch (type) {
1223 case 0:
1224 Shift = ARM_AM_lsl;
1225 break;
1226 case 1:
1227 Shift = ARM_AM_lsr;
1228 break;
1229 case 2:
1230 Shift = ARM_AM_asr;
1231 break;
1232 case 3:
1233 Shift = ARM_AM_ror;
1234 break;
1235 }
1236
1237 MCOperand_CreateImm0(Inst, Shift);
1238
1239 return S;
1240 }
1241
DecodeRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1242 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
1243 uint64_t Address, const void *Decoder)
1244 {
1245 unsigned i;
1246 DecodeStatus S = MCDisassembler_Success;
1247 unsigned opcode;
1248
1249 bool NeedDisjointWriteback = false;
1250 unsigned WritebackReg = 0;
1251
1252 opcode = MCInst_getOpcode(Inst);
1253 switch (opcode) {
1254 default:
1255 break;
1256 case ARM_LDMIA_UPD:
1257 case ARM_LDMDB_UPD:
1258 case ARM_LDMIB_UPD:
1259 case ARM_LDMDA_UPD:
1260 case ARM_t2LDMIA_UPD:
1261 case ARM_t2LDMDB_UPD:
1262 case ARM_t2STMIA_UPD:
1263 case ARM_t2STMDB_UPD:
1264 NeedDisjointWriteback = true;
1265 WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0));
1266 break;
1267 }
1268
1269 // Empty register lists are not allowed.
1270 if (Val == 0) return MCDisassembler_Fail;
1271 for (i = 0; i < 16; ++i) {
1272 if (Val & (1 << i)) {
1273 if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1274 return MCDisassembler_Fail;
1275 // Writeback not allowed if Rn is in the target list.
1276 if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size-1])))
1277 Check(&S, MCDisassembler_SoftFail);
1278 }
1279 }
1280
1281 if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) {
1282 if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) {
1283 // invalid thumb2 pop
1284 // needs no sp in reglist and not both pc and lr set at the same time
1285 return MCDisassembler_Fail;
1286 }
1287 }
1288
1289 return S;
1290 }
1291
DecodeSPRRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1292 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
1293 uint64_t Address, const void *Decoder)
1294 {
1295 DecodeStatus S = MCDisassembler_Success;
1296 unsigned i;
1297 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1298 unsigned regs = fieldFromInstruction_4(Val, 0, 8);
1299
1300 // In case of unpredictable encoding, tweak the operands.
1301 if (regs == 0 || (Vd + regs) > 32) {
1302 regs = Vd + regs > 32 ? 32 - Vd : regs;
1303 regs = (1u > regs? 1u : regs);
1304 S = MCDisassembler_SoftFail;
1305 }
1306
1307 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1308 return MCDisassembler_Fail;
1309 for (i = 0; i < (regs - 1); ++i) {
1310 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1311 return MCDisassembler_Fail;
1312 }
1313
1314 return S;
1315 }
1316
DecodeDPRRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1317 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
1318 uint64_t Address, const void *Decoder)
1319 {
1320 DecodeStatus S = MCDisassembler_Success;
1321 unsigned i;
1322 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1323 unsigned regs = fieldFromInstruction_4(Val, 1, 7);
1324
1325 // In case of unpredictable encoding, tweak the operands.
1326 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1327 regs = Vd + regs > 32 ? 32 - Vd : regs;
1328 regs = (1u > regs? 1u : regs);
1329 regs = (16u > regs? regs : 16u);
1330 S = MCDisassembler_SoftFail;
1331 }
1332
1333 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1334 return MCDisassembler_Fail;
1335
1336 for (i = 0; i < (regs - 1); ++i) {
1337 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1338 return MCDisassembler_Fail;
1339 }
1340
1341 return S;
1342 }
1343
DecodeBitfieldMaskOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1344 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
1345 uint64_t Address, const void *Decoder)
1346 {
1347 // This operand encodes a mask of contiguous zeros between a specified MSB
1348 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1349 // the mask of all bits LSB-and-lower, and then xor them to create
1350 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1351 // create the final mask.
1352 unsigned msb = fieldFromInstruction_4(Val, 5, 5);
1353 unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
1354 uint32_t lsb_mask, msb_mask;
1355
1356 DecodeStatus S = MCDisassembler_Success;
1357 if (lsb > msb) {
1358 Check(&S, MCDisassembler_SoftFail);
1359 // The check above will cause the warning for the "potentially undefined
1360 // instruction encoding" but we can't build a bad MCOperand value here
1361 // with a lsb > msb or else printing the MCInst will cause a crash.
1362 lsb = msb;
1363 }
1364
1365 msb_mask = 0xFFFFFFFF;
1366 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1367 lsb_mask = (1U << lsb) - 1;
1368
1369 MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask));
1370 return S;
1371 }
1372
DecodeCopMemInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1373 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
1374 uint64_t Address, const void *Decoder)
1375 {
1376 DecodeStatus S = MCDisassembler_Success;
1377
1378 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1379 unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
1380 unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
1381 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
1382 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1383 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
1384
1385 switch (MCInst_getOpcode(Inst)) {
1386 case ARM_LDC_OFFSET:
1387 case ARM_LDC_PRE:
1388 case ARM_LDC_POST:
1389 case ARM_LDC_OPTION:
1390 case ARM_LDCL_OFFSET:
1391 case ARM_LDCL_PRE:
1392 case ARM_LDCL_POST:
1393 case ARM_LDCL_OPTION:
1394 case ARM_STC_OFFSET:
1395 case ARM_STC_PRE:
1396 case ARM_STC_POST:
1397 case ARM_STC_OPTION:
1398 case ARM_STCL_OFFSET:
1399 case ARM_STCL_PRE:
1400 case ARM_STCL_POST:
1401 case ARM_STCL_OPTION:
1402 case ARM_t2LDC_OFFSET:
1403 case ARM_t2LDC_PRE:
1404 case ARM_t2LDC_POST:
1405 case ARM_t2LDC_OPTION:
1406 case ARM_t2LDCL_OFFSET:
1407 case ARM_t2LDCL_PRE:
1408 case ARM_t2LDCL_POST:
1409 case ARM_t2LDCL_OPTION:
1410 case ARM_t2STC_OFFSET:
1411 case ARM_t2STC_PRE:
1412 case ARM_t2STC_POST:
1413 case ARM_t2STC_OPTION:
1414 case ARM_t2STCL_OFFSET:
1415 case ARM_t2STCL_PRE:
1416 case ARM_t2STCL_POST:
1417 case ARM_t2STCL_OPTION:
1418 if (coproc == 0xA || coproc == 0xB)
1419 return MCDisassembler_Fail;
1420 break;
1421 default:
1422 break;
1423 }
1424
1425 MCOperand_CreateImm0(Inst, coproc);
1426 MCOperand_CreateImm0(Inst, CRd);
1427 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1428 return MCDisassembler_Fail;
1429
1430 switch (MCInst_getOpcode(Inst)) {
1431 case ARM_t2LDC2_OFFSET:
1432 case ARM_t2LDC2L_OFFSET:
1433 case ARM_t2LDC2_PRE:
1434 case ARM_t2LDC2L_PRE:
1435 case ARM_t2STC2_OFFSET:
1436 case ARM_t2STC2L_OFFSET:
1437 case ARM_t2STC2_PRE:
1438 case ARM_t2STC2L_PRE:
1439 case ARM_LDC2_OFFSET:
1440 case ARM_LDC2L_OFFSET:
1441 case ARM_LDC2_PRE:
1442 case ARM_LDC2L_PRE:
1443 case ARM_STC2_OFFSET:
1444 case ARM_STC2L_OFFSET:
1445 case ARM_STC2_PRE:
1446 case ARM_STC2L_PRE:
1447 case ARM_t2LDC_OFFSET:
1448 case ARM_t2LDCL_OFFSET:
1449 case ARM_t2LDC_PRE:
1450 case ARM_t2LDCL_PRE:
1451 case ARM_t2STC_OFFSET:
1452 case ARM_t2STCL_OFFSET:
1453 case ARM_t2STC_PRE:
1454 case ARM_t2STCL_PRE:
1455 case ARM_LDC_OFFSET:
1456 case ARM_LDCL_OFFSET:
1457 case ARM_LDC_PRE:
1458 case ARM_LDCL_PRE:
1459 case ARM_STC_OFFSET:
1460 case ARM_STCL_OFFSET:
1461 case ARM_STC_PRE:
1462 case ARM_STCL_PRE:
1463 imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm);
1464 MCOperand_CreateImm0(Inst, imm);
1465 break;
1466 case ARM_t2LDC2_POST:
1467 case ARM_t2LDC2L_POST:
1468 case ARM_t2STC2_POST:
1469 case ARM_t2STC2L_POST:
1470 case ARM_LDC2_POST:
1471 case ARM_LDC2L_POST:
1472 case ARM_STC2_POST:
1473 case ARM_STC2L_POST:
1474 case ARM_t2LDC_POST:
1475 case ARM_t2LDCL_POST:
1476 case ARM_t2STC_POST:
1477 case ARM_t2STCL_POST:
1478 case ARM_LDC_POST:
1479 case ARM_LDCL_POST:
1480 case ARM_STC_POST:
1481 case ARM_STCL_POST:
1482 imm |= U << 8;
1483 // fall through.
1484 default:
1485 // The 'option' variant doesn't encode 'U' in the immediate since
1486 // the immediate is unsigned [0,255].
1487 MCOperand_CreateImm0(Inst, imm);
1488 break;
1489 }
1490
1491 switch (MCInst_getOpcode(Inst)) {
1492 case ARM_LDC_OFFSET:
1493 case ARM_LDC_PRE:
1494 case ARM_LDC_POST:
1495 case ARM_LDC_OPTION:
1496 case ARM_LDCL_OFFSET:
1497 case ARM_LDCL_PRE:
1498 case ARM_LDCL_POST:
1499 case ARM_LDCL_OPTION:
1500 case ARM_STC_OFFSET:
1501 case ARM_STC_PRE:
1502 case ARM_STC_POST:
1503 case ARM_STC_OPTION:
1504 case ARM_STCL_OFFSET:
1505 case ARM_STCL_PRE:
1506 case ARM_STCL_POST:
1507 case ARM_STCL_OPTION:
1508 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1509 return MCDisassembler_Fail;
1510 break;
1511 default:
1512 break;
1513 }
1514
1515 return S;
1516 }
1517
DecodeAddrMode2IdxInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1518 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
1519 uint64_t Address, const void *Decoder)
1520 {
1521 DecodeStatus S = MCDisassembler_Success;
1522 ARM_AM_AddrOpc Op;
1523 ARM_AM_ShiftOpc Opc;
1524 bool writeback;
1525 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1526 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1527 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1528 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
1529 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1530 unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
1531 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1532 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1533 unsigned idx_mode = 0, amt, tmp;
1534
1535 // On stores, the writeback operand precedes Rt.
1536 switch (MCInst_getOpcode(Inst)) {
1537 case ARM_STR_POST_IMM:
1538 case ARM_STR_POST_REG:
1539 case ARM_STRB_POST_IMM:
1540 case ARM_STRB_POST_REG:
1541 case ARM_STRT_POST_REG:
1542 case ARM_STRT_POST_IMM:
1543 case ARM_STRBT_POST_REG:
1544 case ARM_STRBT_POST_IMM:
1545 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1546 return MCDisassembler_Fail;
1547 break;
1548 default:
1549 break;
1550 }
1551
1552 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1553 return MCDisassembler_Fail;
1554
1555 // On loads, the writeback operand comes after Rt.
1556 switch (MCInst_getOpcode(Inst)) {
1557 case ARM_LDR_POST_IMM:
1558 case ARM_LDR_POST_REG:
1559 case ARM_LDRB_POST_IMM:
1560 case ARM_LDRB_POST_REG:
1561 case ARM_LDRBT_POST_REG:
1562 case ARM_LDRBT_POST_IMM:
1563 case ARM_LDRT_POST_REG:
1564 case ARM_LDRT_POST_IMM:
1565 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1566 return MCDisassembler_Fail;
1567 break;
1568 default:
1569 break;
1570 }
1571
1572 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1573 return MCDisassembler_Fail;
1574
1575 Op = ARM_AM_add;
1576 if (!fieldFromInstruction_4(Insn, 23, 1))
1577 Op = ARM_AM_sub;
1578
1579 writeback = (P == 0) || (W == 1);
1580 if (P && writeback)
1581 idx_mode = ARMII_IndexModePre;
1582 else if (!P && writeback)
1583 idx_mode = ARMII_IndexModePost;
1584
1585 if (writeback && (Rn == 15 || Rn == Rt))
1586 S = MCDisassembler_SoftFail; // UNPREDICTABLE
1587
1588 if (reg) {
1589 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1590 return MCDisassembler_Fail;
1591 Opc = ARM_AM_lsl;
1592 switch( fieldFromInstruction_4(Insn, 5, 2)) {
1593 case 0:
1594 Opc = ARM_AM_lsl;
1595 break;
1596 case 1:
1597 Opc = ARM_AM_lsr;
1598 break;
1599 case 2:
1600 Opc = ARM_AM_asr;
1601 break;
1602 case 3:
1603 Opc = ARM_AM_ror;
1604 break;
1605 default:
1606 return MCDisassembler_Fail;
1607 }
1608 amt = fieldFromInstruction_4(Insn, 7, 5);
1609 if (Opc == ARM_AM_ror && amt == 0)
1610 Opc = ARM_AM_rrx;
1611 imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
1612
1613 MCOperand_CreateImm0(Inst, imm);
1614 } else {
1615 MCOperand_CreateReg0(Inst, 0);
1616 tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
1617 MCOperand_CreateImm0(Inst, tmp);
1618 }
1619
1620 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1621 return MCDisassembler_Fail;
1622
1623 return S;
1624 }
1625
DecodeSORegMemOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1626 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
1627 uint64_t Address, const void *Decoder)
1628 {
1629 DecodeStatus S = MCDisassembler_Success;
1630 ARM_AM_ShiftOpc ShOp;
1631 unsigned shift;
1632 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
1633 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1634 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1635 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1636 unsigned U = fieldFromInstruction_4(Val, 12, 1);
1637
1638 ShOp = ARM_AM_lsl;
1639 switch (type) {
1640 case 0:
1641 ShOp = ARM_AM_lsl;
1642 break;
1643 case 1:
1644 ShOp = ARM_AM_lsr;
1645 break;
1646 case 2:
1647 ShOp = ARM_AM_asr;
1648 break;
1649 case 3:
1650 ShOp = ARM_AM_ror;
1651 break;
1652 }
1653
1654 if (ShOp == ARM_AM_ror && imm == 0)
1655 ShOp = ARM_AM_rrx;
1656
1657 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1658 return MCDisassembler_Fail;
1659 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1660 return MCDisassembler_Fail;
1661 if (U)
1662 shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0);
1663 else
1664 shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0);
1665 MCOperand_CreateImm0(Inst, shift);
1666
1667 return S;
1668 }
1669
DecodeAddrMode3Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1670 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
1671 uint64_t Address, const void *Decoder)
1672 {
1673 DecodeStatus S = MCDisassembler_Success;
1674
1675 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1676 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1677 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1678 unsigned type = fieldFromInstruction_4(Insn, 22, 1);
1679 unsigned imm = fieldFromInstruction_4(Insn, 8, 4);
1680 unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8;
1681 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1682 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1683 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1684 unsigned Rt2 = Rt + 1;
1685
1686 bool writeback = (W == 1) | (P == 0);
1687
1688 // For {LD,ST}RD, Rt must be even, else undefined.
1689 switch (MCInst_getOpcode(Inst)) {
1690 case ARM_STRD:
1691 case ARM_STRD_PRE:
1692 case ARM_STRD_POST:
1693 case ARM_LDRD:
1694 case ARM_LDRD_PRE:
1695 case ARM_LDRD_POST:
1696 if (Rt & 0x1) S = MCDisassembler_SoftFail;
1697 break;
1698 default:
1699 break;
1700 }
1701 switch (MCInst_getOpcode(Inst)) {
1702 case ARM_STRD:
1703 case ARM_STRD_PRE:
1704 case ARM_STRD_POST:
1705 if (P == 0 && W == 1)
1706 S = MCDisassembler_SoftFail;
1707
1708 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1709 S = MCDisassembler_SoftFail;
1710 if (type && Rm == 15)
1711 S = MCDisassembler_SoftFail;
1712 if (Rt2 == 15)
1713 S = MCDisassembler_SoftFail;
1714 if (!type && fieldFromInstruction_4(Insn, 8, 4))
1715 S = MCDisassembler_SoftFail;
1716 break;
1717 case ARM_STRH:
1718 case ARM_STRH_PRE:
1719 case ARM_STRH_POST:
1720 if (Rt == 15)
1721 S = MCDisassembler_SoftFail;
1722 if (writeback && (Rn == 15 || Rn == Rt))
1723 S = MCDisassembler_SoftFail;
1724 if (!type && Rm == 15)
1725 S = MCDisassembler_SoftFail;
1726 break;
1727 case ARM_LDRD:
1728 case ARM_LDRD_PRE:
1729 case ARM_LDRD_POST:
1730 if (type && Rn == 15){
1731 if (Rt2 == 15)
1732 S = MCDisassembler_SoftFail;
1733 break;
1734 }
1735 if (P == 0 && W == 1)
1736 S = MCDisassembler_SoftFail;
1737 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1738 S = MCDisassembler_SoftFail;
1739 if (!type && writeback && Rn == 15)
1740 S = MCDisassembler_SoftFail;
1741 if (writeback && (Rn == Rt || Rn == Rt2))
1742 S = MCDisassembler_SoftFail;
1743 break;
1744 case ARM_LDRH:
1745 case ARM_LDRH_PRE:
1746 case ARM_LDRH_POST:
1747 if (type && Rn == 15){
1748 if (Rt == 15)
1749 S = MCDisassembler_SoftFail;
1750 break;
1751 }
1752 if (Rt == 15)
1753 S = MCDisassembler_SoftFail;
1754 if (!type && Rm == 15)
1755 S = MCDisassembler_SoftFail;
1756 if (!type && writeback && (Rn == 15 || Rn == Rt))
1757 S = MCDisassembler_SoftFail;
1758 break;
1759 case ARM_LDRSH:
1760 case ARM_LDRSH_PRE:
1761 case ARM_LDRSH_POST:
1762 case ARM_LDRSB:
1763 case ARM_LDRSB_PRE:
1764 case ARM_LDRSB_POST:
1765 if (type && Rn == 15){
1766 if (Rt == 15)
1767 S = MCDisassembler_SoftFail;
1768 break;
1769 }
1770 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1771 S = MCDisassembler_SoftFail;
1772 if (!type && (Rt == 15 || Rm == 15))
1773 S = MCDisassembler_SoftFail;
1774 if (!type && writeback && (Rn == 15 || Rn == Rt))
1775 S = MCDisassembler_SoftFail;
1776 break;
1777 default:
1778 break;
1779 }
1780
1781 if (writeback) { // Writeback
1782 Inst->writeback = true;
1783 if (P)
1784 U |= ARMII_IndexModePre << 9;
1785 else
1786 U |= ARMII_IndexModePost << 9;
1787
1788 // On stores, the writeback operand precedes Rt.
1789 switch (MCInst_getOpcode(Inst)) {
1790 case ARM_STRD:
1791 case ARM_STRD_PRE:
1792 case ARM_STRD_POST:
1793 case ARM_STRH:
1794 case ARM_STRH_PRE:
1795 case ARM_STRH_POST:
1796 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1797 return MCDisassembler_Fail;
1798 break;
1799 default:
1800 break;
1801 }
1802 }
1803
1804 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1805 return MCDisassembler_Fail;
1806 switch (MCInst_getOpcode(Inst)) {
1807 case ARM_STRD:
1808 case ARM_STRD_PRE:
1809 case ARM_STRD_POST:
1810 case ARM_LDRD:
1811 case ARM_LDRD_PRE:
1812 case ARM_LDRD_POST:
1813 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1814 return MCDisassembler_Fail;
1815 break;
1816 default:
1817 break;
1818 }
1819
1820 if (writeback) {
1821 // On loads, the writeback operand comes after Rt.
1822 switch (MCInst_getOpcode(Inst)) {
1823 case ARM_LDRD:
1824 case ARM_LDRD_PRE:
1825 case ARM_LDRD_POST:
1826 case ARM_LDRH:
1827 case ARM_LDRH_PRE:
1828 case ARM_LDRH_POST:
1829 case ARM_LDRSH:
1830 case ARM_LDRSH_PRE:
1831 case ARM_LDRSH_POST:
1832 case ARM_LDRSB:
1833 case ARM_LDRSB_PRE:
1834 case ARM_LDRSB_POST:
1835 case ARM_LDRHTr:
1836 case ARM_LDRSBTr:
1837 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1838 return MCDisassembler_Fail;
1839 break;
1840 default:
1841 break;
1842 }
1843 }
1844
1845 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1846 return MCDisassembler_Fail;
1847
1848 if (type) {
1849 MCOperand_CreateReg0(Inst, 0);
1850 MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm);
1851 } else {
1852 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1853 return MCDisassembler_Fail;
1854 MCOperand_CreateImm0(Inst, U);
1855 }
1856
1857 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1858 return MCDisassembler_Fail;
1859
1860 return S;
1861 }
1862
DecodeRFEInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1863 static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
1864 uint64_t Address, const void *Decoder)
1865 {
1866 DecodeStatus S = MCDisassembler_Success;
1867
1868 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1869 unsigned mode = fieldFromInstruction_4(Insn, 23, 2);
1870
1871 switch (mode) {
1872 case 0:
1873 mode = ARM_AM_da;
1874 break;
1875 case 1:
1876 mode = ARM_AM_ia;
1877 break;
1878 case 2:
1879 mode = ARM_AM_db;
1880 break;
1881 case 3:
1882 mode = ARM_AM_ib;
1883 break;
1884 }
1885
1886 MCOperand_CreateImm0(Inst, mode);
1887 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1888 return MCDisassembler_Fail;
1889
1890 return S;
1891 }
1892
DecodeQADDInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1893 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
1894 uint64_t Address, const void *Decoder)
1895 {
1896 DecodeStatus S = MCDisassembler_Success;
1897
1898 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
1899 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1900 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1901 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1902
1903 if (pred == 0xF)
1904 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1905
1906 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1907 return MCDisassembler_Fail;
1908 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1909 return MCDisassembler_Fail;
1910 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1911 return MCDisassembler_Fail;
1912 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1913 return MCDisassembler_Fail;
1914 return S;
1915 }
1916
DecodeMemMultipleWritebackInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1917 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
1918 unsigned Insn, uint64_t Address, const void *Decoder)
1919 {
1920 DecodeStatus S = MCDisassembler_Success;
1921
1922 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1923 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1924 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16);
1925
1926 if (pred == 0xF) {
1927 // Ambiguous with RFE and SRS
1928 switch (MCInst_getOpcode(Inst)) {
1929 case ARM_LDMDA:
1930 MCInst_setOpcode(Inst, ARM_RFEDA);
1931 break;
1932 case ARM_LDMDA_UPD:
1933 MCInst_setOpcode(Inst, ARM_RFEDA_UPD);
1934 break;
1935 case ARM_LDMDB:
1936 MCInst_setOpcode(Inst, ARM_RFEDB);
1937 break;
1938 case ARM_LDMDB_UPD:
1939 MCInst_setOpcode(Inst, ARM_RFEDB_UPD);
1940 break;
1941 case ARM_LDMIA:
1942 MCInst_setOpcode(Inst, ARM_RFEIA);
1943 break;
1944 case ARM_LDMIA_UPD:
1945 MCInst_setOpcode(Inst, ARM_RFEIA_UPD);
1946 break;
1947 case ARM_LDMIB:
1948 MCInst_setOpcode(Inst, ARM_RFEIB);
1949 break;
1950 case ARM_LDMIB_UPD:
1951 MCInst_setOpcode(Inst, ARM_RFEIB_UPD);
1952 break;
1953 case ARM_STMDA:
1954 MCInst_setOpcode(Inst, ARM_SRSDA);
1955 break;
1956 case ARM_STMDA_UPD:
1957 MCInst_setOpcode(Inst, ARM_SRSDA_UPD);
1958 break;
1959 case ARM_STMDB:
1960 MCInst_setOpcode(Inst, ARM_SRSDB);
1961 break;
1962 case ARM_STMDB_UPD:
1963 MCInst_setOpcode(Inst, ARM_SRSDB_UPD);
1964 break;
1965 case ARM_STMIA:
1966 MCInst_setOpcode(Inst, ARM_SRSIA);
1967 break;
1968 case ARM_STMIA_UPD:
1969 MCInst_setOpcode(Inst, ARM_SRSIA_UPD);
1970 break;
1971 case ARM_STMIB:
1972 MCInst_setOpcode(Inst, ARM_SRSIB);
1973 break;
1974 case ARM_STMIB_UPD:
1975 MCInst_setOpcode(Inst, ARM_SRSIB_UPD);
1976 break;
1977 default:
1978 return MCDisassembler_Fail;
1979 }
1980
1981 // For stores (which become SRS's, the only operand is the mode.
1982 if (fieldFromInstruction_4(Insn, 20, 1) == 0) {
1983 // Check SRS encoding constraints
1984 if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 &&
1985 fieldFromInstruction_4(Insn, 20, 1) == 0))
1986 return MCDisassembler_Fail;
1987
1988 MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4));
1989 return S;
1990 }
1991
1992 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1993 }
1994
1995 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1996 return MCDisassembler_Fail;
1997 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1998 return MCDisassembler_Fail; // Tied
1999 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2000 return MCDisassembler_Fail;
2001 if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2002 return MCDisassembler_Fail;
2003
2004 return S;
2005 }
2006
DecodeCPSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2007 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
2008 uint64_t Address, const void *Decoder)
2009 {
2010 unsigned imod = fieldFromInstruction_4(Insn, 18, 2);
2011 unsigned M = fieldFromInstruction_4(Insn, 17, 1);
2012 unsigned iflags = fieldFromInstruction_4(Insn, 6, 3);
2013 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2014
2015 DecodeStatus S = MCDisassembler_Success;
2016
2017 // This decoder is called from multiple location that do not check
2018 // the full encoding is valid before they do.
2019 if (fieldFromInstruction_4(Insn, 5, 1) != 0 ||
2020 fieldFromInstruction_4(Insn, 16, 1) != 0 ||
2021 fieldFromInstruction_4(Insn, 20, 8) != 0x10)
2022 return MCDisassembler_Fail;
2023
2024 // imod == '01' --> UNPREDICTABLE
2025 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2026 // return failure here. The '01' imod value is unprintable, so there's
2027 // nothing useful we could do even if we returned UNPREDICTABLE.
2028
2029 if (imod == 1) return MCDisassembler_Fail;
2030
2031 if (imod && M) {
2032 MCInst_setOpcode(Inst, ARM_CPS3p);
2033 MCOperand_CreateImm0(Inst, imod);
2034 MCOperand_CreateImm0(Inst, iflags);
2035 MCOperand_CreateImm0(Inst, mode);
2036 } else if (imod && !M) {
2037 MCInst_setOpcode(Inst, ARM_CPS2p);
2038 MCOperand_CreateImm0(Inst, imod);
2039 MCOperand_CreateImm0(Inst, iflags);
2040 if (mode) S = MCDisassembler_SoftFail;
2041 } else if (!imod && M) {
2042 MCInst_setOpcode(Inst, ARM_CPS1p);
2043 MCOperand_CreateImm0(Inst, mode);
2044 if (iflags) S = MCDisassembler_SoftFail;
2045 } else {
2046 // imod == '00' && M == '0' --> UNPREDICTABLE
2047 MCInst_setOpcode(Inst, ARM_CPS1p);
2048 MCOperand_CreateImm0(Inst, mode);
2049 S = MCDisassembler_SoftFail;
2050 }
2051
2052 return S;
2053 }
2054
DecodeT2CPSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2055 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
2056 uint64_t Address, const void *Decoder)
2057 {
2058 unsigned imod = fieldFromInstruction_4(Insn, 9, 2);
2059 unsigned M = fieldFromInstruction_4(Insn, 8, 1);
2060 unsigned iflags = fieldFromInstruction_4(Insn, 5, 3);
2061 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2062
2063 DecodeStatus S = MCDisassembler_Success;
2064
2065 // imod == '01' --> UNPREDICTABLE
2066 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2067 // return failure here. The '01' imod value is unprintable, so there's
2068 // nothing useful we could do even if we returned UNPREDICTABLE.
2069
2070 if (imod == 1) return MCDisassembler_Fail;
2071
2072 if (imod && M) {
2073 MCInst_setOpcode(Inst, ARM_t2CPS3p);
2074 MCOperand_CreateImm0(Inst, imod);
2075 MCOperand_CreateImm0(Inst, iflags);
2076 MCOperand_CreateImm0(Inst, mode);
2077 } else if (imod && !M) {
2078 MCInst_setOpcode(Inst, ARM_t2CPS2p);
2079 MCOperand_CreateImm0(Inst, imod);
2080 MCOperand_CreateImm0(Inst, iflags);
2081 if (mode) S = MCDisassembler_SoftFail;
2082 } else if (!imod && M) {
2083 MCInst_setOpcode(Inst, ARM_t2CPS1p);
2084 MCOperand_CreateImm0(Inst, mode);
2085 if (iflags) S = MCDisassembler_SoftFail;
2086 } else {
2087 // imod == '00' && M == '0' --> this is a HINT instruction
2088 int imm = fieldFromInstruction_4(Insn, 0, 8);
2089 // HINT are defined only for immediate in [0..4]
2090 if(imm > 4) return MCDisassembler_Fail;
2091 MCInst_setOpcode(Inst, ARM_t2HINT);
2092 MCOperand_CreateImm0(Inst, imm);
2093 }
2094
2095 return S;
2096 }
2097
DecodeT2MOVTWInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2098 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
2099 uint64_t Address, const void *Decoder)
2100 {
2101 DecodeStatus S = MCDisassembler_Success;
2102
2103 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
2104 unsigned imm = 0;
2105
2106 imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0);
2107 imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8);
2108 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2109 imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11);
2110
2111 if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16)
2112 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2113 return MCDisassembler_Fail;
2114 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2115 return MCDisassembler_Fail;
2116
2117 MCOperand_CreateImm0(Inst, imm);
2118
2119 return S;
2120 }
2121
DecodeArmMOVTWInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2122 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
2123 uint64_t Address, const void *Decoder)
2124 {
2125 DecodeStatus S = MCDisassembler_Success;
2126
2127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2128 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2129 unsigned imm = 0;
2130
2131 imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0);
2132 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2133
2134 if (MCInst_getOpcode(Inst) == ARM_MOVTi16)
2135 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2136 return MCDisassembler_Fail;
2137
2138 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2139 return MCDisassembler_Fail;
2140
2141 MCOperand_CreateImm0(Inst, imm);
2142
2143 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2144 return MCDisassembler_Fail;
2145
2146 return S;
2147 }
2148
DecodeSMLAInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2149 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
2150 uint64_t Address, const void *Decoder)
2151 {
2152 DecodeStatus S = MCDisassembler_Success;
2153
2154 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4);
2155 unsigned Rn = fieldFromInstruction_4(Insn, 0, 4);
2156 unsigned Rm = fieldFromInstruction_4(Insn, 8, 4);
2157 unsigned Ra = fieldFromInstruction_4(Insn, 12, 4);
2158 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2159
2160 if (pred == 0xF)
2161 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2162
2163 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2164 return MCDisassembler_Fail;
2165 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2166 return MCDisassembler_Fail;
2167 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2168 return MCDisassembler_Fail;
2169 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2170 return MCDisassembler_Fail;
2171
2172 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2173 return MCDisassembler_Fail;
2174
2175 return S;
2176 }
2177
DecodeAddrModeImm12Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2178 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
2179 uint64_t Address, const void *Decoder)
2180 {
2181 DecodeStatus S = MCDisassembler_Success;
2182
2183 unsigned add = fieldFromInstruction_4(Val, 12, 1);
2184 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
2185 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
2186
2187 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2188 return MCDisassembler_Fail;
2189
2190 if (!add) imm *= (unsigned int)-1;
2191 if (imm == 0 && !add) imm = (unsigned int)INT32_MIN;
2192 MCOperand_CreateImm0(Inst, imm);
2193 //if (Rn == 15)
2194 // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2195
2196 return S;
2197 }
2198
DecodeAddrMode5Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2199 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
2200 uint64_t Address, const void *Decoder)
2201 {
2202 DecodeStatus S = MCDisassembler_Success;
2203
2204 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
2205 unsigned U = fieldFromInstruction_4(Val, 8, 1);
2206 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
2207
2208 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2209 return MCDisassembler_Fail;
2210
2211 if (U)
2212 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm));
2213 else
2214 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm));
2215
2216 return S;
2217 }
2218
DecodeAddrMode7Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2219 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
2220 uint64_t Address, const void *Decoder)
2221 {
2222 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2223 }
2224
DecodeT2BInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2225 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
2226 uint64_t Address, const void *Decoder)
2227 {
2228 DecodeStatus Status = MCDisassembler_Success;
2229
2230 // Note the J1 and J2 values are from the encoded instruction. So here
2231 // change them to I1 and I2 values via as documented:
2232 // I1 = NOT(J1 EOR S);
2233 // I2 = NOT(J2 EOR S);
2234 // and build the imm32 with one trailing zero as documented:
2235 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2236 unsigned S = fieldFromInstruction_4(Insn, 26, 1);
2237 unsigned J1 = fieldFromInstruction_4(Insn, 13, 1);
2238 unsigned J2 = fieldFromInstruction_4(Insn, 11, 1);
2239 unsigned I1 = !(J1 ^ S);
2240 unsigned I2 = !(J2 ^ S);
2241 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10);
2242 unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11);
2243 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2244 int imm32 = SignExtend32(tmp << 1, 25);
2245 MCOperand_CreateImm0(Inst, imm32);
2246
2247 return Status;
2248 }
2249
DecodeBranchImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2250 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
2251 uint64_t Address, const void *Decoder)
2252 {
2253 DecodeStatus S = MCDisassembler_Success;
2254
2255 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2256 unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2;
2257
2258 if (pred == 0xF) {
2259 MCInst_setOpcode(Inst, ARM_BLXi);
2260 imm |= fieldFromInstruction_4(Insn, 24, 1) << 1;
2261 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
2262 return S;
2263 }
2264
2265 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
2266 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2267 return MCDisassembler_Fail;
2268
2269 return S;
2270 }
2271
2272
DecodeAddrMode6Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2273 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
2274 uint64_t Address, const void *Decoder)
2275 {
2276 DecodeStatus S = MCDisassembler_Success;
2277
2278 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
2279 unsigned align = fieldFromInstruction_4(Val, 4, 2);
2280
2281 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2282 return MCDisassembler_Fail;
2283 if (!align)
2284 MCOperand_CreateImm0(Inst, 0);
2285 else
2286 MCOperand_CreateImm0(Inst, 4 << align);
2287
2288 return S;
2289 }
2290
DecodeVLDInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2291 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
2292 uint64_t Address, const void *Decoder)
2293 {
2294 DecodeStatus S = MCDisassembler_Success;
2295 unsigned wb, Rn, Rm;
2296 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2297 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2298 wb = fieldFromInstruction_4(Insn, 16, 4);
2299 Rn = fieldFromInstruction_4(Insn, 16, 4);
2300 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2301 Rm = fieldFromInstruction_4(Insn, 0, 4);
2302
2303 // First output register
2304 switch (MCInst_getOpcode(Inst)) {
2305 case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8:
2306 case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register:
2307 case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register:
2308 case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register:
2309 case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register:
2310 case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8:
2311 case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register:
2312 case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register:
2313 case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register:
2314 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2315 return MCDisassembler_Fail;
2316 break;
2317 case ARM_VLD2b16:
2318 case ARM_VLD2b32:
2319 case ARM_VLD2b8:
2320 case ARM_VLD2b16wb_fixed:
2321 case ARM_VLD2b16wb_register:
2322 case ARM_VLD2b32wb_fixed:
2323 case ARM_VLD2b32wb_register:
2324 case ARM_VLD2b8wb_fixed:
2325 case ARM_VLD2b8wb_register:
2326 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2327 return MCDisassembler_Fail;
2328 break;
2329 default:
2330 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2331 return MCDisassembler_Fail;
2332 }
2333
2334 // Second output register
2335 switch (MCInst_getOpcode(Inst)) {
2336 case ARM_VLD3d8:
2337 case ARM_VLD3d16:
2338 case ARM_VLD3d32:
2339 case ARM_VLD3d8_UPD:
2340 case ARM_VLD3d16_UPD:
2341 case ARM_VLD3d32_UPD:
2342 case ARM_VLD4d8:
2343 case ARM_VLD4d16:
2344 case ARM_VLD4d32:
2345 case ARM_VLD4d8_UPD:
2346 case ARM_VLD4d16_UPD:
2347 case ARM_VLD4d32_UPD:
2348 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2349 return MCDisassembler_Fail;
2350 break;
2351 case ARM_VLD3q8:
2352 case ARM_VLD3q16:
2353 case ARM_VLD3q32:
2354 case ARM_VLD3q8_UPD:
2355 case ARM_VLD3q16_UPD:
2356 case ARM_VLD3q32_UPD:
2357 case ARM_VLD4q8:
2358 case ARM_VLD4q16:
2359 case ARM_VLD4q32:
2360 case ARM_VLD4q8_UPD:
2361 case ARM_VLD4q16_UPD:
2362 case ARM_VLD4q32_UPD:
2363 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2364 return MCDisassembler_Fail;
2365 default:
2366 break;
2367 }
2368
2369 // Third output register
2370 switch(MCInst_getOpcode(Inst)) {
2371 case ARM_VLD3d8:
2372 case ARM_VLD3d16:
2373 case ARM_VLD3d32:
2374 case ARM_VLD3d8_UPD:
2375 case ARM_VLD3d16_UPD:
2376 case ARM_VLD3d32_UPD:
2377 case ARM_VLD4d8:
2378 case ARM_VLD4d16:
2379 case ARM_VLD4d32:
2380 case ARM_VLD4d8_UPD:
2381 case ARM_VLD4d16_UPD:
2382 case ARM_VLD4d32_UPD:
2383 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2384 return MCDisassembler_Fail;
2385 break;
2386 case ARM_VLD3q8:
2387 case ARM_VLD3q16:
2388 case ARM_VLD3q32:
2389 case ARM_VLD3q8_UPD:
2390 case ARM_VLD3q16_UPD:
2391 case ARM_VLD3q32_UPD:
2392 case ARM_VLD4q8:
2393 case ARM_VLD4q16:
2394 case ARM_VLD4q32:
2395 case ARM_VLD4q8_UPD:
2396 case ARM_VLD4q16_UPD:
2397 case ARM_VLD4q32_UPD:
2398 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2399 return MCDisassembler_Fail;
2400 break;
2401 default:
2402 break;
2403 }
2404
2405 // Fourth output register
2406 switch (MCInst_getOpcode(Inst)) {
2407 case ARM_VLD4d8:
2408 case ARM_VLD4d16:
2409 case ARM_VLD4d32:
2410 case ARM_VLD4d8_UPD:
2411 case ARM_VLD4d16_UPD:
2412 case ARM_VLD4d32_UPD:
2413 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2414 return MCDisassembler_Fail;
2415 break;
2416 case ARM_VLD4q8:
2417 case ARM_VLD4q16:
2418 case ARM_VLD4q32:
2419 case ARM_VLD4q8_UPD:
2420 case ARM_VLD4q16_UPD:
2421 case ARM_VLD4q32_UPD:
2422 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2423 return MCDisassembler_Fail;
2424 break;
2425 default:
2426 break;
2427 }
2428
2429 // Writeback operand
2430 switch (MCInst_getOpcode(Inst)) {
2431 case ARM_VLD1d8wb_fixed:
2432 case ARM_VLD1d16wb_fixed:
2433 case ARM_VLD1d32wb_fixed:
2434 case ARM_VLD1d64wb_fixed:
2435 case ARM_VLD1d8wb_register:
2436 case ARM_VLD1d16wb_register:
2437 case ARM_VLD1d32wb_register:
2438 case ARM_VLD1d64wb_register:
2439 case ARM_VLD1q8wb_fixed:
2440 case ARM_VLD1q16wb_fixed:
2441 case ARM_VLD1q32wb_fixed:
2442 case ARM_VLD1q64wb_fixed:
2443 case ARM_VLD1q8wb_register:
2444 case ARM_VLD1q16wb_register:
2445 case ARM_VLD1q32wb_register:
2446 case ARM_VLD1q64wb_register:
2447 case ARM_VLD1d8Twb_fixed:
2448 case ARM_VLD1d8Twb_register:
2449 case ARM_VLD1d16Twb_fixed:
2450 case ARM_VLD1d16Twb_register:
2451 case ARM_VLD1d32Twb_fixed:
2452 case ARM_VLD1d32Twb_register:
2453 case ARM_VLD1d64Twb_fixed:
2454 case ARM_VLD1d64Twb_register:
2455 case ARM_VLD1d8Qwb_fixed:
2456 case ARM_VLD1d8Qwb_register:
2457 case ARM_VLD1d16Qwb_fixed:
2458 case ARM_VLD1d16Qwb_register:
2459 case ARM_VLD1d32Qwb_fixed:
2460 case ARM_VLD1d32Qwb_register:
2461 case ARM_VLD1d64Qwb_fixed:
2462 case ARM_VLD1d64Qwb_register:
2463 case ARM_VLD2d8wb_fixed:
2464 case ARM_VLD2d16wb_fixed:
2465 case ARM_VLD2d32wb_fixed:
2466 case ARM_VLD2q8wb_fixed:
2467 case ARM_VLD2q16wb_fixed:
2468 case ARM_VLD2q32wb_fixed:
2469 case ARM_VLD2d8wb_register:
2470 case ARM_VLD2d16wb_register:
2471 case ARM_VLD2d32wb_register:
2472 case ARM_VLD2q8wb_register:
2473 case ARM_VLD2q16wb_register:
2474 case ARM_VLD2q32wb_register:
2475 case ARM_VLD2b8wb_fixed:
2476 case ARM_VLD2b16wb_fixed:
2477 case ARM_VLD2b32wb_fixed:
2478 case ARM_VLD2b8wb_register:
2479 case ARM_VLD2b16wb_register:
2480 case ARM_VLD2b32wb_register:
2481 MCOperand_CreateImm0(Inst, 0);
2482 break;
2483 case ARM_VLD3d8_UPD:
2484 case ARM_VLD3d16_UPD:
2485 case ARM_VLD3d32_UPD:
2486 case ARM_VLD3q8_UPD:
2487 case ARM_VLD3q16_UPD:
2488 case ARM_VLD3q32_UPD:
2489 case ARM_VLD4d8_UPD:
2490 case ARM_VLD4d16_UPD:
2491 case ARM_VLD4d32_UPD:
2492 case ARM_VLD4q8_UPD:
2493 case ARM_VLD4q16_UPD:
2494 case ARM_VLD4q32_UPD:
2495 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2496 return MCDisassembler_Fail;
2497 break;
2498 default:
2499 break;
2500 }
2501
2502 // AddrMode6 Base (register+alignment)
2503 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2504 return MCDisassembler_Fail;
2505
2506 // AddrMode6 Offset (register)
2507 switch (MCInst_getOpcode(Inst)) {
2508 default:
2509 // The below have been updated to have explicit am6offset split
2510 // between fixed and register offset. For those instructions not
2511 // yet updated, we need to add an additional reg0 operand for the
2512 // fixed variant.
2513 //
2514 // The fixed offset encodes as Rm == 0xd, so we check for that.
2515 if (Rm == 0xd) {
2516 MCOperand_CreateReg0(Inst, 0);
2517 break;
2518 }
2519 // Fall through to handle the register offset variant.
2520 case ARM_VLD1d8wb_fixed:
2521 case ARM_VLD1d16wb_fixed:
2522 case ARM_VLD1d32wb_fixed:
2523 case ARM_VLD1d64wb_fixed:
2524 case ARM_VLD1d8Twb_fixed:
2525 case ARM_VLD1d16Twb_fixed:
2526 case ARM_VLD1d32Twb_fixed:
2527 case ARM_VLD1d64Twb_fixed:
2528 case ARM_VLD1d8Qwb_fixed:
2529 case ARM_VLD1d16Qwb_fixed:
2530 case ARM_VLD1d32Qwb_fixed:
2531 case ARM_VLD1d64Qwb_fixed:
2532 case ARM_VLD1d8wb_register:
2533 case ARM_VLD1d16wb_register:
2534 case ARM_VLD1d32wb_register:
2535 case ARM_VLD1d64wb_register:
2536 case ARM_VLD1q8wb_fixed:
2537 case ARM_VLD1q16wb_fixed:
2538 case ARM_VLD1q32wb_fixed:
2539 case ARM_VLD1q64wb_fixed:
2540 case ARM_VLD1q8wb_register:
2541 case ARM_VLD1q16wb_register:
2542 case ARM_VLD1q32wb_register:
2543 case ARM_VLD1q64wb_register:
2544 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2545 // variant encodes Rm == 0xf. Anything else is a register offset post-
2546 // increment and we need to add the register operand to the instruction.
2547 if (Rm != 0xD && Rm != 0xF &&
2548 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2549 return MCDisassembler_Fail;
2550 break;
2551 case ARM_VLD2d8wb_fixed:
2552 case ARM_VLD2d16wb_fixed:
2553 case ARM_VLD2d32wb_fixed:
2554 case ARM_VLD2b8wb_fixed:
2555 case ARM_VLD2b16wb_fixed:
2556 case ARM_VLD2b32wb_fixed:
2557 case ARM_VLD2q8wb_fixed:
2558 case ARM_VLD2q16wb_fixed:
2559 case ARM_VLD2q32wb_fixed:
2560 break;
2561 }
2562
2563 return S;
2564 }
2565
DecodeVLDST1Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2566 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
2567 uint64_t Address, const void *Decoder)
2568 {
2569 unsigned load;
2570 unsigned type = fieldFromInstruction_4(Insn, 8, 4);
2571 unsigned align = fieldFromInstruction_4(Insn, 4, 2);
2572 if (type == 6 && (align & 2)) return MCDisassembler_Fail;
2573 if (type == 7 && (align & 2)) return MCDisassembler_Fail;
2574 if (type == 10 && align == 3) return MCDisassembler_Fail;
2575
2576 load = fieldFromInstruction_4(Insn, 21, 1);
2577 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2578 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2579 }
2580
DecodeVLDST2Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2581 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
2582 uint64_t Address, const void *Decoder)
2583 {
2584 unsigned type, align, load;
2585 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2586 if (size == 3) return MCDisassembler_Fail;
2587
2588 type = fieldFromInstruction_4(Insn, 8, 4);
2589 align = fieldFromInstruction_4(Insn, 4, 2);
2590 if (type == 8 && align == 3) return MCDisassembler_Fail;
2591 if (type == 9 && align == 3) return MCDisassembler_Fail;
2592
2593 load = fieldFromInstruction_4(Insn, 21, 1);
2594 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2595 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2596 }
2597
DecodeVLDST3Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2598 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
2599 uint64_t Address, const void *Decoder)
2600 {
2601 unsigned align, load;
2602 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2603 if (size == 3) return MCDisassembler_Fail;
2604
2605 align = fieldFromInstruction_4(Insn, 4, 2);
2606 if (align & 2) return MCDisassembler_Fail;
2607
2608 load = fieldFromInstruction_4(Insn, 21, 1);
2609 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2610 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2611 }
2612
DecodeVLDST4Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2613 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
2614 uint64_t Address, const void *Decoder)
2615 {
2616 unsigned load;
2617 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2618 if (size == 3) return MCDisassembler_Fail;
2619
2620 load = fieldFromInstruction_4(Insn, 21, 1);
2621 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2622 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2623 }
2624
DecodeVSTInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2625 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
2626 uint64_t Address, const void *Decoder)
2627 {
2628 DecodeStatus S = MCDisassembler_Success;
2629 unsigned wb, Rn, Rm;
2630 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2631 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2632 wb = fieldFromInstruction_4(Insn, 16, 4);
2633 Rn = fieldFromInstruction_4(Insn, 16, 4);
2634 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2635 Rm = fieldFromInstruction_4(Insn, 0, 4);
2636
2637 // Writeback Operand
2638 switch (MCInst_getOpcode(Inst)) {
2639 case ARM_VST1d8wb_fixed:
2640 case ARM_VST1d16wb_fixed:
2641 case ARM_VST1d32wb_fixed:
2642 case ARM_VST1d64wb_fixed:
2643 case ARM_VST1d8wb_register:
2644 case ARM_VST1d16wb_register:
2645 case ARM_VST1d32wb_register:
2646 case ARM_VST1d64wb_register:
2647 case ARM_VST1q8wb_fixed:
2648 case ARM_VST1q16wb_fixed:
2649 case ARM_VST1q32wb_fixed:
2650 case ARM_VST1q64wb_fixed:
2651 case ARM_VST1q8wb_register:
2652 case ARM_VST1q16wb_register:
2653 case ARM_VST1q32wb_register:
2654 case ARM_VST1q64wb_register:
2655 case ARM_VST1d8Twb_fixed:
2656 case ARM_VST1d16Twb_fixed:
2657 case ARM_VST1d32Twb_fixed:
2658 case ARM_VST1d64Twb_fixed:
2659 case ARM_VST1d8Twb_register:
2660 case ARM_VST1d16Twb_register:
2661 case ARM_VST1d32Twb_register:
2662 case ARM_VST1d64Twb_register:
2663 case ARM_VST1d8Qwb_fixed:
2664 case ARM_VST1d16Qwb_fixed:
2665 case ARM_VST1d32Qwb_fixed:
2666 case ARM_VST1d64Qwb_fixed:
2667 case ARM_VST1d8Qwb_register:
2668 case ARM_VST1d16Qwb_register:
2669 case ARM_VST1d32Qwb_register:
2670 case ARM_VST1d64Qwb_register:
2671 case ARM_VST2d8wb_fixed:
2672 case ARM_VST2d16wb_fixed:
2673 case ARM_VST2d32wb_fixed:
2674 case ARM_VST2d8wb_register:
2675 case ARM_VST2d16wb_register:
2676 case ARM_VST2d32wb_register:
2677 case ARM_VST2q8wb_fixed:
2678 case ARM_VST2q16wb_fixed:
2679 case ARM_VST2q32wb_fixed:
2680 case ARM_VST2q8wb_register:
2681 case ARM_VST2q16wb_register:
2682 case ARM_VST2q32wb_register:
2683 case ARM_VST2b8wb_fixed:
2684 case ARM_VST2b16wb_fixed:
2685 case ARM_VST2b32wb_fixed:
2686 case ARM_VST2b8wb_register:
2687 case ARM_VST2b16wb_register:
2688 case ARM_VST2b32wb_register:
2689 if (Rm == 0xF)
2690 return MCDisassembler_Fail;
2691 MCOperand_CreateImm0(Inst, 0);
2692 break;
2693 case ARM_VST3d8_UPD:
2694 case ARM_VST3d16_UPD:
2695 case ARM_VST3d32_UPD:
2696 case ARM_VST3q8_UPD:
2697 case ARM_VST3q16_UPD:
2698 case ARM_VST3q32_UPD:
2699 case ARM_VST4d8_UPD:
2700 case ARM_VST4d16_UPD:
2701 case ARM_VST4d32_UPD:
2702 case ARM_VST4q8_UPD:
2703 case ARM_VST4q16_UPD:
2704 case ARM_VST4q32_UPD:
2705 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2706 return MCDisassembler_Fail;
2707 break;
2708 default:
2709 break;
2710 }
2711
2712 // AddrMode6 Base (register+alignment)
2713 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2714 return MCDisassembler_Fail;
2715
2716 // AddrMode6 Offset (register)
2717 switch (MCInst_getOpcode(Inst)) {
2718 default:
2719 if (Rm == 0xD)
2720 MCOperand_CreateReg0(Inst, 0);
2721 else if (Rm != 0xF) {
2722 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2723 return MCDisassembler_Fail;
2724 }
2725 break;
2726 case ARM_VST1d8wb_fixed:
2727 case ARM_VST1d16wb_fixed:
2728 case ARM_VST1d32wb_fixed:
2729 case ARM_VST1d64wb_fixed:
2730 case ARM_VST1q8wb_fixed:
2731 case ARM_VST1q16wb_fixed:
2732 case ARM_VST1q32wb_fixed:
2733 case ARM_VST1q64wb_fixed:
2734 case ARM_VST1d8Twb_fixed:
2735 case ARM_VST1d16Twb_fixed:
2736 case ARM_VST1d32Twb_fixed:
2737 case ARM_VST1d64Twb_fixed:
2738 case ARM_VST1d8Qwb_fixed:
2739 case ARM_VST1d16Qwb_fixed:
2740 case ARM_VST1d32Qwb_fixed:
2741 case ARM_VST1d64Qwb_fixed:
2742 case ARM_VST2d8wb_fixed:
2743 case ARM_VST2d16wb_fixed:
2744 case ARM_VST2d32wb_fixed:
2745 case ARM_VST2q8wb_fixed:
2746 case ARM_VST2q16wb_fixed:
2747 case ARM_VST2q32wb_fixed:
2748 case ARM_VST2b8wb_fixed:
2749 case ARM_VST2b16wb_fixed:
2750 case ARM_VST2b32wb_fixed:
2751 break;
2752 }
2753
2754
2755 // First input register
2756 switch (MCInst_getOpcode(Inst)) {
2757 case ARM_VST1q16:
2758 case ARM_VST1q32:
2759 case ARM_VST1q64:
2760 case ARM_VST1q8:
2761 case ARM_VST1q16wb_fixed:
2762 case ARM_VST1q16wb_register:
2763 case ARM_VST1q32wb_fixed:
2764 case ARM_VST1q32wb_register:
2765 case ARM_VST1q64wb_fixed:
2766 case ARM_VST1q64wb_register:
2767 case ARM_VST1q8wb_fixed:
2768 case ARM_VST1q8wb_register:
2769 case ARM_VST2d16:
2770 case ARM_VST2d32:
2771 case ARM_VST2d8:
2772 case ARM_VST2d16wb_fixed:
2773 case ARM_VST2d16wb_register:
2774 case ARM_VST2d32wb_fixed:
2775 case ARM_VST2d32wb_register:
2776 case ARM_VST2d8wb_fixed:
2777 case ARM_VST2d8wb_register:
2778 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2779 return MCDisassembler_Fail;
2780 break;
2781 case ARM_VST2b16:
2782 case ARM_VST2b32:
2783 case ARM_VST2b8:
2784 case ARM_VST2b16wb_fixed:
2785 case ARM_VST2b16wb_register:
2786 case ARM_VST2b32wb_fixed:
2787 case ARM_VST2b32wb_register:
2788 case ARM_VST2b8wb_fixed:
2789 case ARM_VST2b8wb_register:
2790 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2791 return MCDisassembler_Fail;
2792 break;
2793 default:
2794 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2795 return MCDisassembler_Fail;
2796 }
2797
2798 // Second input register
2799 switch (MCInst_getOpcode(Inst)) {
2800 case ARM_VST3d8:
2801 case ARM_VST3d16:
2802 case ARM_VST3d32:
2803 case ARM_VST3d8_UPD:
2804 case ARM_VST3d16_UPD:
2805 case ARM_VST3d32_UPD:
2806 case ARM_VST4d8:
2807 case ARM_VST4d16:
2808 case ARM_VST4d32:
2809 case ARM_VST4d8_UPD:
2810 case ARM_VST4d16_UPD:
2811 case ARM_VST4d32_UPD:
2812 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2813 return MCDisassembler_Fail;
2814 break;
2815 case ARM_VST3q8:
2816 case ARM_VST3q16:
2817 case ARM_VST3q32:
2818 case ARM_VST3q8_UPD:
2819 case ARM_VST3q16_UPD:
2820 case ARM_VST3q32_UPD:
2821 case ARM_VST4q8:
2822 case ARM_VST4q16:
2823 case ARM_VST4q32:
2824 case ARM_VST4q8_UPD:
2825 case ARM_VST4q16_UPD:
2826 case ARM_VST4q32_UPD:
2827 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2828 return MCDisassembler_Fail;
2829 break;
2830 default:
2831 break;
2832 }
2833
2834 // Third input register
2835 switch (MCInst_getOpcode(Inst)) {
2836 case ARM_VST3d8:
2837 case ARM_VST3d16:
2838 case ARM_VST3d32:
2839 case ARM_VST3d8_UPD:
2840 case ARM_VST3d16_UPD:
2841 case ARM_VST3d32_UPD:
2842 case ARM_VST4d8:
2843 case ARM_VST4d16:
2844 case ARM_VST4d32:
2845 case ARM_VST4d8_UPD:
2846 case ARM_VST4d16_UPD:
2847 case ARM_VST4d32_UPD:
2848 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2849 return MCDisassembler_Fail;
2850 break;
2851 case ARM_VST3q8:
2852 case ARM_VST3q16:
2853 case ARM_VST3q32:
2854 case ARM_VST3q8_UPD:
2855 case ARM_VST3q16_UPD:
2856 case ARM_VST3q32_UPD:
2857 case ARM_VST4q8:
2858 case ARM_VST4q16:
2859 case ARM_VST4q32:
2860 case ARM_VST4q8_UPD:
2861 case ARM_VST4q16_UPD:
2862 case ARM_VST4q32_UPD:
2863 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2864 return MCDisassembler_Fail;
2865 break;
2866 default:
2867 break;
2868 }
2869
2870 // Fourth input register
2871 switch (MCInst_getOpcode(Inst)) {
2872 case ARM_VST4d8:
2873 case ARM_VST4d16:
2874 case ARM_VST4d32:
2875 case ARM_VST4d8_UPD:
2876 case ARM_VST4d16_UPD:
2877 case ARM_VST4d32_UPD:
2878 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2879 return MCDisassembler_Fail;
2880 break;
2881 case ARM_VST4q8:
2882 case ARM_VST4q16:
2883 case ARM_VST4q32:
2884 case ARM_VST4q8_UPD:
2885 case ARM_VST4q16_UPD:
2886 case ARM_VST4q32_UPD:
2887 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2888 return MCDisassembler_Fail;
2889 break;
2890 default:
2891 break;
2892 }
2893
2894 return S;
2895 }
2896
DecodeVLD1DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2897 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
2898 uint64_t Address, const void *Decoder)
2899 {
2900 DecodeStatus S = MCDisassembler_Success;
2901 unsigned Rn, Rm, align, size;
2902 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2903 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2904 Rn = fieldFromInstruction_4(Insn, 16, 4);
2905 Rm = fieldFromInstruction_4(Insn, 0, 4);
2906 align = fieldFromInstruction_4(Insn, 4, 1);
2907 size = fieldFromInstruction_4(Insn, 6, 2);
2908
2909 if (size == 0 && align == 1)
2910 return MCDisassembler_Fail;
2911 align *= (1 << size);
2912
2913 switch (MCInst_getOpcode(Inst)) {
2914 case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8:
2915 case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register:
2916 case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register:
2917 case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register:
2918 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2919 return MCDisassembler_Fail;
2920 break;
2921 default:
2922 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2923 return MCDisassembler_Fail;
2924 break;
2925 }
2926 if (Rm != 0xF) {
2927 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2928 return MCDisassembler_Fail;
2929 }
2930
2931 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2932 return MCDisassembler_Fail;
2933 MCOperand_CreateImm0(Inst, align);
2934
2935 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2936 // variant encodes Rm == 0xf. Anything else is a register offset post-
2937 // increment and we need to add the register operand to the instruction.
2938 if (Rm != 0xD && Rm != 0xF &&
2939 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2940 return MCDisassembler_Fail;
2941
2942 return S;
2943 }
2944
DecodeVLD2DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2945 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
2946 uint64_t Address, const void *Decoder)
2947 {
2948 DecodeStatus S = MCDisassembler_Success;
2949 unsigned Rn, Rm, align, size;
2950 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2951 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2952 Rn = fieldFromInstruction_4(Insn, 16, 4);
2953 Rm = fieldFromInstruction_4(Insn, 0, 4);
2954 align = fieldFromInstruction_4(Insn, 4, 1);
2955 size = 1 << fieldFromInstruction_4(Insn, 6, 2);
2956 align *= 2*size;
2957
2958 switch (MCInst_getOpcode(Inst)) {
2959 case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8:
2960 case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register:
2961 case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register:
2962 case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register:
2963 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2964 return MCDisassembler_Fail;
2965 break;
2966 case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2:
2967 case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register:
2968 case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register:
2969 case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register:
2970 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2971 return MCDisassembler_Fail;
2972 break;
2973 default:
2974 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2975 return MCDisassembler_Fail;
2976 break;
2977 }
2978
2979 if (Rm != 0xF)
2980 MCOperand_CreateImm0(Inst, 0);
2981
2982 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2983 return MCDisassembler_Fail;
2984 MCOperand_CreateImm0(Inst, align);
2985
2986 if (Rm != 0xD && Rm != 0xF) {
2987 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2988 return MCDisassembler_Fail;
2989 }
2990
2991 return S;
2992 }
2993
DecodeVLD3DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2994 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
2995 uint64_t Address, const void *Decoder)
2996 {
2997 DecodeStatus S = MCDisassembler_Success;
2998 unsigned Rn, Rm, inc;
2999 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3000 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3001 Rn = fieldFromInstruction_4(Insn, 16, 4);
3002 Rm = fieldFromInstruction_4(Insn, 0, 4);
3003 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3004
3005 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3006 return MCDisassembler_Fail;
3007 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3008 return MCDisassembler_Fail;
3009 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3010 return MCDisassembler_Fail;
3011 if (Rm != 0xF) {
3012 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3013 return MCDisassembler_Fail;
3014 }
3015
3016 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3017 return MCDisassembler_Fail;
3018 MCOperand_CreateImm0(Inst, 0);
3019
3020 if (Rm == 0xD)
3021 MCOperand_CreateReg0(Inst, 0);
3022 else if (Rm != 0xF) {
3023 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3024 return MCDisassembler_Fail;
3025 }
3026
3027 return S;
3028 }
3029
DecodeVLD4DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3030 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
3031 uint64_t Address, const void *Decoder)
3032 {
3033 DecodeStatus S = MCDisassembler_Success;
3034 unsigned Rn, Rm, size, inc, align;
3035 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3036 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3037 Rn = fieldFromInstruction_4(Insn, 16, 4);
3038 Rm = fieldFromInstruction_4(Insn, 0, 4);
3039 size = fieldFromInstruction_4(Insn, 6, 2);
3040 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3041 align = fieldFromInstruction_4(Insn, 4, 1);
3042
3043 if (size == 0x3) {
3044 if (align == 0)
3045 return MCDisassembler_Fail;
3046 align = 16;
3047 } else {
3048 if (size == 2) {
3049 align *= 8;
3050 } else {
3051 size = 1 << size;
3052 align *= 4 * size;
3053 }
3054 }
3055
3056 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3057 return MCDisassembler_Fail;
3058 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3059 return MCDisassembler_Fail;
3060 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3061 return MCDisassembler_Fail;
3062 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3063 return MCDisassembler_Fail;
3064 if (Rm != 0xF) {
3065 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3066 return MCDisassembler_Fail;
3067 }
3068
3069 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3070 return MCDisassembler_Fail;
3071 MCOperand_CreateImm0(Inst, align);
3072
3073 if (Rm == 0xD)
3074 MCOperand_CreateReg0(Inst, 0);
3075 else if (Rm != 0xF) {
3076 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3077 return MCDisassembler_Fail;
3078 }
3079
3080 return S;
3081 }
3082
DecodeNEONModImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3083 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
3084 uint64_t Address, const void *Decoder)
3085 {
3086 DecodeStatus S = MCDisassembler_Success;
3087 unsigned imm, Q;
3088 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3089 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3090 imm = fieldFromInstruction_4(Insn, 0, 4);
3091 imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
3092 imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
3093 imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
3094 imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
3095 Q = fieldFromInstruction_4(Insn, 6, 1);
3096
3097 if (Q) {
3098 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3099 return MCDisassembler_Fail;
3100 } else {
3101 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3102 return MCDisassembler_Fail;
3103 }
3104
3105 MCOperand_CreateImm0(Inst, imm);
3106
3107 switch (MCInst_getOpcode(Inst)) {
3108 case ARM_VORRiv4i16:
3109 case ARM_VORRiv2i32:
3110 case ARM_VBICiv4i16:
3111 case ARM_VBICiv2i32:
3112 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3113 return MCDisassembler_Fail;
3114 break;
3115 case ARM_VORRiv8i16:
3116 case ARM_VORRiv4i32:
3117 case ARM_VBICiv8i16:
3118 case ARM_VBICiv4i32:
3119 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3120 return MCDisassembler_Fail;
3121 break;
3122 default:
3123 break;
3124 }
3125
3126 return S;
3127 }
3128
DecodeVSHLMaxInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3129 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
3130 uint64_t Address, const void *Decoder)
3131 {
3132 DecodeStatus S = MCDisassembler_Success;
3133 unsigned Rm, size;
3134 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3135 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3136 Rm = fieldFromInstruction_4(Insn, 0, 4);
3137 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3138 size = fieldFromInstruction_4(Insn, 18, 2);
3139
3140 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3141 return MCDisassembler_Fail;
3142 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3143 return MCDisassembler_Fail;
3144 MCOperand_CreateImm0(Inst, 8 << size);
3145
3146 return S;
3147 }
3148
DecodeShiftRight8Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3149 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
3150 uint64_t Address, const void *Decoder)
3151 {
3152 MCOperand_CreateImm0(Inst, 8 - Val);
3153 return MCDisassembler_Success;
3154 }
3155
DecodeShiftRight16Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3156 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
3157 uint64_t Address, const void *Decoder)
3158 {
3159 MCOperand_CreateImm0(Inst, 16 - Val);
3160 return MCDisassembler_Success;
3161 }
3162
DecodeShiftRight32Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3163 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
3164 uint64_t Address, const void *Decoder)
3165 {
3166 MCOperand_CreateImm0(Inst, 32 - Val);
3167 return MCDisassembler_Success;
3168 }
3169
DecodeShiftRight64Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3170 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
3171 uint64_t Address, const void *Decoder)
3172 {
3173 MCOperand_CreateImm0(Inst, 64 - Val);
3174 return MCDisassembler_Success;
3175 }
3176
DecodeTBLInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3177 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
3178 uint64_t Address, const void *Decoder)
3179 {
3180 DecodeStatus S = MCDisassembler_Success;
3181 unsigned Rn, Rm, op;
3182 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3183 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3184 Rn = fieldFromInstruction_4(Insn, 16, 4);
3185 Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
3186 Rm = fieldFromInstruction_4(Insn, 0, 4);
3187 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3188 op = fieldFromInstruction_4(Insn, 6, 1);
3189
3190 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3191 return MCDisassembler_Fail;
3192 if (op) {
3193 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3194 return MCDisassembler_Fail; // Writeback
3195 }
3196
3197 switch (MCInst_getOpcode(Inst)) {
3198 case ARM_VTBL2:
3199 case ARM_VTBX2:
3200 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3201 return MCDisassembler_Fail;
3202 break;
3203 default:
3204 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3205 return MCDisassembler_Fail;
3206 }
3207
3208 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3209 return MCDisassembler_Fail;
3210
3211 return S;
3212 }
3213
DecodeThumbAddSpecialReg(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3214 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
3215 uint64_t Address, const void *Decoder)
3216 {
3217 DecodeStatus S = MCDisassembler_Success;
3218
3219 unsigned dst = fieldFromInstruction_2(Insn, 8, 3);
3220 unsigned imm = fieldFromInstruction_2(Insn, 0, 8);
3221
3222 if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3223 return MCDisassembler_Fail;
3224
3225 switch(MCInst_getOpcode(Inst)) {
3226 default:
3227 return MCDisassembler_Fail;
3228 case ARM_tADR:
3229 break; // tADR does not explicitly represent the PC as an operand.
3230 case ARM_tADDrSPi:
3231 MCOperand_CreateReg0(Inst, ARM_SP);
3232 break;
3233 }
3234
3235 MCOperand_CreateImm0(Inst, imm);
3236 return S;
3237 }
3238
DecodeThumbBROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3239 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
3240 uint64_t Address, const void *Decoder)
3241 {
3242 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12));
3243 return MCDisassembler_Success;
3244 }
3245
DecodeT2BROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3246 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
3247 uint64_t Address, const void *Decoder)
3248 {
3249 MCOperand_CreateImm0(Inst, SignExtend32(Val, 21));
3250 return MCDisassembler_Success;
3251 }
3252
DecodeThumbCmpBROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3253 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
3254 uint64_t Address, const void *Decoder)
3255 {
3256 MCOperand_CreateImm0(Inst, Val << 1);
3257 return MCDisassembler_Success;
3258 }
3259
DecodeThumbAddrModeRR(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3260 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
3261 uint64_t Address, const void *Decoder)
3262 {
3263 DecodeStatus S = MCDisassembler_Success;
3264
3265 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3266 unsigned Rm = fieldFromInstruction_4(Val, 3, 3);
3267
3268 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3269 return MCDisassembler_Fail;
3270 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3271 return MCDisassembler_Fail;
3272
3273 return S;
3274 }
3275
DecodeThumbAddrModeIS(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3276 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
3277 uint64_t Address, const void *Decoder)
3278 {
3279 DecodeStatus S = MCDisassembler_Success;
3280
3281 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3282 unsigned imm = fieldFromInstruction_4(Val, 3, 5);
3283
3284 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3285 return MCDisassembler_Fail;
3286 MCOperand_CreateImm0(Inst, imm);
3287
3288 return S;
3289 }
3290
DecodeThumbAddrModePC(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3291 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
3292 uint64_t Address, const void *Decoder)
3293 {
3294 unsigned imm = Val << 2;
3295
3296 MCOperand_CreateImm0(Inst, imm);
3297 //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3298
3299 return MCDisassembler_Success;
3300 }
3301
DecodeThumbAddrModeSP(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3302 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
3303 uint64_t Address, const void *Decoder)
3304 {
3305 MCOperand_CreateReg0(Inst, ARM_SP);
3306 MCOperand_CreateImm0(Inst, Val);
3307
3308 return MCDisassembler_Success;
3309 }
3310
DecodeT2AddrModeSOReg(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3311 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
3312 uint64_t Address, const void *Decoder)
3313 {
3314 DecodeStatus S = MCDisassembler_Success;
3315
3316 unsigned Rn = fieldFromInstruction_4(Val, 6, 4);
3317 unsigned Rm = fieldFromInstruction_4(Val, 2, 4);
3318 unsigned imm = fieldFromInstruction_4(Val, 0, 2);
3319
3320 // Thumb stores cannot use PC as dest register.
3321 switch (MCInst_getOpcode(Inst)) {
3322 case ARM_t2STRHs:
3323 case ARM_t2STRBs:
3324 case ARM_t2STRs:
3325 if (Rn == 15)
3326 return MCDisassembler_Fail;
3327 default:
3328 break;
3329 }
3330
3331 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler_Fail;
3333 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3334 return MCDisassembler_Fail;
3335 MCOperand_CreateImm0(Inst, imm);
3336
3337 return S;
3338 }
3339
DecodeT2LoadShift(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3340 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
3341 uint64_t Address, const void *Decoder)
3342 {
3343 DecodeStatus S = MCDisassembler_Success;
3344 unsigned addrmode;
3345 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3346 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3347 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3348 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3349 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3350
3351 if (Rn == 15) {
3352 switch (MCInst_getOpcode(Inst)) {
3353 case ARM_t2LDRBs:
3354 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3355 break;
3356 case ARM_t2LDRHs:
3357 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3358 break;
3359 case ARM_t2LDRSHs:
3360 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3361 break;
3362 case ARM_t2LDRSBs:
3363 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3364 break;
3365 case ARM_t2LDRs:
3366 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3367 break;
3368 case ARM_t2PLDs:
3369 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3370 break;
3371 case ARM_t2PLIs:
3372 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3373 break;
3374 default:
3375 return MCDisassembler_Fail;
3376 }
3377
3378 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3379 }
3380
3381 if (Rt == 15) {
3382 switch (MCInst_getOpcode(Inst)) {
3383 case ARM_t2LDRSHs:
3384 return MCDisassembler_Fail;
3385 case ARM_t2LDRHs:
3386 MCInst_setOpcode(Inst, ARM_t2PLDWs);
3387 break;
3388 case ARM_t2LDRSBs:
3389 MCInst_setOpcode(Inst, ARM_t2PLIs);
3390 default:
3391 break;
3392 }
3393 }
3394
3395 switch (MCInst_getOpcode(Inst)) {
3396 case ARM_t2PLDs:
3397 break;
3398 case ARM_t2PLIs:
3399 if (!hasV7Ops)
3400 return MCDisassembler_Fail;
3401 break;
3402 case ARM_t2PLDWs:
3403 if (!hasV7Ops || !hasMP)
3404 return MCDisassembler_Fail;
3405 break;
3406 default:
3407 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3408 return MCDisassembler_Fail;
3409 }
3410
3411 addrmode = fieldFromInstruction_4(Insn, 4, 2);
3412 addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
3413 addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
3414 if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3415 return MCDisassembler_Fail;
3416
3417 return S;
3418 }
3419
DecodeT2LoadImm8(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3420 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
3421 uint64_t Address, const void* Decoder)
3422 {
3423 DecodeStatus S = MCDisassembler_Success;
3424
3425 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3426 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3427 unsigned U = fieldFromInstruction_4(Insn, 9, 1);
3428 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3429 unsigned add = fieldFromInstruction_4(Insn, 9, 1);
3430
3431 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3432 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3433 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3434
3435 imm |= (U << 8);
3436 imm |= (Rn << 9);
3437 if (Rn == 15) {
3438 switch (MCInst_getOpcode(Inst)) {
3439 case ARM_t2LDRi8:
3440 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3441 break;
3442 case ARM_t2LDRBi8:
3443 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3444 break;
3445 case ARM_t2LDRSBi8:
3446 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3447 break;
3448 case ARM_t2LDRHi8:
3449 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3450 break;
3451 case ARM_t2LDRSHi8:
3452 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3453 break;
3454 case ARM_t2PLDi8:
3455 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3456 break;
3457 case ARM_t2PLIi8:
3458 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3459 break;
3460 default:
3461 return MCDisassembler_Fail;
3462 }
3463 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3464 }
3465
3466 if (Rt == 15) {
3467 switch (MCInst_getOpcode(Inst)) {
3468 case ARM_t2LDRSHi8:
3469 return MCDisassembler_Fail;
3470 case ARM_t2LDRHi8:
3471 if (!add)
3472 MCInst_setOpcode(Inst, ARM_t2PLDWi8);
3473 break;
3474 case ARM_t2LDRSBi8:
3475 MCInst_setOpcode(Inst, ARM_t2PLIi8);
3476 break;
3477 default:
3478 break;
3479 }
3480 }
3481
3482 switch (MCInst_getOpcode(Inst)) {
3483 case ARM_t2PLDi8:
3484 break;
3485 case ARM_t2PLIi8:
3486 if (!hasV7Ops)
3487 return MCDisassembler_Fail;
3488 break;
3489 case ARM_t2PLDWi8:
3490 if (!hasV7Ops || !hasMP)
3491 return MCDisassembler_Fail;
3492 break;
3493 default:
3494 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3495 return MCDisassembler_Fail;
3496 }
3497
3498 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3499 return MCDisassembler_Fail;
3500 return S;
3501 }
3502
DecodeT2LoadImm12(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3503 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
3504 uint64_t Address, const void* Decoder)
3505 {
3506 DecodeStatus S = MCDisassembler_Success;
3507
3508 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3509 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3510 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
3511 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3512 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3513 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3514
3515 imm |= (Rn << 13);
3516
3517 if (Rn == 15) {
3518 switch (MCInst_getOpcode(Inst)) {
3519 case ARM_t2LDRi12:
3520 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3521 break;
3522 case ARM_t2LDRHi12:
3523 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3524 break;
3525 case ARM_t2LDRSHi12:
3526 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3527 break;
3528 case ARM_t2LDRBi12:
3529 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3530 break;
3531 case ARM_t2LDRSBi12:
3532 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3533 break;
3534 case ARM_t2PLDi12:
3535 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3536 break;
3537 case ARM_t2PLIi12:
3538 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3539 break;
3540 default:
3541 return MCDisassembler_Fail;
3542 }
3543 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3544 }
3545
3546 if (Rt == 15) {
3547 switch (MCInst_getOpcode(Inst)) {
3548 case ARM_t2LDRSHi12:
3549 return MCDisassembler_Fail;
3550 case ARM_t2LDRHi12:
3551 MCInst_setOpcode(Inst, ARM_t2PLDWi12);
3552 break;
3553 case ARM_t2LDRSBi12:
3554 MCInst_setOpcode(Inst, ARM_t2PLIi12);
3555 break;
3556 default:
3557 break;
3558 }
3559 }
3560
3561 switch (MCInst_getOpcode(Inst)) {
3562 case ARM_t2PLDi12:
3563 break;
3564 case ARM_t2PLIi12:
3565 if (!hasV7Ops)
3566 return MCDisassembler_Fail;
3567 break;
3568 case ARM_t2PLDWi12:
3569 if (!hasV7Ops || !hasMP)
3570 return MCDisassembler_Fail;
3571 break;
3572 default:
3573 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3574 return MCDisassembler_Fail;
3575 }
3576
3577 if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3578 return MCDisassembler_Fail;
3579 return S;
3580 }
3581
DecodeT2LoadT(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3582 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
3583 uint64_t Address, const void* Decoder)
3584 {
3585 DecodeStatus S = MCDisassembler_Success;
3586
3587 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3588 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3589 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3590 imm |= (Rn << 9);
3591
3592 if (Rn == 15) {
3593 switch (MCInst_getOpcode(Inst)) {
3594 case ARM_t2LDRT:
3595 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3596 break;
3597 case ARM_t2LDRBT:
3598 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3599 break;
3600 case ARM_t2LDRHT:
3601 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3602 break;
3603 case ARM_t2LDRSBT:
3604 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3605 break;
3606 case ARM_t2LDRSHT:
3607 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3608 break;
3609 default:
3610 return MCDisassembler_Fail;
3611 }
3612 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3613 }
3614
3615 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3616 return MCDisassembler_Fail;
3617 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3618 return MCDisassembler_Fail;
3619 return S;
3620 }
3621
DecodeT2LoadLabel(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3622 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
3623 uint64_t Address, const void* Decoder)
3624 {
3625 DecodeStatus S = MCDisassembler_Success;
3626
3627 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3628 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
3629 int imm = fieldFromInstruction_4(Insn, 0, 12);
3630 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3631 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3632
3633 if (Rt == 15) {
3634 switch (MCInst_getOpcode(Inst)) {
3635 case ARM_t2LDRBpci:
3636 case ARM_t2LDRHpci:
3637 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3638 break;
3639 case ARM_t2LDRSBpci:
3640 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3641 break;
3642 case ARM_t2LDRSHpci:
3643 return MCDisassembler_Fail;
3644 default:
3645 break;
3646 }
3647 }
3648
3649 switch(MCInst_getOpcode(Inst)) {
3650 case ARM_t2PLDpci:
3651 break;
3652 case ARM_t2PLIpci:
3653 if (!hasV7Ops)
3654 return MCDisassembler_Fail;
3655 break;
3656 default:
3657 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3658 return MCDisassembler_Fail;
3659 }
3660
3661 if (!U) {
3662 // Special case for #-0.
3663 if (imm == 0)
3664 imm = INT32_MIN;
3665 else
3666 imm = -imm;
3667 }
3668 MCOperand_CreateImm0(Inst, imm);
3669
3670 return S;
3671 }
3672
DecodeT2Imm8S4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3673 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
3674 uint64_t Address, const void *Decoder)
3675 {
3676 if (Val == 0)
3677 MCOperand_CreateImm0(Inst, INT32_MIN);
3678 else {
3679 int imm = Val & 0xFF;
3680
3681 if (!(Val & 0x100)) imm *= -1;
3682 MCOperand_CreateImm0(Inst, imm * 4);
3683 }
3684
3685 return MCDisassembler_Success;
3686 }
3687
DecodeT2AddrModeImm8s4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3688 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
3689 uint64_t Address, const void *Decoder)
3690 {
3691 DecodeStatus S = MCDisassembler_Success;
3692
3693 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3694 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3695
3696 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3697 return MCDisassembler_Fail;
3698 if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3699 return MCDisassembler_Fail;
3700
3701 return S;
3702 }
3703
DecodeT2AddrModeImm0_1020s4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3704 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
3705 uint64_t Address, const void *Decoder)
3706 {
3707 DecodeStatus S = MCDisassembler_Success;
3708
3709 unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
3710 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
3711
3712 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3713 return MCDisassembler_Fail;
3714
3715 MCOperand_CreateImm0(Inst, imm);
3716
3717 return S;
3718 }
3719
DecodeT2Imm8(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3720 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
3721 uint64_t Address, const void *Decoder)
3722 {
3723 int imm = Val & 0xFF;
3724 if (Val == 0)
3725 imm = INT32_MIN;
3726 else if (!(Val & 0x100))
3727 imm *= -1;
3728 MCOperand_CreateImm0(Inst, imm);
3729
3730 return MCDisassembler_Success;
3731 }
3732
DecodeT2AddrModeImm8(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3733 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
3734 uint64_t Address, const void *Decoder)
3735 {
3736 DecodeStatus S = MCDisassembler_Success;
3737
3738 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3739 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3740
3741 // Thumb stores cannot use PC as dest register.
3742 switch (MCInst_getOpcode(Inst)) {
3743 case ARM_t2STRT:
3744 case ARM_t2STRBT:
3745 case ARM_t2STRHT:
3746 case ARM_t2STRi8:
3747 case ARM_t2STRHi8:
3748 case ARM_t2STRBi8:
3749 if (Rn == 15)
3750 return MCDisassembler_Fail;
3751 break;
3752 default:
3753 break;
3754 }
3755
3756 // Some instructions always use an additive offset.
3757 switch (MCInst_getOpcode(Inst)) {
3758 case ARM_t2LDRT:
3759 case ARM_t2LDRBT:
3760 case ARM_t2LDRHT:
3761 case ARM_t2LDRSBT:
3762 case ARM_t2LDRSHT:
3763 case ARM_t2STRT:
3764 case ARM_t2STRBT:
3765 case ARM_t2STRHT:
3766 imm |= 0x100;
3767 break;
3768 default:
3769 break;
3770 }
3771
3772 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3773 return MCDisassembler_Fail;
3774 if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3775 return MCDisassembler_Fail;
3776
3777 return S;
3778 }
3779
DecodeT2LdStPre(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3780 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
3781 uint64_t Address, const void *Decoder)
3782 {
3783 DecodeStatus S = MCDisassembler_Success;
3784 unsigned load;
3785 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3786 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3787 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
3788 addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
3789 addr |= Rn << 9;
3790 load = fieldFromInstruction_4(Insn, 20, 1);
3791
3792 if (Rn == 15) {
3793 switch (MCInst_getOpcode(Inst)) {
3794 case ARM_t2LDR_PRE:
3795 case ARM_t2LDR_POST:
3796 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3797 break;
3798 case ARM_t2LDRB_PRE:
3799 case ARM_t2LDRB_POST:
3800 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3801 break;
3802 case ARM_t2LDRH_PRE:
3803 case ARM_t2LDRH_POST:
3804 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3805 break;
3806 case ARM_t2LDRSB_PRE:
3807 case ARM_t2LDRSB_POST:
3808 if (Rt == 15)
3809 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3810 else
3811 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3812 break;
3813 case ARM_t2LDRSH_PRE:
3814 case ARM_t2LDRSH_POST:
3815 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3816 break;
3817 default:
3818 return MCDisassembler_Fail;
3819 }
3820 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3821 }
3822
3823 if (!load) {
3824 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3825 return MCDisassembler_Fail;
3826 }
3827
3828 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3829 return MCDisassembler_Fail;
3830
3831 if (load) {
3832 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3833 return MCDisassembler_Fail;
3834 }
3835
3836 if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3837 return MCDisassembler_Fail;
3838
3839 return S;
3840 }
3841
DecodeT2AddrModeImm12(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3842 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
3843 uint64_t Address, const void *Decoder)
3844 {
3845 DecodeStatus S = MCDisassembler_Success;
3846
3847 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
3848 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
3849
3850 // Thumb stores cannot use PC as dest register.
3851 switch (MCInst_getOpcode(Inst)) {
3852 case ARM_t2STRi12:
3853 case ARM_t2STRBi12:
3854 case ARM_t2STRHi12:
3855 if (Rn == 15)
3856 return MCDisassembler_Fail;
3857 default:
3858 break;
3859 }
3860
3861 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3862 return MCDisassembler_Fail;
3863 MCOperand_CreateImm0(Inst, imm);
3864
3865 return S;
3866 }
3867
DecodeThumbAddSPImm(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3868 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn,
3869 uint64_t Address, const void *Decoder)
3870 {
3871 unsigned imm = fieldFromInstruction_2(Insn, 0, 7);
3872
3873 MCOperand_CreateReg0(Inst, ARM_SP);
3874 MCOperand_CreateReg0(Inst, ARM_SP);
3875 MCOperand_CreateImm0(Inst, imm);
3876
3877 return MCDisassembler_Success;
3878 }
3879
DecodeThumbAddSPReg(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3880 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
3881 uint64_t Address, const void *Decoder)
3882 {
3883 DecodeStatus S = MCDisassembler_Success;
3884
3885 if (MCInst_getOpcode(Inst) == ARM_tADDrSP) {
3886 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3);
3887 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3;
3888
3889 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3890 return MCDisassembler_Fail;
3891 MCOperand_CreateReg0(Inst, ARM_SP);
3892 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3893 return MCDisassembler_Fail;
3894 } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) {
3895 unsigned Rm = fieldFromInstruction_2(Insn, 3, 4);
3896
3897 MCOperand_CreateReg0(Inst, ARM_SP);
3898 MCOperand_CreateReg0(Inst, ARM_SP);
3899 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3900 return MCDisassembler_Fail;
3901 }
3902
3903 return S;
3904 }
3905
DecodeThumbCPS(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3906 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
3907 uint64_t Address, const void *Decoder)
3908 {
3909 unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2;
3910 unsigned flags = fieldFromInstruction_2(Insn, 0, 3);
3911
3912 MCOperand_CreateImm0(Inst, imod);
3913 MCOperand_CreateImm0(Inst, flags);
3914
3915 return MCDisassembler_Success;
3916 }
3917
DecodePostIdxReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3918 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
3919 uint64_t Address, const void *Decoder)
3920 {
3921 DecodeStatus S = MCDisassembler_Success;
3922 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3923 unsigned add = fieldFromInstruction_4(Insn, 4, 1);
3924
3925 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3926 return MCDisassembler_Fail;
3927 MCOperand_CreateImm0(Inst, add);
3928
3929 return S;
3930 }
3931
DecodeThumbBLXOffset(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3932 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val,
3933 uint64_t Address, const void *Decoder)
3934 {
3935 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3936 // Note only one trailing zero not two. Also the J1 and J2 values are from
3937 // the encoded instruction. So here change to I1 and I2 values via:
3938 // I1 = NOT(J1 EOR S);
3939 // I2 = NOT(J2 EOR S);
3940 // and build the imm32 with two trailing zeros as documented:
3941 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3942 unsigned S = (Val >> 23) & 1;
3943 unsigned J1 = (Val >> 22) & 1;
3944 unsigned J2 = (Val >> 21) & 1;
3945 unsigned I1 = !(J1 ^ S);
3946 unsigned I2 = !(J2 ^ S);
3947 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3948 int imm32 = SignExtend32(tmp << 1, 25);
3949
3950 MCOperand_CreateImm0(Inst, imm32);
3951 return MCDisassembler_Success;
3952 }
3953
DecodeCoprocessor(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3954 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val,
3955 uint64_t Address, const void *Decoder)
3956 {
3957 if (Val == 0xA || Val == 0xB)
3958 return MCDisassembler_Fail;
3959
3960 MCOperand_CreateImm0(Inst, Val);
3961 return MCDisassembler_Success;
3962 }
3963
DecodeThumbTableBranch(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3964 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn,
3965 uint64_t Address, const void *Decoder)
3966 {
3967 DecodeStatus S = MCDisassembler_Success;
3968
3969 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3970 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3971
3972 if (Rn == ARM_SP) S = MCDisassembler_SoftFail;
3973 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3974 return MCDisassembler_Fail;
3975 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3976 return MCDisassembler_Fail;
3977 return S;
3978 }
3979
DecodeThumb2BCCInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3980 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
3981 uint64_t Address, const void *Decoder)
3982 {
3983 DecodeStatus S = MCDisassembler_Success;
3984 unsigned brtarget;
3985 unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
3986 if (pred == 0xE || pred == 0xF) {
3987 unsigned imm;
3988 unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
3989 switch (opc) {
3990 default:
3991 return MCDisassembler_Fail;
3992 case 0xf3bf8f4:
3993 MCInst_setOpcode(Inst, ARM_t2DSB);
3994 break;
3995 case 0xf3bf8f5:
3996 MCInst_setOpcode(Inst, ARM_t2DMB);
3997 break;
3998 case 0xf3bf8f6:
3999 MCInst_setOpcode(Inst, ARM_t2ISB);
4000 break;
4001 }
4002
4003 imm = fieldFromInstruction_4(Insn, 0, 4);
4004 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4005 }
4006
4007 brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
4008 brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
4009 brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
4010 brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
4011 brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20;
4012
4013 if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4014 return MCDisassembler_Fail;
4015 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4016 return MCDisassembler_Fail;
4017
4018 return S;
4019 }
4020
4021 // Decode a shifted immediate operand. These basically consist
4022 // of an 8-bit value, and a 4-bit directive that specifies either
4023 // a splat operation or a rotation.
DecodeT2SOImm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4024 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
4025 uint64_t Address, const void *Decoder)
4026 {
4027 unsigned ctrl = fieldFromInstruction_4(Val, 10, 2);
4028 if (ctrl == 0) {
4029 unsigned byte = fieldFromInstruction_4(Val, 8, 2);
4030 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
4031 switch (byte) {
4032 case 0:
4033 MCOperand_CreateImm0(Inst, imm);
4034 break;
4035 case 1:
4036 MCOperand_CreateImm0(Inst, (imm << 16) | imm);
4037 break;
4038 case 2:
4039 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8));
4040 break;
4041 case 3:
4042 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm);
4043 break;
4044 }
4045 } else {
4046 unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80;
4047 unsigned rot = fieldFromInstruction_4(Val, 7, 5);
4048 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4049 MCOperand_CreateImm0(Inst, imm);
4050 }
4051
4052 return MCDisassembler_Success;
4053 }
4054
DecodeThumbBCCTargetOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4055 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
4056 uint64_t Address, const void *Decoder)
4057 {
4058 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9));
4059 return MCDisassembler_Success;
4060 }
4061
DecodeThumbBLTargetOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4062 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
4063 uint64_t Address, const void *Decoder)
4064 {
4065 // Val is passed in as S:J1:J2:imm10:imm11
4066 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4067 // the encoded instruction. So here change to I1 and I2 values via:
4068 // I1 = NOT(J1 EOR S);
4069 // I2 = NOT(J2 EOR S);
4070 // and build the imm32 with one trailing zero as documented:
4071 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4072 unsigned S = (Val >> 23) & 1;
4073 unsigned J1 = (Val >> 22) & 1;
4074 unsigned J2 = (Val >> 21) & 1;
4075 unsigned I1 = !(J1 ^ S);
4076 unsigned I2 = !(J2 ^ S);
4077 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4078 int imm32 = SignExtend32(tmp << 1, 25);
4079
4080 MCOperand_CreateImm0(Inst, imm32);
4081 return MCDisassembler_Success;
4082 }
4083
DecodeMemBarrierOption(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4084 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val,
4085 uint64_t Address, const void *Decoder)
4086 {
4087 if (Val & ~0xf)
4088 return MCDisassembler_Fail;
4089
4090 MCOperand_CreateImm0(Inst, Val);
4091 return MCDisassembler_Success;
4092 }
4093
DecodeInstSyncBarrierOption(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4094 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
4095 uint64_t Address, const void *Decoder)
4096 {
4097 if (Val & ~0xf)
4098 return MCDisassembler_Fail;
4099
4100 MCOperand_CreateImm0(Inst, Val);
4101 return MCDisassembler_Success;
4102 }
4103
DecodeMSRMask(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4104 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
4105 uint64_t Address, const void *Decoder)
4106 {
4107 DecodeStatus S = MCDisassembler_Success;
4108 uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode);
4109 if (FeatureBits & ARM_FeatureMClass) {
4110 unsigned ValLow = Val & 0xff;
4111
4112 // Validate the SYSm value first.
4113 switch (ValLow) {
4114 case 0: // apsr
4115 case 1: // iapsr
4116 case 2: // eapsr
4117 case 3: // xpsr
4118 case 5: // ipsr
4119 case 6: // epsr
4120 case 7: // iepsr
4121 case 8: // msp
4122 case 9: // psp
4123 case 16: // primask
4124 case 20: // control
4125 break;
4126 case 17: // basepri
4127 case 18: // basepri_max
4128 case 19: // faultmask
4129 if (!(FeatureBits & ARM_HasV7Ops))
4130 // Values basepri, basepri_max and faultmask are only valid for v7m.
4131 return MCDisassembler_Fail;
4132 break;
4133 default:
4134 return MCDisassembler_Fail;
4135 }
4136
4137 if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
4138 unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
4139 if (!(FeatureBits & ARM_HasV7Ops)) {
4140 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4141 // unpredictable.
4142 if (Mask != 2)
4143 S = MCDisassembler_SoftFail;
4144 }
4145 else {
4146 // The ARMv7-M architecture stores an additional 2-bit mask value in
4147 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4148 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4149 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4150 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4151 // only if the processor includes the DSP extension.
4152 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4153 (!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1)))
4154 S = MCDisassembler_SoftFail;
4155 }
4156 }
4157 } else {
4158 // A/R class
4159 if (Val == 0)
4160 return MCDisassembler_Fail;
4161 }
4162
4163 MCOperand_CreateImm0(Inst, Val);
4164 return S;
4165 }
4166
DecodeBankedReg(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4167 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val,
4168 uint64_t Address, const void *Decoder)
4169 {
4170
4171 unsigned R = fieldFromInstruction_4(Val, 5, 1);
4172 unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
4173
4174 // The table of encodings for these banked registers comes from B9.2.3 of the
4175 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4176 // neater. So by fiat, these values are UNPREDICTABLE:
4177 if (!R) {
4178 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4179 SysM == 0x1a || SysM == 0x1b)
4180 return MCDisassembler_SoftFail;
4181 } else {
4182 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4183 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4184 return MCDisassembler_SoftFail;
4185 }
4186
4187 MCOperand_CreateImm0(Inst, Val);
4188 return MCDisassembler_Success;
4189 }
4190
DecodeDoubleRegLoad(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4191 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
4192 uint64_t Address, const void *Decoder)
4193 {
4194 DecodeStatus S = MCDisassembler_Success;
4195
4196 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4197 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4198 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4199
4200 if (Rn == 0xF)
4201 S = MCDisassembler_SoftFail;
4202
4203 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4204 return MCDisassembler_Fail;
4205 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4206 return MCDisassembler_Fail;
4207 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4208 return MCDisassembler_Fail;
4209
4210 return S;
4211 }
4212
DecodeDoubleRegStore(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4213 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
4214 uint64_t Address, const void *Decoder)
4215 {
4216 DecodeStatus S = MCDisassembler_Success;
4217
4218 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4219 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
4220 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4221 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4222
4223 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4224 return MCDisassembler_Fail;
4225
4226 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4227 S = MCDisassembler_SoftFail;
4228
4229 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4230 return MCDisassembler_Fail;
4231 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4232 return MCDisassembler_Fail;
4233 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4234 return MCDisassembler_Fail;
4235
4236 return S;
4237 }
4238
DecodeLDRPreImm(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4239 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
4240 uint64_t Address, const void *Decoder)
4241 {
4242 DecodeStatus S = MCDisassembler_Success;
4243 unsigned pred;
4244 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4245 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4246 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4247 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4248 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4249 pred = fieldFromInstruction_4(Insn, 28, 4);
4250
4251 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4252
4253 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4254 return MCDisassembler_Fail;
4255 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4256 return MCDisassembler_Fail;
4257 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4258 return MCDisassembler_Fail;
4259 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4260 return MCDisassembler_Fail;
4261
4262 return S;
4263 }
4264
DecodeLDRPreReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4265 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
4266 uint64_t Address, const void *Decoder)
4267 {
4268 DecodeStatus S = MCDisassembler_Success;
4269 unsigned pred, Rm;
4270 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4271 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4272 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4273 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4274 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4275 pred = fieldFromInstruction_4(Insn, 28, 4);
4276 Rm = fieldFromInstruction_4(Insn, 0, 4);
4277
4278 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4279 if (Rm == 0xF) S = MCDisassembler_SoftFail;
4280
4281 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4282 return MCDisassembler_Fail;
4283 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4284 return MCDisassembler_Fail;
4285 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4286 return MCDisassembler_Fail;
4287 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4288 return MCDisassembler_Fail;
4289
4290 return S;
4291 }
4292
DecodeSTRPreImm(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4293 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
4294 uint64_t Address, const void *Decoder)
4295 {
4296 DecodeStatus S = MCDisassembler_Success;
4297 unsigned pred;
4298 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4299 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4300 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4301 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4302 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4303 pred = fieldFromInstruction_4(Insn, 28, 4);
4304
4305 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4306
4307 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4308 return MCDisassembler_Fail;
4309 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4310 return MCDisassembler_Fail;
4311 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4312 return MCDisassembler_Fail;
4313 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4314 return MCDisassembler_Fail;
4315
4316 return S;
4317 }
4318
DecodeSTRPreReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4319 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
4320 uint64_t Address, const void *Decoder)
4321 {
4322 DecodeStatus S = MCDisassembler_Success;
4323 unsigned pred;
4324 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4325 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4326 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4327 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4328 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4329 pred = fieldFromInstruction_4(Insn, 28, 4);
4330
4331 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4332
4333 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4334 return MCDisassembler_Fail;
4335 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4336 return MCDisassembler_Fail;
4337 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4338 return MCDisassembler_Fail;
4339 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4340 return MCDisassembler_Fail;
4341
4342 return S;
4343 }
4344
DecodeVLD1LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4345 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
4346 uint64_t Address, const void *Decoder)
4347 {
4348 DecodeStatus S = MCDisassembler_Success;
4349 unsigned size, align = 0, index = 0;
4350 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4351 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4352 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4353 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4354 size = fieldFromInstruction_4(Insn, 10, 2);
4355
4356 switch (size) {
4357 default:
4358 return MCDisassembler_Fail;
4359 case 0:
4360 if (fieldFromInstruction_4(Insn, 4, 1))
4361 return MCDisassembler_Fail; // UNDEFINED
4362 index = fieldFromInstruction_4(Insn, 5, 3);
4363 break;
4364 case 1:
4365 if (fieldFromInstruction_4(Insn, 5, 1))
4366 return MCDisassembler_Fail; // UNDEFINED
4367 index = fieldFromInstruction_4(Insn, 6, 2);
4368 if (fieldFromInstruction_4(Insn, 4, 1))
4369 align = 2;
4370 break;
4371 case 2:
4372 if (fieldFromInstruction_4(Insn, 6, 1))
4373 return MCDisassembler_Fail; // UNDEFINED
4374 index = fieldFromInstruction_4(Insn, 7, 1);
4375
4376 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4377 case 0 :
4378 align = 0; break;
4379 case 3:
4380 align = 4; break;
4381 default:
4382 return MCDisassembler_Fail;
4383 }
4384 break;
4385 }
4386
4387 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4388 return MCDisassembler_Fail;
4389 if (Rm != 0xF) { // Writeback
4390 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4391 return MCDisassembler_Fail;
4392 }
4393 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4394 return MCDisassembler_Fail;
4395 MCOperand_CreateImm0(Inst, align);
4396 if (Rm != 0xF) {
4397 if (Rm != 0xD) {
4398 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4399 return MCDisassembler_Fail;
4400 } else
4401 MCOperand_CreateReg0(Inst, 0);
4402 }
4403
4404 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4405 return MCDisassembler_Fail;
4406 MCOperand_CreateImm0(Inst, index);
4407
4408 return S;
4409 }
4410
DecodeVST1LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4411 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
4412 uint64_t Address, const void *Decoder)
4413 {
4414 DecodeStatus S = MCDisassembler_Success;
4415 unsigned size, align = 0, index = 0;
4416 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4417 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4418 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4419 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4420 size = fieldFromInstruction_4(Insn, 10, 2);
4421
4422 switch (size) {
4423 default:
4424 return MCDisassembler_Fail;
4425 case 0:
4426 if (fieldFromInstruction_4(Insn, 4, 1))
4427 return MCDisassembler_Fail; // UNDEFINED
4428 index = fieldFromInstruction_4(Insn, 5, 3);
4429 break;
4430 case 1:
4431 if (fieldFromInstruction_4(Insn, 5, 1))
4432 return MCDisassembler_Fail; // UNDEFINED
4433 index = fieldFromInstruction_4(Insn, 6, 2);
4434 if (fieldFromInstruction_4(Insn, 4, 1))
4435 align = 2;
4436 break;
4437 case 2:
4438 if (fieldFromInstruction_4(Insn, 6, 1))
4439 return MCDisassembler_Fail; // UNDEFINED
4440 index = fieldFromInstruction_4(Insn, 7, 1);
4441
4442 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4443 case 0:
4444 align = 0; break;
4445 case 3:
4446 align = 4; break;
4447 default:
4448 return MCDisassembler_Fail;
4449 }
4450 break;
4451 }
4452
4453 if (Rm != 0xF) { // Writeback
4454 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4455 return MCDisassembler_Fail;
4456 }
4457 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4458 return MCDisassembler_Fail;
4459 MCOperand_CreateImm0(Inst, align);
4460 if (Rm != 0xF) {
4461 if (Rm != 0xD) {
4462 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4463 return MCDisassembler_Fail;
4464 } else
4465 MCOperand_CreateReg0(Inst, 0);
4466 }
4467
4468 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4469 return MCDisassembler_Fail;
4470 MCOperand_CreateImm0(Inst, index);
4471
4472 return S;
4473 }
4474
DecodeVLD2LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4475 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
4476 uint64_t Address, const void *Decoder)
4477 {
4478 DecodeStatus S = MCDisassembler_Success;
4479 unsigned size, align = 0, index = 0, inc = 1;
4480 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4481 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4482 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4483 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4484 size = fieldFromInstruction_4(Insn, 10, 2);
4485
4486 switch (size) {
4487 default:
4488 return MCDisassembler_Fail;
4489 case 0:
4490 index = fieldFromInstruction_4(Insn, 5, 3);
4491 if (fieldFromInstruction_4(Insn, 4, 1))
4492 align = 2;
4493 break;
4494 case 1:
4495 index = fieldFromInstruction_4(Insn, 6, 2);
4496 if (fieldFromInstruction_4(Insn, 4, 1))
4497 align = 4;
4498 if (fieldFromInstruction_4(Insn, 5, 1))
4499 inc = 2;
4500 break;
4501 case 2:
4502 if (fieldFromInstruction_4(Insn, 5, 1))
4503 return MCDisassembler_Fail; // UNDEFINED
4504 index = fieldFromInstruction_4(Insn, 7, 1);
4505 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4506 align = 8;
4507 if (fieldFromInstruction_4(Insn, 6, 1))
4508 inc = 2;
4509 break;
4510 }
4511
4512 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4513 return MCDisassembler_Fail;
4514 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4515 return MCDisassembler_Fail;
4516 if (Rm != 0xF) { // Writeback
4517 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4518 return MCDisassembler_Fail;
4519 }
4520 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4521 return MCDisassembler_Fail;
4522 MCOperand_CreateImm0(Inst, align);
4523 if (Rm != 0xF) {
4524 if (Rm != 0xD) {
4525 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4526 return MCDisassembler_Fail;
4527 } else
4528 MCOperand_CreateReg0(Inst, 0);
4529 }
4530
4531 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4532 return MCDisassembler_Fail;
4533 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4534 return MCDisassembler_Fail;
4535 MCOperand_CreateImm0(Inst, index);
4536
4537 return S;
4538 }
4539
DecodeVST2LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4540 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
4541 uint64_t Address, const void *Decoder)
4542 {
4543 DecodeStatus S = MCDisassembler_Success;
4544 unsigned size, align = 0, index = 0, inc = 1;
4545 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4546 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4547 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4548 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4549 size = fieldFromInstruction_4(Insn, 10, 2);
4550
4551 switch (size) {
4552 default:
4553 return MCDisassembler_Fail;
4554 case 0:
4555 index = fieldFromInstruction_4(Insn, 5, 3);
4556 if (fieldFromInstruction_4(Insn, 4, 1))
4557 align = 2;
4558 break;
4559 case 1:
4560 index = fieldFromInstruction_4(Insn, 6, 2);
4561 if (fieldFromInstruction_4(Insn, 4, 1))
4562 align = 4;
4563 if (fieldFromInstruction_4(Insn, 5, 1))
4564 inc = 2;
4565 break;
4566 case 2:
4567 if (fieldFromInstruction_4(Insn, 5, 1))
4568 return MCDisassembler_Fail; // UNDEFINED
4569 index = fieldFromInstruction_4(Insn, 7, 1);
4570 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4571 align = 8;
4572 if (fieldFromInstruction_4(Insn, 6, 1))
4573 inc = 2;
4574 break;
4575 }
4576
4577 if (Rm != 0xF) { // Writeback
4578 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 return MCDisassembler_Fail;
4580 }
4581 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4582 return MCDisassembler_Fail;
4583 MCOperand_CreateImm0(Inst, align);
4584 if (Rm != 0xF) {
4585 if (Rm != 0xD) {
4586 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4587 return MCDisassembler_Fail;
4588 } else
4589 MCOperand_CreateReg0(Inst, 0);
4590 }
4591
4592 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4593 return MCDisassembler_Fail;
4594 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4595 return MCDisassembler_Fail;
4596 MCOperand_CreateImm0(Inst, index);
4597
4598 return S;
4599 }
4600
DecodeVLD3LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4601 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
4602 uint64_t Address, const void *Decoder)
4603 {
4604 DecodeStatus S = MCDisassembler_Success;
4605 unsigned size, align = 0, index = 0, inc = 1;
4606 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4607 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4608 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4609 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4610 size = fieldFromInstruction_4(Insn, 10, 2);
4611
4612 switch (size) {
4613 default:
4614 return MCDisassembler_Fail;
4615 case 0:
4616 if (fieldFromInstruction_4(Insn, 4, 1))
4617 return MCDisassembler_Fail; // UNDEFINED
4618 index = fieldFromInstruction_4(Insn, 5, 3);
4619 break;
4620 case 1:
4621 if (fieldFromInstruction_4(Insn, 4, 1))
4622 return MCDisassembler_Fail; // UNDEFINED
4623 index = fieldFromInstruction_4(Insn, 6, 2);
4624 if (fieldFromInstruction_4(Insn, 5, 1))
4625 inc = 2;
4626 break;
4627 case 2:
4628 if (fieldFromInstruction_4(Insn, 4, 2))
4629 return MCDisassembler_Fail; // UNDEFINED
4630 index = fieldFromInstruction_4(Insn, 7, 1);
4631 if (fieldFromInstruction_4(Insn, 6, 1))
4632 inc = 2;
4633 break;
4634 }
4635
4636 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4637 return MCDisassembler_Fail;
4638 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4639 return MCDisassembler_Fail;
4640 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4641 return MCDisassembler_Fail;
4642
4643 if (Rm != 0xF) { // Writeback
4644 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4645 return MCDisassembler_Fail;
4646 }
4647 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4648 return MCDisassembler_Fail;
4649 MCOperand_CreateImm0(Inst, align);
4650 if (Rm != 0xF) {
4651 if (Rm != 0xD) {
4652 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4653 return MCDisassembler_Fail;
4654 } else
4655 MCOperand_CreateReg0(Inst, 0);
4656 }
4657
4658 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4659 return MCDisassembler_Fail;
4660 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4661 return MCDisassembler_Fail;
4662 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4663 return MCDisassembler_Fail;
4664 MCOperand_CreateImm0(Inst, index);
4665
4666 return S;
4667 }
4668
DecodeVST3LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4669 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
4670 uint64_t Address, const void *Decoder)
4671 {
4672 DecodeStatus S = MCDisassembler_Success;
4673 unsigned size, align = 0, index = 0, inc = 1;
4674 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4675 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4676 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4677 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4678 size = fieldFromInstruction_4(Insn, 10, 2);
4679
4680 switch (size) {
4681 default:
4682 return MCDisassembler_Fail;
4683 case 0:
4684 if (fieldFromInstruction_4(Insn, 4, 1))
4685 return MCDisassembler_Fail; // UNDEFINED
4686 index = fieldFromInstruction_4(Insn, 5, 3);
4687 break;
4688 case 1:
4689 if (fieldFromInstruction_4(Insn, 4, 1))
4690 return MCDisassembler_Fail; // UNDEFINED
4691 index = fieldFromInstruction_4(Insn, 6, 2);
4692 if (fieldFromInstruction_4(Insn, 5, 1))
4693 inc = 2;
4694 break;
4695 case 2:
4696 if (fieldFromInstruction_4(Insn, 4, 2))
4697 return MCDisassembler_Fail; // UNDEFINED
4698 index = fieldFromInstruction_4(Insn, 7, 1);
4699 if (fieldFromInstruction_4(Insn, 6, 1))
4700 inc = 2;
4701 break;
4702 }
4703
4704 if (Rm != 0xF) { // Writeback
4705 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4706 return MCDisassembler_Fail;
4707 }
4708 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4709 return MCDisassembler_Fail;
4710 MCOperand_CreateImm0(Inst, align);
4711 if (Rm != 0xF) {
4712 if (Rm != 0xD) {
4713 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4714 return MCDisassembler_Fail;
4715 } else
4716 MCOperand_CreateReg0(Inst, 0);
4717 }
4718
4719 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4720 return MCDisassembler_Fail;
4721 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4722 return MCDisassembler_Fail;
4723 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4724 return MCDisassembler_Fail;
4725 MCOperand_CreateImm0(Inst, index);
4726
4727 return S;
4728 }
4729
DecodeVLD4LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4730 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
4731 uint64_t Address, const void *Decoder)
4732 {
4733 DecodeStatus S = MCDisassembler_Success;
4734 unsigned size, align = 0, index = 0, inc = 1;
4735 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4736 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4737 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4738 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4739 size = fieldFromInstruction_4(Insn, 10, 2);
4740
4741 switch (size) {
4742 default:
4743 return MCDisassembler_Fail;
4744 case 0:
4745 if (fieldFromInstruction_4(Insn, 4, 1))
4746 align = 4;
4747 index = fieldFromInstruction_4(Insn, 5, 3);
4748 break;
4749 case 1:
4750 if (fieldFromInstruction_4(Insn, 4, 1))
4751 align = 8;
4752 index = fieldFromInstruction_4(Insn, 6, 2);
4753 if (fieldFromInstruction_4(Insn, 5, 1))
4754 inc = 2;
4755 break;
4756 case 2:
4757 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4758 case 0:
4759 align = 0; break;
4760 case 3:
4761 return MCDisassembler_Fail;
4762 default:
4763 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
4764 }
4765
4766 index = fieldFromInstruction_4(Insn, 7, 1);
4767 if (fieldFromInstruction_4(Insn, 6, 1))
4768 inc = 2;
4769 break;
4770 }
4771
4772 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4773 return MCDisassembler_Fail;
4774 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4775 return MCDisassembler_Fail;
4776 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4777 return MCDisassembler_Fail;
4778 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4779 return MCDisassembler_Fail;
4780
4781 if (Rm != 0xF) { // Writeback
4782 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4783 return MCDisassembler_Fail;
4784 }
4785 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4786 return MCDisassembler_Fail;
4787 MCOperand_CreateImm0(Inst, align);
4788 if (Rm != 0xF) {
4789 if (Rm != 0xD) {
4790 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4791 return MCDisassembler_Fail;
4792 } else
4793 MCOperand_CreateReg0(Inst, 0);
4794 }
4795
4796 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4797 return MCDisassembler_Fail;
4798 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4799 return MCDisassembler_Fail;
4800 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4801 return MCDisassembler_Fail;
4802 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4803 return MCDisassembler_Fail;
4804 MCOperand_CreateImm0(Inst, index);
4805
4806 return S;
4807 }
4808
DecodeVST4LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4809 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
4810 uint64_t Address, const void *Decoder)
4811 {
4812 DecodeStatus S = MCDisassembler_Success;
4813 unsigned size, align = 0, index = 0, inc = 1;
4814 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4815 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4816 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4817 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4818 size = fieldFromInstruction_4(Insn, 10, 2);
4819
4820 switch (size) {
4821 default:
4822 return MCDisassembler_Fail;
4823 case 0:
4824 if (fieldFromInstruction_4(Insn, 4, 1))
4825 align = 4;
4826 index = fieldFromInstruction_4(Insn, 5, 3);
4827 break;
4828 case 1:
4829 if (fieldFromInstruction_4(Insn, 4, 1))
4830 align = 8;
4831 index = fieldFromInstruction_4(Insn, 6, 2);
4832 if (fieldFromInstruction_4(Insn, 5, 1))
4833 inc = 2;
4834 break;
4835 case 2:
4836 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4837 case 0:
4838 align = 0; break;
4839 case 3:
4840 return MCDisassembler_Fail;
4841 default:
4842 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
4843 }
4844
4845 index = fieldFromInstruction_4(Insn, 7, 1);
4846 if (fieldFromInstruction_4(Insn, 6, 1))
4847 inc = 2;
4848 break;
4849 }
4850
4851 if (Rm != 0xF) { // Writeback
4852 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4853 return MCDisassembler_Fail;
4854 }
4855 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4856 return MCDisassembler_Fail;
4857 MCOperand_CreateImm0(Inst, align);
4858 if (Rm != 0xF) {
4859 if (Rm != 0xD) {
4860 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4861 return MCDisassembler_Fail;
4862 } else
4863 MCOperand_CreateReg0(Inst, 0);
4864 }
4865
4866 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4867 return MCDisassembler_Fail;
4868 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4869 return MCDisassembler_Fail;
4870 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4871 return MCDisassembler_Fail;
4872 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4873 return MCDisassembler_Fail;
4874 MCOperand_CreateImm0(Inst, index);
4875
4876 return S;
4877 }
4878
DecodeVMOVSRR(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4879 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
4880 uint64_t Address, const void *Decoder)
4881 {
4882 DecodeStatus S = MCDisassembler_Success;
4883 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4884 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4885 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4886 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4887 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4888
4889 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4890 S = MCDisassembler_SoftFail;
4891
4892 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4893 return MCDisassembler_Fail;
4894 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4895 return MCDisassembler_Fail;
4896 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4897 return MCDisassembler_Fail;
4898 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4899 return MCDisassembler_Fail;
4900 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4901 return MCDisassembler_Fail;
4902
4903 return S;
4904 }
4905
DecodeVMOVRRS(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4906 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
4907 uint64_t Address, const void *Decoder)
4908 {
4909 DecodeStatus S = MCDisassembler_Success;
4910 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4911 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4912 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4913 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4914 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4915
4916 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4917 S = MCDisassembler_SoftFail;
4918
4919 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4920 return MCDisassembler_Fail;
4921 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4922 return MCDisassembler_Fail;
4923 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4924 return MCDisassembler_Fail;
4925 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4926 return MCDisassembler_Fail;
4927 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4928 return MCDisassembler_Fail;
4929
4930 return S;
4931 }
4932
DecodeIT(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4933 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn,
4934 uint64_t Address, const void *Decoder)
4935 {
4936 DecodeStatus S = MCDisassembler_Success;
4937 unsigned pred = fieldFromInstruction_4(Insn, 4, 4);
4938 unsigned mask = fieldFromInstruction_4(Insn, 0, 4);
4939
4940 if (pred == 0xF) {
4941 pred = 0xE;
4942 S = MCDisassembler_SoftFail;
4943 }
4944
4945 if (mask == 0x0)
4946 return MCDisassembler_Fail;
4947
4948 MCOperand_CreateImm0(Inst, pred);
4949 MCOperand_CreateImm0(Inst, mask);
4950 return S;
4951 }
4952
DecodeT2LDRDPreInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4953 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
4954 uint64_t Address, const void *Decoder)
4955 {
4956 DecodeStatus S = MCDisassembler_Success;
4957
4958 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4959 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
4960 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4961 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4962 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
4963 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
4964 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
4965 bool writeback = (W == 1) | (P == 0);
4966
4967 addr |= (U << 8) | (Rn << 9);
4968
4969 if (writeback && (Rn == Rt || Rn == Rt2))
4970 Check(&S, MCDisassembler_SoftFail);
4971 if (Rt == Rt2)
4972 Check(&S, MCDisassembler_SoftFail);
4973
4974 // Rt
4975 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4976 return MCDisassembler_Fail;
4977 // Rt2
4978 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4979 return MCDisassembler_Fail;
4980 // Writeback operand
4981 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4982 return MCDisassembler_Fail;
4983 // addr
4984 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4985 return MCDisassembler_Fail;
4986
4987 return S;
4988 }
4989
DecodeT2STRDPreInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4990 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
4991 uint64_t Address, const void *Decoder)
4992 {
4993 DecodeStatus S = MCDisassembler_Success;
4994
4995 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4996 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
4997 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4998 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4999 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
5000 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
5001 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
5002 bool writeback = (W == 1) | (P == 0);
5003
5004 addr |= (U << 8) | (Rn << 9);
5005
5006 if (writeback && (Rn == Rt || Rn == Rt2))
5007 Check(&S, MCDisassembler_SoftFail);
5008
5009 // Writeback operand
5010 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5011 return MCDisassembler_Fail;
5012 // Rt
5013 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5014 return MCDisassembler_Fail;
5015 // Rt2
5016 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5017 return MCDisassembler_Fail;
5018 // addr
5019 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5020 return MCDisassembler_Fail;
5021
5022 return S;
5023 }
5024
DecodeT2Adr(MCInst * Inst,uint32_t Insn,uint64_t Address,const void * Decoder)5025 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn,
5026 uint64_t Address, const void *Decoder)
5027 {
5028 unsigned Val;
5029 unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
5030 unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
5031 if (sign1 != sign2) return MCDisassembler_Fail;
5032
5033 Val = fieldFromInstruction_4(Insn, 0, 8);
5034 Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
5035 Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
5036 Val |= sign1 << 12;
5037 MCOperand_CreateImm0(Inst, SignExtend32(Val, 13));
5038
5039 return MCDisassembler_Success;
5040 }
5041
DecodeT2ShifterImmOperand(MCInst * Inst,uint32_t Val,uint64_t Address,const void * Decoder)5042 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
5043 uint64_t Address, const void *Decoder)
5044 {
5045 DecodeStatus S = MCDisassembler_Success;
5046
5047 // Shift of "asr #32" is not allowed in Thumb2 mode.
5048 if (Val == 0x20)
5049 S = MCDisassembler_Fail;
5050 MCOperand_CreateImm0(Inst, Val);
5051
5052 return S;
5053 }
5054
DecodeSwap(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5055 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
5056 uint64_t Address, const void *Decoder)
5057 {
5058 DecodeStatus S;
5059
5060 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5061 unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
5062 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5063 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5064
5065 if (pred == 0xF)
5066 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5067
5068 S = MCDisassembler_Success;
5069
5070 if (Rt == Rn || Rn == Rt2)
5071 S = MCDisassembler_SoftFail;
5072
5073 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5074 return MCDisassembler_Fail;
5075 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5076 return MCDisassembler_Fail;
5077 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5078 return MCDisassembler_Fail;
5079 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5080 return MCDisassembler_Fail;
5081
5082 return S;
5083 }
5084
DecodeVCVTD(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5085 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
5086 uint64_t Address, const void *Decoder)
5087 {
5088 DecodeStatus S = MCDisassembler_Success;
5089 unsigned Vm, imm, cmode, op;
5090 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5091 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5092 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5093 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5094 imm = fieldFromInstruction_4(Insn, 16, 6);
5095 cmode = fieldFromInstruction_4(Insn, 8, 4);
5096 op = fieldFromInstruction_4(Insn, 5, 1);
5097
5098 // VMOVv2f32 is ambiguous with these decodings.
5099 if (!(imm & 0x38) && cmode == 0xF) {
5100 if (op == 1) return MCDisassembler_Fail;
5101 MCInst_setOpcode(Inst, ARM_VMOVv2f32);
5102 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5103 }
5104
5105 if (!(imm & 0x20)) return MCDisassembler_Fail;
5106
5107 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5108 return MCDisassembler_Fail;
5109 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5110 return MCDisassembler_Fail;
5111 MCOperand_CreateImm0(Inst, 64 - imm);
5112
5113 return S;
5114 }
5115
DecodeVCVTQ(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5116 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
5117 uint64_t Address, const void *Decoder)
5118 {
5119 DecodeStatus S = MCDisassembler_Success;
5120 unsigned Vm, imm, cmode, op;
5121 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5122 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5123 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5124 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5125 imm = fieldFromInstruction_4(Insn, 16, 6);
5126 cmode = fieldFromInstruction_4(Insn, 8, 4);
5127 op = fieldFromInstruction_4(Insn, 5, 1);
5128
5129 // VMOVv4f32 is ambiguous with these decodings.
5130 if (!(imm & 0x38) && cmode == 0xF) {
5131 if (op == 1) return MCDisassembler_Fail;
5132 MCInst_setOpcode(Inst, ARM_VMOVv4f32);
5133 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5134 }
5135
5136 if (!(imm & 0x20)) return MCDisassembler_Fail;
5137
5138 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5139 return MCDisassembler_Fail;
5140 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5141 return MCDisassembler_Fail;
5142 MCOperand_CreateImm0(Inst, 64 - imm);
5143
5144 return S;
5145 }
5146
DecodeLDR(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)5147 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
5148 uint64_t Address, const void *Decoder)
5149 {
5150 DecodeStatus S = MCDisassembler_Success;
5151 unsigned Cond;
5152 unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
5153 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5154 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
5155 Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
5156 Cond = fieldFromInstruction_4(Val, 28, 4);
5157
5158 if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
5159 S = MCDisassembler_SoftFail;
5160
5161 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5162 return MCDisassembler_Fail;
5163 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5164 return MCDisassembler_Fail;
5165 if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5166 return MCDisassembler_Fail;
5167 if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5168 return MCDisassembler_Fail;
5169 if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5170 return MCDisassembler_Fail;
5171
5172 return S;
5173 }
5174
DecodeMRRC2(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)5175 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
5176 uint64_t Address, const void *Decoder)
5177 {
5178
5179 DecodeStatus S = MCDisassembler_Success;
5180
5181 unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
5182 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
5183 unsigned cop = fieldFromInstruction_4(Val, 8, 4);
5184 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5185 unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4);
5186
5187 if ((cop & ~0x1) == 0xa)
5188 return MCDisassembler_Fail;
5189
5190 if (Rt == Rt2)
5191 S = MCDisassembler_SoftFail;
5192
5193 MCOperand_CreateImm0(Inst, cop);
5194 MCOperand_CreateImm0(Inst, opc1);
5195 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5196 return MCDisassembler_Fail;
5197 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5198 return MCDisassembler_Fail;
5199 MCOperand_CreateImm0(Inst, CRm);
5200
5201 return S;
5202 }
5203
5204 #endif
5205