1 // Copyright 2014, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_CPU_AARCH64_H 28 #define VIXL_CPU_AARCH64_H 29 30 #include "../cpu-features.h" 31 #include "../globals-vixl.h" 32 33 #include "instructions-aarch64.h" 34 35 #ifndef VIXL_INCLUDE_TARGET_AARCH64 36 // The supporting .cc file is only compiled when the A64 target is selected. 37 // Throw an explicit error now to avoid a harder-to-debug linker error later. 38 // 39 // These helpers _could_ work on any AArch64 host, even when generating AArch32 40 // code, but we don't support this because the available features may differ 41 // between AArch32 and AArch64 on the same platform, so basing AArch32 code 42 // generation on aarch64::CPU features is probably broken. 43 #error cpu-aarch64.h requires VIXL_INCLUDE_TARGET_AARCH64 (scons target=a64). 44 #endif 45 46 namespace vixl { 47 namespace aarch64 { 48 49 // A CPU ID register, for use with CPUFeatures::kIDRegisterEmulation. Fields 50 // specific to each register are described in relevant subclasses. 51 class IDRegister { 52 protected: value_(value)53 explicit IDRegister(uint64_t value = 0) : value_(value) {} 54 55 class Field { 56 public: 57 enum Type { kUnsigned, kSigned }; 58 59 // This needs to be constexpr so that fields have "constant initialisation". 60 // This avoids initialisation order problems when these values are used to 61 // (dynamically) initialise static variables, etc. 62 explicit constexpr Field(int lsb, Type type = kUnsigned) lsb_(lsb)63 : lsb_(lsb), type_(type) {} 64 65 static const int kMaxWidthInBits = 4; 66 GetWidthInBits()67 int GetWidthInBits() const { 68 // All current ID fields have four bits. 69 return kMaxWidthInBits; 70 } GetLsb()71 int GetLsb() const { return lsb_; } GetMsb()72 int GetMsb() const { return lsb_ + GetWidthInBits() - 1; } GetType()73 Type GetType() const { return type_; } 74 75 private: 76 int lsb_; 77 Type type_; 78 }; 79 80 public: 81 // Extract the specified field, performing sign-extension for signed fields. 82 // This allows us to implement the 'value >= number' detection mechanism 83 // recommended by the Arm ARM, for both signed and unsigned fields. 84 int Get(Field field) const; 85 86 private: 87 uint64_t value_; 88 }; 89 90 class AA64PFR0 : public IDRegister { 91 public: AA64PFR0(uint64_t value)92 explicit AA64PFR0(uint64_t value) : IDRegister(value) {} 93 94 CPUFeatures GetCPUFeatures() const; 95 96 private: 97 static const Field kFP; 98 static const Field kAdvSIMD; 99 static const Field kRAS; 100 static const Field kSVE; 101 static const Field kDIT; 102 static const Field kCSV2; 103 static const Field kCSV3; 104 }; 105 106 class AA64PFR1 : public IDRegister { 107 public: AA64PFR1(uint64_t value)108 explicit AA64PFR1(uint64_t value) : IDRegister(value) {} 109 110 CPUFeatures GetCPUFeatures() const; 111 112 private: 113 static const Field kBT; 114 static const Field kSSBS; 115 static const Field kMTE; 116 }; 117 118 class AA64ISAR0 : public IDRegister { 119 public: AA64ISAR0(uint64_t value)120 explicit AA64ISAR0(uint64_t value) : IDRegister(value) {} 121 122 CPUFeatures GetCPUFeatures() const; 123 124 private: 125 static const Field kAES; 126 static const Field kSHA1; 127 static const Field kSHA2; 128 static const Field kCRC32; 129 static const Field kAtomic; 130 static const Field kRDM; 131 static const Field kSHA3; 132 static const Field kSM3; 133 static const Field kSM4; 134 static const Field kDP; 135 static const Field kFHM; 136 static const Field kTS; 137 static const Field kRNDR; 138 }; 139 140 class AA64ISAR1 : public IDRegister { 141 public: AA64ISAR1(uint64_t value)142 explicit AA64ISAR1(uint64_t value) : IDRegister(value) {} 143 144 CPUFeatures GetCPUFeatures() const; 145 146 private: 147 static const Field kDPB; 148 static const Field kAPA; 149 static const Field kAPI; 150 static const Field kJSCVT; 151 static const Field kFCMA; 152 static const Field kLRCPC; 153 static const Field kGPA; 154 static const Field kGPI; 155 static const Field kFRINTTS; 156 static const Field kSB; 157 static const Field kSPECRES; 158 static const Field kBF16; 159 static const Field kDGH; 160 static const Field kI8MM; 161 }; 162 163 class AA64ISAR2 : public IDRegister { 164 public: AA64ISAR2(uint64_t value)165 explicit AA64ISAR2(uint64_t value) : IDRegister(value) {} 166 167 CPUFeatures GetCPUFeatures() const; 168 169 private: 170 static const Field kRPRES; 171 }; 172 173 class AA64MMFR0 : public IDRegister { 174 public: AA64MMFR0(uint64_t value)175 explicit AA64MMFR0(uint64_t value) : IDRegister(value) {} 176 177 CPUFeatures GetCPUFeatures() const; 178 179 private: 180 static const Field kECV; 181 }; 182 183 class AA64MMFR1 : public IDRegister { 184 public: AA64MMFR1(uint64_t value)185 explicit AA64MMFR1(uint64_t value) : IDRegister(value) {} 186 187 CPUFeatures GetCPUFeatures() const; 188 189 private: 190 static const Field kLO; 191 static const Field kAFP; 192 }; 193 194 class AA64MMFR2 : public IDRegister { 195 public: AA64MMFR2(uint64_t value)196 explicit AA64MMFR2(uint64_t value) : IDRegister(value) {} 197 198 CPUFeatures GetCPUFeatures() const; 199 200 private: 201 static const Field kAT; 202 }; 203 204 class AA64ZFR0 : public IDRegister { 205 public: AA64ZFR0(uint64_t value)206 explicit AA64ZFR0(uint64_t value) : IDRegister(value) {} 207 208 CPUFeatures GetCPUFeatures() const; 209 210 private: 211 static const Field kSVEver; 212 static const Field kAES; 213 static const Field kBitPerm; 214 static const Field kBF16; 215 static const Field kSHA3; 216 static const Field kSM4; 217 static const Field kI8MM; 218 static const Field kF32MM; 219 static const Field kF64MM; 220 }; 221 222 class CPU { 223 public: 224 // Initialise CPU support. 225 static void SetUp(); 226 227 // Ensures the data at a given address and with a given size is the same for 228 // the I and D caches. I and D caches are not automatically coherent on ARM 229 // so this operation is required before any dynamically generated code can 230 // safely run. 231 static void EnsureIAndDCacheCoherency(void *address, size_t length); 232 233 // Read and interpret the ID registers. This requires 234 // CPUFeatures::kIDRegisterEmulation, and therefore cannot be called on 235 // non-AArch64 platforms. 236 static CPUFeatures InferCPUFeaturesFromIDRegisters(); 237 238 // Read and interpret CPUFeatures reported by the OS. Failed queries (or 239 // unsupported platforms) return an empty list. Note that this is 240 // indistinguishable from a successful query on a platform that advertises no 241 // features. 242 // 243 // Non-AArch64 hosts are considered to be unsupported platforms, and this 244 // function returns an empty list. 245 static CPUFeatures InferCPUFeaturesFromOS( 246 CPUFeatures::QueryIDRegistersOption option = 247 CPUFeatures::kQueryIDRegistersIfAvailable); 248 249 // Query the SVE vector length. This requires CPUFeatures::kSVE. 250 static int ReadSVEVectorLengthInBits(); 251 252 // Handle tagged pointers. 253 template <typename T> SetPointerTag(T pointer,uint64_t tag)254 static T SetPointerTag(T pointer, uint64_t tag) { 255 VIXL_ASSERT(IsUintN(kAddressTagWidth, tag)); 256 257 // Use C-style casts to get static_cast behaviour for integral types (T), 258 // and reinterpret_cast behaviour for other types. 259 260 uint64_t raw = (uint64_t)pointer; 261 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 262 263 raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset); 264 return (T)raw; 265 } 266 267 template <typename T> GetPointerTag(T pointer)268 static uint64_t GetPointerTag(T pointer) { 269 // Use C-style casts to get static_cast behaviour for integral types (T), 270 // and reinterpret_cast behaviour for other types. 271 272 uint64_t raw = (uint64_t)pointer; 273 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 274 275 return (raw & kAddressTagMask) >> kAddressTagOffset; 276 } 277 278 private: 279 #define VIXL_AARCH64_ID_REG_LIST(V) \ 280 V(AA64PFR0, "ID_AA64PFR0_EL1") \ 281 V(AA64PFR1, "ID_AA64PFR1_EL1") \ 282 V(AA64ISAR0, "ID_AA64ISAR0_EL1") \ 283 V(AA64ISAR1, "ID_AA64ISAR1_EL1") \ 284 V(AA64MMFR0, "ID_AA64MMFR0_EL1") \ 285 V(AA64MMFR1, "ID_AA64MMFR1_EL1") \ 286 /* These registers are RES0 in the baseline Arm8.0. We can always safely */ \ 287 /* read them, but some compilers don't accept the symbolic names. */ \ 288 V(AA64ISAR2, "S3_0_C0_C6_2") \ 289 V(AA64MMFR2, "S3_0_C0_C7_2") \ 290 V(AA64ZFR0, "S3_0_C0_C4_4") 291 292 #define VIXL_READ_ID_REG(NAME, MRS_ARG) static NAME Read##NAME(); 293 // On native AArch64 platforms, read the named CPU ID registers. These require 294 // CPUFeatures::kIDRegisterEmulation, and should not be called on non-AArch64 295 // platforms. 296 VIXL_AARCH64_ID_REG_LIST(VIXL_READ_ID_REG) 297 #undef VIXL_READ_ID_REG 298 299 // Return the content of the cache type register. 300 static uint32_t GetCacheType(); 301 302 // I and D cache line size in bytes. 303 static unsigned icache_line_size_; 304 static unsigned dcache_line_size_; 305 }; 306 307 } // namespace aarch64 308 } // namespace vixl 309 310 #endif // VIXL_CPU_AARCH64_H 311