1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* */
23 /* File Name : ih264d_api.c */
24 /* */
25 /* Description : Has all API related functions */
26 /* */
27 /* */
28 /* List of Functions : api_check_struct_sanity */
29 /* ih264d_set_processor */
30 /* ih264d_create */
31 /* ih264d_delete */
32 /* ih264d_init */
33 /* ih264d_map_error */
34 /* ih264d_video_decode */
35 /* ih264d_get_version */
36 /* ih264d_get_display_frame */
37 /* ih264d_set_display_frame */
38 /* ih264d_set_flush_mode */
39 /* ih264d_get_status */
40 /* ih264d_get_buf_info */
41 /* ih264d_set_params */
42 /* ih264d_set_default_params */
43 /* ih264d_reset */
44 /* ih264d_ctl */
45 /* ih264d_rel_display_frame */
46 /* ih264d_set_degrade */
47 /* ih264d_get_frame_dimensions */
48 /* ih264d_set_num_cores */
49 /* ih264d_fill_output_struct_from_context */
50 /* ih264d_api_function */
51 /* */
52 /* Issues / Problems : None */
53 /* */
54 /* Revision History : */
55 /* */
56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
57 /* 14 10 2008 100356(SKV) Draft */
58 /* */
59 /*****************************************************************************/
60 #include "ih264_typedefs.h"
61 #include "ih264_macros.h"
62 #include "ih264_platform_macros.h"
63 #include "ih264d_tables.h"
64 #include "iv.h"
65 #include "ivd.h"
66 #include "ih264d.h"
67 #include "ih264d_defs.h"
68
69 #include <string.h>
70 #include <limits.h>
71 #include <stddef.h>
72
73 #include "ih264d_inter_pred.h"
74
75 #include "ih264d_structs.h"
76 #include "ih264d_nal.h"
77 #include "ih264d_error_handler.h"
78
79 #include "ih264d_defs.h"
80
81 #include "ithread.h"
82 #include "ih264d_parse_slice.h"
83 #include "ih264d_function_selector.h"
84 #include "ih264_error.h"
85 #include "ih264_disp_mgr.h"
86 #include "ih264_buf_mgr.h"
87 #include "ih264d_deblocking.h"
88 #include "ih264d_parse_cavlc.h"
89 #include "ih264d_parse_cabac.h"
90 #include "ih264d_utils.h"
91 #include "ih264d_format_conv.h"
92 #include "ih264d_parse_headers.h"
93 #include "ih264d_thread_compute_bs.h"
94 #include <assert.h>
95
96
97 /*********************/
98 /* Codec Versioning */
99 /*********************/
100 //Move this to where it is used
101 #define CODEC_NAME "H264VDEC"
102 #define CODEC_RELEASE_TYPE "production"
103 #define CODEC_RELEASE_VER "05.00"
104 #define CODEC_VENDOR "ITTIAM"
105 #define MAXVERSION_STRLEN 511
106 #ifdef ANDROID
107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
108 snprintf(version_string, MAXVERSION_STRLEN, \
109 "@(#)Id:%s_%s Ver:%s Released by %s", \
110 codec_name, codec_release_type, codec_release_ver, codec_vendor)
111 #else
112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
113 snprintf(version_string, MAXVERSION_STRLEN, \
114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116 #endif
117
118
119 #define MIN_IN_BUFS 1
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125 #define NUM_FRAMES_LIMIT_ENABLED 0
126
127 #if NUM_FRAMES_LIMIT_ENABLED
128 #define NUM_FRAMES_LIMIT 10000
129 #else
130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
131 #endif
132
133
134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139 void *pv_api_ip,
140 void *pv_api_op);
141
142 WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
143 void *pv_api_ip,
144 void *pv_api_op);
145
146 WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
147 void *pv_api_ip,
148 void *pv_api_op);
149
150 WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
151 void *pv_api_ip,
152 void *pv_api_op);
153
154 WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
155 void *pv_api_ip,
156 void *pv_api_op);
157
158 WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
159
160 WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
161
162 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
163
164 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
165
166 void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
167
168 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
169 void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
170
171 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
172 void *pv_api_ip,
173 void *pv_api_op);
174
175 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
176 ivd_video_decode_op_t *ps_dec_op);
177
178 /*!
179 **************************************************************************
180 * \if Function name : ih264d_export_sei_params \endif
181 *
182 * \brief
183 * Exports sei params from decoder to application.
184 *
185 * \return
186 * 0 on Success and error code otherwise
187 **************************************************************************
188 */
189
ih264d_export_sei_params(ivd_sei_decode_op_t * ps_sei_decode_op,dec_struct_t * ps_dec)190 void ih264d_export_sei_params(ivd_sei_decode_op_t *ps_sei_decode_op, dec_struct_t *ps_dec)
191 {
192 WORD32 i4_status = IV_SUCCESS;
193 sei *ps_sei = (sei *)ps_dec->pv_disp_sei_params;
194
195 i4_status = ih264d_export_sei_mdcv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
196 i4_status = ih264d_export_sei_cll_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
197 i4_status = ih264d_export_sei_ave_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
198 i4_status = ih264d_export_sei_ccv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
199 i4_status = ih264d_export_sei_sii_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
200 i4_status = ih264d_export_sei_fgc_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
201
202 UNUSED(i4_status);
203 }
204
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)205 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
206 void *pv_api_ip,
207 void *pv_api_op)
208 {
209 IVD_API_COMMAND_TYPE_T e_cmd;
210 UWORD32 *pu4_api_ip;
211 UWORD32 *pu4_api_op;
212 UWORD32 i, j;
213
214 if(NULL == pv_api_op)
215 return (IV_FAIL);
216
217 if(NULL == pv_api_ip)
218 return (IV_FAIL);
219
220 pu4_api_ip = (UWORD32 *)pv_api_ip;
221 pu4_api_op = (UWORD32 *)pv_api_op;
222 e_cmd = *(pu4_api_ip + 1);
223
224 /* error checks on handle */
225 switch((WORD32)e_cmd)
226 {
227 case IVD_CMD_CREATE:
228 break;
229
230 case IVD_CMD_REL_DISPLAY_FRAME:
231 case IVD_CMD_SET_DISPLAY_FRAME:
232 case IVD_CMD_GET_DISPLAY_FRAME:
233 case IVD_CMD_VIDEO_DECODE:
234 case IVD_CMD_DELETE:
235 case IVD_CMD_VIDEO_CTL:
236 if(ps_handle == NULL)
237 {
238 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
239 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
240 return IV_FAIL;
241 }
242
243 if(ps_handle->u4_size != sizeof(iv_obj_t))
244 {
245 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
246 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
247 return IV_FAIL;
248 }
249
250 if(ps_handle->pv_fxns != ih264d_api_function)
251 {
252 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
253 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
254 return IV_FAIL;
255 }
256
257 if(ps_handle->pv_codec_handle == NULL)
258 {
259 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
260 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
261 return IV_FAIL;
262 }
263 break;
264 default:
265 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
266 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
267 return IV_FAIL;
268 }
269
270 switch((WORD32)e_cmd)
271 {
272 case IVD_CMD_CREATE:
273 {
274 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
275 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
276
277
278 ps_op->s_ivd_create_op_t.u4_error_code = 0;
279
280 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
281 || (ps_ip->s_ivd_create_ip_t.u4_size
282 < sizeof(ivd_create_ip_t)))
283 {
284 ps_op->s_ivd_create_op_t.u4_error_code |= 1
285 << IVD_UNSUPPORTEDPARAM;
286 ps_op->s_ivd_create_op_t.u4_error_code |=
287 IVD_IP_API_STRUCT_SIZE_INCORRECT;
288 H264_DEC_DEBUG_PRINT("\n");
289 return (IV_FAIL);
290 }
291
292 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
293 && (ps_op->s_ivd_create_op_t.u4_size
294 != sizeof(ivd_create_op_t)))
295 {
296 ps_op->s_ivd_create_op_t.u4_error_code |= 1
297 << IVD_UNSUPPORTEDPARAM;
298 ps_op->s_ivd_create_op_t.u4_error_code |=
299 IVD_OP_API_STRUCT_SIZE_INCORRECT;
300 H264_DEC_DEBUG_PRINT("\n");
301 return (IV_FAIL);
302 }
303
304
305 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
306 && (ps_ip->s_ivd_create_ip_t.e_output_format
307 != IV_YUV_422ILE)
308 && (ps_ip->s_ivd_create_ip_t.e_output_format
309 != IV_RGB_565)
310 && (ps_ip->s_ivd_create_ip_t.e_output_format
311 != IV_YUV_420SP_UV)
312 && (ps_ip->s_ivd_create_ip_t.e_output_format
313 != IV_YUV_420SP_VU))
314 {
315 ps_op->s_ivd_create_op_t.u4_error_code |= 1
316 << IVD_UNSUPPORTEDPARAM;
317 ps_op->s_ivd_create_op_t.u4_error_code |=
318 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
319 H264_DEC_DEBUG_PRINT("\n");
320 return (IV_FAIL);
321 }
322
323 }
324 break;
325
326 case IVD_CMD_GET_DISPLAY_FRAME:
327 {
328 ih264d_get_display_frame_ip_t *ps_ip =
329 (ih264d_get_display_frame_ip_t *)pv_api_ip;
330 ih264d_get_display_frame_op_t *ps_op =
331 (ih264d_get_display_frame_op_t *)pv_api_op;
332
333 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
334
335 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
336 != sizeof(ih264d_get_display_frame_ip_t))
337 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
338 != sizeof(ivd_get_display_frame_ip_t)))
339 {
340 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
341 << IVD_UNSUPPORTEDPARAM;
342 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
343 IVD_IP_API_STRUCT_SIZE_INCORRECT;
344 return (IV_FAIL);
345 }
346
347 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
348 != sizeof(ih264d_get_display_frame_op_t))
349 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
350 != sizeof(ivd_get_display_frame_op_t)))
351 {
352 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
353 << IVD_UNSUPPORTEDPARAM;
354 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
355 IVD_OP_API_STRUCT_SIZE_INCORRECT;
356 return (IV_FAIL);
357 }
358 }
359 break;
360
361 case IVD_CMD_REL_DISPLAY_FRAME:
362 {
363 ih264d_rel_display_frame_ip_t *ps_ip =
364 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
365 ih264d_rel_display_frame_op_t *ps_op =
366 (ih264d_rel_display_frame_op_t *)pv_api_op;
367
368 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
369
370 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
371 != sizeof(ih264d_rel_display_frame_ip_t))
372 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
373 != sizeof(ivd_rel_display_frame_ip_t)))
374 {
375 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
376 << IVD_UNSUPPORTEDPARAM;
377 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
378 IVD_IP_API_STRUCT_SIZE_INCORRECT;
379 return (IV_FAIL);
380 }
381
382 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
383 != sizeof(ih264d_rel_display_frame_op_t))
384 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
385 != sizeof(ivd_rel_display_frame_op_t)))
386 {
387 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
388 << IVD_UNSUPPORTEDPARAM;
389 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
390 IVD_OP_API_STRUCT_SIZE_INCORRECT;
391 return (IV_FAIL);
392 }
393
394 }
395 break;
396
397 case IVD_CMD_SET_DISPLAY_FRAME:
398 {
399 ih264d_set_display_frame_ip_t *ps_ip =
400 (ih264d_set_display_frame_ip_t *)pv_api_ip;
401 ih264d_set_display_frame_op_t *ps_op =
402 (ih264d_set_display_frame_op_t *)pv_api_op;
403 UWORD32 j;
404
405 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
406
407 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
408 != sizeof(ih264d_set_display_frame_ip_t))
409 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
410 != sizeof(ivd_set_display_frame_ip_t)))
411 {
412 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
413 << IVD_UNSUPPORTEDPARAM;
414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
415 IVD_IP_API_STRUCT_SIZE_INCORRECT;
416 return (IV_FAIL);
417 }
418
419 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
420 != sizeof(ih264d_set_display_frame_op_t))
421 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
422 != sizeof(ivd_set_display_frame_op_t)))
423 {
424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425 << IVD_UNSUPPORTEDPARAM;
426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427 IVD_OP_API_STRUCT_SIZE_INCORRECT;
428 return (IV_FAIL);
429 }
430
431 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
432 {
433 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
434 << IVD_UNSUPPORTEDPARAM;
435 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
436 IVD_DISP_FRM_ZERO_OP_BUFS;
437 return IV_FAIL;
438 }
439
440 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
441 j++)
442 {
443 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
444 == 0)
445 {
446 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
447 << IVD_UNSUPPORTEDPARAM;
448 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
449 IVD_DISP_FRM_ZERO_OP_BUFS;
450 return IV_FAIL;
451 }
452
453 for(i = 0;
454 i
455 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
456 i++)
457 {
458 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
459 == NULL)
460 {
461 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
464 IVD_DISP_FRM_OP_BUF_NULL;
465 return IV_FAIL;
466 }
467
468 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
469 == 0)
470 {
471 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
472 << IVD_UNSUPPORTEDPARAM;
473 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
474 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
475 return IV_FAIL;
476 }
477 }
478 }
479 }
480 break;
481
482 case IVD_CMD_VIDEO_DECODE:
483 {
484 ih264d_video_decode_ip_t *ps_ip =
485 (ih264d_video_decode_ip_t *)pv_api_ip;
486 ih264d_video_decode_op_t *ps_op =
487 (ih264d_video_decode_op_t *)pv_api_op;
488
489 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
490 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
491 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
492
493 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ih264d_video_decode_ip_t) &&
494 ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ivd_video_decode_ip_t) &&
495 ps_ip->s_ivd_video_decode_ip_t.u4_size !=
496 offsetof(ivd_video_decode_ip_t, s_out_buffer))
497 {
498 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
499 << IVD_UNSUPPORTEDPARAM;
500 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
501 IVD_IP_API_STRUCT_SIZE_INCORRECT;
502 return (IV_FAIL);
503 }
504
505 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ih264d_video_decode_op_t) &&
506 ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ivd_video_decode_op_t) &&
507 ps_op->s_ivd_video_decode_op_t.u4_size !=
508 offsetof(ivd_video_decode_op_t, u4_output_present))
509 {
510 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
511 << IVD_UNSUPPORTEDPARAM;
512 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
513 IVD_OP_API_STRUCT_SIZE_INCORRECT;
514 return (IV_FAIL);
515 }
516
517 {
518 dec_struct_t *ps_dec = (dec_struct_t *)(ps_handle->pv_codec_handle);
519 if(ps_dec->u1_enable_mb_info)
520 {
521 if(!ps_ip->pu1_8x8_blk_qp_map && !ps_ip->pu1_8x8_blk_type_map)
522 {
523 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
524 << IVD_UNSUPPORTEDPARAM;
525 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
526 IH264D_FRAME_INFO_OP_BUF_NULL;
527 return IV_FAIL;
528 }
529 }
530 }
531 }
532 break;
533
534 case IVD_CMD_DELETE:
535 {
536 ih264d_delete_ip_t *ps_ip =
537 (ih264d_delete_ip_t *)pv_api_ip;
538 ih264d_delete_op_t *ps_op =
539 (ih264d_delete_op_t *)pv_api_op;
540
541 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
542
543 if(ps_ip->s_ivd_delete_ip_t.u4_size
544 != sizeof(ih264d_delete_ip_t))
545 {
546 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
547 << IVD_UNSUPPORTEDPARAM;
548 ps_op->s_ivd_delete_op_t.u4_error_code |=
549 IVD_IP_API_STRUCT_SIZE_INCORRECT;
550 return (IV_FAIL);
551 }
552
553 if(ps_op->s_ivd_delete_op_t.u4_size
554 != sizeof(ih264d_delete_op_t))
555 {
556 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
557 << IVD_UNSUPPORTEDPARAM;
558 ps_op->s_ivd_delete_op_t.u4_error_code |=
559 IVD_OP_API_STRUCT_SIZE_INCORRECT;
560 return (IV_FAIL);
561 }
562
563 }
564 break;
565
566 case IVD_CMD_VIDEO_CTL:
567 {
568 UWORD32 *pu4_ptr_cmd;
569 UWORD32 sub_command;
570
571 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
572 pu4_ptr_cmd += 2;
573 sub_command = *pu4_ptr_cmd;
574
575 switch(sub_command)
576 {
577 case IVD_CMD_CTL_SETPARAMS:
578 {
579 ih264d_ctl_set_config_ip_t *ps_ip;
580 ih264d_ctl_set_config_op_t *ps_op;
581 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
582 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
583
584 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
585 != sizeof(ih264d_ctl_set_config_ip_t))
586 {
587 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
588 << IVD_UNSUPPORTEDPARAM;
589 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
590 IVD_IP_API_STRUCT_SIZE_INCORRECT;
591 return IV_FAIL;
592 }
593 }
594 //no break; is needed here
595 case IVD_CMD_CTL_SETDEFAULT:
596 {
597 ih264d_ctl_set_config_op_t *ps_op;
598 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
599 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
600 != sizeof(ih264d_ctl_set_config_op_t))
601 {
602 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
603 << IVD_UNSUPPORTEDPARAM;
604 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
605 IVD_OP_API_STRUCT_SIZE_INCORRECT;
606 return IV_FAIL;
607 }
608 }
609 break;
610
611 case IVD_CMD_CTL_GETPARAMS:
612 {
613 ih264d_ctl_getstatus_ip_t *ps_ip;
614 ih264d_ctl_getstatus_op_t *ps_op;
615
616 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
617 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
618 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
619 != sizeof(ih264d_ctl_getstatus_ip_t))
620 {
621 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
622 << IVD_UNSUPPORTEDPARAM;
623 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
624 IVD_IP_API_STRUCT_SIZE_INCORRECT;
625 return IV_FAIL;
626 }
627 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
628 != sizeof(ih264d_ctl_getstatus_op_t))
629 {
630 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
631 << IVD_UNSUPPORTEDPARAM;
632 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
633 IVD_OP_API_STRUCT_SIZE_INCORRECT;
634 return IV_FAIL;
635 }
636 }
637 break;
638
639 case IVD_CMD_CTL_GETBUFINFO:
640 {
641 ih264d_ctl_getbufinfo_ip_t *ps_ip;
642 ih264d_ctl_getbufinfo_op_t *ps_op;
643 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
644 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
645
646 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
647 != sizeof(ih264d_ctl_getbufinfo_ip_t))
648 {
649 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
650 << IVD_UNSUPPORTEDPARAM;
651 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
652 IVD_IP_API_STRUCT_SIZE_INCORRECT;
653 return IV_FAIL;
654 }
655 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
656 != sizeof(ih264d_ctl_getbufinfo_op_t))
657 {
658 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
659 << IVD_UNSUPPORTEDPARAM;
660 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
661 IVD_OP_API_STRUCT_SIZE_INCORRECT;
662 return IV_FAIL;
663 }
664 }
665 break;
666
667 case IVD_CMD_CTL_GETVERSION:
668 {
669 ih264d_ctl_getversioninfo_ip_t *ps_ip;
670 ih264d_ctl_getversioninfo_op_t *ps_op;
671 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
672 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
673 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
674 != sizeof(ih264d_ctl_getversioninfo_ip_t))
675 {
676 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
677 << IVD_UNSUPPORTEDPARAM;
678 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
679 IVD_IP_API_STRUCT_SIZE_INCORRECT;
680 return IV_FAIL;
681 }
682 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
683 != sizeof(ih264d_ctl_getversioninfo_op_t))
684 {
685 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
686 << IVD_UNSUPPORTEDPARAM;
687 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
688 IVD_OP_API_STRUCT_SIZE_INCORRECT;
689 return IV_FAIL;
690 }
691 }
692 break;
693
694 case IVD_CMD_CTL_FLUSH:
695 {
696 ih264d_ctl_flush_ip_t *ps_ip;
697 ih264d_ctl_flush_op_t *ps_op;
698 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
699 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
700 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
701 != sizeof(ih264d_ctl_flush_ip_t))
702 {
703 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
704 << IVD_UNSUPPORTEDPARAM;
705 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
706 IVD_IP_API_STRUCT_SIZE_INCORRECT;
707 return IV_FAIL;
708 }
709 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
710 != sizeof(ih264d_ctl_flush_op_t))
711 {
712 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
713 << IVD_UNSUPPORTEDPARAM;
714 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
715 IVD_OP_API_STRUCT_SIZE_INCORRECT;
716 return IV_FAIL;
717 }
718 }
719 break;
720
721 case IVD_CMD_CTL_RESET:
722 {
723 ih264d_ctl_reset_ip_t *ps_ip;
724 ih264d_ctl_reset_op_t *ps_op;
725 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
726 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
727 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
728 != sizeof(ih264d_ctl_reset_ip_t))
729 {
730 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
731 << IVD_UNSUPPORTEDPARAM;
732 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
733 IVD_IP_API_STRUCT_SIZE_INCORRECT;
734 return IV_FAIL;
735 }
736 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
737 != sizeof(ih264d_ctl_reset_op_t))
738 {
739 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
740 << IVD_UNSUPPORTEDPARAM;
741 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
742 IVD_OP_API_STRUCT_SIZE_INCORRECT;
743 return IV_FAIL;
744 }
745 }
746 break;
747
748 case IH264D_CMD_CTL_DEGRADE:
749 {
750 ih264d_ctl_degrade_ip_t *ps_ip;
751 ih264d_ctl_degrade_op_t *ps_op;
752
753 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
754 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
755
756 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
757 {
758 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
759 ps_op->u4_error_code |=
760 IVD_IP_API_STRUCT_SIZE_INCORRECT;
761 return IV_FAIL;
762 }
763
764 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
765 {
766 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
767 ps_op->u4_error_code |=
768 IVD_OP_API_STRUCT_SIZE_INCORRECT;
769 return IV_FAIL;
770 }
771
772 if((ps_ip->i4_degrade_pics < 0)
773 || (ps_ip->i4_degrade_pics > 4)
774 || (ps_ip->i4_nondegrade_interval < 0)
775 || (ps_ip->i4_degrade_type < 0)
776 || (ps_ip->i4_degrade_type > 15))
777 {
778 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
779 return IV_FAIL;
780 }
781
782 break;
783 }
784
785 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
786 {
787 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
788 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
789
790 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
791 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
792
793 if(ps_ip->u4_size
794 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
795 {
796 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
797 ps_op->u4_error_code |=
798 IVD_IP_API_STRUCT_SIZE_INCORRECT;
799 return IV_FAIL;
800 }
801
802 if(ps_op->u4_size
803 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
804 {
805 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
806 ps_op->u4_error_code |=
807 IVD_OP_API_STRUCT_SIZE_INCORRECT;
808 return IV_FAIL;
809 }
810
811 break;
812 }
813 case IH264D_CMD_CTL_GET_VUI_PARAMS:
814 {
815 ih264d_ctl_get_vui_params_ip_t *ps_ip;
816 ih264d_ctl_get_vui_params_op_t *ps_op;
817
818 ps_ip =
819 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
820 ps_op =
821 (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
822
823 if(ps_ip->u4_size
824 != sizeof(ih264d_ctl_get_vui_params_ip_t))
825 {
826 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
827 ps_op->u4_error_code |=
828 IVD_IP_API_STRUCT_SIZE_INCORRECT;
829 return IV_FAIL;
830 }
831
832 if(ps_op->u4_size
833 != sizeof(ih264d_ctl_get_vui_params_op_t))
834 {
835 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
836 ps_op->u4_error_code |=
837 IVD_OP_API_STRUCT_SIZE_INCORRECT;
838 return IV_FAIL;
839 }
840
841 break;
842 }
843 case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
844 {
845 ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
846 ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
847
848 ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
849 ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
850
851 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_ip_t))
852 {
853 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
854 ps_op->u4_error_code |=
855 IVD_IP_API_STRUCT_SIZE_INCORRECT;
856 return IV_FAIL;
857 }
858
859 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_op_t))
860 {
861 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
862 ps_op->u4_error_code |=
863 IVD_OP_API_STRUCT_SIZE_INCORRECT;
864 return IV_FAIL;
865 }
866
867 break;
868 }
869
870 case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
871 {
872 ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
873 ih264d_ctl_get_sei_cll_params_op_t *ps_op;
874
875 ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
876 ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
877
878 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_ip_t))
879 {
880 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
881 ps_op->u4_error_code |=
882 IVD_IP_API_STRUCT_SIZE_INCORRECT;
883 return IV_FAIL;
884 }
885
886 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_op_t))
887 {
888 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
889 ps_op->u4_error_code |=
890 IVD_OP_API_STRUCT_SIZE_INCORRECT;
891 return IV_FAIL;
892 }
893
894 break;
895 }
896
897 case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
898 {
899 ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
900 ih264d_ctl_get_sei_ave_params_op_t *ps_op;
901
902 ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
903 ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
904
905 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_ip_t))
906 {
907 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
908 ps_op->u4_error_code |=
909 IVD_IP_API_STRUCT_SIZE_INCORRECT;
910 return IV_FAIL;
911 }
912
913 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_op_t))
914 {
915 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
916 ps_op->u4_error_code |=
917 IVD_OP_API_STRUCT_SIZE_INCORRECT;
918 return IV_FAIL;
919 }
920
921 break;
922 }
923
924 case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
925 {
926 ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
927 ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
928
929 ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
930 ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
931
932 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_ip_t))
933 {
934 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
935 ps_op->u4_error_code |=
936 IVD_IP_API_STRUCT_SIZE_INCORRECT;
937 return IV_FAIL;
938 }
939
940 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_op_t))
941 {
942 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
943 ps_op->u4_error_code |=
944 IVD_OP_API_STRUCT_SIZE_INCORRECT;
945 return IV_FAIL;
946 }
947
948 break;
949 }
950
951 case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
952 {
953 ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
954 ih264d_ctl_get_sei_sii_params_op_t *ps_op;
955
956 ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
957 ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
958
959 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_ip_t))
960 {
961 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
962 ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
963 return IV_FAIL;
964 }
965
966 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_op_t))
967 {
968 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
969 ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
970 return IV_FAIL;
971 }
972
973 break;
974 }
975
976 case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
977 {
978 ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
979 ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
980
981 ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
982 ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
983
984 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_ip_t))
985 {
986 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
987 ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
988 return IV_FAIL;
989 }
990
991 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_op_t))
992 {
993 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
994 ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
995 return IV_FAIL;
996 }
997
998 break;
999 }
1000
1001 case IH264D_CMD_CTL_SET_NUM_CORES:
1002 {
1003 ih264d_ctl_set_num_cores_ip_t *ps_ip;
1004 ih264d_ctl_set_num_cores_op_t *ps_op;
1005
1006 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1007 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1008
1009 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1010 {
1011 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1012 ps_op->u4_error_code |=
1013 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1014 return IV_FAIL;
1015 }
1016
1017 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1018 {
1019 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1020 ps_op->u4_error_code |=
1021 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1022 return IV_FAIL;
1023 }
1024
1025 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1026 && (ps_ip->u4_num_cores != 3)
1027 && (ps_ip->u4_num_cores != 4))
1028 {
1029 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1030 return IV_FAIL;
1031 }
1032 break;
1033 }
1034 case IH264D_CMD_CTL_SET_PROCESSOR:
1035 {
1036 ih264d_ctl_set_processor_ip_t *ps_ip;
1037 ih264d_ctl_set_processor_op_t *ps_op;
1038
1039 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1040 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1041
1042 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1043 {
1044 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1045 ps_op->u4_error_code |=
1046 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1047 return IV_FAIL;
1048 }
1049
1050 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1051 {
1052 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1053 ps_op->u4_error_code |=
1054 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1055 return IV_FAIL;
1056 }
1057
1058 break;
1059 }
1060 default:
1061 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1062 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1063 return IV_FAIL;
1064 break;
1065 }
1066 }
1067 break;
1068 }
1069
1070 return IV_SUCCESS;
1071 }
1072
1073
1074 /**
1075 *******************************************************************************
1076 *
1077 * @brief
1078 * Sets Processor type
1079 *
1080 * @par Description:
1081 * Sets Processor type
1082 *
1083 * @param[in] ps_codec_obj
1084 * Pointer to codec object at API level
1085 *
1086 * @param[in] pv_api_ip
1087 * Pointer to input argument structure
1088 *
1089 * @param[out] pv_api_op
1090 * Pointer to output argument structure
1091 *
1092 * @returns Status
1093 *
1094 * @remarks
1095 *
1096 *
1097 *******************************************************************************
1098 */
1099
ih264d_set_processor(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1100 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1101 {
1102 ih264d_ctl_set_processor_ip_t *ps_ip;
1103 ih264d_ctl_set_processor_op_t *ps_op;
1104 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1105
1106 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1107 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1108
1109 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1110 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1111
1112 ih264d_init_function_ptr(ps_codec);
1113
1114 ps_op->u4_error_code = 0;
1115 return IV_SUCCESS;
1116 }
1117
1118
1119 /**************************************************************************
1120 * \if Function name : ih264d_init_decoder \endif
1121 *
1122 *
1123 * \brief
1124 * Initializes the decoder
1125 *
1126 * \param apiVersion : Version of the api being used.
1127 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
1128 * \param postFilteringType: Type of post filtering operation to be used.
1129 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1130 * \param uc_dispBufs: Number of Display Buffers.
1131 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1132 * \param p_DispBufAPI: Pointer to Display Buffer API.
1133 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1134 * for memory allocation and freeing.
1135 *
1136 * \return
1137 * 0 on Success and -1 on error
1138 *
1139 **************************************************************************
1140 */
ih264d_init_decoder(void * ps_dec_params)1141 void ih264d_init_decoder(void * ps_dec_params)
1142 {
1143 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1144 dec_slice_params_t *ps_cur_slice;
1145 pocstruct_t *ps_prev_poc, *ps_cur_poc;
1146 WORD32 size;
1147
1148 size = sizeof(pred_info_t) * 2 * 32;
1149 memset(ps_dec->ps_pred, 0 , size);
1150
1151 size = sizeof(disp_mgr_t);
1152 memset(ps_dec->pv_disp_buf_mgr, 0 , size);
1153
1154 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1155 memset(ps_dec->pv_pic_buf_mgr, 0, size);
1156
1157 size = sizeof(dec_err_status_t);
1158 memset(ps_dec->ps_dec_err_status, 0, size);
1159
1160 size = sizeof(sei);
1161 memset(ps_dec->ps_sei, 0, size);
1162
1163 size = sizeof(sei);
1164 memset(ps_dec->ps_sei_parse, 0, size);
1165
1166 size = sizeof(dpb_commands_t);
1167 memset(ps_dec->ps_dpb_cmds, 0, size);
1168
1169 size = sizeof(dec_bit_stream_t);
1170 memset(ps_dec->ps_bitstrm, 0, size);
1171
1172 size = sizeof(dec_slice_params_t);
1173 memset(ps_dec->ps_cur_slice, 0, size);
1174
1175 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1176 memset(ps_dec->pv_scratch_sps_pps, 0, size);
1177
1178 size = sizeof(ctxt_inc_mb_info_t);
1179 memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
1180
1181 size = (sizeof(neighbouradd_t) << 2);
1182 memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
1183
1184 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1185 memset(ps_dec->pv_mv_buf_mgr, 0, size);
1186
1187 /* Free any dynamic buffers that are allocated */
1188 ih264d_free_dynamic_bufs(ps_dec);
1189
1190 {
1191 UWORD8 i;
1192 struct pic_buffer_t *ps_init_dpb;
1193 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
1194 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1195 {
1196 ps_init_dpb->pu1_buf1 = NULL;
1197 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1198 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
1199 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
1200 ps_init_dpb++;
1201 }
1202
1203 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
1204 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1205 {
1206 ps_init_dpb->pu1_buf1 = NULL;
1207 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1208 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
1209 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
1210 ps_init_dpb++;
1211 }
1212 }
1213
1214 ps_cur_slice = ps_dec->ps_cur_slice;
1215 ps_dec->init_done = 0;
1216
1217 ps_dec->u4_num_cores = 1;
1218
1219 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1220
1221 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1222 ps_dec->u4_app_disable_deblk_frm = 0;
1223 ps_dec->i4_degrade_type = 0;
1224 ps_dec->i4_degrade_pics = 0;
1225
1226 memset(ps_dec->ps_pps, 0,
1227 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1228 memset(ps_dec->ps_sps, 0,
1229 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1230
1231 /* Initialization of function pointers ih264d_deblock_picture function*/
1232
1233 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1234 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1235
1236 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1237
1238 ps_dec->u4_num_fld_in_frm = 0;
1239
1240 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1241
1242 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1243 ps_dec->ps_sei->u1_is_valid = 0;
1244
1245 /* decParams Initializations */
1246 ps_dec->ps_cur_pps = NULL;
1247 ps_dec->ps_cur_sps = NULL;
1248 ps_dec->u1_init_dec_flag = 0;
1249 ps_dec->u1_first_slice_in_stream = 1;
1250 ps_dec->u1_last_pic_not_decoded = 0;
1251 ps_dec->u4_app_disp_width = 0;
1252 ps_dec->i4_header_decoded = 0;
1253 ps_dec->u4_total_frames_decoded = 0;
1254
1255 ps_dec->i4_error_code = 0;
1256 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1257 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1258
1259 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1260 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1261 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1262 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1263 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1264
1265 ps_dec->u1_pr_sl_type = 0xFF;
1266 ps_dec->u2_mbx = 0xffff;
1267 ps_dec->u2_mby = 0;
1268 ps_dec->u2_total_mbs_coded = 0;
1269
1270 /* POC initializations */
1271 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1272 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1273 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1274 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1275 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1276 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1277 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1278 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1279 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1280 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1281 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1282 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1283 0;
1284 ps_prev_poc->i4_bottom_field_order_count =
1285 ps_cur_poc->i4_bottom_field_order_count = 0;
1286 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1287 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1288 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1289 ps_cur_slice->u1_mmco_equalto5 = 0;
1290 ps_cur_slice->u2_frame_num = 0;
1291
1292 ps_dec->i4_max_poc = 0;
1293 ps_dec->i4_prev_max_display_seq = 0;
1294 ps_dec->u1_recon_mb_grp = 4;
1295 ps_dec->i4_reorder_depth = -1;
1296
1297 /* Field PIC initializations */
1298 ps_dec->u1_second_field = 0;
1299 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1300
1301 /* Set the cropping parameters as zero */
1302 ps_dec->u2_crop_offset_y = 0;
1303 ps_dec->u2_crop_offset_uv = 0;
1304
1305 /* The Initial Frame Rate Info is not Present */
1306 ps_dec->i4_vui_frame_rate = -1;
1307 ps_dec->i4_pic_type = NA_SLICE;
1308 ps_dec->i4_frametype = IV_NA_FRAME;
1309 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1310
1311 ps_dec->u1_res_changed = 0;
1312
1313
1314 ps_dec->u1_frame_decoded_flag = 0;
1315
1316 /* Set the default frame seek mask mode */
1317 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1318
1319 /********************************************************/
1320 /* Initialize CAVLC residual decoding function pointers */
1321 /********************************************************/
1322 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1323 ps_dec->pf_cavlc_4x4res_block[1] =
1324 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1325 ps_dec->pf_cavlc_4x4res_block[2] =
1326 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1327
1328 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1329 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1330
1331 ps_dec->pf_cavlc_parse_8x8block[0] =
1332 ih264d_cavlc_parse_8x8block_none_available;
1333 ps_dec->pf_cavlc_parse_8x8block[1] =
1334 ih264d_cavlc_parse_8x8block_left_available;
1335 ps_dec->pf_cavlc_parse_8x8block[2] =
1336 ih264d_cavlc_parse_8x8block_top_available;
1337 ps_dec->pf_cavlc_parse_8x8block[3] =
1338 ih264d_cavlc_parse_8x8block_both_available;
1339
1340 /***************************************************************************/
1341 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1342 /***************************************************************************/
1343 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1344 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1345
1346 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1347 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1348
1349 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1350 ih264d_fill_bs_xtra_left_edge_cur_frm;
1351 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1352 ih264d_fill_bs_xtra_left_edge_cur_fld;
1353
1354 /* Initialize Reference Pic Buffers */
1355 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1356
1357 ps_dec->u2_prv_frame_num = 0;
1358 ps_dec->u1_top_bottom_decoded = 0;
1359 ps_dec->u1_dangling_field = 0;
1360
1361 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1362
1363 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1364 ps_dec->pi1_left_ref_idx_ctxt_inc =
1365 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1366 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1367
1368 /* ! */
1369 /* Initializing flush frame u4_flag */
1370 ps_dec->u1_flushfrm = 0;
1371
1372 {
1373 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1374 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1375 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1376 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1377 }
1378
1379 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1380 memset(ps_dec->u4_disp_buf_mapping, 0,
1381 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1382 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1383 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1384 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1385
1386 ih264d_init_arch(ps_dec);
1387 ih264d_init_function_ptr(ps_dec);
1388 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1389 ps_dec->init_done = 1;
1390
1391 }
ih264d_free_static_bufs(iv_obj_t * dec_hdl)1392 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1393 {
1394 dec_struct_t *ps_dec;
1395
1396 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1397 void *pv_mem_ctxt;
1398
1399 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1400 pf_aligned_free = ps_dec->pf_aligned_free;
1401 pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1402
1403 #ifdef KEEP_THREADS_ACTIVE
1404 /* Wait for threads */
1405 ps_dec->i4_break_threads = 1;
1406 if(ps_dec->u4_dec_thread_created)
1407 {
1408 ithread_mutex_lock(ps_dec->apv_proc_start_mutex[0]);
1409
1410 ps_dec->ai4_process_start[0] = PROC_START;
1411
1412 ithread_cond_signal(ps_dec->apv_proc_start_condition[0]);
1413
1414 ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[0]);
1415
1416 ithread_join(ps_dec->pv_dec_thread_handle, NULL);
1417
1418 ps_dec->u4_dec_thread_created = 0;
1419 }
1420
1421 if(ps_dec->u4_bs_deblk_thread_created)
1422 {
1423 ithread_mutex_lock(ps_dec->apv_proc_start_mutex[1]);
1424
1425 ps_dec->ai4_process_start[1] = PROC_START;
1426
1427 ithread_cond_signal(ps_dec->apv_proc_start_condition[1]);
1428
1429 ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[1]);
1430
1431 ithread_join(ps_dec->pv_bs_deblk_thread_handle, NULL);
1432
1433 ps_dec->u4_bs_deblk_thread_created = 0;
1434 }
1435
1436 // destroy mutex and condition variable for both the threads
1437 // 1. ih264d_decode_picture_thread
1438 // 2. ih264d_recon_deblk_thread
1439 {
1440 UWORD32 i;
1441 for(i = 0; i < 2; i++)
1442 {
1443 ithread_cond_destroy(ps_dec->apv_proc_start_condition[i]);
1444 ithread_cond_destroy(ps_dec->apv_proc_done_condition[i]);
1445
1446 ithread_mutex_destroy(ps_dec->apv_proc_start_mutex[i]);
1447 ithread_mutex_destroy(ps_dec->apv_proc_done_mutex[i]);
1448 }
1449 }
1450 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_mutex[0]);
1451 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_condition[0]);
1452 #endif
1453
1454 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1455 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1456 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1457 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1458 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1459 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1460 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1461 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1462 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1463 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1464 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1465 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei_parse);
1466 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1467 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1468 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1469 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1470 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1471 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1472 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1473 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1474 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1475 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1476 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1477 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1478 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1479 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1480 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1481 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1482 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1483 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1484
1485 if(dec_hdl)
1486 {
1487 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1488 }
1489 return IV_SUCCESS;
1490 }
1491 /*****************************************************************************/
1492 /* */
1493 /* Function Name : ih264d_create */
1494 /* */
1495 /* Description : creates decoder */
1496 /* */
1497 /* Inputs :iv_obj_t decoder handle */
1498 /* :pv_api_ip pointer to input structure */
1499 /* :pv_api_op pointer to output structure */
1500 /* Outputs : */
1501 /* Returns : void */
1502 /* */
1503 /* Issues : none */
1504 /* */
1505 /* Revision History: */
1506 /* */
1507 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1508 /* 22 10 2008 100356 Draft */
1509 /* */
1510 /*****************************************************************************/
ih264d_allocate_static_bufs(iv_obj_t ** dec_hdl,void * pv_api_ip,void * pv_api_op)1511 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1512 {
1513 ih264d_create_ip_t *ps_create_ip;
1514 ih264d_create_op_t *ps_create_op;
1515 void *pv_buf;
1516 UWORD8 *pu1_buf;
1517 dec_struct_t *ps_dec;
1518 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1519 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1520 void *pv_mem_ctxt;
1521 WORD32 size;
1522
1523 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1524 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1525
1526 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1527
1528 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1529 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1530 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1531
1532 /* Initialize return handle to NULL */
1533 ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1534 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1535 RETURN_IF((NULL == pv_buf), IV_FAIL);
1536 memset(pv_buf, 0, sizeof(iv_obj_t));
1537 *dec_hdl = (iv_obj_t *)pv_buf;
1538 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1539
1540 (*dec_hdl)->pv_codec_handle = NULL;
1541 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1542 RETURN_IF((NULL == pv_buf), IV_FAIL);
1543 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1544 ps_dec = (dec_struct_t *)pv_buf;
1545
1546 memset(ps_dec, 0, sizeof(dec_struct_t));
1547
1548 #ifndef LOGO_EN
1549 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1550 #else
1551 ps_dec->u4_share_disp_buf = 0;
1552 #endif
1553
1554 ps_dec->u1_chroma_format =
1555 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1556
1557 if((ps_dec->u1_chroma_format != IV_YUV_420P)
1558 && (ps_dec->u1_chroma_format
1559 != IV_YUV_420SP_UV)
1560 && (ps_dec->u1_chroma_format
1561 != IV_YUV_420SP_VU))
1562 {
1563 ps_dec->u4_share_disp_buf = 0;
1564 }
1565
1566 ps_dec->u1_enable_mb_info = ps_create_ip->u4_enable_frame_info;
1567 ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1568 ps_dec->pf_aligned_free = pf_aligned_free;
1569 ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1570
1571
1572 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1573 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1574 RETURN_IF((NULL == pv_buf), IV_FAIL);
1575 memset(pv_buf, 0, size);
1576 ps_dec->ps_sps = pv_buf;
1577
1578 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1579 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1580 RETURN_IF((NULL == pv_buf), IV_FAIL);
1581 memset(pv_buf, 0, size);
1582 ps_dec->ps_pps = pv_buf;
1583
1584 size = ithread_get_handle_size();
1585 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1586 RETURN_IF((NULL == pv_buf), IV_FAIL);
1587 memset(pv_buf, 0, size);
1588 ps_dec->pv_dec_thread_handle = pv_buf;
1589
1590 size = ithread_get_handle_size();
1591 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1592 RETURN_IF((NULL == pv_buf), IV_FAIL);
1593 memset(pv_buf, 0, size);
1594 ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1595
1596 #ifdef KEEP_THREADS_ACTIVE
1597 {
1598 UWORD32 i;
1599 /* Request memory to hold mutex (start/done) for both threads */
1600 size = ithread_get_mutex_lock_size() << 2;
1601 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1602 RETURN_IF((NULL == pv_buf), IV_FAIL);
1603 memset(pv_buf, 0, size);
1604
1605 // init mutex variable for both the threads
1606 // 1. ih264d_decode_picture_thread
1607 // 2. ih264d_recon_deblk_thread
1608 for(i = 0; i < 2; i++)
1609 {
1610 WORD32 ret;
1611 WORD32 mutex_size = ithread_get_mutex_lock_size();
1612
1613 ps_dec->apv_proc_start_mutex[i] =
1614 (UWORD8 *)pv_buf + (2 * i * mutex_size);
1615 ps_dec->apv_proc_done_mutex[i] =
1616 (UWORD8 *)pv_buf + ((2 * i + 1) * mutex_size);
1617
1618 ret = ithread_mutex_init(ps_dec->apv_proc_start_mutex[0]);
1619 RETURN_IF((ret != IV_SUCCESS), ret);
1620
1621 ret = ithread_mutex_init(ps_dec->apv_proc_done_mutex[i]);
1622 RETURN_IF((ret != IV_SUCCESS), ret);
1623 }
1624
1625 size = ithread_get_cond_struct_size() << 2;
1626 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1627 RETURN_IF((NULL == pv_buf), IV_FAIL);
1628 memset(pv_buf, 0, size);
1629
1630 // init condition variable for both the threads
1631 for(i = 0; i < 2; i++)
1632 {
1633 WORD32 ret;
1634 WORD32 cond_size = ithread_get_cond_struct_size();
1635 ps_dec->apv_proc_start_condition[i] =
1636 (UWORD8 *)pv_buf + (2 * i * cond_size);
1637 ps_dec->apv_proc_done_condition[i] =
1638 (UWORD8 *)pv_buf + ((2 * i + 1) * cond_size);
1639
1640 ret = ithread_cond_init(ps_dec->apv_proc_start_condition[i]);
1641 RETURN_IF((ret != IV_SUCCESS), ret);
1642
1643 ret = ithread_cond_init(ps_dec->apv_proc_done_condition[i]);
1644 RETURN_IF((ret != IV_SUCCESS), ret);
1645 }
1646 }
1647 #endif
1648
1649 size = sizeof(dpb_manager_t);
1650 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1651 RETURN_IF((NULL == pv_buf), IV_FAIL);
1652 memset(pv_buf, 0, size);
1653 ps_dec->ps_dpb_mgr = pv_buf;
1654
1655 size = sizeof(pred_info_t) * 2 * 32;
1656 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1657 RETURN_IF((NULL == pv_buf), IV_FAIL);
1658 memset(pv_buf, 0, size);
1659 ps_dec->ps_pred = pv_buf;
1660
1661 size = sizeof(disp_mgr_t);
1662 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1663 RETURN_IF((NULL == pv_buf), IV_FAIL);
1664 memset(pv_buf, 0, size);
1665 ps_dec->pv_disp_buf_mgr = pv_buf;
1666
1667 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1668 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1669 RETURN_IF((NULL == pv_buf), IV_FAIL);
1670 memset(pv_buf, 0, size);
1671 ps_dec->pv_pic_buf_mgr = pv_buf;
1672
1673 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1674 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1675 RETURN_IF((NULL == pv_buf), IV_FAIL);
1676 memset(pv_buf, 0, size);
1677 ps_dec->ps_pic_buf_base = pv_buf;
1678
1679 size = sizeof(dec_err_status_t);
1680 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1681 RETURN_IF((NULL == pv_buf), IV_FAIL);
1682 memset(pv_buf, 0, size);
1683 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1684
1685 size = sizeof(sei);
1686 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1687 RETURN_IF((NULL == pv_buf), IV_FAIL);
1688 memset(pv_buf, 0, size);
1689 ps_dec->ps_sei = (sei *)pv_buf;
1690
1691 size = sizeof(sei);
1692 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1693 RETURN_IF((NULL == pv_buf), IV_FAIL);
1694 memset(pv_buf, 0, size);
1695 ps_dec->ps_sei_parse = (sei *)pv_buf;
1696
1697 size = sizeof(dpb_commands_t);
1698 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1699 RETURN_IF((NULL == pv_buf), IV_FAIL);
1700 memset(pv_buf, 0, size);
1701 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1702
1703 size = sizeof(dec_bit_stream_t);
1704 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1705 RETURN_IF((NULL == pv_buf), IV_FAIL);
1706 memset(pv_buf, 0, size);
1707 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1708
1709 size = sizeof(dec_slice_params_t);
1710 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1711 RETURN_IF((NULL == pv_buf), IV_FAIL);
1712 memset(pv_buf, 0, size);
1713 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1714
1715 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1716 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1717 RETURN_IF((NULL == pv_buf), IV_FAIL);
1718 memset(pv_buf, 0, size);
1719 ps_dec->pv_scratch_sps_pps = pv_buf;
1720
1721
1722 ps_dec->u4_static_bits_buf_size = 256000;
1723 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1724 RETURN_IF((NULL == pv_buf), IV_FAIL);
1725 memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1726 ps_dec->pu1_bits_buf_static = pv_buf;
1727
1728
1729 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1730 * sizeof(void *));
1731 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1732 RETURN_IF((NULL == pv_buf), IV_FAIL);
1733 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1734 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1735
1736 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1737
1738
1739 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1740 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1741 RETURN_IF((NULL == pv_buf), IV_FAIL);
1742 memset(pv_buf, 0, size);
1743 ps_dec->p_cabac_ctxt_table_t = pv_buf;
1744
1745
1746
1747 size = sizeof(ctxt_inc_mb_info_t);
1748 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1749 RETURN_IF((NULL == pv_buf), IV_FAIL);
1750 memset(pv_buf, 0, size);
1751 ps_dec->ps_left_mb_ctxt_info = pv_buf;
1752
1753
1754
1755 size = MAX_REF_BUF_SIZE * 2;
1756 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1757 RETURN_IF((NULL == pv_buf), IV_FAIL);
1758 memset(pv_buf, 0, size);
1759 ps_dec->pu1_ref_buff_base = pv_buf;
1760 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1761
1762
1763 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1764 * PRED_BUFFER_HEIGHT * 2);
1765 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1766 RETURN_IF((NULL == pv_buf), IV_FAIL);
1767 memset(pv_buf, 0, size);
1768 ps_dec->pi2_pred1 = pv_buf;
1769
1770
1771 size = sizeof(UWORD8) * (MB_LUM_SIZE);
1772 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1773 RETURN_IF((NULL == pv_buf), IV_FAIL);
1774 memset(pv_buf, 0, size);
1775 ps_dec->pu1_temp_mc_buffer = pv_buf;
1776
1777
1778
1779
1780 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1781 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1782 RETURN_IF((NULL == pv_buf), IV_FAIL);
1783 memset(pv_buf, 0, size);
1784
1785 ps_dec->pu1_init_dpb_base = pv_buf;
1786 pu1_buf = pv_buf;
1787 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1788
1789 pu1_buf += size / 2;
1790 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1791
1792 size = (sizeof(UWORD32) * 2 * 3
1793 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1794 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1795 RETURN_IF((NULL == pv_buf), IV_FAIL);
1796 memset(pv_buf, 0, size);
1797 ps_dec->pu4_mbaff_wt_mat = pv_buf;
1798
1799 size = sizeof(UWORD32) * 2 * 3
1800 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1801 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1802 RETURN_IF((NULL == pv_buf), IV_FAIL);
1803 memset(pv_buf, 0, size);
1804 ps_dec->pu4_wts_ofsts_mat = pv_buf;
1805
1806
1807 size = (sizeof(neighbouradd_t) << 2);
1808 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1809 RETURN_IF((NULL == pv_buf), IV_FAIL);
1810 memset(pv_buf, 0, size);
1811 ps_dec->ps_left_mvpred_addr = pv_buf;
1812
1813
1814 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1815 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1816 RETURN_IF((NULL == pv_buf), IV_FAIL);
1817 memset(pv_buf, 0, size);
1818 ps_dec->pv_mv_buf_mgr = pv_buf;
1819
1820
1821 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1822 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1823 RETURN_IF((NULL == pv_buf), IV_FAIL);
1824 ps_dec->ps_col_mv_base = pv_buf;
1825 memset(ps_dec->ps_col_mv_base, 0, size);
1826
1827 ih264d_init_decoder(ps_dec);
1828
1829 return IV_SUCCESS;
1830 }
1831
1832
1833 /*****************************************************************************/
1834 /* */
1835 /* Function Name : ih264d_create */
1836 /* */
1837 /* Description : creates decoder */
1838 /* */
1839 /* Inputs :iv_obj_t decoder handle */
1840 /* :pv_api_ip pointer to input structure */
1841 /* :pv_api_op pointer to output structure */
1842 /* Outputs : */
1843 /* Returns : void */
1844 /* */
1845 /* Issues : none */
1846 /* */
1847 /* Revision History: */
1848 /* */
1849 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1850 /* 22 10 2008 100356 Draft */
1851 /* */
1852 /*****************************************************************************/
ih264d_create(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1853 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1854 {
1855 ih264d_create_ip_t *ps_create_ip;
1856 ih264d_create_op_t *ps_create_op;
1857
1858 WORD32 ret;
1859
1860 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1861 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1862
1863 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1864 dec_hdl = NULL;
1865 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1866
1867 /* If allocation of some buffer fails, then free buffers allocated till then */
1868 if(IV_FAIL == ret)
1869 {
1870 if(dec_hdl)
1871 {
1872 if(dec_hdl->pv_codec_handle)
1873 {
1874 ih264d_free_static_bufs(dec_hdl);
1875 }
1876 else
1877 {
1878 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1879 void *pv_mem_ctxt;
1880
1881 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1882 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1883 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1884 }
1885 }
1886 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1887 ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1888
1889 return IV_FAIL;
1890 }
1891
1892 return IV_SUCCESS;
1893 }
1894
1895 /*****************************************************************************/
1896 /* */
1897 /* Function Name : ih264d_map_error */
1898 /* */
1899 /* Description : Maps error codes to IVD error groups */
1900 /* */
1901 /* Inputs : */
1902 /* Globals : <Does it use any global variables?> */
1903 /* Outputs : */
1904 /* Returns : void */
1905 /* */
1906 /* Issues : none */
1907 /* */
1908 /* Revision History: */
1909 /* */
1910 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1911 /* 22 10 2008 100356 Draft */
1912 /* */
1913 /*****************************************************************************/
ih264d_map_error(UWORD32 i4_err_status)1914 UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1915 {
1916 UWORD32 temp = 0;
1917
1918 switch(i4_err_status)
1919 {
1920 case ERROR_MEM_ALLOC_ISRAM_T:
1921 case ERROR_MEM_ALLOC_SDRAM_T:
1922 case ERROR_BUF_MGR:
1923 case ERROR_MB_GROUP_ASSGN_T:
1924 case ERROR_FRAME_LIMIT_OVER:
1925 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1926 case ERROR_PROFILE_NOT_SUPPORTED:
1927 case ERROR_INIT_NOT_DONE:
1928 case IVD_MEM_ALLOC_FAILED:
1929 case ERROR_FEATURE_UNAVAIL:
1930 case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1931 temp = 1 << IVD_FATALERROR;
1932 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1933 break;
1934
1935 case ERROR_DBP_MANAGER_T:
1936 case ERROR_GAPS_IN_FRM_NUM:
1937 case ERROR_UNKNOWN_NAL:
1938 case ERROR_INV_MB_SLC_GRP_T:
1939 case ERROR_MULTIPLE_SLC_GRP_T:
1940 case ERROR_UNKNOWN_LEVEL:
1941 case ERROR_UNAVAIL_PICBUF_T:
1942 case ERROR_UNAVAIL_MVBUF_T:
1943 case ERROR_UNAVAIL_DISPBUF_T:
1944 case ERROR_NUM_REF:
1945 case ERROR_REFIDX_ORDER_T:
1946 case ERROR_PIC0_NOT_FOUND_T:
1947 case ERROR_MB_TYPE:
1948 case ERROR_SUB_MB_TYPE:
1949 case ERROR_CBP:
1950 case ERROR_REF_IDX:
1951 case ERROR_NUM_MV:
1952 case ERROR_CHROMA_PRED_MODE:
1953 case ERROR_INTRAPRED:
1954 case ERROR_NEXT_MB_ADDRESS_T:
1955 case ERROR_MB_ADDRESS_T:
1956 case ERROR_PIC1_NOT_FOUND_T:
1957 case ERROR_CAVLC_NUM_COEFF_T:
1958 case ERROR_CAVLC_SCAN_POS_T:
1959 case ERROR_PRED_WEIGHT_TABLE_T:
1960 case ERROR_CORRUPTED_SLICE:
1961 temp = 1 << IVD_CORRUPTEDDATA;
1962 break;
1963
1964 case ERROR_NOT_SUPP_RESOLUTION:
1965 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1966 temp = 1 << IVD_UNSUPPORTEDINPUT;
1967 break;
1968
1969 case ERROR_INVALID_PIC_PARAM:
1970 case ERROR_INVALID_SEQ_PARAM:
1971 case ERROR_EGC_EXCEED_32_1_T:
1972 case ERROR_EGC_EXCEED_32_2_T:
1973 case ERROR_INV_RANGE_TEV_T:
1974 case ERROR_INV_SLC_TYPE_T:
1975 case ERROR_INV_POC_TYPE_T:
1976 case ERROR_INV_RANGE_QP_T:
1977 case ERROR_INV_SPS_PPS_T:
1978 case ERROR_INV_SLICE_HDR_T:
1979 case ERROR_INV_SEI_MDCV_PARAMS:
1980 case ERROR_INV_SEI_CLL_PARAMS:
1981 case ERROR_INV_SEI_AVE_PARAMS:
1982 case ERROR_INV_SEI_CCV_PARAMS:
1983 case ERROR_INV_SEI_SII_PARAMS:
1984
1985 temp = 1 << IVD_CORRUPTEDHEADER;
1986 break;
1987
1988 case ERROR_EOB_FLUSHBITS_T:
1989 case ERROR_EOB_GETBITS_T:
1990 case ERROR_EOB_GETBIT_T:
1991 case ERROR_EOB_BYPASS_T:
1992 case ERROR_EOB_DECISION_T:
1993 case ERROR_EOB_TERMINATE_T:
1994 case ERROR_EOB_READCOEFF4X4CAB_T:
1995 temp = 1 << IVD_INSUFFICIENTDATA;
1996 break;
1997 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
1998 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
1999 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2000 break;
2001
2002 case ERROR_DANGLING_FIELD_IN_PIC:
2003 temp = 1 << IVD_APPLIEDCONCEALMENT;
2004 break;
2005
2006 }
2007
2008 return temp;
2009
2010 }
2011
ih264d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,UWORD8 u1_chroma_format,UWORD32 * p_buf_size)2012 UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
2013 UWORD32 pic_ht,
2014 UWORD8 u1_chroma_format,
2015 UWORD32 *p_buf_size)
2016 {
2017 UWORD32 u4_min_num_out_bufs = 0;
2018
2019 if(u1_chroma_format == IV_YUV_420P)
2020 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2021 else if(u1_chroma_format == IV_YUV_422ILE)
2022 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2023 else if(u1_chroma_format == IV_RGB_565)
2024 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2025 else if((u1_chroma_format == IV_YUV_420SP_UV)
2026 || (u1_chroma_format == IV_YUV_420SP_VU))
2027 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2028
2029 if(u1_chroma_format == IV_YUV_420P)
2030 {
2031 p_buf_size[0] = (pic_wd * pic_ht);
2032 p_buf_size[1] = (pic_wd * pic_ht) >> 2;
2033 p_buf_size[2] = (pic_wd * pic_ht) >> 2;
2034 }
2035 else if(u1_chroma_format == IV_YUV_422ILE)
2036 {
2037 p_buf_size[0] = (pic_wd * pic_ht) * 2;
2038 p_buf_size[1] = p_buf_size[2] = 0;
2039 }
2040 else if(u1_chroma_format == IV_RGB_565)
2041 {
2042 p_buf_size[0] = (pic_wd * pic_ht) * 2;
2043 p_buf_size[1] = p_buf_size[2] = 0;
2044 }
2045 else if((u1_chroma_format == IV_YUV_420SP_UV)
2046 || (u1_chroma_format == IV_YUV_420SP_VU))
2047 {
2048 p_buf_size[0] = (pic_wd * pic_ht);
2049 p_buf_size[1] = (pic_wd * pic_ht) >> 1;
2050 p_buf_size[2] = 0;
2051 }
2052
2053 return u4_min_num_out_bufs;
2054 }
2055
check_app_out_buf_size(dec_struct_t * ps_dec)2056 WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
2057 {
2058 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2059 UWORD32 u4_min_num_out_bufs, i;
2060 UWORD32 pic_wd, pic_ht;
2061
2062 if(0 == ps_dec->u4_share_disp_buf)
2063 {
2064 pic_wd = ps_dec->u2_disp_width;
2065 pic_ht = ps_dec->u2_disp_height;
2066
2067 }
2068 else
2069 {
2070 pic_wd = ps_dec->u2_frm_wd_y;
2071 pic_ht = ps_dec->u2_frm_ht_y;
2072 }
2073
2074 if(ps_dec->u4_app_disp_width > pic_wd)
2075 pic_wd = ps_dec->u4_app_disp_width;
2076
2077 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
2078 ps_dec->u1_chroma_format,
2079 &au4_min_out_buf_size[0]);
2080
2081
2082 if(0 == ps_dec->u4_share_disp_buf)
2083 {
2084 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
2085 return IV_FAIL;
2086
2087 for(i = 0; i < u4_min_num_out_bufs; i++)
2088 {
2089 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
2090 < au4_min_out_buf_size[i])
2091 return (IV_FAIL);
2092 }
2093 }
2094 else
2095 {
2096 if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
2097 return IV_FAIL;
2098
2099 for(i = 0; i < u4_min_num_out_bufs; i++)
2100 {
2101 /* We need to check only with the disp_buffer[0], because we have
2102 * already ensured that all the buffers are of the same size in
2103 * ih264d_set_display_frame.
2104 */
2105 if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
2106 return (IV_FAIL);
2107 }
2108
2109 }
2110
2111 return (IV_SUCCESS);
2112 }
2113
2114
2115 /*****************************************************************************/
2116 /* */
2117 /* Function Name : ih264d_video_decode */
2118 /* */
2119 /* Description : handle video decode API command */
2120 /* */
2121 /* Inputs :iv_obj_t decoder handle */
2122 /* :pv_api_ip pointer to input structure */
2123 /* :pv_api_op pointer to output structure */
2124 /* Outputs : */
2125 /* Returns : void */
2126 /* */
2127 /* Issues : none */
2128 /* */
2129 /* Revision History: */
2130 /* */
2131 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2132 /* 22 10 2008 100356 Draft */
2133 /* */
2134 /*****************************************************************************/
2135
ih264d_video_decode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2136 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2137 {
2138 /* ! */
2139
2140 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2141
2142 WORD32 i4_err_status = 0;
2143 UWORD8 *pu1_buf = NULL;
2144 WORD32 buflen;
2145 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2146
2147 UWORD32 bytes_consumed = 0;
2148 UWORD32 cur_slice_is_nonref = 0;
2149 UWORD32 u4_next_is_aud;
2150 UWORD32 u4_first_start_code_found = 0;
2151 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
2152 WORD32 header_data_left = 0,frame_data_left = 0;
2153 UWORD8 *pu1_bitstrm_buf;
2154 ih264d_video_decode_ip_t *ps_h264d_dec_ip;
2155 ih264d_video_decode_op_t *ps_h264d_dec_op;
2156 ivd_video_decode_ip_t *ps_dec_ip;
2157 ivd_video_decode_op_t *ps_dec_op;
2158
2159 ithread_set_name((void*)"Parse_thread");
2160
2161 ps_h264d_dec_ip = (ih264d_video_decode_ip_t *)pv_api_ip;
2162 ps_h264d_dec_op = (ih264d_video_decode_op_t *)pv_api_op;
2163 ps_dec_ip = &ps_h264d_dec_ip->s_ivd_video_decode_ip_t;
2164 ps_dec_op = &ps_h264d_dec_op->s_ivd_video_decode_op_t;
2165
2166 {
2167 UWORD32 u4_size;
2168 u4_size = ps_dec_op->u4_size;
2169 memset(ps_h264d_dec_op, 0, ps_dec_op->u4_size);
2170 ps_dec_op->u4_size = u4_size;
2171 }
2172
2173 ps_dec->pv_dec_out = ps_dec_op;
2174 if(ps_dec->init_done != 1)
2175 {
2176 return IV_FAIL;
2177 }
2178
2179 /*Data memory barries instruction,so that bitstream write by the application is complete*/
2180 DATA_SYNC();
2181
2182 if(0 == ps_dec->u1_flushfrm)
2183 {
2184 if(ps_dec_ip->pv_stream_buffer == NULL)
2185 {
2186 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2187 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2188 return IV_FAIL;
2189 }
2190 if(ps_dec_ip->u4_num_Bytes <= 0)
2191 {
2192 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2193 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2194 return IV_FAIL;
2195
2196 }
2197 }
2198 ps_dec->u1_pic_decode_done = 0;
2199
2200 #ifdef KEEP_THREADS_ACTIVE
2201 {
2202 UWORD32 i;
2203 ps_dec->i4_break_threads = 0;
2204 for (i = 0; i < 2; i++)
2205 {
2206 ret = ithread_mutex_lock(ps_dec->apv_proc_start_mutex[i]);
2207 RETURN_IF((ret != IV_SUCCESS), ret);
2208
2209 ps_dec->ai4_process_start[i] = PROC_INIT;
2210
2211 ret = ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[i]);
2212 RETURN_IF((ret != IV_SUCCESS), ret);
2213 }
2214 }
2215 #else
2216 ps_dec->u4_dec_thread_created = 0;
2217 ps_dec->u4_bs_deblk_thread_created = 0;
2218 #endif
2219
2220 ps_dec_op->u4_num_bytes_consumed = 0;
2221 ps_dec_op->i4_reorder_depth = -1;
2222 ps_dec_op->i4_display_index = DEFAULT_POC;
2223 ps_dec->ps_out_buffer = NULL;
2224
2225 if(ps_dec_ip->u4_size
2226 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2227 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2228
2229 ps_dec->u4_fmt_conv_cur_row = 0;
2230
2231 ps_dec->u4_output_present = 0;
2232 ps_dec->s_disp_op.u4_error_code = 1;
2233 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2234 if(0 == ps_dec->u4_share_disp_buf
2235 && ps_dec->i4_decode_header == 0)
2236 {
2237 UWORD32 i;
2238 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
2239 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
2240 {
2241 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2242 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2243 return IV_FAIL;
2244 }
2245
2246 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2247 {
2248 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2249 {
2250 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2251 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2252 return IV_FAIL;
2253 }
2254
2255 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2256 {
2257 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2258 ps_dec_op->u4_error_code |=
2259 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2260 return IV_FAIL;
2261 }
2262 }
2263 }
2264
2265 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2266 {
2267 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2268 return IV_FAIL;
2269 }
2270
2271 /* ! */
2272 ps_dec->u4_ts = ps_dec_ip->u4_ts;
2273
2274 ps_dec_op->u4_error_code = 0;
2275 ps_dec_op->e_pic_type = IV_NA_FRAME;
2276 ps_dec_op->u4_output_present = 0;
2277 ps_dec_op->u4_frame_decoded_flag = 0;
2278
2279 ps_dec->i4_frametype = IV_NA_FRAME;
2280 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
2281
2282 ps_dec->u4_slice_start_code_found = 0;
2283
2284 /* In case the decoder is not in flush mode(in shared mode),
2285 then decoder has to pick up a buffer to write current frame.
2286 Check if a frame is available in such cases */
2287
2288 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2289 && ps_dec->u1_flushfrm == 0)
2290 {
2291 UWORD32 i;
2292
2293 WORD32 disp_avail = 0, free_id;
2294
2295 /* Check if at least one buffer is available with the codec */
2296 /* If not then return to application with error */
2297 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2298 {
2299 if(0 == ps_dec->u4_disp_buf_mapping[i]
2300 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2301 {
2302 disp_avail = 1;
2303 break;
2304 }
2305
2306 }
2307
2308 if(0 == disp_avail)
2309 {
2310 /* If something is queued for display wait for that buffer to be returned */
2311
2312 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2313 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2314 return (IV_FAIL);
2315 }
2316
2317 while(1)
2318 {
2319 pic_buffer_t *ps_pic_buf;
2320 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2321 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2322
2323 if(ps_pic_buf == NULL)
2324 {
2325 UWORD32 display_queued = 0;
2326
2327 /* check if any buffer was given for display which is not returned yet */
2328 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2329 {
2330 if(0 != ps_dec->u4_disp_buf_mapping[i])
2331 {
2332 display_queued = 1;
2333 break;
2334 }
2335 }
2336 /* If some buffer is queued for display, then codec has to singal an error and wait
2337 for that buffer to be returned.
2338 If nothing is queued for display then codec has ownership of all display buffers
2339 and it can reuse any of the existing buffers and continue decoding */
2340
2341 if(1 == display_queued)
2342 {
2343 /* If something is queued for display wait for that buffer to be returned */
2344 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2345 ps_dec_op->u4_error_code |= (1
2346 << IVD_UNSUPPORTEDPARAM);
2347 return (IV_FAIL);
2348 }
2349 }
2350 else
2351 {
2352 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2353 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2354 {
2355 ih264_buf_mgr_set_status(
2356 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2357 free_id,
2358 BUF_MGR_IO);
2359 }
2360 else
2361 {
2362 /**
2363 * Found a free buffer for present call. Release it now.
2364 * Will be again obtained later.
2365 */
2366 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2367 free_id,
2368 BUF_MGR_IO);
2369 break;
2370 }
2371 }
2372 }
2373
2374 }
2375
2376 if(ps_dec->u1_enable_mb_info && (ps_dec->i4_header_decoded & DECODED_SPS_MASK))
2377 {
2378 UWORD32 blk_qp_map_size = ps_h264d_dec_ip->u4_8x8_blk_qp_map_size;
2379 UWORD32 blk_type_map_size = ps_h264d_dec_ip->u4_8x8_blk_type_map_size;
2380 UWORD32 blk_8x8_map_size = ps_dec->u4_total_mbs << 2;
2381 if ((ps_h264d_dec_ip->pu1_8x8_blk_qp_map && blk_qp_map_size < blk_8x8_map_size) ||
2382 (ps_h264d_dec_ip->pu1_8x8_blk_type_map && blk_type_map_size < blk_8x8_map_size))
2383 {
2384 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2385 ps_dec_op->u4_error_code |= IH264D_INSUFFICIENT_METADATA_BUFFER;
2386 return IV_FAIL;
2387 }
2388 }
2389
2390 if(ps_dec->u1_flushfrm)
2391 {
2392 if(ps_dec->u1_init_dec_flag == 0)
2393 {
2394 /*Come out of flush mode and return*/
2395 ps_dec->u1_flushfrm = 0;
2396 return (IV_FAIL);
2397 }
2398
2399
2400
2401 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2402 &(ps_dec->s_disp_op));
2403 if(0 == ps_dec->s_disp_op.u4_error_code)
2404 {
2405 /* check output buffer size given by the application */
2406 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2407 {
2408 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2409 return (IV_FAIL);
2410 }
2411
2412 ps_dec->u4_fmt_conv_cur_row = 0;
2413 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2414 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2415 ps_dec->u4_fmt_conv_cur_row,
2416 ps_dec->u4_fmt_conv_num_rows);
2417 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2418 ps_dec->u4_output_present = 1;
2419
2420 if(ps_dec->u1_enable_mb_info)
2421 {
2422 UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2423 if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2424 {
2425 ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2426 ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2427 ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2428 ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2429 ps_dec->u4_total_mbs << 2);
2430 }
2431 if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2432 {
2433 ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2434 ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2435 ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2436 ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2437 ps_dec->u4_total_mbs << 2);
2438 }
2439 }
2440 }
2441 ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
2442
2443 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2444
2445 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2446 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2447 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2448 ps_dec_op->i4_display_index = ps_dec->i4_display_index;
2449
2450 ps_dec_op->u4_new_seq = 0;
2451
2452 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2453 ps_dec_op->u4_progressive_frame_flag =
2454 ps_dec->s_disp_op.u4_progressive_frame_flag;
2455 ps_dec_op->e_output_format =
2456 ps_dec->s_disp_op.e_output_format;
2457 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2458 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2459 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2460 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2461
2462 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2463 ps_dec_op->u4_is_ref_flag = -1;
2464 ps_dec_op->e_pic_type = IV_NA_FRAME;
2465 ps_dec_op->u4_frame_decoded_flag = 0;
2466
2467 if(0 == ps_dec->s_disp_op.u4_error_code)
2468 {
2469 return (IV_SUCCESS);
2470 }
2471 else
2472 return (IV_FAIL);
2473
2474 }
2475 if(ps_dec->u1_res_changed == 1)
2476 {
2477 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2478 ih264d_init_decoder(ps_dec);
2479 }
2480
2481 ps_dec->u2_cur_mb_addr = 0;
2482 ps_dec->u2_total_mbs_coded = 0;
2483 ps_dec->u2_cur_slice_num = 0;
2484 ps_dec->cur_dec_mb_num = 0;
2485 ps_dec->cur_recon_mb_num = 0;
2486 ps_dec->u4_first_slice_in_pic = 1;
2487 ps_dec->u1_slice_header_done = 0;
2488 ps_dec->u1_dangling_field = 0;
2489 ps_dec->u4_cur_bs_mb_num = 0;
2490 ps_dec->u4_start_recon_deblk = 0;
2491 ps_dec->u4_sps_cnt_in_process = 0;
2492
2493 DEBUG_THREADS_PRINTF(" Starting process call\n");
2494
2495
2496 ps_dec->u4_pic_buf_got = 0;
2497
2498 do
2499 {
2500 WORD32 buf_size;
2501
2502 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2503 + ps_dec_op->u4_num_bytes_consumed;
2504
2505 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2506 - ps_dec_op->u4_num_bytes_consumed;
2507
2508 /* If dynamic bitstream buffer is not allocated and
2509 * header decode is done, then allocate dynamic bitstream buffer
2510 */
2511 if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2512 (ps_dec->i4_header_decoded & 1))
2513 {
2514 WORD32 size;
2515
2516 void *pv_buf;
2517 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2518 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2519 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2520 size + EXTRA_BS_OFFSET);
2521 RETURN_IF((NULL == pv_buf), IV_FAIL);
2522 memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2523 ps_dec->pu1_bits_buf_dynamic = pv_buf;
2524 ps_dec->u4_dynamic_bits_buf_size = size;
2525 }
2526
2527 if(ps_dec->pu1_bits_buf_dynamic)
2528 {
2529 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2530 buf_size = ps_dec->u4_dynamic_bits_buf_size;
2531 }
2532 else
2533 {
2534 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2535 buf_size = ps_dec->u4_static_bits_buf_size;
2536 }
2537
2538 u4_next_is_aud = 0;
2539
2540 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2541 &u4_length_of_start_code,
2542 &u4_next_is_aud);
2543
2544 if(buflen == -1)
2545 buflen = 0;
2546 /* Ignore bytes beyond the allocated size of intermediate buffer */
2547 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2548 end of the buffer, which will be memset to 0 after emulation prevention */
2549 buflen = MIN(buflen, buf_size - 8);
2550
2551 bytes_consumed = buflen + u4_length_of_start_code;
2552 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2553
2554 if(buflen)
2555 {
2556 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2557 buflen);
2558 /* Decoder may read extra 8 bytes near end of the frame */
2559 if((buflen + 8) < buf_size)
2560 {
2561 memset(pu1_bitstrm_buf + buflen, 0, 8);
2562 }
2563 u4_first_start_code_found = 1;
2564
2565 }
2566 else
2567 {
2568 /*start code not found*/
2569
2570 if(u4_first_start_code_found == 0)
2571 {
2572 /*no start codes found in current process call*/
2573
2574 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2575 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2576
2577 if(ps_dec->u4_pic_buf_got == 0)
2578 {
2579
2580 ih264d_fill_output_struct_from_context(ps_dec,
2581 ps_dec_op);
2582
2583 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2584 ps_dec_op->u4_frame_decoded_flag = 0;
2585
2586 return (IV_FAIL);
2587 }
2588 else
2589 {
2590 ps_dec->u1_pic_decode_done = 1;
2591 continue;
2592 }
2593 }
2594 else
2595 {
2596 /* a start code has already been found earlier in the same process call*/
2597 frame_data_left = 0;
2598 header_data_left = 0;
2599 continue;
2600 }
2601
2602 }
2603
2604 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2605 pu1_bitstrm_buf, buflen);
2606 if(ret != OK)
2607 {
2608 UWORD32 error = ih264d_map_error(ret);
2609 ps_dec_op->u4_error_code = error | ret;
2610 api_ret_value = IV_FAIL;
2611
2612 if((ret == IVD_RES_CHANGED)
2613 || (ret == IVD_MEM_ALLOC_FAILED)
2614 || (ret == ERROR_UNAVAIL_PICBUF_T)
2615 || (ret == ERROR_UNAVAIL_MVBUF_T)
2616 || (ret == ERROR_INV_SPS_PPS_T)
2617 || (ret == ERROR_FEATURE_UNAVAIL)
2618 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2619 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2620 {
2621 ps_dec->u4_slice_start_code_found = 0;
2622 break;
2623 }
2624
2625 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2626 {
2627 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2628 api_ret_value = IV_FAIL;
2629 break;
2630 }
2631
2632 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2633 {
2634 api_ret_value = IV_FAIL;
2635 break;
2636 }
2637
2638 }
2639
2640 header_data_left = ((ps_dec->i4_decode_header == 1)
2641 && (ps_dec->i4_header_decoded != 3)
2642 && (ps_dec_op->u4_num_bytes_consumed
2643 < ps_dec_ip->u4_num_Bytes));
2644 frame_data_left = (((ps_dec->i4_decode_header == 0)
2645 && ((ps_dec->u1_pic_decode_done == 0)
2646 || (u4_next_is_aud == 1)))
2647 && (ps_dec_op->u4_num_bytes_consumed
2648 < ps_dec_ip->u4_num_Bytes));
2649 }
2650 while(( header_data_left == 1)||(frame_data_left == 1));
2651
2652 if((ps_dec->u4_pic_buf_got == 1)
2653 && (ret != IVD_MEM_ALLOC_FAILED)
2654 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2655 {
2656 // last slice - missing/corruption
2657 WORD32 num_mb_skipped;
2658 WORD32 prev_slice_err;
2659 pocstruct_t temp_poc;
2660 WORD32 ret1;
2661 WORD32 ht_in_mbs;
2662 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2663 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2664 - ps_dec->u2_total_mbs_coded;
2665
2666 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2667 prev_slice_err = 1;
2668 else
2669 prev_slice_err = 2;
2670
2671 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
2672 prev_slice_err = 1;
2673
2674 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2675 &temp_poc, prev_slice_err);
2676
2677 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2678 (ret1 == ERROR_INV_SPS_PPS_T))
2679 {
2680 ret = ret1;
2681 }
2682 }
2683
2684 if((ret == IVD_RES_CHANGED)
2685 || (ret == IVD_MEM_ALLOC_FAILED)
2686 || (ret == ERROR_UNAVAIL_PICBUF_T)
2687 || (ret == ERROR_UNAVAIL_MVBUF_T)
2688 || (ret == ERROR_INV_SPS_PPS_T))
2689 {
2690
2691 /* signal the decode thread */
2692 ih264d_signal_decode_thread(ps_dec);
2693 /* close deblock thread if it is not closed yet */
2694 if(ps_dec->u4_num_cores == 3)
2695 {
2696 ih264d_signal_bs_deblk_thread(ps_dec);
2697 }
2698 /* dont consume bitstream for change in resolution case */
2699 if(ret == IVD_RES_CHANGED)
2700 {
2701 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2702 }
2703 return IV_FAIL;
2704 }
2705
2706
2707 if(ps_dec->u1_separate_parse)
2708 {
2709 /* If Format conversion is not complete,
2710 complete it here */
2711 if(ps_dec->u4_num_cores == 2)
2712 {
2713
2714 /*do deblocking of all mbs*/
2715 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2716 {
2717 UWORD32 u4_num_mbs,u4_max_addr;
2718 tfr_ctxt_t s_tfr_ctxt;
2719 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2720 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2721
2722 /*BS is done for all mbs while parsing*/
2723 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2724 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2725
2726
2727 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2728 ps_dec->u2_frm_wd_in_mbs, 0);
2729
2730
2731 u4_num_mbs = u4_max_addr
2732 - ps_dec->u4_cur_deblk_mb_num + 1;
2733
2734 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2735
2736 if(u4_num_mbs != 0)
2737 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2738 ps_tfr_cxt,1);
2739
2740 ps_dec->u4_start_recon_deblk = 0;
2741
2742 }
2743
2744 }
2745
2746 /*signal the decode thread*/
2747 ih264d_signal_decode_thread(ps_dec);
2748 /* close deblock thread if it is not closed yet*/
2749 if(ps_dec->u4_num_cores == 3)
2750 {
2751 ih264d_signal_bs_deblk_thread(ps_dec);
2752 }
2753 }
2754
2755
2756 DATA_SYNC();
2757
2758
2759 if((ps_dec_op->u4_error_code & 0xff)
2760 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2761 {
2762 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2763 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2764 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2765 }
2766
2767 //Report if header (sps and pps) has not been decoded yet
2768 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2769 {
2770 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2771 api_ret_value = IV_FAIL;
2772 }
2773
2774 if((ps_dec->u4_pic_buf_got == 1)
2775 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2776 {
2777 /*
2778 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2779 */
2780
2781 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2782 {
2783 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2784 {
2785 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2786 }
2787 else
2788 {
2789 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2790 }
2791 }
2792 else
2793 {
2794 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2795 }
2796
2797 /* if new frame in not found (if we are still getting slices from previous frame)
2798 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2799 */
2800 if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2801 {
2802 /* Calling Function to deblock Picture and Display */
2803 ret = ih264d_deblock_display(ps_dec);
2804 }
2805
2806
2807 /*set to complete ,as we dont support partial frame decode*/
2808 if(ps_dec->i4_header_decoded == 3)
2809 {
2810 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
2811 }
2812
2813 /*Update the i4_frametype at the end of picture*/
2814 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2815 {
2816 ps_dec->i4_frametype = IV_IDR_FRAME;
2817 }
2818 else if(ps_dec->i4_pic_type == B_SLICE)
2819 {
2820 ps_dec->i4_frametype = IV_B_FRAME;
2821 }
2822 else if(ps_dec->i4_pic_type == P_SLICE)
2823 {
2824 ps_dec->i4_frametype = IV_P_FRAME;
2825 }
2826 else if(ps_dec->i4_pic_type == I_SLICE)
2827 {
2828 ps_dec->i4_frametype = IV_I_FRAME;
2829 }
2830 else
2831 {
2832 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2833 }
2834
2835 //Update the content type
2836 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2837
2838 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2839 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2840 - ps_dec->ps_cur_slice->u1_field_pic_flag;
2841
2842 }
2843
2844 /* close deblock thread if it is not closed yet*/
2845 #ifndef KEEP_THREADS_ACTIVE
2846 if(ps_dec->u4_num_cores == 3)
2847 {
2848 ih264d_signal_bs_deblk_thread(ps_dec);
2849 }
2850 #endif
2851
2852
2853 {
2854 /* In case the decoder is configured to run in low delay mode,
2855 * then get display buffer and then format convert.
2856 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2857 */
2858
2859 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2860 && ps_dec->u1_init_dec_flag)
2861 {
2862
2863 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2864 &(ps_dec->s_disp_op));
2865 if(0 == ps_dec->s_disp_op.u4_error_code)
2866 {
2867 ps_dec->u4_fmt_conv_cur_row = 0;
2868 ps_dec->u4_output_present = 1;
2869 }
2870 }
2871
2872 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2873
2874 /* If Format conversion is not complete,
2875 complete it here */
2876 if(ps_dec->u4_output_present &&
2877 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2878 {
2879 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2880 - ps_dec->u4_fmt_conv_cur_row;
2881 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2882 ps_dec->u4_fmt_conv_cur_row,
2883 ps_dec->u4_fmt_conv_num_rows);
2884 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2885 }
2886
2887 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2888 }
2889
2890 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2891 {
2892 ps_dec_op->u4_progressive_frame_flag = 1;
2893 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2894 {
2895 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2896 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2897 ps_dec_op->u4_progressive_frame_flag = 0;
2898
2899 }
2900 }
2901
2902 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2903 {
2904 ps_dec->u1_top_bottom_decoded = 0;
2905 }
2906 /*--------------------------------------------------------------------*/
2907 /* Do End of Pic processing. */
2908 /* Should be called only if frame was decoded in previous process call*/
2909 /*--------------------------------------------------------------------*/
2910 if(ps_dec->u4_pic_buf_got == 1)
2911 {
2912 if(1 == ps_dec->u1_last_pic_not_decoded)
2913 {
2914 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2915
2916 if(ret != OK)
2917 return ret;
2918
2919 ret = ih264d_end_of_pic(ps_dec);
2920 if(ret != OK)
2921 return ret;
2922 }
2923 else
2924 {
2925 ret = ih264d_end_of_pic(ps_dec);
2926 if(ret != OK)
2927 return ret;
2928 }
2929
2930 }
2931
2932 if(ps_dec->u1_enable_mb_info && ps_dec->u4_output_present)
2933 {
2934 UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2935 if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2936 {
2937 ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2938 ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2939 ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2940 ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2941 ps_dec->u4_total_mbs << 2);
2942 }
2943 if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2944 {
2945 ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2946 ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2947 ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2948 ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2949 ps_dec->u4_total_mbs << 2);
2950 }
2951 }
2952
2953 /*Data memory barrier instruction,so that yuv write by the library is complete*/
2954 DATA_SYNC();
2955
2956 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2957 ps_dec_op->u4_num_bytes_consumed);
2958 return api_ret_value;
2959 }
2960
ih264d_get_version(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2961 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2962 {
2963 char version_string[MAXVERSION_STRLEN + 1];
2964 UWORD32 version_string_len;
2965
2966 ivd_ctl_getversioninfo_ip_t *ps_ip;
2967 ivd_ctl_getversioninfo_op_t *ps_op;
2968
2969 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2970 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2971 UNUSED(dec_hdl);
2972 ps_op->u4_error_code = IV_SUCCESS;
2973
2974 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2975 CODEC_VENDOR);
2976
2977 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2978 {
2979 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2980 return (IV_FAIL);
2981 }
2982
2983 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2984
2985 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
2986 {
2987 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
2988 ps_op->u4_error_code = IV_SUCCESS;
2989 }
2990 else
2991 {
2992 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2993 return IV_FAIL;
2994 }
2995 return (IV_SUCCESS);
2996 }
2997
2998 /*****************************************************************************/
2999 /* */
3000 /* Function Name : ih264d_get_display_frame */
3001 /* */
3002 /* Description : */
3003 /* Inputs :iv_obj_t decoder handle */
3004 /* :pv_api_ip pointer to input structure */
3005 /* :pv_api_op pointer to output structure */
3006 /* Outputs : */
3007 /* Returns : void */
3008 /* */
3009 /* Issues : none */
3010 /* */
3011 /* Revision History: */
3012 /* */
3013 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3014 /* 22 10 2008 100356 Draft */
3015 /* */
3016 /*****************************************************************************/
ih264d_get_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3017 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3018 void *pv_api_ip,
3019 void *pv_api_op)
3020 {
3021
3022 UNUSED(dec_hdl);
3023 UNUSED(pv_api_ip);
3024 UNUSED(pv_api_op);
3025 // This function is no longer needed, output is returned in the process()
3026 return IV_FAIL;
3027 }
3028
3029 /*****************************************************************************/
3030 /* */
3031 /* Function Name : ih264d_set_display_frame */
3032 /* */
3033 /* Description : */
3034 /* */
3035 /* Inputs :iv_obj_t decoder handle */
3036 /* :pv_api_ip pointer to input structure */
3037 /* :pv_api_op pointer to output structure */
3038 /* Outputs : */
3039 /* Returns : void */
3040 /* */
3041 /* Issues : none */
3042 /* */
3043 /* Revision History: */
3044 /* */
3045 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3046 /* 22 10 2008 100356 Draft */
3047 /* */
3048 /*****************************************************************************/
ih264d_set_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3049 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3050 void *pv_api_ip,
3051 void *pv_api_op)
3052 {
3053
3054 UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
3055 ivd_set_display_frame_ip_t *dec_disp_ip;
3056 ivd_set_display_frame_op_t *dec_disp_op;
3057
3058 UWORD32 i;
3059 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3060
3061 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3062 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3063 dec_disp_op->u4_error_code = 0;
3064
3065
3066 ps_dec->u4_num_disp_bufs = 0;
3067 if(ps_dec->u4_share_disp_buf)
3068 {
3069 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3070
3071 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3072
3073 ps_dec->u4_num_disp_bufs = u4_num_bufs;
3074
3075 /* Get the number and sizes of the first buffer. Compare this with the
3076 * rest to make sure all the buffers are of the same size.
3077 */
3078 u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
3079
3080 u4_disp_buf_size[0] =
3081 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
3082 u4_disp_buf_size[1] =
3083 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
3084 u4_disp_buf_size[2] =
3085 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
3086
3087 for(i = 0; i < u4_num_bufs; i++)
3088 {
3089 if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
3090 {
3091 return IV_FAIL;
3092 }
3093
3094 if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
3095 != u4_disp_buf_size[0])
3096 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
3097 != u4_disp_buf_size[1])
3098 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
3099 != u4_disp_buf_size[2]))
3100 {
3101 return IV_FAIL;
3102 }
3103
3104 ps_dec->disp_bufs[i].u4_num_bufs =
3105 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3106
3107 ps_dec->disp_bufs[i].buf[0] =
3108 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3109 ps_dec->disp_bufs[i].buf[1] =
3110 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3111 ps_dec->disp_bufs[i].buf[2] =
3112 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3113
3114 ps_dec->disp_bufs[i].u4_bufsize[0] =
3115 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3116 ps_dec->disp_bufs[i].u4_bufsize[1] =
3117 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3118 ps_dec->disp_bufs[i].u4_bufsize[2] =
3119 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3120
3121 }
3122 }
3123 return IV_SUCCESS;
3124
3125 }
3126
3127 /*****************************************************************************/
3128 /* */
3129 /* Function Name : ih264d_set_flush_mode */
3130 /* */
3131 /* Description : */
3132 /* */
3133 /* Inputs :iv_obj_t decoder handle */
3134 /* :pv_api_ip pointer to input structure */
3135 /* :pv_api_op pointer to output structure */
3136 /* Globals : <Does it use any global variables?> */
3137 /* Outputs : */
3138 /* Returns : void */
3139 /* */
3140 /* Issues : none */
3141 /* */
3142 /* Revision History: */
3143 /* */
3144 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3145 /* 22 10 2008 100356 Draft */
3146 /* */
3147 /*****************************************************************************/
ih264d_set_flush_mode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3148 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3149 {
3150 dec_struct_t * ps_dec;
3151 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3152 ps_ctl_op->u4_error_code = 0;
3153
3154 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3155 UNUSED(pv_api_ip);
3156 /* ! */
3157 /* Signal flush frame control call */
3158 ps_dec->u1_flushfrm = 1;
3159
3160 if(ps_dec->u1_init_dec_flag == 1)
3161 {
3162 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
3163 ih264d_release_display_bufs(ps_dec);
3164 }
3165
3166 ps_ctl_op->u4_error_code = 0;
3167
3168 /* Ignore dangling fields during flush */
3169 ps_dec->u1_top_bottom_decoded = 0;
3170
3171 return IV_SUCCESS;
3172 }
3173
3174 /*****************************************************************************/
3175 /* */
3176 /* Function Name : ih264d_get_status */
3177 /* */
3178 /* Description : */
3179 /* */
3180 /* Inputs :iv_obj_t decoder handle */
3181 /* :pv_api_ip pointer to input structure */
3182 /* :pv_api_op pointer to output structure */
3183 /* Globals : <Does it use any global variables?> */
3184 /* Outputs : */
3185 /* Returns : void */
3186 /* */
3187 /* Issues : none */
3188 /* */
3189 /* Revision History: */
3190 /* */
3191 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3192 /* 22 10 2008 100356 Draft */
3193 /* */
3194 /*****************************************************************************/
3195
ih264d_get_status(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3196 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3197 {
3198
3199 UWORD32 i;
3200 dec_struct_t * ps_dec;
3201 UWORD32 pic_wd, pic_ht;
3202 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3203 UNUSED(pv_api_ip);
3204 ps_ctl_op->u4_error_code = 0;
3205
3206 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3207
3208
3209 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3210 {
3211 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3212 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3213
3214 if(0 == ps_dec->u4_share_disp_buf)
3215 {
3216 pic_wd = ps_dec->u2_disp_width;
3217 pic_ht = ps_dec->u2_disp_height;
3218
3219 }
3220 else
3221 {
3222 pic_wd = ps_dec->u2_frm_wd_y;
3223 pic_ht = ps_dec->u2_frm_ht_y;
3224 }
3225 }
3226 else
3227 {
3228 pic_wd = 0;
3229 pic_ht = 0;
3230
3231 ps_ctl_op->u4_pic_ht = pic_wd;
3232 ps_ctl_op->u4_pic_wd = pic_ht;
3233
3234 if(1 == ps_dec->u4_share_disp_buf)
3235 {
3236 pic_wd += (PAD_LEN_Y_H << 1);
3237 pic_ht += (PAD_LEN_Y_V << 2);
3238
3239 }
3240
3241 }
3242
3243 if(ps_dec->u4_app_disp_width > pic_wd)
3244 pic_wd = ps_dec->u4_app_disp_width;
3245 if(0 == ps_dec->u4_share_disp_buf)
3246 ps_ctl_op->u4_num_disp_bufs = 1;
3247 else
3248 {
3249 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3250 {
3251 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3252 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3253 {
3254 ps_ctl_op->u4_num_disp_bufs =
3255 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3256 }
3257 else
3258 {
3259 /*if VUI is not present assume maximum possible refrence frames for the level,
3260 * as max reorder frames*/
3261 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3262 }
3263
3264 ps_ctl_op->u4_num_disp_bufs +=
3265 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3266 }
3267 else
3268 {
3269 ps_ctl_op->u4_num_disp_bufs = 32;
3270 }
3271 ps_ctl_op->u4_num_disp_bufs = MAX(
3272 ps_ctl_op->u4_num_disp_bufs, 6);
3273 ps_ctl_op->u4_num_disp_bufs = MIN(
3274 ps_ctl_op->u4_num_disp_bufs, 32);
3275 }
3276
3277 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3278
3279 ps_ctl_op->u4_frame_rate = 0; //make it proper
3280 ps_ctl_op->u4_bit_rate = 0; //make it proper
3281 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3282 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3283 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3284
3285 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3286 {
3287 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3288 }
3289 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3290 {
3291 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3292 }
3293 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3294 {
3295 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3296 }
3297 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3298 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3299 {
3300 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3301 }
3302
3303 else
3304 {
3305 //Invalid chroma format; Error code may be updated, verify in testing if needed
3306 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3307 return IV_FAIL;
3308 }
3309
3310 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3311 {
3312 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3313 }
3314
3315 /*!*/
3316 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3317 {
3318 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3319 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3320 >> 2;
3321 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3322 >> 2;
3323 }
3324 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3325 {
3326 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3327 * 2;
3328 ps_ctl_op->u4_min_out_buf_size[1] =
3329 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3330 }
3331 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3332 {
3333 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3334 * 2;
3335 ps_ctl_op->u4_min_out_buf_size[1] =
3336 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3337 }
3338 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3339 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3340 {
3341 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3342 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3343 >> 1;
3344 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3345 }
3346
3347 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3348 return IV_SUCCESS;
3349 }
3350
3351 /*****************************************************************************/
3352 /* */
3353 /* Function Name : ih264d_get_buf_info */
3354 /* */
3355 /* Description : */
3356 /* */
3357 /* Inputs :iv_obj_t decoder handle */
3358 /* :pv_api_ip pointer to input structure */
3359 /* :pv_api_op pointer to output structure */
3360 /* Globals : <Does it use any global variables?> */
3361 /* Outputs : */
3362 /* Returns : void */
3363 /* */
3364 /* Issues : none */
3365 /* */
3366 /* Revision History: */
3367 /* */
3368 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3369 /* 22 10 2008 100356 Draft */
3370 /* */
3371 /*****************************************************************************/
ih264d_get_buf_info(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3372 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3373 {
3374
3375 dec_struct_t * ps_dec;
3376 UWORD8 i = 0; // Default for 420P format
3377 UWORD16 pic_wd, pic_ht;
3378 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3379 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3380 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3381 UNUSED(pv_api_ip);
3382
3383 ps_ctl_op->u4_error_code = 0;
3384
3385 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3386
3387 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3388
3389
3390 ps_ctl_op->u4_num_disp_bufs = 1;
3391
3392
3393 pic_wd = 0;
3394 pic_ht = 0;
3395
3396 if(ps_dec->i4_header_decoded == 3)
3397 {
3398
3399 if(0 == ps_dec->u4_share_disp_buf)
3400 {
3401 pic_wd = ps_dec->u2_disp_width;
3402 pic_ht = ps_dec->u2_disp_height;
3403
3404 }
3405 else
3406 {
3407 pic_wd = ps_dec->u2_frm_wd_y;
3408 pic_ht = ps_dec->u2_frm_ht_y;
3409 }
3410
3411 }
3412
3413 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3414 {
3415 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3416 }
3417 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3418 pic_wd = ps_dec->u4_app_disp_width;
3419
3420 if(0 == ps_dec->u4_share_disp_buf)
3421 ps_ctl_op->u4_num_disp_bufs = 1;
3422 else
3423 {
3424 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3425 {
3426 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3427 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3428 {
3429 ps_ctl_op->u4_num_disp_bufs =
3430 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3431 }
3432 else
3433 {
3434 /*if VUI is not present assume maximum possible refrence frames for the level,
3435 * as max reorder frames*/
3436 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3437 }
3438
3439 ps_ctl_op->u4_num_disp_bufs +=
3440 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3441
3442 }
3443 else
3444 {
3445 ps_ctl_op->u4_num_disp_bufs = 32;
3446
3447 }
3448
3449 ps_ctl_op->u4_num_disp_bufs = MAX(
3450 ps_ctl_op->u4_num_disp_bufs, 6);
3451 ps_ctl_op->u4_num_disp_bufs = MIN(
3452 ps_ctl_op->u4_num_disp_bufs, 32);
3453 }
3454
3455 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3456 pic_wd, pic_ht, ps_dec->u1_chroma_format,
3457 &au4_min_out_buf_size[0]);
3458
3459 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3460 {
3461 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3462 }
3463
3464 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3465
3466 return IV_SUCCESS;
3467 }
3468
3469 /*****************************************************************************/
3470 /* */
3471 /* Function Name : ih264d_set_params */
3472 /* */
3473 /* Description : */
3474 /* */
3475 /* Inputs :iv_obj_t decoder handle */
3476 /* :pv_api_ip pointer to input structure */
3477 /* :pv_api_op pointer to output structure */
3478 /* Outputs : */
3479 /* Returns : void */
3480 /* */
3481 /* Issues : none */
3482 /* */
3483 /* Revision History: */
3484 /* */
3485 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3486 /* 22 10 2008 100356 Draft */
3487 /* */
3488 /*****************************************************************************/
ih264d_set_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3489 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3490 {
3491
3492 dec_struct_t * ps_dec;
3493 WORD32 ret = IV_SUCCESS;
3494
3495 ih264d_ctl_set_config_ip_t *ps_h264d_ctl_ip =
3496 (ih264d_ctl_set_config_ip_t *)pv_api_ip;
3497 ih264d_ctl_set_config_op_t *ps_h264d_ctl_op =
3498 (ih264d_ctl_set_config_op_t *)pv_api_op;
3499 ivd_ctl_set_config_ip_t *ps_ctl_ip =
3500 &ps_h264d_ctl_ip->s_ivd_ctl_set_config_ip_t;
3501 ivd_ctl_set_config_op_t *ps_ctl_op =
3502 &ps_h264d_ctl_op->s_ivd_ctl_set_config_op_t;
3503
3504 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3505
3506 ps_dec->u4_skip_frm_mask = 0;
3507
3508 ps_ctl_op->u4_error_code = 0;
3509
3510 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3511 {
3512 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3513 ret = IV_FAIL;
3514 }
3515
3516 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_disp_width)
3517 {
3518 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3519 }
3520 else if(0 == ps_dec->i4_header_decoded)
3521 {
3522 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3523 }
3524 else if(ps_ctl_ip->u4_disp_wd == 0)
3525 {
3526 ps_dec->u4_app_disp_width = 0;
3527 }
3528 else
3529 {
3530 /*
3531 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3532 * does not propogate.
3533 */
3534 ps_dec->u4_app_disp_width = 0;
3535 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3536 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3537 ret = IV_FAIL;
3538 }
3539
3540 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3541 ps_dec->i4_decode_header = 0;
3542 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3543 ps_dec->i4_decode_header = 1;
3544 else
3545 {
3546 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3547 ps_dec->i4_decode_header = 1;
3548 ret = IV_FAIL;
3549 }
3550 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3551
3552 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3553 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3554 {
3555 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3556 ret = IV_FAIL;
3557 }
3558 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3559 return ret;
3560
3561 }
3562
3563 /*****************************************************************************/
3564 /* */
3565 /* Function Name : ih264d_set_default_params */
3566 /* */
3567 /* Description : */
3568 /* */
3569 /* Inputs :iv_obj_t decoder handle */
3570 /* :pv_api_ip pointer to input structure */
3571 /* :pv_api_op pointer to output structure */
3572 /* Outputs : */
3573 /* Returns : void */
3574 /* */
3575 /* Issues : none */
3576 /* */
3577 /* Revision History: */
3578 /* */
3579 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3580 /* 08 08 2011 100421 Copied from set_params */
3581 /* */
3582 /*****************************************************************************/
ih264d_set_default_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3583 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3584 void *pv_api_ip,
3585 void *pv_api_op)
3586 {
3587
3588 dec_struct_t * ps_dec;
3589 WORD32 ret = IV_SUCCESS;
3590
3591 ivd_ctl_set_config_op_t *ps_ctl_op =
3592 (ivd_ctl_set_config_op_t *)pv_api_op;
3593 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3594 UNUSED(pv_api_ip);
3595
3596
3597 {
3598 ps_dec->u4_app_disp_width = 0;
3599 ps_dec->u4_skip_frm_mask = 0;
3600 ps_dec->i4_decode_header = 1;
3601
3602 ps_ctl_op->u4_error_code = 0;
3603 }
3604
3605
3606 return ret;
3607 }
3608 /*****************************************************************************/
3609 /* */
3610 /* Function Name : ih264d_reset */
3611 /* */
3612 /* Description : */
3613 /* */
3614 /* Inputs :iv_obj_t decoder handle */
3615 /* :pv_api_ip pointer to input structure */
3616 /* :pv_api_op pointer to output structure */
3617 /* Globals : <Does it use any global variables?> */
3618 /* Outputs : */
3619 /* Returns : void */
3620 /* */
3621 /* Issues : none */
3622 /* */
3623 /* Revision History: */
3624 /* */
3625 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3626 /* 22 10 2008 100356 Draft */
3627 /* */
3628 /*****************************************************************************/
ih264d_delete(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3629 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3630 {
3631 dec_struct_t *ps_dec;
3632 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3633 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3634
3635 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3636 UNUSED(ps_ip);
3637 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3638 ih264d_free_dynamic_bufs(ps_dec);
3639 ih264d_free_static_bufs(dec_hdl);
3640 return IV_SUCCESS;
3641 }
3642 /*****************************************************************************/
3643 /* */
3644 /* Function Name : ih264d_reset */
3645 /* */
3646 /* Description : */
3647 /* */
3648 /* Inputs :iv_obj_t decoder handle */
3649 /* :pv_api_ip pointer to input structure */
3650 /* :pv_api_op pointer to output structure */
3651 /* Globals : <Does it use any global variables?> */
3652 /* Outputs : */
3653 /* Returns : void */
3654 /* */
3655 /* Issues : none */
3656 /* */
3657 /* Revision History: */
3658 /* */
3659 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3660 /* 22 10 2008 100356 Draft */
3661 /* */
3662 /*****************************************************************************/
ih264d_reset(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3663 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3664 {
3665 dec_struct_t * ps_dec;
3666 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3667 UNUSED(pv_api_ip);
3668 ps_ctl_op->u4_error_code = 0;
3669
3670 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3671
3672 if(ps_dec != NULL)
3673 {
3674 ih264d_init_decoder(ps_dec);
3675 }
3676 else
3677 {
3678 H264_DEC_DEBUG_PRINT(
3679 "\nReset called without Initializing the decoder\n");
3680 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3681 }
3682
3683 return IV_SUCCESS;
3684 }
3685
3686 /*****************************************************************************/
3687 /* */
3688 /* Function Name : ih264d_ctl */
3689 /* */
3690 /* Description : */
3691 /* */
3692 /* Inputs :iv_obj_t decoder handle */
3693 /* :pv_api_ip pointer to input structure */
3694 /* :pv_api_op pointer to output structure */
3695 /* Outputs : */
3696 /* Returns : void */
3697 /* */
3698 /* Issues : none */
3699 /* */
3700 /* Revision History: */
3701 /* */
3702 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3703 /* 22 10 2008 100356 Draft */
3704 /* */
3705 /*****************************************************************************/
ih264d_ctl(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3706 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3707 {
3708 ivd_ctl_set_config_ip_t *ps_ctl_ip;
3709 ivd_ctl_set_config_op_t *ps_ctl_op;
3710 WORD32 ret = IV_SUCCESS;
3711 UWORD32 subcommand;
3712 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3713
3714 if(ps_dec->init_done != 1)
3715 {
3716 //Return proper Error Code
3717 return IV_FAIL;
3718 }
3719 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3720 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3721 ps_ctl_op->u4_error_code = 0;
3722 subcommand = ps_ctl_ip->e_sub_cmd;
3723
3724 switch(subcommand)
3725 {
3726 case IVD_CMD_CTL_GETPARAMS:
3727 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3728 (void *)pv_api_op);
3729 break;
3730 case IVD_CMD_CTL_SETPARAMS:
3731 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3732 (void *)pv_api_op);
3733 break;
3734 case IVD_CMD_CTL_RESET:
3735 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3736 break;
3737 case IVD_CMD_CTL_SETDEFAULT:
3738 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3739 (void *)pv_api_op);
3740 break;
3741 case IVD_CMD_CTL_FLUSH:
3742 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3743 (void *)pv_api_op);
3744 break;
3745 case IVD_CMD_CTL_GETBUFINFO:
3746 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3747 (void *)pv_api_op);
3748 break;
3749 case IVD_CMD_CTL_GETVERSION:
3750 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3751 (void *)pv_api_op);
3752 break;
3753 case IH264D_CMD_CTL_DEGRADE:
3754 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3755 (void *)pv_api_op);
3756 break;
3757
3758 case IH264D_CMD_CTL_SET_NUM_CORES:
3759 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3760 (void *)pv_api_op);
3761 break;
3762 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3763 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3764 (void *)pv_api_op);
3765 break;
3766 case IH264D_CMD_CTL_GET_VUI_PARAMS:
3767 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3768 (void *)pv_api_op);
3769 break;
3770 case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
3771 ret = ih264d_get_sei_mdcv_params(dec_hdl, (void *)pv_api_ip,
3772 (void *)pv_api_op);
3773 break;
3774 case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
3775 ret = ih264d_get_sei_cll_params(dec_hdl, (void *)pv_api_ip,
3776 (void *)pv_api_op);
3777 break;
3778 case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
3779 ret = ih264d_get_sei_ave_params(dec_hdl, (void *)pv_api_ip,
3780 (void *)pv_api_op);
3781 break;
3782 case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
3783 ret = ih264d_get_sei_ccv_params(dec_hdl, (void *)pv_api_ip,
3784 (void *)pv_api_op);
3785 break;
3786 case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
3787 ret = ih264d_get_sei_sii_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3788 break;
3789
3790 case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
3791 ret = ih264d_get_sei_fgc_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3792 break;
3793
3794 case IH264D_CMD_CTL_SET_PROCESSOR:
3795 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3796 (void *)pv_api_op);
3797 break;
3798 default:
3799 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3800 ;
3801 break;
3802 }
3803
3804 return ret;
3805 }
3806 /*****************************************************************************/
3807 /* */
3808 /* Function Name : ih264d_rel_display_frame */
3809 /* */
3810 /* Description : */
3811 /* */
3812 /* Inputs :iv_obj_t decoder handle */
3813 /* :pv_api_ip pointer to input structure */
3814 /* :pv_api_op pointer to output structure */
3815 /* Outputs : */
3816 /* Returns : void */
3817 /* */
3818 /* Issues : none */
3819 /* */
3820 /* Revision History: */
3821 /* */
3822 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3823 /* 22 10 2008 100356 Draft */
3824 /* */
3825 /*****************************************************************************/
ih264d_rel_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3826 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3827 void *pv_api_ip,
3828 void *pv_api_op)
3829 {
3830
3831 ivd_rel_display_frame_ip_t *ps_rel_ip;
3832 ivd_rel_display_frame_op_t *ps_rel_op;
3833 UWORD32 buf_released = 0;
3834
3835 UWORD32 u4_ts = 0;
3836 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3837
3838 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3839 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3840 ps_rel_op->u4_error_code = 0;
3841 u4_ts = ps_rel_ip->u4_disp_buf_id;
3842
3843 if(0 == ps_dec->u4_share_disp_buf)
3844 {
3845 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3846 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3847 return IV_SUCCESS;
3848 }
3849
3850 if(ps_dec->pv_pic_buf_mgr != NULL)
3851 {
3852 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3853 {
3854 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3855 ps_rel_ip->u4_disp_buf_id,
3856 BUF_MGR_IO);
3857 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3858 buf_released = 1;
3859 }
3860 }
3861
3862 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3863 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3864
3865 return IV_SUCCESS;
3866 }
3867
3868 /**
3869 *******************************************************************************
3870 *
3871 * @brief
3872 * Sets degrade params
3873 *
3874 * @par Description:
3875 * Sets degrade params.
3876 * Refer to ih264d_ctl_degrade_ip_t definition for details
3877 *
3878 * @param[in] ps_codec_obj
3879 * Pointer to codec object at API level
3880 *
3881 * @param[in] pv_api_ip
3882 * Pointer to input argument structure
3883 *
3884 * @param[out] pv_api_op
3885 * Pointer to output argument structure
3886 *
3887 * @returns Status
3888 *
3889 * @remarks
3890 *
3891 *
3892 *******************************************************************************
3893 */
3894
ih264d_set_degrade(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3895 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3896 void *pv_api_ip,
3897 void *pv_api_op)
3898 {
3899 ih264d_ctl_degrade_ip_t *ps_ip;
3900 ih264d_ctl_degrade_op_t *ps_op;
3901 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3902
3903 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3904 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3905
3906 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3907 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3908 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3909
3910 ps_op->u4_error_code = 0;
3911 ps_codec->i4_degrade_pic_cnt = 0;
3912
3913 return IV_SUCCESS;
3914 }
3915
ih264d_get_frame_dimensions(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3916 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3917 void *pv_api_ip,
3918 void *pv_api_op)
3919 {
3920 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3921 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3922 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3923 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3924
3925 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3926
3927 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3928 UNUSED(ps_ip);
3929 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3930 {
3931 disp_wd = ps_dec->u2_disp_width;
3932 disp_ht = ps_dec->u2_disp_height;
3933
3934 if(0 == ps_dec->u4_share_disp_buf)
3935 {
3936 buffer_wd = disp_wd;
3937 buffer_ht = disp_ht;
3938 }
3939 else
3940 {
3941 buffer_wd = ps_dec->u2_frm_wd_y;
3942 buffer_ht = ps_dec->u2_frm_ht_y;
3943 }
3944 }
3945 else
3946 {
3947 disp_wd = 0;
3948 disp_ht = 0;
3949
3950 if(0 == ps_dec->u4_share_disp_buf)
3951 {
3952 buffer_wd = disp_wd;
3953 buffer_ht = disp_ht;
3954 }
3955 else
3956 {
3957 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3958 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3959 }
3960 }
3961 if(ps_dec->u4_app_disp_width > buffer_wd)
3962 buffer_wd = ps_dec->u4_app_disp_width;
3963
3964 if(0 == ps_dec->u4_share_disp_buf)
3965 {
3966 x_offset = 0;
3967 y_offset = 0;
3968 }
3969 else
3970 {
3971 y_offset = (PAD_LEN_Y_V << 1);
3972 x_offset = PAD_LEN_Y_H;
3973
3974 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3975 && (0 != ps_dec->u2_crop_offset_y))
3976 {
3977 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3978 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3979 }
3980 }
3981
3982 ps_op->u4_disp_wd[0] = disp_wd;
3983 ps_op->u4_disp_ht[0] = disp_ht;
3984 ps_op->u4_buffer_wd[0] = buffer_wd;
3985 ps_op->u4_buffer_ht[0] = buffer_ht;
3986 ps_op->u4_x_offset[0] = x_offset;
3987 ps_op->u4_y_offset[0] = y_offset;
3988
3989 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
3990 >> 1);
3991 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
3992 >> 1);
3993 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
3994 >> 1);
3995 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
3996 >> 1);
3997 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
3998 (ps_op->u4_x_offset[0] >> 1);
3999 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4000 (ps_op->u4_y_offset[0] >> 1);
4001
4002 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4003 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4004 {
4005 ps_op->u4_disp_wd[2] = 0;
4006 ps_op->u4_disp_ht[2] = 0;
4007 ps_op->u4_buffer_wd[2] = 0;
4008 ps_op->u4_buffer_ht[2] = 0;
4009 ps_op->u4_x_offset[2] = 0;
4010 ps_op->u4_y_offset[2] = 0;
4011
4012 ps_op->u4_disp_wd[1] <<= 1;
4013 ps_op->u4_buffer_wd[1] <<= 1;
4014 ps_op->u4_x_offset[1] <<= 1;
4015 }
4016
4017 return IV_SUCCESS;
4018
4019 }
4020
ih264d_get_vui_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4021 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
4022 void *pv_api_ip,
4023 void *pv_api_op)
4024 {
4025 ih264d_ctl_get_vui_params_ip_t *ps_ip;
4026 ih264d_ctl_get_vui_params_op_t *ps_op;
4027 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4028 dec_seq_params_t *ps_sps;
4029 vui_t *ps_vui;
4030 WORD32 i;
4031 UWORD32 u4_size;
4032
4033 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
4034 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
4035 UNUSED(ps_ip);
4036
4037 u4_size = ps_op->u4_size;
4038 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
4039 ps_op->u4_size = u4_size;
4040
4041 if(NULL == ps_dec->ps_cur_sps)
4042 {
4043 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4044 return IV_FAIL;
4045 }
4046
4047 ps_sps = ps_dec->ps_cur_sps;
4048 if((0 == ps_sps->u1_is_valid)
4049 || (0 == ps_sps->u1_vui_parameters_present_flag))
4050 {
4051 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4052 return IV_FAIL;
4053 }
4054
4055 ps_vui = &ps_sps->s_vui;
4056
4057 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc;
4058 ps_op->u2_sar_width = ps_vui->u2_sar_width;
4059 ps_op->u2_sar_height = ps_vui->u2_sar_height;
4060 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag;
4061 ps_op->u1_video_format = ps_vui->u1_video_format;
4062 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag;
4063 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries;
4064 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars;
4065 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs;
4066 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field;
4067 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field;
4068 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick;
4069 ps_op->u4_time_scale = ps_vui->u4_time_scale;
4070 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag;
4071 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present;
4072 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present;
4073 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag;
4074 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag;
4075 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag;
4076 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag;
4077 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom;
4078 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom;
4079 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz;
4080 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert;
4081 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames;
4082 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering;
4083
4084 return IV_SUCCESS;
4085 }
4086 /*****************************************************************************/
4087 /* */
4088 /* Function Name : ih264d_get_sei_mdcv_params */
4089 /* */
4090 /* Description : This function populates SEI mdcv message in */
4091 /* output structure */
4092 /* Inputs : iv_obj_t decoder handle */
4093 /* : pv_api_ip pointer to input structure */
4094 /* : pv_api_op pointer to output structure */
4095 /* Outputs : */
4096 /* Returns : returns 0; 1 with error code when MDCV is not present */
4097 /* */
4098 /* Issues : none */
4099 /* */
4100 /* Revision History: */
4101 /* */
4102 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4103 /* */
4104 /* */
4105 /*****************************************************************************/
ih264d_get_sei_mdcv_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4106 WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
4107 void *pv_api_ip,
4108 void *pv_api_op)
4109 {
4110 ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
4111 ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
4112 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4113 sei_mdcv_params_t *ps_sei_mdcv;
4114 WORD32 i4_count;
4115
4116 ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
4117 ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
4118 UNUSED(ps_ip);
4119
4120 if(0 == ps_dec->s_sei_export.u1_sei_mdcv_params_present_flag)
4121 {
4122 ps_op->u4_error_code = ERROR_SEI_MDCV_PARAMS_NOT_FOUND;
4123 return IV_FAIL;
4124 }
4125
4126 ps_sei_mdcv = &ps_dec->s_sei_export.s_sei_mdcv_params;
4127
4128 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
4129 {
4130 ps_op->au2_display_primaries_x[i4_count] = ps_sei_mdcv->au2_display_primaries_x[i4_count];
4131 ps_op->au2_display_primaries_y[i4_count] = ps_sei_mdcv->au2_display_primaries_y[i4_count];
4132 }
4133
4134 ps_op->u2_white_point_x = ps_sei_mdcv->u2_white_point_x;
4135 ps_op->u2_white_point_y = ps_sei_mdcv->u2_white_point_y;
4136 ps_op->u4_max_display_mastering_luminance = ps_sei_mdcv->u4_max_display_mastering_luminance;
4137 ps_op->u4_min_display_mastering_luminance = ps_sei_mdcv->u4_min_display_mastering_luminance;
4138
4139 return IV_SUCCESS;
4140 }
4141
4142 /*****************************************************************************/
4143 /* */
4144 /* Function Name : ih264d_get_sei_cll_params */
4145 /* */
4146 /* Description : This function populates SEI cll message in */
4147 /* output structure */
4148 /* Inputs : iv_obj_t decoder handle */
4149 /* : pv_api_ip pointer to input structure */
4150 /* : pv_api_op pointer to output structure */
4151 /* Outputs : */
4152 /* Returns : returns 0; 1 with error code when CLL is not present */
4153 /* */
4154 /* Issues : none */
4155 /* */
4156 /* Revision History: */
4157 /* */
4158 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4159 /* */
4160 /* */
4161 /*****************************************************************************/
ih264d_get_sei_cll_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4162 WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
4163 void *pv_api_ip,
4164 void *pv_api_op)
4165 {
4166 ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
4167 ih264d_ctl_get_sei_cll_params_op_t *ps_op;
4168 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4169 sei_cll_params_t *ps_sei_cll;
4170
4171 ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
4172 ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
4173 UNUSED(ps_ip);
4174
4175 if(0 == ps_dec->s_sei_export.u1_sei_cll_params_present_flag)
4176 {
4177 ps_op->u4_error_code = ERROR_SEI_CLL_PARAMS_NOT_FOUND;
4178 return IV_FAIL;
4179 }
4180
4181 ps_sei_cll = &ps_dec->s_sei_export.s_sei_cll_params;
4182
4183 ps_op->u2_max_content_light_level = ps_sei_cll->u2_max_content_light_level;
4184 ps_op->u2_max_pic_average_light_level = ps_sei_cll->u2_max_pic_average_light_level;
4185
4186 return IV_SUCCESS;
4187 }
4188
4189 /*****************************************************************************/
4190 /* */
4191 /* Function Name : ih264d_get_sei_ave_params */
4192 /* */
4193 /* Description : This function populates SEI ave message in */
4194 /* output structure */
4195 /* Inputs : iv_obj_t decoder handle */
4196 /* : pv_api_ip pointer to input structure */
4197 /* : pv_api_op pointer to output structure */
4198 /* Outputs : */
4199 /* Returns : returns 0; 1 with error code when AVE is not present */
4200 /* */
4201 /* Issues : none */
4202 /* */
4203 /* Revision History: */
4204 /* */
4205 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4206 /* */
4207 /* */
4208 /*****************************************************************************/
ih264d_get_sei_ave_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4209 WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
4210 void *pv_api_ip,
4211 void *pv_api_op)
4212 {
4213 ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
4214 ih264d_ctl_get_sei_ave_params_op_t *ps_op;
4215 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4216 sei_ave_params_t *ps_sei_ave;
4217
4218 ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
4219 ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
4220 UNUSED(ps_ip);
4221
4222 if(0 == ps_dec->s_sei_export.u1_sei_ave_params_present_flag)
4223 {
4224 ps_op->u4_error_code = ERROR_SEI_AVE_PARAMS_NOT_FOUND;
4225 return IV_FAIL;
4226 }
4227
4228 ps_sei_ave = &ps_dec->s_sei_export.s_sei_ave_params;
4229
4230 ps_op->u4_ambient_illuminance = ps_sei_ave->u4_ambient_illuminance;
4231 ps_op->u2_ambient_light_x = ps_sei_ave->u2_ambient_light_x;
4232 ps_op->u2_ambient_light_y = ps_sei_ave->u2_ambient_light_y;
4233
4234 return IV_SUCCESS;
4235 }
4236
4237 /*****************************************************************************/
4238 /* */
4239 /* Function Name : ih264d_get_sei_ccv_params */
4240 /* */
4241 /* Description : This function populates SEI mdcv message in */
4242 /* output structure */
4243 /* Inputs : iv_obj_t decoder handle */
4244 /* : pv_api_ip pointer to input structure */
4245 /* : pv_api_op pointer to output structure */
4246 /* Outputs : */
4247 /* Returns : returns 0; 1 with error code when CCV is not present */
4248 /* */
4249 /* Issues : none */
4250 /* */
4251 /* Revision History: */
4252 /* */
4253 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4254 /* */
4255 /* */
4256 /*****************************************************************************/
ih264d_get_sei_ccv_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4257 WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
4258 void *pv_api_ip,
4259 void *pv_api_op)
4260 {
4261 ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
4262 ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
4263 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4264 sei_ccv_params_t *ps_sei_ccv;
4265 WORD32 i4_count;
4266
4267 ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
4268 ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
4269 UNUSED(ps_ip);
4270
4271 if(0 == ps_dec->s_sei_export.u1_sei_ccv_params_present_flag)
4272 {
4273 ps_op->u4_error_code = ERROR_SEI_CCV_PARAMS_NOT_FOUND;
4274 return IV_FAIL;
4275 }
4276
4277 ps_sei_ccv = &ps_dec->s_sei_export.s_sei_ccv_params;
4278
4279 ps_op->u1_ccv_cancel_flag = ps_sei_ccv->u1_ccv_cancel_flag;
4280
4281 if(0 == ps_op->u1_ccv_cancel_flag)
4282 {
4283 ps_op->u1_ccv_persistence_flag = ps_sei_ccv->u1_ccv_persistence_flag;
4284 ps_op->u1_ccv_primaries_present_flag = ps_sei_ccv->u1_ccv_primaries_present_flag;
4285 ps_op->u1_ccv_min_luminance_value_present_flag =
4286 ps_sei_ccv->u1_ccv_min_luminance_value_present_flag;
4287 ps_op->u1_ccv_max_luminance_value_present_flag =
4288 ps_sei_ccv->u1_ccv_max_luminance_value_present_flag;
4289 ps_op->u1_ccv_avg_luminance_value_present_flag =
4290 ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag;
4291 ps_op->u1_ccv_reserved_zero_2bits = ps_sei_ccv->u1_ccv_reserved_zero_2bits;
4292
4293 if(1 == ps_sei_ccv->u1_ccv_primaries_present_flag)
4294 {
4295 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
4296 {
4297 ps_op->ai4_ccv_primaries_x[i4_count] = ps_sei_ccv->ai4_ccv_primaries_x[i4_count];
4298 ps_op->ai4_ccv_primaries_y[i4_count] = ps_sei_ccv->ai4_ccv_primaries_y[i4_count];
4299 }
4300 }
4301
4302 if(1 == ps_sei_ccv->u1_ccv_min_luminance_value_present_flag)
4303 {
4304 ps_op->u4_ccv_min_luminance_value = ps_sei_ccv->u4_ccv_min_luminance_value;
4305 }
4306 if(1 == ps_sei_ccv->u1_ccv_max_luminance_value_present_flag)
4307 {
4308 ps_op->u4_ccv_max_luminance_value = ps_sei_ccv->u4_ccv_max_luminance_value;
4309 }
4310 if(1 == ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag)
4311 {
4312 ps_op->u4_ccv_avg_luminance_value = ps_sei_ccv->u4_ccv_avg_luminance_value;
4313 }
4314 }
4315
4316 return IV_SUCCESS;
4317 }
4318
4319 /*****************************************************************************/
4320 /* */
4321 /* Function Name : ih264d_get_sei_sii_params */
4322 /* */
4323 /* Description : This function populates SEI sii message in */
4324 /* output structure */
4325 /* Inputs : iv_obj_t decoder handle */
4326 /* : pv_api_ip pointer to input structure */
4327 /* : pv_api_op pointer to output structure */
4328 /* Outputs : */
4329 /* Returns : returns 0; 1 with error code when SII is not present */
4330 /* */
4331 /* Issues : none */
4332 /* */
4333 /* Revision History: */
4334 /* */
4335 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4336 /* */
4337 /* */
4338 /*****************************************************************************/
ih264d_get_sei_sii_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4339 WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4340 {
4341 ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
4342 ih264d_ctl_get_sei_sii_params_op_t *ps_op;
4343 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4344 sei_sii_params_t *ps_sei_sii;
4345 int i;
4346
4347 ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
4348 ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
4349 UNUSED(ps_ip);
4350
4351 if(0 == ps_dec->s_sei_export.u1_sei_sii_params_present_flag)
4352 {
4353 ps_op->u4_error_code = ERROR_SEI_SII_PARAMS_NOT_FOUND;
4354 return IV_FAIL;
4355 }
4356
4357 ps_sei_sii = &ps_dec->s_sei_export.s_sei_sii_params;
4358
4359 if((ps_sei_sii->u4_sii_sub_layer_idx > 0) &&
4360 (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 1))
4361 {
4362 ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4363 return IV_FAIL;
4364 }
4365
4366 if((ps_sei_sii->u4_sii_sub_layer_idx > ps_sei_sii->u1_sii_max_sub_layers_minus1) &&
4367 (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 0))
4368 {
4369 ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4370 return IV_FAIL;
4371 }
4372
4373 ps_op->u4_sii_sub_layer_idx = ps_sei_sii->u4_sii_sub_layer_idx;
4374
4375 if(0 == ps_op->u4_sii_sub_layer_idx)
4376 {
4377 ps_op->u1_shutter_interval_info_present_flag =
4378 ps_sei_sii->u1_shutter_interval_info_present_flag;
4379
4380 if(1 == ps_sei_sii->u1_shutter_interval_info_present_flag)
4381 {
4382 ps_op->u4_sii_time_scale = ps_sei_sii->u4_sii_time_scale;
4383 ps_op->u1_fixed_shutter_interval_within_cvs_flag =
4384 ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag;
4385
4386 if(1 == ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag)
4387 {
4388 ps_op->u4_sii_num_units_in_shutter_interval =
4389 ps_sei_sii->u4_sii_num_units_in_shutter_interval;
4390 }
4391 else
4392 {
4393 ps_op->u1_sii_max_sub_layers_minus1 = ps_sei_sii->u1_sii_max_sub_layers_minus1;
4394 for(i = 0; i <= ps_sei_sii->u1_sii_max_sub_layers_minus1; i++)
4395 {
4396 ps_op->au4_sub_layer_num_units_in_shutter_interval[i] =
4397 ps_sei_sii->au4_sub_layer_num_units_in_shutter_interval[i];
4398 }
4399 }
4400 }
4401 }
4402
4403 return IV_SUCCESS;
4404 }
4405
4406 /*****************************************************************************/
4407 /* */
4408 /* Function Name : ih264d_get_sei_fgc_params */
4409 /* */
4410 /* Description : This function populates SEI FGC message in */
4411 /* output structure */
4412 /* Inputs : iv_obj_t decoder handle */
4413 /* : pv_api_ip pointer to input structure */
4414 /* : pv_api_op pointer to output structure */
4415 /* Outputs : */
4416 /* Returns : returns 0; 1 with error code when FGC is not present */
4417 /* */
4418 /* Issues : none */
4419 /* */
4420 /* Revision History: */
4421 /* */
4422 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4423 /* */
4424 /* */
4425 /*****************************************************************************/
ih264d_get_sei_fgc_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4426 WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4427 {
4428 ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
4429 ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
4430 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4431 sei_fgc_params_t *ps_sei_fgc;
4432 WORD32 i4_count;
4433 UWORD32 c, i, j;
4434
4435 ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
4436 ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
4437 UNUSED(ps_ip);
4438
4439 if(0 == ps_dec->s_sei_export.u1_sei_fgc_params_present_flag)
4440 {
4441 ps_op->u4_error_code = ERROR_SEI_FGC_PARAMS_NOT_FOUND;
4442 return IV_FAIL;
4443 }
4444
4445 ps_sei_fgc = &ps_dec->s_sei_export.s_sei_fgc_params;
4446
4447 ps_op->u1_film_grain_characteristics_cancel_flag =
4448 ps_sei_fgc->u1_film_grain_characteristics_cancel_flag;
4449
4450 if(0 == ps_op->u1_film_grain_characteristics_cancel_flag)
4451 {
4452 ps_op->i4_poc = ps_sei_fgc->i4_poc;
4453 ps_op->u4_idr_pic_id = ps_sei_fgc->u4_idr_pic_id;
4454 ps_op->u1_film_grain_model_id = ps_sei_fgc->u1_film_grain_model_id;
4455 ps_op->u1_separate_colour_description_present_flag =
4456 ps_sei_fgc->u1_separate_colour_description_present_flag;
4457
4458 if(ps_op->u1_separate_colour_description_present_flag)
4459 {
4460 ps_op->u1_film_grain_bit_depth_luma_minus8 =
4461 ps_sei_fgc->u1_film_grain_bit_depth_luma_minus8;
4462 ps_op->u1_film_grain_bit_depth_chroma_minus8 =
4463 ps_sei_fgc->u1_film_grain_bit_depth_chroma_minus8;
4464 ps_op->u1_film_grain_full_range_flag = ps_sei_fgc->u1_film_grain_full_range_flag;
4465 ps_op->u1_film_grain_colour_primaries = ps_sei_fgc->u1_film_grain_colour_primaries;
4466 ps_op->u1_film_grain_transfer_characteristics =
4467 ps_sei_fgc->u1_film_grain_transfer_characteristics;
4468 ps_op->u1_film_grain_matrix_coefficients =
4469 ps_sei_fgc->u1_film_grain_matrix_coefficients;
4470 }
4471 ps_op->u1_blending_mode_id = ps_sei_fgc->u1_blending_mode_id;
4472 ps_op->u1_log2_scale_factor = ps_sei_fgc->u1_log2_scale_factor;
4473
4474 for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4475 {
4476 ps_op->au1_comp_model_present_flag[c] = ps_sei_fgc->au1_comp_model_present_flag[c];
4477 }
4478
4479 for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4480 {
4481 if(ps_op->au1_comp_model_present_flag[c])
4482 {
4483 ps_op->au1_num_intensity_intervals_minus1[c] =
4484 ps_sei_fgc->au1_num_intensity_intervals_minus1[c];
4485
4486 ps_op->au1_num_model_values_minus1[c] = ps_sei_fgc->au1_num_model_values_minus1[c];
4487
4488 for(i = 0; i <= ps_op->au1_num_intensity_intervals_minus1[c]; i++)
4489 {
4490 ps_op->au1_intensity_interval_lower_bound[c][i] =
4491 ps_sei_fgc->au1_intensity_interval_lower_bound[c][i];
4492 ps_op->au1_intensity_interval_upper_bound[c][i] =
4493 ps_sei_fgc->au1_intensity_interval_upper_bound[c][i];
4494
4495 for(j = 0; j <= ps_op->au1_num_model_values_minus1[c]; j++)
4496 {
4497 ps_op->ai4_comp_model_value[c][i][j] =
4498 ps_sei_fgc->ai4_comp_model_value[c][i][j];
4499 }
4500 }
4501 }
4502 }
4503 ps_op->u4_film_grain_characteristics_repetition_period =
4504 ps_sei_fgc->u4_film_grain_characteristics_repetition_period;
4505 }
4506 return IV_SUCCESS;
4507 }
4508
ih264d_set_num_cores(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4509 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4510 {
4511 ih264d_ctl_set_num_cores_ip_t *ps_ip;
4512 ih264d_ctl_set_num_cores_op_t *ps_op;
4513 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4514
4515 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4516 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4517 ps_op->u4_error_code = 0;
4518 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4519 if(ps_dec->u4_num_cores == 1)
4520 {
4521 ps_dec->u1_separate_parse = 0;
4522 }
4523 else
4524 {
4525 ps_dec->u1_separate_parse = 1;
4526 }
4527
4528 /*using only upto three threads currently*/
4529 if(ps_dec->u4_num_cores > 3)
4530 ps_dec->u4_num_cores = 3;
4531
4532 return IV_SUCCESS;
4533 }
4534
ih264d_fill_output_struct_from_context(dec_struct_t * ps_dec,ivd_video_decode_op_t * ps_dec_op)4535 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4536 ivd_video_decode_op_t *ps_dec_op)
4537 {
4538 if((ps_dec_op->u4_error_code & 0xff)
4539 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4540 {
4541 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4542 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4543 }
4544 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
4545 ps_dec_op->i4_display_index = ps_dec->i4_display_index;
4546 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4547
4548 ps_dec_op->u4_new_seq = 0;
4549 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4550 ps_dec_op->u4_progressive_frame_flag =
4551 ps_dec->s_disp_op.u4_progressive_frame_flag;
4552
4553 ps_dec_op->u4_is_ref_flag = 1;
4554 if(ps_dec_op->u4_frame_decoded_flag)
4555 {
4556 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4557 ps_dec_op->u4_is_ref_flag = 0;
4558 }
4559
4560 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4561 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4562 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4563 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4564 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4565
4566 ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
4567 }
4568
4569 /*****************************************************************************/
4570 /* */
4571 /* Function Name : ih264d_api_function */
4572 /* */
4573 /* Description : */
4574 /* */
4575 /* Inputs :iv_obj_t decoder handle */
4576 /* :pv_api_ip pointer to input structure */
4577 /* :pv_api_op pointer to output structure */
4578 /* Outputs : */
4579 /* Returns : void */
4580 /* */
4581 /* Issues : none */
4582 /* */
4583 /* Revision History: */
4584 /* */
4585 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4586 /* 22 10 2008 100356 Draft */
4587 /* */
4588 /*****************************************************************************/
ih264d_api_function(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4589 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4590 void *pv_api_ip,
4591 void *pv_api_op)
4592 {
4593 UWORD32 command;
4594 UWORD32 *pu2_ptr_cmd;
4595 UWORD32 u4_api_ret;
4596 IV_API_CALL_STATUS_T e_status;
4597 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4598
4599 if(e_status != IV_SUCCESS)
4600 {
4601 UWORD32 *ptr_err;
4602
4603 ptr_err = (UWORD32 *)pv_api_op;
4604 UNUSED(ptr_err);
4605 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4606 return IV_FAIL;
4607 }
4608
4609 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4610 pu2_ptr_cmd++;
4611
4612 command = *pu2_ptr_cmd;
4613 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4614 switch(command)
4615 {
4616
4617 case IVD_CMD_CREATE:
4618 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
4619 (void *)pv_api_op);
4620 break;
4621 case IVD_CMD_DELETE:
4622 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
4623 (void *)pv_api_op);
4624 break;
4625
4626 case IVD_CMD_VIDEO_DECODE:
4627 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4628 (void *)pv_api_op);
4629 break;
4630
4631 case IVD_CMD_GET_DISPLAY_FRAME:
4632 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4633 (void *)pv_api_op);
4634
4635 break;
4636
4637 case IVD_CMD_SET_DISPLAY_FRAME:
4638 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4639 (void *)pv_api_op);
4640
4641 break;
4642
4643 case IVD_CMD_REL_DISPLAY_FRAME:
4644 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4645 (void *)pv_api_op);
4646 break;
4647
4648 case IVD_CMD_VIDEO_CTL:
4649 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4650 (void *)pv_api_op);
4651 break;
4652 default:
4653 u4_api_ret = IV_FAIL;
4654 break;
4655 }
4656
4657 return u4_api_ret;
4658 }
4659