1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /**
22 *******************************************************************************
23 * @file
24 * ih264e_api.c
25 *
26 * @brief
27 * Contains api function definitions for H264 encoder
28 *
29 * @author
30 * ittiam
31 *
32 * @par List of Functions:
33 * - api_check_struct_sanity()
34 * - ih264e_codec_update_config()
35 * - ih264e_set_default_params()
36 * - ih264e_init()
37 * - ih264e_get_num_rec()
38 * - ih264e_fill_num_mem_rec()
39 * - ih264e_init_mem_rec()
40 * - ih264e_retrieve_memrec()
41 * - ih264e_set_flush_mode()
42 * - ih264e_get_buf_info()
43 * - ih264e_set_dimensions()
44 * - ih264e_set_frame_rate()
45 * - ih264e_set_bit_rate()
46 * - ih264e_set_frame_type()
47 * - ih264e_set_qp()
48 * - ih264e_set_enc_mode()
49 * - ih264e_set_vbv_params()
50 * - ih264_set_air_params()
51 * - ih264_set_me_params()
52 * - ih264_set_ipe_params()
53 * - ih264_set_gop_params()
54 * - ih264_set_profile_params()
55 * - ih264_set_deblock_params()
56 * - ih264e_set_num_cores()
57 * - ih264e_reset()
58 * - ih264e_ctl()
59 * - ih264e_api_function()
60 *
61 * @remarks
62 * None
63 *
64 *******************************************************************************
65 */
66
67 /*****************************************************************************/
68 /* File Includes */
69 /*****************************************************************************/
70
71 /* System Include Files */
72 #include <stdio.h>
73 #include <stddef.h>
74 #include <stdlib.h>
75 #include <string.h>
76 #include <assert.h>
77
78 /* User Include Files */
79 #include "ih264e_config.h"
80 #include "ih264_typedefs.h"
81 #include "ih264_size_defs.h"
82 #include "iv2.h"
83 #include "ive2.h"
84 #include "ih264e.h"
85 #include "ithread.h"
86 #include "ih264_debug.h"
87 #include "ih264_defs.h"
88 #include "ih264_error.h"
89 #include "ih264_structs.h"
90 #include "ih264_trans_quant_itrans_iquant.h"
91 #include "ih264_inter_pred_filters.h"
92 #include "ih264_mem_fns.h"
93 #include "ih264_padding.h"
94 #include "ih264_intra_pred_filters.h"
95 #include "ih264_deblk_edge_filters.h"
96 #include "ih264_cabac_tables.h"
97 #include "ih264_macros.h"
98 #include "ih264e_defs.h"
99 #include "ih264e_globals.h"
100 #include "ih264_buf_mgr.h"
101 #include "irc_mem_req_and_acq.h"
102 #include "irc_cntrl_param.h"
103 #include "irc_frame_info_collector.h"
104 #include "irc_rate_control_api.h"
105 #include "ih264e_time_stamp.h"
106 #include "ih264e_modify_frm_rate.h"
107 #include "ih264e_rate_control.h"
108 #include "ih264e_error.h"
109 #include "ih264e_bitstream.h"
110 #include "ime_defs.h"
111 #include "ime_distortion_metrics.h"
112 #include "ime_structs.h"
113 #include "ih264e_cabac_structs.h"
114 #include "ih264e_structs.h"
115 #include "ih264e_utils.h"
116 #include "ih264e_core_coding.h"
117 #include "ih264_platform_macros.h"
118 #include "ih264e_platform_macros.h"
119 #include "ih264_list.h"
120 #include "ih264_dpb_mgr.h"
121 #include "ih264_cavlc_tables.h"
122 #include "ih264e_cavlc.h"
123 #include "ih264_common_tables.h"
124 #include "ih264e_master.h"
125 #include "ih264e_fmt_conv.h"
126 #include "ih264e_version.h"
127
128
129 /*****************************************************************************/
130 /* Function Declarations */
131 /*****************************************************************************/
132 WORD32 ih264e_get_rate_control_mem_tab(void *pv_rate_control,
133 iv_mem_rec_t *ps_mem,
134 ITT_FUNC_TYPE_E e_func_type);
135
136
137 /*****************************************************************************/
138 /* Function Definitions */
139 /*****************************************************************************/
140
141 /**
142 *******************************************************************************
143 *
144 * @brief
145 * Used to test validity of input dimensions
146 *
147 * @par Description:
148 * Dimensions of the input buffer passed to encode call are validated
149 *
150 * @param[in] ps_codec
151 * Codec context
152 *
153 * @param[in] ps_ip
154 * Pointer to input structure
155 *
156 * @param[out] ps_op
157 * Pointer to output structure
158 *
159 * @returns error status
160 *
161 * @remarks none
162 *
163 *******************************************************************************
164 */
api_check_input_dimensions(codec_t * ps_codec,ih264e_video_encode_ip_t * ps_ip,ih264e_video_encode_op_t * ps_op)165 static IV_STATUS_T api_check_input_dimensions(codec_t *ps_codec,
166 ih264e_video_encode_ip_t *ps_ip,
167 ih264e_video_encode_op_t *ps_op)
168 {
169 UWORD32 u4_wd, u4_ht;
170 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
171 iv_raw_buf_t *ps_inp_buf = &ps_ip->s_ive_ip.s_inp_buf;
172
173 u4_wd = ps_inp_buf->au4_wd[0];
174 u4_ht = ps_inp_buf->au4_ht[0];
175 switch (ps_inp_buf->e_color_fmt)
176 {
177 case IV_YUV_420P:
178 if (((ps_inp_buf->au4_wd[0] / 2) != ps_inp_buf->au4_wd[1]) ||
179 ((ps_inp_buf->au4_wd[0] / 2) != ps_inp_buf->au4_wd[2]) ||
180 (ps_inp_buf->au4_wd[1] != ps_inp_buf->au4_wd[2]))
181 {
182 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
183 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
184 return (IV_FAIL);
185 }
186 if (((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[1]) ||
187 ((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[2]) ||
188 (ps_inp_buf->au4_ht[1] != ps_inp_buf->au4_ht[2]))
189 {
190 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
191 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
192 return (IV_FAIL);
193 }
194 break;
195 case IV_YUV_420SP_UV:
196 case IV_YUV_420SP_VU:
197 if (ps_inp_buf->au4_wd[0] != ps_inp_buf->au4_wd[1])
198 {
199 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
200 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
201 return (IV_FAIL);
202 }
203 if ((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[1])
204 {
205 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
206 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
207 return (IV_FAIL);
208 }
209 break;
210 case IV_YUV_422ILE:
211 u4_wd = ps_inp_buf->au4_wd[0] / 2;
212 break;
213 default:
214 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
215 ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
216 return (IV_FAIL);
217 }
218
219 if (u4_wd != ps_curr_cfg->u4_disp_wd)
220 {
221 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
222 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
223 return (IV_FAIL);
224 }
225
226 if (u4_ht != ps_curr_cfg->u4_disp_ht)
227 {
228 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
229 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
230 return (IV_FAIL);
231 }
232
233 return IV_SUCCESS;
234 }
235
236 /**
237 *******************************************************************************
238 *
239 * @brief
240 * Used to test arguments for corresponding API call
241 *
242 * @par Description:
243 * For each command the arguments are validated
244 *
245 * @param[in] ps_handle
246 * Codec handle at API level
247 *
248 * @param[in] pv_api_ip
249 * Pointer to input structure
250 *
251 * @param[out] pv_api_op
252 * Pointer to output structure
253 *
254 * @returns error status
255 *
256 * @remarks none
257 *
258 *******************************************************************************
259 */
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)260 static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
261 void *pv_api_ip,
262 void *pv_api_op)
263 {
264 /* api call */
265 WORD32 command = IV_CMD_NA;
266
267 /* input structure expected by the api call */
268 UWORD32 *pu4_api_ip = pv_api_ip;
269
270 /* output structure expected by the api call */
271 UWORD32 *pu4_api_op = pv_api_op;
272
273 /* temp var */
274 WORD32 i, j;
275
276 if (NULL == pv_api_op || NULL == pv_api_ip)
277 {
278 return (IV_FAIL);
279 }
280
281 /* get command */
282 command = pu4_api_ip[1];
283
284 /* set error code */
285 pu4_api_op[1] = 0;
286
287 /* error checks on handle */
288 switch (command)
289 {
290 case IV_CMD_GET_NUM_MEM_REC:
291 case IV_CMD_FILL_NUM_MEM_REC:
292 break;
293
294 case IV_CMD_INIT:
295 if (ps_handle == NULL)
296 {
297 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
298 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
299 return IV_FAIL;
300 }
301
302 if (ps_handle->u4_size != sizeof(iv_obj_t))
303 {
304 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
305 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
306 return IV_FAIL;
307 }
308 break;
309
310 case IVE_CMD_QUEUE_INPUT:
311 case IVE_CMD_QUEUE_OUTPUT:
312 case IVE_CMD_DEQUEUE_OUTPUT:
313 case IVE_CMD_GET_RECON:
314 case IV_CMD_RETRIEVE_MEMREC:
315 case IVE_CMD_VIDEO_CTL:
316 case IVE_CMD_VIDEO_ENCODE:
317
318 if (ps_handle == NULL)
319 {
320 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
321 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
322 return IV_FAIL;
323 }
324
325 if (ps_handle->u4_size != sizeof(iv_obj_t))
326 {
327 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
328 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
329 return IV_FAIL;
330 }
331
332 if (ps_handle->pv_fxns != ih264e_api_function)
333 {
334 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
335 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
336 return IV_FAIL;
337 }
338
339 if (ps_handle->pv_codec_handle == NULL)
340 {
341 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
342 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
343 return IV_FAIL;
344 }
345 break;
346
347 default:
348 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
349 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
350 return IV_FAIL;
351 }
352
353 /* error checks on input output structures */
354 switch (command)
355 {
356 case IV_CMD_GET_NUM_MEM_REC:
357 {
358 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip;
359 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
360
361 ps_op->s_ive_op.u4_error_code = 0;
362
363 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t))
364 {
365 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
366 ps_op->s_ive_op.u4_error_code |=
367 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
368 return (IV_FAIL);
369 }
370
371 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t))
372 {
373 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
374 ps_op->s_ive_op.u4_error_code |=
375 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
376 return (IV_FAIL);
377 }
378 break;
379 }
380
381 case IV_CMD_FILL_NUM_MEM_REC:
382 {
383 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
384 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
385
386 iv_mem_rec_t *ps_mem_rec = NULL;
387
388 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
389 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
390
391 ps_op->s_ive_op.u4_error_code = 0;
392
393 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t))
394 {
395 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
396 ps_op->s_ive_op.u4_error_code |=
397 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
398 return (IV_FAIL);
399 }
400
401 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t))
402 {
403 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
404 ps_op->s_ive_op.u4_error_code |=
405 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
406 return (IV_FAIL);
407 }
408
409 if (max_wd < MIN_WD || max_wd > MAX_WD)
410 {
411 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
412 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
413 return (IV_FAIL);
414 }
415
416 if (max_ht < MIN_HT || max_ht > MAX_HT)
417 {
418 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
419 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
420 return (IV_FAIL);
421 }
422
423 /* verify number of mem rec ptr */
424 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
425 {
426 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
427 ps_op->s_ive_op.u4_error_code |=
428 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
429 return (IV_FAIL);
430 }
431
432 /* verify number of mem records */
433 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
434 {
435 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
436 ps_op->s_ive_op.u4_error_code |=
437 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
438 return IV_FAIL;
439 }
440
441 /* check mem records sizes are correct */
442 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
443 for (i = 0; i < MEM_REC_CNT; i++)
444 {
445 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
446 {
447 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
448 ps_op->s_ive_op.u4_error_code |=
449 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
450 return IV_FAIL;
451 }
452 }
453 break;
454 }
455
456 case IV_CMD_INIT:
457 {
458 ih264e_init_ip_t *ps_ip = pv_api_ip;
459 ih264e_init_op_t *ps_op = pv_api_op;
460
461 iv_mem_rec_t *ps_mem_rec = NULL;
462
463 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
464 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
465
466 ps_op->s_ive_op.u4_error_code = 0;
467
468 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t))
469 {
470 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
471 ps_op->s_ive_op.u4_error_code |=
472 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
473 return (IV_FAIL);
474 }
475
476 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t))
477 {
478 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
479 ps_op->s_ive_op.u4_error_code |=
480 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
481 return (IV_FAIL);
482 }
483
484 if (max_wd < MIN_WD || max_wd > MAX_WD)
485 {
486 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
487 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
488 return (IV_FAIL);
489 }
490
491 if (max_ht < MIN_HT || max_ht > MAX_HT)
492 {
493 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
494 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
495 return (IV_FAIL);
496 }
497
498 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
499 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
500 {
501 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
502 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
503 return (IV_FAIL);
504 }
505
506 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
507 {
508 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
509 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
510 return (IV_FAIL);
511 }
512
513 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10)
514 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B)
515 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11)
516 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12)
517 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13)
518 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20)
519 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21)
520 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22)
521 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30)
522 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31)
523 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32)
524 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40)
525 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41)
526 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42)
527 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50)
528 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
529 {
530 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
531 ps_op->s_ive_op.u4_error_code |=
532 IH264E_CODEC_LEVEL_NOT_SUPPORTED;
533 return (IV_FAIL);
534 }
535
536 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
537 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
538 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
539 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
540 {
541 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
542 ps_op->s_ive_op.u4_error_code |=
543 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
544 return (IV_FAIL);
545 }
546
547 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
548 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV)
549 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU))
550 {
551 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
552 ps_op->s_ive_op.u4_error_code |=
553 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
554 return (IV_FAIL);
555 }
556
557 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE)
558 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE)
559 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
560 {
561 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
562 ps_op->s_ive_op.u4_error_code |=
563 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
564 return (IV_FAIL);
565 }
566
567 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
568 {
569 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
570 ps_op->s_ive_op.u4_error_code |=
571 IH264E_FRAME_RATE_NOT_SUPPORTED;
572 return (IV_FAIL);
573 }
574
575 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE)
576 {
577 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
578 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
579 return (IV_FAIL);
580 }
581
582 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES)
583 {
584 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
585 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
586 return (IV_FAIL);
587 }
588
589 if (ps_ip->s_ive_ip.u4_num_bframes
590 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
591 {
592 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
593 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
594 return (IV_FAIL);
595 }
596
597 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
598 {
599 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
600 ps_op->s_ive_op.u4_error_code |=
601 IH264E_CONTENT_TYPE_NOT_SUPPORTED;
602 return (IV_FAIL);
603 }
604
605 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
606 {
607 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
608 ps_op->s_ive_op.u4_error_code |=
609 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
610 return (IV_FAIL);
611 }
612
613 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
614 {
615 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
616 ps_op->s_ive_op.u4_error_code |=
617 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
618 return (IV_FAIL);
619 }
620
621 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
622 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS))
623 {
624 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
625 ps_op->s_ive_op.u4_error_code |=
626 IH264E_SLICE_TYPE_INPUT_INVALID;
627 return (IV_FAIL);
628 }
629
630 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS)
631 {
632 if (ps_ip->s_ive_ip.u4_slice_param == 0
633 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4))
634 {
635 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
636 ps_op->s_ive_op.u4_error_code |=
637 IH264E_SLICE_PARAM_INPUT_INVALID;
638 return (IV_FAIL);
639 }
640 }
641
642 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
643 {
644 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
645 ps_op->s_ive_op.u4_error_code |=
646 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
647 return (IV_FAIL);
648 }
649
650 /* verify number of mem records */
651 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
652 {
653 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
654 ps_op->s_ive_op.u4_error_code |=
655 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
656 return (IV_FAIL);
657 }
658
659 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
660
661 /* check memrecords sizes are correct */
662 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++)
663 {
664 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
665 {
666 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
667 ps_op->s_ive_op.u4_error_code |=
668 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
669 return IV_FAIL;
670 }
671
672 /* check memrecords pointers are not NULL */
673 if (ps_mem_rec[i].pv_base == NULL)
674 {
675 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
676 ps_op->s_ive_op.u4_error_code |=
677 IVE_ERR_MEM_REC_BASE_POINTER_NULL;
678 return IV_FAIL;
679 }
680 }
681
682 /* verify memtabs for overlapping regions */
683 {
684 void *start[MEM_REC_CNT];
685 void *end[MEM_REC_CNT];
686
687 start[0] = (ps_mem_rec[0].pv_base);
688 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base)
689 + ps_mem_rec[0].u4_mem_size - 1;
690
691 for (i = 1; i < MEM_REC_CNT; i++)
692 {
693 /* This array is populated to check memtab overlap */
694 start[i] = (ps_mem_rec[i].pv_base);
695 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base)
696 + ps_mem_rec[i].u4_mem_size - 1;
697
698 for (j = 0; j < i; j++)
699 {
700 if ((start[i] >= start[j]) && (start[i] <= end[j]))
701 {
702 ps_op->s_ive_op.u4_error_code |= 1
703 << IVE_UNSUPPORTEDPARAM;
704 ps_op->s_ive_op.u4_error_code |=
705 IVE_ERR_MEM_REC_OVERLAP_ERR;
706 return IV_FAIL;
707 }
708
709 if ((end[i] >= start[j]) && (end[i] <= end[j]))
710 {
711 ps_op->s_ive_op.u4_error_code |= 1
712 << IVE_UNSUPPORTEDPARAM;
713 ps_op->s_ive_op.u4_error_code |=
714 IVE_ERR_MEM_REC_OVERLAP_ERR;
715 return IV_FAIL;
716 }
717
718 if ((start[i] < start[j]) && (end[i] > end[j]))
719 {
720 ps_op->s_ive_op.u4_error_code |= 1
721 << IVE_UNSUPPORTEDPARAM;
722 ps_op->s_ive_op.u4_error_code |=
723 IVE_ERR_MEM_REC_OVERLAP_ERR;
724 return IV_FAIL;
725 }
726 }
727 }
728 }
729
730 /* re-validate mem records with init config */
731 {
732 /* mem records */
733 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT];
734
735 /* api interface structs */
736 ih264e_fill_mem_rec_ip_t s_ip;
737 ih264e_fill_mem_rec_op_t s_op;
738
739 /* error status */
740 IV_STATUS_T e_status;
741
742 /* temp var */
743 WORD32 i;
744
745 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t);
746 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t);
747
748 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
749 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
750 s_ip.s_ive_ip.u4_max_wd = max_wd;
751 s_ip.s_ive_ip.u4_max_ht = max_ht;
752 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
753 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
754 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
755 s_ip.s_ive_ip.u4_max_reorder_cnt =
756 ps_ip->s_ive_ip.u4_max_reorder_cnt;
757 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
758 s_ip.s_ive_ip.u4_max_srch_rng_x =
759 ps_ip->s_ive_ip.u4_max_srch_rng_x;
760 s_ip.s_ive_ip.u4_max_srch_rng_y =
761 ps_ip->s_ive_ip.u4_max_srch_rng_y;
762
763 for (i = 0; i < MEM_REC_CNT; i++)
764 {
765 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
766 }
767
768 /* fill mem records */
769 e_status = ih264e_api_function(NULL, (void *) &s_ip,
770 (void *) &s_op);
771
772 if (IV_FAIL == e_status)
773 {
774 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
775 return (IV_FAIL);
776 }
777
778 /* verify mem records */
779 for (i = 0; i < MEM_REC_CNT; i++)
780 {
781 if (ps_mem_rec[i].u4_mem_size
782 < s_mem_rec_ittiam_api[i].u4_mem_size)
783 {
784 ps_op->s_ive_op.u4_error_code |= 1
785 << IVE_UNSUPPORTEDPARAM;
786 ps_op->s_ive_op.u4_error_code |=
787 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
788
789 return IV_FAIL;
790 }
791
792 if (ps_mem_rec[i].u4_mem_alignment
793 != s_mem_rec_ittiam_api[i].u4_mem_alignment)
794 {
795 ps_op->s_ive_op.u4_error_code |= 1
796 << IVE_UNSUPPORTEDPARAM;
797 ps_op->s_ive_op.u4_error_code |=
798 IVE_ERR_MEM_REC_ALIGNMENT_ERR;
799
800 return IV_FAIL;
801 }
802
803 if (ps_mem_rec[i].e_mem_type
804 != s_mem_rec_ittiam_api[i].e_mem_type)
805 {
806 UWORD32 check = IV_SUCCESS;
807 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type
808 - ps_mem_rec[i].e_mem_type;
809
810 if ((ps_mem_rec[i].e_mem_type
811 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
812 && (s_mem_rec_ittiam_api[i].e_mem_type
813 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
814 {
815 check = IV_FAIL;
816 }
817
818 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
819 {
820 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
821 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
822
823 if ((diff < 1) || (diff > 3))
824 {
825 /* Difference between 1 and 3 is okay for all cases other than the
826 * two filtered with the MOD condition above */
827 check = IV_FAIL;
828 }
829 }
830 else
831 {
832 if (diff == 1)
833 {
834 /* This particular case is when codec asked for External Persistent,
835 * but got Internal Scratch */
836 check = IV_FAIL;
837 }
838 if ((diff != 2) && (diff != 3))
839 {
840 check = IV_FAIL;
841 }
842 }
843
844 if (check == IV_FAIL)
845 {
846 ps_op->s_ive_op.u4_error_code |= 1
847 << IVE_UNSUPPORTEDPARAM;
848 ps_op->s_ive_op.u4_error_code |=
849 IVE_ERR_MEM_REC_INCORRECT_TYPE;
850
851 return IV_FAIL;
852 }
853 }
854 }
855 }
856 break;
857 }
858
859 case IVE_CMD_QUEUE_INPUT:
860 case IVE_CMD_QUEUE_OUTPUT:
861 case IVE_CMD_DEQUEUE_OUTPUT:
862 case IVE_CMD_GET_RECON:
863 break;
864
865 case IV_CMD_RETRIEVE_MEMREC:
866 {
867 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
868 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
869
870 iv_mem_rec_t *ps_mem_rec = NULL;
871
872 ps_op->s_ive_op.u4_error_code = 0;
873
874 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t))
875 {
876 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
877 ps_op->s_ive_op.u4_error_code |=
878 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
879 return (IV_FAIL);
880 }
881
882 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t))
883 {
884 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
885 ps_op->s_ive_op.u4_error_code |=
886 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
887 return (IV_FAIL);
888 }
889
890 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
891 {
892 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
893 ps_op->s_ive_op.u4_error_code |=
894 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
895 return (IV_FAIL);
896 }
897
898 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
899
900 /* check memrecords sizes are correct */
901 for (i = 0; i < MEM_REC_CNT; i++)
902 {
903 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
904 {
905 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
906 ps_op->s_ive_op.u4_error_code |=
907 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
908 return IV_FAIL;
909 }
910 }
911 break;
912 }
913
914 case IVE_CMD_VIDEO_ENCODE:
915 {
916 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
917 ih264e_video_encode_ip_t *ps_ip = pv_api_ip;
918 ih264e_video_encode_op_t *ps_op = pv_api_op;
919
920 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t))
921 {
922 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
923 ps_op->s_ive_op.u4_error_code |=
924 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
925 return (IV_FAIL);
926 }
927
928 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t))
929 {
930 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
931 ps_op->s_ive_op.u4_error_code |=
932 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
933 return (IV_FAIL);
934 }
935
936 if (NULL != ps_ip->s_ive_ip.s_inp_buf.apv_bufs[0] &&
937 ps_codec->i4_header_mode != 1 &&
938 IV_SUCCESS != api_check_input_dimensions(ps_codec, ps_ip, ps_op))
939 {
940 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
941 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
942 return (IV_FAIL);
943 }
944 break;
945 }
946
947 case IVE_CMD_VIDEO_CTL:
948 {
949 /* ptr to input structure */
950 WORD32 *pu4_ptr_cmd = pv_api_ip;
951
952 /* sub command */
953 WORD32 sub_command = pu4_ptr_cmd[2];
954
955 switch (sub_command)
956 {
957 case IVE_CMD_CTL_SETDEFAULT:
958 {
959 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
960 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
961
962 if (ps_ip->s_ive_ip.u4_size
963 != sizeof(ih264e_ctl_setdefault_ip_t))
964 {
965 ps_op->s_ive_op.u4_error_code |= 1
966 << IVE_UNSUPPORTEDPARAM;
967 ps_op->s_ive_op.u4_error_code |=
968 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
969 return IV_FAIL;
970 }
971
972 if (ps_op->s_ive_op.u4_size
973 != sizeof(ih264e_ctl_setdefault_op_t))
974 {
975 ps_op->s_ive_op.u4_error_code |= 1
976 << IVE_UNSUPPORTEDPARAM;
977 ps_op->s_ive_op.u4_error_code |=
978 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
979 return IV_FAIL;
980 }
981 break;
982 }
983
984 case IVE_CMD_CTL_GETBUFINFO:
985 {
986 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
987
988 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
989 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
990
991 if (ps_ip->s_ive_ip.u4_size
992 != sizeof(ih264e_ctl_getbufinfo_ip_t))
993 {
994 ps_op->s_ive_op.u4_error_code |= 1
995 << IVE_UNSUPPORTEDPARAM;
996 ps_op->s_ive_op.u4_error_code |=
997 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
998 return IV_FAIL;
999 }
1000
1001 if (ps_op->s_ive_op.u4_size
1002 != sizeof(ih264e_ctl_getbufinfo_op_t))
1003 {
1004 ps_op->s_ive_op.u4_error_code |= 1
1005 << IVE_UNSUPPORTEDPARAM;
1006 ps_op->s_ive_op.u4_error_code |=
1007 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
1008 return IV_FAIL;
1009 }
1010
1011 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
1012 {
1013 ps_op->s_ive_op.u4_error_code |= 1
1014 << IVE_UNSUPPORTEDPARAM;
1015 ps_op->s_ive_op.u4_error_code |=
1016 IH264E_WIDTH_NOT_SUPPORTED;
1017 return (IV_FAIL);
1018 }
1019
1020 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd)
1021 {
1022 ps_op->s_ive_op.u4_error_code |= 1
1023 << IVE_UNSUPPORTEDPARAM;
1024 ps_op->s_ive_op.u4_error_code |=
1025 IH264E_WIDTH_NOT_SUPPORTED;
1026 return (IV_FAIL);
1027 }
1028
1029 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
1030 {
1031 ps_op->s_ive_op.u4_error_code |= 1
1032 << IVE_UNSUPPORTEDPARAM;
1033 ps_op->s_ive_op.u4_error_code |=
1034 IH264E_HEIGHT_NOT_SUPPORTED;
1035 return (IV_FAIL);
1036 }
1037
1038 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht)
1039 {
1040 ps_op->s_ive_op.u4_error_code |= 1
1041 << IVE_UNSUPPORTEDPARAM;
1042 ps_op->s_ive_op.u4_error_code |=
1043 IH264E_HEIGHT_NOT_SUPPORTED;
1044 return (IV_FAIL);
1045 }
1046
1047 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
1048 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
1049 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
1050 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
1051 {
1052 ps_op->s_ive_op.u4_error_code |= 1
1053 << IVE_UNSUPPORTEDPARAM;
1054 ps_op->s_ive_op.u4_error_code |=
1055 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
1056 return (IV_FAIL);
1057 }
1058 break;
1059 }
1060
1061 case IVE_CMD_CTL_GETVERSION:
1062 {
1063 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
1064 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
1065
1066 if (ps_ip->s_ive_ip.u4_size
1067 != sizeof(ih264e_ctl_getversioninfo_ip_t))
1068 {
1069 ps_op->s_ive_op.u4_error_code |= 1
1070 << IVE_UNSUPPORTEDPARAM;
1071 ps_op->s_ive_op.u4_error_code |=
1072 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
1073 return IV_FAIL;
1074 }
1075
1076 if (ps_op->s_ive_op.u4_size
1077 != sizeof(ih264e_ctl_getversioninfo_op_t))
1078 {
1079 ps_op->s_ive_op.u4_error_code |= 1
1080 << IVE_UNSUPPORTEDPARAM;
1081 ps_op->s_ive_op.u4_error_code |=
1082 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
1083 return IV_FAIL;
1084 }
1085
1086 if (ps_ip->s_ive_ip.pu1_version == NULL)
1087 {
1088 ps_op->s_ive_op.u4_error_code |= 1
1089 << IVE_UNSUPPORTEDPARAM;
1090 ps_op->s_ive_op.u4_error_code |=
1091 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
1092 return IV_FAIL;
1093 }
1094
1095 break;
1096 }
1097
1098 case IVE_CMD_CTL_FLUSH:
1099 {
1100 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip;
1101 ih264e_ctl_flush_op_t *ps_op = pv_api_op;
1102
1103 if (ps_ip->s_ive_ip.u4_size
1104 != sizeof(ih264e_ctl_flush_ip_t))
1105 {
1106 ps_op->s_ive_op.u4_error_code |= 1
1107 << IVE_UNSUPPORTEDPARAM;
1108 ps_op->s_ive_op.u4_error_code |=
1109 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1110 return IV_FAIL;
1111 }
1112
1113 if (ps_op->s_ive_op.u4_size
1114 != sizeof(ih264e_ctl_flush_op_t))
1115 {
1116 ps_op->s_ive_op.u4_error_code |= 1
1117 << IVE_UNSUPPORTEDPARAM;
1118 ps_op->s_ive_op.u4_error_code |=
1119 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1120 return IV_FAIL;
1121 }
1122
1123 break;
1124 }
1125
1126 case IVE_CMD_CTL_RESET:
1127 {
1128 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip;
1129 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
1130
1131 if (ps_ip->s_ive_ip.u4_size
1132 != sizeof(ih264e_ctl_reset_ip_t))
1133 {
1134 ps_op->s_ive_op.u4_error_code |= 1
1135 << IVE_UNSUPPORTEDPARAM;
1136 ps_op->s_ive_op.u4_error_code |=
1137 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1138 return IV_FAIL;
1139 }
1140
1141 if (ps_op->s_ive_op.u4_size
1142 != sizeof(ih264e_ctl_reset_op_t))
1143 {
1144 ps_op->s_ive_op.u4_error_code |= 1
1145 << IVE_UNSUPPORTEDPARAM;
1146 ps_op->s_ive_op.u4_error_code |=
1147 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1148 return IV_FAIL;
1149 }
1150
1151 break;
1152 }
1153
1154 case IVE_CMD_CTL_SET_NUM_CORES:
1155 {
1156 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
1157 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
1158
1159 if (ps_ip->s_ive_ip.u4_size
1160 != sizeof(ih264e_ctl_set_num_cores_ip_t))
1161 {
1162 ps_op->s_ive_op.u4_error_code |= 1
1163 << IVE_UNSUPPORTEDPARAM;
1164 ps_op->s_ive_op.u4_error_code |=
1165 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1166 return IV_FAIL;
1167 }
1168
1169 if (ps_op->s_ive_op.u4_size
1170 != sizeof(ih264e_ctl_set_num_cores_op_t))
1171 {
1172 ps_op->s_ive_op.u4_error_code |= 1
1173 << IVE_UNSUPPORTEDPARAM;
1174 ps_op->s_ive_op.u4_error_code |=
1175 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1176 return IV_FAIL;
1177 }
1178
1179 if ((ps_ip->s_ive_ip.u4_num_cores < 1)
1180 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
1181 {
1182 ps_op->s_ive_op.u4_error_code |= 1
1183 << IVE_UNSUPPORTEDPARAM;
1184 ps_op->s_ive_op.u4_error_code |=
1185 IH264E_INVALID_NUM_CORES;
1186 return IV_FAIL;
1187 }
1188
1189 break;
1190 }
1191
1192 case IVE_CMD_CTL_SET_DIMENSIONS:
1193 {
1194 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1195
1196 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
1197 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
1198
1199 if (ps_ip->s_ive_ip.u4_size
1200 != sizeof(ih264e_ctl_set_dimensions_ip_t))
1201 {
1202 ps_op->s_ive_op.u4_error_code |= 1
1203 << IVE_UNSUPPORTEDPARAM;
1204 ps_op->s_ive_op.u4_error_code |=
1205 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1206 return IV_FAIL;
1207 }
1208
1209 if (ps_op->s_ive_op.u4_size
1210 != sizeof(ih264e_ctl_set_dimensions_op_t))
1211 {
1212 ps_op->s_ive_op.u4_error_code |= 1
1213 << IVE_UNSUPPORTEDPARAM;
1214 ps_op->s_ive_op.u4_error_code |=
1215 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1216 return IV_FAIL;
1217 }
1218
1219 if (ps_ip->s_ive_ip.u4_wd < MIN_WD)
1220 {
1221 ps_op->s_ive_op.u4_error_code |= 1
1222 << IVE_UNSUPPORTEDPARAM;
1223 ps_op->s_ive_op.u4_error_code |=
1224 IH264E_WIDTH_NOT_SUPPORTED;
1225 return (IV_FAIL);
1226 }
1227
1228 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
1229 {
1230 ps_op->s_ive_op.u4_error_code |= 1
1231 << IVE_UNSUPPORTEDPARAM;
1232 ps_op->s_ive_op.u4_error_code |=
1233 IH264E_WIDTH_NOT_SUPPORTED;
1234 return (IV_FAIL);
1235 }
1236
1237 if (ps_ip->s_ive_ip.u4_ht < MIN_HT)
1238 {
1239 ps_op->s_ive_op.u4_error_code |= 1
1240 << IVE_UNSUPPORTEDPARAM;
1241 ps_op->s_ive_op.u4_error_code |=
1242 IH264E_HEIGHT_NOT_SUPPORTED;
1243 return (IV_FAIL);
1244 }
1245
1246 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1247 {
1248 ps_op->s_ive_op.u4_error_code |= 1
1249 << IVE_UNSUPPORTEDPARAM;
1250 ps_op->s_ive_op.u4_error_code |=
1251 IH264E_HEIGHT_NOT_SUPPORTED;
1252 return (IV_FAIL);
1253 }
1254
1255 if(ps_ip->s_ive_ip.u4_wd & 1)
1256 {
1257 ps_op->s_ive_op.u4_error_code |= 1
1258 << IVE_UNSUPPORTEDPARAM;
1259 ps_op->s_ive_op.u4_error_code |=
1260 IH264E_WIDTH_NOT_SUPPORTED;
1261 return (IV_FAIL);
1262 }
1263
1264 if(ps_ip->s_ive_ip.u4_ht & 1)
1265 {
1266 ps_op->s_ive_op.u4_error_code |= 1
1267 << IVE_UNSUPPORTEDPARAM;
1268 ps_op->s_ive_op.u4_error_code |=
1269 IH264E_HEIGHT_NOT_SUPPORTED;
1270 return (IV_FAIL);
1271 }
1272
1273 break;
1274 }
1275
1276 case IVE_CMD_CTL_SET_FRAMERATE:
1277 {
1278 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1279 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1280
1281 if (ps_ip->s_ive_ip.u4_size
1282 != sizeof(ih264e_ctl_set_frame_rate_ip_t))
1283 {
1284 ps_op->s_ive_op.u4_error_code |= 1
1285 << IVE_UNSUPPORTEDPARAM;
1286 ps_op->s_ive_op.u4_error_code |=
1287 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1288 return IV_FAIL;
1289 }
1290
1291 if (ps_op->s_ive_op.u4_size
1292 != sizeof(ih264e_ctl_set_frame_rate_op_t))
1293 {
1294 ps_op->s_ive_op.u4_error_code |= 1
1295 << IVE_UNSUPPORTEDPARAM;
1296 ps_op->s_ive_op.u4_error_code |=
1297 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1298 return IV_FAIL;
1299 }
1300
1301 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)
1302 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1303 {
1304 ps_op->s_ive_op.u4_error_code |= 1
1305 << IVE_UNSUPPORTEDPARAM;
1306 ps_op->s_ive_op.u4_error_code |=
1307 IH264E_FRAME_RATE_NOT_SUPPORTED;
1308 return (IV_FAIL);
1309 }
1310
1311 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0)
1312 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1313 {
1314 ps_op->s_ive_op.u4_error_code |= 1
1315 << IVE_UNSUPPORTEDPARAM;
1316 ps_op->s_ive_op.u4_error_code |=
1317 IH264E_FRAME_RATE_NOT_SUPPORTED;
1318 return (IV_FAIL);
1319 }
1320
1321 if (ps_ip->s_ive_ip.u4_tgt_frame_rate
1322 > ps_ip->s_ive_ip.u4_src_frame_rate)
1323 {
1324 ps_op->s_ive_op.u4_error_code |= 1
1325 << IVE_UNSUPPORTEDPARAM;
1326 ps_op->s_ive_op.u4_error_code |=
1327 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1328 return (IV_FAIL);
1329 }
1330
1331 break;
1332 }
1333
1334 case IVE_CMD_CTL_SET_BITRATE:
1335 {
1336 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1337 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1338
1339 if (ps_ip->s_ive_ip.u4_size
1340 != sizeof(ih264e_ctl_set_bitrate_ip_t))
1341 {
1342 ps_op->s_ive_op.u4_error_code |= 1
1343 << IVE_UNSUPPORTEDPARAM;
1344 ps_op->s_ive_op.u4_error_code |=
1345 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1346 return IV_FAIL;
1347 }
1348
1349 if (ps_op->s_ive_op.u4_size
1350 != sizeof(ih264e_ctl_set_bitrate_op_t))
1351 {
1352 ps_op->s_ive_op.u4_error_code |= 1
1353 << IVE_UNSUPPORTEDPARAM;
1354 ps_op->s_ive_op.u4_error_code |=
1355 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1356 return IV_FAIL;
1357 }
1358
1359 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE)
1360 || (ps_ip->s_ive_ip.u4_target_bitrate == 0))
1361 {
1362 ps_op->s_ive_op.u4_error_code |= 1
1363 << IVE_UNSUPPORTEDPARAM;
1364 ps_op->s_ive_op.u4_error_code |=
1365 IH264E_BITRATE_NOT_SUPPORTED;
1366 return (IV_FAIL);
1367 }
1368
1369 break;
1370 }
1371
1372 case IVE_CMD_CTL_SET_FRAMETYPE:
1373 {
1374 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1375 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1376
1377 if (ps_ip->s_ive_ip.u4_size
1378 != sizeof(ih264e_ctl_set_frame_type_ip_t))
1379 {
1380 ps_op->s_ive_op.u4_error_code |= 1
1381 << IVE_UNSUPPORTEDPARAM;
1382 ps_op->s_ive_op.u4_error_code |=
1383 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1384 return IV_FAIL;
1385 }
1386
1387 if (ps_op->s_ive_op.u4_size
1388 != sizeof(ih264e_ctl_set_frame_type_op_t))
1389 {
1390 ps_op->s_ive_op.u4_error_code |= 1
1391 << IVE_UNSUPPORTEDPARAM;
1392 ps_op->s_ive_op.u4_error_code |=
1393 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1394 return IV_FAIL;
1395 }
1396
1397 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME)
1398 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME)
1399 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME)
1400 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1401 {
1402 ps_op->s_ive_op.u4_error_code |= 1
1403 << IVE_UNSUPPORTEDPARAM;
1404 ps_op->s_ive_op.u4_error_code |=
1405 IH264E_INVALID_FORCE_FRAME_INPUT;
1406 return IV_FAIL;
1407 }
1408 break;
1409 }
1410
1411 case IVE_CMD_CTL_SET_ME_PARAMS:
1412 {
1413 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1414
1415 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1416 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
1417
1418 if (ps_ip->s_ive_ip.u4_size
1419 != sizeof(ih264e_ctl_set_me_params_ip_t))
1420 {
1421 ps_op->s_ive_op.u4_error_code |= 1
1422 << IVE_UNSUPPORTEDPARAM;
1423 ps_op->s_ive_op.u4_error_code |=
1424 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1425 return IV_FAIL;
1426 }
1427
1428 if (ps_op->s_ive_op.u4_size
1429 != sizeof(ih264e_ctl_set_me_params_op_t))
1430 {
1431 ps_op->s_ive_op.u4_error_code |= 1
1432 << IVE_UNSUPPORTEDPARAM;
1433 ps_op->s_ive_op.u4_error_code |=
1434 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1435 return IV_FAIL;
1436 }
1437
1438 if ((ps_ip->s_ive_ip.u4_me_speed_preset != FULL_SRCH)
1439 && (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1440 && (ps_ip->s_ive_ip.u4_me_speed_preset != HEX_SRCH))
1441 {
1442 ps_op->s_ive_op.u4_error_code |= 1
1443 << IVE_UNSUPPORTEDPARAM;
1444 ps_op->s_ive_op.u4_error_code |=
1445 IH264E_INVALID_ME_SPEED_PRESET;
1446 return IV_FAIL;
1447 }
1448
1449 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0)
1450 && (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1451 {
1452 ps_op->s_ive_op.u4_error_code |= 1
1453 << IVE_UNSUPPORTEDPARAM;
1454 ps_op->s_ive_op.u4_error_code |=
1455 IH264E_INVALID_HALFPEL_OPTION;
1456 return IV_FAIL;
1457 }
1458
1459 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0)
1460 && (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1461 {
1462 ps_op->s_ive_op.u4_error_code |= 1
1463 << IVE_UNSUPPORTEDPARAM;
1464 ps_op->s_ive_op.u4_error_code |=
1465 IH264E_INVALID_QPEL_OPTION;
1466 return IV_FAIL;
1467 }
1468
1469 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0)
1470 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1))
1471 {
1472 ps_op->s_ive_op.u4_error_code |= 1
1473 << IVE_UNSUPPORTEDPARAM;
1474 ps_op->s_ive_op.u4_error_code |=
1475 IH264E_INVALID_FAST_SAD_OPTION;
1476 return IV_FAIL;
1477 }
1478
1479 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255)
1480 {
1481 ps_op->s_ive_op.u4_error_code |= 1
1482 << IVE_UNSUPPORTEDPARAM;
1483 ps_op->s_ive_op.u4_error_code |=
1484 IH264E_INVALID_ALT_REF_OPTION;
1485 return IV_FAIL;
1486 }
1487
1488 if (ps_ip->s_ive_ip.u4_srch_rng_x
1489 > ps_codec->s_cfg.u4_max_srch_rng_x)
1490 {
1491 ps_op->s_ive_op.u4_error_code |= 1
1492 << IVE_UNSUPPORTEDPARAM;
1493 ps_op->s_ive_op.u4_error_code |=
1494 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1495 return (IV_FAIL);
1496 }
1497
1498 if (ps_ip->s_ive_ip.u4_srch_rng_y
1499 > ps_codec->s_cfg.u4_max_srch_rng_y)
1500 {
1501 ps_op->s_ive_op.u4_error_code |= 1
1502 << IVE_UNSUPPORTEDPARAM;
1503 ps_op->s_ive_op.u4_error_code |=
1504 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1505 return (IV_FAIL);
1506 }
1507
1508 break;
1509 }
1510
1511 case IVE_CMD_CTL_SET_IPE_PARAMS:
1512 {
1513 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1514 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1515
1516 if (ps_ip->s_ive_ip.u4_size
1517 != sizeof(ih264e_ctl_set_ipe_params_ip_t))
1518 {
1519 ps_op->s_ive_op.u4_error_code |= 1
1520 << IVE_UNSUPPORTEDPARAM;
1521 ps_op->s_ive_op.u4_error_code |=
1522 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1523 return IV_FAIL;
1524 }
1525
1526 if (ps_op->s_ive_op.u4_size
1527 != sizeof(ih264e_ctl_set_ipe_params_op_t))
1528 {
1529 ps_op->s_ive_op.u4_error_code |= 1
1530 << IVE_UNSUPPORTEDPARAM;
1531 ps_op->s_ive_op.u4_error_code |=
1532 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1533 return IV_FAIL;
1534 }
1535
1536 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0)
1537 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1538 {
1539 ps_op->s_ive_op.u4_error_code |= 1
1540 << IVE_UNSUPPORTEDPARAM;
1541 ps_op->s_ive_op.u4_error_code |=
1542 IH264E_INVALID_INTRA4x4_OPTION;
1543 return IV_FAIL;
1544 }
1545
1546 if ((ps_ip->s_ive_ip.u4_constrained_intra_pred != 0)
1547 && (ps_ip->s_ive_ip.u4_constrained_intra_pred != 1))
1548 {
1549 ps_op->s_ive_op.u4_error_code |= 1
1550 << IVE_UNSUPPORTEDPARAM;
1551 ps_op->s_ive_op.u4_error_code |=
1552 IH264E_INVALID_CONSTRAINED_INTRA_PREDICTION_MODE;
1553 return IV_FAIL;
1554 }
1555
1556 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG)
1557 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST)
1558 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL)
1559 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST)
1560 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED)
1561 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1562 {
1563 ps_op->s_ive_op.u4_error_code |= 1
1564 << IVE_UNSUPPORTEDPARAM;
1565 ps_op->s_ive_op.u4_error_code |=
1566 IH264E_INVALID_ENC_SPEED_PRESET;
1567 return IV_FAIL;
1568 }
1569
1570 break;
1571 }
1572
1573 case IVE_CMD_CTL_SET_GOP_PARAMS:
1574 {
1575 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1576 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1577
1578 if (ps_ip->s_ive_ip.u4_size
1579 != sizeof(ih264e_ctl_set_gop_params_ip_t))
1580 {
1581 ps_op->s_ive_op.u4_error_code |= 1
1582 << IVE_UNSUPPORTEDPARAM;
1583 ps_op->s_ive_op.u4_error_code |=
1584 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1585 return IV_FAIL;
1586 }
1587
1588 if (ps_op->s_ive_op.u4_size
1589 != sizeof(ih264e_ctl_set_gop_params_op_t))
1590 {
1591 ps_op->s_ive_op.u4_error_code |= 1
1592 << IVE_UNSUPPORTEDPARAM;
1593 ps_op->s_ive_op.u4_error_code |=
1594 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1595 return IV_FAIL;
1596 }
1597
1598 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1599 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1600 {
1601 ps_op->s_ive_op.u4_error_code |= 1
1602 << IVE_UNSUPPORTEDPARAM;
1603 ps_op->s_ive_op.u4_error_code |=
1604 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1605 return IV_FAIL;
1606 }
1607
1608 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1609 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1610 {
1611 ps_op->s_ive_op.u4_error_code |= 1
1612 << IVE_UNSUPPORTEDPARAM;
1613 ps_op->s_ive_op.u4_error_code |=
1614 IH264E_INVALID_IDR_FRAME_INTERVAL;
1615 return IV_FAIL;
1616 }
1617
1618 break;
1619 }
1620
1621 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
1622 {
1623 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1624 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1625
1626 if (ps_ip->s_ive_ip.u4_size
1627 != sizeof(ih264e_ctl_set_deblock_params_ip_t))
1628 {
1629 ps_op->s_ive_op.u4_error_code |= 1
1630 << IVE_UNSUPPORTEDPARAM;
1631 ps_op->s_ive_op.u4_error_code |=
1632 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1633 return IV_FAIL;
1634 }
1635
1636 if (ps_op->s_ive_op.u4_size
1637 != sizeof(ih264e_ctl_set_deblock_params_op_t))
1638 {
1639 ps_op->s_ive_op.u4_error_code |= 1
1640 << IVE_UNSUPPORTEDPARAM;
1641 ps_op->s_ive_op.u4_error_code |=
1642 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1643 return IV_FAIL;
1644 }
1645
1646 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0)
1647 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2)
1648 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3)
1649 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1650 {
1651 ps_op->s_ive_op.u4_error_code |= 1
1652 << IVE_UNSUPPORTEDPARAM;
1653 ps_op->s_ive_op.u4_error_code |=
1654 IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1655 return IV_FAIL;
1656 }
1657
1658 break;
1659 }
1660
1661 case IVE_CMD_CTL_SET_QP:
1662 {
1663 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1664 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op;
1665
1666 if (ps_ip->s_ive_ip.u4_size
1667 != sizeof(ih264e_ctl_set_qp_ip_t))
1668 {
1669 ps_op->s_ive_op.u4_error_code |= 1
1670 << IVE_UNSUPPORTEDPARAM;
1671 ps_op->s_ive_op.u4_error_code |=
1672 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1673 return IV_FAIL;
1674 }
1675
1676 if (ps_op->s_ive_op.u4_size
1677 != sizeof(ih264e_ctl_set_qp_op_t))
1678 {
1679 ps_op->s_ive_op.u4_error_code |= 1
1680 << IVE_UNSUPPORTEDPARAM;
1681 ps_op->s_ive_op.u4_error_code |=
1682 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1683 return IV_FAIL;
1684 }
1685
1686 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP)
1687 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP)
1688 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP))
1689 {
1690 ps_op->s_ive_op.u4_error_code |= 1
1691 << IVE_UNSUPPORTEDPARAM;
1692 ps_op->s_ive_op.u4_error_code |=
1693 IH264E_INVALID_MAX_FRAME_QP;
1694 return IV_FAIL;
1695 }
1696
1697 /* We donot support QP < 4 */
1698 if ((ps_ip->s_ive_ip.u4_i_qp_min < 4)
1699 || (ps_ip->s_ive_ip.u4_p_qp_min < 4)
1700 || (ps_ip->s_ive_ip.u4_b_qp_min < 4)
1701 || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max)
1702 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max)
1703 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max))
1704 {
1705 ps_op->s_ive_op.u4_error_code |= 1
1706 << IVE_UNSUPPORTEDPARAM;
1707 ps_op->s_ive_op.u4_error_code |=
1708 IH264E_INVALID_MIN_FRAME_QP;
1709 return IV_FAIL;
1710 }
1711
1712 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max)
1713 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max)
1714 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max))
1715 {
1716 ps_op->s_ive_op.u4_error_code |= 1
1717 << IVE_UNSUPPORTEDPARAM;
1718 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1719 return IV_FAIL;
1720 }
1721
1722 if ((ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min)
1723 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min)
1724 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min))
1725 {
1726 ps_op->s_ive_op.u4_error_code |= 1
1727 << IVE_UNSUPPORTEDPARAM;
1728 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1729 return IV_FAIL;
1730 }
1731
1732 break;
1733 }
1734
1735 case IVE_CMD_CTL_SET_VUI_PARAMS:
1736 {
1737 ih264e_vui_ip_t *ps_ip = pv_api_ip;
1738 ih264e_vui_op_t *ps_op = pv_api_op;
1739
1740 if(ps_ip->u4_size != sizeof(ih264e_vui_ip_t))
1741 {
1742 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1743 ps_op->u4_error_code |=
1744 IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1745 return IV_FAIL;
1746 }
1747
1748 if(ps_op->u4_size != sizeof(ih264e_vui_op_t))
1749 {
1750 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1751 ps_op->u4_error_code |=
1752 IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1753 return IV_FAIL;
1754 }
1755
1756 break;
1757 }
1758
1759 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
1760 {
1761 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
1762 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
1763
1764 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_ip_t))
1765 {
1766 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1767 ps_op->u4_error_code |=
1768 IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1769 return IV_FAIL;
1770 }
1771
1772 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_op_t))
1773 {
1774 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1775 ps_op->u4_error_code |=
1776 IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1777 return IV_FAIL;
1778 }
1779
1780 if((ps_ip->u1_sei_mdcv_params_present_flag != 0)
1781 && (ps_ip->u1_sei_mdcv_params_present_flag) != 1)
1782 {
1783 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1784 ps_op->u4_error_code |=
1785 IH264E_INVALID_SEI_MDCV_PARAMS;
1786 return IV_FAIL;
1787 }
1788
1789 if(1 == ps_ip->u1_sei_mdcv_params_present_flag)
1790 {
1791 /* Check values for u2_display_primaries_x and u2_display_primaries_y */
1792 for(i = 0; i < 3; i++)
1793 {
1794 if((ps_ip->au2_display_primaries_x[i] >
1795 DISPLAY_PRIMARIES_X_UPPER_LIMIT) ||
1796 (ps_ip->au2_display_primaries_x[i] <
1797 DISPLAY_PRIMARIES_X_LOWER_LIMIT) ||
1798 ((ps_ip->au2_display_primaries_x[i] %
1799 DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0))
1800 {
1801 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1802 ps_op->u4_error_code |=
1803 IH264E_INVALID_SEI_MDCV_PARAMS;
1804 return IV_FAIL;
1805 }
1806
1807 if((ps_ip->au2_display_primaries_y[i] >
1808 DISPLAY_PRIMARIES_Y_UPPER_LIMIT) ||
1809 (ps_ip->au2_display_primaries_y[i] <
1810 DISPLAY_PRIMARIES_Y_LOWER_LIMIT) ||
1811 ((ps_ip->au2_display_primaries_y[i] %
1812 DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0))
1813 {
1814 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1815 ps_op->u4_error_code |=
1816 IH264E_INVALID_SEI_MDCV_PARAMS;
1817 return IV_FAIL;
1818 }
1819 }
1820
1821 if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) ||
1822 (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) ||
1823 ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0))
1824 {
1825 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1826 ps_op->u4_error_code |=
1827 IH264E_INVALID_SEI_MDCV_PARAMS;
1828 return IV_FAIL;
1829 }
1830
1831 if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) ||
1832 (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) ||
1833 ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0))
1834 {
1835 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1836 ps_op->u4_error_code |=
1837 IH264E_INVALID_SEI_MDCV_PARAMS;
1838 return IV_FAIL;
1839 }
1840
1841 if((ps_ip->u4_max_display_mastering_luminance >
1842 MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1843 (ps_ip->u4_max_display_mastering_luminance <
1844 MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) ||
1845 ((ps_ip->u4_max_display_mastering_luminance %
1846 MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0))
1847 {
1848 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1849 ps_op->u4_error_code |=
1850 IH264E_INVALID_SEI_MDCV_PARAMS;
1851 return IV_FAIL;
1852 }
1853
1854 if((ps_ip->u4_min_display_mastering_luminance >
1855 MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT ) ||
1856 (ps_ip->u4_min_display_mastering_luminance <
1857 MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT))
1858 {
1859 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1860 ps_op->u4_error_code |=
1861 IH264E_INVALID_SEI_MDCV_PARAMS;
1862 return IV_FAIL;
1863 }
1864
1865 if(ps_ip->u4_max_display_mastering_luminance <=
1866 ps_ip->u4_min_display_mastering_luminance)
1867 {
1868 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1869 ps_op->u4_error_code |=
1870 IH264E_INVALID_SEI_MDCV_PARAMS;
1871 return IV_FAIL;
1872 }
1873 }
1874 break;
1875 }
1876
1877 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
1878 {
1879 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
1880 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
1881
1882 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_ip_t))
1883 {
1884 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1885 ps_op->u4_error_code |=
1886 IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1887 return IV_FAIL;
1888 }
1889
1890 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_op_t))
1891 {
1892 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1893 ps_op->u4_error_code |=
1894 IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1895 return IV_FAIL;
1896 }
1897
1898 if((ps_ip->u1_sei_cll_params_present_flag != 0)
1899 && (ps_ip->u1_sei_cll_params_present_flag != 1))
1900 {
1901 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1902 ps_op->u4_error_code |=
1903 IH264E_INVALID_SEI_CLL_PARAMS;
1904 return IV_FAIL;
1905 }
1906 break;
1907 }
1908
1909 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
1910 {
1911 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
1912 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
1913
1914 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_ip_t))
1915 {
1916 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1917 ps_op->u4_error_code |=
1918 IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1919 return IV_FAIL;
1920 }
1921
1922 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_op_t))
1923 {
1924 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1925 ps_op->u4_error_code |=
1926 IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1927 return IV_FAIL;
1928 }
1929
1930 if((ps_ip->u1_sei_ave_params_present_flag != 0)
1931 && (ps_ip->u1_sei_ave_params_present_flag != 1))
1932 {
1933 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1934 ps_op->u4_error_code |=
1935 IH264E_INVALID_SEI_AVE_PARAMS;
1936 return IV_FAIL;
1937 }
1938
1939 if(1 == ps_ip->u1_sei_ave_params_present_flag)
1940 {
1941 if((0 == ps_ip->u4_ambient_illuminance))
1942 {
1943 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1944 ps_op->u4_error_code |=
1945 IH264E_INVALID_SEI_AVE_PARAMS;
1946 return IV_FAIL;
1947 }
1948
1949 if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT)
1950 {
1951 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1952 ps_op->u4_error_code |=
1953 IH264E_INVALID_SEI_AVE_PARAMS;
1954 return IV_FAIL;
1955 }
1956
1957 if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT)
1958 {
1959 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1960 ps_op->u4_error_code |=
1961 IH264E_INVALID_SEI_AVE_PARAMS;
1962 return IV_FAIL;
1963 }
1964 }
1965 break;
1966 }
1967
1968 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
1969 {
1970 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
1971 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
1972
1973 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_ip_t))
1974 {
1975 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1976 ps_op->u4_error_code |=
1977 IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1978 return IV_FAIL;
1979 }
1980
1981 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_op_t))
1982 {
1983 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1984 ps_op->u4_error_code |=
1985 IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1986 return IV_FAIL;
1987 }
1988
1989 if((ps_ip->u1_sei_ccv_params_present_flag != 0)
1990 && (ps_ip->u1_sei_ccv_params_present_flag != 1))
1991 {
1992 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1993 ps_op->u4_error_code |=
1994 IH264E_INVALID_SEI_CCV_PARAMS;
1995 return IV_FAIL;
1996 }
1997
1998
1999 if(1 == ps_ip->u1_sei_ccv_params_present_flag)
2000 {
2001 if((ps_ip->u1_ccv_cancel_flag != 0)
2002 && (ps_ip->u1_ccv_cancel_flag != 1))
2003 {
2004 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2005 ps_op->u4_error_code |=
2006 IH264E_INVALID_SEI_CCV_PARAMS;
2007 return IV_FAIL;
2008 }
2009
2010 if(0 == ps_ip->u1_ccv_cancel_flag)
2011 {
2012 if((ps_ip->u1_ccv_persistence_flag != 0)
2013 && (ps_ip->u1_ccv_persistence_flag != 1))
2014 {
2015 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2016 ps_op->u4_error_code |=
2017 IH264E_INVALID_SEI_CCV_PARAMS;
2018 return IV_FAIL;
2019 }
2020 if((ps_ip->u1_ccv_primaries_present_flag != 0)
2021 && (ps_ip->u1_ccv_primaries_present_flag != 1))
2022 {
2023 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2024 ps_op->u4_error_code |=
2025 IH264E_INVALID_SEI_CCV_PARAMS;
2026 return IV_FAIL;
2027 }
2028 if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0)
2029 && (ps_ip->u1_ccv_min_luminance_value_present_flag != 1))
2030 {
2031 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2032 ps_op->u4_error_code |=
2033 IH264E_INVALID_SEI_CCV_PARAMS;
2034 return IV_FAIL;
2035 }
2036 if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0)
2037 && (ps_ip->u1_ccv_max_luminance_value_present_flag != 1))
2038 {
2039 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2040 ps_op->u4_error_code |=
2041 IH264E_INVALID_SEI_CCV_PARAMS;
2042 return IV_FAIL;
2043 }
2044 if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0)
2045 && (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1))
2046 {
2047 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2048 ps_op->u4_error_code |=
2049 IH264E_INVALID_SEI_CCV_PARAMS;
2050 return IV_FAIL;
2051 }
2052 if((ps_ip->u1_ccv_primaries_present_flag == 0)
2053 && (ps_ip->u1_ccv_min_luminance_value_present_flag == 0)
2054 && (ps_ip->u1_ccv_max_luminance_value_present_flag == 0)
2055 && (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0))
2056 {
2057 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2058 ps_op->u4_error_code |=
2059 IH264E_INVALID_SEI_CCV_PARAMS;
2060 return IV_FAIL;
2061 }
2062
2063 if((ps_ip->u1_ccv_reserved_zero_2bits != 0))
2064 {
2065 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2066 ps_op->u4_error_code |=
2067 IH264E_INVALID_SEI_CCV_PARAMS;
2068 return IV_FAIL;
2069 }
2070
2071 if(1 == ps_ip->u1_ccv_primaries_present_flag)
2072 {
2073 for(i = 0; i < 3; i++)
2074 {
2075 if((ps_ip->ai4_ccv_primaries_x[i] >
2076 CCV_PRIMARIES_X_UPPER_LIMIT) ||
2077 (ps_ip->ai4_ccv_primaries_x[i] <
2078 CCV_PRIMARIES_X_LOWER_LIMIT))
2079 {
2080 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2081 ps_op->u4_error_code |=
2082 IH264E_INVALID_SEI_CCV_PARAMS;
2083 return IV_FAIL;
2084 }
2085
2086 if((ps_ip->ai4_ccv_primaries_y[i] >
2087 CCV_PRIMARIES_Y_UPPER_LIMIT) ||
2088 (ps_ip->ai4_ccv_primaries_y[i] <
2089 CCV_PRIMARIES_Y_LOWER_LIMIT))
2090 {
2091 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2092 ps_op->u4_error_code |=
2093 IH264E_INVALID_SEI_CCV_PARAMS;
2094 return IV_FAIL;
2095 }
2096 }
2097 }
2098
2099 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
2100 (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag))
2101 {
2102 if((ps_ip->u4_ccv_avg_luminance_value <
2103 ps_ip->u4_ccv_min_luminance_value))
2104 {
2105 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2106 ps_op->u4_error_code |=
2107 IH264E_INVALID_SEI_CCV_PARAMS;
2108 return IV_FAIL;
2109 }
2110 }
2111
2112 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
2113 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2114 {
2115 if((ps_ip->u4_ccv_max_luminance_value <
2116 ps_ip->u4_ccv_min_luminance_value))
2117 {
2118 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2119 ps_op->u4_error_code |=
2120 IH264E_INVALID_SEI_CCV_PARAMS;
2121 return IV_FAIL;
2122 }
2123 }
2124 if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) &&
2125 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2126 {
2127 if((ps_ip->u4_ccv_max_luminance_value <
2128 ps_ip->u4_ccv_avg_luminance_value))
2129 {
2130 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2131 ps_op->u4_error_code |=
2132 IH264E_INVALID_SEI_CCV_PARAMS;
2133 return IV_FAIL;
2134 }
2135 }
2136 }
2137 }
2138 break;
2139 }
2140
2141 case IVE_CMD_CTL_SET_SEI_SII_PARAMS:
2142 {
2143 ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip;
2144 ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op;
2145
2146 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_ip_t))
2147 {
2148 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2149 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT;
2150 return IV_FAIL;
2151 }
2152
2153 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_op_t))
2154 {
2155 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2156 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT;
2157 return IV_FAIL;
2158 }
2159
2160 /* The below error check is based on H264 spec docs SII syntax */
2161 if(0 != ps_ip->u4_sii_sub_layer_idx)
2162 {
2163 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2164 ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS;
2165 return IV_FAIL;
2166 }
2167
2168 if(ps_ip->u1_sii_max_sub_layers_minus1 > 7)
2169 {
2170 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2171 ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS;
2172 return IV_FAIL;
2173 }
2174
2175 if((ps_ip->u4_sii_sub_layer_idx > 0) &&
2176 (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 1))
2177 {
2178 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2179 ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND;
2180 return IV_FAIL;
2181 }
2182
2183 if((ps_ip->u4_sii_sub_layer_idx > ps_ip->u1_sii_max_sub_layers_minus1) &&
2184 (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 0))
2185 {
2186 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2187 ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND;
2188 return IV_FAIL;
2189 }
2190
2191 break;
2192 }
2193
2194 case IVE_CMD_CTL_SET_ENC_MODE:
2195 {
2196 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
2197 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
2198
2199 if (ps_ip->s_ive_ip.u4_size
2200 != sizeof(ih264e_ctl_set_enc_mode_ip_t))
2201 {
2202 ps_op->s_ive_op.u4_error_code |= 1
2203 << IVE_UNSUPPORTEDPARAM;
2204 ps_op->s_ive_op.u4_error_code |=
2205 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2206 return IV_FAIL;
2207 }
2208
2209 if (ps_op->s_ive_op.u4_size
2210 != sizeof(ih264e_ctl_set_enc_mode_op_t))
2211 {
2212 ps_op->s_ive_op.u4_error_code |= 1
2213 << IVE_UNSUPPORTEDPARAM;
2214 ps_op->s_ive_op.u4_error_code |=
2215 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2216 return IV_FAIL;
2217 }
2218
2219 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER)
2220 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
2221 {
2222 ps_op->s_ive_op.u4_error_code |= 1
2223 << IVE_UNSUPPORTEDPARAM;
2224 ps_op->s_ive_op.u4_error_code |=
2225 IH264E_INVALID_ENC_OPERATION_MODE;
2226 return IV_FAIL;
2227 }
2228
2229 break;
2230 }
2231
2232 case IVE_CMD_CTL_SET_VBV_PARAMS:
2233 {
2234 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
2235 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
2236
2237 if (ps_ip->s_ive_ip.u4_size
2238 != sizeof(ih264e_ctl_set_vbv_params_ip_t))
2239 {
2240 ps_op->s_ive_op.u4_error_code |= 1
2241 << IVE_UNSUPPORTEDPARAM;
2242 ps_op->s_ive_op.u4_error_code |=
2243 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2244 return IV_FAIL;
2245 }
2246
2247 if (ps_op->s_ive_op.u4_size
2248 != sizeof(ih264e_ctl_set_vbv_params_op_t))
2249 {
2250 ps_op->s_ive_op.u4_error_code |= 1
2251 << IVE_UNSUPPORTEDPARAM;
2252 ps_op->s_ive_op.u4_error_code |=
2253 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2254 return IV_FAIL;
2255 }
2256
2257 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY)
2258 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY))
2259 {
2260 ps_op->s_ive_op.u4_error_code |= 1
2261 << IVE_UNSUPPORTEDPARAM;
2262 ps_op->s_ive_op.u4_error_code |=
2263 IH264E_INVALID_BUFFER_DELAY;
2264 return IV_FAIL;
2265 }
2266
2267 break;
2268 }
2269
2270 case IVE_CMD_CTL_SET_AIR_PARAMS:
2271 {
2272 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
2273 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
2274
2275 if (ps_ip->s_ive_ip.u4_size
2276 != sizeof(ih264e_ctl_set_air_params_ip_t))
2277 {
2278 ps_op->s_ive_op.u4_error_code |= 1
2279 << IVE_UNSUPPORTEDPARAM;
2280 ps_op->s_ive_op.u4_error_code |=
2281 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2282 return IV_FAIL;
2283 }
2284
2285 if (ps_op->s_ive_op.u4_size
2286 != sizeof(ih264e_ctl_set_air_params_op_t))
2287 {
2288 ps_op->s_ive_op.u4_error_code |= 1
2289 << IVE_UNSUPPORTEDPARAM;
2290 ps_op->s_ive_op.u4_error_code |=
2291 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2292 return IV_FAIL;
2293 }
2294
2295 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE)
2296 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC)
2297 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
2298 {
2299 ps_op->s_ive_op.u4_error_code |= 1
2300 << IVE_UNSUPPORTEDPARAM;
2301 ps_op->s_ive_op.u4_error_code |=
2302 IH264E_INVALID_AIR_MODE;
2303 return IV_FAIL;
2304 }
2305
2306 if (ps_ip->s_ive_ip.u4_air_refresh_period == 0)
2307 {
2308 ps_op->s_ive_op.u4_error_code |= 1
2309 << IVE_UNSUPPORTEDPARAM;
2310 ps_op->s_ive_op.u4_error_code |=
2311 IH264E_INVALID_AIR_REFRESH_PERIOD;
2312 return IV_FAIL;
2313 }
2314
2315 break;
2316 }
2317
2318 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
2319 {
2320 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
2321 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
2322
2323 if (ps_ip->s_ive_ip.u4_size
2324 != sizeof(ih264e_ctl_set_profile_params_ip_t))
2325 {
2326 ps_op->s_ive_op.u4_error_code |= 1
2327 << IVE_UNSUPPORTEDPARAM;
2328 ps_op->s_ive_op.u4_error_code |=
2329 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2330 return IV_FAIL;
2331 }
2332
2333 if (ps_op->s_ive_op.u4_size
2334 != sizeof(ih264e_ctl_set_profile_params_op_t))
2335 {
2336 ps_op->s_ive_op.u4_error_code |= 1
2337 << IVE_UNSUPPORTEDPARAM;
2338 ps_op->s_ive_op.u4_error_code |=
2339 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2340 return IV_FAIL;
2341 }
2342
2343 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
2344 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
2345 {
2346 ps_op->s_ive_op.u4_error_code |= 1
2347 << IVE_UNSUPPORTEDPARAM;
2348 ps_op->s_ive_op.u4_error_code |=
2349 IH264E_PROFILE_NOT_SUPPORTED;
2350 return IV_FAIL;
2351 }
2352
2353 if (ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
2354 {
2355 ps_op->s_ive_op.u4_error_code |= 1
2356 << IVE_UNSUPPORTEDPARAM;
2357 ps_op->s_ive_op.u4_error_code |=
2358 IH264E_INVALID_ENTROPY_CODING_MODE;
2359 return IV_FAIL;
2360 }
2361
2362 break;
2363 }
2364
2365 default:
2366 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2367 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
2368 return IV_FAIL;
2369 }
2370
2371 break;
2372 }
2373
2374 default:
2375 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2376 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
2377 return IV_FAIL;
2378 }
2379
2380 return IV_SUCCESS;
2381 }
2382
2383 /**
2384 *******************************************************************************
2385 *
2386 * @brief update encoder configuration parameters
2387 *
2388 * @par Description:
2389 * updates encoder configuration parameters from the given config set.
2390 * Initialize/reinitialize codec parameters according to new configurations.
2391 *
2392 * @param[in] ps_codec
2393 * Pointer to codec context
2394 *
2395 * @param[in] ps_cfg
2396 * Pointer to config param set
2397 *
2398 * @remarks none
2399 *
2400 *******************************************************************************
2401 */
ih264e_codec_update_config(codec_t * ps_codec,cfg_params_t * ps_cfg)2402 IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec,
2403 cfg_params_t *ps_cfg)
2404 {
2405 /* config params */
2406 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
2407
2408 /* error status */
2409 IH264E_ERROR_T err = IH264E_SUCCESS;
2410
2411 /* temp var */
2412 UWORD32 u4_init_rc = 0;
2413
2414 /***********************/
2415 /* UPDATE CODEC CONFIG */
2416 /***********************/
2417 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS)
2418 {
2419 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd);
2420 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht);
2421
2422 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln
2423 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd
2424 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht)
2425 {
2426 ps_curr_cfg->u4_wd = wd_aln;
2427 ps_curr_cfg->u4_ht = ht_aln;
2428
2429 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd;
2430 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht;
2431
2432 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4;
2433 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4;
2434
2435 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD;
2436
2437 /* If number of MBs in a frame changes the air map also changes.
2438 * Hence recompute air map also reset air pic cnt */
2439 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE)
2440 {
2441 /* re-init the air map */
2442 ih264e_init_air_map(ps_codec);
2443
2444 /* reset air counter */
2445 ps_codec->i4_air_pic_cnt = -1;
2446 }
2447
2448 /* initialize mv bank buffer manager */
2449 err = ih264e_mv_buf_mgr_add_bufs(ps_codec);
2450 if (err != IH264E_SUCCESS)
2451 return err;
2452
2453 /* initialize ref bank buffer manager */
2454 err = ih264e_pic_buf_mgr_add_bufs(ps_codec);
2455 if (err != IH264E_SUCCESS)
2456 return err;
2457
2458 /* since dimension changed, start new sequence by forcing IDR */
2459 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2460
2461 /* in case dimension changes, we need to reinitialize RC as the
2462 * old model shall not fit further */
2463 u4_init_rc = 1;
2464
2465 /* when the dimension changes, the header needs to be regenerated */
2466 ps_codec->i4_gen_header = 1;
2467 }
2468 }
2469 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE)
2470 {
2471 /* temp var */
2472 UWORD32 u4_src_ticks, u4_tgt_ticks;
2473
2474 u4_src_ticks = ih264e_frame_time_get_src_ticks(
2475 ps_codec->s_rate_control.pps_frame_time);
2476
2477 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks(
2478 ps_codec->s_rate_control.pps_frame_time);
2479
2480 /* Change frame rate */
2481 if (ps_codec->s_cfg.u4_src_frame_rate
2482 != ps_cfg->u4_src_frame_rate * 1000)
2483 {
2484 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate
2485 * 1000;
2486
2487 ih264e_frame_time_update_src_frame_rate(
2488 ps_codec->s_rate_control.pps_frame_time,
2489 ps_codec->s_cfg.u4_src_frame_rate);
2490
2491 ih264_time_stamp_update_frame_rate(
2492 ps_codec->s_rate_control.pps_time_stamp,
2493 ps_codec->s_cfg.u4_src_frame_rate);
2494
2495 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2496 ps_codec->s_cfg.u4_src_frame_rate,
2497 u4_src_ticks, u4_tgt_ticks);
2498 }
2499
2500 if (ps_codec->s_cfg.u4_tgt_frame_rate
2501 != ps_cfg->u4_tgt_frame_rate * 1000)
2502 {
2503 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate
2504 * 1000;
2505
2506 ih264e_frame_time_update_tgt_frame_rate(
2507 ps_codec->s_rate_control.pps_frame_time,
2508 ps_codec->s_cfg.u4_tgt_frame_rate);
2509
2510 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2511 ps_codec->s_cfg.u4_src_frame_rate,
2512 u4_src_ticks, u4_tgt_ticks);
2513
2514 irc_change_frm_rate_for_bit_alloc(
2515 ps_codec->s_rate_control.pps_rate_control_api,
2516 ps_codec->s_cfg.u4_tgt_frame_rate);
2517 }
2518
2519 }
2520 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE)
2521 {
2522 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate)
2523 {
2524 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode)
2525 irc_change_avg_bit_rate(
2526 ps_codec->s_rate_control.pps_rate_control_api,
2527 ps_cfg->u4_target_bitrate);
2528
2529 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate;
2530 }
2531 }
2532 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE)
2533 {
2534 switch (ps_cfg->e_frame_type)
2535 {
2536 case IV_I_FRAME:
2537 ps_codec->force_curr_frame_type = IV_I_FRAME;
2538 break;
2539
2540 case IV_IDR_FRAME:
2541 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2542 break;
2543
2544 case IV_P_FRAME:
2545 default:
2546 break;
2547 }
2548 }
2549 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS)
2550 {
2551 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2552 {
2553 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel;
2554 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2555 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset;
2556 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel;
2557 }
2558 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2559 {
2560 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2561 }
2562 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x;
2563 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y;
2564
2565 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref)
2566 {
2567 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref;
2568 ps_codec->u4_is_curr_frm_ref = 1;
2569 }
2570 }
2571 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS)
2572 {
2573 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset;
2574 ps_curr_cfg->u4_constrained_intra_pred = ps_cfg->u4_constrained_intra_pred;
2575 if (ps_curr_cfg->u4_enc_speed_preset == IVE_SLOWEST)
2576 {/* high quality */
2577 /* enable diamond search */
2578 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2579 ps_curr_cfg->u4_enable_fast_sad = 0;
2580
2581 /* disable intra 4x4 */
2582 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2583 ps_codec->luma_energy_compaction[1] =
2584 ih264e_code_luma_intra_macroblock_4x4_rdopt_on;
2585
2586 /* sub pel off */
2587 ps_curr_cfg->u4_enable_hpel = 1;
2588
2589 /* deblocking off */
2590 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2591
2592 /* disabled intra inter gating in Inter slices */
2593 ps_codec->u4_inter_gate = 0;
2594 }
2595 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_NORMAL)
2596 {/* normal */
2597 /* enable diamond search */
2598 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2599 ps_curr_cfg->u4_enable_fast_sad = 0;
2600
2601 /* disable intra 4x4 */
2602 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2603
2604 /* sub pel off */
2605 ps_curr_cfg->u4_enable_hpel = 1;
2606
2607 /* deblocking off */
2608 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2609
2610 /* disabled intra inter gating in Inter slices */
2611 ps_codec->u4_inter_gate = 0;
2612 }
2613 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FAST)
2614 {/* normal */
2615 /* enable diamond search */
2616 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2617 ps_curr_cfg->u4_enable_fast_sad = 0;
2618
2619 /* disable intra 4x4 */
2620 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2621
2622 /* sub pel off */
2623 ps_curr_cfg->u4_enable_hpel = 1;
2624
2625 /* deblocking off */
2626 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2627
2628 /* disabled intra inter gating in Inter slices */
2629 ps_codec->u4_inter_gate = 1;
2630 }
2631 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_HIGH_SPEED)
2632 {/* fast */
2633 /* enable diamond search */
2634 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2635 ps_curr_cfg->u4_enable_fast_sad = 0;
2636
2637 /* disable intra 4x4 */
2638 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2639
2640 /* sub pel off */
2641 ps_curr_cfg->u4_enable_hpel = 0;
2642
2643 /* deblocking off */
2644 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2645
2646 /* disabled intra inter gating in Inter slices */
2647 ps_codec->u4_inter_gate = 0;
2648 }
2649 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2650 {/* fastest */
2651 /* enable diamond search */
2652 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2653 //u4_num_layers = 4;
2654
2655 /* disable intra 4x4 */
2656 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2657
2658 /* sub pel off */
2659 ps_curr_cfg->u4_enable_hpel = 0;
2660
2661 /* deblocking off */
2662 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2663
2664 /* disabled intra inter gating in Inter slices */
2665 ps_codec->u4_inter_gate = 1;
2666 }
2667 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2668 {
2669 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4;
2670 }
2671 }
2672 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS)
2673 {
2674 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval)
2675 {
2676 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval;
2677
2678 /* reset air counter */
2679 ps_codec->i4_air_pic_cnt = -1;
2680
2681 /* re-init air map */
2682 ih264e_init_air_map(ps_codec);
2683
2684 /*Effect intra frame interval change*/
2685
2686 irc_change_intra_frm_int_call(
2687 ps_codec->s_rate_control.pps_rate_control_api,
2688 ps_curr_cfg->u4_i_frm_interval);
2689 }
2690
2691 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval;
2692
2693 }
2694 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS)
2695 {
2696 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2697 {
2698 ps_curr_cfg->u4_disable_deblock_level =
2699 ps_cfg->u4_disable_deblock_level;
2700 }
2701 }
2702 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP)
2703 {
2704 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2705 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2706
2707 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max;
2708 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min;
2709 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp;
2710
2711 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max;
2712 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min;
2713 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp;
2714
2715 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max;
2716 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min;
2717 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp;
2718
2719 /* update rc lib with modified qp */
2720 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2721 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2722 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2723
2724 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api,
2725 au1_init_qp);
2726
2727 au1_min_max_qp[2 * I_PIC] =
2728 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2729 au1_min_max_qp[2 * I_PIC + 1] =
2730 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2731
2732 au1_min_max_qp[2 * P_PIC] =
2733 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2734 au1_min_max_qp[2 * P_PIC + 1] =
2735 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2736
2737 au1_min_max_qp[2 * B_PIC] =
2738 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2739 au1_min_max_qp[2 * B_PIC + 1] =
2740 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2741
2742 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api,
2743 au1_min_max_qp);
2744 }
2745 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE)
2746 {
2747 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode;
2748
2749 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER)
2750 {
2751 ps_codec->i4_header_mode = 1;
2752 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE;
2753 }
2754 else
2755 {
2756 ps_codec->i4_header_mode = 0;
2757 }
2758 }
2759 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS
2760 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode)
2761 {
2762 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size;
2763 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay;
2764
2765 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay);
2766
2767 // TODO: remove this when the support for changing buffer dynamically
2768 // is yet to be added.
2769 u4_init_rc = 1;
2770 }
2771 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS)
2772 {
2773 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode
2774 || ps_curr_cfg->u4_air_refresh_period
2775 != ps_cfg->u4_air_refresh_period)
2776 {
2777 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode;
2778 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period;
2779
2780 ih264e_init_air_map(ps_codec);
2781
2782 /* reset air counter */
2783 ps_codec->i4_air_pic_cnt = -1;
2784 }
2785 }
2786 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS)
2787 {
2788 ps_codec->s_cfg.e_profile = ps_cfg->e_profile;
2789 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode;
2790 }
2791 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES)
2792 {
2793 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores;
2794 }
2795 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VUI_PARAMS)
2796 {
2797 ps_codec->s_cfg.s_vui = ps_cfg->s_vui;
2798 }
2799
2800 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_MDCV_PARAMS)
2801 {
2802 ps_codec->s_cfg.s_sei.u1_sei_mdcv_params_present_flag =
2803 ps_cfg->s_sei.u1_sei_mdcv_params_present_flag;
2804 ps_codec->s_cfg.s_sei.s_sei_mdcv_params = ps_cfg->s_sei.s_sei_mdcv_params;
2805 }
2806 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CLL_PARAMS)
2807 {
2808 ps_codec->s_cfg.s_sei.u1_sei_cll_params_present_flag =
2809 ps_cfg->s_sei.u1_sei_cll_params_present_flag;
2810 ps_codec->s_cfg.s_sei.s_sei_cll_params = ps_cfg->s_sei.s_sei_cll_params;
2811 }
2812 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_AVE_PARAMS)
2813 {
2814 ps_codec->s_cfg.s_sei.u1_sei_ave_params_present_flag =
2815 ps_cfg->s_sei.u1_sei_ave_params_present_flag;
2816 ps_codec->s_cfg.s_sei.s_sei_ave_params = ps_cfg->s_sei.s_sei_ave_params;
2817 }
2818 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CCV_PARAMS)
2819 {
2820 ps_codec->s_cfg.s_sei.u1_sei_ccv_params_present_flag =
2821 ps_cfg->s_sei.u1_sei_ccv_params_present_flag;
2822 ps_codec->s_cfg.s_sei.s_sei_ccv_params = ps_cfg->s_sei.s_sei_ccv_params;
2823 }
2824 else if(ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_SII_PARAMS)
2825 {
2826 ps_codec->s_cfg.s_sei.u1_sei_sii_params_present_flag =
2827 ps_cfg->s_sei.u1_sei_sii_params_present_flag;
2828 ps_codec->s_cfg.s_sei.s_sei_sii_params = ps_cfg->s_sei.s_sei_sii_params;
2829 }
2830
2831 /* reset RC model */
2832 if (u4_init_rc)
2833 {
2834 /* init qp */
2835 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2836
2837 /* min max qp */
2838 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2839
2840 /* init i,p,b qp */
2841 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2842 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2843 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2844
2845 /* init min max qp */
2846 au1_min_max_qp[2 * I_PIC] =
2847 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2848 au1_min_max_qp[2 * I_PIC + 1] =
2849 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2850
2851 au1_min_max_qp[2 * P_PIC] =
2852 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2853 au1_min_max_qp[2 * P_PIC + 1] =
2854 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2855
2856 au1_min_max_qp[2 * B_PIC] =
2857 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2858 au1_min_max_qp[2 * B_PIC + 1] =
2859 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2860
2861 /* get rc mode */
2862 switch (ps_codec->s_cfg.e_rc_mode)
2863 {
2864 case IVE_RC_STORAGE:
2865 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE;
2866 break;
2867
2868 case IVE_RC_CBR_NON_LOW_DELAY:
2869 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC;
2870 break;
2871
2872 case IVE_RC_CBR_LOW_DELAY:
2873 ps_codec->s_rate_control.e_rc_type = CBR_LDRC;
2874 break;
2875
2876 case IVE_RC_NONE:
2877 ps_codec->s_rate_control.e_rc_type = CONST_QP;
2878 break;
2879
2880 default:
2881 break;
2882 }
2883
2884 /* init rate control */
2885 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api,
2886 ps_codec->s_rate_control.pps_frame_time,
2887 ps_codec->s_rate_control.pps_time_stamp,
2888 ps_codec->s_rate_control.pps_pd_frm_rate,
2889 ps_codec->s_cfg.u4_max_framerate,
2890 ps_codec->s_cfg.u4_src_frame_rate,
2891 ps_codec->s_cfg.u4_tgt_frame_rate,
2892 ps_codec->s_rate_control.e_rc_type,
2893 ps_codec->s_cfg.u4_target_bitrate,
2894 ps_codec->s_cfg.u4_max_bitrate,
2895 ps_codec->s_cfg.u4_vbv_buffer_delay,
2896 ps_codec->s_cfg.u4_i_frm_interval,
2897 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp,
2898 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp,
2899 ps_codec->s_cfg.u4_max_level);
2900 }
2901
2902 return err;
2903 }
2904
2905 /**
2906 *******************************************************************************
2907 *
2908 * @brief
2909 * Sets default encoder config parameters
2910 *
2911 * @par Description:
2912 * Sets default dynamic parameters. Will be called in ih264e_init() to ensure
2913 * that even if set_params is not called, codec continues to work
2914 *
2915 * @param[in] ps_cfg
2916 * Pointer to encoder config params
2917 *
2918 * @returns error status
2919 *
2920 * @remarks none
2921 *
2922 *******************************************************************************
2923 */
ih264e_set_default_params(cfg_params_t * ps_cfg)2924 static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg)
2925 {
2926 WORD32 ret = IV_SUCCESS;
2927
2928 ps_cfg->u4_max_wd = MAX_WD;
2929 ps_cfg->u4_max_ht = MAX_HT;
2930 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
2931 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
2932 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
2933 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
2934 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
2935 ps_cfg->u4_enable_quality_metrics = DEFAULT_QUALITY_METRICS_ENABLE;
2936 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
2937 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
2938 ps_cfg->e_rc_mode = DEFAULT_RC;
2939 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
2940 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE;
2941 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
2942 ps_cfg->e_content_type = IV_PROGRESSIVE;
2943 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
2944 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
2945 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
2946 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
2947 ps_cfg->e_arch = ih264e_default_arch();
2948 ps_cfg->e_soc = SOC_GENERIC;
2949 ps_cfg->u4_disp_wd = MAX_WD;
2950 ps_cfg->u4_disp_ht = MAX_HT;
2951 ps_cfg->u4_wd = MAX_WD;
2952 ps_cfg->u4_ht = MAX_HT;
2953 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
2954 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
2955 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE;
2956 ps_cfg->e_frame_type = IV_NA_FRAME;
2957 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
2958 ps_cfg->u4_i_qp = DEFAULT_I_QP;
2959 ps_cfg->u4_p_qp = DEFAULT_P_QP;
2960 ps_cfg->u4_b_qp = DEFAULT_B_QP;
2961 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN;
2962 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX;
2963 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN;
2964 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX;
2965 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN;
2966 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX;
2967 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
2968 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
2969 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY;
2970 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE;
2971 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
2972 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
2973 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
2974 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
2975 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
2976 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2977 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2978 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2979 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2980 ps_cfg->i4_min_sad =
2981 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ?
2982 DEFAULT_MIN_SAD_ENABLE :
2983 DEFAULT_MIN_SAD_DISABLE;
2984 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2985 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2986 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2987 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
2988 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2989 ps_cfg->e_profile = DEFAULT_PROFILE;
2990 ps_cfg->u4_timestamp_low = 0;
2991 ps_cfg->u4_timestamp_high = 0;
2992 ps_cfg->u4_is_valid = 1;
2993 ps_cfg->e_cmd = IVE_CMD_CT_NA;
2994 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2995 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2996 ps_cfg->u4_entropy_coding_mode = CAVLC;
2997 ps_cfg->u4_weighted_prediction = 0;
2998 ps_cfg->u4_constrained_intra_pred = 0;
2999 ps_cfg->u4_pic_info_type = 0;
3000 ps_cfg->u4_mb_info_type = 0;
3001 ps_cfg->s_vui.u1_video_signal_type_present_flag = 0;
3002 ps_cfg->s_vui.u1_colour_description_present_flag = 0;
3003
3004 return ret;
3005 }
3006
3007 /**
3008 *******************************************************************************
3009 *
3010 * @brief
3011 * Initialize encoder context. This will be called by init_mem_rec and during
3012 * codec reset
3013 *
3014 * @par Description:
3015 * Initializes the context
3016 *
3017 * @param[in] ps_codec
3018 * Codec context pointer
3019 *
3020 * @returns error status
3021 *
3022 * @remarks none
3023 *
3024 *******************************************************************************
3025 */
ih264e_init(codec_t * ps_codec)3026 static WORD32 ih264e_init(codec_t *ps_codec)
3027 {
3028 /* enc config param set */
3029 cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
3030
3031 /* temp var */
3032 WORD32 i;
3033
3034 /* coded pic count */
3035 ps_codec->i4_poc = 0;
3036
3037 /* Number of API calls to encode are made */
3038 ps_codec->i4_encode_api_call_cnt = -1;
3039
3040 /* Indicates no header has been generated yet */
3041 ps_codec->u4_header_generated = 0;
3042
3043 /* Number of pictures encoded */
3044 ps_codec->i4_pic_cnt = -1;
3045
3046 /* Number of threads created */
3047 ps_codec->i4_proc_thread_cnt = 0;
3048
3049 /* ctl mutex init */
3050 ithread_mutex_init(ps_codec->pv_ctl_mutex);
3051
3052 /* Set encoder chroma format */
3053 ps_codec->e_codec_color_format =
3054 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ?
3055 IV_YUV_420SP_VU : IV_YUV_420SP_UV;
3056
3057 /* Number of continuous frames where deblocking was disabled */
3058 ps_codec->i4_disable_deblk_pic_cnt = 0;
3059
3060 /* frame num */
3061 ps_codec->i4_frame_num = 0;
3062
3063 /* set the current frame type to I frame, since we are going to start encoding*/
3064 ps_codec->force_curr_frame_type = IV_NA_FRAME;
3065
3066 /* idr_pic_id */
3067 ps_codec->i4_idr_pic_id = -1;
3068
3069 /* Flush mode */
3070 ps_codec->i4_flush_mode = 0;
3071
3072 /* Encode header mode */
3073 ps_codec->i4_header_mode = 0;
3074
3075 /* Encode generate header */
3076 ps_codec->i4_gen_header = 0;
3077
3078 /* To signal successful completion of init */
3079 ps_codec->i4_init_done = 1;
3080
3081 /* To signal that at least one picture was decoded */
3082 ps_codec->i4_first_pic_done = 0;
3083
3084 /* Reset Codec */
3085 ps_codec->i4_reset_flag = 0;
3086
3087 /* Current error code */
3088 ps_codec->i4_error_code = IH264E_SUCCESS;
3089
3090 /* threshold residue */
3091 ps_codec->u4_thres_resi = 1;
3092
3093 /* inter gating enable */
3094 ps_codec->u4_inter_gate = 0;
3095
3096 /* entropy mutex init */
3097 ithread_mutex_init(ps_codec->pv_entropy_mutex);
3098
3099 /* sps id */
3100 ps_codec->i4_sps_id = 0;
3101
3102 /* sps id */
3103 ps_codec->i4_pps_id = 0;
3104
3105 /* Process thread created status */
3106 memset(ps_codec->ai4_process_thread_created, 0, MAX_PROCESS_THREADS);
3107
3108 memset(&ps_codec->s_global_quality_stats, 0, sizeof(ps_codec->s_global_quality_stats));
3109
3110 /* Number of MBs processed together */
3111 ps_codec->i4_proc_nmb = 8;
3112
3113 /* Previous POC msb */
3114 ps_codec->i4_prev_poc_msb = 0;
3115
3116 /* Previous POC lsb */
3117 ps_codec->i4_prev_poc_lsb = -1;
3118
3119 /* max Previous POC lsb */
3120 ps_codec->i4_max_prev_poc_lsb = -1;
3121
3122 /* sps, pps status */
3123 {
3124 sps_t *ps_sps = ps_codec->ps_sps_base;
3125 pps_t *ps_pps = ps_codec->ps_pps_base;
3126
3127 for (i = 0; i < MAX_SPS_CNT; i++)
3128 {
3129 ps_sps->i1_sps_valid = 0;
3130 ps_sps++;
3131 }
3132
3133 for (i = 0; i < MAX_PPS_CNT; i++)
3134 {
3135 ps_pps->i1_pps_valid = 0;
3136 ps_pps++;
3137 }
3138 }
3139
3140 {
3141 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs;
3142
3143 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3144 WORD32 clz;
3145
3146 /* Use next power of two number of entries*/
3147 clz = CLZ(num_jobs);
3148 num_jobs = 1 << (32 - clz);
3149
3150 /* init process jobq */
3151 ps_codec->pv_proc_jobq = ih264_list_init(
3152 ps_codec->pv_proc_jobq_buf,
3153 ps_codec->i4_proc_jobq_buf_size, num_jobs,
3154 sizeof(job_t), 10);
3155 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
3156 ih264_list_reset(ps_codec->pv_proc_jobq);
3157
3158 /* init entropy jobq */
3159 ps_codec->pv_entropy_jobq = ih264_list_init(
3160 ps_codec->pv_entropy_jobq_buf,
3161 ps_codec->i4_entropy_jobq_buf_size, num_jobs,
3162 sizeof(job_t), 10);
3163 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
3164 ih264_list_reset(ps_codec->pv_entropy_jobq);
3165 }
3166
3167 /* Update the jobq context to all the threads */
3168 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3169 {
3170 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
3171 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
3172
3173 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
3174 ps_codec->as_process[i].i4_id =
3175 (i >= MAX_PROCESS_THREADS) ?
3176 (i - MAX_PROCESS_THREADS) : i;
3177 ps_codec->as_process[i].ps_codec = ps_codec;
3178
3179 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
3180 ps_codec->as_process[i].s_entropy.pv_entropy_jobq =
3181 ps_codec->pv_entropy_jobq;
3182 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
3183 }
3184
3185 /* Initialize MV Bank buffer manager */
3186 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base);
3187
3188 /* Initialize Picture buffer manager for reference buffers*/
3189 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(
3190 ps_codec->pv_ref_buf_mgr_base);
3191
3192 /* Initialize Picture buffer manager for input buffers*/
3193 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(
3194 ps_codec->pv_inp_buf_mgr_base);
3195
3196 /* Initialize buffer manager for output buffers*/
3197 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(
3198 ps_codec->pv_out_buf_mgr_base);
3199
3200 /* buffer cnt in buffer manager */
3201 ps_codec->i4_inp_buf_cnt = 0;
3202 ps_codec->i4_out_buf_cnt = 0;
3203 ps_codec->i4_ref_buf_cnt = 0;
3204
3205 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base;
3206 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
3207
3208 /* Initialize dpb manager */
3209 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr);
3210
3211 memset(ps_codec->as_ref_set, 0,
3212 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS));
3213 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++)
3214 {
3215 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
3216 }
3217
3218 /* fn ptr init */
3219 ih264e_init_function_ptr(ps_codec);
3220
3221 /* reset status flags */
3222 for (i = 0; i < MAX_CTXT_SETS; i++)
3223 {
3224 ps_codec->au4_entropy_thread_active[i] = 0;
3225 ps_codec->ai4_pic_cnt[i] = -1;
3226
3227 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
3228 ps_codec->s_rate_control.post_encode_skip[i] = 0;
3229 }
3230
3231 ps_codec->s_rate_control.num_intra_in_prev_frame = 0;
3232 ps_codec->s_rate_control.i4_avg_activity = 0;
3233
3234 return IV_SUCCESS;
3235 }
3236
3237 /**
3238 *******************************************************************************
3239 *
3240 * @brief
3241 * Gets number of memory records required by the codec
3242 *
3243 * @par Description:
3244 * Gets codec memory requirements
3245 *
3246 * @param[in] pv_api_ip
3247 * Pointer to input argument structure
3248 *
3249 * @param[out] pv_api_op
3250 * Pointer to output argument structure
3251 *
3252 * @returns status
3253 *
3254 * @remarks
3255 *
3256 *******************************************************************************
3257 */
ih264e_get_num_rec(void * pv_api_ip,void * pv_api_op)3258 static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op)
3259 {
3260 /* api call I/O structures */
3261 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
3262
3263 UNUSED(pv_api_ip);
3264
3265 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3266
3267 return IV_SUCCESS;
3268 }
3269
3270 /**
3271 *******************************************************************************
3272 *
3273 * @brief
3274 * Fills memory records of the codec
3275 *
3276 * @par Description:
3277 * Fills codec memory requirements
3278 *
3279 * @param[in] pv_api_ip
3280 * Pointer to input argument structure
3281 *
3282 * @param[out] pv_api_op
3283 * Pointer to output argument structure
3284 *
3285 * @returns error status
3286 *
3287 * @remarks none
3288 *
3289 *******************************************************************************
3290 */
ih264e_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)3291 static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
3292 {
3293 /* api call I/O structures */
3294 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
3295 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
3296
3297 /* profile / level info */
3298 WORD32 level;
3299 WORD32 num_reorder_frames;
3300 WORD32 num_ref_frames;
3301
3302 /* mem records */
3303 WORD32 no_of_mem_rec;
3304 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3305
3306 /* frame dimensions */
3307 WORD32 max_wd_luma, max_ht_luma;
3308 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3309
3310 /* temp var */
3311 WORD32 i;
3312
3313 /* error status */
3314 IV_STATUS_T status = IV_SUCCESS;
3315
3316 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3317 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
3318
3319 /* mem records */
3320 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3321 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
3322
3323 /* frame dimensions */
3324 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht;
3325 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd;
3326 max_ht_luma = ALIGN16(max_ht_luma);
3327 max_wd_luma = ALIGN16(max_wd_luma);
3328 max_mb_rows = max_ht_luma / MB_SIZE;
3329 max_mb_cols = max_wd_luma / MB_SIZE;
3330 max_mb_cnt = max_mb_rows * max_mb_cols;
3331
3332 /* profile / level info */
3333 level = ih264e_get_min_level(max_ht_luma, max_wd_luma);
3334
3335 /* validate params */
3336 if ((level < MIN_LEVEL) || (level > MAX_LEVEL))
3337 {
3338 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3339 level = MAX_LEVEL;
3340 }
3341
3342 if (num_ref_frames > MAX_REF_CNT)
3343 {
3344 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3345 num_ref_frames = MAX_REF_CNT;
3346 }
3347
3348 if (num_reorder_frames > MAX_REF_CNT)
3349 {
3350 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3351 num_reorder_frames = MAX_REF_CNT;
3352 }
3353
3354 /* Set all memory records as persistent and alignment as 128 by default */
3355 ps_mem_rec = ps_mem_rec_base;
3356 for (i = 0; i < no_of_mem_rec; i++)
3357 {
3358 ps_mem_rec->u4_mem_alignment = 128;
3359 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
3360 ps_mem_rec++;
3361 }
3362
3363 /************************************************************************
3364 * Request memory for h264 encoder handle *
3365 ***********************************************************************/
3366 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
3367 {
3368 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
3369 }
3370 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
3371
3372 /************************************************************************
3373 * Request memory for h264 encoder context *
3374 ***********************************************************************/
3375 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
3376 {
3377 ps_mem_rec->u4_mem_size = sizeof(codec_t);
3378 }
3379 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
3380
3381 /************************************************************************
3382 * Request memory for CABAC context *
3383 ***********************************************************************/
3384 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
3385 {
3386 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t);
3387 }
3388 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
3389
3390 /************************************************************************
3391 * Request memory for CABAC MB info *
3392 ***********************************************************************/
3393 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
3394 {
3395 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1)
3396 * sizeof(mb_info_ctxt_t);
3397 }
3398 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
3399
3400
3401 /************************************************************************
3402 * Request memory for entropy context *
3403 * In multi core encoding, each row is assumed to be launched on a *
3404 * thread. The rows below can only start after its neighbors are coded *
3405 * The status of an mb coded/uncoded is signaled via entropy map. *
3406 * 1. One word32 to store skip run cnt *
3407 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
3408 * of the entropy map is max mb cols. Further allocate one *
3409 * more additional row to evade checking for row -1. *
3410 * 3. size of bit stream buffer to store bit stream ctxt. *
3411 * 4. Entropy coding is dependent on nnz coefficient count for *
3412 * the neighbor blocks. It is sufficient to maintain one row *
3413 * worth of nnz as entropy for lower row waits on entropy map*
3414 ************************************************************************/
3415 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
3416 {
3417 /* total size of the mem record */
3418 WORD32 total_size = 0;
3419
3420 /* size of skip mb run */
3421 total_size += sizeof(WORD32);
3422 total_size = ALIGN8(total_size);
3423
3424 /* size in bytes to store entropy status of an entire frame */
3425 total_size += (max_mb_cols * max_mb_rows);
3426 /* add an additional 1 row of bytes to evade the special case of row 0 */
3427 total_size += max_mb_cols;
3428 total_size = ALIGN128(total_size);
3429
3430 /* size of bit stream buffer */
3431 total_size += sizeof(bitstrm_t);
3432 total_size = ALIGN128(total_size);
3433
3434 /* top nnz luma */
3435 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3436 total_size = ALIGN128(total_size);
3437
3438 /* top nnz cbcr */
3439 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3440 total_size = ALIGN128(total_size);
3441
3442 /* total size per each proc ctxt */
3443 total_size *= MAX_CTXT_SETS;
3444
3445 ps_mem_rec->u4_mem_size = total_size;
3446 }
3447 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
3448
3449 /************************************************************************
3450 * The residue coefficients that needs to be entropy coded are packed *
3451 * at a buffer space by the proc threads. The entropy thread shall *
3452 * read from the buffer space, unpack them and encode the same. The *
3453 * buffer space required to pack a row of mbs are as follows. *
3454 * Assuming transform_8x8_flag is disabled, *
3455 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
3456 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
3457 * by 8 ac 4x4 chroma sub blocks. *
3458 * For the sake of simplicity we assume that all sub blocks are of *
3459 * type 4x4. The packing of each 4x4 is depicted by the structure *
3460 * tu_sblk_coeff_data_t *
3461 ************************************************************************/
3462 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
3463 {
3464 /* temp var */
3465 WORD32 size = 0;
3466
3467 /* size of coeff data of 1 mb */
3468 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3469
3470 /* size of coeff data of 1 row of mb's */
3471 size *= max_mb_cols;
3472
3473 /* align to avoid any false sharing across threads */
3474 size = ALIGN64(size);
3475
3476 /* size for one full frame */
3477 size *= max_mb_rows;
3478
3479 /* size of each proc buffer set (ping, pong) */
3480 size *= MAX_CTXT_SETS;
3481
3482 ps_mem_rec->u4_mem_size = size;
3483 }
3484 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
3485
3486 /************************************************************************
3487 * while encoding an mb, the mb header data is signaled to the entropy*
3488 * thread by writing to a buffer space. the size of header data per mb *
3489 * is assumed to be 40 bytes *
3490 * TODO: revisit this inference *
3491 ************************************************************************/
3492 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
3493 {
3494 /* temp var */
3495 WORD32 size;
3496
3497 /* size per MB */
3498 size = 40;
3499
3500 /* size for 1 row of mbs */
3501 size = size * max_mb_cols;
3502
3503 /* align to avoid any false sharing across threads */
3504 size = ALIGN64(size);
3505
3506 /* size for one full frame */
3507 size *= max_mb_rows;
3508
3509 /* size of each proc buffer set (ping, pong) */
3510 size *= MAX_CTXT_SETS;
3511
3512 ps_mem_rec->u4_mem_size = size;
3513 }
3514 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
3515
3516 /************************************************************************
3517 * Size for holding mv_buf_t for each MV Bank. *
3518 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3519 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3520 * max_dpb_size will be based on max_wd and max_ht *
3521 * For higher max_wd and max_ht this number will be smaller than *
3522 * MAX_DPB_SIZE But during actual initialization number of buffers *
3523 * allocated can be more. *
3524 * *
3525 * One extra MV Bank is needed to hold current pics MV bank. *
3526 * Since this is only a structure allocation and not actual buffer *
3527 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3528 ************************************************************************/
3529 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
3530 {
3531 /* max luma samples */
3532 WORD32 max_luma_samples = 0;
3533
3534 /* determine max luma samples */
3535 for (i = 0; i < 16; i++)
3536 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc)
3537 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs
3538 << (BLK_SIZE + BLK_SIZE);
3539
3540 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3541
3542 /************************************************************************
3543 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank *
3544 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3545 * is set to maximum number of luma samples allowed at the given level. *
3546 * This is done to ensure that any stream with width and height lesser *
3547 * than max_wd and max_ht is supported. Number of buffers required can *
3548 * be greater for lower width and heights at a given level and this *
3549 * increased number of buffers might require more memory than what *
3550 * max_wd and max_ht buffer would have required Also note one extra *
3551 * buffer is allocated to store current pictures MV bank. *
3552 ***********************************************************************/
3553
3554 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t);
3555
3556 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames
3557 + MAX_CTXT_SETS)
3558 * ih264e_get_pic_mv_bank_size(max_luma_samples);
3559 }
3560 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
3561
3562 /************************************************************************
3563 * While encoding inter slices, to compute the cost of encoding an mb *
3564 * with the mv's at hand, we employ the expression cost = sad + lambda *
3565 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
3566 * nt the mv in the stream. The mv bits for all the possible mv are *
3567 * stored in the look up table. The mem record for this look up table *
3568 * is given below. *
3569 ************************************************************************/
3570 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
3571 {
3572 /* max srch range x */
3573 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3574
3575 /* max srch range y */
3576 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3577
3578 /* max srch range */
3579 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3580
3581 /* due to subpel */
3582 u4_max_srch_range <<= 2;
3583
3584 /* due to mv on either direction */
3585 u4_max_srch_range = (u4_max_srch_range << 1);
3586
3587 /* due to pred mv + zero */
3588 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3589
3590 u4_max_srch_range = ALIGN128(u4_max_srch_range);
3591
3592 ps_mem_rec->u4_mem_size = u4_max_srch_range;
3593 }
3594 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
3595
3596 /************************************************************************
3597 * Request memory for SPS *
3598 ***********************************************************************/
3599 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3600 {
3601 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
3602 }
3603 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size);
3604
3605 /************************************************************************
3606 * Request memory for PPS *
3607 ***********************************************************************/
3608 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3609 {
3610 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
3611 }
3612 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size);
3613
3614 /************************************************************************
3615 * Request memory for Slice Header *
3616 ***********************************************************************/
3617 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3618 {
3619 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT
3620 * sizeof(slice_header_t);
3621 }
3622 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
3623
3624 /************************************************************************
3625 * Request memory for Adaptive Intra Refresh *
3626 ***********************************************************************/
3627 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3628 {
3629 /* total size of the mem record */
3630 WORD32 total_size = 0;
3631
3632 /* intra coded map */
3633 total_size += max_mb_cnt;
3634 total_size *= MAX_CTXT_SETS;
3635
3636 /* mb refresh map */
3637 total_size += sizeof(UWORD16) * max_mb_cnt;
3638
3639 /* alignment */
3640 total_size = ALIGN128(total_size);
3641
3642 ps_mem_rec->u4_mem_size = total_size;
3643 }
3644 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
3645
3646 /************************************************************************
3647 * In multi slice encoding, this memory record helps tracking the start*
3648 * of slice with reference to mb. *
3649 * MEM RECORD for holding *
3650 * 1. mb slice map *
3651 ************************************************************************/
3652 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3653 {
3654 /* total size of the mem record */
3655 WORD32 total_size = 0;
3656
3657 /* size in bytes to slice index of all mbs of a frame */
3658 total_size = ALIGN64(max_mb_cnt);
3659
3660 /* ih264e_update_proc_ctxt can overread by 1 at the end */
3661 total_size += 1;
3662
3663 /* total size per each proc ctxt */
3664 total_size *= MAX_CTXT_SETS;
3665 ps_mem_rec->u4_mem_size = total_size;
3666 }
3667 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
3668
3669 /************************************************************************
3670 * Request memory to hold thread handles for each processing thread *
3671 ************************************************************************/
3672 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3673 {
3674 WORD32 handle_size = ithread_get_handle_size();
3675
3676 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
3677 }
3678 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
3679
3680 /************************************************************************
3681 * Request memory to hold mutex for control calls *
3682 ************************************************************************/
3683 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3684 {
3685 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3686 }
3687 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
3688
3689 /************************************************************************
3690 * Request memory to hold mutex for entropy calls *
3691 ************************************************************************/
3692 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3693 {
3694 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3695 }
3696 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
3697
3698 /************************************************************************
3699 * Request memory to hold process jobs *
3700 ***********************************************************************/
3701 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3702 {
3703 /* One process job per row of MBs */
3704 /* Allocate for two pictures, so that wrap around can be handled easily */
3705 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3706
3707 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3708
3709 ps_mem_rec->u4_mem_size = job_queue_size;
3710 }
3711 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
3712
3713 /************************************************************************
3714 * Request memory to hold entropy jobs *
3715 ***********************************************************************/
3716 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3717 {
3718 /* One process job per row of MBs */
3719 /* Allocate for two pictures, so that wrap around can be handled easily */
3720 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3721
3722 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3723
3724 ps_mem_rec->u4_mem_size = job_queue_size;
3725 }
3726 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
3727
3728 /************************************************************************
3729 * In multi core encoding, each row is assumed to be launched on a *
3730 * thread. The rows below can only start after its neighbors are coded *
3731 * The status of an mb coded/uncoded is signaled via proc map. *
3732 * MEM RECORD for holding *
3733 * 1. mb proc map (mb status core coded/uncoded) *
3734 ************************************************************************/
3735 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3736 {
3737 /* total size of the mem record */
3738 WORD32 total_size = 0;
3739
3740 /* size in bytes to mb core coding status of an entire frame */
3741 total_size = max_mb_cnt;
3742
3743 /* add an additional 1 row of bytes to evade the special case of row 0 */
3744 total_size += max_mb_cols;
3745
3746 /* total size per each proc ctxt */
3747 total_size *= MAX_CTXT_SETS;
3748 ps_mem_rec->u4_mem_size = total_size;
3749 }
3750 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
3751
3752 /************************************************************************
3753 * mem record for holding a particular MB is deblocked or not *
3754 * 1. mb deblk map (mb status deblocked/not deblocked) *
3755 ************************************************************************/
3756 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3757 {
3758 /* total size of the mem record */
3759 WORD32 total_size = 0;
3760
3761 /* size in bytes to mb core coding status of an entire frame */
3762 total_size = max_mb_cnt;
3763
3764 /* add an additional 1 row of bytes to evade the special case of row 0 */
3765 total_size += max_mb_cols;
3766
3767 total_size = ALIGN64(total_size);
3768
3769 /* total size per each proc ctxt */
3770 total_size *= MAX_CTXT_SETS;
3771 ps_mem_rec->u4_mem_size = total_size;
3772 }
3773 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
3774
3775 /************************************************************************
3776 * mem record for holding a particular MB's me is done or not *
3777 * 1. mb me map *
3778 ************************************************************************/
3779 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
3780 {
3781 /* total size of the mem record */
3782 WORD32 total_size = 0;
3783
3784 /* size in bytes to mb core coding status of an entire frame */
3785 total_size = max_mb_cnt;
3786
3787 /* add an additional 1 row of bytes to evade the special case of row 0 */
3788 total_size += max_mb_cols;
3789
3790 /* total size per each proc ctxt */
3791 total_size *= MAX_CTXT_SETS;
3792
3793 ps_mem_rec->u4_mem_size = total_size;
3794 }
3795 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
3796
3797 /************************************************************************
3798 * size for holding dpb manager context *
3799 ************************************************************************/
3800 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
3801 {
3802 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
3803 }
3804 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
3805
3806 /************************************************************************
3807 * luma or chroma core coding involves mb estimation, error computation*
3808 * between the estimated singnal and the actual signal, transform the *
3809 * error, quantize the error, then inverse transform and inverse quant *
3810 * ize the residue and add the result back to estimated signal. *
3811 * To perform all these, a set of temporary buffers are needed. *
3812 * MEM RECORD for holding scratch buffers *
3813 * 1. prediction buffer used during mb mode analysis *
3814 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
3815 * enabled *
3816 * - when intra 4x4 is enabled, rdopt is on, to store the *
3817 * reconstructed values and use them later this temp. buffer *
3818 * is used. *
3819 * 3. prediction buffer used during intra mode analysis *
3820 * 4. prediction buffer used during intra 16x16 plane mode *
3821 * analysis
3822 * 5. prediction buffer used during intra chroma mode analysis *
3823 * 6. prediction buffer used during intra chroma 16x16 plane *
3824 * mode analysis
3825 * 7. forward transform output buffer *
3826 * - to store the error between estimated and the actual inp *
3827 * ut and to store the fwd transformed quantized output *
3828 * 8. forward transform output buffer *
3829 * - when intra 4x4 is enabled, rdopt is on, to store the *
3830 * fwd transform values and use them later this temp. buffer *
3831 * is used. *
3832 * 9. temporary buffer for inverse transform *
3833 * - temporary buffer used in inverse transform and inverse *
3834 * quantization *
3835 * A. Buffers for holding half_x , half_y and half_xy planes *
3836 ************************************************************************/
3837 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
3838 {
3839 WORD32 total_size = 0;
3840 WORD32 i4_tmp_size;
3841
3842 /* size to hold prediction buffer */
3843 total_size += sizeof(UWORD8) * 16 * 16;
3844 total_size = ALIGN64(total_size);
3845
3846 /* size to hold recon for intra 4x4 buffer */
3847 total_size += sizeof(UWORD8) * 16 * 16;
3848 total_size = ALIGN64(total_size);
3849
3850 /* prediction buffer intra 16x16 */
3851 total_size += sizeof(UWORD8) * 16 * 16;
3852 total_size = ALIGN64(total_size);
3853
3854 /* prediction buffer intra 16x16 plane*/
3855 total_size += sizeof(UWORD8) * 16 * 16;
3856 total_size = ALIGN64(total_size);
3857
3858 /* prediction buffer intra chroma*/
3859 total_size += sizeof(UWORD8) * 16 * 8;
3860 total_size = ALIGN64(total_size);
3861
3862 /* prediction buffer intra chroma plane*/
3863 total_size += sizeof(UWORD8) * 16 * 8;
3864 total_size = ALIGN64(total_size);
3865
3866 /* size to hold fwd transform output */
3867 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3868 total_size = ALIGN64(total_size);
3869
3870 /* size to hold fwd transform output */
3871 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3872 total_size = ALIGN64(total_size);
3873
3874 /* size to hold temporary data during inverse transform */
3875 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3876 total_size = ALIGN64(total_size);
3877
3878 /* Buffers for holding half_x , half_y and half_xy planes */
3879 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3880 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
3881
3882 /* Allocate for each process thread */
3883 total_size *= MAX_PROCESS_CTXT;
3884
3885 ps_mem_rec->u4_mem_size = total_size;
3886 }
3887 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
3888
3889 /************************************************************************
3890 * When transform_8x8_flag is disabled, the size of a sub block is *
3891 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
3892 * block is 8x8. The threshold matrix and the forward scaling list *
3893 * is of the size of the sub block. *
3894 * MEM RECORD for holding *
3895 * 1. quantization parameters for plane y, cb, cr *
3896 * - threshold matrix for quantization *
3897 * - forward weight matrix *
3898 * - satqd threshold matrix *
3899 ************************************************************************/
3900 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
3901 {
3902 /* total size of the mem record */
3903 WORD32 total_size = 0;
3904
3905 /* quantization parameter list for planes y,cb and cr */
3906 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
3907
3908 /* size of threshold matrix for quantization
3909 * (assuming the transform_8x8_flag is disabled).
3910 * for all 3 planes */
3911 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3912
3913 /* size of forward weight matrix for quantization
3914 * (assuming the transform_8x8_flag is disabled).
3915 * for all 3 planes */
3916 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3917
3918 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
3919 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
3920
3921 /* total size per each proc thread */
3922 total_size *= MAX_PROCESS_CTXT;
3923
3924 ps_mem_rec->u4_mem_size = total_size;
3925 }
3926 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
3927
3928 /************************************************************************
3929 * While computing blocking strength for the current mb, the csbp, mb *
3930 * type for the neighboring mbs are necessary. memtab for storing top *
3931 * row mbtype and csbp is evaluated here. *
3932 * *
3933 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
3934 * and sent. The estimation is dependent on neighbor mbs. For this *
3935 * store the top row sub mb types for intra mbs *
3936 * *
3937 * During motion vector prediction, the curr mb mv is predicted from *
3938 * neigbors left, top, top right and sometimes top left depending on *
3939 * the availability. The top and top right content is accessed from *
3940 * the memtab specified below. *
3941 ************************************************************************/
3942 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
3943 {
3944 /* total size of the mem record */
3945 WORD32 total_size = 0;
3946
3947 /* size in bytes to store 1 row of mb_info_t */
3948 /* one additional mb, to avoid checking end of row condition */
3949 total_size += (max_mb_cols + 1) * sizeof(mb_info_t);
3950
3951 /* size in bytes to store 1 row of intra macroblock sub modes */
3952 total_size += max_mb_cols * sizeof(UWORD8) * 16;
3953
3954 /* size in bytes to store 1 row + 1 of enc_pu_t */
3955 /* one additional mb, to avoid checking end of row condition */
3956 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t);
3957
3958 /* total size per proc ctxt */
3959 total_size = ALIGN128(total_size);
3960
3961 /* total size per each proc ctxt */
3962 total_size *= MAX_CTXT_SETS;
3963 ps_mem_rec->u4_mem_size = total_size;
3964 }
3965 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
3966
3967 /************************************************************************
3968 * When transform_8x8_flag is disabled, the mb is partitioned into *
3969 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3970 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3971 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3972 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3973 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3974 * edge and 3 horizontal inner edges per mb. *
3975 * MEM RECORD for holding *
3976 * 1. vertical edge blocking strength *
3977 * 2. horizontal edge blocking strength *
3978 * 3. mb qp *
3979 * all are frame level *
3980 ************************************************************************/
3981 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
3982 {
3983 /* total size of the mem record */
3984 WORD32 total_size = 0;
3985
3986 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
3987 WORD32 vert_bs_size, horz_bs_size, qp_size;
3988
3989 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
3990 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3991 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3992 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3993
3994 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
3995 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3996 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3997 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3998
3999 /* qp of each mb requires 1 byte */
4000 qp_size = ALIGN64(max_mb_cnt);
4001
4002 /* total size */
4003 total_size = vert_bs_size + horz_bs_size + qp_size;
4004
4005 /* total size per each proc ctxt */
4006 total_size *= MAX_CTXT_SETS;
4007
4008 ps_mem_rec->u4_mem_size = total_size;
4009 }
4010 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
4011
4012 /************************************************************************
4013 * size for holding dpb manager context *
4014 ************************************************************************/
4015 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4016 {
4017 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
4018 }
4019 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
4020
4021 /************************************************************************
4022 * size for holding dpb manager context *
4023 ************************************************************************/
4024 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4025 {
4026 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
4027 }
4028 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size);
4029
4030 /************************************************************************
4031 * Size for color space conversion *
4032 ************************************************************************/
4033 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4034 {
4035 /* We need a total a memory for a single frame of 420 sp, ie
4036 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
4037 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS
4038 * ((3 * max_ht_luma * max_wd_luma) >> 1);
4039 /* Allocate an extra row, since inverse transform functions for
4040 * chroma access(only read, not used) few extra bytes due to
4041 * interleaved input
4042 */
4043 ps_mem_rec->u4_mem_size += max_wd_luma;
4044 }
4045 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size);
4046
4047 /************************************************************************
4048 * Size for holding pic_buf_t for each reference picture *
4049 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
4050 * MAX_DPB_SIZE or max_dpb_size for following reasons *
4051 * max_dpb_size will be based on max_wd and max_ht *
4052 * For higher max_wd and max_ht this number will be smaller than *
4053 * MAX_DPB_SIZE But during actual initialization number of buffers *
4054 * allocated can be more. *
4055 * *
4056 * Also to handle display depth application can allocate more than *
4057 * what codec asks for in case of non-shared mode *
4058 * Since this is only a structure allocation and not actual buffer *
4059 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
4060 ************************************************************************/
4061 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4062 {
4063 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
4064 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
4065
4066 /************************************************************************
4067 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
4068 * is set to maximum number of luma samples allowed at the given level. *
4069 * This is done to ensure that any stream with width and height lesser *
4070 * than max_wd and max_ht is supported. Number of buffers required can *
4071 * be greater for lower width and heights at a given level and this *
4072 * increased number of buffers might require more memory than what *
4073 * max_wd and max_ht buffer would have required. Number of buffers is *
4074 * doubled in order to return one frame at a time instead of sending *
4075 * multiple outputs during dpb full case. Also note one extra buffer is *
4076 * allocted to store current picture. *
4077 * *
4078 * Half-pel planes for each reference buffer are allocated along with *
4079 * the reference buffer. So each reference buffer is 4 times the *
4080 * required size. This way buffer management for the half-pel planes is *
4081 * easier and while using the half-pel planes in MC, an offset can be *
4082 * used from a single pointer *
4083 ***********************************************************************/
4084 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT
4085 * ih264e_get_total_pic_buf_size(
4086 max_wd_luma * max_ht_luma, level,
4087 PAD_WD, PAD_HT, num_ref_frames,
4088 num_reorder_frames);
4089 }
4090 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
4091
4092 /************************************************************************
4093 * Request memory to hold mem recs to be returned during retrieve call *
4094 ************************************************************************/
4095 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
4096 {
4097 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
4098 }
4099 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
4100
4101 /************************************************************************
4102 * size for memory required by NMB info structs and buffer for storing *
4103 * half pel plane *
4104 ************************************************************************/
4105 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4106 {
4107 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols *
4108 (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE
4109 * sizeof(UWORD8));
4110 }
4111 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
4112
4113 /************************************************************************
4114 * RC mem records *
4115 ************************************************************************/
4116 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4117 {
4118 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
4119 }
4120 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size);
4121
4122 /* Each memtab size is aligned to next multiple of 128 bytes */
4123 /* This is to ensure all the memtabs start at different cache lines */
4124 ps_mem_rec = ps_mem_rec_base;
4125 for (i = 0; i < MEM_REC_CNT; i++)
4126 {
4127 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
4128 ps_mem_rec++;
4129 }
4130
4131 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
4132
4133 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
4134
4135 return (status);
4136 }
4137
4138 /**
4139 *******************************************************************************
4140 *
4141 * @brief
4142 * Initializes from mem records passed to the codec
4143 *
4144 * @par Description:
4145 * Initializes pointers based on mem records passed
4146 *
4147 * @param[in] ps_codec_obj
4148 * Pointer to codec object at API level
4149 *
4150 * @param[in] pv_api_ip
4151 * Pointer to input argument structure
4152 *
4153 * @param[out] pv_api_op
4154 * Pointer to output argument structure
4155 *
4156 * @returns error status
4157 *
4158 * @remarks none
4159 *
4160 *******************************************************************************
4161 */
ih264e_init_mem_rec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4162 static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj,
4163 void *pv_api_ip,
4164 void *pv_api_op)
4165 {
4166 /* api call I/O structures */
4167 ih264e_init_ip_t *ps_ip = pv_api_ip;
4168 ih264e_init_op_t *ps_op = pv_api_op;
4169
4170 /* mem records */
4171 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
4172
4173 /* codec variables */
4174 codec_t * ps_codec;
4175 cabac_ctxt_t *ps_cabac;
4176 mb_info_ctxt_t *ps_mb_map_ctxt_inc;
4177
4178 cfg_params_t *ps_cfg;
4179
4180 /* frame dimensions */
4181 WORD32 max_wd_luma, max_ht_luma;
4182 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
4183
4184 /* temp var */
4185 WORD32 i, j;
4186 WORD32 status = IV_SUCCESS;
4187
4188 /* frame dimensions */
4189 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4190 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4191 max_mb_rows = max_ht_luma / MB_SIZE;
4192 max_mb_cols = max_wd_luma / MB_SIZE;
4193 max_mb_cnt = max_mb_rows * max_mb_cols;
4194
4195 /* mem records */
4196 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
4197 /* memset all allocated memory, except the first one. First buffer (i.e. i == MEM_REC_IV_OBJ)
4198 is initialized by application before calling this init function */
4199 for (i = MEM_REC_CODEC; i < MEM_REC_CNT; i++)
4200 {
4201 ps_mem_rec = &ps_mem_rec_base[i];
4202 memset(ps_mem_rec->pv_base, 0, ps_mem_rec->u4_mem_size);
4203 }
4204
4205 /* Init mem records */
4206 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
4207 {
4208 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
4209 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
4210 }
4211 /* Init mem records_cabac ctxt */
4212 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
4213 {
4214 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base);
4215 }
4216
4217 /* Init mem records mb info array for CABAC */
4218 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
4219 {
4220 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base);
4221 }
4222
4223 /* Note this memset can not be done in init() call, since init will called
4224 during reset as well. And calling this during reset will mean all pointers
4225 need to reinitialized */
4226 memset(ps_codec, 0, sizeof(codec_t));
4227 memset(ps_cabac, 0, sizeof(cabac_ctxt_t));
4228
4229 /* Set default Config Params */
4230 ps_cfg = &ps_codec->s_cfg;
4231 ih264e_set_default_params(ps_cfg);
4232
4233 /* Update config params as per input */
4234 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4235 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4236
4237 /* Initialize dimensions to max dimensions during init */
4238 ps_cfg->u4_wd = ps_cfg->u4_disp_wd = ps_cfg->u4_max_wd;
4239 ps_cfg->u4_ht = ps_cfg->u4_disp_ht = ps_cfg->u4_max_ht;
4240
4241 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
4242 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
4243 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
4244 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
4245 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
4246 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
4247 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
4248 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
4249 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate;
4250 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
4251 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
4252 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4253 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4254 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
4255 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
4256 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
4257 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
4258 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
4259 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
4260
4261 /* Validate params */
4262 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL)
4263 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
4264 {
4265 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
4266 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
4267 }
4268
4269 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
4270 {
4271 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
4272 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
4273 }
4274
4275 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
4276 {
4277 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
4278 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
4279 }
4280
4281 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
4282 {
4283 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
4284
4285 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
4286 MEM_REC_CNT * sizeof(iv_mem_rec_t));
4287 }
4288
4289 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
4290 {
4291 /* temp var */
4292 WORD32 size = 0, offset;
4293
4294 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4295 {
4296 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4297 {
4298 /* base ptr */
4299 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4300
4301 /* reset size */
4302 size = 0;
4303
4304 /* skip mb run */
4305 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4306 (void *) (pu1_buf + size);
4307 size += sizeof(WORD32);
4308 size = ALIGN8(size);
4309
4310 /* entropy map */
4311 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4312 (void *) (pu1_buf + size + max_mb_cols);
4313 /* size in bytes to store entropy status of an entire frame */
4314 size += (max_mb_cols * max_mb_rows);
4315 /* add an additional 1 row of bytes to evade the special case of row 0 */
4316 size += max_mb_cols;
4317 size = ALIGN128(size);
4318
4319 /* bit stream ptr */
4320 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4321 + size);
4322 size += sizeof(bitstrm_t);
4323 size = ALIGN128(size);
4324
4325 /* nnz luma */
4326 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4327 (void *) (pu1_buf + size);
4328 size += (max_mb_cols * 4 * sizeof(UWORD8));
4329 size = ALIGN128(size);
4330
4331 /* nnz chroma */
4332 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4333 (void *) (pu1_buf + size);
4334 size += (max_mb_cols * 4 * sizeof(UWORD8));
4335 size = ALIGN128(size);
4336 offset = size;
4337 /* cabac Context */
4338 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4339 }
4340 else
4341 {
4342 /* base ptr */
4343 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4344
4345 /* reset size */
4346 size = offset;
4347
4348 /* skip mb run */
4349 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4350 (void *) (pu1_buf + size);
4351 size += sizeof(WORD32);
4352 size = ALIGN8(size);
4353
4354 /* entropy map */
4355 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4356 (void *) (pu1_buf + size + max_mb_cols);
4357 /* size in bytes to store entropy status of an entire frame */
4358 size += (max_mb_cols * max_mb_rows);
4359 /* add an additional 1 row of bytes to evade the special case of row 0 */
4360 size += max_mb_cols;
4361 size = ALIGN128(size);
4362
4363 /* bit stream ptr */
4364 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4365 + size);
4366 size += sizeof(bitstrm_t);
4367 size = ALIGN128(size);
4368
4369 /* nnz luma */
4370 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4371 (void *) (pu1_buf + size);
4372 size += (max_mb_cols * 4 * sizeof(UWORD8));
4373 size = ALIGN128(size);
4374
4375 /* nnz chroma */
4376 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4377 (void *) (pu1_buf + size);
4378 size += (max_mb_cols * 4 * sizeof(UWORD8));
4379 size = ALIGN128(size);
4380 /* cabac Context */
4381 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4382 }
4383 }
4384 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base =
4385 ps_mb_map_ctxt_inc;
4386 }
4387
4388 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
4389 {
4390 /* temp var */
4391 WORD32 size = 0, size_of_row;
4392 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4393
4394 /* size of coeff data of 1 mb */
4395 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
4396
4397 /* size of coeff data of 1 row of mb's */
4398 size *= max_mb_cols;
4399
4400 /* align to avoid false sharing */
4401 size = ALIGN64(size);
4402 size_of_row = size;
4403
4404 /* size for one full frame */
4405 size *= max_mb_rows;
4406
4407 ps_codec->u4_size_coeff_data = size_of_row;
4408
4409 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4410 {
4411 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4412 {
4413 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
4414 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data =
4415 pu1_buf;
4416 }
4417 else
4418 {
4419 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
4420 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf
4421 + size;
4422 }
4423 }
4424 }
4425
4426 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
4427 {
4428 /* temp var */
4429 WORD32 size, size_of_row;
4430 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4431
4432 /* size of header data of 1 mb */
4433 size = sizeof(mb_hdr_t);
4434
4435 /* size for 1 row of mbs */
4436 size = size * max_mb_cols;
4437
4438 /* align to avoid any false sharing across threads */
4439 size = ALIGN64(size);
4440 size_of_row = size;
4441
4442 /* size for one full frame */
4443 size *= max_mb_rows;
4444
4445 ps_codec->u4_size_header_data = size_of_row;
4446
4447 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4448 {
4449 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4450 {
4451 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
4452 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4453 pu1_buf;
4454 }
4455 else
4456 {
4457 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
4458 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4459 pu1_buf + size;
4460 }
4461 }
4462 }
4463
4464 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
4465 {
4466 /* size of buf mgr struct */
4467 WORD32 size = ih264_buf_mgr_size();
4468
4469 /* temp var */
4470 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4471
4472 /* mv buffer mgr */
4473 ps_codec->pv_mv_buf_mgr_base = pu1_buf;
4474
4475 /* mv bank */
4476 ps_codec->pv_mv_bank_buf_base = pu1_buf + size;
4477 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size;
4478 }
4479
4480 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
4481 {
4482 /* max srch range x */
4483 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4484
4485 /* max srch range y */
4486 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4487
4488 /* max srch range */
4489 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
4490
4491 /* temp var */
4492 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4493
4494 /* due to subpel */
4495 u4_max_srch_range <<= 2;
4496
4497 // /* due to mv on either direction */
4498 // u4_max_srch_range = (u4_max_srch_range << 1);
4499
4500 /* due to pred mv + zero */
4501 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
4502
4503 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4504 {
4505 /* me ctxt */
4506 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
4507
4508 /* init at zero mv */
4509 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
4510 }
4511 }
4512
4513 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
4514 {
4515 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
4516 }
4517
4518 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
4519 {
4520 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
4521 }
4522
4523 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
4524 {
4525 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
4526
4527 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4528 {
4529 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4530 {
4531 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
4532 }
4533 else
4534 {
4535 /* temp var */
4536 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
4537 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
4538
4539 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
4540 }
4541 }
4542 }
4543
4544 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
4545 {
4546 /* temp var */
4547 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4548
4549 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4550 {
4551 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4552 {
4553 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
4554 }
4555 else
4556 {
4557 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf
4558 + max_mb_cnt;
4559 }
4560 }
4561
4562 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
4563 }
4564
4565 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
4566 {
4567 /* pointer to storage space */
4568 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4569
4570 /* init pointer */
4571 pu1_buf_ping = ps_mem_rec->pv_base;
4572 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
4573
4574 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4575 {
4576 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4577 {
4578 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
4579 }
4580 else
4581 {
4582 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
4583 }
4584 }
4585 }
4586
4587 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
4588 {
4589 WORD32 handle_size = ithread_get_handle_size();
4590
4591 for (i = 0; i < MAX_PROCESS_THREADS; i++)
4592 {
4593 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base
4594 + (i * handle_size);
4595 }
4596 }
4597
4598 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
4599 {
4600 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
4601 }
4602
4603 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
4604 {
4605 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
4606 }
4607
4608 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
4609 {
4610 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
4611 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
4612 }
4613
4614 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
4615 {
4616 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
4617 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
4618 }
4619
4620 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
4621 {
4622 /* pointer to storage space */
4623 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4624
4625 /* total size of the mem record */
4626 WORD32 total_size = 0;
4627
4628 /* size in bytes to mb core coding status of an entire frame */
4629 total_size = max_mb_cnt;
4630
4631 /* add an additional 1 row of bytes to evade the special case of row 0 */
4632 total_size += max_mb_cols;
4633
4634 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4635 {
4636 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4637 {
4638 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
4639 }
4640 else
4641 {
4642 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size
4643 + max_mb_cols;
4644 }
4645 }
4646 }
4647
4648 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
4649 {
4650 /* pointer to storage space */
4651 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4652
4653 /* total size of the mem record */
4654 WORD32 total_size = 0;
4655
4656 /* size in bytes to mb core coding status of an entire frame */
4657 total_size = max_mb_cnt;
4658
4659 /* add an additional 1 row of bytes to evade the special case of row 0 */
4660 total_size += max_mb_cols;
4661
4662 /*Align the memory offsets*/
4663 total_size = ALIGN64(total_size);
4664
4665 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4666 {
4667 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4668 {
4669 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
4670
4671 }
4672 else
4673 {
4674 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size
4675 + max_mb_cols;
4676
4677 }
4678 }
4679 }
4680
4681 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
4682 {
4683 /* pointer to storage space */
4684 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4685
4686 /* total size of the mem record */
4687 WORD32 total_size = 0;
4688
4689 /* size in bytes to mb core coding status of an entire frame */
4690 total_size = max_mb_cnt;
4691
4692 /* add an additional 1 row of bytes to evade the special case of row 0 */
4693 total_size += max_mb_cols;
4694
4695 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4696 {
4697 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4698 {
4699 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
4700 }
4701 else
4702 {
4703 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size
4704 + max_mb_cols;
4705 }
4706 }
4707 }
4708
4709 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
4710 {
4711 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
4712 }
4713
4714 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
4715 {
4716 /* pointer to storage space */
4717 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4718
4719 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
4720 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
4721
4722 /* temp var */
4723 WORD32 size = 0;
4724
4725 /* size to hold intra/inter prediction buffer */
4726 size_pred_luma = sizeof(UWORD8) * 16 * 16;
4727 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
4728
4729 /* size to hold fwd transform output */
4730 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
4731
4732 /* size to hold temporary data during inverse transform */
4733 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
4734
4735 /* size to hold half pel plane buffers */
4736 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
4737
4738 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4739 {
4740 /* prediction buffer */
4741 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
4742 ps_codec->as_process[i].i4_pred_strd = 16;
4743 size += size_pred_luma;
4744 size = ALIGN64(size);
4745
4746 /* prediction buffer */
4747 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf
4748 + size);
4749 size += size_pred_luma;
4750 size = ALIGN64(size);
4751
4752 /* prediction buffer intra 16x16 */
4753 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf
4754 + size);
4755 size += size_pred_luma;
4756 size = ALIGN64(size);
4757
4758 /* prediction buffer intra 16x16 plane*/
4759 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane =
4760 (void *) (pu1_buf + size);
4761 size += size_pred_luma;
4762 size = ALIGN64(size);
4763
4764 /* prediction buffer intra chroma*/
4765 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf
4766 + size);
4767 size += size_pred_chroma;
4768 size = ALIGN64(size);
4769
4770 /* prediction buffer intra chroma plane*/
4771 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane =
4772 (void *) (pu1_buf + size);
4773 size += size_pred_chroma;
4774 size = ALIGN64(size);
4775
4776 /* Fwd transform output */
4777 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4778 ps_codec->as_process[i].i4_res_strd = 16;
4779 size += size_fwd;
4780 size = ALIGN64(size);
4781
4782 /* Fwd transform output */
4783 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf
4784 + size);
4785 size += size_fwd;
4786 size = ALIGN64(size);
4787
4788 /* scratch buffer used during inverse transform */
4789 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4790 size += size_inv;
4791 size = ALIGN64(size);
4792
4793 for (j = 0; j < SUBPEL_BUFF_CNT; j++)
4794 {
4795 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4796 size += ALIGN64(size_hp);
4797 }
4798 }
4799 }
4800
4801 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
4802 {
4803 /* pointer to storage space */
4804 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4805
4806 /* size of qp, threshold matrix, fwd scaling list for one plane */
4807 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat,
4808 size_satqd_weight_mat;
4809
4810 /* temp var */
4811 WORD32 total_size = 0;
4812
4813 /* size of quantization parameter list of 1 plane */
4814 size_quant_param = ALIGN64(sizeof(quant_params_t));
4815
4816 /* size of threshold matrix for quantization
4817 * (assuming the transform_8x8_flag is disabled).
4818 * for 1 plane */
4819 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4820
4821 /* size of forward weight matrix for quantization
4822 * (assuming the transform_8x8_flag is disabled).
4823 * for 1 plane */
4824 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4825
4826 /* size of SATQD matrix*/
4827 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4828
4829 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4830 {
4831 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4832
4833 /* quantization param structure */
4834 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4835 total_size = total_size + size_quant_param;
4836 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4837 total_size = total_size + size_quant_param;
4838 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4839 total_size = total_size + size_quant_param;
4840
4841 /* threshold matrix for quantization */
4842 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4843 total_size = total_size + size_thres_mat;
4844 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4845 total_size = total_size + size_thres_mat;
4846 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4847 total_size = total_size + size_thres_mat;
4848
4849 /* fwd weight matrix */
4850 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4851 total_size = total_size + size_fwd_weight_mat;
4852 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4853 total_size = total_size + size_fwd_weight_mat;
4854 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4855 total_size = total_size + size_fwd_weight_mat;
4856
4857 /* threshold matrix for SATQD */
4858 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4859 total_size = total_size + size_satqd_weight_mat;
4860 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4861 total_size = total_size + size_satqd_weight_mat;
4862 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4863 total_size = total_size + size_satqd_weight_mat;
4864
4865 total_size = ALIGN128(total_size);
4866 }
4867 }
4868
4869 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
4870 {
4871 /* total size of the mem record */
4872 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv;
4873
4874 /* pointer to buffer */
4875 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4876
4877 /* size in bytes to store 1 row of mb_info_t */
4878 /* one additional mb, to avoid checking end of row condition */
4879 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t);
4880
4881 /* size in bytes to store 1 row of intra macroblock sub modes */
4882 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16;
4883
4884 /* size in bytes to store 1 row + 1 of enc_pu_t */
4885 /* one additional mb, to avoid checking end of row condition */
4886 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t);
4887
4888 /* total size per proc ctxt */
4889 total_size = size_csbp + size_intra_modes + size_mv;
4890
4891 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4892 {
4893 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4894 {
4895 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4896 (mb_info_t *) pu1_buf;
4897 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4898 + size_csbp;
4899 ps_codec->as_process[i].ps_top_row_pu_base =
4900 (enc_pu_t *) (pu1_buf + size_csbp
4901 + size_intra_modes);
4902 }
4903 else
4904 {
4905 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4906 (mb_info_t *) (pu1_buf + total_size);
4907 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4908 + total_size + size_csbp;
4909 ps_codec->as_process[i].ps_top_row_pu_base =
4910 (enc_pu_t *) (pu1_buf + total_size + size_csbp
4911 + size_intra_modes);
4912 }
4913 }
4914 }
4915
4916 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
4917 {
4918 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4919
4920 /* total size of the mem record */
4921 WORD32 total_size = 0;
4922
4923 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
4924 WORD32 vert_bs_size, horz_bs_size, qp_size;
4925
4926 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
4927 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4928 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4929 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4930
4931 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
4932 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4933 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4934 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4935
4936 /* qp of each mb requires 1 byte */
4937 qp_size = ALIGN64(max_mb_cnt);
4938
4939 /* total size */
4940 total_size = vert_bs_size + horz_bs_size + qp_size;
4941
4942 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4943 {
4944 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4945 {
4946 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4947
4948 /* vertical edge bs storage space */
4949 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4950 (UWORD32 *) pu1_buf_ping;
4951 pu1_buf_ping += vert_bs_size;
4952
4953 /* horizontal edge bs storage space */
4954 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4955 (UWORD32 *) pu1_buf_ping;
4956 pu1_buf_ping += horz_bs_size;
4957
4958 /* qp */
4959 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4960 (UWORD8 *) pu1_buf_ping;
4961 pu1_buf_ping += qp_size;
4962 }
4963 else
4964 {
4965 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base;
4966 pu1_buf_pong += total_size;
4967
4968 /* vertical edge bs storage space */
4969 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4970 (UWORD32 *) pu1_buf_pong;
4971 pu1_buf_pong += vert_bs_size;
4972
4973 /* horizontal edge bs storage space */
4974 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4975 (UWORD32 *) pu1_buf_pong;
4976 pu1_buf_pong += horz_bs_size;
4977
4978 /* qp */
4979 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4980 (UWORD8 *) pu1_buf_pong;
4981 pu1_buf_pong += qp_size;
4982 }
4983 }
4984 }
4985
4986 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4987 {
4988 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4989 }
4990
4991 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4992 {
4993 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4994 }
4995
4996 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4997 {
4998 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4999 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base
5000 + (max_ht_luma * max_wd_luma);
5001 }
5002
5003 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
5004 {
5005 /* size of buf mgr struct */
5006 WORD32 size = ih264_buf_mgr_size();
5007
5008 /* temp var */
5009 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
5010
5011 /* pic buffer mgr */
5012 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
5013
5014 /* picture bank */
5015 ps_codec->pv_pic_buf_base = pu1_buf + size;
5016 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
5017 }
5018
5019 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
5020 {
5021 /* temp var */
5022 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
5023
5024 /* size of nmb ctxt */
5025 WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t);
5026
5027 WORD32 nmb_cntr, subpel_buf_size;
5028
5029 /* init nmb info structure pointer in all proc ctxts */
5030 for (i = 0; i < MAX_PROCESS_CTXT; i++)
5031 {
5032 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf);
5033
5034 pu1_buf += size;
5035 }
5036
5037 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8);
5038
5039 /* adjusting pointers for nmb halfpel buffer */
5040 for (i = 0; i < MAX_PROCESS_CTXT; i++)
5041 {
5042 mb_info_nmb_t* ps_mb_info_nmb =
5043 &ps_codec->as_process[i].ps_nmb_info[0];
5044
5045 for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
5046 {
5047 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
5048
5049 pu1_buf = pu1_buf + subpel_buf_size;
5050
5051 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
5052 }
5053 }
5054 }
5055
5056 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
5057 {
5058 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec,
5059 USE_BASE);
5060 }
5061
5062 /* init codec ctxt */
5063 status = ih264e_init(ps_codec);
5064
5065 return status;
5066 }
5067
5068 /**
5069 *******************************************************************************
5070 *
5071 * @brief
5072 * Retrieves mem records passed to the codec
5073 *
5074 * @par Description:
5075 * Retrieves mem recs passed during init
5076 *
5077 * @param[in] ps_codec_obj
5078 * Pointer to codec object at API level
5079 *
5080 * @param[in] pv_api_ip
5081 * Pointer to input argument structure
5082 *
5083 * @param[out] pv_api_op
5084 * Pointer to output argument structure
5085 *
5086 * @returns error status
5087 *
5088 * @remarks none
5089 *
5090 *******************************************************************************
5091 */
ih264e_retrieve_memrec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5092 static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj,
5093 void *pv_api_ip,
5094 void *pv_api_op)
5095 {
5096 /* codec ctxt */
5097 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5098
5099 /* ctrl call I/O structures */
5100 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
5101 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
5102
5103 if (ps_codec->i4_init_done != 1)
5104 {
5105 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5106 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5107 return IV_FAIL;
5108 }
5109
5110 /* join threads upon at end of sequence */
5111 ih264e_join_threads(ps_codec);
5112
5113 /* collect list of memory records used by the encoder library */
5114 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
5115 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
5116 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT;
5117
5118 /* clean up mutex memory */
5119 ih264_list_free(ps_codec->pv_entropy_jobq);
5120 ih264_list_free(ps_codec->pv_proc_jobq);
5121 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
5122 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
5123
5124
5125 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
5126 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr);
5127 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr);
5128 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr);
5129
5130 return IV_SUCCESS;
5131 }
5132
5133 /**
5134 *******************************************************************************
5135 *
5136 * @brief
5137 * Sets the encoder in flush mode.
5138 *
5139 * @par Description:
5140 * Sets the encoder in flush mode
5141 *
5142 * @param[in] ps_codec_obj
5143 * Pointer to codec object at API level
5144 *
5145 * @param[in] pv_api_ip
5146 * Pointer to input argument structure
5147 *
5148 * @param[out] pv_api_op
5149 * Pointer to output argument structure
5150 *
5151 * @returns error status
5152 *
5153 * @remarks This call has no real effect on encoder
5154 *
5155 *******************************************************************************
5156 */
ih264e_set_flush_mode(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5157 static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj,
5158 void *pv_api_ip,
5159 void *pv_api_op)
5160 {
5161 /* codec ctxt */
5162 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5163
5164 /* ctrl call I/O structures */
5165 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op;
5166
5167 UNUSED(pv_api_ip);
5168
5169 ps_ctl_op->s_ive_op.u4_error_code = 0;
5170
5171 /* signal flush frame control call */
5172 ps_codec->i4_flush_mode = 1;
5173
5174 return IV_SUCCESS;
5175 }
5176
5177 /**
5178 *******************************************************************************
5179 *
5180 * @brief
5181 * Gets encoder buffer requirements
5182 *
5183 * @par Description:
5184 * Gets the encoder buffer requirements. Basing on max width and max height
5185 * configuration settings, this routine, computes the sizes of necessary input,
5186 * output buffers returns this info to callee.
5187 *
5188 * @param[in] ps_codec_obj
5189 * Pointer to codec object at API level
5190 *
5191 * @param[in] pv_api_ip
5192 * Pointer to input argument structure
5193 *
5194 * @param[out] pv_api_op
5195 * Pointer to output argument structure
5196 *
5197 * @returns error status
5198 *
5199 * @remarks none
5200 *
5201 *******************************************************************************
5202 */
ih264e_get_buf_info(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5203 static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj,
5204 void *pv_api_ip,
5205 void *pv_api_op)
5206 {
5207 /* ctrl call I/O structures */
5208 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
5209 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
5210
5211 /* temp var */
5212 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
5213 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
5214 WORD32 i;
5215
5216 UNUSED(ps_codec_obj);
5217
5218 ps_op->s_ive_op.u4_error_code = 0;
5219
5220 /* Number of components in input buffers required for codec &
5221 * Minimum sizes of each component in input buffer required */
5222 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
5223 {
5224 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
5225
5226 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5227 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
5228 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
5229 }
5230 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
5231 {
5232 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
5233
5234 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5235 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5236 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5237 }
5238 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
5239 {
5240 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
5241
5242 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5243 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5244 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5245 }
5246 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
5247 {
5248 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
5249
5250 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
5251 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5252 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5253 }
5254 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV)
5255 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
5256 {
5257 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
5258
5259 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5260 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
5261 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5262 }
5263
5264 /* Number of components in output buffers required for codec &
5265 * Minimum sizes of each component in output buffer required */
5266 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
5267
5268 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
5269 {
5270 ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE);
5271 }
5272
5273 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
5274 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
5275
5276 return IV_SUCCESS;
5277 }
5278
5279 /**
5280 *******************************************************************************
5281 *
5282 * @brief
5283 * Sets the picture dimensions
5284 *
5285 * @par Description:
5286 * Sets width, height, display width, display height and strides
5287 *
5288 * @param[in] pv_api_ip
5289 * Pointer to input argument structure
5290 *
5291 * @param[out] pv_api_op
5292 * Pointer to output argument structure
5293 *
5294 * @param[out] ps_cfg
5295 * Pointer to config structure to be updated
5296 *
5297 * @returns error status
5298 *
5299 * @remarks none
5300 *
5301 *******************************************************************************
5302 */
ih264e_set_dimensions(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5303 static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip,
5304 void *pv_api_op,
5305 cfg_params_t *ps_cfg)
5306 {
5307 /* ctrl call I/O structures */
5308 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
5309 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
5310
5311 ps_op->s_ive_op.u4_error_code = 0;
5312
5313 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd);
5314 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht);
5315 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4;
5316 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4;
5317 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd;
5318 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht;
5319
5320 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5321 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5322
5323 return IV_SUCCESS;
5324 }
5325
5326 /**
5327 *******************************************************************************
5328 *
5329 * @brief
5330 * Sets source and target frame rates
5331 *
5332 * @par Description:
5333 * Sets source and target frame rates
5334 *
5335 * @param[in] pv_api_ip
5336 * Pointer to input argument structure
5337 *
5338 * @param[out] pv_api_op
5339 * Pointer to output argument structure
5340 *
5341 * @param[out] ps_cfg
5342 * Pointer to config structure to be updated
5343 *
5344 * @returns error status
5345 *
5346 * @remarks none
5347 *
5348 *******************************************************************************
5349 */
ih264e_set_frame_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5350 static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip,
5351 void *pv_api_op,
5352 cfg_params_t *ps_cfg)
5353 {
5354 /* ctrl call I/O structures */
5355 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
5356 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
5357
5358 ps_op->s_ive_op.u4_error_code = 0;
5359
5360 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
5361 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
5362
5363 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5364 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5365
5366 return IV_SUCCESS;
5367 }
5368
5369 /**
5370 *******************************************************************************
5371 *
5372 * @brief
5373 * Sets target bit rate
5374 *
5375 * @par Description:
5376 * Sets target bit rate
5377 *
5378 * @param[in] pv_api_ip
5379 * Pointer to input argument structure
5380 *
5381 * @param[out] pv_api_op
5382 * Pointer to output argument structure
5383 *
5384 * @param[out] ps_cfg
5385 * Pointer to config structure to be updated
5386 *
5387 * @returns error status
5388 *
5389 * @remarks none
5390 *
5391 *******************************************************************************
5392 */
ih264e_set_bit_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5393 static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip,
5394 void *pv_api_op,
5395 cfg_params_t *ps_cfg)
5396 {
5397 /* ctrl call I/O structures */
5398 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
5399 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
5400
5401 ps_op->s_ive_op.u4_error_code = 0;
5402
5403 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate;
5404
5405 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5406 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5407
5408 return IV_SUCCESS;
5409 }
5410
5411 /**
5412 *******************************************************************************
5413 *
5414 * @brief
5415 * Sets frame type
5416 *
5417 * @par Description:
5418 * Sets frame type
5419 *
5420 * @param[in] pv_api_ip
5421 * Pointer to input argument structure
5422 *
5423 * @param[out] pv_api_op
5424 * Pointer to output argument structure
5425 *
5426 * @param[out] ps_cfg
5427 * Pointer to config structure to be updated
5428 *
5429 * @returns error status
5430 *
5431 * @remarks not a sticky tag
5432 *
5433 *******************************************************************************
5434 */
ih264e_set_frame_type(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5435 static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip,
5436 void *pv_api_op,
5437 cfg_params_t *ps_cfg)
5438 {
5439 /* ctrl call I/O structures */
5440 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
5441 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
5442
5443 ps_op->s_ive_op.u4_error_code = 0;
5444
5445 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
5446
5447 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5448 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5449
5450 return IV_SUCCESS;
5451 }
5452
5453 /**
5454 *******************************************************************************
5455 *
5456 * @brief
5457 * Sets quantization params
5458 *
5459 * @par Description:
5460 * Sets the max, min and default qp for I frame, P frame and B frame
5461 *
5462 * @param[in] pv_api_ip
5463 * Pointer to input argument structure
5464 *
5465 * @param[out] pv_api_op
5466 * Pointer to output argument structure
5467 *
5468 * @param[out] ps_cfg
5469 * Pointer to config structure to be updated
5470 *
5471 * @returns error status
5472 *
5473 * @remarks none
5474 *
5475 *******************************************************************************
5476 */
ih264e_set_qp(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5477 static IV_STATUS_T ih264e_set_qp(void *pv_api_ip,
5478 void *pv_api_op,
5479 cfg_params_t *ps_cfg)
5480 {
5481 /* ctrl call I/O structures */
5482 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
5483 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
5484
5485 ps_set_qp_op->s_ive_op.u4_error_code = 0;
5486
5487 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max;
5488 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min;
5489 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp;
5490 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max;
5491 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min;
5492 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp;
5493 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max;
5494 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min;
5495 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp;
5496
5497 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
5498 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
5499
5500 return IV_SUCCESS;
5501 }
5502
5503 /**
5504 *******************************************************************************
5505 *
5506 * @brief
5507 * Sets encoding mode
5508 *
5509 * @par Description:
5510 * Sets encoding mode
5511 *
5512 * @param[in] pv_api_ip
5513 * Pointer to input argument structure
5514 *
5515 * @param[out] pv_api_op
5516 * Pointer to output argument structure
5517 *
5518 * @param[out] ps_cfg
5519 * Pointer to config structure to be updated
5520 *
5521 * @returns error status
5522 *
5523 * @remarks none
5524 *
5525 *******************************************************************************
5526 */
ih264e_set_enc_mode(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5527 static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip,
5528 void *pv_api_op,
5529 cfg_params_t *ps_cfg)
5530 {
5531 /* ctrl call I/O structures */
5532 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
5533 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
5534
5535 ps_op->s_ive_op.u4_error_code = 0;
5536
5537 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
5538
5539 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5540 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5541
5542 return IV_SUCCESS;
5543 }
5544
5545 /**
5546 *******************************************************************************
5547 *
5548 * @brief
5549 * Sets vbv parameters
5550 *
5551 * @par Description:
5552 * Sets vbv parameters
5553 *
5554 * @param[in] pv_api_ip
5555 * Pointer to input argument structure
5556 *
5557 * @param[out] pv_api_op
5558 * Pointer to output argument structure
5559 *
5560 * @param[out] ps_cfg
5561 * Pointer to config structure to be updated
5562 *
5563 * @returns error status
5564 *
5565 * @remarks none
5566 *
5567 *******************************************************************************
5568 */
ih264e_set_vbv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5569 static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip,
5570 void *pv_api_op,
5571 cfg_params_t *ps_cfg)
5572 {
5573 /* ctrl call I/O structures */
5574 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
5575 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
5576
5577 ps_op->s_ive_op.u4_error_code = 0;
5578
5579 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size;
5580 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay;
5581
5582 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5583 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5584
5585 return IV_SUCCESS;
5586 }
5587
5588 /**
5589 *******************************************************************************
5590 *
5591 * @brief
5592 * Sets AIR parameters
5593 *
5594 * @par Description:
5595 * Sets AIR parameters
5596 *
5597 * @param[in] pv_api_ip
5598 * Pointer to input argument structure
5599 *
5600 * @param[out] pv_api_op
5601 * Pointer to output argument structure
5602 *
5603 * @param[out] ps_cfg
5604 * Pointer to config structure to be updated
5605 *
5606 * @returns error status
5607 *
5608 * @remarks none
5609 *
5610 *******************************************************************************
5611 */
ih264_set_air_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5612 static IV_STATUS_T ih264_set_air_params(void *pv_api_ip,
5613 void *pv_api_op,
5614 cfg_params_t *ps_cfg)
5615 {
5616 /* ctrl call I/O structures */
5617 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
5618 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
5619
5620 ps_op->s_ive_op.u4_error_code = 0;
5621
5622 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
5623 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
5624
5625 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5626 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5627
5628 return IV_SUCCESS;
5629 }
5630
5631 /**
5632 *******************************************************************************
5633 *
5634 * @brief
5635 * Sets motion estimation parameters
5636 *
5637 * @par Description:
5638 * Sets motion estimation parameters
5639 *
5640 * @param[in] pv_api_ip
5641 * Pointer to input argument structure
5642 *
5643 * @param[out] pv_api_op
5644 * Pointer to output argument structure
5645 *
5646 * @param[out] ps_cfg
5647 * Pointer to config structure to be updated
5648 *
5649 * @returns error status
5650 *
5651 * @remarks none
5652 *
5653 *******************************************************************************
5654 */
ih264_set_me_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5655 static IV_STATUS_T ih264_set_me_params(void *pv_api_ip,
5656 void *pv_api_op,
5657 cfg_params_t *ps_cfg)
5658 {
5659 /* ctrl call I/O structures */
5660 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
5661 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
5662
5663 ps_op->s_ive_op.u4_error_code = 0;
5664
5665 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
5666 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
5667 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
5668 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
5669 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
5670 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
5671 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
5672
5673 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5674 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5675
5676 return IV_SUCCESS;
5677 }
5678
5679 /**
5680 *******************************************************************************
5681 *
5682 * @brief
5683 * Sets Intra/Inter Prediction estimation parameters
5684 *
5685 * @par Description:
5686 * Sets Intra/Inter Prediction estimation parameters
5687 *
5688 * @param[in] pv_api_ip
5689 * Pointer to input argument structure
5690 *
5691 * @param[out] pv_api_op
5692 * Pointer to output argument structure
5693 *
5694 * @param[out] ps_cfg
5695 * Pointer to config structure to be updated
5696 *
5697 * @returns error status
5698 *
5699 * @remarks none
5700 *
5701 *******************************************************************************
5702 */
ih264_set_ipe_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5703 static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip,
5704 void *pv_api_op,
5705 cfg_params_t *ps_cfg)
5706 {
5707 /* ctrl call I/O structures */
5708 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
5709 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
5710
5711 ps_op->s_ive_op.u4_error_code = 0;
5712
5713 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
5714 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
5715
5716 ps_cfg->u4_constrained_intra_pred = ps_ip->s_ive_ip.u4_constrained_intra_pred;
5717
5718 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5719 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5720
5721 return IV_SUCCESS;
5722 }
5723
5724 /**
5725 *******************************************************************************
5726 *
5727 * @brief
5728 * Sets GOP parameters
5729 *
5730 * @par Description:
5731 * Sets GOP parameters
5732 *
5733 * @param[in] pv_api_ip
5734 * Pointer to input argument structure
5735 *
5736 * @param[out] pv_api_op
5737 * Pointer to output argument structure
5738 *
5739 * @param[out] ps_cfg
5740 * Pointer to config structure to be updated
5741 *
5742 * @returns error status
5743 *
5744 * @remarks none
5745 *
5746 *******************************************************************************
5747 */
ih264_set_gop_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5748 static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip,
5749 void *pv_api_op,
5750 cfg_params_t *ps_cfg)
5751 {
5752 /* ctrl call I/O structures */
5753 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5754 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5755
5756 ps_op->s_ive_op.u4_error_code = 0;
5757
5758 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5759 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
5760
5761 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5762 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5763
5764 return IV_SUCCESS;
5765 }
5766
5767 /**
5768 *******************************************************************************
5769 *
5770 * @brief
5771 * Sets profile parameters
5772 *
5773 * @par Description:
5774 * Sets profile parameters
5775 *
5776 * @param[in] pv_api_ip
5777 * Pointer to input argument structure
5778 *
5779 * @param[out] pv_api_op
5780 * Pointer to output argument structure
5781 *
5782 * @param[out] ps_cfg
5783 * Pointer to config structure to be updated
5784 *
5785 * @returns error status
5786 *
5787 * @remarks none
5788 *
5789 *******************************************************************************
5790 */
ih264_set_profile_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5791 static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip,
5792 void *pv_api_op,
5793 cfg_params_t *ps_cfg)
5794 {
5795 /* ctrl call I/O structures */
5796 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5797 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5798
5799 ps_op->s_ive_op.u4_error_code = 0;
5800
5801 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5802
5803 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5804
5805 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5806 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5807
5808 return IV_SUCCESS;
5809 }
5810
5811 /**
5812 *******************************************************************************
5813 *
5814 * @brief
5815 * Sets disable deblock level
5816 *
5817 * @par Description:
5818 * Sets disable deblock level. Level 0 means no disabling and level 4 means
5819 * disable completely. 1, 2, 3 are intermediate levels that control amount
5820 * of deblocking done.
5821 *
5822 * @param[in] ps_codec_obj
5823 * Pointer to codec object at API level
5824 *
5825 * @param[in] pv_api_ip
5826 * Pointer to input argument structure
5827 *
5828 * @param[out] pv_api_op
5829 * Pointer to output argument structure
5830 *
5831 * @returns error status
5832 *
5833 * @remarks none
5834 *
5835 *******************************************************************************
5836 */
ih264_set_deblock_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5837 static WORD32 ih264_set_deblock_params(void *pv_api_ip,
5838 void *pv_api_op,
5839 cfg_params_t *ps_cfg)
5840 {
5841 /* ctrl call I/O structures */
5842 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5843 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5844
5845 ps_op->s_ive_op.u4_error_code = 0;
5846
5847 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5848
5849 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5850 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5851
5852 return IV_SUCCESS;
5853 }
5854 /**
5855 *******************************************************************************
5856 *
5857 * @brief
5858 * Sets vui params
5859 *
5860 * @par Description:
5861 * Video usability information
5862 *
5863 * @param[in] pv_api_ip
5864 * Pointer to input argument structure
5865 *
5866 * @param[out] pv_api_op
5867 * Pointer to output argument structure
5868 *
5869 * @param[out] ps_cfg
5870 * Pointer to config structure to be updated
5871 *
5872 * @returns error status
5873 *
5874 * @remarks none
5875 *
5876 *******************************************************************************
5877 */
ih264e_set_vui_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5878 static WORD32 ih264e_set_vui_params(void *pv_api_ip,
5879 void *pv_api_op,
5880 cfg_params_t *ps_cfg)
5881 {
5882 /* ctrl call I/O structures */
5883 ih264e_vui_ip_t *ps_ip = pv_api_ip;
5884 ih264e_vui_op_t *ps_op = pv_api_op;
5885 vui_t *ps_vui = &ps_cfg->s_vui;
5886
5887 ps_op->u4_error_code = 0;
5888
5889 ps_vui->u1_aspect_ratio_info_present_flag =
5890 ps_ip->u1_aspect_ratio_info_present_flag;
5891 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5892 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5893 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5894 ps_vui->u1_overscan_info_present_flag =
5895 ps_ip->u1_overscan_info_present_flag;
5896 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5897 ps_vui->u1_video_signal_type_present_flag =
5898 ps_ip->u1_video_signal_type_present_flag;
5899 ps_vui->u1_video_format = ps_ip->u1_video_format;
5900 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5901 ps_vui->u1_colour_description_present_flag =
5902 ps_ip->u1_colour_description_present_flag;
5903 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5904 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5905 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5906 ps_vui->u1_chroma_loc_info_present_flag =
5907 ps_ip->u1_chroma_loc_info_present_flag;
5908 ps_vui->u1_chroma_sample_loc_type_top_field =
5909 ps_ip->u1_chroma_sample_loc_type_top_field;
5910 ps_vui->u1_chroma_sample_loc_type_bottom_field =
5911 ps_ip->u1_chroma_sample_loc_type_bottom_field;
5912 ps_vui->u1_vui_timing_info_present_flag =
5913 ps_ip->u1_vui_timing_info_present_flag;
5914 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5915 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5916 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5917 ps_vui->u1_nal_hrd_parameters_present_flag =
5918 ps_ip->u1_nal_hrd_parameters_present_flag;
5919 ps_vui->u1_vcl_hrd_parameters_present_flag =
5920 ps_ip->u1_vcl_hrd_parameters_present_flag;
5921 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5922 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5923 ps_vui->u1_bitstream_restriction_flag =
5924 ps_ip->u1_bitstream_restriction_flag;
5925 ps_vui->u1_motion_vectors_over_pic_boundaries_flag =
5926 ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5927 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5928 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5929 ps_vui->u1_log2_max_mv_length_horizontal =
5930 ps_ip->u1_log2_max_mv_length_horizontal;
5931 ps_vui->u1_log2_max_mv_length_vertical =
5932 ps_ip->u1_log2_max_mv_length_vertical;
5933 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5934 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5935
5936 ps_cfg->u4_timestamp_high = -1;
5937 ps_cfg->u4_timestamp_low = -1;
5938
5939 return IV_SUCCESS;
5940 }
5941
5942 /**
5943 *******************************************************************************
5944 *
5945 * @brief
5946 * Sets Mastering display color volume sei params
5947 *
5948 * @par Description:
5949 * Supplemental enhancement information
5950 *
5951 * @param[in] pv_api_ip
5952 * Pointer to input argument structure
5953 *
5954 * @param[out] pv_api_op
5955 * Pointer to output argument structure
5956 *
5957 * @param[out] ps_cfg
5958 * Pointer to config structure to be updated
5959 *
5960 * @return error status
5961 *
5962 * @remarks none
5963 *
5964 *******************************************************************************
5965 */
ih264e_set_sei_mdcv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5966 static WORD32 ih264e_set_sei_mdcv_params(void *pv_api_ip,
5967 void *pv_api_op,
5968 cfg_params_t *ps_cfg)
5969 {
5970 WORD32 i4_count;
5971 /* ctrl call I/O structures */
5972 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
5973 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
5974 sei_params_t *ps_sei = &ps_cfg->s_sei;
5975
5976 ps_op->u4_error_code = 0;
5977
5978 ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag;
5979 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
5980 {
5981 ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] =
5982 ps_ip->au2_display_primaries_x[i4_count];
5983 ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] =
5984 ps_ip->au2_display_primaries_y[i4_count];
5985 }
5986
5987 ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x;
5988 ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y;
5989 ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance =
5990 ps_ip->u4_max_display_mastering_luminance;
5991 ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance =
5992 ps_ip->u4_min_display_mastering_luminance;
5993
5994 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5995 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5996
5997 return IV_SUCCESS;
5998 }
5999
6000 /**
6001 *******************************************************************************
6002 *
6003 * @brief
6004 * Sets content light level sei params
6005 *
6006 * @par Description:
6007 * Supplemental enhancement information
6008 *
6009 * @param[in] pv_api_ip
6010 * Pointer to input argument structure
6011 *
6012 * @param[out] pv_api_op
6013 * Pointer to output argument structure
6014 *
6015 * @param[out] ps_cfg
6016 * Pointer to config structure to be updated
6017 *
6018 * @return error status
6019 *
6020 * @remarks none
6021 *
6022 *******************************************************************************
6023 */
ih264e_set_sei_cll_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6024 static WORD32 ih264e_set_sei_cll_params(void *pv_api_ip,
6025 void *pv_api_op,
6026 cfg_params_t *ps_cfg)
6027 {
6028 /* ctrl call I/O structures */
6029 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
6030 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
6031 sei_params_t *ps_sei = &ps_cfg->s_sei;
6032
6033 ps_op->u4_error_code = 0;
6034
6035 ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag;
6036
6037 ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level;
6038 ps_sei->s_sei_cll_params.u2_max_pic_average_light_level =
6039 ps_ip->u2_max_pic_average_light_level;
6040
6041 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6042 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6043
6044 return IV_SUCCESS;
6045 }
6046
6047 /**
6048 *******************************************************************************
6049 *
6050 * @brief
6051 * Sets ambient viewing environment sei params
6052 *
6053 * @par Description:
6054 * Supplemental enhancement information
6055 *
6056 * @param[in] pv_api_ip
6057 * Pointer to input argument structure
6058 *
6059 * @param[out] pv_api_op
6060 * Pointer to output argument structure
6061 *
6062 * @param[out] ps_cfg
6063 * Pointer to config structure to be updated
6064 *
6065 * @return error status
6066 *
6067 * @remarks none
6068 *
6069 *******************************************************************************
6070 */
ih264e_set_sei_ave_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6071 static WORD32 ih264e_set_sei_ave_params(void *pv_api_ip,
6072 void *pv_api_op,
6073 cfg_params_t *ps_cfg)
6074 {
6075 /* ctrl call I/O structures */
6076 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
6077 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
6078 sei_params_t *ps_sei = &ps_cfg->s_sei;
6079
6080 ps_op->u4_error_code = 0;
6081
6082 ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag;
6083
6084 ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance;
6085 ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x;
6086 ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y;
6087
6088 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6089 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6090
6091 return IV_SUCCESS;
6092 }
6093
6094 /**
6095 *******************************************************************************
6096 *
6097 * @brief
6098 * Sets content color volume sei params
6099 *
6100 * @par Description:
6101 * Supplemental enhancement information
6102 *
6103 * @param[in] pv_api_ip
6104 * Pointer to input argument structure
6105 *
6106 * @param[out] pv_api_op
6107 * Pointer to output argument structure
6108 *
6109 * @param[out] ps_cfg
6110 * Pointer to config structure to be updated
6111 *
6112 * @return error status
6113 *
6114 * @remarks none
6115 *
6116 *******************************************************************************
6117 */
ih264e_set_sei_ccv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6118 static WORD32 ih264e_set_sei_ccv_params(void *pv_api_ip,
6119 void *pv_api_op,
6120 cfg_params_t *ps_cfg)
6121 {
6122 WORD32 i4_count;
6123 /* ctrl call I/O structures */
6124 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
6125 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
6126 sei_params_t *ps_sei = &ps_cfg->s_sei;
6127
6128 ps_op->u4_error_code = 0;
6129
6130 ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag;
6131
6132 ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag;
6133 ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag;
6134 ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag =
6135 ps_ip->u1_ccv_primaries_present_flag;
6136 ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag =
6137 ps_ip->u1_ccv_min_luminance_value_present_flag;
6138 ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag =
6139 ps_ip->u1_ccv_max_luminance_value_present_flag;
6140 ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag =
6141 ps_ip->u1_ccv_avg_luminance_value_present_flag;
6142 ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits =
6143 ps_ip->u1_ccv_reserved_zero_2bits;
6144
6145 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
6146 {
6147 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] =
6148 ps_ip->ai4_ccv_primaries_x[i4_count];
6149 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] =
6150 ps_ip->ai4_ccv_primaries_y[i4_count];
6151 }
6152
6153 ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value;
6154 ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value;
6155 ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value;
6156
6157 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6158 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6159
6160 return IV_SUCCESS;
6161 }
6162
6163 /**
6164 *******************************************************************************
6165 *
6166 * @brief
6167 * Sets shutter interval info sei params
6168 *
6169 * @par Description:
6170 * Supplemental enhancement information
6171 *
6172 * @param[in] pv_api_ip
6173 * Pointer to input argument structure
6174 *
6175 * @param[out] pv_api_op
6176 * Pointer to output argument structure
6177 *
6178 * @param[out] ps_cfg
6179 * Pointer to config structure to be updated
6180 *
6181 * @return error status
6182 *
6183 * @remarks none
6184 *
6185 *******************************************************************************
6186 */
ih264e_set_sei_sii_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6187 static WORD32 ih264e_set_sei_sii_params(void *pv_api_ip, void *pv_api_op, cfg_params_t *ps_cfg)
6188 {
6189 /* ctrl call I/O structures */
6190 ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip;
6191 ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op;
6192 sei_params_t *ps_sei = &ps_cfg->s_sei;
6193
6194 ps_op->u4_error_code = 0;
6195 ps_sei->u1_sei_sii_params_present_flag = ps_ip->u1_shutter_interval_info_present_flag;
6196 ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx = ps_ip->u4_sii_sub_layer_idx;
6197
6198 if(0 == ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx)
6199 {
6200 ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag =
6201 ps_ip->u1_shutter_interval_info_present_flag;
6202
6203 if(1 == ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag)
6204 {
6205 ps_sei->s_sei_sii_params.u4_sii_time_scale = ps_ip->u4_sii_time_scale;
6206 ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag =
6207 ps_ip->u1_fixed_shutter_interval_within_cvs_flag;
6208
6209 if(1 == ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag)
6210 {
6211 ps_sei->s_sei_sii_params.u4_sii_num_units_in_shutter_interval =
6212 ps_ip->u4_sii_num_units_in_shutter_interval;
6213 }
6214 else
6215 {
6216 int i;
6217 ps_sei->s_sei_sii_params.u1_sii_max_sub_layers_minus1 =
6218 ps_ip->u1_sii_max_sub_layers_minus1;
6219
6220 for(i = 0; i <= ps_ip->u1_sii_max_sub_layers_minus1; i++)
6221 {
6222 ps_sei->s_sei_sii_params.au4_sub_layer_num_units_in_shutter_interval[i] =
6223 ps_ip->au4_sub_layer_num_units_in_shutter_interval[i];
6224 }
6225 }
6226 }
6227 }
6228
6229 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6230 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6231
6232 return IV_SUCCESS;
6233 }
6234
6235 /**
6236 *******************************************************************************
6237 *
6238 * @brief
6239 * Sets number of cores
6240 *
6241 * @par Description:
6242 * Sets number of cores
6243 *
6244 * @param[in] ps_codec_obj
6245 * Pointer to codec object at API level
6246 *
6247 * @param[in] pv_api_ip
6248 * Pointer to input argument structure
6249 *
6250 * @param[out] pv_api_op
6251 * Pointer to output argument structure
6252 *
6253 * @returns error status
6254 *
6255 * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
6256 *
6257 *******************************************************************************
6258 */
ih264e_set_num_cores(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6259 static WORD32 ih264e_set_num_cores(void *pv_api_ip,
6260 void *pv_api_op,
6261 cfg_params_t *ps_cfg)
6262 {
6263 /* ctrl call I/O structures */
6264 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
6265 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
6266
6267 ps_op->s_ive_op.u4_error_code = 0;
6268
6269 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
6270
6271 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
6272 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
6273
6274 return IV_SUCCESS;
6275 }
6276
6277 /**
6278 *******************************************************************************
6279 *
6280 * @brief
6281 * Resets encoder state
6282 *
6283 * @par Description:
6284 * Resets encoder state by calling ih264e_init()
6285 *
6286 * @param[in] ps_codec_obj
6287 * Pointer to codec object at API level
6288 *
6289 * @param[in] pv_api_ip
6290 * Pointer to input argument structure
6291 *
6292 * @param[out] pv_api_op
6293 * Pointer to output argument structure
6294 *
6295 * @returns error status
6296 *
6297 * @remarks none
6298 *
6299 *******************************************************************************
6300 */
ih264e_reset(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6301 static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj,
6302 void *pv_api_ip,
6303 void *pv_api_op)
6304 {
6305 /* codec ctxt */
6306 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
6307
6308 /* ctrl call I/O structures */
6309 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
6310
6311 UNUSED(pv_api_ip);
6312
6313 ps_op->s_ive_op.u4_error_code = 0;
6314
6315 if (ps_codec != NULL)
6316 {
6317 ih264e_init(ps_codec);
6318 }
6319 else
6320 {
6321 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
6322 }
6323
6324 return IV_SUCCESS;
6325 }
6326
6327 /**
6328 *******************************************************************************
6329 *
6330 * @brief
6331 * Codec control call
6332 *
6333 * @par Description:
6334 * Codec control call which in turn calls appropriate calls based on sub-command
6335 *
6336 * @param[in] ps_codec_obj
6337 * Pointer to codec object at API level
6338 *
6339 * @param[in] pv_api_ip
6340 * Pointer to input argument structure
6341 *
6342 * @param[out] pv_api_op
6343 * Pointer to output argument structure
6344 *
6345 * @returns error status
6346 *
6347 * @remarks none
6348 *
6349 *******************************************************************************
6350 */
ih264e_ctl(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6351 static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj,
6352 void *pv_api_ip,
6353 void *pv_api_op)
6354 {
6355 /* codec ctxt */
6356 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
6357
6358 /* ctrl call I/O structures */
6359 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip;
6360 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op;
6361
6362 /* ctrl call sub cmd */
6363 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd;
6364
6365 /* error status */
6366 IV_STATUS_T ret = IV_SUCCESS;
6367
6368 /* temp var */
6369 WORD32 i;
6370 cfg_params_t *ps_cfg = NULL;
6371
6372 /* control call is for configuring encoding params, this is not to be called
6373 * before a successful init call */
6374 if (ps_codec->i4_init_done != 1)
6375 {
6376 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
6377 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
6378 return IV_FAIL;
6379 }
6380
6381 /* make it thread safe */
6382 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
6383
6384 /* find a free config param set to hold current parameters */
6385 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
6386 {
6387 if (0 == ps_codec->as_cfg[i].u4_is_valid)
6388 {
6389 ps_cfg = &ps_codec->as_cfg[i];
6390 break;
6391 }
6392 }
6393
6394 /* If all are invalid, then start overwriting from the head config params */
6395 if (NULL == ps_cfg)
6396 {
6397 ps_cfg = &ps_codec->as_cfg[0];
6398 }
6399
6400 ps_cfg->u4_is_valid = 1;
6401
6402 ps_cfg->e_cmd = sub_cmd;
6403
6404 switch (sub_cmd)
6405 {
6406 case IVE_CMD_CTL_SET_DIMENSIONS:
6407 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
6408 break;
6409
6410 case IVE_CMD_CTL_SET_FRAMERATE:
6411 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
6412 break;
6413
6414 case IVE_CMD_CTL_SET_BITRATE:
6415 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
6416 break;
6417
6418 case IVE_CMD_CTL_SET_FRAMETYPE:
6419 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
6420 break;
6421
6422 case IVE_CMD_CTL_SET_QP:
6423 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg);
6424 break;
6425
6426 case IVE_CMD_CTL_SET_ENC_MODE:
6427 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
6428 break;
6429
6430 case IVE_CMD_CTL_SET_VBV_PARAMS:
6431 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
6432 break;
6433
6434 case IVE_CMD_CTL_SET_AIR_PARAMS:
6435 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
6436 break;
6437
6438 case IVE_CMD_CTL_SET_ME_PARAMS:
6439 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
6440 break;
6441
6442 case IVE_CMD_CTL_SET_IPE_PARAMS:
6443 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
6444 break;
6445
6446 case IVE_CMD_CTL_SET_GOP_PARAMS:
6447 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
6448 break;
6449
6450 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
6451 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
6452 break;
6453
6454 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
6455 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
6456 break;
6457
6458 case IVE_CMD_CTL_SET_VUI_PARAMS:
6459 ret = ih264e_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
6460 break;
6461
6462 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
6463 ret = ih264e_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg);
6464 break;
6465
6466 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
6467 ret = ih264e_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg);
6468 break;
6469
6470 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
6471 ret = ih264e_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg);
6472 break;
6473
6474 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
6475 ret = ih264e_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg);
6476 break;
6477
6478 case IVE_CMD_CTL_SET_SEI_SII_PARAMS:
6479 ret = ih264e_set_sei_sii_params(pv_api_ip, pv_api_op, ps_cfg);
6480 break;
6481
6482 case IVE_CMD_CTL_RESET:
6483
6484 /* invalidate config param struct as it is being served right away */
6485 ps_codec->as_cfg[i].u4_is_valid = 0;
6486
6487 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op);
6488 break;
6489
6490 case IVE_CMD_CTL_SETDEFAULT:
6491 {
6492 /* ctrl call I/O structures */
6493 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
6494
6495 /* invalidate config param struct as it is being served right away */
6496 ps_codec->as_cfg[i].u4_is_valid = 0;
6497
6498 /* error status */
6499 ret = ih264e_set_default_params(ps_cfg);
6500
6501 ps_op->s_ive_op.u4_error_code = ret;
6502
6503 break;
6504 }
6505
6506 case IVE_CMD_CTL_FLUSH:
6507
6508 /* invalidate config param struct as it is being served right away */
6509 ps_codec->as_cfg[i].u4_is_valid = 0;
6510
6511 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
6512 break;
6513
6514 case IVE_CMD_CTL_GETBUFINFO:
6515
6516 /* invalidate config param struct as it is being served right away */
6517 ps_codec->as_cfg[i].u4_is_valid = 0;
6518
6519 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op);
6520 break;
6521
6522 case IVE_CMD_CTL_GETVERSION:
6523 {
6524 /* ctrl call I/O structures */
6525 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
6526 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
6527
6528 /* invalidate config param struct as it is being served right away */
6529 ps_codec->as_cfg[i].u4_is_valid = 0;
6530
6531 /* error status */
6532 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
6533
6534 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0)
6535 {
6536 ps_op->s_ive_op.u4_error_code =
6537 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6538 ret = IV_FAIL;
6539 }
6540 else
6541 {
6542 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
6543 ps_ip->s_ive_ip.u4_version_bufsize);
6544
6545 if (ret != IV_SUCCESS)
6546 {
6547 ps_op->s_ive_op.u4_error_code =
6548 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6549 ret = IV_FAIL;
6550 }
6551 }
6552 break;
6553 }
6554
6555 case IVE_CMD_CTL_SET_NUM_CORES:
6556 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
6557 break;
6558
6559 default:
6560 /* invalidate config param struct as it is being served right away */
6561 ps_codec->as_cfg[i].u4_is_valid = 0;
6562
6563 DEBUG("Warning !! unrecognized control api command \n");
6564 break;
6565 }
6566
6567 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
6568
6569 return ret;
6570 }
6571
6572 /**
6573 *******************************************************************************
6574 *
6575 * @brief
6576 * Codec entry point function. All the function calls to the codec are done
6577 * using this function with different values specified in command
6578 *
6579 * @par Description:
6580 * Arguments are tested for validity and then based on the command
6581 * appropriate function is called
6582 *
6583 * @param[in] ps_handle
6584 * API level handle for codec
6585 *
6586 * @param[in] pv_api_ip
6587 * Input argument structure
6588 *
6589 * @param[out] pv_api_op
6590 * Output argument structure
6591 *
6592 * @returns error_status
6593 *
6594 * @remarks
6595 *
6596 *******************************************************************************
6597 */
ih264e_api_function(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)6598 IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle,
6599 void *pv_api_ip,
6600 void *pv_api_op)
6601 {
6602 /* api command */
6603 WORD32 command = IV_CMD_NA;
6604
6605 /* error status */
6606 IV_STATUS_T e_status;
6607 WORD32 ret;
6608
6609 /* tmp var */
6610 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip;
6611
6612 /* validate input / output structures */
6613 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op);
6614
6615 if (e_status != IV_SUCCESS)
6616 {
6617 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1));
6618 return IV_FAIL;
6619 }
6620
6621 pu4_ptr_cmd++;
6622
6623 command = *pu4_ptr_cmd;
6624
6625 switch (command)
6626 {
6627 case IV_CMD_GET_NUM_MEM_REC:
6628 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op);
6629 break;
6630
6631 case IV_CMD_FILL_NUM_MEM_REC:
6632 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op);
6633 break;
6634
6635 case IV_CMD_INIT:
6636 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
6637 break;
6638
6639 case IV_CMD_RETRIEVE_MEMREC:
6640 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
6641 break;
6642
6643 case IVE_CMD_VIDEO_CTL:
6644 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op);
6645 break;
6646
6647 case IVE_CMD_VIDEO_ENCODE:
6648 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op);
6649 break;
6650
6651 default:
6652 ret = IV_FAIL;
6653 break;
6654 }
6655
6656 return (IV_STATUS_T) ret;
6657 }
6658