1 #ifndef CAPSTONE_ARM_H 2 #define CAPSTONE_ARM_H 3 4 /* Capstone Disassembly Engine */ 5 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #include "platform.h" 12 13 #ifdef _MSC_VER 14 #pragma warning(disable:4201) 15 #endif 16 17 /// ARM shift type 18 typedef enum arm_shifter { 19 ARM_SFT_INVALID = 0, 20 ARM_SFT_ASR, ///< shift with immediate const 21 ARM_SFT_LSL, ///< shift with immediate const 22 ARM_SFT_LSR, ///< shift with immediate const 23 ARM_SFT_ROR, ///< shift with immediate const 24 ARM_SFT_RRX, ///< shift with immediate const 25 ARM_SFT_ASR_REG, ///< shift with register 26 ARM_SFT_LSL_REG, ///< shift with register 27 ARM_SFT_LSR_REG, ///< shift with register 28 ARM_SFT_ROR_REG, ///< shift with register 29 ARM_SFT_RRX_REG, ///< shift with register 30 } arm_shifter; 31 32 /// ARM condition code 33 typedef enum arm_cc { 34 ARM_CC_INVALID = 0, 35 ARM_CC_EQ, ///< Equal Equal 36 ARM_CC_NE, ///< Not equal Not equal, or unordered 37 ARM_CC_HS, ///< Carry set >, ==, or unordered 38 ARM_CC_LO, ///< Carry clear Less than 39 ARM_CC_MI, ///< Minus, negative Less than 40 ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered 41 ARM_CC_VS, ///< Overflow Unordered 42 ARM_CC_VC, ///< No overflow Not unordered 43 ARM_CC_HI, ///< Unsigned higher Greater than, or unordered 44 ARM_CC_LS, ///< Unsigned lower or same Less than or equal 45 ARM_CC_GE, ///< Greater than or equal Greater than or equal 46 ARM_CC_LT, ///< Less than Less than, or unordered 47 ARM_CC_GT, ///< Greater than Greater than 48 ARM_CC_LE, ///< Less than or equal <, ==, or unordered 49 ARM_CC_AL ///< Always (unconditional) Always (unconditional) 50 } arm_cc; 51 52 typedef enum arm_sysreg { 53 /// Special registers for MSR 54 ARM_SYSREG_INVALID = 0, 55 56 // SPSR* registers can be OR combined 57 ARM_SYSREG_SPSR_C = 1, 58 ARM_SYSREG_SPSR_X = 2, 59 ARM_SYSREG_SPSR_S = 4, 60 ARM_SYSREG_SPSR_F = 8, 61 62 // CPSR* registers can be OR combined 63 ARM_SYSREG_CPSR_C = 16, 64 ARM_SYSREG_CPSR_X = 32, 65 ARM_SYSREG_CPSR_S = 64, 66 ARM_SYSREG_CPSR_F = 128, 67 68 // independent registers 69 ARM_SYSREG_APSR = 256, 70 ARM_SYSREG_APSR_G, 71 ARM_SYSREG_APSR_NZCVQ, 72 ARM_SYSREG_APSR_NZCVQG, 73 74 ARM_SYSREG_IAPSR, 75 ARM_SYSREG_IAPSR_G, 76 ARM_SYSREG_IAPSR_NZCVQG, 77 ARM_SYSREG_IAPSR_NZCVQ, 78 79 ARM_SYSREG_EAPSR, 80 ARM_SYSREG_EAPSR_G, 81 ARM_SYSREG_EAPSR_NZCVQG, 82 ARM_SYSREG_EAPSR_NZCVQ, 83 84 ARM_SYSREG_XPSR, 85 ARM_SYSREG_XPSR_G, 86 ARM_SYSREG_XPSR_NZCVQG, 87 ARM_SYSREG_XPSR_NZCVQ, 88 89 ARM_SYSREG_IPSR, 90 ARM_SYSREG_EPSR, 91 ARM_SYSREG_IEPSR, 92 93 ARM_SYSREG_MSP, 94 ARM_SYSREG_PSP, 95 ARM_SYSREG_PRIMASK, 96 ARM_SYSREG_BASEPRI, 97 ARM_SYSREG_BASEPRI_MAX, 98 ARM_SYSREG_FAULTMASK, 99 ARM_SYSREG_CONTROL, 100 101 // Banked Registers 102 ARM_SYSREG_R8_USR, 103 ARM_SYSREG_R9_USR, 104 ARM_SYSREG_R10_USR, 105 ARM_SYSREG_R11_USR, 106 ARM_SYSREG_R12_USR, 107 ARM_SYSREG_SP_USR, 108 ARM_SYSREG_LR_USR, 109 ARM_SYSREG_R8_FIQ, 110 ARM_SYSREG_R9_FIQ, 111 ARM_SYSREG_R10_FIQ, 112 ARM_SYSREG_R11_FIQ, 113 ARM_SYSREG_R12_FIQ, 114 ARM_SYSREG_SP_FIQ, 115 ARM_SYSREG_LR_FIQ, 116 ARM_SYSREG_LR_IRQ, 117 ARM_SYSREG_SP_IRQ, 118 ARM_SYSREG_LR_SVC, 119 ARM_SYSREG_SP_SVC, 120 ARM_SYSREG_LR_ABT, 121 ARM_SYSREG_SP_ABT, 122 ARM_SYSREG_LR_UND, 123 ARM_SYSREG_SP_UND, 124 ARM_SYSREG_LR_MON, 125 ARM_SYSREG_SP_MON, 126 ARM_SYSREG_ELR_HYP, 127 ARM_SYSREG_SP_HYP, 128 129 ARM_SYSREG_SPSR_FIQ, 130 ARM_SYSREG_SPSR_IRQ, 131 ARM_SYSREG_SPSR_SVC, 132 ARM_SYSREG_SPSR_ABT, 133 ARM_SYSREG_SPSR_UND, 134 ARM_SYSREG_SPSR_MON, 135 ARM_SYSREG_SPSR_HYP, 136 } arm_sysreg; 137 138 /// The memory barrier constants map directly to the 4-bit encoding of 139 /// the option field for Memory Barrier operations. 140 typedef enum arm_mem_barrier { 141 ARM_MB_INVALID = 0, 142 ARM_MB_RESERVED_0, 143 ARM_MB_OSHLD, 144 ARM_MB_OSHST, 145 ARM_MB_OSH, 146 ARM_MB_RESERVED_4, 147 ARM_MB_NSHLD, 148 ARM_MB_NSHST, 149 ARM_MB_NSH, 150 ARM_MB_RESERVED_8, 151 ARM_MB_ISHLD, 152 ARM_MB_ISHST, 153 ARM_MB_ISH, 154 ARM_MB_RESERVED_12, 155 ARM_MB_LD, 156 ARM_MB_ST, 157 ARM_MB_SY, 158 } arm_mem_barrier; 159 160 /// Operand type for instruction's operands 161 typedef enum arm_op_type { 162 ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 163 ARM_OP_REG, ///< = CS_OP_REG (Register operand). 164 ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand). 165 ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand). 166 ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand). 167 ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers) 168 ARM_OP_PIMM, ///< P-Immediate (coprocessor registers) 169 ARM_OP_SETEND, ///< operand for SETEND instruction 170 ARM_OP_SYSREG, ///< MSR/MRS special register operand 171 } arm_op_type; 172 173 /// Operand type for SETEND instruction 174 typedef enum arm_setend_type { 175 ARM_SETEND_INVALID = 0, ///< Uninitialized. 176 ARM_SETEND_BE, ///< BE operand. 177 ARM_SETEND_LE, ///< LE operand 178 } arm_setend_type; 179 180 typedef enum arm_cpsmode_type { 181 ARM_CPSMODE_INVALID = 0, 182 ARM_CPSMODE_IE = 2, 183 ARM_CPSMODE_ID = 3 184 } arm_cpsmode_type; 185 186 /// Operand type for SETEND instruction 187 typedef enum arm_cpsflag_type { 188 ARM_CPSFLAG_INVALID = 0, 189 ARM_CPSFLAG_F = 1, 190 ARM_CPSFLAG_I = 2, 191 ARM_CPSFLAG_A = 4, 192 ARM_CPSFLAG_NONE = 16, ///< no flag 193 } arm_cpsflag_type; 194 195 /// Data type for elements of vector instructions. 196 typedef enum arm_vectordata_type { 197 ARM_VECTORDATA_INVALID = 0, 198 199 // Integer type 200 ARM_VECTORDATA_I8, 201 ARM_VECTORDATA_I16, 202 ARM_VECTORDATA_I32, 203 ARM_VECTORDATA_I64, 204 205 // Signed integer type 206 ARM_VECTORDATA_S8, 207 ARM_VECTORDATA_S16, 208 ARM_VECTORDATA_S32, 209 ARM_VECTORDATA_S64, 210 211 // Unsigned integer type 212 ARM_VECTORDATA_U8, 213 ARM_VECTORDATA_U16, 214 ARM_VECTORDATA_U32, 215 ARM_VECTORDATA_U64, 216 217 // Data type for VMUL/VMULL 218 ARM_VECTORDATA_P8, 219 220 // Floating type 221 ARM_VECTORDATA_F32, 222 ARM_VECTORDATA_F64, 223 224 // Convert float <-> float 225 ARM_VECTORDATA_F16F64, // f16.f64 226 ARM_VECTORDATA_F64F16, // f64.f16 227 ARM_VECTORDATA_F32F16, // f32.f16 228 ARM_VECTORDATA_F16F32, // f32.f16 229 ARM_VECTORDATA_F64F32, // f64.f32 230 ARM_VECTORDATA_F32F64, // f32.f64 231 232 // Convert integer <-> float 233 ARM_VECTORDATA_S32F32, // s32.f32 234 ARM_VECTORDATA_U32F32, // u32.f32 235 ARM_VECTORDATA_F32S32, // f32.s32 236 ARM_VECTORDATA_F32U32, // f32.u32 237 ARM_VECTORDATA_F64S16, // f64.s16 238 ARM_VECTORDATA_F32S16, // f32.s16 239 ARM_VECTORDATA_F64S32, // f64.s32 240 ARM_VECTORDATA_S16F64, // s16.f64 241 ARM_VECTORDATA_S16F32, // s16.f64 242 ARM_VECTORDATA_S32F64, // s32.f64 243 ARM_VECTORDATA_U16F64, // u16.f64 244 ARM_VECTORDATA_U16F32, // u16.f32 245 ARM_VECTORDATA_U32F64, // u32.f64 246 ARM_VECTORDATA_F64U16, // f64.u16 247 ARM_VECTORDATA_F32U16, // f32.u16 248 ARM_VECTORDATA_F64U32, // f64.u32 249 } arm_vectordata_type; 250 251 /// ARM registers 252 typedef enum arm_reg { 253 ARM_REG_INVALID = 0, 254 ARM_REG_APSR, 255 ARM_REG_APSR_NZCV, 256 ARM_REG_CPSR, 257 ARM_REG_FPEXC, 258 ARM_REG_FPINST, 259 ARM_REG_FPSCR, 260 ARM_REG_FPSCR_NZCV, 261 ARM_REG_FPSID, 262 ARM_REG_ITSTATE, 263 ARM_REG_LR, 264 ARM_REG_PC, 265 ARM_REG_SP, 266 ARM_REG_SPSR, 267 ARM_REG_D0, 268 ARM_REG_D1, 269 ARM_REG_D2, 270 ARM_REG_D3, 271 ARM_REG_D4, 272 ARM_REG_D5, 273 ARM_REG_D6, 274 ARM_REG_D7, 275 ARM_REG_D8, 276 ARM_REG_D9, 277 ARM_REG_D10, 278 ARM_REG_D11, 279 ARM_REG_D12, 280 ARM_REG_D13, 281 ARM_REG_D14, 282 ARM_REG_D15, 283 ARM_REG_D16, 284 ARM_REG_D17, 285 ARM_REG_D18, 286 ARM_REG_D19, 287 ARM_REG_D20, 288 ARM_REG_D21, 289 ARM_REG_D22, 290 ARM_REG_D23, 291 ARM_REG_D24, 292 ARM_REG_D25, 293 ARM_REG_D26, 294 ARM_REG_D27, 295 ARM_REG_D28, 296 ARM_REG_D29, 297 ARM_REG_D30, 298 ARM_REG_D31, 299 ARM_REG_FPINST2, 300 ARM_REG_MVFR0, 301 ARM_REG_MVFR1, 302 ARM_REG_MVFR2, 303 ARM_REG_Q0, 304 ARM_REG_Q1, 305 ARM_REG_Q2, 306 ARM_REG_Q3, 307 ARM_REG_Q4, 308 ARM_REG_Q5, 309 ARM_REG_Q6, 310 ARM_REG_Q7, 311 ARM_REG_Q8, 312 ARM_REG_Q9, 313 ARM_REG_Q10, 314 ARM_REG_Q11, 315 ARM_REG_Q12, 316 ARM_REG_Q13, 317 ARM_REG_Q14, 318 ARM_REG_Q15, 319 ARM_REG_R0, 320 ARM_REG_R1, 321 ARM_REG_R2, 322 ARM_REG_R3, 323 ARM_REG_R4, 324 ARM_REG_R5, 325 ARM_REG_R6, 326 ARM_REG_R7, 327 ARM_REG_R8, 328 ARM_REG_R9, 329 ARM_REG_R10, 330 ARM_REG_R11, 331 ARM_REG_R12, 332 ARM_REG_S0, 333 ARM_REG_S1, 334 ARM_REG_S2, 335 ARM_REG_S3, 336 ARM_REG_S4, 337 ARM_REG_S5, 338 ARM_REG_S6, 339 ARM_REG_S7, 340 ARM_REG_S8, 341 ARM_REG_S9, 342 ARM_REG_S10, 343 ARM_REG_S11, 344 ARM_REG_S12, 345 ARM_REG_S13, 346 ARM_REG_S14, 347 ARM_REG_S15, 348 ARM_REG_S16, 349 ARM_REG_S17, 350 ARM_REG_S18, 351 ARM_REG_S19, 352 ARM_REG_S20, 353 ARM_REG_S21, 354 ARM_REG_S22, 355 ARM_REG_S23, 356 ARM_REG_S24, 357 ARM_REG_S25, 358 ARM_REG_S26, 359 ARM_REG_S27, 360 ARM_REG_S28, 361 ARM_REG_S29, 362 ARM_REG_S30, 363 ARM_REG_S31, 364 365 ARM_REG_ENDING, // <-- mark the end of the list or registers 366 367 // alias registers 368 ARM_REG_R13 = ARM_REG_SP, 369 ARM_REG_R14 = ARM_REG_LR, 370 ARM_REG_R15 = ARM_REG_PC, 371 372 ARM_REG_SB = ARM_REG_R9, 373 ARM_REG_SL = ARM_REG_R10, 374 ARM_REG_FP = ARM_REG_R11, 375 ARM_REG_IP = ARM_REG_R12, 376 } arm_reg; 377 378 /// Instruction's operand referring to memory 379 /// This is associated with ARM_OP_MEM operand type above 380 typedef struct arm_op_mem { 381 arm_reg base; ///< base register 382 arm_reg index; ///< index register 383 int scale; ///< scale for index register (can be 1, or -1) 384 int disp; ///< displacement/offset value 385 /// left-shift on index register, or 0 if irrelevant 386 /// NOTE: this value can also be fetched via operand.shift.value 387 int lshift; 388 } arm_op_mem; 389 390 /// Instruction operand 391 typedef struct cs_arm_op { 392 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) 393 394 struct { 395 arm_shifter type; 396 unsigned int value; 397 } shift; 398 399 arm_op_type type; ///< operand type 400 401 union { 402 int reg; ///< register value for REG/SYSREG operand 403 int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand 404 double fp; ///< floating point value for FP operand 405 arm_op_mem mem; ///< base/index/scale/disp value for MEM operand 406 arm_setend_type setend; ///< SETEND instruction's operand type 407 }; 408 409 /// in some instructions, an operand can be subtracted or added to 410 /// the base register, 411 /// if TRUE, this operand is subtracted. otherwise, it is added. 412 bool subtracted; 413 414 /// How is this operand accessed? (READ, WRITE or READ|WRITE) 415 /// This field is combined of cs_ac_type. 416 /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 417 uint8_t access; 418 419 /// Neon lane index for NEON instructions (or -1 if irrelevant) 420 int8_t neon_lane; 421 } cs_arm_op; 422 423 /// Instruction structure 424 typedef struct cs_arm { 425 bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions) 426 int vector_size; ///< Scalar size for vector instructions 427 arm_vectordata_type vector_data; ///< Data type for elements of vector instructions 428 arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction 429 arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction 430 arm_cc cc; ///< conditional code for this insn 431 bool update_flags; ///< does this insn update flags? 432 bool writeback; ///< does this insn write-back? 433 arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions 434 435 /// Number of operands of this instruction, 436 /// or 0 when instruction has no operand. 437 uint8_t op_count; 438 439 cs_arm_op operands[36]; ///< operands for this instruction. 440 } cs_arm; 441 442 /// ARM instruction 443 typedef enum arm_insn { 444 ARM_INS_INVALID = 0, 445 446 ARM_INS_ADC, 447 ARM_INS_ADD, 448 ARM_INS_ADR, 449 ARM_INS_AESD, 450 ARM_INS_AESE, 451 ARM_INS_AESIMC, 452 ARM_INS_AESMC, 453 ARM_INS_AND, 454 ARM_INS_BFC, 455 ARM_INS_BFI, 456 ARM_INS_BIC, 457 ARM_INS_BKPT, 458 ARM_INS_BL, 459 ARM_INS_BLX, 460 ARM_INS_BX, 461 ARM_INS_BXJ, 462 ARM_INS_B, 463 ARM_INS_CDP, 464 ARM_INS_CDP2, 465 ARM_INS_CLREX, 466 ARM_INS_CLZ, 467 ARM_INS_CMN, 468 ARM_INS_CMP, 469 ARM_INS_CPS, 470 ARM_INS_CRC32B, 471 ARM_INS_CRC32CB, 472 ARM_INS_CRC32CH, 473 ARM_INS_CRC32CW, 474 ARM_INS_CRC32H, 475 ARM_INS_CRC32W, 476 ARM_INS_DBG, 477 ARM_INS_DMB, 478 ARM_INS_DSB, 479 ARM_INS_EOR, 480 ARM_INS_ERET, 481 ARM_INS_VMOV, 482 ARM_INS_FLDMDBX, 483 ARM_INS_FLDMIAX, 484 ARM_INS_VMRS, 485 ARM_INS_FSTMDBX, 486 ARM_INS_FSTMIAX, 487 ARM_INS_HINT, 488 ARM_INS_HLT, 489 ARM_INS_HVC, 490 ARM_INS_ISB, 491 ARM_INS_LDA, 492 ARM_INS_LDAB, 493 ARM_INS_LDAEX, 494 ARM_INS_LDAEXB, 495 ARM_INS_LDAEXD, 496 ARM_INS_LDAEXH, 497 ARM_INS_LDAH, 498 ARM_INS_LDC2L, 499 ARM_INS_LDC2, 500 ARM_INS_LDCL, 501 ARM_INS_LDC, 502 ARM_INS_LDMDA, 503 ARM_INS_LDMDB, 504 ARM_INS_LDM, 505 ARM_INS_LDMIB, 506 ARM_INS_LDRBT, 507 ARM_INS_LDRB, 508 ARM_INS_LDRD, 509 ARM_INS_LDREX, 510 ARM_INS_LDREXB, 511 ARM_INS_LDREXD, 512 ARM_INS_LDREXH, 513 ARM_INS_LDRH, 514 ARM_INS_LDRHT, 515 ARM_INS_LDRSB, 516 ARM_INS_LDRSBT, 517 ARM_INS_LDRSH, 518 ARM_INS_LDRSHT, 519 ARM_INS_LDRT, 520 ARM_INS_LDR, 521 ARM_INS_MCR, 522 ARM_INS_MCR2, 523 ARM_INS_MCRR, 524 ARM_INS_MCRR2, 525 ARM_INS_MLA, 526 ARM_INS_MLS, 527 ARM_INS_MOV, 528 ARM_INS_MOVT, 529 ARM_INS_MOVW, 530 ARM_INS_MRC, 531 ARM_INS_MRC2, 532 ARM_INS_MRRC, 533 ARM_INS_MRRC2, 534 ARM_INS_MRS, 535 ARM_INS_MSR, 536 ARM_INS_MUL, 537 ARM_INS_MVN, 538 ARM_INS_ORR, 539 ARM_INS_PKHBT, 540 ARM_INS_PKHTB, 541 ARM_INS_PLDW, 542 ARM_INS_PLD, 543 ARM_INS_PLI, 544 ARM_INS_QADD, 545 ARM_INS_QADD16, 546 ARM_INS_QADD8, 547 ARM_INS_QASX, 548 ARM_INS_QDADD, 549 ARM_INS_QDSUB, 550 ARM_INS_QSAX, 551 ARM_INS_QSUB, 552 ARM_INS_QSUB16, 553 ARM_INS_QSUB8, 554 ARM_INS_RBIT, 555 ARM_INS_REV, 556 ARM_INS_REV16, 557 ARM_INS_REVSH, 558 ARM_INS_RFEDA, 559 ARM_INS_RFEDB, 560 ARM_INS_RFEIA, 561 ARM_INS_RFEIB, 562 ARM_INS_RSB, 563 ARM_INS_RSC, 564 ARM_INS_SADD16, 565 ARM_INS_SADD8, 566 ARM_INS_SASX, 567 ARM_INS_SBC, 568 ARM_INS_SBFX, 569 ARM_INS_SDIV, 570 ARM_INS_SEL, 571 ARM_INS_SETEND, 572 ARM_INS_SHA1C, 573 ARM_INS_SHA1H, 574 ARM_INS_SHA1M, 575 ARM_INS_SHA1P, 576 ARM_INS_SHA1SU0, 577 ARM_INS_SHA1SU1, 578 ARM_INS_SHA256H, 579 ARM_INS_SHA256H2, 580 ARM_INS_SHA256SU0, 581 ARM_INS_SHA256SU1, 582 ARM_INS_SHADD16, 583 ARM_INS_SHADD8, 584 ARM_INS_SHASX, 585 ARM_INS_SHSAX, 586 ARM_INS_SHSUB16, 587 ARM_INS_SHSUB8, 588 ARM_INS_SMC, 589 ARM_INS_SMLABB, 590 ARM_INS_SMLABT, 591 ARM_INS_SMLAD, 592 ARM_INS_SMLADX, 593 ARM_INS_SMLAL, 594 ARM_INS_SMLALBB, 595 ARM_INS_SMLALBT, 596 ARM_INS_SMLALD, 597 ARM_INS_SMLALDX, 598 ARM_INS_SMLALTB, 599 ARM_INS_SMLALTT, 600 ARM_INS_SMLATB, 601 ARM_INS_SMLATT, 602 ARM_INS_SMLAWB, 603 ARM_INS_SMLAWT, 604 ARM_INS_SMLSD, 605 ARM_INS_SMLSDX, 606 ARM_INS_SMLSLD, 607 ARM_INS_SMLSLDX, 608 ARM_INS_SMMLA, 609 ARM_INS_SMMLAR, 610 ARM_INS_SMMLS, 611 ARM_INS_SMMLSR, 612 ARM_INS_SMMUL, 613 ARM_INS_SMMULR, 614 ARM_INS_SMUAD, 615 ARM_INS_SMUADX, 616 ARM_INS_SMULBB, 617 ARM_INS_SMULBT, 618 ARM_INS_SMULL, 619 ARM_INS_SMULTB, 620 ARM_INS_SMULTT, 621 ARM_INS_SMULWB, 622 ARM_INS_SMULWT, 623 ARM_INS_SMUSD, 624 ARM_INS_SMUSDX, 625 ARM_INS_SRSDA, 626 ARM_INS_SRSDB, 627 ARM_INS_SRSIA, 628 ARM_INS_SRSIB, 629 ARM_INS_SSAT, 630 ARM_INS_SSAT16, 631 ARM_INS_SSAX, 632 ARM_INS_SSUB16, 633 ARM_INS_SSUB8, 634 ARM_INS_STC2L, 635 ARM_INS_STC2, 636 ARM_INS_STCL, 637 ARM_INS_STC, 638 ARM_INS_STL, 639 ARM_INS_STLB, 640 ARM_INS_STLEX, 641 ARM_INS_STLEXB, 642 ARM_INS_STLEXD, 643 ARM_INS_STLEXH, 644 ARM_INS_STLH, 645 ARM_INS_STMDA, 646 ARM_INS_STMDB, 647 ARM_INS_STM, 648 ARM_INS_STMIB, 649 ARM_INS_STRBT, 650 ARM_INS_STRB, 651 ARM_INS_STRD, 652 ARM_INS_STREX, 653 ARM_INS_STREXB, 654 ARM_INS_STREXD, 655 ARM_INS_STREXH, 656 ARM_INS_STRH, 657 ARM_INS_STRHT, 658 ARM_INS_STRT, 659 ARM_INS_STR, 660 ARM_INS_SUB, 661 ARM_INS_SVC, 662 ARM_INS_SWP, 663 ARM_INS_SWPB, 664 ARM_INS_SXTAB, 665 ARM_INS_SXTAB16, 666 ARM_INS_SXTAH, 667 ARM_INS_SXTB, 668 ARM_INS_SXTB16, 669 ARM_INS_SXTH, 670 ARM_INS_TEQ, 671 ARM_INS_TRAP, 672 ARM_INS_TST, 673 ARM_INS_UADD16, 674 ARM_INS_UADD8, 675 ARM_INS_UASX, 676 ARM_INS_UBFX, 677 ARM_INS_UDF, 678 ARM_INS_UDIV, 679 ARM_INS_UHADD16, 680 ARM_INS_UHADD8, 681 ARM_INS_UHASX, 682 ARM_INS_UHSAX, 683 ARM_INS_UHSUB16, 684 ARM_INS_UHSUB8, 685 ARM_INS_UMAAL, 686 ARM_INS_UMLAL, 687 ARM_INS_UMULL, 688 ARM_INS_UQADD16, 689 ARM_INS_UQADD8, 690 ARM_INS_UQASX, 691 ARM_INS_UQSAX, 692 ARM_INS_UQSUB16, 693 ARM_INS_UQSUB8, 694 ARM_INS_USAD8, 695 ARM_INS_USADA8, 696 ARM_INS_USAT, 697 ARM_INS_USAT16, 698 ARM_INS_USAX, 699 ARM_INS_USUB16, 700 ARM_INS_USUB8, 701 ARM_INS_UXTAB, 702 ARM_INS_UXTAB16, 703 ARM_INS_UXTAH, 704 ARM_INS_UXTB, 705 ARM_INS_UXTB16, 706 ARM_INS_UXTH, 707 ARM_INS_VABAL, 708 ARM_INS_VABA, 709 ARM_INS_VABDL, 710 ARM_INS_VABD, 711 ARM_INS_VABS, 712 ARM_INS_VACGE, 713 ARM_INS_VACGT, 714 ARM_INS_VADD, 715 ARM_INS_VADDHN, 716 ARM_INS_VADDL, 717 ARM_INS_VADDW, 718 ARM_INS_VAND, 719 ARM_INS_VBIC, 720 ARM_INS_VBIF, 721 ARM_INS_VBIT, 722 ARM_INS_VBSL, 723 ARM_INS_VCEQ, 724 ARM_INS_VCGE, 725 ARM_INS_VCGT, 726 ARM_INS_VCLE, 727 ARM_INS_VCLS, 728 ARM_INS_VCLT, 729 ARM_INS_VCLZ, 730 ARM_INS_VCMP, 731 ARM_INS_VCMPE, 732 ARM_INS_VCNT, 733 ARM_INS_VCVTA, 734 ARM_INS_VCVTB, 735 ARM_INS_VCVT, 736 ARM_INS_VCVTM, 737 ARM_INS_VCVTN, 738 ARM_INS_VCVTP, 739 ARM_INS_VCVTT, 740 ARM_INS_VDIV, 741 ARM_INS_VDUP, 742 ARM_INS_VEOR, 743 ARM_INS_VEXT, 744 ARM_INS_VFMA, 745 ARM_INS_VFMS, 746 ARM_INS_VFNMA, 747 ARM_INS_VFNMS, 748 ARM_INS_VHADD, 749 ARM_INS_VHSUB, 750 ARM_INS_VLD1, 751 ARM_INS_VLD2, 752 ARM_INS_VLD3, 753 ARM_INS_VLD4, 754 ARM_INS_VLDMDB, 755 ARM_INS_VLDMIA, 756 ARM_INS_VLDR, 757 ARM_INS_VMAXNM, 758 ARM_INS_VMAX, 759 ARM_INS_VMINNM, 760 ARM_INS_VMIN, 761 ARM_INS_VMLA, 762 ARM_INS_VMLAL, 763 ARM_INS_VMLS, 764 ARM_INS_VMLSL, 765 ARM_INS_VMOVL, 766 ARM_INS_VMOVN, 767 ARM_INS_VMSR, 768 ARM_INS_VMUL, 769 ARM_INS_VMULL, 770 ARM_INS_VMVN, 771 ARM_INS_VNEG, 772 ARM_INS_VNMLA, 773 ARM_INS_VNMLS, 774 ARM_INS_VNMUL, 775 ARM_INS_VORN, 776 ARM_INS_VORR, 777 ARM_INS_VPADAL, 778 ARM_INS_VPADDL, 779 ARM_INS_VPADD, 780 ARM_INS_VPMAX, 781 ARM_INS_VPMIN, 782 ARM_INS_VQABS, 783 ARM_INS_VQADD, 784 ARM_INS_VQDMLAL, 785 ARM_INS_VQDMLSL, 786 ARM_INS_VQDMULH, 787 ARM_INS_VQDMULL, 788 ARM_INS_VQMOVUN, 789 ARM_INS_VQMOVN, 790 ARM_INS_VQNEG, 791 ARM_INS_VQRDMULH, 792 ARM_INS_VQRSHL, 793 ARM_INS_VQRSHRN, 794 ARM_INS_VQRSHRUN, 795 ARM_INS_VQSHL, 796 ARM_INS_VQSHLU, 797 ARM_INS_VQSHRN, 798 ARM_INS_VQSHRUN, 799 ARM_INS_VQSUB, 800 ARM_INS_VRADDHN, 801 ARM_INS_VRECPE, 802 ARM_INS_VRECPS, 803 ARM_INS_VREV16, 804 ARM_INS_VREV32, 805 ARM_INS_VREV64, 806 ARM_INS_VRHADD, 807 ARM_INS_VRINTA, 808 ARM_INS_VRINTM, 809 ARM_INS_VRINTN, 810 ARM_INS_VRINTP, 811 ARM_INS_VRINTR, 812 ARM_INS_VRINTX, 813 ARM_INS_VRINTZ, 814 ARM_INS_VRSHL, 815 ARM_INS_VRSHRN, 816 ARM_INS_VRSHR, 817 ARM_INS_VRSQRTE, 818 ARM_INS_VRSQRTS, 819 ARM_INS_VRSRA, 820 ARM_INS_VRSUBHN, 821 ARM_INS_VSELEQ, 822 ARM_INS_VSELGE, 823 ARM_INS_VSELGT, 824 ARM_INS_VSELVS, 825 ARM_INS_VSHLL, 826 ARM_INS_VSHL, 827 ARM_INS_VSHRN, 828 ARM_INS_VSHR, 829 ARM_INS_VSLI, 830 ARM_INS_VSQRT, 831 ARM_INS_VSRA, 832 ARM_INS_VSRI, 833 ARM_INS_VST1, 834 ARM_INS_VST2, 835 ARM_INS_VST3, 836 ARM_INS_VST4, 837 ARM_INS_VSTMDB, 838 ARM_INS_VSTMIA, 839 ARM_INS_VSTR, 840 ARM_INS_VSUB, 841 ARM_INS_VSUBHN, 842 ARM_INS_VSUBL, 843 ARM_INS_VSUBW, 844 ARM_INS_VSWP, 845 ARM_INS_VTBL, 846 ARM_INS_VTBX, 847 ARM_INS_VCVTR, 848 ARM_INS_VTRN, 849 ARM_INS_VTST, 850 ARM_INS_VUZP, 851 ARM_INS_VZIP, 852 ARM_INS_ADDW, 853 ARM_INS_ASR, 854 ARM_INS_DCPS1, 855 ARM_INS_DCPS2, 856 ARM_INS_DCPS3, 857 ARM_INS_IT, 858 ARM_INS_LSL, 859 ARM_INS_LSR, 860 ARM_INS_ORN, 861 ARM_INS_ROR, 862 ARM_INS_RRX, 863 ARM_INS_SUBW, 864 ARM_INS_TBB, 865 ARM_INS_TBH, 866 ARM_INS_CBNZ, 867 ARM_INS_CBZ, 868 ARM_INS_POP, 869 ARM_INS_PUSH, 870 871 // special instructions 872 ARM_INS_NOP, 873 ARM_INS_YIELD, 874 ARM_INS_WFE, 875 ARM_INS_WFI, 876 ARM_INS_SEV, 877 ARM_INS_SEVL, 878 ARM_INS_VPUSH, 879 ARM_INS_VPOP, 880 881 ARM_INS_ENDING, // <-- mark the end of the list of instructions 882 } arm_insn; 883 884 /// Group of ARM instructions 885 typedef enum arm_insn_group { 886 ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID 887 888 // Generic groups 889 // all jump instructions (conditional+direct+indirect jumps) 890 ARM_GRP_JUMP, ///< = CS_GRP_JUMP 891 ARM_GRP_CALL, ///< = CS_GRP_CALL 892 ARM_GRP_INT = 4, ///< = CS_GRP_INT 893 ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE 894 ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE 895 896 // Architecture-specific groups 897 ARM_GRP_CRYPTO = 128, 898 ARM_GRP_DATABARRIER, 899 ARM_GRP_DIVIDE, 900 ARM_GRP_FPARMV8, 901 ARM_GRP_MULTPRO, 902 ARM_GRP_NEON, 903 ARM_GRP_T2EXTRACTPACK, 904 ARM_GRP_THUMB2DSP, 905 ARM_GRP_TRUSTZONE, 906 ARM_GRP_V4T, 907 ARM_GRP_V5T, 908 ARM_GRP_V5TE, 909 ARM_GRP_V6, 910 ARM_GRP_V6T2, 911 ARM_GRP_V7, 912 ARM_GRP_V8, 913 ARM_GRP_VFP2, 914 ARM_GRP_VFP3, 915 ARM_GRP_VFP4, 916 ARM_GRP_ARM, 917 ARM_GRP_MCLASS, 918 ARM_GRP_NOTMCLASS, 919 ARM_GRP_THUMB, 920 ARM_GRP_THUMB1ONLY, 921 ARM_GRP_THUMB2, 922 ARM_GRP_PREV8, 923 ARM_GRP_FPVMLX, 924 ARM_GRP_MULOPS, 925 ARM_GRP_CRC, 926 ARM_GRP_DPVFP, 927 ARM_GRP_V6M, 928 ARM_GRP_VIRTUALIZATION, 929 930 ARM_GRP_ENDING, 931 } arm_insn_group; 932 933 #ifdef __cplusplus 934 } 935 #endif 936 937 #endif 938