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1 /* Capstone Disassembly Engine */
2 /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3 
4 #ifndef CAPSTONE_TMS320C64X_H
5 #define CAPSTONE_TMS320C64X_H
6 
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10 
11 #include <stdint.h>
12 #include "platform.h"
13 
14 #ifdef _MSC_VER
15 #pragma warning(disable:4201)
16 #endif
17 
18 typedef enum tms320c64x_op_type {
19 	TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
20 	TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
21 	TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
22 	TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
23 	TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
24 } tms320c64x_op_type;
25 
26 typedef enum tms320c64x_mem_disp {
27 	TMS320C64X_MEM_DISP_INVALID = 0,
28 	TMS320C64X_MEM_DISP_CONSTANT,
29 	TMS320C64X_MEM_DISP_REGISTER,
30 } tms320c64x_mem_disp;
31 
32 typedef enum tms320c64x_mem_dir {
33 	TMS320C64X_MEM_DIR_INVALID = 0,
34 	TMS320C64X_MEM_DIR_FW,
35 	TMS320C64X_MEM_DIR_BW,
36 } tms320c64x_mem_dir;
37 
38 typedef enum tms320c64x_mem_mod {
39 	TMS320C64X_MEM_MOD_INVALID = 0,
40 	TMS320C64X_MEM_MOD_NO,
41 	TMS320C64X_MEM_MOD_PRE,
42 	TMS320C64X_MEM_MOD_POST,
43 } tms320c64x_mem_mod;
44 
45 typedef struct tms320c64x_op_mem {
46 	unsigned int	base;	///< base register
47 	unsigned int	disp;	///< displacement/offset value
48 	unsigned int	unit;	///< unit of base and offset register
49 	unsigned int	scaled;	///< offset scaled
50 	unsigned int	disptype;	///< displacement type
51 	unsigned int	direction;	///< direction
52 	unsigned int	modify;	///< modification
53 } tms320c64x_op_mem;
54 
55 typedef struct cs_tms320c64x_op {
56 	tms320c64x_op_type type;	///< operand type
57 	union {
58 		unsigned int reg;	///< register value for REG operand or first register for REGPAIR operand
59 		int32_t imm;		///< immediate value for IMM operand
60 		tms320c64x_op_mem mem;		///< base/disp value for MEM operand
61 	};
62 } cs_tms320c64x_op;
63 
64 typedef struct cs_tms320c64x {
65 	uint8_t op_count;
66 	cs_tms320c64x_op operands[8]; ///< operands for this instruction.
67 	struct {
68 		unsigned int reg;
69 		unsigned int zero;
70 	} condition;
71 	struct {
72 		unsigned int unit;
73 		unsigned int side;
74 		unsigned int crosspath;
75 	} funit;
76 	unsigned int parallel;
77 } cs_tms320c64x;
78 
79 typedef enum tms320c64x_reg {
80 	TMS320C64X_REG_INVALID = 0,
81 
82 	TMS320C64X_REG_AMR,
83 	TMS320C64X_REG_CSR,
84 	TMS320C64X_REG_DIER,
85 	TMS320C64X_REG_DNUM,
86 	TMS320C64X_REG_ECR,
87 	TMS320C64X_REG_GFPGFR,
88 	TMS320C64X_REG_GPLYA,
89 	TMS320C64X_REG_GPLYB,
90 	TMS320C64X_REG_ICR,
91 	TMS320C64X_REG_IER,
92 	TMS320C64X_REG_IERR,
93 	TMS320C64X_REG_ILC,
94 	TMS320C64X_REG_IRP,
95 	TMS320C64X_REG_ISR,
96 	TMS320C64X_REG_ISTP,
97 	TMS320C64X_REG_ITSR,
98 	TMS320C64X_REG_NRP,
99 	TMS320C64X_REG_NTSR,
100 	TMS320C64X_REG_REP,
101 	TMS320C64X_REG_RILC,
102 	TMS320C64X_REG_SSR,
103 	TMS320C64X_REG_TSCH,
104 	TMS320C64X_REG_TSCL,
105 	TMS320C64X_REG_TSR,
106 	TMS320C64X_REG_A0,
107 	TMS320C64X_REG_A1,
108 	TMS320C64X_REG_A2,
109 	TMS320C64X_REG_A3,
110 	TMS320C64X_REG_A4,
111 	TMS320C64X_REG_A5,
112 	TMS320C64X_REG_A6,
113 	TMS320C64X_REG_A7,
114 	TMS320C64X_REG_A8,
115 	TMS320C64X_REG_A9,
116 	TMS320C64X_REG_A10,
117 	TMS320C64X_REG_A11,
118 	TMS320C64X_REG_A12,
119 	TMS320C64X_REG_A13,
120 	TMS320C64X_REG_A14,
121 	TMS320C64X_REG_A15,
122 	TMS320C64X_REG_A16,
123 	TMS320C64X_REG_A17,
124 	TMS320C64X_REG_A18,
125 	TMS320C64X_REG_A19,
126 	TMS320C64X_REG_A20,
127 	TMS320C64X_REG_A21,
128 	TMS320C64X_REG_A22,
129 	TMS320C64X_REG_A23,
130 	TMS320C64X_REG_A24,
131 	TMS320C64X_REG_A25,
132 	TMS320C64X_REG_A26,
133 	TMS320C64X_REG_A27,
134 	TMS320C64X_REG_A28,
135 	TMS320C64X_REG_A29,
136 	TMS320C64X_REG_A30,
137 	TMS320C64X_REG_A31,
138 	TMS320C64X_REG_B0,
139 	TMS320C64X_REG_B1,
140 	TMS320C64X_REG_B2,
141 	TMS320C64X_REG_B3,
142 	TMS320C64X_REG_B4,
143 	TMS320C64X_REG_B5,
144 	TMS320C64X_REG_B6,
145 	TMS320C64X_REG_B7,
146 	TMS320C64X_REG_B8,
147 	TMS320C64X_REG_B9,
148 	TMS320C64X_REG_B10,
149 	TMS320C64X_REG_B11,
150 	TMS320C64X_REG_B12,
151 	TMS320C64X_REG_B13,
152 	TMS320C64X_REG_B14,
153 	TMS320C64X_REG_B15,
154 	TMS320C64X_REG_B16,
155 	TMS320C64X_REG_B17,
156 	TMS320C64X_REG_B18,
157 	TMS320C64X_REG_B19,
158 	TMS320C64X_REG_B20,
159 	TMS320C64X_REG_B21,
160 	TMS320C64X_REG_B22,
161 	TMS320C64X_REG_B23,
162 	TMS320C64X_REG_B24,
163 	TMS320C64X_REG_B25,
164 	TMS320C64X_REG_B26,
165 	TMS320C64X_REG_B27,
166 	TMS320C64X_REG_B28,
167 	TMS320C64X_REG_B29,
168 	TMS320C64X_REG_B30,
169 	TMS320C64X_REG_B31,
170 	TMS320C64X_REG_PCE1,
171 
172 	TMS320C64X_REG_ENDING,	// <-- mark the end of the list of registers
173 
174 	// Alias registers
175 	TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
176 	TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
177 } tms320c64x_reg;
178 
179 typedef enum tms320c64x_insn {
180 	TMS320C64X_INS_INVALID = 0,
181 
182 	TMS320C64X_INS_ABS,
183 	TMS320C64X_INS_ABS2,
184 	TMS320C64X_INS_ADD,
185 	TMS320C64X_INS_ADD2,
186 	TMS320C64X_INS_ADD4,
187 	TMS320C64X_INS_ADDAB,
188 	TMS320C64X_INS_ADDAD,
189 	TMS320C64X_INS_ADDAH,
190 	TMS320C64X_INS_ADDAW,
191 	TMS320C64X_INS_ADDK,
192 	TMS320C64X_INS_ADDKPC,
193 	TMS320C64X_INS_ADDU,
194 	TMS320C64X_INS_AND,
195 	TMS320C64X_INS_ANDN,
196 	TMS320C64X_INS_AVG2,
197 	TMS320C64X_INS_AVGU4,
198 	TMS320C64X_INS_B,
199 	TMS320C64X_INS_BDEC,
200 	TMS320C64X_INS_BITC4,
201 	TMS320C64X_INS_BNOP,
202 	TMS320C64X_INS_BPOS,
203 	TMS320C64X_INS_CLR,
204 	TMS320C64X_INS_CMPEQ,
205 	TMS320C64X_INS_CMPEQ2,
206 	TMS320C64X_INS_CMPEQ4,
207 	TMS320C64X_INS_CMPGT,
208 	TMS320C64X_INS_CMPGT2,
209 	TMS320C64X_INS_CMPGTU4,
210 	TMS320C64X_INS_CMPLT,
211 	TMS320C64X_INS_CMPLTU,
212 	TMS320C64X_INS_DEAL,
213 	TMS320C64X_INS_DOTP2,
214 	TMS320C64X_INS_DOTPN2,
215 	TMS320C64X_INS_DOTPNRSU2,
216 	TMS320C64X_INS_DOTPRSU2,
217 	TMS320C64X_INS_DOTPSU4,
218 	TMS320C64X_INS_DOTPU4,
219 	TMS320C64X_INS_EXT,
220 	TMS320C64X_INS_EXTU,
221 	TMS320C64X_INS_GMPGTU,
222 	TMS320C64X_INS_GMPY4,
223 	TMS320C64X_INS_LDB,
224 	TMS320C64X_INS_LDBU,
225 	TMS320C64X_INS_LDDW,
226 	TMS320C64X_INS_LDH,
227 	TMS320C64X_INS_LDHU,
228 	TMS320C64X_INS_LDNDW,
229 	TMS320C64X_INS_LDNW,
230 	TMS320C64X_INS_LDW,
231 	TMS320C64X_INS_LMBD,
232 	TMS320C64X_INS_MAX2,
233 	TMS320C64X_INS_MAXU4,
234 	TMS320C64X_INS_MIN2,
235 	TMS320C64X_INS_MINU4,
236 	TMS320C64X_INS_MPY,
237 	TMS320C64X_INS_MPY2,
238 	TMS320C64X_INS_MPYH,
239 	TMS320C64X_INS_MPYHI,
240 	TMS320C64X_INS_MPYHIR,
241 	TMS320C64X_INS_MPYHL,
242 	TMS320C64X_INS_MPYHLU,
243 	TMS320C64X_INS_MPYHSLU,
244 	TMS320C64X_INS_MPYHSU,
245 	TMS320C64X_INS_MPYHU,
246 	TMS320C64X_INS_MPYHULS,
247 	TMS320C64X_INS_MPYHUS,
248 	TMS320C64X_INS_MPYLH,
249 	TMS320C64X_INS_MPYLHU,
250 	TMS320C64X_INS_MPYLI,
251 	TMS320C64X_INS_MPYLIR,
252 	TMS320C64X_INS_MPYLSHU,
253 	TMS320C64X_INS_MPYLUHS,
254 	TMS320C64X_INS_MPYSU,
255 	TMS320C64X_INS_MPYSU4,
256 	TMS320C64X_INS_MPYU,
257 	TMS320C64X_INS_MPYU4,
258 	TMS320C64X_INS_MPYUS,
259 	TMS320C64X_INS_MVC,
260 	TMS320C64X_INS_MVD,
261 	TMS320C64X_INS_MVK,
262 	TMS320C64X_INS_MVKL,
263 	TMS320C64X_INS_MVKLH,
264 	TMS320C64X_INS_NOP,
265 	TMS320C64X_INS_NORM,
266 	TMS320C64X_INS_OR,
267 	TMS320C64X_INS_PACK2,
268 	TMS320C64X_INS_PACKH2,
269 	TMS320C64X_INS_PACKH4,
270 	TMS320C64X_INS_PACKHL2,
271 	TMS320C64X_INS_PACKL4,
272 	TMS320C64X_INS_PACKLH2,
273 	TMS320C64X_INS_ROTL,
274 	TMS320C64X_INS_SADD,
275 	TMS320C64X_INS_SADD2,
276 	TMS320C64X_INS_SADDU4,
277 	TMS320C64X_INS_SADDUS2,
278 	TMS320C64X_INS_SAT,
279 	TMS320C64X_INS_SET,
280 	TMS320C64X_INS_SHFL,
281 	TMS320C64X_INS_SHL,
282 	TMS320C64X_INS_SHLMB,
283 	TMS320C64X_INS_SHR,
284 	TMS320C64X_INS_SHR2,
285 	TMS320C64X_INS_SHRMB,
286 	TMS320C64X_INS_SHRU,
287 	TMS320C64X_INS_SHRU2,
288 	TMS320C64X_INS_SMPY,
289 	TMS320C64X_INS_SMPY2,
290 	TMS320C64X_INS_SMPYH,
291 	TMS320C64X_INS_SMPYHL,
292 	TMS320C64X_INS_SMPYLH,
293 	TMS320C64X_INS_SPACK2,
294 	TMS320C64X_INS_SPACKU4,
295 	TMS320C64X_INS_SSHL,
296 	TMS320C64X_INS_SSHVL,
297 	TMS320C64X_INS_SSHVR,
298 	TMS320C64X_INS_SSUB,
299 	TMS320C64X_INS_STB,
300 	TMS320C64X_INS_STDW,
301 	TMS320C64X_INS_STH,
302 	TMS320C64X_INS_STNDW,
303 	TMS320C64X_INS_STNW,
304 	TMS320C64X_INS_STW,
305 	TMS320C64X_INS_SUB,
306 	TMS320C64X_INS_SUB2,
307 	TMS320C64X_INS_SUB4,
308 	TMS320C64X_INS_SUBAB,
309 	TMS320C64X_INS_SUBABS4,
310 	TMS320C64X_INS_SUBAH,
311 	TMS320C64X_INS_SUBAW,
312 	TMS320C64X_INS_SUBC,
313 	TMS320C64X_INS_SUBU,
314 	TMS320C64X_INS_SWAP4,
315 	TMS320C64X_INS_UNPKHU4,
316 	TMS320C64X_INS_UNPKLU4,
317 	TMS320C64X_INS_XOR,
318 	TMS320C64X_INS_XPND2,
319 	TMS320C64X_INS_XPND4,
320 	// Aliases
321 	TMS320C64X_INS_IDLE,
322 	TMS320C64X_INS_MV,
323 	TMS320C64X_INS_NEG,
324 	TMS320C64X_INS_NOT,
325 	TMS320C64X_INS_SWAP2,
326 	TMS320C64X_INS_ZERO,
327 
328 	TMS320C64X_INS_ENDING,   // <-- mark the end of the list of instructions
329 } tms320c64x_insn;
330 
331 typedef enum tms320c64x_insn_group {
332 	TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
333 
334 	TMS320C64X_GRP_JUMP,	///< = CS_GRP_JUMP
335 
336 	TMS320C64X_GRP_FUNIT_D = 128,
337 	TMS320C64X_GRP_FUNIT_L,
338 	TMS320C64X_GRP_FUNIT_M,
339 	TMS320C64X_GRP_FUNIT_S,
340 	TMS320C64X_GRP_FUNIT_NO,
341 
342 	TMS320C64X_GRP_ENDING,   // <-- mark the end of the list of groups
343 } tms320c64x_insn_group;
344 
345 typedef enum tms320c64x_funit {
346 	TMS320C64X_FUNIT_INVALID = 0,
347 	TMS320C64X_FUNIT_D,
348 	TMS320C64X_FUNIT_L,
349 	TMS320C64X_FUNIT_M,
350 	TMS320C64X_FUNIT_S,
351 	TMS320C64X_FUNIT_NO
352 } tms320c64x_funit;
353 
354 #ifdef __cplusplus
355 }
356 #endif
357 
358 #endif
359 
360