1 /* 2 * Copyright (c) 2021-2023 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #include "src/core/NEON/kernels/arm_gemm/utils.hpp" 26 #include "src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp" 27 28 #include <cstdint> 29 30 #pragma once 31 32 #if defined(__aarch64__) 33 34 namespace arm_conv { 35 namespace depthwise { 36 37 void a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( 38 const unsigned int, 39 const uint8_t *const *const, 40 const uint8_t *const, 41 const int32_t *const, 42 const arm_gemm::Requantize32 &, 43 const int32_t *const, 44 const int32_t *const, 45 uint8_t *const *const); 46 47 class a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy<uint8_t, uint8_t, uint8_t, int32_t> 48 { 49 using Parent = DepthwiseDepthfirstStrategy<uint8_t, uint8_t, uint8_t, int32_t>; 50 51 public: 52 constexpr static unsigned int kernel_rows = 3; 53 constexpr static unsigned int kernel_cols = 3; 54 55 constexpr static unsigned int stride_rows = 1; 56 constexpr static unsigned int stride_cols = 1; 57 a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst(const CPUInfo *)58 a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst(const CPUInfo *) : Parent(2, 2, 3, 3, 1, 1) {} 59 get_vl_type(void) const60 arm_gemm::VLType get_vl_type(void) const override { return arm_gemm::VLType::None; } 61 62 Parent::KernelType kernel = a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl; get_kernel(void) const63 Parent::KernelType get_kernel(void) const override { return kernel; } get_accumulator_depth_vl(void) const64 unsigned int get_accumulator_depth_vl(void) const override { return 2; } 65 }; 66 67 } // namespace depthwise 68 } // namespace arm_conv 69 70 #endif // defined(__aarch64__) 71