1 /* 2 * Copyright (c) 2021-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #include "src/core/NEON/kernels/arm_gemm/utils.hpp" 26 #include "src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp" 27 28 #include <cstdint> 29 30 #pragma once 31 32 #if defined(__aarch64__) && defined(ARM_COMPUTE_ENABLE_SVE) 33 34 namespace arm_conv { 35 namespace depthwise { 36 37 void sve_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, int8_t *const *); 38 39 class sve_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy<int8_t, int8_t, int8_t, int32_t> 40 { 41 using Parent = DepthwiseDepthfirstStrategy<int8_t, int8_t, int8_t, int32_t>; 42 43 public: 44 constexpr static unsigned int kernel_rows = 5; 45 constexpr static unsigned int kernel_cols = 5; 46 47 constexpr static unsigned int stride_rows = 1; 48 constexpr static unsigned int stride_cols = 1; 49 get_vl_type(void) const50 arm_gemm::VLType get_vl_type(void) const override { return arm_gemm::VLType::SVE; } get_accumulator_depth_vl(void) const51 unsigned int get_accumulator_depth_vl(void) const override { return 2; } 52 sve_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst(const CPUInfo *)53 sve_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst(const CPUInfo *) : Parent(2, 2, 5, 5, 1, 1) {} 54 55 Parent::KernelType kernel = sve_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl; 56 get_kernel(void) const57 Parent::KernelType get_kernel(void) const override { return kernel; } 58 }; 59 60 } // namespace depthwise 61 } // namespace arm_conv 62 63 #endif // defined(__aarch64__) && defined(ARM_COMPUTE_ENABLE_SVE) 64