1 /* Copyright 2014 The Chromium OS Authors. All rights reserved. 2 * Use of this source code is governed by a BSD-style license that can be 3 * found in the LICENSE file. 4 */ 5 6 #ifndef __CROS_EC_FLASH_LAYOUT_H 7 #define __CROS_EC_FLASH_LAYOUT_H 8 9 /* 10 * The flash memory is implemented in two halves. The SoC bootrom will look for 11 * a first-stage bootloader (aka "RO firmware") at the beginning of each of the 12 * two halves and prefer the newer one if both are valid. The chosen bootloader 13 * also looks in each half of the flash for a valid application image ("RW 14 * firmware"), so we have two possible RW images as well. The RO and RW images 15 * are not tightly coupled, so either RO image can choose to boot either RW 16 * image. RO images are provided by the SoC team, and can be updated separately 17 * from the RW images. 18 */ 19 20 #define CITADEL_FLASH_BASE 0x40000 21 #define CITADEL_FLASH_SIZE (512 * 1024) 22 #define CITADEL_FLASH_HALF (CITADEL_FLASH_SIZE >> 1) 23 #define CITADEL_RO_SIZE 0x4000 24 #define CITADEL_RO_A_MEM_OFF 0 25 #define CITADEL_RO_B_MEM_OFF CITADEL_FLASH_HALF 26 #define CITADEL_RW_A_MEM_OFF CITADEL_RO_SIZE 27 #define CITADEL_RW_B_MEM_OFF (CITADEL_FLASH_HALF + CITADEL_RW_A_MEM_OFF) 28 29 #define DAUNTLESS_FLASH_BASE 0x80000 30 #define DAUNTLESS_FLASH_SIZE (1024 * 1024) 31 #define DAUNTLESS_FLASH_HALF (DAUNTLESS_FLASH_SIZE >> 1) 32 #define DAUNTLESS_RO_SIZE 0x4000 33 #define DAUNTLESS_RO_A_MEM_OFF 0 34 #define DAUNTLESS_RO_B_MEM_OFF DAUNTLESS_FLASH_HALF 35 #define DAUNTLESS_RW_A_MEM_OFF DAUNTLESS_RO_SIZE 36 #define DAUNTLESS_RW_B_MEM_OFF (DAUNTLESS_FLASH_HALF + DAUNTLESS_RW_A_MEM_OFF) 37 38 /* 39 * Citadel reserves 0x4000 bytes (16K) for its RO firmware. Dauntless can vary, 40 * but the RW firmware will follow RO and be aligned on a 16K boundary. 41 */ 42 #define FLASH_RW_ALIGNMENT 0x4000 43 44 #endif /* __CROS_EC_FLASH_LAYOUT_H */ 45