1 /*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
18 #define ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
19
20 #include <android-base/logging.h>
21
22 #include "base/macros.h"
23 #include "constants_arm.h"
24 #include "dwarf/register.h"
25 #include "offsets.h"
26 #include "utils/arm/managed_register_arm.h"
27 #include "utils/assembler.h"
28
29 // TODO(VIXL): Make VIXL compile with -Wshadow and remove pragmas.
30 #pragma GCC diagnostic push
31 #pragma GCC diagnostic ignored "-Wshadow"
32 #include "aarch32/macro-assembler-aarch32.h"
33 #pragma GCC diagnostic pop
34
35 namespace vixl32 = vixl::aarch32;
36
37 namespace art HIDDEN {
38 namespace arm {
39
DWARFReg(vixl32::Register reg)40 inline dwarf::Reg DWARFReg(vixl32::Register reg) {
41 return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode()));
42 }
43
DWARFReg(vixl32::SRegister reg)44 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) {
45 return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode()));
46 }
47
48 enum LoadOperandType {
49 kLoadSignedByte,
50 kLoadUnsignedByte,
51 kLoadSignedHalfword,
52 kLoadUnsignedHalfword,
53 kLoadWord,
54 kLoadWordPair,
55 kLoadSWord,
56 kLoadDWord
57 };
58
59 enum StoreOperandType {
60 kStoreByte,
61 kStoreHalfword,
62 kStoreWord,
63 kStoreWordPair,
64 kStoreSWord,
65 kStoreDWord
66 };
67
68 class ArmVIXLMacroAssembler final : public vixl32::MacroAssembler {
69 public:
70 // Most methods fit in a 1KB code buffer, which results in more optimal alloc/realloc and
71 // fewer system calls than a larger default capacity.
72 static constexpr size_t kDefaultCodeBufferCapacity = 1 * KB;
73
ArmVIXLMacroAssembler()74 ArmVIXLMacroAssembler()
75 : vixl32::MacroAssembler(ArmVIXLMacroAssembler::kDefaultCodeBufferCapacity) {}
76
77 // The following interfaces can generate CMP+Bcc or Cbz/Cbnz.
78 // CMP+Bcc are generated by default.
79 // If a hint is given (is_far_target = false) and rn and label can all fit into Cbz/Cbnz,
80 // then Cbz/Cbnz is generated.
81 // Prefer following interfaces to using vixl32::MacroAssembler::Cbz/Cbnz.
82 // In T32, Cbz/Cbnz instructions have following limitations:
83 // - Far targets, which are over 126 bytes away, are not supported.
84 // - Only low registers can be encoded.
85 // - Backward branches are not supported.
86 void CompareAndBranchIfZero(vixl32::Register rn,
87 vixl32::Label* label,
88 bool is_far_target = true);
89 void CompareAndBranchIfNonZero(vixl32::Register rn,
90 vixl32::Label* label,
91 bool is_far_target = true);
92
93 // In T32 some of the instructions (add, mov, etc) outside an IT block
94 // have only 32-bit encodings. But there are 16-bit flag setting
95 // versions of these instructions (adds, movs, etc). In most of the
96 // cases in ART we don't care if the instructions keep flags or not;
97 // thus we can benefit from smaller code size.
98 // VIXL will never generate flag setting versions (for example, adds
99 // for Add macro instruction) unless vixl32::DontCare option is
100 // explicitly specified. That's why we introduce wrappers to use
101 // DontCare option by default.
102 #define WITH_FLAGS_DONT_CARE_RD_RN_OP(func_name) \
103 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
104 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
105 } \
106 using MacroAssembler::func_name
107
108 WITH_FLAGS_DONT_CARE_RD_RN_OP(Adc);
109 WITH_FLAGS_DONT_CARE_RD_RN_OP(Sub);
110 WITH_FLAGS_DONT_CARE_RD_RN_OP(Sbc);
111 WITH_FLAGS_DONT_CARE_RD_RN_OP(Rsb);
112 WITH_FLAGS_DONT_CARE_RD_RN_OP(Rsc);
113
114 WITH_FLAGS_DONT_CARE_RD_RN_OP(Eor);
115 WITH_FLAGS_DONT_CARE_RD_RN_OP(Orr);
116 WITH_FLAGS_DONT_CARE_RD_RN_OP(Orn);
117 WITH_FLAGS_DONT_CARE_RD_RN_OP(And);
118 WITH_FLAGS_DONT_CARE_RD_RN_OP(Bic);
119
120 WITH_FLAGS_DONT_CARE_RD_RN_OP(Asr);
121 WITH_FLAGS_DONT_CARE_RD_RN_OP(Lsr);
122 WITH_FLAGS_DONT_CARE_RD_RN_OP(Lsl);
123 WITH_FLAGS_DONT_CARE_RD_RN_OP(Ror);
124
125 #undef WITH_FLAGS_DONT_CARE_RD_RN_OP
126
127 #define WITH_FLAGS_DONT_CARE_RD_OP(func_name) \
128 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
129 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
130 } \
131 using MacroAssembler::func_name
132
133 WITH_FLAGS_DONT_CARE_RD_OP(Mvn);
134 WITH_FLAGS_DONT_CARE_RD_OP(Mov);
135
136 #undef WITH_FLAGS_DONT_CARE_RD_OP
137
138 // The following two functions don't fall into above categories. Overload them separately.
Rrx(vixl32::Register rd,vixl32::Register rn)139 void Rrx(vixl32::Register rd, vixl32::Register rn) {
140 MacroAssembler::Rrx(vixl32::DontCare, rd, rn);
141 }
142 using MacroAssembler::Rrx;
143
Mul(vixl32::Register rd,vixl32::Register rn,vixl32::Register rm)144 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) {
145 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm);
146 }
147 using MacroAssembler::Mul;
148
149 // TODO: Remove when MacroAssembler::Add(FlagsUpdate, Condition, Register, Register, Operand)
150 // makes the right decision about 16-bit encodings.
Add(vixl32::Register rd,vixl32::Register rn,const vixl32::Operand & operand)151 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) {
152 if (rd.Is(rn) && operand.IsPlainRegister()) {
153 MacroAssembler::Add(rd, rn, operand);
154 } else {
155 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand);
156 }
157 }
158 using MacroAssembler::Add;
159
160 // These interfaces try to use 16-bit T2 encoding of B instruction.
161 void B(vixl32::Label* label);
162 // For B(label), we always try to use Narrow encoding, because 16-bit T2 encoding supports
163 // jumping within 2KB range. For B(cond, label), because the supported branch range is 256
164 // bytes; we use the far_target hint to try to use 16-bit T1 encoding for short range jumps.
165 void B(vixl32::Condition cond, vixl32::Label* label, bool is_far_target = true);
166
167 // Use literal for generating double constant if it doesn't fit VMOV encoding.
Vmov(vixl32::DRegister rd,double imm)168 void Vmov(vixl32::DRegister rd, double imm) {
169 if (vixl::VFP::IsImmFP64(imm)) {
170 MacroAssembler::Vmov(rd, imm);
171 } else {
172 MacroAssembler::Vldr(rd, imm);
173 }
174 }
175 using MacroAssembler::Vmov;
176 };
177
178 class ArmVIXLAssembler final : public Assembler {
179 private:
180 class ArmException;
181 public:
ArmVIXLAssembler(ArenaAllocator * allocator)182 explicit ArmVIXLAssembler(ArenaAllocator* allocator)
183 : Assembler(allocator) {
184 // Use Thumb2 instruction set.
185 vixl_masm_.UseT32();
186 }
187
~ArmVIXLAssembler()188 virtual ~ArmVIXLAssembler() {}
GetVIXLAssembler()189 ArmVIXLMacroAssembler* GetVIXLAssembler() { return &vixl_masm_; }
190 void FinalizeCode() override;
191
192 // Size of generated code.
193 size_t CodeSize() const override;
194 const uint8_t* CodeBufferBaseAddress() const override;
195
196 // Copy instructions out of assembly buffer into the given region of memory.
197 void FinalizeInstructions(const MemoryRegion& region) override;
198
Bind(Label * label ATTRIBUTE_UNUSED)199 void Bind(Label* label ATTRIBUTE_UNUSED) override {
200 UNIMPLEMENTED(FATAL) << "Do not use Bind(Label*) for ARM";
201 }
Jump(Label * label ATTRIBUTE_UNUSED)202 void Jump(Label* label ATTRIBUTE_UNUSED) override {
203 UNIMPLEMENTED(FATAL) << "Do not use Jump(Label*) for ARM";
204 }
205
Bind(vixl::aarch32::Label * label)206 void Bind(vixl::aarch32::Label* label) {
207 vixl_masm_.Bind(label);
208 }
Jump(vixl::aarch32::Label * label)209 void Jump(vixl::aarch32::Label* label) {
210 vixl_masm_.B(label);
211 }
212
213 //
214 // Heap poisoning.
215 //
216
217 // Poison a heap reference contained in `reg`.
218 void PoisonHeapReference(vixl32::Register reg);
219 // Unpoison a heap reference contained in `reg`.
220 void UnpoisonHeapReference(vixl32::Register reg);
221 // Poison a heap reference contained in `reg` if heap poisoning is enabled.
222 void MaybePoisonHeapReference(vixl32::Register reg);
223 // Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
224 void MaybeUnpoisonHeapReference(vixl32::Register reg);
225
226 // Emit code checking the status of the Marking Register, and aborting
227 // the program if MR does not match the value stored in the art::Thread
228 // object.
229 //
230 // Argument `temp` is used as a temporary register to generate code.
231 // Argument `code` is used to identify the different occurrences of
232 // MaybeGenerateMarkingRegisterCheck and is passed to the BKPT instruction.
233 void GenerateMarkingRegisterCheck(vixl32::Register temp, int code = 0);
234
235 void StoreToOffset(StoreOperandType type,
236 vixl32::Register reg,
237 vixl32::Register base,
238 int32_t offset);
239 void StoreSToOffset(vixl32::SRegister source, vixl32::Register base, int32_t offset);
240 void StoreDToOffset(vixl32::DRegister source, vixl32::Register base, int32_t offset);
241
242 void LoadImmediate(vixl32::Register dest, int32_t value);
243 void LoadFromOffset(LoadOperandType type,
244 vixl32::Register reg,
245 vixl32::Register base,
246 int32_t offset);
247 void LoadSFromOffset(vixl32::SRegister reg, vixl32::Register base, int32_t offset);
248 void LoadDFromOffset(vixl32::DRegister reg, vixl32::Register base, int32_t offset);
249
250 void LoadRegisterList(RegList regs, size_t stack_offset);
251 void StoreRegisterList(RegList regs, size_t stack_offset);
252
253 bool ShifterOperandCanAlwaysHold(uint32_t immediate);
254 bool ShifterOperandCanHold(Opcode opcode,
255 uint32_t immediate,
256 vixl::aarch32::FlagsUpdate update_flags = vixl::aarch32::DontCare);
257 bool CanSplitLoadStoreOffset(int32_t allowed_offset_bits,
258 int32_t offset,
259 /*out*/ int32_t* add_to_base,
260 /*out*/ int32_t* offset_for_load_store);
261 int32_t AdjustLoadStoreOffset(int32_t allowed_offset_bits,
262 vixl32::Register temp,
263 vixl32::Register base,
264 int32_t offset);
265 int32_t GetAllowedLoadOffsetBits(LoadOperandType type);
266 int32_t GetAllowedStoreOffsetBits(StoreOperandType type);
267
268 void AddConstant(vixl32::Register rd, int32_t value);
269 void AddConstant(vixl32::Register rd, vixl32::Register rn, int32_t value);
270 void AddConstantInIt(vixl32::Register rd,
271 vixl32::Register rn,
272 int32_t value,
273 vixl32::Condition cond = vixl32::al);
274
275 template <typename T>
CreateLiteralDestroyedWithPool(T value)276 vixl::aarch32::Literal<T>* CreateLiteralDestroyedWithPool(T value) {
277 vixl::aarch32::Literal<T>* literal =
278 new vixl::aarch32::Literal<T>(value,
279 vixl32::RawLiteral::kPlacedWhenUsed,
280 vixl32::RawLiteral::kDeletedOnPoolDestruction);
281 return literal;
282 }
283
284 private:
285 // VIXL assembler.
286 ArmVIXLMacroAssembler vixl_masm_;
287 };
288
289 // Thread register declaration.
290 extern const vixl32::Register tr;
291 // Marking register declaration.
292 extern const vixl32::Register mr;
293
294 } // namespace arm
295 } // namespace art
296
297 #endif // ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
298