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Searched refs:InAt (Results 1 – 24 of 24) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_vector_x86.cc78 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
86 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
92 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
98 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecReplicateScalar()
99 __ movd(tmp, locations->InAt(0).AsRegisterPairHigh<Register>()); in VisitVecReplicateScalar()
106 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
111 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
149 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecExtractScalar()
175 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
217 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecReduce()
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Dcode_generator_vector_x86_64.cc73 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
81 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
87 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
92 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ true); in VisitVecReplicateScalar()
97 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
102 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
137 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecExtractScalar()
158 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
200 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecReduce()
246 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecCnv()
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Dcode_generator_vector_arm_vixl.cc94 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
136 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecReduce()
173 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNeg()
202 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecAbs()
229 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNot()
276 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecAdd()
277 vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); in VisitVecAdd()
306 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecSaturationAdd()
307 vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); in VisitVecSaturationAdd()
338 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecHalvingAdd()
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Dcode_generator_vector_arm64_neon.cc112 Location src_loc = locations->InAt(0); in VisitVecReplicateScalar()
198 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
212 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
253 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecReduce()
293 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecCnv()
311 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecNeg()
352 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecAbs()
391 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecNot()
442 VRegister lhs = VRegisterFrom(locations->InAt(0)); in VisitVecAdd()
443 VRegister rhs = VRegisterFrom(locations->InAt(1)); in VisitVecAdd()
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Dcode_generator_vector_arm64_sve.cc112 Location src_loc = locations->InAt(0); in VisitVecReplicateScalar()
194 const VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
205 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
247 const ZRegister src = ZRegisterFrom(locations->InAt(0)); in VisitVecReduce()
285 const ZRegister src = ZRegisterFrom(locations->InAt(0)); in VisitVecCnv()
305 const ZRegister src = ZRegisterFrom(locations->InAt(0)); in VisitVecNeg()
343 const ZRegister src = ZRegisterFrom(locations->InAt(0)); in VisitVecAbs()
379 const ZRegister src = ZRegisterFrom(locations->InAt(0)); in VisitVecNot()
438 const ZRegister lhs = ZRegisterFrom(locations->InAt(0)); in VisitVecAdd()
439 const ZRegister rhs = ZRegisterFrom(locations->InAt(1)); in VisitVecAdd()
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Dintrinsics_x86.cc95 Register src = locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
96 Location src_pos = locations->InAt(1); in EmitNativeCode()
97 Register dest = locations->InAt(2).AsRegister<Register>(); in EmitNativeCode()
98 Location dest_pos = locations->InAt(3); in EmitNativeCode()
99 Location length = locations->InAt(4); in EmitNativeCode()
192 Location input = locations->InAt(0); in MoveFPToInt()
207 Location input = locations->InAt(0); in MoveIntToFP()
305 Location input = locations->InAt(0); in VisitLongReverseBytes()
341 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitMathSqrt()
361 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in GenSSE41FPToFPIntrinsic()
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Dintrinsics_x86_64.cc141 Location input = locations->InAt(0); in MoveFPToInt()
147 Location input = locations->InAt(0); in MoveIntToFP()
216 XmmRegister input = locations->InAt(0).AsFpuRegister<XmmRegister>(); in GenIsInfinite()
285 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitMathSqrt()
305 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in GenSSE41FPToFPIntrinsic()
358 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitMathRoundFloat()
399 XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitMathRoundDouble()
724 CpuRegister src = locations->InAt(0).AsRegister<CpuRegister>(); in SystemArrayCopyPrimitive()
725 Location src_pos = locations->InAt(1); in SystemArrayCopyPrimitive()
726 CpuRegister dest = locations->InAt(2).AsRegister<CpuRegister>(); in SystemArrayCopyPrimitive()
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Dcode_generator_x86.cc158 Location index_loc = locations->InAt(0); in EmitNativeCode()
159 Location length_loc = locations->InAt(1); in EmitNativeCode()
170 Location array_loc = array_length->GetLocations()->InAt(0); in EmitNativeCode()
329 Location source = instruction_->IsLoadClass() ? out : locations->InAt(0); in EmitNativeCode()
372 __ UnpoisonHeapReference(locations->InAt(1).AsRegister<Register>()); in EmitNativeCode()
382 x86_codegen->EmitParallelMoves(locations->InAt(0), in EmitNativeCode()
385 locations->InAt(1), in EmitNativeCode()
458 locations->InAt(0), in EmitNativeCode()
463 locations->InAt(1), in EmitNativeCode()
468 locations->InAt(2), in EmitNativeCode()
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Dcommon_arm.h112 return SRegisterFrom(instr->GetLocations()->InAt(input_index)); in InputSRegisterAt()
118 return DRegisterFrom(instr->GetLocations()->InAt(input_index)); in InputDRegisterAt()
141 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
200 return OperandFrom(instr->GetLocations()->InAt(input_index), in InputOperandAt()
Dintrinsics_arm64.cc186 Location input = locations->InAt(0); in MoveFPToInt()
193 Location input = locations->InAt(0); in MoveIntToFP()
286 Location in = locations->InAt(0); in GenReverseBytes()
320 Location in = locations->InAt(0); in GenNumberOfLeadingZeros()
347 Location in = locations->InAt(0); in GenNumberOfTrailingZeros()
375 Location in = locations->InAt(0); in GenReverse()
506 __ Fsqrt(DRegisterFrom(locations->Out()), DRegisterFrom(locations->InAt(0))); in VisitMathSqrt()
516 __ Frintp(DRegisterFrom(locations->Out()), DRegisterFrom(locations->InAt(0))); in VisitMathCeil()
526 __ Frintm(DRegisterFrom(locations->Out()), DRegisterFrom(locations->InAt(0))); in VisitMathFloor()
536 __ Frintn(DRegisterFrom(locations->Out()), DRegisterFrom(locations->InAt(0))); in VisitMathRint()
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Dcode_generator_x86_64.cc209 Location index_loc = locations->InAt(0); in EmitNativeCode()
210 Location length_loc = locations->InAt(1); in EmitNativeCode()
221 Location array_loc = array_length->GetLocations()->InAt(0); in EmitNativeCode()
307 Location source = instruction_->IsLoadClass() ? out : locations->InAt(0); in EmitNativeCode()
384 __ UnpoisonHeapReference(locations->InAt(1).AsRegister<CpuRegister>()); in EmitNativeCode()
394 codegen->EmitParallelMoves(locations->InAt(0), in EmitNativeCode()
397 locations->InAt(1), in EmitNativeCode()
465 locations->InAt(0), in EmitNativeCode()
470 locations->InAt(1), in EmitNativeCode()
475 locations->InAt(2), in EmitNativeCode()
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Dcode_generator_arm_vixl.cc489 locations->InAt(0), in EmitNativeCode()
492 locations->InAt(1), in EmitNativeCode()
548 Location source = instruction_->IsLoadClass() ? out : locations->InAt(0); in EmitNativeCode()
628 codegen->EmitParallelMoves(locations->InAt(0), in EmitNativeCode()
631 locations->InAt(1), in EmitNativeCode()
702 locations->InAt(0), in EmitNativeCode()
707 locations->InAt(1), in EmitNativeCode()
712 locations->InAt(2), in EmitNativeCode()
1200 const Location first = locations->InAt(0); in GenerateLongDataProc()
1201 const Location second = locations->InAt(1); in GenerateLongDataProc()
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Dssa_liveness_analysis.h147 Location location = GetUser()->GetLocations()->InAt(GetInputIndex()); in RequiresRegister()
334 } else if (!locations->InAt(input_index).IsValid()) {
965 && (locations->InAt(0).IsRegister() in DefinitionRequiresRegister()
966 || locations->InAt(0).IsRegisterPair() in DefinitionRequiresRegister()
967 || locations->InAt(0).GetPolicy() == Location::kRequiresRegister))) { in DefinitionRequiresRegister()
971 && (locations->InAt(0).IsFpuRegister() in DefinitionRequiresRegister()
972 || locations->InAt(0).IsFpuRegisterPair() in DefinitionRequiresRegister()
973 || locations->InAt(0).GetPolicy() == Location::kRequiresFpuRegister))) { in DefinitionRequiresRegister()
Dintrinsics_arm_vixl.cc142 Location dest_pos = locations->InAt(3); in EmitNativeCode()
225 Location input = locations->InAt(0); in MoveFPToInt()
235 Location input = locations->InAt(0); in MoveIntToFP()
307 Location in = locations->InAt(0); in GenNumberOfLeadingZeros()
355 vixl32::Register in_reg_lo = LowRegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
356 vixl32::Register in_reg_hi = HighRegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
369 vixl32::Register in = RegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
470 __ Ldrsb(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekByte()
480 __ Ldr(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekIntNative()
490 vixl32::Register addr = LowRegisterFrom(invoke->GetLocations()->InAt(0)); in VisitMemoryPeekLongNative()
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Dcommon_arm64.h87 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
131 return FPRegisterFrom(instr->GetLocations()->InAt(input_index), in InputFPRegisterAt()
178 return OperandFrom(instr->GetLocations()->InAt(input_index), in InputOperandAt()
Dssa_liveness_analysis.cc112 bool has_in_location = current->GetLocations()->InAt(i).IsValid(); in RecursivelyProcessInputs()
225 DCHECK(!user->GetLocations()->InAt(index).IsValid()); in ComputeLiveRanges()
418 Location expected = locations->InAt(use.GetInputIndex()); in FindFirstRegisterHint()
Dcode_generator_arm64.cc222 codegen->EmitParallelMoves(locations->InAt(0), in EmitNativeCode()
225 locations->InAt(1), in EmitNativeCode()
300 Location source = instruction_->IsLoadClass() ? out : locations->InAt(0); in EmitNativeCode()
450 codegen->EmitParallelMoves(locations->InAt(0), in EmitNativeCode()
453 locations->InAt(1), in EmitNativeCode()
518 locations->InAt(0), in EmitNativeCode()
523 locations->InAt(1), in EmitNativeCode()
528 locations->InAt(2), in EmitNativeCode()
2194 Location base_loc = locations->InAt(receiver_input); in HandleFieldGet()
2341 __ Ror(dst, lhs, RegisterFrom(instr->GetLocations()->InAt(1), type)); in HandleBinaryOp()
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Dregister_allocation_resolver.cc133 if (locations->InAt(0).IsUnallocated()) { in Resolve()
136 DCHECK(locations->InAt(0).Equals(source)); in Resolve()
342 Location expected_location = locations->InAt(use.GetInputIndex()); in ConnectSiblings()
Dintrinsics.h94 Location actual_loc = locations->InAt(i); in INTRINSICS_LIST()
Dcode_generator.cc115 DCHECK(CheckType(instruction->GetType(), locations->InAt(0))) in CheckTypeConsistency()
117 << " " << locations->InAt(0); in CheckTypeConsistency()
126 DCHECK(CheckType(inputs[i]->GetType(), locations->InAt(i))) in CheckTypeConsistency()
127 << inputs[i]->GetType() << " " << locations->InAt(i); in CheckTypeConsistency()
545 Location in_location = locations->InAt(i); in PrepareCriticalNativeArgumentMoves()
783 locations->InAt(is_instance ? 1 : 0), in GenerateUnresolvedFieldAccess()
Dregister_allocator_linear_scan.cc355 Location input = locations->InAt(i); in CheckForFixedInputs()
404 Location first = locations->InAt(0); in CheckForFixedOutput()
675 if (locations->InAt(i).IsValid()) { in TryAllocateFreeReg()
Dlocations.h552 Location InAt(uint32_t at) const { in InAt() function
Dregister_allocator_graph_color.cc890 Location input = locations->InAt(i); in CheckForFixedInputs()
913 out = instruction->GetLocations()->InAt(0); in CheckForFixedOutput()
1446 Location input = locations->InAt(use.GetInputIndex()); in FindCoalesceOpportunities()
Dgraph_visualizer.cc719 DumpLocation(input_list.NewEntryStream(), locations->InAt(i)); in PrintInstruction()