Home
last modified time | relevance | path

Searched refs:R0 (Results 1 – 8 of 8) sorted by relevance

/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc32 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST()
38 EXPECT_EQ(R0, reg.AsCoreRegister()); in TEST()
236 EXPECT_EQ(R0, reg.AsRegisterPairLow()); in TEST()
238 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R0))); in TEST()
293 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromCoreRegister(R0))); in TEST()
299 ArmManagedRegister reg_R0 = ArmManagedRegister::FromCoreRegister(R0); in TEST()
301 EXPECT_TRUE(reg_R0.Equals(ArmManagedRegister::FromCoreRegister(R0))); in TEST()
309 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromCoreRegister(R0))); in TEST()
319 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromCoreRegister(R0))); in TEST()
329 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromCoreRegister(R0))); in TEST()
[all …]
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc36 R0, R1, R2, R3
47 ArmManagedRegister::FromCoreRegister(R0),
176 return ArmManagedRegister::FromCoreRegister(R0); in ReturnRegister()
188 return ArmManagedRegister::FromCoreRegister(R0); in ReturnRegister()
193 return ArmManagedRegister::FromCoreRegister(R0); in IntReturnRegister()
199 return ArmManagedRegister::FromCoreRegister(R0); in MethodRegister()
413 static_assert(kHFCoreArgumentRegisters[0].Equals(ArmManagedRegister::FromCoreRegister(R0))); in ArgumentScratchRegisters()
/art/runtime/arch/arm/
Dregisters_arm.cc29 if (rhs >= R0 && rhs <= PC) { in operator <<()
Dcontext_arm.cc34 gprs_[R0] = &arg0_; in Reset()
77 gprs_[R0] = const_cast<uint32_t*>(&gZero); in SmashCallerSaves()
Dregisters_arm.h27 R0 = 0, enumerator
Dcontext_arm.h54 SetGPR(R0, new_arg0_value); in SetArg0()
Dcallee_save_frame_arm.h41 (1 << art::arm::R0) | (1 << art::arm::R1) | (1 << art::arm::R2) | (1 << art::arm::R3) |
/art/compiler/utils/
Dassembler_thumb_test.cc121 const ManagedRegister method_register = ArmManagedRegister::FromCoreRegister(R0); in TEST_F()
252 #define R0 vixl::aarch32::r0 macro
281 __ LoadFromOffset(kLoadWord, R0, R12, 12); // 32-bit because of R12. in TEST_F()
314 __ StoreToOffset(kStoreWord, R0, R12, 12); // 32-bit because of R12. in TEST_F()