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Searched refs:vixl32 (Results 1 – 11 of 11) sorted by relevance

/art/compiler/utils/arm/
Dassembler_arm_vixl.h35 namespace vixl32 = vixl::aarch32; variable
40 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
44 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg()
68 class ArmVIXLMacroAssembler final : public vixl32::MacroAssembler {
75 : vixl32::MacroAssembler(ArmVIXLMacroAssembler::kDefaultCodeBufferCapacity) {} in ArmVIXLMacroAssembler()
86 void CompareAndBranchIfZero(vixl32::Register rn,
87 vixl32::Label* label,
89 void CompareAndBranchIfNonZero(vixl32::Register rn,
90 vixl32::Label* label,
103 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
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Dassembler_arm_vixl.cc39 extern const vixl32::Register tr(TR);
41 extern const vixl32::Register mr(MR);
71 void ArmVIXLAssembler::MaybePoisonHeapReference(vixl32::Register reg) { in MaybePoisonHeapReference()
77 void ArmVIXLAssembler::MaybeUnpoisonHeapReference(vixl32::Register reg) { in MaybeUnpoisonHeapReference()
83 void ArmVIXLAssembler::GenerateMarkingRegisterCheck(vixl32::Register temp, int code) { in GenerateMarkingRegisterCheck()
86 vixl32::Label mr_is_ok; in GenerateMarkingRegisterCheck()
97 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate()
146 vixl32::Register temp, in AdjustLoadStoreOffset()
147 vixl32::Register base, in AdjustLoadStoreOffset()
243 vixl32::Register reg, in StoreToOffset()
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Djni_macro_assembler_arm_vixl.cc28 namespace vixl32 = vixl::aarch32;
122 ___ Vpush(SRegisterList(vixl32::SRegister(first), POPCOUNT(fp_spill_mask))); in BuildFrame()
193 ___ Vpop(SRegisterList(vixl32::SRegister(first), POPCOUNT(fp_spill_mask))); in RemoveFrame()
207 vixl32::Register reg(WhichPowerOf2(core_spill_mask)); in RemoveFrame()
237 vixl32::Register temp = temps.Acquire(); in RemoveFrame()
249 ___ Bx(vixl32::lr); in RemoveFrame()
339 vixl32::Register reg = temps.Acquire(); in StoreStackPointerToThread()
518 ___ Vstr(vixl32::DRegister(sreg / 2u), MemOperand(sp, frame_offset)); in MoveArguments()
521 vixl32::Register base_reg; in MoveArguments()
542 DRegisterList dreg_list(vixl32::DRegister(start_sreg / 2u), dreg_count); in MoveArguments()
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Djni_macro_assembler_arm_vixl.h148 void Load(ArmManagedRegister dest, vixl32::Register base, int32_t offset, size_t size);
167 vixl32::Label,
170 vixl32::Label* AsArm() { in AsArm()
/art/compiler/optimizing/
Dintrinsics_arm_vixl.cc77 const vixl32::Register& array, in GenSystemArrayCopyBaseAddress()
79 const vixl32::Register& base) { in GenSystemArrayCopyBaseAddress()
92 __ Add(base, array, Operand(RegisterFrom(pos), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress()
101 const vixl32::Register& base, in GenSystemArrayCopyEndAddress()
102 const vixl32::Register& end) { in GenSystemArrayCopyEndAddress()
114 __ Add(end, base, Operand(RegisterFrom(copy_length), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyEndAddress()
141 vixl32::Register dest = InputRegisterAt(instruction_, 2); in EmitNativeCode()
143 vixl32::Register src_curr_addr = RegisterFrom(locations->GetTemp(0)); in EmitNativeCode()
144 vixl32::Register dst_curr_addr = RegisterFrom(locations->GetTemp(1)); in EmitNativeCode()
145 vixl32::Register src_stop_addr = RegisterFrom(locations->GetTemp(2)); in EmitNativeCode()
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Dcode_generator_vector_arm_vixl.cc20 namespace vixl32 = vixl::aarch32;
21 using namespace vixl32; // NOLINT(build/namespaces)
56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
94 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
136 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecReduce()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
173 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNeg()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg()
202 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecAbs()
203 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs()
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Dcode_generator_arm_vixl.cc51 namespace vixl32 = vixl::aarch32;
52 using namespace vixl32; // NOLINT(build/namespaces)
80 using RegisterList = vixl32::RegisterList;
111 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { in CanEmitNarrowLdr()
117 EmitAdrCode(ArmVIXLMacroAssembler* assembler, vixl32::Register rd, vixl32::Label* label) in EmitAdrCode()
140 vixl32::Register rd_;
141 vixl32::Label* const label_;
182 __ Vstr(vixl32::SRegister(first), MemOperand(sp, stack_offset)); in SaveContiguousSRegisterList()
186 __ Vstr(vixl32::SRegister(first++), MemOperand(sp, stack_offset)); in SaveContiguousSRegisterList()
197 vixl32::DRegister d_reg = vixl32::DRegister(first / 2); in SaveContiguousSRegisterList()
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Doptimizing_cfi_test.cc34 namespace vixl32 = vixl::aarch32;
197 using vixl32::r0; in TEST_ISA()
207 vixl32::Label target; in TEST_ISA()
211 __ Ldr(r0, vixl32::MemOperand(r0)); in TEST_ISA()
Dcode_generator_arm_vixl.h189 VIXLInt32Literal *lit = new VIXLInt32Literal(0, vixl32::RawLiteral::kManuallyPlaced); in JumpTableARMVIXL()
338 void Exchange(vixl32::Register reg, int mem);
416 vixl32::Register class_reg);
503 /*out*/ vixl32::Register* scratch);
508 /*out*/ vixl32::Register* scratch);
617 vixl32::Label* GetFinalLabel(HInstruction* instruction, vixl32::Label* final_label);
861 vixl::aarch32::Register temp = vixl32::Register());
872 void MaybeGenerateInlineCacheCheck(HInstruction* instruction, vixl32::Register klass);
Dscheduler_arm.cc334 SBC, High32Bits(value + 1), vixl32::FlagsUpdate::SetFlags)) { in CanGenerateTest()
338 SBC, High32Bits(value), vixl32::FlagsUpdate::SetFlags)) { in CanGenerateTest()
/art/test/642-fp-callees/
Dinfo.txt1 Regression test for vixl32 backend, which used to incorrectly