1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ARM_KVM_H__ 20 #define __ARM_KVM_H__ 21 #define KVM_SPSR_EL1 0 22 #define KVM_SPSR_SVC KVM_SPSR_EL1 23 #define KVM_SPSR_ABT 1 24 #define KVM_SPSR_UND 2 25 #define KVM_SPSR_IRQ 3 26 #define KVM_SPSR_FIQ 4 27 #define KVM_NR_SPSR 5 28 #ifndef __ASSEMBLY__ 29 #include <linux/psci.h> 30 #include <linux/types.h> 31 #include <asm/ptrace.h> 32 #include <asm/sve_context.h> 33 #define __KVM_HAVE_GUEST_DEBUG 34 #define __KVM_HAVE_IRQ_LINE 35 #define __KVM_HAVE_READONLY_MEM 36 #define __KVM_HAVE_VCPU_EVENTS 37 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 38 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 39 #define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 40 struct kvm_regs { 41 struct user_pt_regs regs; 42 __u64 sp_el1; 43 __u64 elr_el1; 44 __u64 spsr[KVM_NR_SPSR]; 45 struct user_fpsimd_state fp_regs; 46 }; 47 #define KVM_ARM_TARGET_AEM_V8 0 48 #define KVM_ARM_TARGET_FOUNDATION_V8 1 49 #define KVM_ARM_TARGET_CORTEX_A57 2 50 #define KVM_ARM_TARGET_XGENE_POTENZA 3 51 #define KVM_ARM_TARGET_CORTEX_A53 4 52 #define KVM_ARM_TARGET_GENERIC_V8 5 53 #define KVM_ARM_NUM_TARGETS 6 54 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 55 #define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, KVM_ARM_DEVICE_TYPE_SHIFT) 56 #define KVM_ARM_DEVICE_ID_SHIFT 16 57 #define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, KVM_ARM_DEVICE_ID_SHIFT) 58 #define KVM_ARM_DEVICE_VGIC_V2 0 59 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 60 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 61 #define KVM_VGIC_V2_DIST_SIZE 0x1000 62 #define KVM_VGIC_V2_CPU_SIZE 0x2000 63 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 64 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 65 #define KVM_VGIC_ITS_ADDR_TYPE 4 66 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 67 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 68 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 69 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 70 #define KVM_ARM_VCPU_POWER_OFF 0 71 #define KVM_ARM_VCPU_EL1_32BIT 1 72 #define KVM_ARM_VCPU_PSCI_0_2 2 73 #define KVM_ARM_VCPU_PMU_V3 3 74 #define KVM_ARM_VCPU_SVE 4 75 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 76 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 77 struct kvm_vcpu_init { 78 __u32 target; 79 __u32 features[7]; 80 }; 81 struct kvm_sregs { 82 }; 83 struct kvm_fpu { 84 }; 85 #define KVM_ARM_MAX_DBG_REGS 16 86 struct kvm_guest_debug_arch { 87 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 88 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 89 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 90 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 91 }; 92 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 93 struct kvm_debug_exit_arch { 94 __u32 hsr; 95 __u32 hsr_high; 96 __u64 far; 97 }; 98 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 99 #define KVM_GUESTDBG_USE_HW (1 << 17) 100 struct kvm_sync_regs { 101 __u64 device_irq_level; 102 }; 103 struct kvm_pmu_event_filter { 104 __u16 base_event; 105 __u16 nevents; 106 #define KVM_PMU_EVENT_ALLOW 0 107 #define KVM_PMU_EVENT_DENY 1 108 __u8 action; 109 __u8 pad[3]; 110 }; 111 struct kvm_vcpu_events { 112 struct { 113 __u8 serror_pending; 114 __u8 serror_has_esr; 115 __u8 ext_dabt_pending; 116 __u8 pad[5]; 117 __u64 serror_esr; 118 } exception; 119 __u32 reserved[12]; 120 }; 121 struct kvm_arm_copy_mte_tags { 122 __u64 guest_ipa; 123 __u64 length; 124 void * addr; 125 __u64 flags; 126 __u64 reserved[2]; 127 }; 128 #define KVM_ARM_TAGS_TO_GUEST 0 129 #define KVM_ARM_TAGS_FROM_GUEST 1 130 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 131 #define KVM_REG_ARM_COPROC_SHIFT 16 132 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 133 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 134 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 135 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 136 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 137 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 138 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 139 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 140 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 141 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 142 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 143 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 144 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 145 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 146 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 147 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 148 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 149 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 150 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 151 #define ARM64_SYS_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM64_SYSREG_ ##n ##_SHIFT) & KVM_REG_ARM64_SYSREG_ ##n ##_MASK) 152 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 153 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 154 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 155 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 156 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 157 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 158 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 159 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 160 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 161 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_FW | ((r) & 0xffff)) 162 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 163 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 164 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 165 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 166 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 167 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 168 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 169 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 170 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 171 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 172 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 173 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 174 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 175 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 176 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 177 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 178 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 179 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 180 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 181 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 182 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 183 #define KVM_ARM64_SVE_MAX_SLICES 32 184 #define KVM_REG_ARM64_SVE_ZREG(n,i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | KVM_REG_SIZE_U2048 | (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 185 #define KVM_REG_ARM64_SVE_PREG(n,i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | KVM_REG_SIZE_U256 | (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 186 #define KVM_REG_ARM64_SVE_FFR(i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | KVM_REG_SIZE_U256 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 187 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 188 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 189 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_SIZE_U512 | 0xffff) 190 #define KVM_ARM64_SVE_VLS_WORDS ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 191 #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 192 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_FW_FEAT_BMAP | ((r) & 0xffff)) 193 #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 194 enum { 195 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 196 }; 197 #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 198 enum { 199 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 200 }; 201 #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 202 enum { 203 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 204 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 205 }; 206 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 207 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 208 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 209 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 210 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 211 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 212 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 213 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 214 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 215 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 216 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 217 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 218 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 219 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 220 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 221 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 222 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 223 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 224 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 225 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 226 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 227 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 228 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 229 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 230 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 231 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 232 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 233 #define KVM_ARM_VCPU_PMU_V3_INIT 1 234 #define KVM_ARM_VCPU_PMU_V3_FILTER 2 235 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 236 #define KVM_ARM_VCPU_TIMER_CTRL 1 237 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 238 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 239 #define KVM_ARM_VCPU_PVTIME_CTRL 2 240 #define KVM_ARM_VCPU_PVTIME_IPA 0 241 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 242 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 243 #define KVM_ARM_IRQ_TYPE_SHIFT 24 244 #define KVM_ARM_IRQ_TYPE_MASK 0xf 245 #define KVM_ARM_IRQ_VCPU_SHIFT 16 246 #define KVM_ARM_IRQ_VCPU_MASK 0xff 247 #define KVM_ARM_IRQ_NUM_SHIFT 0 248 #define KVM_ARM_IRQ_NUM_MASK 0xffff 249 #define KVM_ARM_IRQ_TYPE_CPU 0 250 #define KVM_ARM_IRQ_TYPE_SPI 1 251 #define KVM_ARM_IRQ_TYPE_PPI 2 252 #define KVM_ARM_IRQ_CPU_IRQ 0 253 #define KVM_ARM_IRQ_CPU_FIQ 1 254 #define KVM_ARM_IRQ_GIC_MAX 127 255 #define KVM_NR_IRQCHIPS 1 256 #define KVM_PSCI_FN_BASE 0x95c1ba5e 257 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 258 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 259 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 260 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 261 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 262 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 263 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 264 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 265 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 266 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 267 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 268 #endif 269 #endif 270