| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_rescale_subbandsamples.s | 114 BICS R7, R3, #1
162 BICS R7, R3, #1
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 818 BICS r3, r2, r1 // Must be wide - 3 distinct registers
819 BICS r2, r2, r1 // Should choose narrow
820 BICS r1, r2, r1 // Should choose wide - not commutative
821 BICS.W r2, r2, r1 // Explicitly wide
822 BICS.W r0, r1, r0
824 BICS r7, r7, r1 // Should use narrow
825 BICS r8, r1, r8 // high registers so must use wide encoding
826 BICS r8, r8, r1
827 BICS r7, r8, r7
828 BICS r5, r5, r8
[all …]
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| D | basic-thumb-instructions.s | 160 @ BICS
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 72 "Bics", // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
73 // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-const-a32.json | 39 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 45 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 42 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 42 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 47 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 309 "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
314 "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
318 "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi",
322 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 83 # BICS
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 744 LogicalMacro(rd, rn, operand, BICS); in Bics()
830 case BICS: in LogicalMacro()
849 case BICS: in LogicalMacro()
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| D | constants-aarch64.h | 746 BICS = ANDS | NOT enumerator
790 BICS_w = LogicalShiftedFixed | BICS,
791 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
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| D | assembler-aarch64.cc | 610 Logical(rd, rn, operand, BICS); in bics()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 426 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
448 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
467 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
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| D | AArch64InstrInfo.td | 1585 defm BICS : LogicalRegS<0b11, 1, "bics",
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 291 ### BICS ### subsection
6586 ### BICS ### subsection
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | ptmv1_0x13.txt | 4702 Instruction 4553 S:0xC0015462 0xF0334180 0 BICS r1,r3,#0x40000000 false
4735 Instruction 4582 S:0xC00154C8 0xEA320224 0 BICS r2,r2,r4,ASR #32 false
8609 Instruction 8316 S:0xC00388CE 0xEA310121 0 BICS r1,r1,r1,ASR #32 false
8685 Instruction 8390 S:0xC002E736 0xF0334280 0 BICS r2,r3,#0x40000000 false
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| D | etmv3_0x10.txt | 379 Instruction 351 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
569 Instruction 531 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
5338 Instruction 5109 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
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| D | etmv3_0x11.txt | 5169 Instruction 5007 S:0xC00459A2 0xF0320602 2 BICS r6,r2,#2 false
6048 Instruction 5857 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
6184 Instruction 5981 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 901 defm BICS : LogicalRegS<0b11, 1, "bics",
|