1 /* Copyright 2001 Sun Microsystems (thockin@sun.com) */
2 #include <stdio.h>
3 #include "internal.h"
4
5 #define PCI_VENDOR_NATSEMI 0x100b
6 #define PCI_DEVICE_DP83815 0x0020
7 #define NATSEMI_MAGIC (PCI_VENDOR_NATSEMI | \
8 (PCI_DEVICE_DP83815<<16))
9
10 /* register indices in the ethtool_regs->data */
11 #define REG_CR 0
12 #define BIT_CR_TXE (1<<0)
13 #define BIT_CR_RXE (1<<2)
14 #define BIT_CR_RST (1<<8)
15 #define REG_CFG 1
16 #define BIT_CFG_BEM (1<<0)
17 #define BIT_CFG_BROM_DIS (1<<2)
18 #define BIT_CFG_PHY_DIS (1<<9)
19 #define BIT_CFG_PHY_RST (1<<10)
20 #define BIT_CFG_EXT_PHY (1<<12)
21 #define BIT_CFG_ANEG_EN (1<<13)
22 #define BIT_CFG_ANEG_100 (1<<14)
23 #define BIT_CFG_ANEG_FDUP (1<<15)
24 #define BIT_CFG_PINT_ACEN (1<<17)
25 #define BIT_CFG_PHY_CFG (0x3f<<18)
26 #define BIT_CFG_ANEG_DN (1<<27)
27 #define BIT_CFG_POL (1<<28)
28 #define BIT_CFG_FDUP (1<<29)
29 #define BIT_CFG_SPEED100 (1<<30)
30 #define BIT_CFG_LNKSTS (1<<31)
31
32 #define REG_MEAR 2
33 #define REG_PTSCR 3
34 #define BIT_PTSCR_EEBIST_FAIL (1<<0)
35 #define BIT_PTSCR_EELOAD_EN (1<<2)
36 #define BIT_PTSCR_RBIST_RXFFAIL (1<<3)
37 #define BIT_PTSCR_RBIST_TXFAIL (1<<4)
38 #define BIT_PTSCR_RBIST_RXFAIL (1<<5)
39 #define REG_ISR 4
40 #define REG_IMR 5
41 #define BIT_INTR_RXOK (1<<0)
42 #define NAME_INTR_RXOK "Rx Complete"
43 #define BIT_INTR_RXDESC (1<<1)
44 #define NAME_INTR_RXDESC "Rx Descriptor"
45 #define BIT_INTR_RXERR (1<<2)
46 #define NAME_INTR_RXERR "Rx Packet Error"
47 #define BIT_INTR_RXEARLY (1<<3)
48 #define NAME_INTR_RXEARLY "Rx Early Threshold"
49 #define BIT_INTR_RXIDLE (1<<4)
50 #define NAME_INTR_RXIDLE "Rx Idle"
51 #define BIT_INTR_RXORN (1<<5)
52 #define NAME_INTR_RXORN "Rx Overrun"
53 #define BIT_INTR_TXOK (1<<6)
54 #define NAME_INTR_TXOK "Tx Packet OK"
55 #define BIT_INTR_TXDESC (1<<7)
56 #define NAME_INTR_TXDESC "Tx Descriptor"
57 #define BIT_INTR_TXERR (1<<8)
58 #define NAME_INTR_TXERR "Tx Packet Error"
59 #define BIT_INTR_TXIDLE (1<<9)
60 #define NAME_INTR_TXIDLE "Tx Idle"
61 #define BIT_INTR_TXURN (1<<10)
62 #define NAME_INTR_TXURN "Tx Underrun"
63 #define BIT_INTR_MIB (1<<11)
64 #define NAME_INTR_MIB "MIB Service"
65 #define BIT_INTR_SWI (1<<12)
66 #define NAME_INTR_SWI "Software"
67 #define BIT_INTR_PME (1<<13)
68 #define NAME_INTR_PME "Power Management Event"
69 #define BIT_INTR_PHY (1<<14)
70 #define NAME_INTR_PHY "Phy"
71 #define BIT_INTR_HIBERR (1<<15)
72 #define NAME_INTR_HIBERR "High Bits Error"
73 #define BIT_INTR_RXSOVR (1<<16)
74 #define NAME_INTR_RXSOVR "Rx Status FIFO Overrun"
75 #define BIT_INTR_RTABT (1<<20)
76 #define NAME_INTR_RTABT "Received Target Abort"
77 #define BIT_INTR_RMABT (1<<20)
78 #define NAME_INTR_RMABT "Received Master Abort"
79 #define BIT_INTR_SSERR (1<<20)
80 #define NAME_INTR_SSERR "Signaled System Error"
81 #define BIT_INTR_DPERR (1<<20)
82 #define NAME_INTR_DPERR "Detected Parity Error"
83 #define BIT_INTR_RXRCMP (1<<20)
84 #define NAME_INTR_RXRCMP "Rx Reset Complete"
85 #define BIT_INTR_TXRCMP (1<<20)
86 #define NAME_INTR_TXRCMP "Tx Reset Complete"
87 #define REG_IER 6
88 #define BIT_IER_IE (1<<0)
89 #define REG_TXDP 8
90 #define REG_TXCFG 9
91 #define BIT_TXCFG_DRTH (0x3f<<0)
92 #define BIT_TXCFG_FLTH (0x3f<<8)
93 #define BIT_TXCFG_MXDMA (0x7<<20)
94 #define BIT_TXCFG_ATP (1<<28)
95 #define BIT_TXCFG_MLB (1<<29)
96 #define BIT_TXCFG_HBI (1<<30)
97 #define BIT_TXCFG_CSI (1<<31)
98 #define REG_RXDP 12
99 #define REG_RXCFG 13
100 #define BIT_RXCFG_DRTH (0x1f<<1)
101 #define BIT_RXCFG_MXDMA (0x7<<20)
102 #define BIT_RXCFG_ALP (1<<27)
103 #define BIT_RXCFG_ATX (1<<28)
104 #define BIT_RXCFG_ARP (1<<30)
105 #define BIT_RXCFG_AEP (1<<31)
106 #define REG_CCSR 15
107 #define BIT_CCSR_CLKRUN_EN (1<<0)
108 #define BIT_CCSR_PMEEN (1<<8)
109 #define BIT_CCSR_PMESTS (1<<15)
110 #define REG_WCSR 16
111 #define BIT_WCSR_WKPHY (1<<0)
112 #define BIT_WCSR_WKUCP (1<<1)
113 #define BIT_WCSR_WKMCP (1<<2)
114 #define BIT_WCSR_WKBCP (1<<3)
115 #define BIT_WCSR_WKARP (1<<4)
116 #define BIT_WCSR_WKPAT0 (1<<5)
117 #define BIT_WCSR_WKPAT1 (1<<6)
118 #define BIT_WCSR_WKPAT2 (1<<7)
119 #define BIT_WCSR_WKPAT3 (1<<8)
120 #define BIT_WCSR_WKMAG (1<<9)
121 #define BIT_WCSR_MPSOE (1<<10)
122 #define BIT_WCSR_SOHACK (1<<20)
123 #define BIT_WCSR_PHYINT (1<<22)
124 #define BIT_WCSR_UCASTR (1<<23)
125 #define BIT_WCSR_MCASTR (1<<24)
126 #define BIT_WCSR_BCASTR (1<<25)
127 #define BIT_WCSR_ARPR (1<<26)
128 #define BIT_WCSR_PATM0 (1<<27)
129 #define BIT_WCSR_PATM1 (1<<28)
130 #define BIT_WCSR_PATM2 (1<<29)
131 #define BIT_WCSR_PATM3 (1<<30)
132 #define BIT_WCSR_MPR (1<<31)
133 #define REG_PCR 17
134 #define BIT_PCR_PAUSE_CNT (0xffff<<0)
135 #define BIT_PCR_PSNEG (1<<21)
136 #define BIT_PCR_PS_RCVD (1<<22)
137 #define BIT_PCR_PS_DA (1<<29)
138 #define BIT_PCR_PSMCAST (1<<30)
139 #define BIT_PCR_PSEN (1<<31)
140 #define REG_RFCR 18
141 #define BIT_RFCR_UHEN (1<<20)
142 #define BIT_RFCR_MHEN (1<<21)
143 #define BIT_RFCR_AARP (1<<22)
144 #define BIT_RFCR_APAT0 (1<<23)
145 #define BIT_RFCR_APAT1 (1<<24)
146 #define BIT_RFCR_APAT2 (1<<25)
147 #define BIT_RFCR_APAT3 (1<<26)
148 #define BIT_RFCR_APM (1<<27)
149 #define BIT_RFCR_AAU (1<<28)
150 #define BIT_RFCR_AAM (1<<29)
151 #define BIT_RFCR_AAB (1<<30)
152 #define BIT_RFCR_RFEN (1<<31)
153 #define REG_RFDR 19
154 #define REG_BRAR 20
155 #define BIT_BRAR_AUTOINC (1<<31)
156 #define REG_BRDR 21
157 #define REG_SRR 22
158 #define REG_MIBC 23
159 #define BIT_MIBC_WRN (1<<0)
160 #define BIT_MIBC_FRZ (1<<1)
161 #define REG_MIB0 24
162 #define REG_MIB1 25
163 #define REG_MIB2 26
164 #define REG_MIB3 27
165 #define REG_MIB4 28
166 #define REG_MIB5 29
167 #define REG_MIB6 30
168 #define REG_BMCR 32
169 #define BIT_BMCR_FDUP (1<<8)
170 #define BIT_BMCR_ANRST (1<<9)
171 #define BIT_BMCR_ISOL (1<<10)
172 #define BIT_BMCR_PDOWN (1<<11)
173 #define BIT_BMCR_ANEN (1<<12)
174 #define BIT_BMCR_SPEED (1<<13)
175 #define BIT_BMCR_LOOP (1<<14)
176 #define BIT_BMCR_RST (1<<15)
177 #define REG_BMSR 33
178 #define BIT_BMSR_JABBER (1<<1)
179 #define BIT_BMSR_LNK (1<<2)
180 #define BIT_BMSR_ANCAP (1<<3)
181 #define BIT_BMSR_RFAULT (1<<4)
182 #define BIT_BMSR_ANDONE (1<<5)
183 #define BIT_BMSR_PREAMBLE (1<<6)
184 #define BIT_BMSR_10HCAP (1<<11)
185 #define BIT_BMSR_10FCAP (1<<12)
186 #define BIT_BMSR_100HCAP (1<<13)
187 #define BIT_BMSR_100FCAP (1<<14)
188 #define BIT_BMSR_100T4CAP (1<<15)
189 #define REG_PHYIDR1 34
190 #define REG_PHYIDR2 35
191 #define BIT_PHYIDR2_OUILSB (0x3f<<10)
192 #define BIT_PHYIDR2_MODEL (0x3f<<4)
193 #define BIT_PHYIDR2_REV (0xf)
194 #define REG_ANAR 36
195 #define BIT_ANAR_PROTO (0x1f<<0)
196 #define BIT_ANAR_10 (1<<5)
197 #define BIT_ANAR_10_FD (1<<6)
198 #define BIT_ANAR_TX (1<<7)
199 #define BIT_ANAR_TXFD (1<<8)
200 #define BIT_ANAR_T4 (1<<9)
201 #define BIT_ANAR_PAUSE (1<<10)
202 #define BIT_ANAR_RF (1<<13)
203 #define BIT_ANAR_NP (1<<15)
204 #define REG_ANLPAR 37
205 #define BIT_ANLPAR_PROTO (0x1f<<0)
206 #define BIT_ANLPAR_10 (1<<5)
207 #define BIT_ANLPAR_10_FD (1<<6)
208 #define BIT_ANLPAR_TX (1<<7)
209 #define BIT_ANLPAR_TXFD (1<<8)
210 #define BIT_ANLPAR_T4 (1<<9)
211 #define BIT_ANLPAR_PAUSE (1<<10)
212 #define BIT_ANLPAR_RF (1<<13)
213 #define BIT_ANLPAR_ACK (1<<14)
214 #define BIT_ANLPAR_NP (1<<15)
215 #define REG_ANER 38
216 #define BIT_ANER_LP_AN_ENABLE (1<<0)
217 #define BIT_ANER_PAGE_RX (1<<1)
218 #define BIT_ANER_NP_ABLE (1<<2)
219 #define BIT_ANER_LP_NP_ABLE (1<<3)
220 #define BIT_ANER_PDF (1<<4)
221 #define REG_ANNPTR 39
222 #define REG_PHYSTS 48
223 #define BIT_PHYSTS_LNK (1<<0)
224 #define BIT_PHYSTS_SPD10 (1<<1)
225 #define BIT_PHYSTS_FDUP (1<<2)
226 #define BIT_PHYSTS_LOOP (1<<3)
227 #define BIT_PHYSTS_ANDONE (1<<4)
228 #define BIT_PHYSTS_JABBER (1<<5)
229 #define BIT_PHYSTS_RF (1<<6)
230 #define BIT_PHYSTS_MINT (1<<7)
231 #define BIT_PHYSTS_FC (1<<11)
232 #define BIT_PHYSTS_POL (1<<12)
233 #define BIT_PHYSTS_RXERR (1<<13)
234 #define REG_MICR 49
235 #define BIT_MICR_INTEN (1<<1)
236 #define REG_MISR 50
237 #define BIT_MISR_MSK_RHF (1<<9)
238 #define BIT_MISR_MSK_FHF (1<<10)
239 #define BIT_MISR_MSK_ANC (1<<11)
240 #define BIT_MISR_MSK_RF (1<<12)
241 #define BIT_MISR_MSK_JAB (1<<13)
242 #define BIT_MISR_MSK_LNK (1<<14)
243 #define BIT_MISR_MINT (1<<15)
244 #define REG_PGSEL 51
245 #define REG_FCSCR 52
246 #define REG_RECR 53
247 #define REG_PCSR 54
248 #define BIT_PCSR_NRZI (1<<2)
249 #define BIT_PCSR_FORCE_100 (1<<5)
250 #define BIT_PCSR_SDOPT (1<<8)
251 #define BIT_PCSR_SDFORCE (1<<9)
252 #define BIT_PCSR_TQM (1<<10)
253 #define BIT_PCSR_CLK (1<<11)
254 #define BIT_PCSR_4B5B (1<<12)
255 #define REG_PHYCR 57
256 #define BIT_PHYCR_PHYADDR (0x1f<<0)
257 #define BIT_PHYCR_PAUSE_STS (1<<7)
258 #define BIT_PHYCR_STRETCH (1<<8)
259 #define BIT_PHYCR_BIST (1<<9)
260 #define BIT_PHYCR_BIST_STAT (1<<10)
261 #define BIT_PHYCR_PSR15 (1<<11)
262 #define REG_TBTSCR 58
263 #define BIT_TBTSCR_JAB (1<<0)
264 #define BIT_TBTSCR_BEAT (1<<1)
265 #define BIT_TBTSCR_AUTOPOL (1<<3)
266 #define BIT_TBTSCR_POL (1<<4)
267 #define BIT_TBTSCR_FPOL (1<<5)
268 #define BIT_TBTSCR_FORCE_10 (1<<6)
269 #define BIT_TBTSCR_PULSE (1<<7)
270 #define BIT_TBTSCR_LOOP (1<<8)
271 #define REG_PMDCSR 64
272 #define REG_TSTDAT 65
273 #define REG_DSPCFG 66
274 #define REG_SDCFG 67
275 #define REG_PMATCH0 68
276 #define REG_PMATCH1 69
277 #define REG_PMATCH2 70
278 #define REG_PCOUNT0 71
279 #define REG_PCOUNT1 72
280 #define REG_SOPASS0 73
281 #define REG_SOPASS1 74
282 #define REG_SOPASS2 75
283
__print_intr(int d,int intr,const char * name,const char * s1,const char * s2)284 static void __print_intr(int d, int intr, const char *name,
285 const char *s1, const char *s2)
286 {
287 if ((d) & intr)
288 fprintf(stdout, " %s Interrupt: %s\n", name, s1);
289 else if (s2)
290 fprintf(stdout, " %s Interrupt: %s\n", name, s2);
291 }
292
293 #define PRINT_INTR(d, i, s1, s2) do { \
294 int intr = BIT_INTR_ ## i; \
295 const char *name = NAME_INTR_ ## i; \
296 __print_intr(d, intr, name, s1, s2); \
297 } while (0)
298
299 #define PRINT_INTRS(d, s1, s2) do { \
300 PRINT_INTR((d), RXOK, s1, s2); \
301 PRINT_INTR((d), RXDESC, s1, s2); \
302 PRINT_INTR((d), RXERR, s1, s2); \
303 PRINT_INTR((d), RXEARLY, s1, s2); \
304 PRINT_INTR((d), RXIDLE, s1, s2); \
305 PRINT_INTR((d), RXORN, s1, s2); \
306 PRINT_INTR((d), TXOK, s1, s2); \
307 PRINT_INTR((d), TXDESC, s1, s2); \
308 PRINT_INTR((d), TXERR, s1, s2); \
309 PRINT_INTR((d), TXIDLE, s1, s2); \
310 PRINT_INTR((d), TXURN, s1, s2); \
311 PRINT_INTR((d), MIB, s1, s2); \
312 PRINT_INTR((d), SWI, s1, s2); \
313 PRINT_INTR((d), PME, s1, s2); \
314 PRINT_INTR((d), PHY, s1, s2); \
315 PRINT_INTR((d), HIBERR, s1, s2); \
316 PRINT_INTR((d), RXSOVR, s1, s2); \
317 PRINT_INTR((d), RTABT, s1, s2); \
318 PRINT_INTR((d), RMABT, s1, s2); \
319 PRINT_INTR((d), SSERR, s1, s2); \
320 PRINT_INTR((d), DPERR, s1, s2); \
321 PRINT_INTR((d), RXRCMP, s1, s2); \
322 PRINT_INTR((d), TXRCMP, s1, s2); \
323 } while (0)
324
325 int
natsemi_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)326 natsemi_dump_regs(struct ethtool_drvinfo *info maybe_unused,
327 struct ethtool_regs *regs)
328 {
329 u32 *data = (u32 *)regs->data;
330 u32 tmp;
331
332 fprintf(stdout, "Mac/BIU Registers\n");
333 fprintf(stdout, "-----------------\n");
334
335 /* command register */
336 fprintf(stdout,
337 "0x00: CR (Command): 0x%08x\n",
338 data[REG_CR]);
339 fprintf(stdout,
340 " Transmit %s\n"
341 " Receive %s\n",
342 data[REG_CR] & BIT_CR_TXE ? "Active" : "Idle",
343 data[REG_CR] & BIT_CR_RXE ? "Active" : "Idle");
344 if (data[REG_CR] & BIT_CR_RST) fprintf(stdout,
345 " Reset In Progress\n");
346
347 /* configuration register */
348 fprintf(stdout,
349 "0x04: CFG (Configuration): 0x%08x\n",
350 data[REG_CFG]);
351 fprintf(stdout,
352 " %s Endian\n"
353 " Boot ROM %s\n"
354 " Internal Phy %s\n"
355 " Phy Reset %s\n"
356 " External Phy %s\n"
357 " Default Auto-Negotiation %s, %s %s Mb %s Duplex\n"
358 " Phy Interrupt %sAuto-Cleared\n"
359 " Phy Configuration = 0x%02x\n"
360 " Auto-Negotiation %s\n"
361 " %s Polarity\n"
362 " %s Duplex\n"
363 " %d Mb/s\n"
364 " Link %s\n",
365 data[REG_CFG] & BIT_CFG_BEM ? "Big" : "Little",
366 data[REG_CFG] & BIT_CFG_BROM_DIS ? "Disabled" : "Enabled",
367 data[REG_CFG] & BIT_CFG_PHY_DIS ? "Disabled" : "Enabled",
368 data[REG_CFG] & BIT_CFG_PHY_RST ? "In Progress" : "Idle",
369 data[REG_CFG] & BIT_CFG_EXT_PHY ? "Enabled" : "Disabled",
370 data[REG_CFG] & BIT_CFG_ANEG_EN ? "Enabled" : "Disabled",
371 data[REG_CFG] & BIT_CFG_ANEG_EN ? "Advertise" : "Force",
372 data[REG_CFG] & BIT_CFG_ANEG_100 ?
373 (data[REG_CFG] & BIT_CFG_ANEG_EN ? "10/100" : "100")
374 : "10",
375 data[REG_CFG] & BIT_CFG_ANEG_FDUP ?
376 (data[REG_CFG] & BIT_CFG_ANEG_EN ? "Half/Full" : "Full")
377 : "Half",
378 data[REG_CFG] & BIT_CFG_PINT_ACEN ? "" : "Not ",
379 data[REG_CFG] & BIT_CFG_PHY_CFG >> 18,
380 data[REG_CFG] & BIT_CFG_ANEG_DN ? "Done" : "Not Done",
381 data[REG_CFG] & BIT_CFG_POL ? "Reversed" : "Normal",
382 data[REG_CFG] & BIT_CFG_FDUP ? "Full" : "Half",
383 data[REG_CFG] & BIT_CFG_SPEED100 ? 100 : 10,
384 data[REG_CFG] & BIT_CFG_LNKSTS ? "Up" : "Down");
385
386 /* EEPROM access register */
387 fprintf(stdout,
388 "0x08: MEAR (EEPROM Access): 0x%08x\n",
389 data[REG_MEAR]);
390
391 /* PCI test control register */
392 fprintf(stdout,
393 "0x0c: PTSCR (PCI Test Control): 0x%08x\n",
394 data[REG_PTSCR]);
395 fprintf(stdout,
396 " EEPROM Self Test %s\n"
397 " Rx Filter Self Test %s\n"
398 " Tx FIFO Self Test %s\n"
399 " Rx FIFO Self Test %s\n",
400 data[REG_PTSCR] & BIT_PTSCR_EEBIST_FAIL ? "Failed" : "Passed",
401 data[REG_PTSCR] & BIT_PTSCR_RBIST_RXFFAIL ? "Failed" : "Passed",
402 data[REG_PTSCR] & BIT_PTSCR_RBIST_TXFAIL ? "Failed" : "Passed",
403 data[REG_PTSCR] & BIT_PTSCR_RBIST_RXFAIL ? "Failed" : "Passed");
404 if (data[REG_PTSCR] & BIT_PTSCR_EELOAD_EN) fprintf(stdout,
405 " EEPROM Reload In Progress\n");
406
407 /* Interrupt status register */
408 fprintf(stdout,
409 "0x10: ISR (Interrupt Status): 0x%08x\n",
410 data[REG_ISR]);
411 if (data[REG_ISR])
412 PRINT_INTRS(data[REG_ISR], "Active", (char *)NULL);
413 else
414 fprintf(stdout, " No Interrupts Active\n");
415
416 /* Interrupt mask register */
417 fprintf(stdout,
418 "0x14: IMR (Interrupt Mask): 0x%08x\n",
419 data[REG_IMR]);
420 PRINT_INTRS(data[REG_IMR], "Enabled", "Masked");
421
422 /* Interrupt enable register */
423 fprintf(stdout,
424 "0x18: IER (Interrupt Enable): 0x%08x\n",
425 data[REG_IER]);
426 fprintf(stdout,
427 " Interrupts %s\n",
428 data[REG_IER] & BIT_IER_IE ? "Enabled" : "Disabled");
429
430 /* Tx descriptor pointer register */
431 fprintf(stdout,
432 "0x20: TXDP (Tx Descriptor Pointer): 0x%08x\n",
433 data[REG_TXDP]);
434
435 /* Tx configuration register */
436 fprintf(stdout,
437 "0x24: TXCFG (Tx Config): 0x%08x\n",
438 data[REG_TXCFG]);
439 tmp = (data[REG_TXCFG] & BIT_TXCFG_MXDMA)>>20;
440 fprintf(stdout,
441 " Drain Threshold = %d bytes (%d)\n"
442 " Fill Threshold = %d bytes (%d)\n"
443 " Max DMA Burst per Tx = %d bytes\n"
444 " Automatic Tx Padding %s\n"
445 " Mac Loopback %s\n"
446 " Heartbeat Ignore %s\n"
447 " Carrier Sense Ignore %s\n",
448 (data[REG_TXCFG] & BIT_TXCFG_DRTH) * 32,
449 data[REG_TXCFG] & BIT_TXCFG_DRTH,
450 ((data[REG_TXCFG] & BIT_TXCFG_FLTH)>>8) * 32,
451 data[REG_TXCFG] & BIT_TXCFG_FLTH,
452 tmp ? (1<<(tmp-1))*4 : 512,
453 data[REG_TXCFG] & BIT_TXCFG_ATP ? "Enabled" : "Disabled",
454 data[REG_TXCFG] & BIT_TXCFG_MLB ? "Enabled" : "Disabled",
455 data[REG_TXCFG] & BIT_TXCFG_HBI ? "Enabled" : "Disabled",
456 data[REG_TXCFG] & BIT_TXCFG_CSI ? "Enabled" : "Disabled");
457
458
459 /* Rx descriptor pointer register */
460 fprintf(stdout,
461 "0x30: RXDP (Rx Descriptor Pointer): 0x%08x\n",
462 data[REG_RXDP]);
463
464 /* Rx configuration register */
465 fprintf(stdout,
466 "0x34: RXCFG (Rx Config): 0x%08x\n",
467 data[REG_RXCFG]);
468 tmp = (data[REG_RXCFG] & BIT_RXCFG_MXDMA)>>20;
469 fprintf(stdout,
470 " Drain Threshold = %d bytes (%d)\n"
471 " Max DMA Burst per Rx = %d bytes\n"
472 " Long Packets %s\n"
473 " Tx Packets %s\n"
474 " Runt Packets %s\n"
475 " Error Packets %s\n",
476 ((data[REG_RXCFG] & BIT_RXCFG_DRTH) >> 1) * 8,
477 (data[REG_RXCFG] & BIT_RXCFG_DRTH) >> 1,
478 tmp ? (1<<(tmp-1))*4 : 512,
479 data[REG_RXCFG] & BIT_RXCFG_ALP ? "Accepted" : "Rejected",
480 data[REG_RXCFG] & BIT_RXCFG_ATX ? "Accepted" : "Rejected",
481 data[REG_RXCFG] & BIT_RXCFG_ARP ? "Accepted" : "Rejected",
482 data[REG_RXCFG] & BIT_RXCFG_AEP ? "Accepted" : "Rejected");
483
484 /* CLKRUN control/status register */
485 fprintf(stdout,
486 "0x3c: CCSR (CLKRUN Control/Status): 0x%08x\n",
487 data[REG_CCSR]);
488 fprintf(stdout,
489 " CLKRUNN %s\n"
490 " Power Management %s\n",
491 data[REG_CCSR] & BIT_CCSR_CLKRUN_EN ? "Enabled" : "Disabled",
492 data[REG_CCSR] & BIT_CCSR_PMEEN ? "Enabled" : "Disabled");
493 if (data[REG_CCSR] & BIT_CCSR_PMESTS) fprintf(stdout,
494 " Power Management Event Pending\n");
495
496 /* WoL control/status register */
497 fprintf(stdout,
498 "0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x\n",
499 data[REG_WCSR]);
500 if (data[REG_WCSR] & BIT_WCSR_WKPHY) fprintf(stdout,
501 " Wake on Phy Interrupt Enabled\n");
502 if (data[REG_WCSR] & BIT_WCSR_WKUCP) fprintf(stdout,
503 " Wake on Unicast Packet Enabled\n");
504 if (data[REG_WCSR] & BIT_WCSR_WKMCP) fprintf(stdout,
505 " Wake on Multicast Packet Enabled\n");
506 if (data[REG_WCSR] & BIT_WCSR_WKBCP) fprintf(stdout,
507 " Wake on Broadcast Packet Enabled\n");
508 if (data[REG_WCSR] & BIT_WCSR_WKARP) fprintf(stdout,
509 " Wake on Arp Enabled\n");
510 if (data[REG_WCSR] & BIT_WCSR_WKPAT0) fprintf(stdout,
511 " Wake on Pattern 0 Match Enabled\n");
512 if (data[REG_WCSR] & BIT_WCSR_WKPAT1) fprintf(stdout,
513 " Wake on Pattern 1 Match Enabled\n");
514 if (data[REG_WCSR] & BIT_WCSR_WKPAT2) fprintf(stdout,
515 " Wake on Pattern 2 Match Enabled\n");
516 if (data[REG_WCSR] & BIT_WCSR_WKPAT3) fprintf(stdout,
517 " Wake on Pattern 3 Match Enabled\n");
518 if (data[REG_WCSR] & BIT_WCSR_WKMAG) fprintf(stdout,
519 " Wake on Magic Packet Enabled\n");
520 if (data[REG_WCSR] & BIT_WCSR_MPSOE) fprintf(stdout,
521 " Magic Packet SecureOn Enabled\n");
522 if (data[REG_WCSR] & BIT_WCSR_SOHACK) fprintf(stdout,
523 " SecureOn Hack Detected\n");
524 if (data[REG_WCSR] & BIT_WCSR_PHYINT) fprintf(stdout,
525 " Phy Interrupt Received\n");
526 if (data[REG_WCSR] & BIT_WCSR_UCASTR) fprintf(stdout,
527 " Unicast Packet Received\n");
528 if (data[REG_WCSR] & BIT_WCSR_MCASTR) fprintf(stdout,
529 " Multicast Packet Received\n");
530 if (data[REG_WCSR] & BIT_WCSR_BCASTR) fprintf(stdout,
531 " Broadcast Packet Received\n");
532 if (data[REG_WCSR] & BIT_WCSR_ARPR) fprintf(stdout,
533 " Arp Received\n");
534 if (data[REG_WCSR] & BIT_WCSR_PATM0) fprintf(stdout,
535 " Pattern 0 Received\n");
536 if (data[REG_WCSR] & BIT_WCSR_PATM1) fprintf(stdout,
537 " Pattern 1 Received\n");
538 if (data[REG_WCSR] & BIT_WCSR_PATM2) fprintf(stdout,
539 " Pattern 2 Received\n");
540 if (data[REG_WCSR] & BIT_WCSR_PATM3) fprintf(stdout,
541 " Pattern 3 Received\n");
542 if (data[REG_WCSR] & BIT_WCSR_MPR) fprintf(stdout,
543 " Magic Packet Received\n");
544
545 /* Pause control/status register */
546 fprintf(stdout,
547 "0x44: PCR (Pause Control/Status): 0x%08x\n",
548 data[REG_PCR]);
549 fprintf(stdout,
550 " Pause Counter = %d\n"
551 " Pause %sNegotiated\n"
552 " Pause on DA %s\n"
553 " Pause on Mulitcast %s\n"
554 " Pause %s\n",
555 data[REG_PCR] & BIT_PCR_PAUSE_CNT,
556 data[REG_PCR] & BIT_PCR_PSNEG ? "" : "Not ",
557 data[REG_PCR] & BIT_PCR_PS_DA ? "Enabled" : "Disabled",
558 data[REG_PCR] & BIT_PCR_PSMCAST ? "Enabled" : "Disabled",
559 data[REG_PCR] & BIT_PCR_PSEN ? "Enabled" : "Disabled");
560 if (data[REG_PCR] & BIT_PCR_PS_RCVD) fprintf(stdout,
561 " PS_RCVD: Pause Frame Received\n");
562
563 /* Rx Filter Control */
564 fprintf(stdout,
565 "0x48: RFCR (Rx Filter Control): 0x%08x\n",
566 data[REG_RFCR]);
567 fprintf(stdout,
568 " Unicast Hash %s\n"
569 " Multicast Hash %s\n"
570 " Arp %s\n"
571 " Pattern 0 Match %s\n"
572 " Pattern 1 Match %s\n"
573 " Pattern 2 Match %s\n"
574 " Pattern 3 Match %s\n"
575 " Perfect Match %s\n"
576 " All Unicast %s\n"
577 " All Multicast %s\n"
578 " All Broadcast %s\n"
579 " Rx Filter %s\n",
580 data[REG_RFCR] & BIT_RFCR_UHEN ? "Enabled" : "Disabled",
581 data[REG_RFCR] & BIT_RFCR_MHEN ? "Enabled" : "Disabled",
582 data[REG_RFCR] & BIT_RFCR_AARP ? "Accepted" : "Rejected",
583 data[REG_RFCR] & BIT_RFCR_APAT0 ? "Accepted" : "Rejected",
584 data[REG_RFCR] & BIT_RFCR_APAT1 ? "Accepted" : "Rejected",
585 data[REG_RFCR] & BIT_RFCR_APAT2 ? "Accepted" : "Rejected",
586 data[REG_RFCR] & BIT_RFCR_APAT3 ? "Accepted" : "Rejected",
587 data[REG_RFCR] & BIT_RFCR_APM ? "Accepted" : "Rejected",
588 data[REG_RFCR] & BIT_RFCR_AAU ? "Accepted" : "Rejected",
589 data[REG_RFCR] & BIT_RFCR_AAM ? "Accepted" : "Rejected",
590 data[REG_RFCR] & BIT_RFCR_AAB ? "Accepted" : "Rejected",
591 data[REG_RFCR] & BIT_RFCR_RFEN ? "Enabled" : "Disabled");
592
593 /* Rx filter data register */
594 fprintf(stdout,
595 "0x4c: RFDR (Rx Filter Data): 0x%08x\n",
596 data[REG_RFDR]);
597 if (regs->version >= 1) fprintf(stdout,
598 " PMATCH 1-0 = 0x%08x\n"
599 " PMATCH 3-2 = 0x%08x\n"
600 " PMATCH 5-4 = 0x%08x\n"
601 " PCOUNT 1-0 = 0x%08x\n"
602 " PCOUNT 3-2 = 0x%08x\n"
603 " SOPASS 1-0 = 0x%08x\n"
604 " SOPASS 3-2 = 0x%08x\n"
605 " SOPASS 5-4 = 0x%08x\n",
606 data[REG_PMATCH0], data[REG_PMATCH1], data[REG_PMATCH2],
607 data[REG_PCOUNT0], data[REG_PCOUNT1],
608 data[REG_SOPASS0], data[REG_SOPASS1], data[REG_SOPASS2]);
609
610
611 /* Boot ROM address register */
612 fprintf(stdout,
613 "0x50: BRAR (Boot ROM Address): 0x%08x\n",
614 data[REG_BRAR]);
615 if (data[REG_BRAR] & BIT_BRAR_AUTOINC) fprintf(stdout,
616 " Automatically Increment Address\n");
617
618 /* Boot ROM data register */
619 fprintf(stdout,
620 "0x54: BRDR (Boot ROM Data): 0x%08x\n",
621 data[REG_BRDR]);
622
623 /* Silicon revison register */
624 fprintf(stdout,
625 "0x58: SRR (Silicon Revision): 0x%08x\n",
626 data[REG_SRR]);
627
628 /* Management information base control register */
629 fprintf(stdout,
630 "0x5c: MIBC (Mgmt Info Base Control): 0x%08x\n",
631 data[REG_MIBC]);
632 if (data[REG_MIBC] & BIT_MIBC_WRN) fprintf(stdout,
633 " Counter Overflow Warning\n");
634 if (data[REG_MIBC] & BIT_MIBC_FRZ) fprintf(stdout,
635 " Counters Frozen\n");
636
637 /* MIB registers */
638 fprintf(stdout,
639 "0x60: MIB[0] (Rx Errored Packets): 0x%04x\n",
640 data[REG_MIB0]);
641 fprintf(stdout, " Value = %d\n", data[REG_MIB0]);
642 fprintf(stdout,
643 "0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x\n",
644 data[REG_MIB1]);
645 fprintf(stdout, " Value = %d\n", data[REG_MIB1]);
646 fprintf(stdout,
647 "0x68: MIB[2] (Rx Missed Packets): 0x%02x\n",
648 data[REG_MIB2]);
649 fprintf(stdout, " Value = %d\n", data[REG_MIB2]);
650 fprintf(stdout,
651 "0x6c: MIB[3] (Rx Alignment Errors): 0x%02x\n",
652 data[REG_MIB3]);
653 fprintf(stdout, " Value = %d\n", data[REG_MIB3]);
654 fprintf(stdout,
655 "0x70: MIB[4] (Rx Symbol Errors): 0x%02x\n",
656 data[REG_MIB4]);
657 fprintf(stdout, " Value = %d\n", data[REG_MIB4]);
658 fprintf(stdout,
659 "0x74: MIB[5] (Rx Long Frame Errors): 0x%02x\n",
660 data[REG_MIB5]);
661 fprintf(stdout, " Value = %d\n", data[REG_MIB5]);
662 fprintf(stdout,
663 "0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x\n",
664 data[REG_MIB6]);
665 fprintf(stdout, " Value = %d\n", data[REG_MIB6]);
666
667 fprintf(stdout, "\n");
668 fprintf(stdout, "Internal Phy Registers\n");
669 fprintf(stdout, "----------------------\n");
670
671 /* Basic mode control register */
672 fprintf(stdout,
673 "0x80: BMCR (Basic Mode Control): 0x%04x\n",
674 data[REG_BMCR]);
675 fprintf(stdout,
676 " %s Duplex\n"
677 " Port is Powered %s\n"
678 " Auto-Negotiation %s\n"
679 " %d Mb/s\n",
680 data[REG_BMCR] & BIT_BMCR_FDUP ? "Full" : "Half",
681 data[REG_BMCR] & BIT_BMCR_PDOWN ? "Down" : "Up",
682 data[REG_BMCR] & BIT_BMCR_ANEN ? "Enabled" : "Disabled",
683 data[REG_BMCR] & BIT_BMCR_SPEED ? 100 : 10);
684 if (data[REG_BMCR] & BIT_BMCR_ANRST) fprintf(stdout,
685 " Auto-Negotiation Restarting\n");
686 if (data[REG_BMCR] & BIT_BMCR_ISOL) fprintf(stdout,
687 " Port Isolated\n");
688 if (data[REG_BMCR] & BIT_BMCR_LOOP) fprintf(stdout,
689 " Loopback Enabled\n");
690 if (data[REG_BMCR] & BIT_BMCR_RST) fprintf(stdout,
691 " Reset In Progress\n");
692
693 /* Basic mode status register */
694 fprintf(stdout,
695 "0x84: BMSR (Basic Mode Status): 0x%04x\n",
696 data[REG_BMSR]);
697 fprintf(stdout,
698 " Link %s\n"
699 " %sCapable of Auto-Negotiation\n"
700 " Auto-Negotiation %sComplete\n"
701 " %sCapable of Preamble Suppression\n"
702 " %sCapable of 10Base-T Half Duplex\n"
703 " %sCapable of 10Base-T Full Duplex\n"
704 " %sCapable of 100Base-TX Half Duplex\n"
705 " %sCapable of 100Base-TX Full Duplex\n"
706 " %sCapable of 100Base-T4\n",
707 data[REG_BMSR] & BIT_BMSR_LNK ? "Up" : "Down",
708 data[REG_BMSR] & BIT_BMSR_ANCAP ? "" : "Not ",
709 data[REG_BMSR] & BIT_BMSR_ANDONE ? "" : "Not ",
710 data[REG_BMSR] & BIT_BMSR_PREAMBLE ? "" : "Not ",
711 data[REG_BMSR] & BIT_BMSR_10HCAP ? "" : "Not ",
712 data[REG_BMSR] & BIT_BMSR_10FCAP ? "" : "Not ",
713 data[REG_BMSR] & BIT_BMSR_100HCAP ? "" : "Not ",
714 data[REG_BMSR] & BIT_BMSR_100FCAP ? "" : "Not ",
715 data[REG_BMSR] & BIT_BMSR_100T4CAP ? "" : "Not ");
716 if (data[REG_BMSR] & BIT_BMSR_JABBER) fprintf(stdout,
717 " Jabber Condition Detected\n");
718 if (data[REG_BMSR] & BIT_BMSR_RFAULT) fprintf(stdout,
719 " Remote Fault Detected\n");
720
721 /* PHY identification registers */
722 fprintf(stdout,
723 "0x88: PHYIDR1 (PHY ID #1): 0x%04x\n",
724 data[REG_PHYIDR1]);
725 fprintf(stdout,
726 "0x8c: PHYIDR2 (PHY ID #2): 0x%04x\n",
727 data[REG_PHYIDR2]);
728 fprintf(stdout,
729 " OUI = 0x%06x\n"
730 " Model = 0x%02x (%d)\n"
731 " Revision = 0x%01x (%d)\n",
732 (data[REG_PHYIDR1] << 6) | (data[REG_PHYIDR2] >> 10),
733 (data[REG_PHYIDR2] & BIT_PHYIDR2_MODEL) >> 4 & 0x3f,
734 (data[REG_PHYIDR2] & BIT_PHYIDR2_MODEL) >> 4 & 0x3f,
735 data[REG_PHYIDR2] & BIT_PHYIDR2_REV,
736 data[REG_PHYIDR2] & BIT_PHYIDR2_REV);
737
738 /* autonegotiation advertising register */
739 fprintf(stdout,
740 "0x90: ANAR (Autoneg Advertising): 0x%04x\n",
741 data[REG_ANAR]);
742 fprintf(stdout,
743 " Protocol Selector = 0x%02x (%d)\n",
744 data[REG_ANAR] & BIT_ANAR_PROTO,
745 data[REG_ANAR] & BIT_ANAR_PROTO);
746 if (data[REG_ANAR] & BIT_ANAR_10) fprintf(stdout,
747 " Advertising 10Base-T Half Duplex\n");
748 if (data[REG_ANAR] & BIT_ANAR_10_FD) fprintf(stdout,
749 " Advertising 10Base-T Full Duplex\n");
750 if (data[REG_ANAR] & BIT_ANAR_TX) fprintf(stdout,
751 " Advertising 100Base-TX Half Duplex\n");
752 if (data[REG_ANAR] & BIT_ANAR_TXFD) fprintf(stdout,
753 " Advertising 100Base-TX Full Duplex\n");
754 if (data[REG_ANAR] & BIT_ANAR_T4) fprintf(stdout,
755 " Advertising 100Base-T4\n");
756 if (data[REG_ANAR] & BIT_ANAR_PAUSE) fprintf(stdout,
757 " Advertising Pause\n");
758 if (data[REG_ANAR] & BIT_ANAR_RF) fprintf(stdout,
759 " Indicating Remote Fault\n");
760 if (data[REG_ANAR] & BIT_ANAR_NP) fprintf(stdout,
761 " Next Page Desired\n");
762
763 /* Autonegotiation link partner ability register */
764 fprintf(stdout,
765 "0x94: ANLPAR (Autoneg Partner): 0x%04x\n",
766 data[REG_ANLPAR]);
767 fprintf(stdout,
768 " Protocol Selector = 0x%02x (%d)\n",
769 data[REG_ANLPAR] & BIT_ANLPAR_PROTO,
770 data[REG_ANLPAR] & BIT_ANLPAR_PROTO);
771 if (data[REG_ANLPAR] & BIT_ANLPAR_10) fprintf(stdout,
772 " Supports 10Base-T Half Duplex\n");
773 if (data[REG_ANLPAR] & BIT_ANLPAR_10_FD) fprintf(stdout,
774 " Supports 10Base-T Full Duplex\n");
775 if (data[REG_ANLPAR] & BIT_ANLPAR_TX) fprintf(stdout,
776 " Supports 100Base-TX Half Duplex\n");
777 if (data[REG_ANLPAR] & BIT_ANLPAR_TXFD) fprintf(stdout,
778 " Supports 100Base-TX Full Duplex\n");
779 if (data[REG_ANLPAR] & BIT_ANLPAR_T4) fprintf(stdout,
780 " Supports 100Base-T4\n");
781 if (data[REG_ANLPAR] & BIT_ANLPAR_PAUSE) fprintf(stdout,
782 " Supports Pause\n");
783 if (data[REG_ANLPAR] & BIT_ANLPAR_RF) fprintf(stdout,
784 " Indicates Remote Fault\n");
785 if (data[REG_ANLPAR] & BIT_ANLPAR_ACK) fprintf(stdout,
786 " Indicates Acknowledgement\n");
787 if (data[REG_ANLPAR] & BIT_ANLPAR_NP) fprintf(stdout,
788 " Next Page Desired\n");
789
790 /* Autonegotiation expansion register */
791 fprintf(stdout,
792 "0x98: ANER (Autoneg Expansion): 0x%04x\n",
793 data[REG_ANER]);
794 fprintf(stdout,
795 " Link Partner Can %sAuto-Negotiate\n"
796 " Link Code Word %sReceived\n"
797 " Next Page %sSupported\n"
798 " Link Partner Next Page %sSupported\n",
799 data[REG_ANER] & BIT_ANER_LP_AN_ENABLE ? "" : "Not ",
800 data[REG_ANER] & BIT_ANER_PAGE_RX ? "" : "Not ",
801 data[REG_ANER] & BIT_ANER_NP_ABLE ? "" : "Not ",
802 data[REG_ANER] & BIT_ANER_LP_NP_ABLE ? "" : "Not ");
803 if (data[REG_ANER] & BIT_ANER_PDF) fprintf(stdout,
804 " Parallel Detection Fault\n");
805
806 /* Autonegotiation next-page tx register */
807 fprintf(stdout,
808 "0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x\n",
809 data[REG_ANNPTR]);
810
811 /* Phy status register */
812 fprintf(stdout,
813 "0xc0: PHYSTS (Phy Status): 0x%04x\n",
814 data[REG_PHYSTS]);
815 fprintf(stdout,
816 " Link %s\n"
817 " %d Mb/s\n"
818 " %s Duplex\n"
819 " Auto-Negotiation %sComplete\n"
820 " %s Polarity\n",
821 data[REG_PHYSTS] & BIT_PHYSTS_LNK ? "Up" : "Down",
822 data[REG_PHYSTS] & BIT_PHYSTS_SPD10 ? 10 : 100,
823 data[REG_PHYSTS] & BIT_PHYSTS_FDUP ? "Full" : "Half",
824 data[REG_PHYSTS] & BIT_PHYSTS_ANDONE ? "" : "Not ",
825 data[REG_PHYSTS] & BIT_PHYSTS_POL ? "Reverse" : "Normal");
826 if (data[REG_PHYSTS] & BIT_PHYSTS_LOOP) fprintf(stdout,
827 " Loopback Enabled\n");
828 if (data[REG_PHYSTS] & BIT_PHYSTS_JABBER) fprintf(stdout,
829 " Jabber Condition Detected\n");
830 if (data[REG_PHYSTS] & BIT_PHYSTS_RF) fprintf(stdout,
831 " Remote Fault Detected\n");
832 if (data[REG_PHYSTS] & BIT_PHYSTS_MINT) fprintf(stdout,
833 " MII Interrupt Detected\n");
834 if (data[REG_PHYSTS] & BIT_PHYSTS_FC) fprintf(stdout,
835 " False Carrier Detected\n");
836 if (data[REG_PHYSTS] & BIT_PHYSTS_RXERR) fprintf(stdout,
837 " Rx Error Detected\n");
838
839 fprintf(stdout,
840 "0xc4: MICR (MII Interrupt Control): 0x%04x\n",
841 data[REG_MICR]);
842 fprintf(stdout,
843 " MII Interrupts %s\n",
844 data[REG_MICR] & BIT_MICR_INTEN ? "Enabled" : "Disabled");
845
846 fprintf(stdout,
847 "0xc8: MISR (MII Interrupt Status): 0x%04x\n",
848 data[REG_MISR]);
849 fprintf(stdout,
850 " Rx Error Counter Half-Full Interrupt %s\n"
851 " False Carrier Counter Half-Full Interrupt %s\n"
852 " Auto-Negotiation Complete Interrupt %s\n"
853 " Remote Fault Interrupt %s\n"
854 " Jabber Interrupt %s\n"
855 " Link Change Interrupt %s\n",
856 data[REG_MISR] & BIT_MISR_MSK_RHF ? "Masked" : "Enabled",
857 data[REG_MISR] & BIT_MISR_MSK_FHF ? "Masked" : "Enabled",
858 data[REG_MISR] & BIT_MISR_MSK_ANC ? "Masked" : "Enabled",
859 data[REG_MISR] & BIT_MISR_MSK_RF ? "Masked" : "Enabled",
860 data[REG_MISR] & BIT_MISR_MSK_JAB ? "Masked" : "Enabled",
861 data[REG_MISR] & BIT_MISR_MSK_LNK ? "Masked" : "Enabled");
862 if (data[REG_MISR] & BIT_MISR_MINT) fprintf(stdout,
863 " MII Interrupt Pending\n");
864
865 /* Page select register (from section of spec on 'suggested values') */
866 fprintf(stdout,
867 "0xcc: PGSEL (Phy Register Page Select): 0x%04x\n",
868 data[REG_PGSEL]);
869
870 /* counters */
871 fprintf(stdout,
872 "0xd0: FCSCR (False Carrier Counter): 0x%04x\n",
873 data[REG_FCSCR]);
874 fprintf(stdout,
875 " Value = %d\n", data[REG_FCSCR] & 0xff);
876 fprintf(stdout,
877 "0xd4: RECR (Rx Error Counter): 0x%04x\n",
878 data[REG_RECR]);
879 fprintf(stdout,
880 " Value = %d\n", data[REG_RECR] & 0xff);
881
882 /* 100 Mbit configuration register */
883 fprintf(stdout,
884 "0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x\n",
885 data[REG_PCSR]);
886 fprintf(stdout,
887 " NRZI Bypass %s\n"
888 " %s Signal Detect Algorithm\n"
889 " %s Signal Detect Operation\n"
890 " True Quiet Mode %s\n"
891 " Rx Clock is %s\n"
892 " 4B/5B Operation %s\n",
893 data[REG_PCSR] & BIT_PCSR_NRZI ? "Enabled" : "Disabled",
894 data[REG_PCSR] & BIT_PCSR_SDOPT ? "Enhanced" : "Reduced",
895 data[REG_PCSR] & BIT_PCSR_SDFORCE ? "Forced" : "Normal",
896 data[REG_PCSR] & BIT_PCSR_TQM ? "Enabled" : "Disabled",
897 data[REG_PCSR] & BIT_PCSR_CLK ?
898 "Free-Running" : "Phase-Adjusted",
899 data[REG_PCSR] & BIT_PCSR_4B5B ? "Bypassed" : "Normal");
900 if (data[REG_PCSR] & BIT_PCSR_FORCE_100) fprintf(stdout,
901 " Forced 100 Mb/s Good Link\n");
902
903 /* Phy control register */
904 fprintf(stdout,
905 "0xe4: PHYCR (Phy Control): 0x%04x\n",
906 data[REG_PHYCR]);
907 fprintf(stdout,
908 " Phy Address = 0x%x (%d)\n"
909 " %sPause Compatible with Link Partner\n"
910 " LED Stretching %s\n"
911 " Phy Self Test %s\n"
912 " Self Test Sequence = PSR%d\n",
913 data[REG_PHYCR] & BIT_PHYCR_PHYADDR,
914 data[REG_PHYCR] & BIT_PHYCR_PHYADDR,
915 data[REG_PHYCR] & BIT_PHYCR_PAUSE_STS ? "" : "Not ",
916 data[REG_PHYCR] & BIT_PHYCR_STRETCH ? "Bypassed" : "Enabled",
917 data[REG_PHYCR] & BIT_PHYCR_BIST ? "In Progress" :
918 data[REG_PHYCR] & BIT_PHYCR_BIST_STAT ?
919 "Passed" : "Failed or Not Run",
920 data[REG_PHYCR] & BIT_PHYCR_PSR15 ? 15 : 9);
921
922
923 /* 10 Mbit control and status register */
924 fprintf(stdout,
925 "0xe8: TBTSCR (10Base-T Status/Control): 0x%04x\n",
926 data[REG_TBTSCR]);
927 fprintf(stdout,
928 " Jabber %s\n"
929 " Heartbeat %s\n"
930 " Polarity Auto-Sense/Correct %s\n"
931 " %s Polarity %s\n"
932 " Normal Link Pulse %s\n"
933 " 10 Mb/s Loopback %s\n",
934 data[REG_TBTSCR] & BIT_TBTSCR_JAB ? "Disabled" : "Enabled",
935 data[REG_TBTSCR] & BIT_TBTSCR_BEAT ? "Disabled" : "Enabled",
936 data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ? "Disabled" : "Enabled",
937 data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ?
938 data[REG_TBTSCR]&BIT_TBTSCR_FPOL ? "Reverse":"Normal" :
939 data[REG_TBTSCR]&BIT_TBTSCR_POL ? "Reverse":"Normal",
940 data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ? "Forced" : "Detected",
941 data[REG_TBTSCR] & BIT_TBTSCR_PULSE ? "Disabled" : "Enabled",
942 data[REG_TBTSCR] & BIT_TBTSCR_LOOP ? "Enabled" : "Disabled");
943 if (data[REG_TBTSCR] & BIT_TBTSCR_FORCE_10) fprintf(stdout,
944 " Forced 10 Mb/s Good Link\n");
945
946 /* the spec says to set these */
947 fprintf(stdout, "\n");
948 fprintf(stdout, "'Magic' Phy Registers\n");
949 fprintf(stdout, "---------------------\n");
950 fprintf(stdout,
951 "0xe4: PMDCSR: 0x%04x\n",
952 data[REG_PMDCSR]);
953 fprintf(stdout,
954 "0xf4: DSPCFG: 0x%04x\n",
955 data[REG_DSPCFG]);
956 fprintf(stdout,
957 "0xf8: SDCFG: 0x%04x\n",
958 data[REG_SDCFG]);
959 fprintf(stdout,
960 "0xfc: TSTDAT: 0x%04x\n",
961 data[REG_TSTDAT]);
962
963 return 0;
964 }
965
966 int
natsemi_dump_eeprom(struct ethtool_drvinfo * info maybe_unused,struct ethtool_eeprom * ee)967 natsemi_dump_eeprom(struct ethtool_drvinfo *info maybe_unused,
968 struct ethtool_eeprom *ee)
969 {
970 int i;
971 u16 *eebuf = (u16 *)ee->data;
972
973 if (ee->magic != NATSEMI_MAGIC) {
974 fprintf(stderr, "Magic number 0x%08x does not match 0x%08x\n",
975 ee->magic, NATSEMI_MAGIC);
976 return -1;
977 }
978
979 fprintf(stdout, "Address\tData\n");
980 fprintf(stdout, "-------\t------\n");
981 for (i = 0; i < ee->len/2; i++) {
982 fprintf(stdout, "0x%02x \t0x%04x\n", i + ee->offset, eebuf[i]);
983 }
984
985 return 0;
986 }
987
988