1 use core::num::NonZeroUsize; 2 3 use gdbstub::arch::RegId; 4 5 /// AArch64 Architectural Registers. 6 /// 7 /// Represents architectural registers as 8 /// 9 /// - individual variants for those described in section B1.2. _Registers in 10 /// AArch64 Execution state_ of the Architecture Reference Manual (DDI 11 /// 0487H.a), accessed through their own respective subsets of instructions 12 /// _e.g._ GPRs, FP & SIMD, ... 13 /// - a generic variant for system registers, accessed through MSR/MRS 14 /// instructions, based on their encoding as described in section C5.1. _The 15 /// System instruction class encoding space_ when `op0` is `0b10` (_Debug and 16 /// trace registers_) or `0b11` (_Non-debug System registers_ and 17 /// _Special-purpose registers_), as `0b0x` do not encode registers; 18 /// - a variant for the abstraction of process state information, `PSTATE` 19 /// (section D1.4.), which should be preferred over field-specific 20 /// special-purpose registers (`NZCV`, `DAIF`, ...) 21 /// 22 /// Provides `const` aliases for most system registers as syntactic sugar for 23 /// the `System` variant. When those aren't available (_e.g._ for newly-added 24 /// registers), the literal representation `System(0baa_bbb_xxxx_yyyy_cc)` may 25 /// be used, similarly to the standard assembly symbol, 26 /// `S<op0>_<op1>_<CRn>_<CRm>_<op2>`. 27 /// 28 /// To future-proof and greatly simplify the implementation, the target's XML 29 /// must encode system registers by using their 16-bit encoding as the `regnum` 30 /// property; no clash with architectural registers is possible as the top bit 31 /// of the 16-bit value is guaranteed to be set. 32 #[derive(Debug, Clone, Copy, PartialEq, Eq)] 33 #[non_exhaustive] 34 pub enum AArch64RegId { 35 /// General-purpose Register File (X0 - X30) 36 X(u8), 37 /// Stack Pointer 38 Sp, 39 /// Program Counter 40 Pc, 41 /// Process State (Pseudo-Register) 42 Pstate, 43 /// SIMD & FP Register File (V0 - V31) 44 V(u8), 45 /// System Registers encoded as (Op0:2, Op1:3, CRn:4, CRm:4, Op2:2) 46 System(u16), 47 } 48 49 impl RegId for AArch64RegId { from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)>50 fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> { 51 let reg = match id { 52 0..=30 => Self::X(id as u8), 53 31 => Self::Sp, 54 32 => Self::Pc, 55 33 => Self::Pstate, 56 34..=65 => Self::V((id - 34) as u8), 57 66 => Self::FPSR, 58 67 => Self::FPCR, 59 #[allow(clippy::unusual_byte_groupings)] 60 // We configure GDB to use regnums that correspond to the architectural u16 opcode 61 // and avoid clashes with core registers thanks to op0==0b00 and op0==0b01 not being 62 // allocated for system registers. 63 0b10_000_0000_0000_000..=0b11_111_1111_1111_111 => Self::System(id as u16), 64 _ => return None, 65 }; 66 67 Some((reg, Some(NonZeroUsize::new(reg.len()?)?))) 68 } 69 } 70 71 #[allow(clippy::unusual_byte_groupings)] 72 impl AArch64RegId { 73 #[allow(clippy::len_without_is_empty)] 74 /// Gives the size of the register. len(&self) -> Option<usize>75 pub fn len(&self) -> Option<usize> { 76 match self { 77 Self::Pstate => Some(core::mem::size_of::<u32>()), 78 Self::X(_n @ 0..=30) => Some(core::mem::size_of::<u64>()), 79 Self::V(_n @ 0..=31) => Some(core::mem::size_of::<u128>()), 80 Self::Pc | Self::Sp | Self::System(_) => Some(core::mem::size_of::<u64>()), 81 _ => None, 82 } 83 } 84 85 /// Main ID Register 86 pub const MIDR_EL1: Self = Self::System(0b11_000_0000_0000_000); 87 /// Multiprocessor Affinity Register 88 pub const MPIDR_EL1: Self = Self::System(0b11_000_0000_0000_101); 89 /// Revision ID Register 90 pub const REVIDR_EL1: Self = Self::System(0b11_000_0000_0000_110); 91 /// AArch32 Processor Feature Register 0 92 pub const ID_PFR0_EL1: Self = Self::System(0b11_000_0000_0001_000); 93 /// AArch32 Processor Feature Register 1 94 pub const ID_PFR1_EL1: Self = Self::System(0b11_000_0000_0001_001); 95 /// AArch32 Debug Feature Register 0 96 pub const ID_DFR0_EL1: Self = Self::System(0b11_000_0000_0001_010); 97 /// AArch32 Auxiliary Feature Register 0 98 pub const ID_AFR0_EL1: Self = Self::System(0b11_000_0000_0001_011); 99 /// AArch32 Memory Model Feature Register 0 100 pub const ID_MMFR0_EL1: Self = Self::System(0b11_000_0000_0001_100); 101 /// AArch32 Memory Model Feature Register 1 102 pub const ID_MMFR1_EL1: Self = Self::System(0b11_000_0000_0001_101); 103 /// AArch32 Memory Model Feature Register 2 104 pub const ID_MMFR2_EL1: Self = Self::System(0b11_000_0000_0001_110); 105 /// AArch32 Memory Model Feature Register 3 106 pub const ID_MMFR3_EL1: Self = Self::System(0b11_000_0000_0001_111); 107 /// AArch32 Instruction Set Attribute Register 0 108 pub const ID_ISAR0_EL1: Self = Self::System(0b11_000_0000_0010_000); 109 /// AArch32 Instruction Set Attribute Register 1 110 pub const ID_ISAR1_EL1: Self = Self::System(0b11_000_0000_0010_001); 111 /// AArch32 Instruction Set Attribute Register 2 112 pub const ID_ISAR2_EL1: Self = Self::System(0b11_000_0000_0010_010); 113 /// AArch32 Instruction Set Attribute Register 3 114 pub const ID_ISAR3_EL1: Self = Self::System(0b11_000_0000_0010_011); 115 /// AArch32 Instruction Set Attribute Register 4 116 pub const ID_ISAR4_EL1: Self = Self::System(0b11_000_0000_0010_100); 117 /// AArch32 Instruction Set Attribute Register 5 118 pub const ID_ISAR5_EL1: Self = Self::System(0b11_000_0000_0010_101); 119 /// AArch32 Memory Model Feature Register 4 120 pub const ID_MMFR4_EL1: Self = Self::System(0b11_000_0000_0010_110); 121 /// AArch32 Instruction Set Attribute Register 6 122 pub const ID_ISAR6_EL1: Self = Self::System(0b11_000_0000_0010_111); 123 /// AArch32 Media And VFP Feature Register 0 124 pub const MVFR0_EL1: Self = Self::System(0b11_000_0000_0011_000); 125 /// AArch32 Media And VFP Feature Register 1 126 pub const MVFR1_EL1: Self = Self::System(0b11_000_0000_0011_001); 127 /// AArch32 Media And VFP Feature Register 2 128 pub const MVFR2_EL1: Self = Self::System(0b11_000_0000_0011_010); 129 /// AArch32 Processor Feature Register 2 130 pub const ID_PFR2_EL1: Self = Self::System(0b11_000_0000_0011_100); 131 /// Debug Feature Register 1 132 pub const ID_DFR1_EL1: Self = Self::System(0b11_000_0000_0011_101); 133 /// AArch32 Memory Model Feature Register 5 134 pub const ID_MMFR5_EL1: Self = Self::System(0b11_000_0000_0011_110); 135 /// AArch64 Processor Feature Register 0 136 pub const ID_AA64PFR0_EL1: Self = Self::System(0b11_000_0000_0100_000); 137 /// AArch64 Processor Feature Register 1 138 pub const ID_AA64PFR1_EL1: Self = Self::System(0b11_000_0000_0100_001); 139 /// SVE Feature ID Register 0 140 pub const ID_AA64ZFR0_EL1: Self = Self::System(0b11_000_0000_0100_100); 141 /// SME Feature ID Register 0 142 pub const ID_AA64SMFR0_EL1: Self = Self::System(0b11_000_0000_0100_101); 143 /// AArch64 Debug Feature Register 0 144 pub const ID_AA64DFR0_EL1: Self = Self::System(0b11_000_0000_0101_000); 145 /// AArch64 Debug Feature Register 1 146 pub const ID_AA64DFR1_EL1: Self = Self::System(0b11_000_0000_0101_001); 147 /// AArch64 Auxiliary Feature Register 0 148 pub const ID_AA64AFR0_EL1: Self = Self::System(0b11_000_0000_0101_100); 149 /// AArch64 Auxiliary Feature Register 1 150 pub const ID_AA64AFR1_EL1: Self = Self::System(0b11_000_0000_0101_101); 151 /// AArch64 Instruction Set Attribute Register 0 152 pub const ID_AA64ISAR0_EL1: Self = Self::System(0b11_000_0000_0110_000); 153 /// AArch64 Instruction Set Attribute Register 1 154 pub const ID_AA64ISAR1_EL1: Self = Self::System(0b11_000_0000_0110_001); 155 /// AArch64 Instruction Set Attribute Register 2 156 pub const ID_AA64ISAR2_EL1: Self = Self::System(0b11_000_0000_0110_010); 157 /// AArch64 Memory Model Feature Register 0 158 pub const ID_AA64MMFR0_EL1: Self = Self::System(0b11_000_0000_0111_000); 159 /// AArch64 Memory Model Feature Register 1 160 pub const ID_AA64MMFR1_EL1: Self = Self::System(0b11_000_0000_0111_001); 161 /// AArch64 Memory Model Feature Register 2 162 pub const ID_AA64MMFR2_EL1: Self = Self::System(0b11_000_0000_0111_010); 163 /// System Control Register (EL1) 164 pub const SCTLR_EL1: Self = Self::System(0b11_000_0001_0000_000); 165 /// Auxiliary Control Register (EL1) 166 pub const ACTLR_EL1: Self = Self::System(0b11_000_0001_0000_001); 167 /// Architectural Feature Access Control Register 168 pub const CPACR_EL1: Self = Self::System(0b11_000_0001_0000_010); 169 /// Random Allocation Tag Seed Register 170 pub const RGSR_EL1: Self = Self::System(0b11_000_0001_0000_101); 171 /// Tag Control Register 172 pub const GCR_EL1: Self = Self::System(0b11_000_0001_0000_110); 173 /// SVE Control Register (EL1) 174 pub const ZCR_EL1: Self = Self::System(0b11_000_0001_0010_000); 175 /// Trace Filter Control Register (EL1) 176 pub const TRFCR_EL1: Self = Self::System(0b11_000_0001_0010_001); 177 /// Streaming Mode Priority Register 178 pub const SMPRI_EL1: Self = Self::System(0b11_000_0001_0010_100); 179 /// SME Control Register (EL1) 180 pub const SMCR_EL1: Self = Self::System(0b11_000_0001_0010_110); 181 /// Translation Table Base Register 0 (EL1) 182 pub const TTBR0_EL1: Self = Self::System(0b11_000_0010_0000_000); 183 /// Translation Table Base Register 1 (EL1) 184 pub const TTBR1_EL1: Self = Self::System(0b11_000_0010_0000_001); 185 /// Translation Control Register (EL1) 186 pub const TCR_EL1: Self = Self::System(0b11_000_0010_0000_010); 187 /// Pointer Authentication Key A For Instruction (bits[63:0]) 188 pub const APIAKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_000); 189 /// Pointer Authentication Key A For Instruction (bits[127:64]) 190 pub const APIAKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_001); 191 /// Pointer Authentication Key B For Instruction (bits[63:0]) 192 pub const APIBKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_010); 193 /// Pointer Authentication Key B For Instruction (bits[127:64]) 194 pub const APIBKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_011); 195 /// Pointer Authentication Key A For Data (bits[63:0]) 196 pub const APDAKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_000); 197 /// Pointer Authentication Key A For Data (bits[127:64]) 198 pub const APDAKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_001); 199 /// Pointer Authentication Key B For Data (bits[63:0]) 200 pub const APDBKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_010); 201 /// Pointer Authentication Key B For Data (bits[127:64]) 202 pub const APDBKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_011); 203 /// Pointer Authentication Key A For Code (bits[63:0]) 204 pub const APGAKEYLO_EL1: Self = Self::System(0b11_000_0010_0011_000); 205 /// Pointer Authentication Key A For Code (bits[127:64]) 206 pub const APGAKEYHI_EL1: Self = Self::System(0b11_000_0010_0011_001); 207 /// Saved Program Status Register (EL1) 208 pub const SPSR_EL1: Self = Self::System(0b11_000_0100_0000_000); 209 /// Exception Link Register (EL1) 210 pub const ELR_EL1: Self = Self::System(0b11_000_0100_0000_001); 211 /// Stack Pointer (EL0) 212 pub const SP_EL0: Self = Self::System(0b11_000_0100_0001_000); 213 /// Interrupt Controller Interrupt Priority Mask Register 214 pub const ICC_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000); 215 /// Interrupt Controller Virtual Interrupt Priority Mask Register 216 pub const ICV_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000); 217 /// Auxiliary Fault Status Register 0 (EL1) 218 pub const AFSR0_EL1: Self = Self::System(0b11_000_0101_0001_000); 219 /// Auxiliary Fault Status Register 1 (EL1) 220 pub const AFSR1_EL1: Self = Self::System(0b11_000_0101_0001_001); 221 /// Exception Syndrome Register (EL1) 222 pub const ESR_EL1: Self = Self::System(0b11_000_0101_0010_000); 223 /// Error Record ID Register 224 pub const ERRIDR_EL1: Self = Self::System(0b11_000_0101_0011_000); 225 /// Error Record Select Register 226 pub const ERRSELR_EL1: Self = Self::System(0b11_000_0101_0011_001); 227 /// Selected Error Record Feature Register 228 pub const ERXFR_EL1: Self = Self::System(0b11_000_0101_0100_000); 229 /// Selected Error Record Control Register 230 pub const ERXCTLR_EL1: Self = Self::System(0b11_000_0101_0100_001); 231 /// Selected Error Record Primary Status Register 232 pub const ERXSTATUS_EL1: Self = Self::System(0b11_000_0101_0100_010); 233 /// Selected Error Record Address Register 234 pub const ERXADDR_EL1: Self = Self::System(0b11_000_0101_0100_011); 235 /// Selected Pseudo-fault Generation Feature Register 236 pub const ERXPFGF_EL1: Self = Self::System(0b11_000_0101_0100_100); 237 /// Selected Pseudo-fault Generation Control Register 238 pub const ERXPFGCTL_EL1: Self = Self::System(0b11_000_0101_0100_101); 239 /// Selected Pseudo-fault Generation Countdown Register 240 pub const ERXPFGCDN_EL1: Self = Self::System(0b11_000_0101_0100_110); 241 /// Selected Error Record Miscellaneous Register 0 242 pub const ERXMISC0_EL1: Self = Self::System(0b11_000_0101_0101_000); 243 /// Selected Error Record Miscellaneous Register 1 244 pub const ERXMISC1_EL1: Self = Self::System(0b11_000_0101_0101_001); 245 /// Selected Error Record Miscellaneous Register 2 246 pub const ERXMISC2_EL1: Self = Self::System(0b11_000_0101_0101_010); 247 /// Selected Error Record Miscellaneous Register 3 248 pub const ERXMISC3_EL1: Self = Self::System(0b11_000_0101_0101_011); 249 /// Tag Fault Status Register (EL1) 250 pub const TFSR_EL1: Self = Self::System(0b11_000_0101_0110_000); 251 /// Tag Fault Status Register (EL0) 252 pub const TFSRE0_EL1: Self = Self::System(0b11_000_0101_0110_001); 253 /// Fault Address Register (EL1) 254 pub const FAR_EL1: Self = Self::System(0b11_000_0110_0000_000); 255 /// Physical Address Register 256 pub const PAR_EL1: Self = Self::System(0b11_000_0111_0100_000); 257 /// Statistical Profiling Control Register (EL1) 258 pub const PMSCR_EL1: Self = Self::System(0b11_000_1001_1001_000); 259 /// Sampling Inverted Event Filter Register 260 pub const PMSNEVFR_EL1: Self = Self::System(0b11_000_1001_1001_001); 261 /// Sampling Interval Counter Register 262 pub const PMSICR_EL1: Self = Self::System(0b11_000_1001_1001_010); 263 /// Sampling Interval Reload Register 264 pub const PMSIRR_EL1: Self = Self::System(0b11_000_1001_1001_011); 265 /// Sampling Filter Control Register 266 pub const PMSFCR_EL1: Self = Self::System(0b11_000_1001_1001_100); 267 /// Sampling Event Filter Register 268 pub const PMSEVFR_EL1: Self = Self::System(0b11_000_1001_1001_101); 269 /// Sampling Latency Filter Register 270 pub const PMSLATFR_EL1: Self = Self::System(0b11_000_1001_1001_110); 271 /// Sampling Profiling ID Register 272 pub const PMSIDR_EL1: Self = Self::System(0b11_000_1001_1001_111); 273 /// Profiling Buffer Limit Address Register 274 pub const PMBLIMITR_EL1: Self = Self::System(0b11_000_1001_1010_000); 275 /// Profiling Buffer Write Pointer Register 276 pub const PMBPTR_EL1: Self = Self::System(0b11_000_1001_1010_001); 277 /// Profiling Buffer Status/syndrome Register 278 pub const PMBSR_EL1: Self = Self::System(0b11_000_1001_1010_011); 279 /// Profiling Buffer ID Register 280 pub const PMBIDR_EL1: Self = Self::System(0b11_000_1001_1010_111); 281 /// Trace Buffer Limit Address Register 282 pub const TRBLIMITR_EL1: Self = Self::System(0b11_000_1001_1011_000); 283 /// Trace Buffer Write Pointer Register 284 pub const TRBPTR_EL1: Self = Self::System(0b11_000_1001_1011_001); 285 /// Trace Buffer Base Address Register 286 pub const TRBBASER_EL1: Self = Self::System(0b11_000_1001_1011_010); 287 /// Trace Buffer Status/syndrome Register 288 pub const TRBSR_EL1: Self = Self::System(0b11_000_1001_1011_011); 289 /// Trace Buffer Memory Attribute Register 290 pub const TRBMAR_EL1: Self = Self::System(0b11_000_1001_1011_100); 291 /// Trace Buffer Trigger Counter Register 292 pub const TRBTRG_EL1: Self = Self::System(0b11_000_1001_1011_110); 293 /// Trace Buffer ID Register 294 pub const TRBIDR_EL1: Self = Self::System(0b11_000_1001_1011_111); 295 /// Performance Monitors Interrupt Enable Set Register 296 pub const PMINTENSET_EL1: Self = Self::System(0b11_000_1001_1110_001); 297 /// Performance Monitors Interrupt Enable Clear Register 298 pub const PMINTENCLR_EL1: Self = Self::System(0b11_000_1001_1110_010); 299 /// Performance Monitors Machine Identification Register 300 pub const PMMIR_EL1: Self = Self::System(0b11_000_1001_1110_110); 301 /// Memory Attribute Indirection Register (EL1) 302 pub const MAIR_EL1: Self = Self::System(0b11_000_1010_0010_000); 303 /// Auxiliary Memory Attribute Indirection Register (EL1) 304 pub const AMAIR_EL1: Self = Self::System(0b11_000_1010_0011_000); 305 /// LORegion Start Address (EL1) 306 pub const LORSA_EL1: Self = Self::System(0b11_000_1010_0100_000); 307 /// LORegion End Address (EL1) 308 pub const LOREA_EL1: Self = Self::System(0b11_000_1010_0100_001); 309 /// LORegion Number (EL1) 310 pub const LORN_EL1: Self = Self::System(0b11_000_1010_0100_010); 311 /// LORegion Control (EL1) 312 pub const LORC_EL1: Self = Self::System(0b11_000_1010_0100_011); 313 /// MPAM ID Register (EL1) 314 pub const MPAMIDR_EL1: Self = Self::System(0b11_000_1010_0100_100); 315 /// LORegionID (EL1) 316 pub const LORID_EL1: Self = Self::System(0b11_000_1010_0100_111); 317 /// MPAM1 Register (EL1) 318 pub const MPAM1_EL1: Self = Self::System(0b11_000_1010_0101_000); 319 /// MPAM0 Register (EL1) 320 pub const MPAM0_EL1: Self = Self::System(0b11_000_1010_0101_001); 321 /// MPAM Streaming Mode Register 322 pub const MPAMSM_EL1: Self = Self::System(0b11_000_1010_0101_011); 323 /// Vector Base Address Register (EL1) 324 pub const VBAR_EL1: Self = Self::System(0b11_000_1100_0000_000); 325 /// Reset Vector Base Address Register (if EL2 And EL3 Not Implemented) 326 pub const RVBAR_EL1: Self = Self::System(0b11_000_1100_0000_001); 327 /// Reset Management Register (EL1) 328 pub const RMR_EL1: Self = Self::System(0b11_000_1100_0000_010); 329 /// Interrupt Status Register 330 pub const ISR_EL1: Self = Self::System(0b11_000_1100_0001_000); 331 /// Deferred Interrupt Status Register 332 pub const DISR_EL1: Self = Self::System(0b11_000_1100_0001_001); 333 /// Interrupt Controller Interrupt Acknowledge Register 0 334 pub const ICC_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000); 335 /// Interrupt Controller Virtual Interrupt Acknowledge Register 0 336 pub const ICV_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000); 337 /// Interrupt Controller End Of Interrupt Register 0 338 pub const ICC_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001); 339 /// Interrupt Controller Virtual End Of Interrupt Register 0 340 pub const ICV_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001); 341 /// Interrupt Controller Highest Priority Pending Interrupt Register 0 342 pub const ICC_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010); 343 /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register 344 /// 0 345 pub const ICV_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010); 346 /// Interrupt Controller Binary Point Register 0 347 pub const ICC_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011); 348 /// Interrupt Controller Virtual Binary Point Register 0 349 pub const ICV_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011); 350 /// Interrupt Controller Active Priorities Group 0 Registers - 0 351 pub const ICC_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100); 352 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 0 353 pub const ICV_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100); 354 /// Interrupt Controller Active Priorities Group 0 Registers - 1 355 pub const ICC_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101); 356 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 1 357 pub const ICV_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101); 358 /// Interrupt Controller Active Priorities Group 0 Registers - 2 359 pub const ICC_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110); 360 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 2 361 pub const ICV_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110); 362 /// Interrupt Controller Active Priorities Group 0 Registers - 3 363 pub const ICC_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111); 364 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 3 365 pub const ICV_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111); 366 /// Interrupt Controller Active Priorities Group 1 Registers - 0 367 pub const ICC_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000); 368 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 0 369 pub const ICV_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000); 370 /// Interrupt Controller Active Priorities Group 1 Registers - 1 371 pub const ICC_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001); 372 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 1 373 pub const ICV_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001); 374 /// Interrupt Controller Active Priorities Group 1 Registers - 2 375 pub const ICC_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010); 376 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 2 377 pub const ICV_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010); 378 /// Interrupt Controller Active Priorities Group 1 Registers - 3 379 pub const ICC_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011); 380 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 3 381 pub const ICV_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011); 382 /// Interrupt Controller Non-maskable Interrupt Acknowledge Register 1 383 pub const ICC_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101); 384 /// Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register 385 /// 1 386 pub const ICV_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101); 387 /// Interrupt Controller Deactivate Interrupt Register 388 pub const ICC_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001); 389 /// Interrupt Controller Deactivate Virtual Interrupt Register 390 pub const ICV_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001); 391 /// Interrupt Controller Running Priority Register 392 pub const ICC_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011); 393 /// Interrupt Controller Virtual Running Priority Register 394 pub const ICV_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011); 395 /// Interrupt Controller Software Generated Interrupt Group 1 Register 396 pub const ICC_SGI1R_EL1: Self = Self::System(0b11_000_1100_1011_101); 397 /// Interrupt Controller Alias Software Generated Interrupt Group 1 Register 398 pub const ICC_ASGI1R_EL1: Self = Self::System(0b11_000_1100_1011_110); 399 /// Interrupt Controller Software Generated Interrupt Group 0 Register 400 pub const ICC_SGI0R_EL1: Self = Self::System(0b11_000_1100_1011_111); 401 /// Interrupt Controller Interrupt Acknowledge Register 1 402 pub const ICC_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000); 403 /// Interrupt Controller Virtual Interrupt Acknowledge Register 1 404 pub const ICV_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000); 405 /// Interrupt Controller End Of Interrupt Register 1 406 pub const ICC_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001); 407 /// Interrupt Controller Virtual End Of Interrupt Register 1 408 pub const ICV_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001); 409 /// Interrupt Controller Highest Priority Pending Interrupt Register 1 410 pub const ICC_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010); 411 /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register 412 /// 1 413 pub const ICV_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010); 414 /// Interrupt Controller Binary Point Register 1 415 pub const ICC_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011); 416 /// Interrupt Controller Virtual Binary Point Register 1 417 pub const ICV_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011); 418 /// Interrupt Controller Control Register (EL1) 419 pub const ICC_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100); 420 /// Interrupt Controller Virtual Control Register 421 pub const ICV_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100); 422 /// Interrupt Controller System Register Enable Register (EL1) 423 pub const ICC_SRE_EL1: Self = Self::System(0b11_000_1100_1100_101); 424 /// Interrupt Controller Interrupt Group 0 Enable Register 425 pub const ICC_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110); 426 /// Interrupt Controller Virtual Interrupt Group 0 Enable Register 427 pub const ICV_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110); 428 /// Interrupt Controller Interrupt Group 1 Enable Register 429 pub const ICC_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111); 430 /// Interrupt Controller Virtual Interrupt Group 1 Enable Register 431 pub const ICV_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111); 432 /// Context ID Register (EL1) 433 pub const CONTEXTIDR_EL1: Self = Self::System(0b11_000_1101_0000_001); 434 /// EL1 Software Thread ID Register 435 pub const TPIDR_EL1: Self = Self::System(0b11_000_1101_0000_100); 436 /// Accelerator Data 437 pub const ACCDATA_EL1: Self = Self::System(0b11_000_1101_0000_101); 438 /// EL1 Read/Write Software Context Number 439 pub const SCXTNUM_EL1: Self = Self::System(0b11_000_1101_0000_111); 440 /// Counter-timer Kernel Control Register 441 pub const CNTKCTL_EL1: Self = Self::System(0b11_000_1110_0001_000); 442 /// Current Cache Size ID Register 443 pub const CCSIDR_EL1: Self = Self::System(0b11_001_0000_0000_000); 444 /// Cache Level ID Register 445 pub const CLIDR_EL1: Self = Self::System(0b11_001_0000_0000_001); 446 /// Current Cache Size ID Register 2 447 pub const CCSIDR2_EL1: Self = Self::System(0b11_001_0000_0000_010); 448 /// Multiple Tag Transfer ID Register 449 pub const GMID_EL1: Self = Self::System(0b11_001_0000_0000_100); 450 /// Streaming Mode Identification Register 451 pub const SMIDR_EL1: Self = Self::System(0b11_001_0000_0000_110); 452 /// Auxiliary ID Register 453 pub const AIDR_EL1: Self = Self::System(0b11_001_0000_0000_111); 454 /// Cache Size Selection Register 455 pub const CSSELR_EL1: Self = Self::System(0b11_010_0000_0000_000); 456 /// Cache Type Register 457 pub const CTR_EL0: Self = Self::System(0b11_011_0000_0000_001); 458 /// Data Cache Zero ID Register 459 pub const DCZID_EL0: Self = Self::System(0b11_011_0000_0000_111); 460 /// Random Number 461 pub const RNDR: Self = Self::System(0b11_011_0010_0100_000); 462 /// Reseeded Random Number 463 pub const RNDRRS: Self = Self::System(0b11_011_0010_0100_001); 464 /// Streaming Vector Control Register 465 pub const SVCR: Self = Self::System(0b11_011_0100_0010_010); 466 /// Floating-point Control Register 467 pub const FPCR: Self = Self::System(0b11_011_0100_0100_000); 468 /// Floating-point Status Register 469 pub const FPSR: Self = Self::System(0b11_011_0100_0100_001); 470 /// Debug Saved Program Status Register 471 pub const DSPSR_EL0: Self = Self::System(0b11_011_0100_0101_000); 472 /// Debug Link Register 473 pub const DLR_EL0: Self = Self::System(0b11_011_0100_0101_001); 474 /// Performance Monitors Control Register 475 pub const PMCR_EL0: Self = Self::System(0b11_011_1001_1100_000); 476 /// Performance Monitors Count Enable Set Register 477 pub const PMCNTENSET_EL0: Self = Self::System(0b11_011_1001_1100_001); 478 /// Performance Monitors Count Enable Clear Register 479 pub const PMCNTENCLR_EL0: Self = Self::System(0b11_011_1001_1100_010); 480 /// Performance Monitors Overflow Flag Status Clear Register 481 pub const PMOVSCLR_EL0: Self = Self::System(0b11_011_1001_1100_011); 482 /// Performance Monitors Software Increment Register 483 pub const PMSWINC_EL0: Self = Self::System(0b11_011_1001_1100_100); 484 /// Performance Monitors Event Counter Selection Register 485 pub const PMSELR_EL0: Self = Self::System(0b11_011_1001_1100_101); 486 /// Performance Monitors Common Event Identification Register 0 487 pub const PMCEID0_EL0: Self = Self::System(0b11_011_1001_1100_110); 488 /// Performance Monitors Common Event Identification Register 1 489 pub const PMCEID1_EL0: Self = Self::System(0b11_011_1001_1100_111); 490 /// Performance Monitors Cycle Count Register 491 pub const PMCCNTR_EL0: Self = Self::System(0b11_011_1001_1101_000); 492 /// Performance Monitors Selected Event Type Register 493 pub const PMXEVTYPER_EL0: Self = Self::System(0b11_011_1001_1101_001); 494 /// Performance Monitors Selected Event Count Register 495 pub const PMXEVCNTR_EL0: Self = Self::System(0b11_011_1001_1101_010); 496 /// Performance Monitors User Enable Register 497 pub const PMUSERENR_EL0: Self = Self::System(0b11_011_1001_1110_000); 498 /// Performance Monitors Overflow Flag Status Set Register 499 pub const PMOVSSET_EL0: Self = Self::System(0b11_011_1001_1110_011); 500 /// EL0 Read/Write Software Thread ID Register 501 pub const TPIDR_EL0: Self = Self::System(0b11_011_1101_0000_010); 502 /// EL0 Read-Only Software Thread ID Register 503 pub const TPIDRRO_EL0: Self = Self::System(0b11_011_1101_0000_011); 504 /// EL0 Read/Write Software Thread ID Register 2 505 pub const TPIDR2_EL0: Self = Self::System(0b11_011_1101_0000_101); 506 /// EL0 Read/Write Software Context Number 507 pub const SCXTNUM_EL0: Self = Self::System(0b11_011_1101_0000_111); 508 /// Activity Monitors Control Register 509 pub const AMCR_EL0: Self = Self::System(0b11_011_1101_0010_000); 510 /// Activity Monitors Configuration Register 511 pub const AMCFGR_EL0: Self = Self::System(0b11_011_1101_0010_001); 512 /// Activity Monitors Counter Group Configuration Register 513 pub const AMCGCR_EL0: Self = Self::System(0b11_011_1101_0010_010); 514 /// Activity Monitors User Enable Register 515 pub const AMUSERENR_EL0: Self = Self::System(0b11_011_1101_0010_011); 516 /// Activity Monitors Count Enable Clear Register 0 517 pub const AMCNTENCLR0_EL0: Self = Self::System(0b11_011_1101_0010_100); 518 /// Activity Monitors Count Enable Set Register 0 519 pub const AMCNTENSET0_EL0: Self = Self::System(0b11_011_1101_0010_101); 520 /// Activity Monitors Counter Group 1 Identification Register 521 pub const AMCG1IDR_EL0: Self = Self::System(0b11_011_1101_0010_110); 522 /// Activity Monitors Count Enable Clear Register 1 523 pub const AMCNTENCLR1_EL0: Self = Self::System(0b11_011_1101_0011_000); 524 /// Activity Monitors Count Enable Set Register 1 525 pub const AMCNTENSET1_EL0: Self = Self::System(0b11_011_1101_0011_001); 526 /// Activity Monitors Event Counter Registers 0 - 0 527 pub const AMEVCNTR00_EL0: Self = Self::System(0b11_011_1101_0100_000); 528 /// Activity Monitors Event Counter Registers 0 - 1 529 pub const AMEVCNTR01_EL0: Self = Self::System(0b11_011_1101_0100_001); 530 /// Activity Monitors Event Counter Registers 0 - 2 531 pub const AMEVCNTR02_EL0: Self = Self::System(0b11_011_1101_0100_010); 532 /// Activity Monitors Event Counter Registers 0 - 3 533 pub const AMEVCNTR03_EL0: Self = Self::System(0b11_011_1101_0100_011); 534 /// Activity Monitors Event Type Registers 0 - 0 535 pub const AMEVTYPER00_EL0: Self = Self::System(0b11_011_1101_0110_000); 536 /// Activity Monitors Event Type Registers 0 - 1 537 pub const AMEVTYPER01_EL0: Self = Self::System(0b11_011_1101_0110_001); 538 /// Activity Monitors Event Type Registers 0 - 2 539 pub const AMEVTYPER02_EL0: Self = Self::System(0b11_011_1101_0110_010); 540 /// Activity Monitors Event Type Registers 0 - 3 541 pub const AMEVTYPER03_EL0: Self = Self::System(0b11_011_1101_0110_011); 542 /// Activity Monitors Event Counter Registers 1 - 0 543 pub const AMEVCNTR10_EL0: Self = Self::System(0b11_011_1101_1100_000); 544 /// Activity Monitors Event Counter Registers 1 - 1 545 pub const AMEVCNTR11_EL0: Self = Self::System(0b11_011_1101_1100_001); 546 /// Activity Monitors Event Counter Registers 1 - 2 547 pub const AMEVCNTR12_EL0: Self = Self::System(0b11_011_1101_1100_010); 548 /// Activity Monitors Event Counter Registers 1 - 3 549 pub const AMEVCNTR13_EL0: Self = Self::System(0b11_011_1101_1100_011); 550 /// Activity Monitors Event Counter Registers 1 - 4 551 pub const AMEVCNTR14_EL0: Self = Self::System(0b11_011_1101_1100_100); 552 /// Activity Monitors Event Counter Registers 1 - 5 553 pub const AMEVCNTR15_EL0: Self = Self::System(0b11_011_1101_1100_101); 554 /// Activity Monitors Event Counter Registers 1 - 6 555 pub const AMEVCNTR16_EL0: Self = Self::System(0b11_011_1101_1100_110); 556 /// Activity Monitors Event Counter Registers 1 - 7 557 pub const AMEVCNTR17_EL0: Self = Self::System(0b11_011_1101_1100_111); 558 /// Activity Monitors Event Counter Registers 1 - 8 559 pub const AMEVCNTR18_EL0: Self = Self::System(0b11_011_1101_1101_000); 560 /// Activity Monitors Event Counter Registers 1 - 9 561 pub const AMEVCNTR19_EL0: Self = Self::System(0b11_011_1101_1101_001); 562 /// Activity Monitors Event Counter Registers 1 - 10 563 pub const AMEVCNTR110_EL0: Self = Self::System(0b11_011_1101_1101_010); 564 /// Activity Monitors Event Counter Registers 1 - 11 565 pub const AMEVCNTR111_EL0: Self = Self::System(0b11_011_1101_1101_011); 566 /// Activity Monitors Event Counter Registers 1 - 12 567 pub const AMEVCNTR112_EL0: Self = Self::System(0b11_011_1101_1101_100); 568 /// Activity Monitors Event Counter Registers 1 - 13 569 pub const AMEVCNTR113_EL0: Self = Self::System(0b11_011_1101_1101_101); 570 /// Activity Monitors Event Counter Registers 1 - 14 571 pub const AMEVCNTR114_EL0: Self = Self::System(0b11_011_1101_1101_110); 572 /// Activity Monitors Event Counter Registers 1 - 15 573 pub const AMEVCNTR115_EL0: Self = Self::System(0b11_011_1101_1101_111); 574 /// Activity Monitors Event Type Registers 1 - 0 575 pub const AMEVTYPER10_EL0: Self = Self::System(0b11_011_1101_1110_000); 576 /// Activity Monitors Event Type Registers 1 - 1 577 pub const AMEVTYPER11_EL0: Self = Self::System(0b11_011_1101_1110_001); 578 /// Activity Monitors Event Type Registers 1 - 2 579 pub const AMEVTYPER12_EL0: Self = Self::System(0b11_011_1101_1110_010); 580 /// Activity Monitors Event Type Registers 1 - 3 581 pub const AMEVTYPER13_EL0: Self = Self::System(0b11_011_1101_1110_011); 582 /// Activity Monitors Event Type Registers 1 - 4 583 pub const AMEVTYPER14_EL0: Self = Self::System(0b11_011_1101_1110_100); 584 /// Activity Monitors Event Type Registers 1 - 5 585 pub const AMEVTYPER15_EL0: Self = Self::System(0b11_011_1101_1110_101); 586 /// Activity Monitors Event Type Registers 1 - 6 587 pub const AMEVTYPER16_EL0: Self = Self::System(0b11_011_1101_1110_110); 588 /// Activity Monitors Event Type Registers 1 - 7 589 pub const AMEVTYPER17_EL0: Self = Self::System(0b11_011_1101_1110_111); 590 /// Activity Monitors Event Type Registers 1 - 8 591 pub const AMEVTYPER18_EL0: Self = Self::System(0b11_011_1101_1111_000); 592 /// Activity Monitors Event Type Registers 1 - 9 593 pub const AMEVTYPER19_EL0: Self = Self::System(0b11_011_1101_1111_001); 594 /// Activity Monitors Event Type Registers 1 - 10 595 pub const AMEVTYPER110_EL0: Self = Self::System(0b11_011_1101_1111_010); 596 /// Activity Monitors Event Type Registers 1 - 11 597 pub const AMEVTYPER111_EL0: Self = Self::System(0b11_011_1101_1111_011); 598 /// Activity Monitors Event Type Registers 1 - 12 599 pub const AMEVTYPER112_EL0: Self = Self::System(0b11_011_1101_1111_100); 600 /// Activity Monitors Event Type Registers 1 - 13 601 pub const AMEVTYPER113_EL0: Self = Self::System(0b11_011_1101_1111_101); 602 /// Activity Monitors Event Type Registers 1 - 14 603 pub const AMEVTYPER114_EL0: Self = Self::System(0b11_011_1101_1111_110); 604 /// Activity Monitors Event Type Registers 1 - 15 605 pub const AMEVTYPER115_EL0: Self = Self::System(0b11_011_1101_1111_111); 606 /// Counter-timer Frequency Register 607 pub const CNTFRQ_EL0: Self = Self::System(0b11_011_1110_0000_000); 608 /// Counter-timer Physical Count Register 609 pub const CNTPCT_EL0: Self = Self::System(0b11_011_1110_0000_001); 610 /// Counter-timer Virtual Count Register 611 pub const CNTVCT_EL0: Self = Self::System(0b11_011_1110_0000_010); 612 /// Counter-timer Self-Synchronized Physical Count Register 613 pub const CNTPCTSS_EL0: Self = Self::System(0b11_011_1110_0000_101); 614 /// Counter-timer Self-Synchronized Virtual Count Register 615 pub const CNTVCTSS_EL0: Self = Self::System(0b11_011_1110_0000_110); 616 /// Counter-timer Physical Timer TimerValue Register 617 pub const CNTP_TVAL_EL0: Self = Self::System(0b11_011_1110_0010_000); 618 /// Counter-timer Physical Timer Control Register 619 pub const CNTP_CTL_EL0: Self = Self::System(0b11_011_1110_0010_001); 620 /// Counter-timer Physical Timer CompareValue Register 621 pub const CNTP_CVAL_EL0: Self = Self::System(0b11_011_1110_0010_010); 622 /// Counter-timer Virtual Timer TimerValue Register 623 pub const CNTV_TVAL_EL0: Self = Self::System(0b11_011_1110_0011_000); 624 /// Counter-timer Virtual Timer Control Register 625 pub const CNTV_CTL_EL0: Self = Self::System(0b11_011_1110_0011_001); 626 /// Counter-timer Virtual Timer CompareValue Register 627 pub const CNTV_CVAL_EL0: Self = Self::System(0b11_011_1110_0011_010); 628 /// Performance Monitors Event Count Registers - 0 629 pub const PMEVCNTR0_EL0: Self = Self::System(0b11_011_1110_1000_000); 630 /// Performance Monitors Event Count Registers - 1 631 pub const PMEVCNTR1_EL0: Self = Self::System(0b11_011_1110_1000_001); 632 /// Performance Monitors Event Count Registers - 2 633 pub const PMEVCNTR2_EL0: Self = Self::System(0b11_011_1110_1000_010); 634 /// Performance Monitors Event Count Registers - 3 635 pub const PMEVCNTR3_EL0: Self = Self::System(0b11_011_1110_1000_011); 636 /// Performance Monitors Event Count Registers - 4 637 pub const PMEVCNTR4_EL0: Self = Self::System(0b11_011_1110_1000_100); 638 /// Performance Monitors Event Count Registers - 5 639 pub const PMEVCNTR5_EL0: Self = Self::System(0b11_011_1110_1000_101); 640 /// Performance Monitors Event Count Registers - 6 641 pub const PMEVCNTR6_EL0: Self = Self::System(0b11_011_1110_1000_110); 642 /// Performance Monitors Event Count Registers - 7 643 pub const PMEVCNTR7_EL0: Self = Self::System(0b11_011_1110_1000_111); 644 /// Performance Monitors Event Count Registers - 8 645 pub const PMEVCNTR8_EL0: Self = Self::System(0b11_011_1110_1001_000); 646 /// Performance Monitors Event Count Registers - 9 647 pub const PMEVCNTR9_EL0: Self = Self::System(0b11_011_1110_1001_001); 648 /// Performance Monitors Event Count Registers - 10 649 pub const PMEVCNTR10_EL0: Self = Self::System(0b11_011_1110_1001_010); 650 /// Performance Monitors Event Count Registers - 11 651 pub const PMEVCNTR11_EL0: Self = Self::System(0b11_011_1110_1001_011); 652 /// Performance Monitors Event Count Registers - 12 653 pub const PMEVCNTR12_EL0: Self = Self::System(0b11_011_1110_1001_100); 654 /// Performance Monitors Event Count Registers - 13 655 pub const PMEVCNTR13_EL0: Self = Self::System(0b11_011_1110_1001_101); 656 /// Performance Monitors Event Count Registers - 14 657 pub const PMEVCNTR14_EL0: Self = Self::System(0b11_011_1110_1001_110); 658 /// Performance Monitors Event Count Registers - 15 659 pub const PMEVCNTR15_EL0: Self = Self::System(0b11_011_1110_1001_111); 660 /// Performance Monitors Event Count Registers - 16 661 pub const PMEVCNTR16_EL0: Self = Self::System(0b11_011_1110_1010_000); 662 /// Performance Monitors Event Count Registers - 17 663 pub const PMEVCNTR17_EL0: Self = Self::System(0b11_011_1110_1010_001); 664 /// Performance Monitors Event Count Registers - 18 665 pub const PMEVCNTR18_EL0: Self = Self::System(0b11_011_1110_1010_010); 666 /// Performance Monitors Event Count Registers - 19 667 pub const PMEVCNTR19_EL0: Self = Self::System(0b11_011_1110_1010_011); 668 /// Performance Monitors Event Count Registers - 20 669 pub const PMEVCNTR20_EL0: Self = Self::System(0b11_011_1110_1010_100); 670 /// Performance Monitors Event Count Registers - 21 671 pub const PMEVCNTR21_EL0: Self = Self::System(0b11_011_1110_1010_101); 672 /// Performance Monitors Event Count Registers - 22 673 pub const PMEVCNTR22_EL0: Self = Self::System(0b11_011_1110_1010_110); 674 /// Performance Monitors Event Count Registers - 23 675 pub const PMEVCNTR23_EL0: Self = Self::System(0b11_011_1110_1010_111); 676 /// Performance Monitors Event Count Registers - 24 677 pub const PMEVCNTR24_EL0: Self = Self::System(0b11_011_1110_1011_000); 678 /// Performance Monitors Event Count Registers - 25 679 pub const PMEVCNTR25_EL0: Self = Self::System(0b11_011_1110_1011_001); 680 /// Performance Monitors Event Count Registers - 26 681 pub const PMEVCNTR26_EL0: Self = Self::System(0b11_011_1110_1011_010); 682 /// Performance Monitors Event Count Registers - 27 683 pub const PMEVCNTR27_EL0: Self = Self::System(0b11_011_1110_1011_011); 684 /// Performance Monitors Event Count Registers - 28 685 pub const PMEVCNTR28_EL0: Self = Self::System(0b11_011_1110_1011_100); 686 /// Performance Monitors Event Count Registers - 29 687 pub const PMEVCNTR29_EL0: Self = Self::System(0b11_011_1110_1011_101); 688 /// Performance Monitors Event Count Registers - 30 689 pub const PMEVCNTR30_EL0: Self = Self::System(0b11_011_1110_1011_110); 690 /// Performance Monitors Event Type Registers - 0 691 pub const PMEVTYPER0_EL0: Self = Self::System(0b11_011_1110_1100_000); 692 /// Performance Monitors Event Type Registers - 1 693 pub const PMEVTYPER1_EL0: Self = Self::System(0b11_011_1110_1100_001); 694 /// Performance Monitors Event Type Registers - 2 695 pub const PMEVTYPER2_EL0: Self = Self::System(0b11_011_1110_1100_010); 696 /// Performance Monitors Event Type Registers - 3 697 pub const PMEVTYPER3_EL0: Self = Self::System(0b11_011_1110_1100_011); 698 /// Performance Monitors Event Type Registers - 4 699 pub const PMEVTYPER4_EL0: Self = Self::System(0b11_011_1110_1100_100); 700 /// Performance Monitors Event Type Registers - 5 701 pub const PMEVTYPER5_EL0: Self = Self::System(0b11_011_1110_1100_101); 702 /// Performance Monitors Event Type Registers - 6 703 pub const PMEVTYPER6_EL0: Self = Self::System(0b11_011_1110_1100_110); 704 /// Performance Monitors Event Type Registers - 7 705 pub const PMEVTYPER7_EL0: Self = Self::System(0b11_011_1110_1100_111); 706 /// Performance Monitors Event Type Registers - 8 707 pub const PMEVTYPER8_EL0: Self = Self::System(0b11_011_1110_1101_000); 708 /// Performance Monitors Event Type Registers - 9 709 pub const PMEVTYPER9_EL0: Self = Self::System(0b11_011_1110_1101_001); 710 /// Performance Monitors Event Type Registers - 10 711 pub const PMEVTYPER10_EL0: Self = Self::System(0b11_011_1110_1101_010); 712 /// Performance Monitors Event Type Registers - 11 713 pub const PMEVTYPER11_EL0: Self = Self::System(0b11_011_1110_1101_011); 714 /// Performance Monitors Event Type Registers - 12 715 pub const PMEVTYPER12_EL0: Self = Self::System(0b11_011_1110_1101_100); 716 /// Performance Monitors Event Type Registers - 13 717 pub const PMEVTYPER13_EL0: Self = Self::System(0b11_011_1110_1101_101); 718 /// Performance Monitors Event Type Registers - 14 719 pub const PMEVTYPER14_EL0: Self = Self::System(0b11_011_1110_1101_110); 720 /// Performance Monitors Event Type Registers - 15 721 pub const PMEVTYPER15_EL0: Self = Self::System(0b11_011_1110_1101_111); 722 /// Performance Monitors Event Type Registers - 16 723 pub const PMEVTYPER16_EL0: Self = Self::System(0b11_011_1110_1110_000); 724 /// Performance Monitors Event Type Registers - 17 725 pub const PMEVTYPER17_EL0: Self = Self::System(0b11_011_1110_1110_001); 726 /// Performance Monitors Event Type Registers - 18 727 pub const PMEVTYPER18_EL0: Self = Self::System(0b11_011_1110_1110_010); 728 /// Performance Monitors Event Type Registers - 19 729 pub const PMEVTYPER19_EL0: Self = Self::System(0b11_011_1110_1110_011); 730 /// Performance Monitors Event Type Registers - 20 731 pub const PMEVTYPER20_EL0: Self = Self::System(0b11_011_1110_1110_100); 732 /// Performance Monitors Event Type Registers - 21 733 pub const PMEVTYPER21_EL0: Self = Self::System(0b11_011_1110_1110_101); 734 /// Performance Monitors Event Type Registers - 22 735 pub const PMEVTYPER22_EL0: Self = Self::System(0b11_011_1110_1110_110); 736 /// Performance Monitors Event Type Registers - 23 737 pub const PMEVTYPER23_EL0: Self = Self::System(0b11_011_1110_1110_111); 738 /// Performance Monitors Event Type Registers - 24 739 pub const PMEVTYPER24_EL0: Self = Self::System(0b11_011_1110_1111_000); 740 /// Performance Monitors Event Type Registers - 25 741 pub const PMEVTYPER25_EL0: Self = Self::System(0b11_011_1110_1111_001); 742 /// Performance Monitors Event Type Registers - 26 743 pub const PMEVTYPER26_EL0: Self = Self::System(0b11_011_1110_1111_010); 744 /// Performance Monitors Event Type Registers - 27 745 pub const PMEVTYPER27_EL0: Self = Self::System(0b11_011_1110_1111_011); 746 /// Performance Monitors Event Type Registers - 28 747 pub const PMEVTYPER28_EL0: Self = Self::System(0b11_011_1110_1111_100); 748 /// Performance Monitors Event Type Registers - 29 749 pub const PMEVTYPER29_EL0: Self = Self::System(0b11_011_1110_1111_101); 750 /// Performance Monitors Event Type Registers - 30 751 pub const PMEVTYPER30_EL0: Self = Self::System(0b11_011_1110_1111_110); 752 /// Performance Monitors Cycle Count Filter Register 753 pub const PMCCFILTR_EL0: Self = Self::System(0b11_011_1110_1111_111); 754 /// Virtualization Processor ID Register 755 pub const VPIDR_EL2: Self = Self::System(0b11_100_0000_0000_000); 756 /// Virtualization Multiprocessor ID Register 757 pub const VMPIDR_EL2: Self = Self::System(0b11_100_0000_0000_101); 758 /// System Control Register (EL2) 759 pub const SCTLR_EL2: Self = Self::System(0b11_100_0001_0000_000); 760 /// Auxiliary Control Register (EL2) 761 pub const ACTLR_EL2: Self = Self::System(0b11_100_0001_0000_001); 762 /// Hypervisor Configuration Register 763 pub const HCR_EL2: Self = Self::System(0b11_100_0001_0001_000); 764 /// Monitor Debug Configuration Register (EL2) 765 pub const MDCR_EL2: Self = Self::System(0b11_100_0001_0001_001); 766 /// Architectural Feature Trap Register (EL2) 767 pub const CPTR_EL2: Self = Self::System(0b11_100_0001_0001_010); 768 /// Hypervisor System Trap Register 769 pub const HSTR_EL2: Self = Self::System(0b11_100_0001_0001_011); 770 /// Hypervisor Fine-Grained Read Trap Register 771 pub const HFGRTR_EL2: Self = Self::System(0b11_100_0001_0001_100); 772 /// Hypervisor Fine-Grained Write Trap Register 773 pub const HFGWTR_EL2: Self = Self::System(0b11_100_0001_0001_101); 774 /// Hypervisor Fine-Grained Instruction Trap Register 775 pub const HFGITR_EL2: Self = Self::System(0b11_100_0001_0001_110); 776 /// Hypervisor Auxiliary Control Register 777 pub const HACR_EL2: Self = Self::System(0b11_100_0001_0001_111); 778 /// SVE Control Register (EL2) 779 pub const ZCR_EL2: Self = Self::System(0b11_100_0001_0010_000); 780 /// Trace Filter Control Register (EL2) 781 pub const TRFCR_EL2: Self = Self::System(0b11_100_0001_0010_001); 782 /// Extended Hypervisor Configuration Register 783 pub const HCRX_EL2: Self = Self::System(0b11_100_0001_0010_010); 784 /// Streaming Mode Priority Mapping Register 785 pub const SMPRIMAP_EL2: Self = Self::System(0b11_100_0001_0010_101); 786 /// SME Control Register (EL2) 787 pub const SMCR_EL2: Self = Self::System(0b11_100_0001_0010_110); 788 /// AArch32 Secure Debug Enable Register 789 pub const SDER32_EL2: Self = Self::System(0b11_100_0001_0011_001); 790 /// Translation Table Base Register 0 (EL2) 791 pub const TTBR0_EL2: Self = Self::System(0b11_100_0010_0000_000); 792 /// Translation Table Base Register 1 (EL2) 793 pub const TTBR1_EL2: Self = Self::System(0b11_100_0010_0000_001); 794 /// Translation Control Register (EL2) 795 pub const TCR_EL2: Self = Self::System(0b11_100_0010_0000_010); 796 /// Virtualization Translation Table Base Register 797 pub const VTTBR_EL2: Self = Self::System(0b11_100_0010_0001_000); 798 /// Virtualization Translation Control Register 799 pub const VTCR_EL2: Self = Self::System(0b11_100_0010_0001_010); 800 /// Virtual Nested Control Register 801 pub const VNCR_EL2: Self = Self::System(0b11_100_0010_0010_000); 802 /// Virtualization Secure Translation Table Base Register 803 pub const VSTTBR_EL2: Self = Self::System(0b11_100_0010_0110_000); 804 /// Virtualization Secure Translation Control Register 805 pub const VSTCR_EL2: Self = Self::System(0b11_100_0010_0110_010); 806 /// Domain Access Control Register 807 pub const DACR32_EL2: Self = Self::System(0b11_100_0011_0000_000); 808 /// Hypervisor Debug Fine-Grained Read Trap Register 809 pub const HDFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_100); 810 /// Hypervisor Debug Fine-Grained Write Trap Register 811 pub const HDFGWTR_EL2: Self = Self::System(0b11_100_0011_0001_101); 812 /// Hypervisor Activity Monitors Fine-Grained Read Trap Register 813 pub const HAFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_110); 814 /// Saved Program Status Register (EL2) 815 pub const SPSR_EL2: Self = Self::System(0b11_100_0100_0000_000); 816 /// Exception Link Register (EL2) 817 pub const ELR_EL2: Self = Self::System(0b11_100_0100_0000_001); 818 /// Stack Pointer (EL1) 819 pub const SP_EL1: Self = Self::System(0b11_100_0100_0001_000); 820 /// Saved Program Status Register (IRQ Mode) 821 pub const SPSR_IRQ: Self = Self::System(0b11_100_0100_0011_000); 822 /// Saved Program Status Register (Abort Mode) 823 pub const SPSR_ABT: Self = Self::System(0b11_100_0100_0011_001); 824 /// Saved Program Status Register (Undefined Mode) 825 pub const SPSR_UND: Self = Self::System(0b11_100_0100_0011_010); 826 /// Saved Program Status Register (FIQ Mode) 827 pub const SPSR_FIQ: Self = Self::System(0b11_100_0100_0011_011); 828 /// Instruction Fault Status Register (EL2) 829 pub const IFSR32_EL2: Self = Self::System(0b11_100_0101_0000_001); 830 /// Auxiliary Fault Status Register 0 (EL2) 831 pub const AFSR0_EL2: Self = Self::System(0b11_100_0101_0001_000); 832 /// Auxiliary Fault Status Register 1 (EL2) 833 pub const AFSR1_EL2: Self = Self::System(0b11_100_0101_0001_001); 834 /// Exception Syndrome Register (EL2) 835 pub const ESR_EL2: Self = Self::System(0b11_100_0101_0010_000); 836 /// Virtual SError Exception Syndrome Register 837 pub const VSESR_EL2: Self = Self::System(0b11_100_0101_0010_011); 838 /// Floating-Point Exception Control Register 839 pub const FPEXC32_EL2: Self = Self::System(0b11_100_0101_0011_000); 840 /// Tag Fault Status Register (EL2) 841 pub const TFSR_EL2: Self = Self::System(0b11_100_0101_0110_000); 842 /// Fault Address Register (EL2) 843 pub const FAR_EL2: Self = Self::System(0b11_100_0110_0000_000); 844 /// Hypervisor IPA Fault Address Register 845 pub const HPFAR_EL2: Self = Self::System(0b11_100_0110_0000_100); 846 /// Statistical Profiling Control Register (EL2) 847 pub const PMSCR_EL2: Self = Self::System(0b11_100_1001_1001_000); 848 /// Memory Attribute Indirection Register (EL2) 849 pub const MAIR_EL2: Self = Self::System(0b11_100_1010_0010_000); 850 /// Auxiliary Memory Attribute Indirection Register (EL2) 851 pub const AMAIR_EL2: Self = Self::System(0b11_100_1010_0011_000); 852 /// MPAM Hypervisor Control Register (EL2) 853 pub const MPAMHCR_EL2: Self = Self::System(0b11_100_1010_0100_000); 854 /// MPAM Virtual Partition Mapping Valid Register 855 pub const MPAMVPMV_EL2: Self = Self::System(0b11_100_1010_0100_001); 856 /// MPAM2 Register (EL2) 857 pub const MPAM2_EL2: Self = Self::System(0b11_100_1010_0101_000); 858 /// MPAM Virtual PARTID Mapping Register 0 859 pub const MPAMVPM0_EL2: Self = Self::System(0b11_100_1010_0110_000); 860 /// MPAM Virtual PARTID Mapping Register 1 861 pub const MPAMVPM1_EL2: Self = Self::System(0b11_100_1010_0110_001); 862 /// MPAM Virtual PARTID Mapping Register 2 863 pub const MPAMVPM2_EL2: Self = Self::System(0b11_100_1010_0110_010); 864 /// MPAM Virtual PARTID Mapping Register 3 865 pub const MPAMVPM3_EL2: Self = Self::System(0b11_100_1010_0110_011); 866 /// MPAM Virtual PARTID Mapping Register 4 867 pub const MPAMVPM4_EL2: Self = Self::System(0b11_100_1010_0110_100); 868 /// MPAM Virtual PARTID Mapping Register 5 869 pub const MPAMVPM5_EL2: Self = Self::System(0b11_100_1010_0110_101); 870 /// MPAM Virtual PARTID Mapping Register 6 871 pub const MPAMVPM6_EL2: Self = Self::System(0b11_100_1010_0110_110); 872 /// MPAM Virtual PARTID Mapping Register 7 873 pub const MPAMVPM7_EL2: Self = Self::System(0b11_100_1010_0110_111); 874 /// Vector Base Address Register (EL2) 875 pub const VBAR_EL2: Self = Self::System(0b11_100_1100_0000_000); 876 /// Reset Vector Base Address Register (if EL3 Not Implemented) 877 pub const RVBAR_EL2: Self = Self::System(0b11_100_1100_0000_001); 878 /// Reset Management Register (EL2) 879 pub const RMR_EL2: Self = Self::System(0b11_100_1100_0000_010); 880 /// Virtual Deferred Interrupt Status Register 881 pub const VDISR_EL2: Self = Self::System(0b11_100_1100_0001_001); 882 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 0 883 pub const ICH_AP0R0_EL2: Self = Self::System(0b11_100_1100_1000_000); 884 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 1 885 pub const ICH_AP0R1_EL2: Self = Self::System(0b11_100_1100_1000_001); 886 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 2 887 pub const ICH_AP0R2_EL2: Self = Self::System(0b11_100_1100_1000_010); 888 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 3 889 pub const ICH_AP0R3_EL2: Self = Self::System(0b11_100_1100_1000_011); 890 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 0 891 pub const ICH_AP1R0_EL2: Self = Self::System(0b11_100_1100_1001_000); 892 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 1 893 pub const ICH_AP1R1_EL2: Self = Self::System(0b11_100_1100_1001_001); 894 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 2 895 pub const ICH_AP1R2_EL2: Self = Self::System(0b11_100_1100_1001_010); 896 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 3 897 pub const ICH_AP1R3_EL2: Self = Self::System(0b11_100_1100_1001_011); 898 /// Interrupt Controller System Register Enable Register (EL2) 899 pub const ICC_SRE_EL2: Self = Self::System(0b11_100_1100_1001_101); 900 /// Interrupt Controller Hyp Control Register 901 pub const ICH_HCR_EL2: Self = Self::System(0b11_100_1100_1011_000); 902 /// Interrupt Controller VGIC Type Register 903 pub const ICH_VTR_EL2: Self = Self::System(0b11_100_1100_1011_001); 904 /// Interrupt Controller Maintenance Interrupt State Register 905 pub const ICH_MISR_EL2: Self = Self::System(0b11_100_1100_1011_010); 906 /// Interrupt Controller End Of Interrupt Status Register 907 pub const ICH_EISR_EL2: Self = Self::System(0b11_100_1100_1011_011); 908 /// Interrupt Controller Empty List Register Status Register 909 pub const ICH_ELRSR_EL2: Self = Self::System(0b11_100_1100_1011_101); 910 /// Interrupt Controller Virtual Machine Control Register 911 pub const ICH_VMCR_EL2: Self = Self::System(0b11_100_1100_1011_111); 912 /// Interrupt Controller List Registers - 0 913 pub const ICH_LR0_EL2: Self = Self::System(0b11_100_1100_1100_000); 914 /// Interrupt Controller List Registers - 1 915 pub const ICH_LR1_EL2: Self = Self::System(0b11_100_1100_1100_001); 916 /// Interrupt Controller List Registers - 2 917 pub const ICH_LR2_EL2: Self = Self::System(0b11_100_1100_1100_010); 918 /// Interrupt Controller List Registers - 3 919 pub const ICH_LR3_EL2: Self = Self::System(0b11_100_1100_1100_011); 920 /// Interrupt Controller List Registers - 4 921 pub const ICH_LR4_EL2: Self = Self::System(0b11_100_1100_1100_100); 922 /// Interrupt Controller List Registers - 5 923 pub const ICH_LR5_EL2: Self = Self::System(0b11_100_1100_1100_101); 924 /// Interrupt Controller List Registers - 6 925 pub const ICH_LR6_EL2: Self = Self::System(0b11_100_1100_1100_110); 926 /// Interrupt Controller List Registers - 7 927 pub const ICH_LR7_EL2: Self = Self::System(0b11_100_1100_1100_111); 928 /// Interrupt Controller List Registers - 8 929 pub const ICH_LR8_EL2: Self = Self::System(0b11_100_1100_1101_000); 930 /// Interrupt Controller List Registers - 9 931 pub const ICH_LR9_EL2: Self = Self::System(0b11_100_1100_1101_001); 932 /// Interrupt Controller List Registers - 10 933 pub const ICH_LR10_EL2: Self = Self::System(0b11_100_1100_1101_010); 934 /// Interrupt Controller List Registers - 11 935 pub const ICH_LR11_EL2: Self = Self::System(0b11_100_1100_1101_011); 936 /// Interrupt Controller List Registers - 12 937 pub const ICH_LR12_EL2: Self = Self::System(0b11_100_1100_1101_100); 938 /// Interrupt Controller List Registers - 13 939 pub const ICH_LR13_EL2: Self = Self::System(0b11_100_1100_1101_101); 940 /// Interrupt Controller List Registers - 14 941 pub const ICH_LR14_EL2: Self = Self::System(0b11_100_1100_1101_110); 942 /// Interrupt Controller List Registers - 15 943 pub const ICH_LR15_EL2: Self = Self::System(0b11_100_1100_1101_111); 944 /// Context ID Register (EL2) 945 pub const CONTEXTIDR_EL2: Self = Self::System(0b11_100_1101_0000_001); 946 /// EL2 Software Thread ID Register 947 pub const TPIDR_EL2: Self = Self::System(0b11_100_1101_0000_010); 948 /// EL2 Read/Write Software Context Number 949 pub const SCXTNUM_EL2: Self = Self::System(0b11_100_1101_0000_111); 950 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 0 951 pub const AMEVCNTVOFF00_EL2: Self = Self::System(0b11_100_1101_1000_000); 952 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 1 953 pub const AMEVCNTVOFF01_EL2: Self = Self::System(0b11_100_1101_1000_001); 954 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 2 955 pub const AMEVCNTVOFF02_EL2: Self = Self::System(0b11_100_1101_1000_010); 956 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 3 957 pub const AMEVCNTVOFF03_EL2: Self = Self::System(0b11_100_1101_1000_011); 958 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 4 959 pub const AMEVCNTVOFF04_EL2: Self = Self::System(0b11_100_1101_1000_100); 960 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 5 961 pub const AMEVCNTVOFF05_EL2: Self = Self::System(0b11_100_1101_1000_101); 962 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 6 963 pub const AMEVCNTVOFF06_EL2: Self = Self::System(0b11_100_1101_1000_110); 964 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 7 965 pub const AMEVCNTVOFF07_EL2: Self = Self::System(0b11_100_1101_1000_111); 966 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 8 967 pub const AMEVCNTVOFF08_EL2: Self = Self::System(0b11_100_1101_1001_000); 968 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 9 969 pub const AMEVCNTVOFF09_EL2: Self = Self::System(0b11_100_1101_1001_001); 970 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 10 971 pub const AMEVCNTVOFF010_EL2: Self = Self::System(0b11_100_1101_1001_010); 972 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 11 973 pub const AMEVCNTVOFF011_EL2: Self = Self::System(0b11_100_1101_1001_011); 974 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 12 975 pub const AMEVCNTVOFF012_EL2: Self = Self::System(0b11_100_1101_1001_100); 976 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 13 977 pub const AMEVCNTVOFF013_EL2: Self = Self::System(0b11_100_1101_1001_101); 978 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 14 979 pub const AMEVCNTVOFF014_EL2: Self = Self::System(0b11_100_1101_1001_110); 980 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 15 981 pub const AMEVCNTVOFF015_EL2: Self = Self::System(0b11_100_1101_1001_111); 982 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 0 983 pub const AMEVCNTVOFF10_EL2: Self = Self::System(0b11_100_1101_1010_000); 984 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 1 985 pub const AMEVCNTVOFF11_EL2: Self = Self::System(0b11_100_1101_1010_001); 986 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 2 987 pub const AMEVCNTVOFF12_EL2: Self = Self::System(0b11_100_1101_1010_010); 988 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 3 989 pub const AMEVCNTVOFF13_EL2: Self = Self::System(0b11_100_1101_1010_011); 990 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 4 991 pub const AMEVCNTVOFF14_EL2: Self = Self::System(0b11_100_1101_1010_100); 992 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 5 993 pub const AMEVCNTVOFF15_EL2: Self = Self::System(0b11_100_1101_1010_101); 994 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 6 995 pub const AMEVCNTVOFF16_EL2: Self = Self::System(0b11_100_1101_1010_110); 996 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 7 997 pub const AMEVCNTVOFF17_EL2: Self = Self::System(0b11_100_1101_1010_111); 998 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 8 999 pub const AMEVCNTVOFF18_EL2: Self = Self::System(0b11_100_1101_1011_000); 1000 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 9 1001 pub const AMEVCNTVOFF19_EL2: Self = Self::System(0b11_100_1101_1011_001); 1002 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 10 1003 pub const AMEVCNTVOFF110_EL2: Self = Self::System(0b11_100_1101_1011_010); 1004 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 11 1005 pub const AMEVCNTVOFF111_EL2: Self = Self::System(0b11_100_1101_1011_011); 1006 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 12 1007 pub const AMEVCNTVOFF112_EL2: Self = Self::System(0b11_100_1101_1011_100); 1008 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 13 1009 pub const AMEVCNTVOFF113_EL2: Self = Self::System(0b11_100_1101_1011_101); 1010 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 14 1011 pub const AMEVCNTVOFF114_EL2: Self = Self::System(0b11_100_1101_1011_110); 1012 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 15 1013 pub const AMEVCNTVOFF115_EL2: Self = Self::System(0b11_100_1101_1011_111); 1014 /// Counter-timer Virtual Offset Register 1015 pub const CNTVOFF_EL2: Self = Self::System(0b11_100_1110_0000_011); 1016 /// Counter-timer Physical Offset Register 1017 pub const CNTPOFF_EL2: Self = Self::System(0b11_100_1110_0000_110); 1018 /// Counter-timer Hypervisor Control Register 1019 pub const CNTHCTL_EL2: Self = Self::System(0b11_100_1110_0001_000); 1020 /// Counter-timer Physical Timer TimerValue Register (EL2) 1021 pub const CNTHP_TVAL_EL2: Self = Self::System(0b11_100_1110_0010_000); 1022 /// Counter-timer Hypervisor Physical Timer Control Register 1023 pub const CNTHP_CTL_EL2: Self = Self::System(0b11_100_1110_0010_001); 1024 /// Counter-timer Physical Timer CompareValue Register (EL2) 1025 pub const CNTHP_CVAL_EL2: Self = Self::System(0b11_100_1110_0010_010); 1026 /// Counter-timer Virtual Timer TimerValue Register (EL2) 1027 pub const CNTHV_TVAL_EL2: Self = Self::System(0b11_100_1110_0011_000); 1028 /// Counter-timer Virtual Timer Control Register (EL2) 1029 pub const CNTHV_CTL_EL2: Self = Self::System(0b11_100_1110_0011_001); 1030 /// Counter-timer Virtual Timer CompareValue Register (EL2) 1031 pub const CNTHV_CVAL_EL2: Self = Self::System(0b11_100_1110_0011_010); 1032 /// Counter-timer Secure Virtual Timer TimerValue Register (EL2) 1033 pub const CNTHVS_TVAL_EL2: Self = Self::System(0b11_100_1110_0100_000); 1034 /// Counter-timer Secure Virtual Timer Control Register (EL2) 1035 pub const CNTHVS_CTL_EL2: Self = Self::System(0b11_100_1110_0100_001); 1036 /// Counter-timer Secure Virtual Timer CompareValue Register (EL2) 1037 pub const CNTHVS_CVAL_EL2: Self = Self::System(0b11_100_1110_0100_010); 1038 /// Counter-timer Secure Physical Timer TimerValue Register (EL2) 1039 pub const CNTHPS_TVAL_EL2: Self = Self::System(0b11_100_1110_0101_000); 1040 /// Counter-timer Secure Physical Timer Control Register (EL2) 1041 pub const CNTHPS_CTL_EL2: Self = Self::System(0b11_100_1110_0101_001); 1042 /// Counter-timer Secure Physical Timer CompareValue Register (EL2) 1043 pub const CNTHPS_CVAL_EL2: Self = Self::System(0b11_100_1110_0101_010); 1044 /// System Control Register (EL3) 1045 pub const SCTLR_EL3: Self = Self::System(0b11_110_0001_0000_000); 1046 /// Auxiliary Control Register (EL3) 1047 pub const ACTLR_EL3: Self = Self::System(0b11_110_0001_0000_001); 1048 /// Secure Configuration Register 1049 pub const SCR_EL3: Self = Self::System(0b11_110_0001_0001_000); 1050 /// AArch32 Secure Debug Enable Register 1051 pub const SDER32_EL3: Self = Self::System(0b11_110_0001_0001_001); 1052 /// Architectural Feature Trap Register (EL3) 1053 pub const CPTR_EL3: Self = Self::System(0b11_110_0001_0001_010); 1054 /// SVE Control Register (EL3) 1055 pub const ZCR_EL3: Self = Self::System(0b11_110_0001_0010_000); 1056 /// SME Control Register (EL3) 1057 pub const SMCR_EL3: Self = Self::System(0b11_110_0001_0010_110); 1058 /// Monitor Debug Configuration Register (EL3) 1059 pub const MDCR_EL3: Self = Self::System(0b11_110_0001_0011_001); 1060 /// Translation Table Base Register 0 (EL3) 1061 pub const TTBR0_EL3: Self = Self::System(0b11_110_0010_0000_000); 1062 /// Translation Control Register (EL3) 1063 pub const TCR_EL3: Self = Self::System(0b11_110_0010_0000_010); 1064 /// Granule Protection Table Base Register 1065 pub const GPTBR_EL3: Self = Self::System(0b11_110_0010_0001_100); 1066 /// Granule Protection Check Control Register (EL3) 1067 pub const GPCCR_EL3: Self = Self::System(0b11_110_0010_0001_110); 1068 /// Saved Program Status Register (EL3) 1069 pub const SPSR_EL3: Self = Self::System(0b11_110_0100_0000_000); 1070 /// Exception Link Register (EL3) 1071 pub const ELR_EL3: Self = Self::System(0b11_110_0100_0000_001); 1072 /// Stack Pointer (EL2) 1073 pub const SP_EL2: Self = Self::System(0b11_110_0100_0001_000); 1074 /// Auxiliary Fault Status Register 0 (EL3) 1075 pub const AFSR0_EL3: Self = Self::System(0b11_110_0101_0001_000); 1076 /// Auxiliary Fault Status Register 1 (EL3) 1077 pub const AFSR1_EL3: Self = Self::System(0b11_110_0101_0001_001); 1078 /// Exception Syndrome Register (EL3) 1079 pub const ESR_EL3: Self = Self::System(0b11_110_0101_0010_000); 1080 /// Tag Fault Status Register (EL3) 1081 pub const TFSR_EL3: Self = Self::System(0b11_110_0101_0110_000); 1082 /// Fault Address Register (EL3) 1083 pub const FAR_EL3: Self = Self::System(0b11_110_0110_0000_000); 1084 /// PA Fault Address Register 1085 pub const MFAR_EL3: Self = Self::System(0b11_110_0110_0000_101); 1086 /// Memory Attribute Indirection Register (EL3) 1087 pub const MAIR_EL3: Self = Self::System(0b11_110_1010_0010_000); 1088 /// Auxiliary Memory Attribute Indirection Register (EL3) 1089 pub const AMAIR_EL3: Self = Self::System(0b11_110_1010_0011_000); 1090 /// MPAM3 Register (EL3) 1091 pub const MPAM3_EL3: Self = Self::System(0b11_110_1010_0101_000); 1092 /// Vector Base Address Register (EL3) 1093 pub const VBAR_EL3: Self = Self::System(0b11_110_1100_0000_000); 1094 /// Reset Vector Base Address Register (if EL3 Implemented) 1095 pub const RVBAR_EL3: Self = Self::System(0b11_110_1100_0000_001); 1096 /// Reset Management Register (EL3) 1097 pub const RMR_EL3: Self = Self::System(0b11_110_1100_0000_010); 1098 /// Interrupt Controller Control Register (EL3) 1099 pub const ICC_CTLR_EL3: Self = Self::System(0b11_110_1100_1100_100); 1100 /// Interrupt Controller System Register Enable Register (EL3) 1101 pub const ICC_SRE_EL3: Self = Self::System(0b11_110_1100_1100_101); 1102 /// Interrupt Controller Interrupt Group 1 Enable Register (EL3) 1103 pub const ICC_IGRPEN1_EL3: Self = Self::System(0b11_110_1100_1100_111); 1104 /// EL3 Software Thread ID Register 1105 pub const TPIDR_EL3: Self = Self::System(0b11_110_1101_0000_010); 1106 /// EL3 Read/Write Software Context Number 1107 pub const SCXTNUM_EL3: Self = Self::System(0b11_110_1101_0000_111); 1108 /// Counter-timer Physical Secure Timer TimerValue Register 1109 pub const CNTPS_TVAL_EL1: Self = Self::System(0b11_111_1110_0010_000); 1110 /// Counter-timer Physical Secure Timer Control Register 1111 pub const CNTPS_CTL_EL1: Self = Self::System(0b11_111_1110_0010_001); 1112 /// Counter-timer Physical Secure Timer CompareValue Register 1113 pub const CNTPS_CVAL_EL1: Self = Self::System(0b11_111_1110_0010_010); 1114 1115 /// OS Lock Data Transfer Register, Receive 1116 pub const OSDTRRX_EL1: Self = Self::System(0b10_000_0000_0000_010); 1117 /// Debug Breakpoint Value Registers - 0 1118 pub const DBGBVR0_EL1: Self = Self::System(0b10_000_0000_0000_100); 1119 /// Debug Breakpoint Control Registers - 0 1120 pub const DBGBCR0_EL1: Self = Self::System(0b10_000_0000_0000_101); 1121 /// Debug Watchpoint Value Registers - 0 1122 pub const DBGWVR0_EL1: Self = Self::System(0b10_000_0000_0000_110); 1123 /// Debug Watchpoint Control Registers - 0 1124 pub const DBGWCR0_EL1: Self = Self::System(0b10_000_0000_0000_111); 1125 /// Debug Breakpoint Value Registers - 1 1126 pub const DBGBVR1_EL1: Self = Self::System(0b10_000_0000_0001_100); 1127 /// Debug Breakpoint Control Registers - 1 1128 pub const DBGBCR1_EL1: Self = Self::System(0b10_000_0000_0001_101); 1129 /// Debug Watchpoint Value Registers - 1 1130 pub const DBGWVR1_EL1: Self = Self::System(0b10_000_0000_0001_110); 1131 /// Debug Watchpoint Control Registers - 1 1132 pub const DBGWCR1_EL1: Self = Self::System(0b10_000_0000_0001_111); 1133 /// Monitor DCC Interrupt Enable Register 1134 pub const MDCCINT_EL1: Self = Self::System(0b10_000_0000_0010_000); 1135 /// Monitor Debug System Control Register 1136 pub const MDSCR_EL1: Self = Self::System(0b10_000_0000_0010_010); 1137 /// Debug Breakpoint Value Registers - 2 1138 pub const DBGBVR2_EL1: Self = Self::System(0b10_000_0000_0010_100); 1139 /// Debug Breakpoint Control Registers - 2 1140 pub const DBGBCR2_EL1: Self = Self::System(0b10_000_0000_0010_101); 1141 /// Debug Watchpoint Value Registers - 2 1142 pub const DBGWVR2_EL1: Self = Self::System(0b10_000_0000_0010_110); 1143 /// Debug Watchpoint Control Registers - 2 1144 pub const DBGWCR2_EL1: Self = Self::System(0b10_000_0000_0010_111); 1145 /// OS Lock Data Transfer Register, Transmit 1146 pub const OSDTRTX_EL1: Self = Self::System(0b10_000_0000_0011_010); 1147 /// Debug Breakpoint Value Registers - 3 1148 pub const DBGBVR3_EL1: Self = Self::System(0b10_000_0000_0011_100); 1149 /// Debug Breakpoint Control Registers - 3 1150 pub const DBGBCR3_EL1: Self = Self::System(0b10_000_0000_0011_101); 1151 /// Debug Watchpoint Value Registers - 3 1152 pub const DBGWVR3_EL1: Self = Self::System(0b10_000_0000_0011_110); 1153 /// Debug Watchpoint Control Registers - 3 1154 pub const DBGWCR3_EL1: Self = Self::System(0b10_000_0000_0011_111); 1155 /// Debug Breakpoint Value Registers - 4 1156 pub const DBGBVR4_EL1: Self = Self::System(0b10_000_0000_0100_100); 1157 /// Debug Breakpoint Control Registers - 4 1158 pub const DBGBCR4_EL1: Self = Self::System(0b10_000_0000_0100_101); 1159 /// Debug Watchpoint Value Registers - 4 1160 pub const DBGWVR4_EL1: Self = Self::System(0b10_000_0000_0100_110); 1161 /// Debug Watchpoint Control Registers - 4 1162 pub const DBGWCR4_EL1: Self = Self::System(0b10_000_0000_0100_111); 1163 /// Debug Breakpoint Value Registers - 5 1164 pub const DBGBVR5_EL1: Self = Self::System(0b10_000_0000_0101_100); 1165 /// Debug Breakpoint Control Registers - 5 1166 pub const DBGBCR5_EL1: Self = Self::System(0b10_000_0000_0101_101); 1167 /// Debug Watchpoint Value Registers - 5 1168 pub const DBGWVR5_EL1: Self = Self::System(0b10_000_0000_0101_110); 1169 /// Debug Watchpoint Control Registers - 5 1170 pub const DBGWCR5_EL1: Self = Self::System(0b10_000_0000_0101_111); 1171 /// OS Lock Exception Catch Control Register 1172 pub const OSECCR_EL1: Self = Self::System(0b10_000_0000_0110_010); 1173 /// Debug Breakpoint Value Registers - 6 1174 pub const DBGBVR6_EL1: Self = Self::System(0b10_000_0000_0110_100); 1175 /// Debug Breakpoint Control Registers - 6 1176 pub const DBGBCR6_EL1: Self = Self::System(0b10_000_0000_0110_101); 1177 /// Debug Watchpoint Value Registers - 6 1178 pub const DBGWVR6_EL1: Self = Self::System(0b10_000_0000_0110_110); 1179 /// Debug Watchpoint Control Registers - 6 1180 pub const DBGWCR6_EL1: Self = Self::System(0b10_000_0000_0110_111); 1181 /// Debug Breakpoint Value Registers - 7 1182 pub const DBGBVR7_EL1: Self = Self::System(0b10_000_0000_0111_100); 1183 /// Debug Breakpoint Control Registers - 7 1184 pub const DBGBCR7_EL1: Self = Self::System(0b10_000_0000_0111_101); 1185 /// Debug Watchpoint Value Registers - 7 1186 pub const DBGWVR7_EL1: Self = Self::System(0b10_000_0000_0111_110); 1187 /// Debug Watchpoint Control Registers - 7 1188 pub const DBGWCR7_EL1: Self = Self::System(0b10_000_0000_0111_111); 1189 /// Debug Breakpoint Value Registers - 8 1190 pub const DBGBVR8_EL1: Self = Self::System(0b10_000_0000_1000_100); 1191 /// Debug Breakpoint Control Registers - 8 1192 pub const DBGBCR8_EL1: Self = Self::System(0b10_000_0000_1000_101); 1193 /// Debug Watchpoint Value Registers - 8 1194 pub const DBGWVR8_EL1: Self = Self::System(0b10_000_0000_1000_110); 1195 /// Debug Watchpoint Control Registers - 8 1196 pub const DBGWCR8_EL1: Self = Self::System(0b10_000_0000_1000_111); 1197 /// Debug Breakpoint Value Registers - 9 1198 pub const DBGBVR9_EL1: Self = Self::System(0b10_000_0000_1001_100); 1199 /// Debug Breakpoint Control Registers - 9 1200 pub const DBGBCR9_EL1: Self = Self::System(0b10_000_0000_1001_101); 1201 /// Debug Watchpoint Value Registers - 9 1202 pub const DBGWVR9_EL1: Self = Self::System(0b10_000_0000_1001_110); 1203 /// Debug Watchpoint Control Registers - 9 1204 pub const DBGWCR9_EL1: Self = Self::System(0b10_000_0000_1001_111); 1205 /// Debug Breakpoint Value Registers - 10 1206 pub const DBGBVR10_EL1: Self = Self::System(0b10_000_0000_1010_100); 1207 /// Debug Breakpoint Control Registers - 10 1208 pub const DBGBCR10_EL1: Self = Self::System(0b10_000_0000_1010_101); 1209 /// Debug Watchpoint Value Registers - 10 1210 pub const DBGWVR10_EL1: Self = Self::System(0b10_000_0000_1010_110); 1211 /// Debug Watchpoint Control Registers - 10 1212 pub const DBGWCR10_EL1: Self = Self::System(0b10_000_0000_1010_111); 1213 /// Debug Breakpoint Value Registers - 11 1214 pub const DBGBVR11_EL1: Self = Self::System(0b10_000_0000_1011_100); 1215 /// Debug Breakpoint Control Registers - 11 1216 pub const DBGBCR11_EL1: Self = Self::System(0b10_000_0000_1011_101); 1217 /// Debug Watchpoint Value Registers - 11 1218 pub const DBGWVR11_EL1: Self = Self::System(0b10_000_0000_1011_110); 1219 /// Debug Watchpoint Control Registers - 11 1220 pub const DBGWCR11_EL1: Self = Self::System(0b10_000_0000_1011_111); 1221 /// Debug Breakpoint Value Registers - 12 1222 pub const DBGBVR12_EL1: Self = Self::System(0b10_000_0000_1100_100); 1223 /// Debug Breakpoint Control Registers - 12 1224 pub const DBGBCR12_EL1: Self = Self::System(0b10_000_0000_1100_101); 1225 /// Debug Watchpoint Value Registers - 12 1226 pub const DBGWVR12_EL1: Self = Self::System(0b10_000_0000_1100_110); 1227 /// Debug Watchpoint Control Registers - 12 1228 pub const DBGWCR12_EL1: Self = Self::System(0b10_000_0000_1100_111); 1229 /// Debug Breakpoint Value Registers - 13 1230 pub const DBGBVR13_EL1: Self = Self::System(0b10_000_0000_1101_100); 1231 /// Debug Breakpoint Control Registers - 13 1232 pub const DBGBCR13_EL1: Self = Self::System(0b10_000_0000_1101_101); 1233 /// Debug Watchpoint Value Registers - 13 1234 pub const DBGWVR13_EL1: Self = Self::System(0b10_000_0000_1101_110); 1235 /// Debug Watchpoint Control Registers - 13 1236 pub const DBGWCR13_EL1: Self = Self::System(0b10_000_0000_1101_111); 1237 /// Debug Breakpoint Value Registers - 14 1238 pub const DBGBVR14_EL1: Self = Self::System(0b10_000_0000_1110_100); 1239 /// Debug Breakpoint Control Registers - 14 1240 pub const DBGBCR14_EL1: Self = Self::System(0b10_000_0000_1110_101); 1241 /// Debug Watchpoint Value Registers - 14 1242 pub const DBGWVR14_EL1: Self = Self::System(0b10_000_0000_1110_110); 1243 /// Debug Watchpoint Control Registers - 14 1244 pub const DBGWCR14_EL1: Self = Self::System(0b10_000_0000_1110_111); 1245 /// Debug Breakpoint Value Registers - 15 1246 pub const DBGBVR15_EL1: Self = Self::System(0b10_000_0000_1111_100); 1247 /// Debug Breakpoint Control Registers - 15 1248 pub const DBGBCR15_EL1: Self = Self::System(0b10_000_0000_1111_101); 1249 /// Debug Watchpoint Value Registers - 15 1250 pub const DBGWVR15_EL1: Self = Self::System(0b10_000_0000_1111_110); 1251 /// Debug Watchpoint Control Registers - 15 1252 pub const DBGWCR15_EL1: Self = Self::System(0b10_000_0000_1111_111); 1253 /// Monitor Debug ROM Address Register 1254 pub const MDRAR_EL1: Self = Self::System(0b10_000_0001_0000_000); 1255 /// OS Lock Access Register 1256 pub const OSLAR_EL1: Self = Self::System(0b10_000_0001_0000_100); 1257 /// OS Lock Status Register 1258 pub const OSLSR_EL1: Self = Self::System(0b10_000_0001_0001_100); 1259 /// OS Double Lock Register 1260 pub const OSDLR_EL1: Self = Self::System(0b10_000_0001_0011_100); 1261 /// Debug Power Control Register 1262 pub const DBGPRCR_EL1: Self = Self::System(0b10_000_0001_0100_100); 1263 /// Debug CLAIM Tag Set Register 1264 pub const DBGCLAIMSET_EL1: Self = Self::System(0b10_000_0111_1000_110); 1265 /// Debug CLAIM Tag Clear Register 1266 pub const DBGCLAIMCLR_EL1: Self = Self::System(0b10_000_0111_1001_110); 1267 /// Debug Authentication Status Register 1268 pub const DBGAUTHSTATUS_EL1: Self = Self::System(0b10_000_0111_1110_110); 1269 /// Trace ID Register 1270 pub const TRCTRACEIDR: Self = Self::System(0b10_001_0000_0000_001); 1271 /// ViewInst Main Control Register 1272 pub const TRCVICTLR: Self = Self::System(0b10_001_0000_0000_010); 1273 /// Sequencer State Transition Control Register 0 1274 pub const TRCSEQEVR0: Self = Self::System(0b10_001_0000_0000_100); 1275 /// Counter Reload Value Register 0 1276 pub const TRCCNTRLDVR0: Self = Self::System(0b10_001_0000_0000_101); 1277 /// ID Register 8 1278 pub const TRCIDR8: Self = Self::System(0b10_001_0000_0000_110); 1279 /// IMP DEF Register 0 1280 pub const TRCIMSPEC0: Self = Self::System(0b10_001_0000_0000_111); 1281 /// Programming Control Register 1282 pub const TRCPRGCTLR: Self = Self::System(0b10_001_0000_0001_000); 1283 /// Q Element Control Register 1284 pub const TRCQCTLR: Self = Self::System(0b10_001_0000_0001_001); 1285 /// ViewInst Include/Exclude Control Register 1286 pub const TRCVIIECTLR: Self = Self::System(0b10_001_0000_0001_010); 1287 /// Sequencer State Transition Control Register 1 1288 pub const TRCSEQEVR1: Self = Self::System(0b10_001_0000_0001_100); 1289 /// Counter Reload Value Register 1 1290 pub const TRCCNTRLDVR1: Self = Self::System(0b10_001_0000_0001_101); 1291 /// ID Register 9 1292 pub const TRCIDR9: Self = Self::System(0b10_001_0000_0001_110); 1293 /// IMP DEF Register 1 1294 pub const TRCIMSPEC1: Self = Self::System(0b10_001_0000_0001_111); 1295 /// ViewInst Start/Stop Control Register 1296 pub const TRCVISSCTLR: Self = Self::System(0b10_001_0000_0010_010); 1297 /// Sequencer State Transition Control Register 2 1298 pub const TRCSEQEVR2: Self = Self::System(0b10_001_0000_0010_100); 1299 /// Counter Reload Value Register 2 1300 pub const TRCCNTRLDVR2: Self = Self::System(0b10_001_0000_0010_101); 1301 /// ID Register 10 1302 pub const TRCIDR10: Self = Self::System(0b10_001_0000_0010_110); 1303 /// IMP DEF Register 2 1304 pub const TRCIMSPEC2: Self = Self::System(0b10_001_0000_0010_111); 1305 /// Trace Status Register 1306 pub const TRCSTATR: Self = Self::System(0b10_001_0000_0011_000); 1307 /// ViewInst Start/Stop PE Comparator Control Register 1308 pub const TRCVIPCSSCTLR: Self = Self::System(0b10_001_0000_0011_010); 1309 /// Counter Reload Value Register 3 1310 pub const TRCCNTRLDVR3: Self = Self::System(0b10_001_0000_0011_101); 1311 /// ID Register 11 1312 pub const TRCIDR11: Self = Self::System(0b10_001_0000_0011_110); 1313 /// IMP DEF Register 3 1314 pub const TRCIMSPEC3: Self = Self::System(0b10_001_0000_0011_111); 1315 /// Trace Configuration Register 1316 pub const TRCCONFIGR: Self = Self::System(0b10_001_0000_0100_000); 1317 /// Counter Control Register 0 1318 pub const TRCCNTCTLR0: Self = Self::System(0b10_001_0000_0100_101); 1319 /// ID Register 12 1320 pub const TRCIDR12: Self = Self::System(0b10_001_0000_0100_110); 1321 /// IMP DEF Register 4 1322 pub const TRCIMSPEC4: Self = Self::System(0b10_001_0000_0100_111); 1323 /// Counter Control Register 1 1324 pub const TRCCNTCTLR1: Self = Self::System(0b10_001_0000_0101_101); 1325 /// ID Register 13 1326 pub const TRCIDR13: Self = Self::System(0b10_001_0000_0101_110); 1327 /// IMP DEF Register 5 1328 pub const TRCIMSPEC5: Self = Self::System(0b10_001_0000_0101_111); 1329 /// Auxiliary Control Register 1330 pub const TRCAUXCTLR: Self = Self::System(0b10_001_0000_0110_000); 1331 /// Sequencer Reset Control Register 1332 pub const TRCSEQRSTEVR: Self = Self::System(0b10_001_0000_0110_100); 1333 /// Counter Control Register 2 1334 pub const TRCCNTCTLR2: Self = Self::System(0b10_001_0000_0110_101); 1335 /// IMP DEF Register 6 1336 pub const TRCIMSPEC6: Self = Self::System(0b10_001_0000_0110_111); 1337 /// Sequencer State Register 1338 pub const TRCSEQSTR: Self = Self::System(0b10_001_0000_0111_100); 1339 /// Counter Control Register 3 1340 pub const TRCCNTCTLR3: Self = Self::System(0b10_001_0000_0111_101); 1341 /// IMP DEF Register 7 1342 pub const TRCIMSPEC7: Self = Self::System(0b10_001_0000_0111_111); 1343 /// Event Control 0 Register 1344 pub const TRCEVENTCTL0R: Self = Self::System(0b10_001_0000_1000_000); 1345 /// External Input Select Register 0 1346 pub const TRCEXTINSELR0: Self = Self::System(0b10_001_0000_1000_100); 1347 /// Counter Value Register 0 1348 pub const TRCCNTVR0: Self = Self::System(0b10_001_0000_1000_101); 1349 /// ID Register 0 1350 pub const TRCIDR0: Self = Self::System(0b10_001_0000_1000_111); 1351 /// Event Control 1 Register 1352 pub const TRCEVENTCTL1R: Self = Self::System(0b10_001_0000_1001_000); 1353 /// External Input Select Register 1 1354 pub const TRCEXTINSELR1: Self = Self::System(0b10_001_0000_1001_100); 1355 /// Counter Value Register 1 1356 pub const TRCCNTVR1: Self = Self::System(0b10_001_0000_1001_101); 1357 /// ID Register 1 1358 pub const TRCIDR1: Self = Self::System(0b10_001_0000_1001_111); 1359 /// Resources Status Register 1360 pub const TRCRSR: Self = Self::System(0b10_001_0000_1010_000); 1361 /// External Input Select Register 2 1362 pub const TRCEXTINSELR2: Self = Self::System(0b10_001_0000_1010_100); 1363 /// Counter Value Register 2 1364 pub const TRCCNTVR2: Self = Self::System(0b10_001_0000_1010_101); 1365 /// ID Register 2 1366 pub const TRCIDR2: Self = Self::System(0b10_001_0000_1010_111); 1367 /// Stall Control Register 1368 pub const TRCSTALLCTLR: Self = Self::System(0b10_001_0000_1011_000); 1369 /// External Input Select Register 3 1370 pub const TRCEXTINSELR3: Self = Self::System(0b10_001_0000_1011_100); 1371 /// Counter Value Register 3 1372 pub const TRCCNTVR3: Self = Self::System(0b10_001_0000_1011_101); 1373 /// ID Register 3 1374 pub const TRCIDR3: Self = Self::System(0b10_001_0000_1011_111); 1375 /// Timestamp Control Register 1376 pub const TRCTSCTLR: Self = Self::System(0b10_001_0000_1100_000); 1377 /// ID Register 4 1378 pub const TRCIDR4: Self = Self::System(0b10_001_0000_1100_111); 1379 /// Synchronization Period Register 1380 pub const TRCSYNCPR: Self = Self::System(0b10_001_0000_1101_000); 1381 /// ID Register 5 1382 pub const TRCIDR5: Self = Self::System(0b10_001_0000_1101_111); 1383 /// Cycle Count Control Register 1384 pub const TRCCCCTLR: Self = Self::System(0b10_001_0000_1110_000); 1385 /// ID Register 6 1386 pub const TRCIDR6: Self = Self::System(0b10_001_0000_1110_111); 1387 /// Branch Broadcast Control Register 1388 pub const TRCBBCTLR: Self = Self::System(0b10_001_0000_1111_000); 1389 /// ID Register 7 1390 pub const TRCIDR7: Self = Self::System(0b10_001_0000_1111_111); 1391 /// Resource Selection Control Register 16 1392 pub const TRCRSCTLR16: Self = Self::System(0b10_001_0001_0000_001); 1393 /// Single-shot Comparator Control Register 0 1394 pub const TRCSSCCR0: Self = Self::System(0b10_001_0001_0000_010); 1395 /// Single-shot Processing Element Comparator Input Control Register 0 1396 pub const TRCSSPCICR0: Self = Self::System(0b10_001_0001_0000_011); 1397 /// Resource Selection Control Register 17 1398 pub const TRCRSCTLR17: Self = Self::System(0b10_001_0001_0001_001); 1399 /// Single-shot Comparator Control Register 1 1400 pub const TRCSSCCR1: Self = Self::System(0b10_001_0001_0001_010); 1401 /// Single-shot Processing Element Comparator Input Control Register 1 1402 pub const TRCSSPCICR1: Self = Self::System(0b10_001_0001_0001_011); 1403 /// Trace OS Lock Status Register 1404 pub const TRCOSLSR: Self = Self::System(0b10_001_0001_0001_100); 1405 /// Resource Selection Control Register 2 1406 pub const TRCRSCTLR2: Self = Self::System(0b10_001_0001_0010_000); 1407 /// Resource Selection Control Register 18 1408 pub const TRCRSCTLR18: Self = Self::System(0b10_001_0001_0010_001); 1409 /// Single-shot Comparator Control Register 2 1410 pub const TRCSSCCR2: Self = Self::System(0b10_001_0001_0010_010); 1411 /// Single-shot Processing Element Comparator Input Control Register 2 1412 pub const TRCSSPCICR2: Self = Self::System(0b10_001_0001_0010_011); 1413 /// Resource Selection Control Register 3 1414 pub const TRCRSCTLR3: Self = Self::System(0b10_001_0001_0011_000); 1415 /// Resource Selection Control Register 19 1416 pub const TRCRSCTLR19: Self = Self::System(0b10_001_0001_0011_001); 1417 /// Single-shot Comparator Control Register 3 1418 pub const TRCSSCCR3: Self = Self::System(0b10_001_0001_0011_010); 1419 /// Single-shot Processing Element Comparator Input Control Register 3 1420 pub const TRCSSPCICR3: Self = Self::System(0b10_001_0001_0011_011); 1421 /// Resource Selection Control Register 4 1422 pub const TRCRSCTLR4: Self = Self::System(0b10_001_0001_0100_000); 1423 /// Resource Selection Control Register 20 1424 pub const TRCRSCTLR20: Self = Self::System(0b10_001_0001_0100_001); 1425 /// Single-shot Comparator Control Register 4 1426 pub const TRCSSCCR4: Self = Self::System(0b10_001_0001_0100_010); 1427 /// Single-shot Processing Element Comparator Input Control Register 4 1428 pub const TRCSSPCICR4: Self = Self::System(0b10_001_0001_0100_011); 1429 /// Resource Selection Control Register 5 1430 pub const TRCRSCTLR5: Self = Self::System(0b10_001_0001_0101_000); 1431 /// Resource Selection Control Register 21 1432 pub const TRCRSCTLR21: Self = Self::System(0b10_001_0001_0101_001); 1433 /// Single-shot Comparator Control Register 5 1434 pub const TRCSSCCR5: Self = Self::System(0b10_001_0001_0101_010); 1435 /// Single-shot Processing Element Comparator Input Control Register 5 1436 pub const TRCSSPCICR5: Self = Self::System(0b10_001_0001_0101_011); 1437 /// Resource Selection Control Register 6 1438 pub const TRCRSCTLR6: Self = Self::System(0b10_001_0001_0110_000); 1439 /// Resource Selection Control Register 22 1440 pub const TRCRSCTLR22: Self = Self::System(0b10_001_0001_0110_001); 1441 /// Single-shot Comparator Control Register 6 1442 pub const TRCSSCCR6: Self = Self::System(0b10_001_0001_0110_010); 1443 /// Single-shot Processing Element Comparator Input Control Register 6 1444 pub const TRCSSPCICR6: Self = Self::System(0b10_001_0001_0110_011); 1445 /// Resource Selection Control Register 7 1446 pub const TRCRSCTLR7: Self = Self::System(0b10_001_0001_0111_000); 1447 /// Resource Selection Control Register 23 1448 pub const TRCRSCTLR23: Self = Self::System(0b10_001_0001_0111_001); 1449 /// Single-shot Comparator Control Register 7 1450 pub const TRCSSCCR7: Self = Self::System(0b10_001_0001_0111_010); 1451 /// Single-shot Processing Element Comparator Input Control Register 7 1452 pub const TRCSSPCICR7: Self = Self::System(0b10_001_0001_0111_011); 1453 /// Resource Selection Control Register 8 1454 pub const TRCRSCTLR8: Self = Self::System(0b10_001_0001_1000_000); 1455 /// Resource Selection Control Register 24 1456 pub const TRCRSCTLR24: Self = Self::System(0b10_001_0001_1000_001); 1457 /// Single-shot Comparator Control Status Register 0 1458 pub const TRCSSCSR0: Self = Self::System(0b10_001_0001_1000_010); 1459 /// Resource Selection Control Register 9 1460 pub const TRCRSCTLR9: Self = Self::System(0b10_001_0001_1001_000); 1461 /// Resource Selection Control Register 25 1462 pub const TRCRSCTLR25: Self = Self::System(0b10_001_0001_1001_001); 1463 /// Single-shot Comparator Control Status Register 1 1464 pub const TRCSSCSR1: Self = Self::System(0b10_001_0001_1001_010); 1465 /// Resource Selection Control Register 10 1466 pub const TRCRSCTLR10: Self = Self::System(0b10_001_0001_1010_000); 1467 /// Resource Selection Control Register 26 1468 pub const TRCRSCTLR26: Self = Self::System(0b10_001_0001_1010_001); 1469 /// Single-shot Comparator Control Status Register 2 1470 pub const TRCSSCSR2: Self = Self::System(0b10_001_0001_1010_010); 1471 /// Resource Selection Control Register 11 1472 pub const TRCRSCTLR11: Self = Self::System(0b10_001_0001_1011_000); 1473 /// Resource Selection Control Register 27 1474 pub const TRCRSCTLR27: Self = Self::System(0b10_001_0001_1011_001); 1475 /// Single-shot Comparator Control Status Register 3 1476 pub const TRCSSCSR3: Self = Self::System(0b10_001_0001_1011_010); 1477 /// Resource Selection Control Register 12 1478 pub const TRCRSCTLR12: Self = Self::System(0b10_001_0001_1100_000); 1479 /// Resource Selection Control Register 28 1480 pub const TRCRSCTLR28: Self = Self::System(0b10_001_0001_1100_001); 1481 /// Single-shot Comparator Control Status Register 4 1482 pub const TRCSSCSR4: Self = Self::System(0b10_001_0001_1100_010); 1483 /// Resource Selection Control Register 13 1484 pub const TRCRSCTLR13: Self = Self::System(0b10_001_0001_1101_000); 1485 /// Resource Selection Control Register 29 1486 pub const TRCRSCTLR29: Self = Self::System(0b10_001_0001_1101_001); 1487 /// Single-shot Comparator Control Status Register 5 1488 pub const TRCSSCSR5: Self = Self::System(0b10_001_0001_1101_010); 1489 /// Resource Selection Control Register 14 1490 pub const TRCRSCTLR14: Self = Self::System(0b10_001_0001_1110_000); 1491 /// Resource Selection Control Register 30 1492 pub const TRCRSCTLR30: Self = Self::System(0b10_001_0001_1110_001); 1493 /// Single-shot Comparator Control Status Register 6 1494 pub const TRCSSCSR6: Self = Self::System(0b10_001_0001_1110_010); 1495 /// Resource Selection Control Register 15 1496 pub const TRCRSCTLR15: Self = Self::System(0b10_001_0001_1111_000); 1497 /// Resource Selection Control Register 31 1498 pub const TRCRSCTLR31: Self = Self::System(0b10_001_0001_1111_001); 1499 /// Single-shot Comparator Control Status Register 7 1500 pub const TRCSSCSR7: Self = Self::System(0b10_001_0001_1111_010); 1501 /// Address Comparator Value Register 0 1502 pub const TRCACVR0: Self = Self::System(0b10_001_0010_0000_000); 1503 /// Address Comparator Value Register 8 1504 pub const TRCACVR8: Self = Self::System(0b10_001_0010_0000_001); 1505 /// Address Comparator Access Type Register 0 1506 pub const TRCACATR0: Self = Self::System(0b10_001_0010_0000_010); 1507 /// Address Comparator Access Type Register 8 1508 pub const TRCACATR8: Self = Self::System(0b10_001_0010_0000_011); 1509 /// Address Comparator Value Register 1 1510 pub const TRCACVR1: Self = Self::System(0b10_001_0010_0010_000); 1511 /// Address Comparator Value Register 9 1512 pub const TRCACVR9: Self = Self::System(0b10_001_0010_0010_001); 1513 /// Address Comparator Access Type Register 1 1514 pub const TRCACATR1: Self = Self::System(0b10_001_0010_0010_010); 1515 /// Address Comparator Access Type Register 9 1516 pub const TRCACATR9: Self = Self::System(0b10_001_0010_0010_011); 1517 /// Address Comparator Value Register 2 1518 pub const TRCACVR2: Self = Self::System(0b10_001_0010_0100_000); 1519 /// Address Comparator Value Register 10 1520 pub const TRCACVR10: Self = Self::System(0b10_001_0010_0100_001); 1521 /// Address Comparator Access Type Register 2 1522 pub const TRCACATR2: Self = Self::System(0b10_001_0010_0100_010); 1523 /// Address Comparator Access Type Register 10 1524 pub const TRCACATR10: Self = Self::System(0b10_001_0010_0100_011); 1525 /// Address Comparator Value Register 3 1526 pub const TRCACVR3: Self = Self::System(0b10_001_0010_0110_000); 1527 /// Address Comparator Value Register 11 1528 pub const TRCACVR11: Self = Self::System(0b10_001_0010_0110_001); 1529 /// Address Comparator Access Type Register 3 1530 pub const TRCACATR3: Self = Self::System(0b10_001_0010_0110_010); 1531 /// Address Comparator Access Type Register 11 1532 pub const TRCACATR11: Self = Self::System(0b10_001_0010_0110_011); 1533 /// Address Comparator Value Register 4 1534 pub const TRCACVR4: Self = Self::System(0b10_001_0010_1000_000); 1535 /// Address Comparator Value Register 12 1536 pub const TRCACVR12: Self = Self::System(0b10_001_0010_1000_001); 1537 /// Address Comparator Access Type Register 4 1538 pub const TRCACATR4: Self = Self::System(0b10_001_0010_1000_010); 1539 /// Address Comparator Access Type Register 12 1540 pub const TRCACATR12: Self = Self::System(0b10_001_0010_1000_011); 1541 /// Address Comparator Value Register 5 1542 pub const TRCACVR5: Self = Self::System(0b10_001_0010_1010_000); 1543 /// Address Comparator Value Register 13 1544 pub const TRCACVR13: Self = Self::System(0b10_001_0010_1010_001); 1545 /// Address Comparator Access Type Register 5 1546 pub const TRCACATR5: Self = Self::System(0b10_001_0010_1010_010); 1547 /// Address Comparator Access Type Register 13 1548 pub const TRCACATR13: Self = Self::System(0b10_001_0010_1010_011); 1549 /// Address Comparator Value Register 6 1550 pub const TRCACVR6: Self = Self::System(0b10_001_0010_1100_000); 1551 /// Address Comparator Value Register 14 1552 pub const TRCACVR14: Self = Self::System(0b10_001_0010_1100_001); 1553 /// Address Comparator Access Type Register 6 1554 pub const TRCACATR6: Self = Self::System(0b10_001_0010_1100_010); 1555 /// Address Comparator Access Type Register 14 1556 pub const TRCACATR14: Self = Self::System(0b10_001_0010_1100_011); 1557 /// Address Comparator Value Register 7 1558 pub const TRCACVR7: Self = Self::System(0b10_001_0010_1110_000); 1559 /// Address Comparator Value Register 15 1560 pub const TRCACVR15: Self = Self::System(0b10_001_0010_1110_001); 1561 /// Address Comparator Access Type Register 7 1562 pub const TRCACATR7: Self = Self::System(0b10_001_0010_1110_010); 1563 /// Address Comparator Access Type Register 15 1564 pub const TRCACATR15: Self = Self::System(0b10_001_0010_1110_011); 1565 /// Context Identifier Comparator Value Registers 0 1566 pub const TRCCIDCVR0: Self = Self::System(0b10_001_0011_0000_000); 1567 /// Virtual Context Identifier Comparator Value Register 0 1568 pub const TRCVMIDCVR0: Self = Self::System(0b10_001_0011_0000_001); 1569 /// Context Identifier Comparator Control Register 0 1570 pub const TRCCIDCCTLR0: Self = Self::System(0b10_001_0011_0000_010); 1571 /// Context Identifier Comparator Control Register 1 1572 pub const TRCCIDCCTLR1: Self = Self::System(0b10_001_0011_0001_010); 1573 /// Context Identifier Comparator Value Registers 1 1574 pub const TRCCIDCVR1: Self = Self::System(0b10_001_0011_0010_000); 1575 /// Virtual Context Identifier Comparator Value Register 1 1576 pub const TRCVMIDCVR1: Self = Self::System(0b10_001_0011_0010_001); 1577 /// Virtual Context Identifier Comparator Control Register 0 1578 pub const TRCVMIDCCTLR0: Self = Self::System(0b10_001_0011_0010_010); 1579 /// Virtual Context Identifier Comparator Control Register 1 1580 pub const TRCVMIDCCTLR1: Self = Self::System(0b10_001_0011_0011_010); 1581 /// Context Identifier Comparator Value Registers 2 1582 pub const TRCCIDCVR2: Self = Self::System(0b10_001_0011_0100_000); 1583 /// Virtual Context Identifier Comparator Value Register 2 1584 pub const TRCVMIDCVR2: Self = Self::System(0b10_001_0011_0100_001); 1585 /// Context Identifier Comparator Value Registers 3 1586 pub const TRCCIDCVR3: Self = Self::System(0b10_001_0011_0110_000); 1587 /// Virtual Context Identifier Comparator Value Register 3 1588 pub const TRCVMIDCVR3: Self = Self::System(0b10_001_0011_0110_001); 1589 /// Context Identifier Comparator Value Registers 4 1590 pub const TRCCIDCVR4: Self = Self::System(0b10_001_0011_1000_000); 1591 /// Virtual Context Identifier Comparator Value Register 4 1592 pub const TRCVMIDCVR4: Self = Self::System(0b10_001_0011_1000_001); 1593 /// Context Identifier Comparator Value Registers 5 1594 pub const TRCCIDCVR5: Self = Self::System(0b10_001_0011_1010_000); 1595 /// Virtual Context Identifier Comparator Value Register 5 1596 pub const TRCVMIDCVR5: Self = Self::System(0b10_001_0011_1010_001); 1597 /// Context Identifier Comparator Value Registers 6 1598 pub const TRCCIDCVR6: Self = Self::System(0b10_001_0011_1100_000); 1599 /// Virtual Context Identifier Comparator Value Register 6 1600 pub const TRCVMIDCVR6: Self = Self::System(0b10_001_0011_1100_001); 1601 /// Context Identifier Comparator Value Registers 7 1602 pub const TRCCIDCVR7: Self = Self::System(0b10_001_0011_1110_000); 1603 /// Virtual Context Identifier Comparator Value Register 7 1604 pub const TRCVMIDCVR7: Self = Self::System(0b10_001_0011_1110_001); 1605 /// Device Configuration Register 1606 pub const TRCDEVID: Self = Self::System(0b10_001_0111_0010_111); 1607 /// Claim Tag Set Register 1608 pub const TRCCLAIMSET: Self = Self::System(0b10_001_0111_1000_110); 1609 /// Claim Tag Clear Register 1610 pub const TRCCLAIMCLR: Self = Self::System(0b10_001_0111_1001_110); 1611 /// Authentication Status Register 1612 pub const TRCAUTHSTATUS: Self = Self::System(0b10_001_0111_1110_110); 1613 /// Device Architecture Register 1614 pub const TRCDEVARCH: Self = Self::System(0b10_001_0111_1111_110); 1615 /// Branch Record Buffer Information Register 0 1616 pub const BRBINF0_EL1: Self = Self::System(0b10_001_1000_0000_000); 1617 /// Branch Record Buffer Source Address Register 0 1618 pub const BRBSRC0_EL1: Self = Self::System(0b10_001_1000_0000_001); 1619 /// Branch Record Buffer Target Address Register 0 1620 pub const BRBTGT0_EL1: Self = Self::System(0b10_001_1000_0000_010); 1621 /// Branch Record Buffer Information Register 16 1622 pub const BRBINF16_EL1: Self = Self::System(0b10_001_1000_0000_100); 1623 /// Branch Record Buffer Source Address Register 16 1624 pub const BRBSRC16_EL1: Self = Self::System(0b10_001_1000_0000_101); 1625 /// Branch Record Buffer Target Address Register 16 1626 pub const BRBTGT16_EL1: Self = Self::System(0b10_001_1000_0000_110); 1627 /// Branch Record Buffer Information Register 1 1628 pub const BRBINF1_EL1: Self = Self::System(0b10_001_1000_0001_000); 1629 /// Branch Record Buffer Source Address Register 1 1630 pub const BRBSRC1_EL1: Self = Self::System(0b10_001_1000_0001_001); 1631 /// Branch Record Buffer Target Address Register 1 1632 pub const BRBTGT1_EL1: Self = Self::System(0b10_001_1000_0001_010); 1633 /// Branch Record Buffer Information Register 17 1634 pub const BRBINF17_EL1: Self = Self::System(0b10_001_1000_0001_100); 1635 /// Branch Record Buffer Source Address Register 17 1636 pub const BRBSRC17_EL1: Self = Self::System(0b10_001_1000_0001_101); 1637 /// Branch Record Buffer Target Address Register 17 1638 pub const BRBTGT17_EL1: Self = Self::System(0b10_001_1000_0001_110); 1639 /// Branch Record Buffer Information Register 2 1640 pub const BRBINF2_EL1: Self = Self::System(0b10_001_1000_0010_000); 1641 /// Branch Record Buffer Source Address Register 2 1642 pub const BRBSRC2_EL1: Self = Self::System(0b10_001_1000_0010_001); 1643 /// Branch Record Buffer Target Address Register 2 1644 pub const BRBTGT2_EL1: Self = Self::System(0b10_001_1000_0010_010); 1645 /// Branch Record Buffer Information Register 18 1646 pub const BRBINF18_EL1: Self = Self::System(0b10_001_1000_0010_100); 1647 /// Branch Record Buffer Source Address Register 18 1648 pub const BRBSRC18_EL1: Self = Self::System(0b10_001_1000_0010_101); 1649 /// Branch Record Buffer Target Address Register 18 1650 pub const BRBTGT18_EL1: Self = Self::System(0b10_001_1000_0010_110); 1651 /// Branch Record Buffer Information Register 3 1652 pub const BRBINF3_EL1: Self = Self::System(0b10_001_1000_0011_000); 1653 /// Branch Record Buffer Source Address Register 3 1654 pub const BRBSRC3_EL1: Self = Self::System(0b10_001_1000_0011_001); 1655 /// Branch Record Buffer Target Address Register 3 1656 pub const BRBTGT3_EL1: Self = Self::System(0b10_001_1000_0011_010); 1657 /// Branch Record Buffer Information Register 19 1658 pub const BRBINF19_EL1: Self = Self::System(0b10_001_1000_0011_100); 1659 /// Branch Record Buffer Source Address Register 19 1660 pub const BRBSRC19_EL1: Self = Self::System(0b10_001_1000_0011_101); 1661 /// Branch Record Buffer Target Address Register 19 1662 pub const BRBTGT19_EL1: Self = Self::System(0b10_001_1000_0011_110); 1663 /// Branch Record Buffer Information Register 4 1664 pub const BRBINF4_EL1: Self = Self::System(0b10_001_1000_0100_000); 1665 /// Branch Record Buffer Source Address Register 4 1666 pub const BRBSRC4_EL1: Self = Self::System(0b10_001_1000_0100_001); 1667 /// Branch Record Buffer Target Address Register 4 1668 pub const BRBTGT4_EL1: Self = Self::System(0b10_001_1000_0100_010); 1669 /// Branch Record Buffer Information Register 20 1670 pub const BRBINF20_EL1: Self = Self::System(0b10_001_1000_0100_100); 1671 /// Branch Record Buffer Source Address Register 20 1672 pub const BRBSRC20_EL1: Self = Self::System(0b10_001_1000_0100_101); 1673 /// Branch Record Buffer Target Address Register 20 1674 pub const BRBTGT20_EL1: Self = Self::System(0b10_001_1000_0100_110); 1675 /// Branch Record Buffer Information Register 5 1676 pub const BRBINF5_EL1: Self = Self::System(0b10_001_1000_0101_000); 1677 /// Branch Record Buffer Source Address Register 5 1678 pub const BRBSRC5_EL1: Self = Self::System(0b10_001_1000_0101_001); 1679 /// Branch Record Buffer Target Address Register 5 1680 pub const BRBTGT5_EL1: Self = Self::System(0b10_001_1000_0101_010); 1681 /// Branch Record Buffer Information Register 21 1682 pub const BRBINF21_EL1: Self = Self::System(0b10_001_1000_0101_100); 1683 /// Branch Record Buffer Source Address Register 21 1684 pub const BRBSRC21_EL1: Self = Self::System(0b10_001_1000_0101_101); 1685 /// Branch Record Buffer Target Address Register 21 1686 pub const BRBTGT21_EL1: Self = Self::System(0b10_001_1000_0101_110); 1687 /// Branch Record Buffer Information Register 6 1688 pub const BRBINF6_EL1: Self = Self::System(0b10_001_1000_0110_000); 1689 /// Branch Record Buffer Source Address Register 6 1690 pub const BRBSRC6_EL1: Self = Self::System(0b10_001_1000_0110_001); 1691 /// Branch Record Buffer Target Address Register 6 1692 pub const BRBTGT6_EL1: Self = Self::System(0b10_001_1000_0110_010); 1693 /// Branch Record Buffer Information Register 22 1694 pub const BRBINF22_EL1: Self = Self::System(0b10_001_1000_0110_100); 1695 /// Branch Record Buffer Source Address Register 22 1696 pub const BRBSRC22_EL1: Self = Self::System(0b10_001_1000_0110_101); 1697 /// Branch Record Buffer Target Address Register 22 1698 pub const BRBTGT22_EL1: Self = Self::System(0b10_001_1000_0110_110); 1699 /// Branch Record Buffer Information Register 7 1700 pub const BRBINF7_EL1: Self = Self::System(0b10_001_1000_0111_000); 1701 /// Branch Record Buffer Source Address Register 7 1702 pub const BRBSRC7_EL1: Self = Self::System(0b10_001_1000_0111_001); 1703 /// Branch Record Buffer Target Address Register 7 1704 pub const BRBTGT7_EL1: Self = Self::System(0b10_001_1000_0111_010); 1705 /// Branch Record Buffer Information Register 23 1706 pub const BRBINF23_EL1: Self = Self::System(0b10_001_1000_0111_100); 1707 /// Branch Record Buffer Source Address Register 23 1708 pub const BRBSRC23_EL1: Self = Self::System(0b10_001_1000_0111_101); 1709 /// Branch Record Buffer Target Address Register 23 1710 pub const BRBTGT23_EL1: Self = Self::System(0b10_001_1000_0111_110); 1711 /// Branch Record Buffer Information Register 8 1712 pub const BRBINF8_EL1: Self = Self::System(0b10_001_1000_1000_000); 1713 /// Branch Record Buffer Source Address Register 8 1714 pub const BRBSRC8_EL1: Self = Self::System(0b10_001_1000_1000_001); 1715 /// Branch Record Buffer Target Address Register 8 1716 pub const BRBTGT8_EL1: Self = Self::System(0b10_001_1000_1000_010); 1717 /// Branch Record Buffer Information Register 24 1718 pub const BRBINF24_EL1: Self = Self::System(0b10_001_1000_1000_100); 1719 /// Branch Record Buffer Source Address Register 24 1720 pub const BRBSRC24_EL1: Self = Self::System(0b10_001_1000_1000_101); 1721 /// Branch Record Buffer Target Address Register 24 1722 pub const BRBTGT24_EL1: Self = Self::System(0b10_001_1000_1000_110); 1723 /// Branch Record Buffer Information Register 9 1724 pub const BRBINF9_EL1: Self = Self::System(0b10_001_1000_1001_000); 1725 /// Branch Record Buffer Source Address Register 9 1726 pub const BRBSRC9_EL1: Self = Self::System(0b10_001_1000_1001_001); 1727 /// Branch Record Buffer Target Address Register 9 1728 pub const BRBTGT9_EL1: Self = Self::System(0b10_001_1000_1001_010); 1729 /// Branch Record Buffer Information Register 25 1730 pub const BRBINF25_EL1: Self = Self::System(0b10_001_1000_1001_100); 1731 /// Branch Record Buffer Source Address Register 25 1732 pub const BRBSRC25_EL1: Self = Self::System(0b10_001_1000_1001_101); 1733 /// Branch Record Buffer Target Address Register 25 1734 pub const BRBTGT25_EL1: Self = Self::System(0b10_001_1000_1001_110); 1735 /// Branch Record Buffer Information Register 10 1736 pub const BRBINF10_EL1: Self = Self::System(0b10_001_1000_1010_000); 1737 /// Branch Record Buffer Source Address Register 10 1738 pub const BRBSRC10_EL1: Self = Self::System(0b10_001_1000_1010_001); 1739 /// Branch Record Buffer Target Address Register 10 1740 pub const BRBTGT10_EL1: Self = Self::System(0b10_001_1000_1010_010); 1741 /// Branch Record Buffer Information Register 26 1742 pub const BRBINF26_EL1: Self = Self::System(0b10_001_1000_1010_100); 1743 /// Branch Record Buffer Source Address Register 26 1744 pub const BRBSRC26_EL1: Self = Self::System(0b10_001_1000_1010_101); 1745 /// Branch Record Buffer Target Address Register 26 1746 pub const BRBTGT26_EL1: Self = Self::System(0b10_001_1000_1010_110); 1747 /// Branch Record Buffer Information Register 11 1748 pub const BRBINF11_EL1: Self = Self::System(0b10_001_1000_1011_000); 1749 /// Branch Record Buffer Source Address Register 11 1750 pub const BRBSRC11_EL1: Self = Self::System(0b10_001_1000_1011_001); 1751 /// Branch Record Buffer Target Address Register 11 1752 pub const BRBTGT11_EL1: Self = Self::System(0b10_001_1000_1011_010); 1753 /// Branch Record Buffer Information Register 27 1754 pub const BRBINF27_EL1: Self = Self::System(0b10_001_1000_1011_100); 1755 /// Branch Record Buffer Source Address Register 27 1756 pub const BRBSRC27_EL1: Self = Self::System(0b10_001_1000_1011_101); 1757 /// Branch Record Buffer Target Address Register 27 1758 pub const BRBTGT27_EL1: Self = Self::System(0b10_001_1000_1011_110); 1759 /// Branch Record Buffer Information Register 12 1760 pub const BRBINF12_EL1: Self = Self::System(0b10_001_1000_1100_000); 1761 /// Branch Record Buffer Source Address Register 12 1762 pub const BRBSRC12_EL1: Self = Self::System(0b10_001_1000_1100_001); 1763 /// Branch Record Buffer Target Address Register 12 1764 pub const BRBTGT12_EL1: Self = Self::System(0b10_001_1000_1100_010); 1765 /// Branch Record Buffer Information Register 28 1766 pub const BRBINF28_EL1: Self = Self::System(0b10_001_1000_1100_100); 1767 /// Branch Record Buffer Source Address Register 28 1768 pub const BRBSRC28_EL1: Self = Self::System(0b10_001_1000_1100_101); 1769 /// Branch Record Buffer Target Address Register 28 1770 pub const BRBTGT28_EL1: Self = Self::System(0b10_001_1000_1100_110); 1771 /// Branch Record Buffer Information Register 13 1772 pub const BRBINF13_EL1: Self = Self::System(0b10_001_1000_1101_000); 1773 /// Branch Record Buffer Source Address Register 13 1774 pub const BRBSRC13_EL1: Self = Self::System(0b10_001_1000_1101_001); 1775 /// Branch Record Buffer Target Address Register 13 1776 pub const BRBTGT13_EL1: Self = Self::System(0b10_001_1000_1101_010); 1777 /// Branch Record Buffer Information Register 29 1778 pub const BRBINF29_EL1: Self = Self::System(0b10_001_1000_1101_100); 1779 /// Branch Record Buffer Source Address Register 29 1780 pub const BRBSRC29_EL1: Self = Self::System(0b10_001_1000_1101_101); 1781 /// Branch Record Buffer Target Address Register 29 1782 pub const BRBTGT29_EL1: Self = Self::System(0b10_001_1000_1101_110); 1783 /// Branch Record Buffer Information Register 14 1784 pub const BRBINF14_EL1: Self = Self::System(0b10_001_1000_1110_000); 1785 /// Branch Record Buffer Source Address Register 14 1786 pub const BRBSRC14_EL1: Self = Self::System(0b10_001_1000_1110_001); 1787 /// Branch Record Buffer Target Address Register 14 1788 pub const BRBTGT14_EL1: Self = Self::System(0b10_001_1000_1110_010); 1789 /// Branch Record Buffer Information Register 30 1790 pub const BRBINF30_EL1: Self = Self::System(0b10_001_1000_1110_100); 1791 /// Branch Record Buffer Source Address Register 30 1792 pub const BRBSRC30_EL1: Self = Self::System(0b10_001_1000_1110_101); 1793 /// Branch Record Buffer Target Address Register 30 1794 pub const BRBTGT30_EL1: Self = Self::System(0b10_001_1000_1110_110); 1795 /// Branch Record Buffer Information Register 15 1796 pub const BRBINF15_EL1: Self = Self::System(0b10_001_1000_1111_000); 1797 /// Branch Record Buffer Source Address Register 15 1798 pub const BRBSRC15_EL1: Self = Self::System(0b10_001_1000_1111_001); 1799 /// Branch Record Buffer Target Address Register 15 1800 pub const BRBTGT15_EL1: Self = Self::System(0b10_001_1000_1111_010); 1801 /// Branch Record Buffer Information Register 31 1802 pub const BRBINF31_EL1: Self = Self::System(0b10_001_1000_1111_100); 1803 /// Branch Record Buffer Source Address Register 31 1804 pub const BRBSRC31_EL1: Self = Self::System(0b10_001_1000_1111_101); 1805 /// Branch Record Buffer Target Address Register 31 1806 pub const BRBTGT31_EL1: Self = Self::System(0b10_001_1000_1111_110); 1807 /// Branch Record Buffer Control Register (EL1) 1808 pub const BRBCR_EL1: Self = Self::System(0b10_001_1001_0000_000); 1809 /// Branch Record Buffer Control Register (EL2) 1810 pub const BRBCR_EL2: Self = Self::System(0b10_001_1001_0000_000); 1811 /// Branch Record Buffer Function Control Register 1812 pub const BRBFCR_EL1: Self = Self::System(0b10_001_1001_0000_001); 1813 /// Branch Record Buffer Timestamp Register 1814 pub const BRBTS_EL1: Self = Self::System(0b10_001_1001_0000_010); 1815 /// Branch Record Buffer Information Injection Register 1816 pub const BRBINFINJ_EL1: Self = Self::System(0b10_001_1001_0001_000); 1817 /// Branch Record Buffer Source Address Injection Register 1818 pub const BRBSRCINJ_EL1: Self = Self::System(0b10_001_1001_0001_001); 1819 /// Branch Record Buffer Target Address Injection Register 1820 pub const BRBTGTINJ_EL1: Self = Self::System(0b10_001_1001_0001_010); 1821 /// Branch Record Buffer ID0 Register 1822 pub const BRBIDR0_EL1: Self = Self::System(0b10_001_1001_0010_000); 1823 /// Monitor DCC Status Register 1824 pub const MDCCSR_EL0: Self = Self::System(0b10_011_0000_0001_000); 1825 /// Debug Data Transfer Register, Half-duplex 1826 pub const DBGDTR_EL0: Self = Self::System(0b10_011_0000_0100_000); 1827 /// Debug Data Transfer Register, Receive 1828 pub const DBGDTRRX_EL0: Self = Self::System(0b10_011_0000_0101_000); 1829 /// Debug Data Transfer Register, Transmit 1830 pub const DBGDTRTX_EL0: Self = Self::System(0b10_011_0000_0101_000); 1831 /// Debug Vector Catch Register 1832 pub const DBGVCR32_EL2: Self = Self::System(0b10_100_0000_0111_000); 1833 } 1834